Skip to content

Commit 46fc93b

Browse files
s-barannikovs-barannikov
committed
[AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
1 parent ed950c3 commit 46fc93b

File tree

6 files changed

+106
-51
lines changed

6 files changed

+106
-51
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1559,13 +1559,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
15591559
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
15601560
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
15611561

1562-
let OperandNamespace = "AArch64" in {
1563-
let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
1564-
defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
1565-
[{ return ((uint64_t)Imm) == 0; }]>;
1566-
defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand,
1567-
[{ return ((uint32_t)Imm) == 0; }]>;
1568-
}
1562+
let DecoderMethod = "DecodeZeroImm" in {
1563+
defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
1564+
[{ return ((uint64_t)Imm) == 0; }]>;
1565+
defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand,
1566+
[{ return ((uint32_t)Imm) == 0; }]>;
15691567
}
15701568
defm VectorIndex1 : VectorIndex<i64, VectorIndex1Operand,
15711569
[{ return ((uint64_t)Imm) == 1; }]>;
@@ -1615,9 +1613,8 @@ def sme_elm_idx0_0 : Operand<i32>, TImmLeaf<i32, [{
16151613
return ((uint32_t)Imm) == 0;
16161614
}]> {
16171615
let ParserMatchClass = Imm0_0Operand;
1616+
let DecoderMethod = "DecodeZeroImm";
16181617
let PrintMethod = "printMatrixIndex";
1619-
let OperandNamespace = "AArch64";
1620-
let OperandType = "OPERAND_IMPLICIT_IMM_0";
16211618
}
16221619
def sme_elm_idx0_1 : Operand<i32>, TImmLeaf<i32, [{
16231620
return ((uint32_t)Imm) <= 1;
@@ -1677,18 +1674,16 @@ def UImm3s2RangeOperand : UImmScaledMemoryIndexedRange<3, 2, 1>;
16771674

16781675
def uimm0s2range : Operand<i64>, ImmLeaf<i64,
16791676
[{ return Imm == 0; }], UImmS1XForm> {
1677+
let DecoderMethod = "DecodeZeroImm";
16801678
let PrintMethod = "printImmRangeScale<2, 1>";
16811679
let ParserMatchClass = UImm0s2RangeOperand;
1682-
let OperandNamespace = "AArch64";
1683-
let OperandType = "OPERAND_IMPLICIT_IMM_0";
16841680
}
16851681

16861682
def uimm0s4range : Operand<i64>, ImmLeaf<i64,
16871683
[{ return Imm == 0; }], UImmS1XForm> {
1684+
let DecoderMethod = "DecodeZeroImm";
16881685
let PrintMethod = "printImmRangeScale<4, 3>";
16891686
let ParserMatchClass = UImm0s4RangeOperand;
1690-
let OperandNamespace = "AArch64";
1691-
let OperandType = "OPERAND_IMPLICIT_IMM_0";
16921687
}
16931688

16941689
def uimm1s2range : Operand<i64>, ImmLeaf<i64,
@@ -8218,18 +8213,23 @@ multiclass SMov {
82188213
// streaming mode.
82198214
let Predicates = [HasNEONandIsStreamingSafe] in {
82208215
def vi8to32_idx0 : SIMDSMov<0, ".b", GPR32, VectorIndex0> {
8216+
bits<0> idx;
82218217
let Inst{20-16} = 0b00001;
82228218
}
82238219
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
8220+
bits<0> idx;
82248221
let Inst{20-16} = 0b00001;
82258222
}
82268223
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
8224+
bits<0> idx;
82278225
let Inst{20-16} = 0b00010;
82288226
}
82298227
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
8228+
bits<0> idx;
82308229
let Inst{20-16} = 0b00010;
82318230
}
82328231
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
8232+
bits<0> idx;
82338233
let Inst{20-16} = 0b00100;
82348234
}
82358235
}
@@ -8265,15 +8265,19 @@ multiclass UMov {
82658265
// streaming mode.
82668266
let Predicates = [HasNEONandIsStreamingSafe] in {
82678267
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
8268+
bits<0> idx;
82688269
let Inst{20-16} = 0b00001;
82698270
}
82708271
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
8272+
bits<0> idx;
82718273
let Inst{20-16} = 0b00010;
82728274
}
82738275
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
8276+
bits<0> idx;
82748277
let Inst{20-16} = 0b00100;
82758278
}
82768279
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
8280+
bits<0> idx;
82778281
let Inst{20-16} = 0b01000;
82788282
}
82798283
def : SIMDMovAlias<"mov", ".s",

‎llvm/lib/Target/AArch64/CMakeLists.txt‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
88
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
99
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
10-
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
11-
-ignore-non-decodable-operands)
10+
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
1211
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
1312
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
1413
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
130130
return Success;
131131
}
132132

133+
static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst,
134+
const MCDisassembler *Decoder) {
135+
Inst.addOperand(MCOperand::createReg(AArch64::ZA));
136+
return Success;
137+
}
138+
139+
static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst,
140+
const MCDisassembler *Decoder) {
141+
Inst.addOperand(MCOperand::createReg(AArch64::ZT0));
142+
return Success;
143+
}
144+
133145
static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
134146
{AArch64::ZAB0},
135147
{AArch64::ZAH0, AArch64::ZAH1},
@@ -141,10 +153,19 @@ static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
141153
AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
142154
AArch64::ZAQ14, AArch64::ZAQ15}};
143155

156+
template <unsigned NumBitsForTile>
157+
static DecodeStatus DecodeMatrixTile(MCInst &Inst,
158+
const MCDisassembler *Decoder) {
159+
static_assert(NumBitsForTile == 0);
160+
Inst.addOperand(MCOperand::createReg(AArch64::ZAB0));
161+
return Success;
162+
}
163+
144164
template <unsigned NumBitsForTile>
145165
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
146166
uint64_t Address,
147167
const MCDisassembler *Decoder) {
168+
static_assert(NumBitsForTile != 0);
148169
unsigned LastReg = (1 << NumBitsForTile) - 1;
149170
if (RegNo > LastReg)
150171
return Fail;
@@ -1422,6 +1443,11 @@ DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
14221443
return Success;
14231444
}
14241445

1446+
static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder) {
1447+
Inst.addOperand(MCOperand::createImm(0));
1448+
return Success;
1449+
}
1450+
14251451
template <int Bits>
14261452
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
14271453
const MCDisassembler *Decoder) {
@@ -1570,6 +1596,7 @@ DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
15701596
unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
15711597
unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
15721598

1599+
DecodeMPRRegisterClass(Inst, Decoder);
15731600
DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>(
15741601
Inst, RvBits, Addr, Decoder);
15751602
Inst.addOperand(MCOperand::createImm(Imm4Bits));
@@ -1613,33 +1640,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
16131640
for (const auto *Table : Tables) {
16141641
DecodeStatus Result =
16151642
decodeInstruction(Table, MI, Insn, Address, this, STI);
1616-
1617-
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1618-
1619-
// For Scalable Matrix Extension (SME) instructions that have an implicit
1620-
// operand for the accumulator (ZA) or implicit immediate zero which isn't
1621-
// encoded, manually insert operand.
1622-
for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
1623-
if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
1624-
switch (Desc.operands()[i].RegClass) {
1625-
default:
1626-
break;
1627-
case AArch64::MPRRegClassID:
1628-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
1629-
break;
1630-
case AArch64::MPR8RegClassID:
1631-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
1632-
break;
1633-
case AArch64::ZTRRegClassID:
1634-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
1635-
break;
1636-
}
1637-
} else if (Desc.operands()[i].OperandType ==
1638-
AArch64::OPERAND_IMPLICIT_IMM_0) {
1639-
MI.insert(MI.begin() + i, MCOperand::createImm(0));
1640-
}
1641-
}
1642-
16431643
if (Result != MCDisassembler::Fail)
16441644
return Result;
16451645
}

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -67,12 +67,6 @@ bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
6767
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
6868
}
6969

70-
namespace AArch64 {
71-
enum OperandType {
72-
OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
73-
};
74-
} // namespace AArch64
75-
7670
} // End llvm namespace
7771

7872
// Defines symbolic names for AArch64 registers. This defines a mapping from

0 commit comments

Comments
 (0)