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[RISCV] Add commutative support for Qualcomm uC Xqcicm extension (#160653)
This is a follow-up to #145643. See #145643 (comment).
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8 files changed

+645
-339
lines changed

8 files changed

+645
-339
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1023,6 +1023,37 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
10231023
Cond.push_back(LastInst.getOperand(1));
10241024
}
10251025

1026+
static unsigned getInverseXqcicmOpcode(unsigned Opcode) {
1027+
switch (Opcode) {
1028+
default:
1029+
llvm_unreachable("Unexpected Opcode");
1030+
case RISCV::QC_MVEQ:
1031+
return RISCV::QC_MVNE;
1032+
case RISCV::QC_MVNE:
1033+
return RISCV::QC_MVEQ;
1034+
case RISCV::QC_MVLT:
1035+
return RISCV::QC_MVGE;
1036+
case RISCV::QC_MVGE:
1037+
return RISCV::QC_MVLT;
1038+
case RISCV::QC_MVLTU:
1039+
return RISCV::QC_MVGEU;
1040+
case RISCV::QC_MVGEU:
1041+
return RISCV::QC_MVLTU;
1042+
case RISCV::QC_MVEQI:
1043+
return RISCV::QC_MVNEI;
1044+
case RISCV::QC_MVNEI:
1045+
return RISCV::QC_MVEQI;
1046+
case RISCV::QC_MVLTI:
1047+
return RISCV::QC_MVGEI;
1048+
case RISCV::QC_MVGEI:
1049+
return RISCV::QC_MVLTI;
1050+
case RISCV::QC_MVLTUI:
1051+
return RISCV::QC_MVGEUI;
1052+
case RISCV::QC_MVGEUI:
1053+
return RISCV::QC_MVLTUI;
1054+
}
1055+
}
1056+
10261057
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
10271058
switch (SelectOpc) {
10281059
default:
@@ -3762,6 +3793,19 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
37623793
return false;
37633794
// Operands 1 and 2 are commutable, if we switch the opcode.
37643795
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3796+
case RISCV::QC_MVEQ:
3797+
case RISCV::QC_MVNE:
3798+
case RISCV::QC_MVLT:
3799+
case RISCV::QC_MVGE:
3800+
case RISCV::QC_MVLTU:
3801+
case RISCV::QC_MVGEU:
3802+
case RISCV::QC_MVEQI:
3803+
case RISCV::QC_MVNEI:
3804+
case RISCV::QC_MVLTI:
3805+
case RISCV::QC_MVGEI:
3806+
case RISCV::QC_MVLTUI:
3807+
case RISCV::QC_MVGEUI:
3808+
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 4);
37653809
case RISCV::TH_MULA:
37663810
case RISCV::TH_MULAW:
37673811
case RISCV::TH_MULAH:
@@ -3974,6 +4018,23 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
39744018
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
39754019
OpIdx2);
39764020
}
4021+
case RISCV::QC_MVEQ:
4022+
case RISCV::QC_MVNE:
4023+
case RISCV::QC_MVLT:
4024+
case RISCV::QC_MVGE:
4025+
case RISCV::QC_MVLTU:
4026+
case RISCV::QC_MVGEU:
4027+
case RISCV::QC_MVEQI:
4028+
case RISCV::QC_MVNEI:
4029+
case RISCV::QC_MVLTI:
4030+
case RISCV::QC_MVGEI:
4031+
case RISCV::QC_MVLTUI:
4032+
case RISCV::QC_MVGEUI: {
4033+
auto &WorkingMI = cloneIfNew(MI);
4034+
WorkingMI.setDesc(get(getInverseXqcicmOpcode(MI.getOpcode())));
4035+
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
4036+
OpIdx2);
4037+
}
39774038
case RISCV::PseudoCCMOVGPRNoX0:
39784039
case RISCV::PseudoCCMOVGPR: {
39794040
// CCMOV can be commuted by inverting the condition.

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -604,15 +604,15 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes
604604
let Inst{31-25} = {simm, funct2};
605605
}
606606

607-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
607+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
608608
class QCIMVCC<bits<3> funct3, string opcodestr>
609609
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
610610
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
611611
opcodestr, "$rd, $rs1, $rs2, $rs3"> {
612612
let Constraints = "$rd = $rd_wb";
613613
}
614614

615-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
615+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
616616
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
617617
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
618618
(ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),

‎llvm/test/CodeGen/RISCV/select-bare.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,8 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
2626
; RV32IXQCI-LABEL: bare_select:
2727
; RV32IXQCI: # %bb.0:
2828
; RV32IXQCI-NEXT: andi a0, a0, 1
29-
; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
30-
; RV32IXQCI-NEXT: mv a0, a2
29+
; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
30+
; RV32IXQCI-NEXT: mv a0, a1
3131
; RV32IXQCI-NEXT: ret
3232
%1 = select i1 %a, i32 %b, i32 %c
3333
ret i32 %1
@@ -53,8 +53,8 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
5353
; RV32IXQCI-LABEL: bare_select_float:
5454
; RV32IXQCI: # %bb.0:
5555
; RV32IXQCI-NEXT: andi a0, a0, 1
56-
; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
57-
; RV32IXQCI-NEXT: mv a0, a2
56+
; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
57+
; RV32IXQCI-NEXT: mv a0, a1
5858
; RV32IXQCI-NEXT: ret
5959
%1 = select i1 %a, float %b, float %c
6060
ret float %1

‎llvm/test/CodeGen/RISCV/select-cc.ll‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -87,40 +87,40 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
8787
;
8888
; RV32IXQCI-LABEL: foo:
8989
; RV32IXQCI: # %bb.0:
90-
; RV32IXQCI-NEXT: lw a5, 0(a1)
9190
; RV32IXQCI-NEXT: lw a2, 0(a1)
9291
; RV32IXQCI-NEXT: lw a4, 0(a1)
9392
; RV32IXQCI-NEXT: lw t5, 0(a1)
9493
; RV32IXQCI-NEXT: lw t4, 0(a1)
94+
; RV32IXQCI-NEXT: lw t3, 0(a1)
9595
; RV32IXQCI-NEXT: lw t2, 0(a1)
96-
; RV32IXQCI-NEXT: lw t1, 0(a1)
9796
; RV32IXQCI-NEXT: lw t0, 0(a1)
9897
; RV32IXQCI-NEXT: lw a7, 0(a1)
9998
; RV32IXQCI-NEXT: lw a6, 0(a1)
100-
; RV32IXQCI-NEXT: lw t3, 0(a1)
10199
; RV32IXQCI-NEXT: lw a3, 0(a1)
102-
; RV32IXQCI-NEXT: bltz t3, .LBB0_2
100+
; RV32IXQCI-NEXT: lw t1, 0(a1)
101+
; RV32IXQCI-NEXT: lw a5, 0(a1)
102+
; RV32IXQCI-NEXT: bltz t1, .LBB0_2
103103
; RV32IXQCI-NEXT: # %bb.1:
104-
; RV32IXQCI-NEXT: li t6, 0
105-
; RV32IXQCI-NEXT: qc.mveq a5, a0, a5, a0
106-
; RV32IXQCI-NEXT: qc.mvne a2, a5, a2, a5
107-
; RV32IXQCI-NEXT: qc.mvltu a4, a4, a2, a2
108-
; RV32IXQCI-NEXT: qc.mvgeu t5, a4, t5, a4
109-
; RV32IXQCI-NEXT: qc.mvltu t4, t5, t4, t5
110-
; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t4, t4
111-
; RV32IXQCI-NEXT: qc.mvlt t1, t1, t2, t2
112-
; RV32IXQCI-NEXT: qc.mvge t0, t1, t0, t1
113-
; RV32IXQCI-NEXT: qc.mvlt a7, t0, a7, t0
114-
; RV32IXQCI-NEXT: qc.mvge a6, a6, a7, a7
115-
; RV32IXQCI-NEXT: mv a3, t3
116-
; RV32IXQCI-NEXT: qc.mvge a3, t6, t3, a6
104+
; RV32IXQCI-NEXT: li a5, 0
105+
; RV32IXQCI-NEXT: qc.mveq a2, a0, a2, a0
106+
; RV32IXQCI-NEXT: qc.mvne a4, a2, a4, a2
107+
; RV32IXQCI-NEXT: qc.mvltu t5, t5, a4, a4
108+
; RV32IXQCI-NEXT: qc.mvgeu t4, t5, t4, t5
109+
; RV32IXQCI-NEXT: qc.mvltu t3, t4, t3, t4
110+
; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t3, t3
111+
; RV32IXQCI-NEXT: qc.mvlt t0, t0, t2, t2
112+
; RV32IXQCI-NEXT: qc.mvge a7, t0, a7, t0
113+
; RV32IXQCI-NEXT: qc.mvlt a6, a7, a6, a7
114+
; RV32IXQCI-NEXT: qc.mvge a3, a3, a6, a6
115+
; RV32IXQCI-NEXT: qc.mvlt a3, a5, t1, t1
116+
; RV32IXQCI-NEXT: mv a5, a3
117117
; RV32IXQCI-NEXT: .LBB0_2:
118118
; RV32IXQCI-NEXT: lw a2, 0(a1)
119119
; RV32IXQCI-NEXT: lw a0, 0(a1)
120120
; RV32IXQCI-NEXT: li a1, 1024
121-
; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a3
121+
; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a5
122122
; RV32IXQCI-NEXT: li a1, 2046
123-
; RV32IXQCI-NEXT: qc.mvltu a0, a1, t3, a2
123+
; RV32IXQCI-NEXT: qc.mvltu a0, a1, t1, a2
124124
; RV32IXQCI-NEXT: ret
125125
;
126126
; RV64I-LABEL: foo:
@@ -417,8 +417,8 @@ define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z)
417417
; RV32IXQCI: # %bb.0:
418418
; RV32IXQCI-NEXT: lui a3, 1048560
419419
; RV32IXQCI-NEXT: addi a3, a3, -1
420-
; RV32IXQCI-NEXT: qc.mvlt a2, a3, a0, a1
421-
; RV32IXQCI-NEXT: mv a0, a2
420+
; RV32IXQCI-NEXT: qc.mvge a1, a3, a0, a2
421+
; RV32IXQCI-NEXT: mv a0, a1
422422
; RV32IXQCI-NEXT: ret
423423
;
424424
; RV64I-LABEL: select_sge_int16min:
@@ -471,10 +471,10 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
471471
; RV32IXQCI-NEXT: srli a0, a1, 31
472472
; RV32IXQCI-NEXT: xori a0, a0, 1
473473
; RV32IXQCI-NEXT: qc.mveqi a0, a1, -1, a6
474-
; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a2
475-
; RV32IXQCI-NEXT: qc.mvnei a5, a0, 0, a3
476-
; RV32IXQCI-NEXT: mv a0, a4
477-
; RV32IXQCI-NEXT: mv a1, a5
474+
; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4
475+
; RV32IXQCI-NEXT: qc.mveqi a3, a0, 0, a5
476+
; RV32IXQCI-NEXT: mv a0, a2
477+
; RV32IXQCI-NEXT: mv a1, a3
478478
; RV32IXQCI-NEXT: ret
479479
;
480480
; RV64I-LABEL: select_sge_int32min:

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