SPV_INTEL_long_composites is not completed: mark test cases as XFAIL

Author: VyacheslavLevytskyy

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -221,11 +221,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
   bool selectWaveReduceSum(Register ResVReg, const SPIRVType *ResType,
                            MachineInstr &I) const;
 
-  //void renderImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
-  //                 int OpIdx) const;
-  //void renderFImm64(MachineInstrBuilder &MIB, const MachineInstr &I,
-  //                  int OpIdx) const;
-
   bool selectConst(Register ResVReg, const SPIRVType *ResType,
                    MachineInstr &I) const;
 
@@ -2464,24 +2459,7 @@ bool SPIRVInstructionSelector::selectICmp(Register ResVReg,
     CmpOpc = getICmpOpcode(Pred);
   return selectCmp(ResVReg, ResType, CmpOpc, I);
 }
-/*
-void SPIRVInstructionSelector::renderFImm64(MachineInstrBuilder &MIB,
-                                            const MachineInstr &I,
-                                            int OpIdx) const {
-  assert(I.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 &&
-         "Expected G_FCONSTANT");
-  const ConstantFP *FPImm = I.getOperand(1).getFPImm();
-  addNumImm(FPImm->getValueAPF().bitcastToAPInt(), MIB);
-}
 
-void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB,
-                                           const MachineInstr &I,
-                                           int OpIdx) const {
-  assert(I.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
-         "Expected G_CONSTANT");
-  addNumImm(I.getOperand(1).getCImm()->getValue(), MIB);
-}
-*/
 std::pair<Register, bool>
 SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I,
                                            const SPIRVType *ResType) const {

llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

@@ -146,8 +146,6 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
 
   for (auto Opc : getTypeFoldingSupportedOpcodes())
     getActionDefinitionsBuilder(Opc).custom();
-  //getActionDefinitionsBuilder(TargetOpcode::G_CONSTANT).custom();
-  //getActionDefinitionsBuilder(TargetOpcode::G_FCONSTANT).custom();
 
   getActionDefinitionsBuilder(G_GLOBAL_VALUE).alwaysLegal();
 

llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

@@ -396,29 +396,7 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
   if (NewSz != Sz)
     MRI.setType(Reg, LLT::scalar(NewSz));
 }
-/*
-static std::pair<Register, unsigned>
-createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
-               const SPIRVGlobalRegistry &GR) {
-  if (!SpvType)
-    SpvType = GR.getSPIRVTypeForVReg(SrcReg);
-  const TargetRegisterClass *RC = GR.getRegClass(SpvType);
-  Register Reg = MRI.createGenericVirtualRegister(GR.getRegType(SpvType));
-  MRI.setRegClass(Reg, RC);
-  unsigned GetIdOp = SPIRV::GET_ID;
-  if (RC == &SPIRV::fIDRegClass)
-    GetIdOp = SPIRV::GET_fID;
-  else if (RC == &SPIRV::pIDRegClass)
-    GetIdOp = SPIRV::GET_pID;
-  else if (RC == &SPIRV::vfIDRegClass)
-    GetIdOp = SPIRV::GET_vfID;
-  else if (RC == &SPIRV::vpIDRegClass)
-    GetIdOp = SPIRV::GET_vpID;
-  else if (RC == &SPIRV::vIDRegClass)
-    GetIdOp = SPIRV::GET_vID;
-  return {Reg, GetIdOp};
-}
-*/
+
 static void setInsertPtAfterDef(MachineIRBuilder &MIB, MachineInstr *Def) {
   MachineBasicBlock &MBB = *Def->getParent();
   MachineBasicBlock::iterator DefIt =
@@ -502,23 +480,6 @@ void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
       MRI.setType(OpReg, GR->getRegType(SpvType));
   }
 }
-
-/*void processInstr2(MachineInstr &MI, MachineIRBuilder &MIB,
-                  MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR) {
-  MIB.setInsertPt(*MI.getParent(), MI.getIterator());
-  for (auto &Op : MI.operands()) {
-    if (!Op.isReg() || Op.isDef())
-      continue;
-    Register OpReg = Op.getReg();
-    SPIRVType *SpvType = GR->getSPIRVTypeForVReg(OpReg);
-    auto IdOpInfo = createNewIdReg(SpvType, OpReg, MRI, *GR);
-    MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(OpReg);
-    const TargetRegisterClass *RC = GR->getRegClass(SpvType);
-    if (RC != MRI.getRegClassOrNull(OpReg))
-      MRI.setRegClass(OpReg, RC);
-    Op.setReg(IdOpInfo.first);
-  }
-}*/
 } // namespace llvm
 
 static void