Skip to content

Commit 3e1d4d4

Browse files
topperctopperc
authored
[RISCV] Remove Zicntr from sifive-p450/p470/p670. (#161444)
These cores don't implement the `time` CSR. They require SBI to trap and emulate it which is allowed by RVA20U.
1 parent d392563 commit 3e1d4d4

File tree

2 files changed

+72
-12
lines changed

2 files changed

+72
-12
lines changed

‎clang/test/Driver/riscv-cpus.c‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,6 @@
462462
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif"
463463
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm"
464464
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse"
465-
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicntr"
466465
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr"
467466
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei"
468467
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl"
@@ -492,7 +491,6 @@
492491
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
493492
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
494493
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
495-
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicntr"
496494
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
497495
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
498496
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
@@ -555,7 +553,6 @@
555553
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif"
556554
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm"
557555
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse"
558-
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicntr"
559556
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr"
560557
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei"
561558
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl"

‎llvm/lib/Target/RISCV/RISCVProcessors.td‎

Lines changed: 72 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -347,16 +347,58 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
347347
TunePostRAScheduler];
348348

349349
def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
350-
!listconcat(RVA22U64Features,
351-
[FeatureStdExtZifencei,
350+
[Feature64Bit,
351+
FeatureStdExtI,
352+
FeatureStdExtM,
353+
FeatureStdExtA,
354+
FeatureStdExtF,
355+
FeatureStdExtD,
356+
FeatureStdExtC,
357+
FeatureStdExtZicsr,
358+
FeatureStdExtZiccif,
359+
FeatureStdExtZiccrse,
360+
FeatureStdExtZiccamoa,
361+
FeatureStdExtZicclsm,
362+
FeatureStdExtZa64rs,
363+
FeatureStdExtZihpm,
364+
FeatureStdExtZihintpause,
365+
FeatureStdExtB,
366+
FeatureStdExtZic64b,
367+
FeatureStdExtZicbom,
368+
FeatureStdExtZicbop,
369+
FeatureStdExtZicboz,
370+
FeatureStdExtZfhmin,
371+
FeatureStdExtZkt,
372+
FeatureStdExtZifencei,
352373
FeatureStdExtZihintntl,
353374
FeatureUnalignedScalarMem,
354-
FeatureUnalignedVectorMem]),
375+
FeatureUnalignedVectorMem],
355376
SiFiveP400TuneFeatures>;
356377

357378
def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
358-
!listconcat(RVA22U64Features,
359-
[FeatureStdExtV,
379+
[Feature64Bit,
380+
FeatureStdExtI,
381+
FeatureStdExtM,
382+
FeatureStdExtA,
383+
FeatureStdExtF,
384+
FeatureStdExtD,
385+
FeatureStdExtC,
386+
FeatureStdExtZicsr,
387+
FeatureStdExtZiccif,
388+
FeatureStdExtZiccrse,
389+
FeatureStdExtZiccamoa,
390+
FeatureStdExtZicclsm,
391+
FeatureStdExtZa64rs,
392+
FeatureStdExtZihpm,
393+
FeatureStdExtZihintpause,
394+
FeatureStdExtB,
395+
FeatureStdExtZic64b,
396+
FeatureStdExtZicbom,
397+
FeatureStdExtZicbop,
398+
FeatureStdExtZicboz,
399+
FeatureStdExtZfhmin,
400+
FeatureStdExtZkt,
401+
FeatureStdExtV,
360402
FeatureStdExtZifencei,
361403
FeatureStdExtZihintntl,
362404
FeatureStdExtZvl128b,
@@ -368,7 +410,7 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
368410
FeatureVendorXSiFivecdiscarddlone,
369411
FeatureVendorXSiFivecflushdlone,
370412
FeatureUnalignedScalarMem,
371-
FeatureUnalignedVectorMem]),
413+
FeatureUnalignedVectorMem],
372414
!listconcat(SiFiveP400TuneFeatures,
373415
[TuneNoSinkSplatOperands,
374416
TuneVXRMPipelineFlush])>;
@@ -397,8 +439,29 @@ def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,
397439
}
398440

399441
def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
400-
!listconcat(RVA22U64Features,
401-
[FeatureStdExtV,
442+
[Feature64Bit,
443+
FeatureStdExtI,
444+
FeatureStdExtM,
445+
FeatureStdExtA,
446+
FeatureStdExtF,
447+
FeatureStdExtD,
448+
FeatureStdExtC,
449+
FeatureStdExtZicsr,
450+
FeatureStdExtZiccif,
451+
FeatureStdExtZiccrse,
452+
FeatureStdExtZiccamoa,
453+
FeatureStdExtZicclsm,
454+
FeatureStdExtZa64rs,
455+
FeatureStdExtZihpm,
456+
FeatureStdExtZihintpause,
457+
FeatureStdExtB,
458+
FeatureStdExtZic64b,
459+
FeatureStdExtZicbom,
460+
FeatureStdExtZicbop,
461+
FeatureStdExtZicboz,
462+
FeatureStdExtZfhmin,
463+
FeatureStdExtZkt,
464+
FeatureStdExtV,
402465
FeatureStdExtZifencei,
403466
FeatureStdExtZihintntl,
404467
FeatureStdExtZvl128b,
@@ -408,7 +471,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
408471
FeatureStdExtZvksc,
409472
FeatureStdExtZvksg,
410473
FeatureUnalignedScalarMem,
411-
FeatureUnalignedVectorMem]),
474+
FeatureUnalignedVectorMem],
412475
[TuneNoDefaultUnroll,
413476
TuneConditionalCompressedMoveFusion,
414477
TuneLUIADDIFusion,

0 commit comments

Comments
 (0)