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Tony Varghese
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[PowerPC]xxeval instruction for ternary operations support for v4i32
1 parent 4dcdf7a commit 3da0ef4

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6 files changed

+56
-42
lines changed

6 files changed

+56
-42
lines changed

‎llvm/lib/Target/PowerPC/PPCInstrP10.td

Lines changed: 4 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2171,26 +2171,15 @@ class DagCondVNot<dag d, bit negate> {
21712171

21722172
class XXEvalUnaryPattern<ValueType vt> {
21732173
// vnot Operand B
2174-
dag vnotB = !cond(
2175-
!eq(vt, v4i32) : (vnot v4i32:$vB),
2176-
!eq(vt, v2i64) : (v2i64 (bitconvert (vnot (v4i32 (bitconvert v2i64:$vB)))))
2177-
);
2174+
dag vnotB = (vnot vt:$vB);
21782175
// vnot Operand C
2179-
dag vnotC = !cond(
2180-
!eq(vt, v4i32) : (vnot v4i32:$vC),
2181-
!eq(vt, v2i64) : (v2i64 (bitconvert (vnot (v4i32 (bitconvert v2i64:$vC)))))
2182-
);
2176+
dag vnotC = (vnot vt:$vC);
21832177
}
21842178

21852179
class XXEvalBinaryPattern<ValueType vt, SDPatternOperator op, bit notResult = 0> {
21862180
// Defines a wrapper class for binary patterns with optional NOT on result.
21872181
// Generate op pattern with optional NOT wrapping for result depending on "notResult".
2188-
dag opPat = !cond(
2189-
!eq(vt, v4i32) : DagCondVNot<(op v4i32:$vB, v4i32:$vC), notResult>.res,
2190-
!eq(vt, v2i64) : (v2i64 (bitconvert DagCondVNot<(op
2191-
(v4i32 (bitconvert v2i64:$vB)),
2192-
(v4i32 (bitconvert v2i64:$vC))), notResult>.res))
2193-
);
2182+
dag opPat = DagCondVNot<(op vt:$vB, vt:$vC), notResult>.res;
21942183
}
21952184

21962185
multiclass XXEvalVSelectWithXAnd<ValueType vt, bits<8> baseImm> {
@@ -2395,16 +2384,12 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
23952384

23962385
// Utilize xxeval instruction for ternary vector expressions.
23972386
defm : XXEvalVSelectWithXAnd<v4i32, 22>;
2398-
defm : XXEvalVSelectWithXAnd<v2i64, 22>;
23992387

24002388
defm : XXEvalVSelectWithXB<v4i32, 49>;
2401-
defm : XXEvalVSelectWithXB<v2i64, 49>;
24022389

24032390
defm : XXEvalVSelectWithXC<v4i32, 81>;
2404-
defm : XXEvalVSelectWithXC<v2i64, 81>;
2405-
2391+
24062392
defm : XXEvalVSelectWithXXor<v4i32, 97>;
2407-
defm : XXEvalVSelectWithXXor<v2i64, 97>;
24082393

24092394
// Anonymous patterns to select prefixed VSX loads and stores.
24102395
// Load / Store f128

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,12 @@ define <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i
3131
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
3232
; CHECK: # %bb.0: # %entry
3333
; CHECK-NEXT: xxlxor v5, v5, v5
34+
; CHECK-NEXT: xxlxor vs0, v3, v4
35+
; CHECK-NEXT: xxland vs1, v3, v4
3436
; CHECK-NEXT: xxsplti32dx v5, 1, 63
3537
; CHECK-NEXT: vsld v2, v2, v5
3638
; CHECK-NEXT: vsrad v2, v2, v5
37-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 22
39+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
3840
; CHECK-NEXT: blr
3941
entry:
4042
%xor = xor <2 x i64> %B, %C
@@ -65,10 +67,12 @@ define <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i
6567
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
6668
; CHECK: # %bb.0: # %entry
6769
; CHECK-NEXT: xxlxor v5, v5, v5
70+
; CHECK-NEXT: xxlnor vs0, v3, v4
71+
; CHECK-NEXT: xxland vs1, v3, v4
6872
; CHECK-NEXT: xxsplti32dx v5, 1, 63
6973
; CHECK-NEXT: vsld v2, v2, v5
7074
; CHECK-NEXT: vsrad v2, v2, v5
71-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
75+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
7276
; CHECK-NEXT: blr
7377
entry:
7478
%or = or <2 x i64> %B, %C
@@ -100,10 +104,12 @@ define <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i
100104
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
101105
; CHECK: # %bb.0: # %entry
102106
; CHECK-NEXT: xxlxor v5, v5, v5
107+
; CHECK-NEXT: xxleqv vs0, v3, v4
108+
; CHECK-NEXT: xxland vs1, v3, v4
103109
; CHECK-NEXT: xxsplti32dx v5, 1, 63
104110
; CHECK-NEXT: vsld v2, v2, v5
105111
; CHECK-NEXT: vsrad v2, v2, v5
106-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 25
112+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
107113
; CHECK-NEXT: blr
108114
entry:
109115
%xor = xor <2 x i64> %B, %C
@@ -134,10 +140,12 @@ define <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i6
134140
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
135141
; CHECK: # %bb.0: # %entry
136142
; CHECK-NEXT: xxlxor v5, v5, v5
143+
; CHECK-NEXT: xxlnor vs0, v4, v4
144+
; CHECK-NEXT: xxland vs1, v3, v4
137145
; CHECK-NEXT: xxsplti32dx v5, 1, 63
138146
; CHECK-NEXT: vsld v2, v2, v5
139147
; CHECK-NEXT: vsrad v2, v2, v5
140-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 26
148+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
141149
; CHECK-NEXT: blr
142150
entry:
143151
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
@@ -167,10 +175,12 @@ define <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i6
167175
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
168176
; CHECK: # %bb.0: # %entry
169177
; CHECK-NEXT: xxlxor v5, v5, v5
178+
; CHECK-NEXT: xxlnor vs0, v3, v3
179+
; CHECK-NEXT: xxland vs1, v3, v4
170180
; CHECK-NEXT: xxsplti32dx v5, 1, 63
171181
; CHECK-NEXT: vsld v2, v2, v5
172182
; CHECK-NEXT: vsrad v2, v2, v5
173-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 28
183+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
174184
; CHECK-NEXT: blr
175185
entry:
176186
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,11 @@ define <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
3030
; CHECK-LABEL: ternary_A_and_BC_B_2x64:
3131
; CHECK: # %bb.0: # %entry
3232
; CHECK-NEXT: xxlxor v5, v5, v5
33+
; CHECK-NEXT: xxland vs0, v3, v4
3334
; CHECK-NEXT: xxsplti32dx v5, 1, 63
3435
; CHECK-NEXT: vsld v2, v2, v5
3536
; CHECK-NEXT: vsrad v2, v2, v5
36-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 49
37+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
3738
; CHECK-NEXT: blr
3839
entry:
3940
%and = and <2 x i64> %B, %C
@@ -62,10 +63,11 @@ define <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
6263
; CHECK-LABEL: ternary_A_nor_BC_B_2x64:
6364
; CHECK: # %bb.0: # %entry
6465
; CHECK-NEXT: xxlxor v5, v5, v5
66+
; CHECK-NEXT: xxlnor vs0, v3, v4
6567
; CHECK-NEXT: xxsplti32dx v5, 1, 63
6668
; CHECK-NEXT: vsld v2, v2, v5
6769
; CHECK-NEXT: vsrad v2, v2, v5
68-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 56
70+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
6971
; CHECK-NEXT: blr
7072
entry:
7173
%or = or <2 x i64> %B, %C
@@ -95,10 +97,11 @@ define <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
9597
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64:
9698
; CHECK: # %bb.0: # %entry
9799
; CHECK-NEXT: xxlxor v5, v5, v5
100+
; CHECK-NEXT: xxleqv vs0, v3, v4
98101
; CHECK-NEXT: xxsplti32dx v5, 1, 63
99102
; CHECK-NEXT: vsld v2, v2, v5
100103
; CHECK-NEXT: vsrad v2, v2, v5
101-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 57
104+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
102105
; CHECK-NEXT: blr
103106
entry:
104107
%xor = xor <2 x i64> %B, %C
@@ -127,10 +130,11 @@ define <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C
127130
; CHECK-LABEL: ternary_A_not_C_B_2x64:
128131
; CHECK: # %bb.0: # %entry
129132
; CHECK-NEXT: xxlxor v5, v5, v5
133+
; CHECK-NEXT: xxlnor vs0, v4, v4
130134
; CHECK-NEXT: xxsplti32dx v5, 1, 63
131135
; CHECK-NEXT: vsld v2, v2, v5
132136
; CHECK-NEXT: vsrad v2, v2, v5
133-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 58
137+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
134138
; CHECK-NEXT: blr
135139
entry:
136140
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
@@ -159,10 +163,11 @@ define <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64>
159163
; CHECK-LABEL: ternary_A_nand_BC_B_2x64:
160164
; CHECK: # %bb.0: # %entry
161165
; CHECK-NEXT: xxlxor v5, v5, v5
166+
; CHECK-NEXT: xxlnand vs0, v3, v4
162167
; CHECK-NEXT: xxsplti32dx v5, 1, 63
163168
; CHECK-NEXT: vsld v2, v2, v5
164169
; CHECK-NEXT: vsrad v2, v2, v5
165-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 62
170+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
166171
; CHECK-NEXT: blr
167172
entry:
168173
%and = and <2 x i64> %B, %C

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,11 @@ define <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
3030
; CHECK-LABEL: ternary_A_and_BC_C_2x64:
3131
; CHECK: # %bb.0: # %entry
3232
; CHECK-NEXT: xxlxor v5, v5, v5
33+
; CHECK-NEXT: xxland vs0, v3, v4
3334
; CHECK-NEXT: xxsplti32dx v5, 1, 63
3435
; CHECK-NEXT: vsld v2, v2, v5
3536
; CHECK-NEXT: vsrad v2, v2, v5
36-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 81
37+
; CHECK-NEXT: xxsel v2, v4, vs0, v2
3738
; CHECK-NEXT: blr
3839
entry:
3940
%and = and <2 x i64> %B, %C
@@ -62,10 +63,11 @@ define <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
6263
; CHECK-LABEL: ternary_A_nor_BC_C_2x64:
6364
; CHECK: # %bb.0: # %entry
6465
; CHECK-NEXT: xxlxor v5, v5, v5
66+
; CHECK-NEXT: xxlnor vs0, v3, v4
6567
; CHECK-NEXT: xxsplti32dx v5, 1, 63
6668
; CHECK-NEXT: vsld v2, v2, v5
6769
; CHECK-NEXT: vsrad v2, v2, v5
68-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 88
70+
; CHECK-NEXT: xxsel v2, v4, vs0, v2
6971
; CHECK-NEXT: blr
7072
entry:
7173
%or = or <2 x i64> %B, %C
@@ -95,10 +97,11 @@ define <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
9597
; CHECK-LABEL: ternary_A_eqv_BC_C_2x64:
9698
; CHECK: # %bb.0: # %entry
9799
; CHECK-NEXT: xxlxor v5, v5, v5
100+
; CHECK-NEXT: xxleqv vs0, v3, v4
98101
; CHECK-NEXT: xxsplti32dx v5, 1, 63
99102
; CHECK-NEXT: vsld v2, v2, v5
100103
; CHECK-NEXT: vsrad v2, v2, v5
101-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 89
104+
; CHECK-NEXT: xxsel v2, v4, vs0, v2
102105
; CHECK-NEXT: blr
103106
entry:
104107
%xor = xor <2 x i64> %B, %C
@@ -128,10 +131,11 @@ define <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64>
128131
; CHECK-LABEL: ternary_A_nand_BC_C_2x64:
129132
; CHECK: # %bb.0: # %entry
130133
; CHECK-NEXT: xxlxor v5, v5, v5
134+
; CHECK-NEXT: xxlnand vs0, v3, v4
131135
; CHECK-NEXT: xxsplti32dx v5, 1, 63
132136
; CHECK-NEXT: vsld v2, v2, v5
133137
; CHECK-NEXT: vsrad v2, v2, v5
134-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 94
138+
; CHECK-NEXT: xxsel v2, v4, vs0, v2
135139
; CHECK-NEXT: blr
136140
entry:
137141
%and = and <2 x i64> %B, %C

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-or.ll

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -176,11 +176,12 @@ define <2 x i64> @ternary_A_not_C_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64
176176
; CHECK-LABEL: ternary_A_not_C_or_BC_2x64:
177177
; CHECK: # %bb.0: # %entry
178178
; CHECK-NEXT: xxlxor v5, v5, v5
179-
; CHECK-NEXT: xxlor vs0, v3, v4
179+
; CHECK-NEXT: xxlnor vs0, v4, v4
180+
; CHECK-NEXT: xxlor vs1, v3, v4
180181
; CHECK-NEXT: xxsplti32dx v5, 1, 63
181182
; CHECK-NEXT: vsld v2, v2, v5
182183
; CHECK-NEXT: vsrad v2, v2, v5
183-
; CHECK-NEXT: xxeval v2, v2, vs0, v4, 58
184+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
184185
; CHECK-NEXT: blr
185186
entry:
186187
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
@@ -211,11 +212,12 @@ define <2 x i64> @ternary_A_not_B_or_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64
211212
; CHECK-LABEL: ternary_A_not_B_or_BC_2x64:
212213
; CHECK: # %bb.0: # %entry
213214
; CHECK-NEXT: xxlxor v5, v5, v5
214-
; CHECK-NEXT: xxlor vs0, v3, v4
215+
; CHECK-NEXT: xxlnor vs0, v3, v3
216+
; CHECK-NEXT: xxlor vs1, v3, v4
215217
; CHECK-NEXT: xxsplti32dx v5, 1, 63
216218
; CHECK-NEXT: vsld v2, v2, v5
217219
; CHECK-NEXT: vsrad v2, v2, v5
218-
; CHECK-NEXT: xxeval v2, v2, vs0, v3, 58
220+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
219221
; CHECK-NEXT: blr
220222
entry:
221223
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,12 @@ define <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i
3131
; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64:
3232
; CHECK: # %bb.0: # %entry
3333
; CHECK-NEXT: xxlxor v5, v5, v5
34+
; CHECK-NEXT: xxland vs0, v3, v4
35+
; CHECK-NEXT: xxlxor vs1, v3, v4
3436
; CHECK-NEXT: xxsplti32dx v5, 1, 63
3537
; CHECK-NEXT: vsld v2, v2, v5
3638
; CHECK-NEXT: vsrad v2, v2, v5
37-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 97
39+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
3840
; CHECK-NEXT: blr
3941
entry:
4042
%and = and <2 x i64> %B, %C
@@ -63,10 +65,11 @@ define <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
6365
; CHECK-LABEL: ternary_A_B_xor_BC_2x64:
6466
; CHECK: # %bb.0: # %entry
6567
; CHECK-NEXT: xxlxor v5, v5, v5
68+
; CHECK-NEXT: xxlxor vs0, v3, v4
6669
; CHECK-NEXT: xxsplti32dx v5, 1, 63
6770
; CHECK-NEXT: vsld v2, v2, v5
6871
; CHECK-NEXT: vsrad v2, v2, v5
69-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 99
72+
; CHECK-NEXT: xxsel v2, vs0, v3, v2
7073
; CHECK-NEXT: blr
7174
entry:
7275
%xor = xor <2 x i64> %B, %C
@@ -94,10 +97,11 @@ define <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %
9497
; CHECK-LABEL: ternary_A_C_xor_BC_2x64:
9598
; CHECK: # %bb.0: # %entry
9699
; CHECK-NEXT: xxlxor v5, v5, v5
100+
; CHECK-NEXT: xxlxor vs0, v3, v4
97101
; CHECK-NEXT: xxsplti32dx v5, 1, 63
98102
; CHECK-NEXT: vsld v2, v2, v5
99103
; CHECK-NEXT: vsrad v2, v2, v5
100-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 101
104+
; CHECK-NEXT: xxsel v2, vs0, v4, v2
101105
; CHECK-NEXT: blr
102106
entry:
103107
%xor = xor <2 x i64> %B, %C
@@ -126,10 +130,12 @@ define <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i6
126130
; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64:
127131
; CHECK: # %bb.0: # %entry
128132
; CHECK-NEXT: xxlxor v5, v5, v5
133+
; CHECK-NEXT: xxlor vs0, v3, v4
134+
; CHECK-NEXT: xxlxor vs1, v3, v4
129135
; CHECK-NEXT: xxsplti32dx v5, 1, 63
130136
; CHECK-NEXT: vsld v2, v2, v5
131137
; CHECK-NEXT: vsrad v2, v2, v5
132-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 103
138+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
133139
; CHECK-NEXT: blr
134140
entry:
135141
%or = or <2 x i64> %B, %C
@@ -160,10 +166,12 @@ define <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i
160166
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64:
161167
; CHECK: # %bb.0: # %entry
162168
; CHECK-NEXT: xxlxor v5, v5, v5
169+
; CHECK-NEXT: xxlnor vs0, v3, v4
170+
; CHECK-NEXT: xxlxor vs1, v3, v4
163171
; CHECK-NEXT: xxsplti32dx v5, 1, 63
164172
; CHECK-NEXT: vsld v2, v2, v5
165173
; CHECK-NEXT: vsrad v2, v2, v5
166-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 104
174+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
167175
; CHECK-NEXT: blr
168176
entry:
169177
%or = or <2 x i64> %B, %C

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