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1 parent b3c72a9 commit 362594aCopy full SHA for 362594a
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2295,9 +2295,6 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
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SRSets[I].push_back(R);
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}
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- for (auto I : SRSets)
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- sortAndUniqueRegisters(I.second);
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-
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// Find matching classes for all SRSets entries. Iterate in SubRegIndex
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// numerical order to visit synthetic indices last.
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for (const CodeGenSubRegIndex &SubIdx : SubRegIndices) {
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