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[RISCV] Add support of Sdext,Sdtrig extentions (#120936)
`Sdext` and `Sdtrig` are RISC-V extensions related to debugging. The full specification can be found at https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
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// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
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// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
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// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
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// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
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// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
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// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
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// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)

‎clang/test/Preprocessor/riscv-target-features.c‎

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// Experimental extensions
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// CHECK-NOT: __riscv_sdext{{.*$}}
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// CHECK-NOT: __riscv_sdtrig{{.*$}}
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// CHECK-NOT: __riscv_smctr{{.*$}}
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// CHECK-NOT: __riscv_smmpm{{.*$}}
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// CHECK-NOT: __riscv_smnpm{{.*$}}
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// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
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// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_sdext1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SDEXT-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_sdext1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SDEXT-EXT %s
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// CHECK-SDEXT-EXT: __riscv_sdext 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_sdtrig1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SDTRIG-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_sdtrig1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SDTRIG-EXT %s
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// CHECK-SDTRIG-EXT: __riscv_sdtrig 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_smctr1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCTR-EXT %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -326,6 +326,9 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zvbc32e``, ``experimental-zvkgs``
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LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.
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``experimental-sdext``, ``experimental-sdtrig``
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LLVM implements the `1.0-rc4 specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf>`__.
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``experimental-smctr``, ``experimental-ssctr``
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LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__.
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‎llvm/docs/ReleaseNotes.md‎

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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcicli` (Conditional Load Immediate)
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extension.
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* Added ``Sdext`` and ``Sdtrig`` extensions.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -844,6 +844,10 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
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// Supervisor extensions
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def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
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def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
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def FeatureStdExtShgatpa
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: RISCVExtension<1, 0,
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"SvNNx4 mode supported for all modes supported by satp, as well as Bare">;

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td‎

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@@ -323,7 +323,10 @@ def : SysReg<"tselect", 0x7A0>;
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def : SysReg<"tdata1", 0x7A1>;
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def : SysReg<"tdata2", 0x7A2>;
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def : SysReg<"tdata3", 0x7A3>;
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def : SysReg<"tinfo", 0x7A4>;
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def : SysReg<"tcontrol", 0x7A5>;
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def : SysReg<"mcontext", 0x7A8>;
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def : SysReg<"mscontext", 0x7AA>;
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//===----------------------------------------------------------------------===//
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// Debug Mode Registers

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
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; Tests for profile features.
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; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
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; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
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; RV64SMCTR: .attribute 5, "rv64i2p1_smctr1p0_sscsrind1p0"
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; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0"
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; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
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; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
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; RVI20U32: .attribute 5, "rv32i2p1"
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; RVI20U64: .attribute 5, "rv64i2p1"

‎llvm/test/CodeGen/RISCV/features-info.ll‎

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; CHECK: e - 'E' (Embedded Instruction Set with 16 GPRs).
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; CHECK: experimental - Experimental intrinsics.
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; CHECK: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
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; CHECK: experimental-sdext - 'Sdext' (External debugger).
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; CHECK: experimental-sdtrig - 'Sdtrig' (Debugger triggers).
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; CHECK: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
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; CHECK: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
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; CHECK: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).

‎llvm/test/MC/RISCV/attribute-arch.s‎

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.attribute arch, "rv32i_ssctr1p0"
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# CHECK: attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
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.attribute arch, "rv32i_sdext1p0"
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# CHECK: attribute 5, "rv32i2p1_sdext1p0"
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.attribute arch, "rv32i_sdtrig1p0"
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# CHECK: attribute 5, "rv32i2p1_sdtrig1p0"

‎llvm/test/MC/RISCV/machine-csr-names.s‎

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# uimm12
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csrrs t2, 0x7A3, zero
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# tinfo
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# name
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# CHECK-INST: csrrs t1, tinfo, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x40,0x7a]
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# CHECK-INST-ALIAS: csrr t1, tinfo
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# uimm12
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# CHECK-INST: csrrs t2, tinfo, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7a]
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# CHECK-INST-ALIAS: csrr t2, tinfo
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# name
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csrrs t1, tinfo, zero
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# uimm12
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csrrs t2, 0x7A4, zero
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# tcontrol
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# name
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# CHECK-INST: csrrs t1, tcontrol, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x50,0x7a]
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# CHECK-INST-ALIAS: csrr t1, tcontrol
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# uimm12
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# CHECK-INST: csrrs t2, tcontrol, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7a]
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# CHECK-INST-ALIAS: csrr t2, tcontrol
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# name
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csrrs t1, tcontrol, zero
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# uimm12
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csrrs t2, 0x7A5, zero
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# mcontext
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# name
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# CHECK-INST: csrrs t1, mcontext, zero
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# uimm12
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csrrs t2, 0x7A8, zero
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# mscontext
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# name
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# CHECK-INST: csrrs t1, mscontext, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x7a]
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# CHECK-INST-ALIAS: csrr t1, mscontext
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# uimm12
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# CHECK-INST: csrrs t2, mscontext, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7a]
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# CHECK-INST-ALIAS: csrr t2, mscontext
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# name
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csrrs t1, mscontext, zero
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# uimm12
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csrrs t2, 0x7AA, zero
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#######################
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# Debug Mode Registers
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########################

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