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RISCV: Replace most Specifier constants with relocation types
... as they map directly and we don't utilize -Wswitch. Retained VK_*_LO constants for lowering to LO_I or LO_S. The Sparc port has eliminated all Specifier constants (commit 003fa77), and the LoongArch port is nearly free of them (#138632). Pull Request: #138644
1 parent 573746e commit 2f05451

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9 files changed

+103
-145
lines changed

9 files changed

+103
-145
lines changed

‎bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -247,7 +247,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
247247
Inst.clear();
248248
Inst.addOperand(MCOperand::createExpr(RISCVMCExpr::create(
249249
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx),
250-
RISCVMCExpr::VK_CALL, *Ctx)));
250+
ELF::R_RISCV_CALL_PLT, *Ctx)));
251251
}
252252

253253
void createCall(MCInst &Inst, const MCSymbol *Target,
@@ -435,19 +435,19 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
435435
case ELF::R_RISCV_TLS_GD_HI20:
436436
// The GOT is reused so no need to create GOT relocations
437437
case ELF::R_RISCV_PCREL_HI20:
438-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_PCREL_HI, Ctx);
438+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_PCREL_HI20, Ctx);
439439
case ELF::R_RISCV_PCREL_LO12_I:
440440
case ELF::R_RISCV_PCREL_LO12_S:
441441
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_PCREL_LO, Ctx);
442442
case ELF::R_RISCV_HI20:
443-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_HI, Ctx);
443+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_HI20, Ctx);
444444
case ELF::R_RISCV_LO12_I:
445445
case ELF::R_RISCV_LO12_S:
446446
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_LO, Ctx);
447447
case ELF::R_RISCV_CALL:
448-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_CALL, Ctx);
448+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
449449
case ELF::R_RISCV_CALL_PLT:
450-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_CALL_PLT, Ctx);
450+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
451451
}
452452
}
453453

@@ -472,8 +472,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
472472
switch (cast<RISCVMCExpr>(ImmExpr)->getSpecifier()) {
473473
default:
474474
return false;
475-
case RISCVMCExpr::VK_CALL:
476-
case RISCVMCExpr::VK_CALL_PLT:
475+
case ELF::R_RISCV_CALL_PLT:
477476
return true;
478477
}
479478
}

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -583,7 +583,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
583583

584584
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
585585
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
586-
(VK == RISCVMCExpr::VK_CALL || VK == RISCVMCExpr::VK_CALL_PLT);
586+
VK == ELF::R_RISCV_CALL_PLT;
587587
}
588588

589589
bool isPseudoJumpSymbol() const {
@@ -594,7 +594,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
594594

595595
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
596596
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
597-
VK == RISCVMCExpr::VK_CALL;
597+
VK == ELF::R_RISCV_CALL_PLT;
598598
}
599599

600600
bool isTPRelAddSymbol() const {
@@ -605,7 +605,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
605605

606606
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
607607
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
608-
VK == RISCVMCExpr::VK_TPREL_ADD;
608+
VK == ELF::R_RISCV_TPREL_ADD;
609609
}
610610

611611
bool isTLSDESCCallSymbol() const {
@@ -616,7 +616,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
616616

617617
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
618618
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
619-
VK == RISCVMCExpr::VK_TLSDESC_CALL;
619+
VK == ELF::R_RISCV_TLSDESC_CALL;
620620
}
621621

622622
bool isCSRSystemRegister() const { return isSystemRegister(); }
@@ -868,8 +868,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
868868
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
869869
(VK == RISCVMCExpr::VK_LO || VK == RISCVMCExpr::VK_PCREL_LO ||
870870
VK == RISCVMCExpr::VK_TPREL_LO ||
871-
VK == RISCVMCExpr::VK_TLSDESC_LOAD_LO ||
872-
VK == RISCVMCExpr::VK_TLSDESC_ADD_LO);
871+
VK == ELF::R_RISCV_TLSDESC_LOAD_LO12 ||
872+
VK == ELF::R_RISCV_TLSDESC_ADD_LO12);
873873
}
874874

875875
bool isSImm12Lsb00000() const {
@@ -912,7 +912,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
912912

913913
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
914914
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
915-
(VK == RISCVMCExpr::VK_HI || VK == RISCVMCExpr::VK_TPREL_HI);
915+
(VK == ELF::R_RISCV_HI20 || VK == ELF::R_RISCV_TPREL_HI20);
916916
}
917917

918918
bool isUImm20AUIPC() const {
@@ -925,10 +925,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
925925

926926
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
927927
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
928-
(VK == RISCVMCExpr::VK_PCREL_HI || VK == RISCVMCExpr::VK_GOT_HI ||
929-
VK == RISCVMCExpr::VK_TLS_GOT_HI ||
930-
VK == RISCVMCExpr::VK_TLS_GD_HI ||
931-
VK == RISCVMCExpr::VK_TLSDESC_HI);
928+
(VK == ELF::R_RISCV_PCREL_HI20 || VK == ELF::R_RISCV_GOT_HI20 ||
929+
VK == ELF::R_RISCV_TLS_GOT_HI20 || VK == ELF::R_RISCV_TLS_GD_HI20 ||
930+
VK == ELF::R_RISCV_TLSDESC_HI20);
932931
}
933932

934933
bool isImmZero() const {
@@ -2180,7 +2179,7 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
21802179
}
21812180

21822181
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
2183-
RISCVMCExpr::Specifier Kind = RISCVMCExpr::VK_CALL_PLT;
2182+
RISCVMCExpr::Specifier Kind = ELF::R_RISCV_CALL_PLT;
21842183

21852184
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
21862185
Res = MCSymbolRefExpr::create(Sym, getContext());
@@ -2200,7 +2199,7 @@ ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) {
22002199
if (Res->getKind() != MCExpr::ExprKind::SymbolRef)
22012200
return Error(S, "operand must be a valid jump target");
22022201

2203-
Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_CALL, getContext());
2202+
Res = RISCVMCExpr::create(Res, ELF::R_RISCV_CALL_PLT, getContext());
22042203
Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
22052204
return ParseStatus::Success;
22062205
}
@@ -3421,7 +3420,7 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
34213420
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
34223421
MCRegister DestReg = Inst.getOperand(0).getReg();
34233422
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
3424-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_PCREL_HI,
3423+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_PCREL_HI20,
34253424
RISCV::ADDI, IDLoc, Out);
34263425
}
34273426

@@ -3436,7 +3435,7 @@ void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
34363435
MCRegister DestReg = Inst.getOperand(0).getReg();
34373436
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
34383437
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
3439-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_GOT_HI,
3438+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_GOT_HI20,
34403439
SecondOpcode, IDLoc, Out);
34413440
}
34423441

@@ -3466,7 +3465,7 @@ void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
34663465
MCRegister DestReg = Inst.getOperand(0).getReg();
34673466
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
34683467
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
3469-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GOT_HI,
3468+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GOT_HI20,
34703469
SecondOpcode, IDLoc, Out);
34713470
}
34723471

@@ -3480,7 +3479,7 @@ void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
34803479
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
34813480
MCRegister DestReg = Inst.getOperand(0).getReg();
34823481
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
3483-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GD_HI,
3482+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GD_HI20,
34843483
RISCV::ADDI, IDLoc, Out);
34853484
}
34863485

@@ -3506,7 +3505,7 @@ void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
35063505
}
35073506

35083507
const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr();
3509-
emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_PCREL_HI, Opcode,
3508+
emitAuipcInstPair(DestReg, TmpReg, Symbol, ELF::R_RISCV_PCREL_HI20, Opcode,
35103509
IDLoc, Out);
35113510
}
35123511

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp‎

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -54,15 +54,15 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
5454
unsigned Kind = Fixup.getTargetKind();
5555
auto Spec = RISCVMCExpr::Specifier(Target.getSpecifier());
5656
switch (Spec) {
57-
case RISCVMCExpr::VK_TPREL_HI:
58-
case RISCVMCExpr::VK_TLS_GOT_HI:
59-
case RISCVMCExpr::VK_TLS_GD_HI:
60-
case RISCVMCExpr::VK_TLSDESC_HI:
57+
case ELF::R_RISCV_TPREL_HI20:
58+
case ELF::R_RISCV_TLS_GOT_HI20:
59+
case ELF::R_RISCV_TLS_GD_HI20:
60+
case ELF::R_RISCV_TLSDESC_HI20:
6161
if (auto *SA = Target.getAddSym())
6262
cast<MCSymbolELF>(SA)->setType(ELF::STT_TLS);
6363
break;
64-
case RISCVMCExpr::VK_PLTPCREL:
65-
case RISCVMCExpr::VK_GOTPCREL:
64+
case ELF::R_RISCV_PLT32:
65+
case ELF::R_RISCV_GOT32_PCREL:
6666
if (Kind == FK_Data_4)
6767
break;
6868
Ctx.reportError(Fixup.getLoc(),
@@ -124,15 +124,12 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
124124
return ELF::R_RISCV_NONE;
125125
case FK_Data_4:
126126
if (Expr->getKind() == MCExpr::Target) {
127-
switch (cast<RISCVMCExpr>(Expr)->getSpecifier()) {
128-
case RISCVMCExpr::VK_32_PCREL:
129-
return ELF::R_RISCV_32_PCREL;
130-
case RISCVMCExpr::VK_GOTPCREL:
131-
return ELF::R_RISCV_GOT32_PCREL;
132-
case RISCVMCExpr::VK_PLTPCREL:
133-
return ELF::R_RISCV_PLT32;
134-
default:
135-
break;
127+
auto Spec = cast<RISCVMCExpr>(Expr)->getSpecifier();
128+
switch (Spec) {
129+
case ELF::R_RISCV_32_PCREL:
130+
case ELF::R_RISCV_GOT32_PCREL:
131+
case ELF::R_RISCV_PLT32:
132+
return Spec;
136133
}
137134
}
138135
return ELF::R_RISCV_32;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include "RISCVMCAsmInfo.h"
1414
#include "MCTargetDesc/RISCVMCExpr.h"
1515
#include "llvm/BinaryFormat/Dwarf.h"
16+
#include "llvm/BinaryFormat/ELF.h"
1617
#include "llvm/MC/MCExpr.h"
1718
#include "llvm/MC/MCStreamer.h"
1819
#include "llvm/TargetParser/Triple.h"
@@ -44,5 +45,5 @@ const MCExpr *RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym,
4445
MCContext &Ctx = Streamer.getContext();
4546
const MCExpr *ME = MCSymbolRefExpr::create(Sym, Ctx);
4647
assert(Encoding & dwarf::DW_EH_PE_sdata4 && "Unexpected encoding");
47-
return RISCVMCExpr::create(ME, RISCVMCExpr::VK_32_PCREL, Ctx);
48+
return RISCVMCExpr::create(ME, ELF::R_RISCV_32_PCREL, Ctx);
4849
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

Lines changed: 12 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
206206
"Expected expression as third input to TP-relative add");
207207

208208
const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
209-
assert(Expr && Expr->getSpecifier() == RISCVMCExpr::VK_TPREL_ADD &&
209+
assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
210210
"Expected tprel_add relocation on TP-relative symbol");
211211

212212
// Emit the correct tprel_add relocation for the symbol.
@@ -573,20 +573,19 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
573573
bool RelaxCandidate = false;
574574
if (Kind == MCExpr::Target) {
575575
const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
576-
576+
FixupKind = RVExpr->getSpecifier();
577577
switch (RVExpr->getSpecifier()) {
578-
case RISCVMCExpr::VK_None:
579-
case RISCVMCExpr::VK_32_PCREL:
580-
case RISCVMCExpr::VK_GOTPCREL:
581-
case RISCVMCExpr::VK_PLTPCREL:
582-
llvm_unreachable("unhandled specifier");
583-
case RISCVMCExpr::VK_TPREL_ADD:
578+
default:
579+
assert(FixupKind && FixupKind < FirstTargetFixupKind &&
580+
"invalid specifier");
581+
break;
582+
case ELF::R_RISCV_TPREL_ADD:
584583
// tprel_add is only used to indicate that a relocation should be emitted
585584
// for an add instruction used in TP-relative addressing. It should not be
586585
// expanded as if representing an actual instruction operand and so to
587586
// encounter it here is an error.
588587
llvm_unreachable(
589-
"VK_TPREL_ADD should not represent an instruction operand");
588+
"ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");
590589
case RISCVMCExpr::VK_LO:
591590
if (MIFrm == RISCVII::InstFormatI)
592591
FixupKind = RISCV::fixup_riscv_lo12_i;
@@ -596,7 +595,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
596595
llvm_unreachable("VK_LO used with unexpected instruction format");
597596
RelaxCandidate = true;
598597
break;
599-
case RISCVMCExpr::VK_HI:
598+
case ELF::R_RISCV_HI20:
600599
FixupKind = RISCV::fixup_riscv_hi20;
601600
RelaxCandidate = true;
602601
break;
@@ -609,13 +608,10 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
609608
llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");
610609
RelaxCandidate = true;
611610
break;
612-
case RISCVMCExpr::VK_PCREL_HI:
611+
case ELF::R_RISCV_PCREL_HI20:
613612
FixupKind = RISCV::fixup_riscv_pcrel_hi20;
614613
RelaxCandidate = true;
615614
break;
616-
case RISCVMCExpr::VK_GOT_HI:
617-
FixupKind = ELF::R_RISCV_GOT_HI20;
618-
break;
619615
case RISCVMCExpr::VK_TPREL_LO:
620616
if (MIFrm == RISCVII::InstFormatI)
621617
FixupKind = ELF::R_RISCV_TPREL_LO12_I;
@@ -625,36 +621,13 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
625621
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
626622
RelaxCandidate = true;
627623
break;
628-
case RISCVMCExpr::VK_TPREL_HI:
629-
FixupKind = ELF::R_RISCV_TPREL_HI20;
624+
case ELF::R_RISCV_TPREL_HI20:
630625
RelaxCandidate = true;
631626
break;
632-
case RISCVMCExpr::VK_TLS_GOT_HI:
633-
FixupKind = ELF::R_RISCV_TLS_GOT_HI20;
634-
break;
635-
case RISCVMCExpr::VK_TLS_GD_HI:
636-
FixupKind = ELF::R_RISCV_TLS_GD_HI20;
637-
break;
638-
case RISCVMCExpr::VK_CALL:
639-
FixupKind = RISCV::fixup_riscv_call;
640-
RelaxCandidate = true;
641-
break;
642-
case RISCVMCExpr::VK_CALL_PLT:
627+
case ELF::R_RISCV_CALL_PLT:
643628
FixupKind = RISCV::fixup_riscv_call_plt;
644629
RelaxCandidate = true;
645630
break;
646-
case RISCVMCExpr::VK_TLSDESC_HI:
647-
FixupKind = ELF::R_RISCV_TLSDESC_HI20;
648-
break;
649-
case RISCVMCExpr::VK_TLSDESC_LOAD_LO:
650-
FixupKind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
651-
break;
652-
case RISCVMCExpr::VK_TLSDESC_ADD_LO:
653-
FixupKind = ELF::R_RISCV_TLSDESC_ADD_LO12;
654-
break;
655-
case RISCVMCExpr::VK_TLSDESC_CALL:
656-
FixupKind = ELF::R_RISCV_TLSDESC_CALL;
657-
break;
658631
case RISCVMCExpr::VK_QC_ABS20:
659632
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
660633
break;

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