fixup! Update tests

Author: mshockwave

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

@@ -1858,18 +1858,17 @@ define <8 x float> @buildvec_vfredusum_slideup_leading_undef(float %start, <8 x
 ; CHECK-LABEL: buildvec_vfredusum_slideup_leading_undef:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT:    vfmv.s.f v16, fa0
-; CHECK-NEXT:    vfredusum.vs v9, v8, v16
-; CHECK-NEXT:    vfredusum.vs v10, v10, v16
-; CHECK-NEXT:    vfredusum.vs v11, v12, v16
-; CHECK-NEXT:    vfredusum.vs v8, v14, v16
-; CHECK-NEXT:    vfmv.f.s fa5, v9
-; CHECK-NEXT:    vfmv.f.s fa4, v10
-; CHECK-NEXT:    vfmv.f.s fa3, v11
-; CHECK-NEXT:    vfslide1up.vf v10, v8, fa3
-; CHECK-NEXT:    vfslide1up.vf v8, v10, fa4
-; CHECK-NEXT:    vfslide1up.vf v10, v8, fa5
-; CHECK-NEXT:    vslideup.vi v8, v10, 4
+; CHECK-NEXT:    vfmv.s.f v17, fa0
+; CHECK-NEXT:    vfredusum.vs v16, v8, v17
+; CHECK-NEXT:    vfredusum.vs v8, v10, v17
+; CHECK-NEXT:    vfredusum.vs v10, v12, v17
+; CHECK-NEXT:    vfredusum.vs v12, v14, v17
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT:    vslideup.vi v10, v12, 1
+; CHECK-NEXT:    vslideup.vi v8, v10, 1
+; CHECK-NEXT:    vslideup.vi v16, v8, 1
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v16, 4
 ; CHECK-NEXT:    ret
   %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
   %253 = insertelement <8 x float> poison, float %252, i64 4
@@ -1887,16 +1886,14 @@ define <8 x float> @buildvec_vfredusum_slideup_trailing_undef(float %start, <8 x
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; CHECK-NEXT:    vfmv.s.f v16, fa0
-; CHECK-NEXT:    vfredusum.vs v9, v8, v16
+; CHECK-NEXT:    vfredusum.vs v8, v8, v16
 ; CHECK-NEXT:    vfredusum.vs v10, v10, v16
-; CHECK-NEXT:    vfredusum.vs v11, v12, v16
-; CHECK-NEXT:    vfredusum.vs v8, v14, v16
-; CHECK-NEXT:    vfmv.f.s fa5, v9
-; CHECK-NEXT:    vfmv.f.s fa4, v10
-; CHECK-NEXT:    vfmv.f.s fa3, v11
-; CHECK-NEXT:    vfslide1up.vf v10, v8, fa3
-; CHECK-NEXT:    vfslide1up.vf v12, v10, fa4
-; CHECK-NEXT:    vfslide1up.vf v8, v12, fa5
+; CHECK-NEXT:    vfredusum.vs v12, v12, v16
+; CHECK-NEXT:    vfredusum.vs v14, v14, v16
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT:    vslideup.vi v12, v14, 1
+; CHECK-NEXT:    vslideup.vi v10, v12, 1
+; CHECK-NEXT:    vslideup.vi v8, v10, 1
 ; CHECK-NEXT:    ret
   %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
   %253 = insertelement <8 x float> poison, float %252, i64 0
@@ -1941,17 +1938,17 @@ define <8 x float> @buildvec_vfredusum_slideup_mid_undef(float %start, <8 x floa
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; CHECK-NEXT:    vfmv.s.f v16, fa0
-; CHECK-NEXT:    vfredusum.vs v9, v8, v16
+; CHECK-NEXT:    vfredusum.vs v8, v8, v16
 ; CHECK-NEXT:    vfredusum.vs v10, v10, v16
-; CHECK-NEXT:    vfredusum.vs v11, v12, v16
-; CHECK-NEXT:    vfredusum.vs v8, v14, v16
-; CHECK-NEXT:    vfmv.f.s fa5, v9
-; CHECK-NEXT:    vfmv.f.s fa4, v10
-; CHECK-NEXT:    vfmv.f.s fa3, v11
-; CHECK-NEXT:    vfslide1up.vf v10, v8, fa3
-; CHECK-NEXT:    vslideup.vi v8, v10, 4
-; CHECK-NEXT:    vfslide1up.vf v10, v8, fa4
-; CHECK-NEXT:    vfslide1up.vf v8, v10, fa5
+; CHECK-NEXT:    vfredusum.vs v12, v12, v16
+; CHECK-NEXT:    vfredusum.vs v14, v14, v16
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT:    vslideup.vi v12, v14, 1
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vslideup.vi v14, v12, 4
+; CHECK-NEXT:    vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT:    vslideup.vi v10, v14, 1
+; CHECK-NEXT:    vslideup.vi v8, v10, 1
 ; CHECK-NEXT:    ret
   %252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
   %253 = insertelement <8 x float> poison, float %252, i64 0