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[X86][MC] Support Enc/Dec for EGPR for promoted MOVDIR instruction (#74713)
R16-R31 was added into GPRs in #70958, This patch supports the encoding/decoding for promoted MOVDIR instruction in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
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‎llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,8 @@ enum attributeBits {
140140
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
141141
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
142142
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
143+
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \
144+
"requires EVEX, OPSIZE and the ADSIZE prefix") \
143145
ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
144146
ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
145147
ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \

‎llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1330,7 +1330,8 @@ static int getInstructionID(struct InternalInstruction *insn,
13301330
// any position.
13311331
if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
13321332
(insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
1333-
(insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
1333+
(insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) ||
1334+
(insn->opcodeType == MAP4 && insn->opcode == 0xF8)) {
13341335
// Make sure we observed the prefixes in any position.
13351336
if (insn->hasAdSize)
13361337
attrMask |= ATTR_ADSIZE;

‎llvm/lib/Target/X86/X86InstrMisc.td‎

Lines changed: 20 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1497,11 +1497,19 @@ let SchedRW = [WriteStore] in {
14971497
def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
14981498
"movdiri\t{$src, $dst|$dst, $src}",
14991499
[(int_x86_directstore32 addr:$dst, GR32:$src)]>,
1500-
T8PS, Requires<[HasMOVDIRI]>;
1500+
T8PS, Requires<[HasMOVDIRI, NoEGPR]>;
15011501
def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
15021502
"movdiri\t{$src, $dst|$dst, $src}",
15031503
[(int_x86_directstore64 addr:$dst, GR64:$src)]>,
1504-
T8PS, Requires<[In64BitMode, HasMOVDIRI]>;
1504+
T8PS, Requires<[In64BitMode, HasMOVDIRI, NoEGPR]>;
1505+
def MOVDIRI32_EVEX : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1506+
"movdiri\t{$src, $dst|$dst, $src}",
1507+
[(int_x86_directstore32 addr:$dst, GR32:$src)]>,
1508+
EVEX_NoCD8, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
1509+
def MOVDIRI64_EVEX : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1510+
"movdiri\t{$src, $dst|$dst, $src}",
1511+
[(int_x86_directstore64 addr:$dst, GR64:$src)]>,
1512+
EVEX_NoCD8, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
15051513
} // SchedRW
15061514

15071515
//===----------------------------------------------------------------------===//
@@ -1514,11 +1522,19 @@ def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
15141522
def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
15151523
"movdir64b\t{$src, $dst|$dst, $src}",
15161524
[(int_x86_movdir64b GR32:$dst, addr:$src)]>,
1517-
T8PD, AdSize32, Requires<[HasMOVDIR64B]>;
1525+
T8PD, AdSize32, Requires<[HasMOVDIR64B, NoEGPR]>;
15181526
def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
15191527
"movdir64b\t{$src, $dst|$dst, $src}",
15201528
[(int_x86_movdir64b GR64:$dst, addr:$src)]>,
1521-
T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>;
1529+
T8PD, AdSize64, Requires<[HasMOVDIR64B, NoEGPR, In64BitMode]>;
1530+
def MOVDIR64B32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1531+
"movdir64b\t{$src, $dst|$dst, $src}",
1532+
[(int_x86_movdir64b GR32:$dst, addr:$src)]>,
1533+
EVEX_NoCD8, T_MAP4PD, AdSize32, Requires<[HasMOVDIR64B, HasEGPR, In64BitMode]>;
1534+
def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1535+
"movdir64b\t{$src, $dst|$dst, $src}",
1536+
[(int_x86_movdir64b GR64:$dst, addr:$src)]>,
1537+
EVEX_NoCD8, T_MAP4PD, AdSize64, Requires<[HasMOVDIR64B, HasEGPR, In64BitMode]>;
15221538
} // SchedRW
15231539

15241540
//===----------------------------------------------------------------------===//

‎llvm/test/MC/Disassembler/X86/apx/movdir64b.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: movdir64b 291(%r28d,%r29d,4), %r18d
5+
# INTEL: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
6+
0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
7+
8+
# ATT: movdir64b 291(%r28,%r29,4), %r19
9+
# INTEL: movdir64b r19, zmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/movdiri.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: movdiri %r18d, 291(%r28,%r29,4)
5+
# INTEL: movdiri dword ptr [r28 + 4*r29 + 291], r18d
6+
0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00
7+
8+
# ATT: movdiri %r19, 291(%r28,%r29,4)
9+
# INTEL: movdiri qword ptr [r28 + 4*r29 + 291], r19
10+
0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/X86/apx/movdir64b-att.s‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
3+
4+
# ERROR-COUNT-2: error:
5+
# ERROR-NOT: error:
6+
# CHECK: movdir64b 291(%r28d,%r29d,4), %r18d
7+
# CHECK: encoding: [0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
8+
movdir64b 291(%r28d,%r29d,4), %r18d
9+
10+
# CHECK: movdir64b 291(%r28,%r29,4), %r19
11+
# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
12+
movdir64b 291(%r28,%r29,4), %r19

‎llvm/test/MC/X86/apx/movdir64b-intel.s‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
4+
# CHECK: encoding: [0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
5+
movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
6+
7+
# CHECK: movdir64b r19, zmmword ptr [r28 + 4*r29 + 291]
8+
# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
9+
movdir64b r19, zmmword ptr [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/movdiri-att.s‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
3+
4+
# ERROR-COUNT-2: error:
5+
# ERROR-NOT: error:
6+
# CHECK: movdiri %r18d, 291(%r28,%r29,4)
7+
# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00]
8+
movdiri %r18d, 291(%r28,%r29,4)
9+
10+
# CHECK: movdiri %r19, 291(%r28,%r29,4)
11+
# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00]
12+
movdiri %r19, 291(%r28,%r29,4)

‎llvm/test/MC/X86/apx/movdiri-intel.s‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: movdiri dword ptr [r28 + 4*r29 + 291], r18d
4+
# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00]
5+
movdiri dword ptr [r28 + 4*r29 + 291], r18d
6+
7+
# CHECK: movdiri qword ptr [r28 + 4*r29 + 291], r19
8+
# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00]
9+
movdiri qword ptr [r28 + 4*r29 + 291], r19

‎llvm/utils/TableGen/X86DisassemblerTables.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,8 @@ static inline bool inheritsFrom(InstructionContext child,
213213
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE)) ||
214214
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
215215
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
216+
case IC_EVEX_OPSIZE_ADSIZE:
217+
return false;
216218
case IC_EVEX_K:
217219
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
218220
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_K)) ||
@@ -885,7 +887,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
885887
for (unsigned index = 0; index < ATTR_max; ++index) {
886888
o.indent(i * 2);
887889

888-
if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
890+
if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
891+
o << "IC_EVEX_OPSIZE_ADSIZE";
892+
else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
889893
if (index & ATTR_EVEX)
890894
o << "IC_EVEX";
891895
else
@@ -906,7 +910,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
906910
else if (index & ATTR_XS)
907911
o << "_XS";
908912

909-
if ((index & ATTR_EVEX)) {
913+
if (index & ATTR_EVEX) {
910914
if (index & ATTR_EVEXKZ)
911915
o << "_KZ";
912916
else if (index & ATTR_EVEXK)

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