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[AArch64] Add FeatureFuseCCSelect to a number of CPU configurations. (#153188)
This marks CMP+CSel as fusable according to the SWOGs of cortex-a78 cortex-a710 cortex-a715 cortex-a720 cortex-a725 cortex-x4 cortex-x925 neoverse-n2 neoverse-n3 neoverse-v1 neoverse-v2 neoverse-v3
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‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,7 @@ def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78",
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FeatureCmpBccFusion,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureAddrLSLSlow14,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
@@ -146,6 +147,7 @@ def TuneA78AE : SubtargetFeature<"a78ae", "ARMProcFamily",
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FeatureCmpBccFusion,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureAddrLSLSlow14,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
@@ -158,6 +160,7 @@ def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily",
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FeatureCmpBccFusion,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureAddrLSLSlow14,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
@@ -169,6 +172,7 @@ def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710",
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FeatureCmpBccFusion,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
@@ -181,6 +185,7 @@ def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715",
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FeatureCmpBccFusion,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive]>;
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@@ -191,6 +196,7 @@ def TuneA720 : SubtargetFeature<"a720", "ARMProcFamily", "CortexA720",
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FeatureCmpBccFusion,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive]>;
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@@ -201,6 +207,7 @@ def TuneA720AE : SubtargetFeature<"a720ae", "ARMProcFamily", "CortexA720",
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FeatureCmpBccFusion,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive]>;
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@@ -212,6 +219,7 @@ def TuneA725 : SubtargetFeature<"cortex-a725", "ARMProcFamily",
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FeatureCmpBccFusion,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive]>;
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@@ -262,6 +270,7 @@ def TuneX4 : SubtargetFeature<"cortex-x4", "ARMProcFamily", "CortexX4",
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"Cortex-X4 ARM processors", [
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureFuseAES,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
@@ -273,6 +282,7 @@ def TuneX925 : SubtargetFeature<"cortex-x925", "ARMProcFamily",
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"CortexX925", "Cortex-X925 ARM processors",[
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureFuseAES,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
@@ -548,6 +558,7 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2
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"Neoverse N2 ARM processors", [
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
@@ -559,6 +570,7 @@ def TuneNeoverseN3 : SubtargetFeature<"neoversen3", "ARMProcFamily", "NeoverseN3
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FeaturePostRAScheduler,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive]>;
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@@ -575,6 +587,7 @@ def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1
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"Neoverse V1 ARM processors", [
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureAddrLSLSlow14,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
@@ -587,6 +600,7 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2
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FeatureFuseAES,
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FeatureCmpBccFusion,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeatureALULSLFast,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
@@ -600,6 +614,7 @@ def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3
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FeatureFuseAES,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
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FeatureAvoidLDAPUR,
@@ -610,6 +625,7 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover
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FeatureFuseAES,
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FeatureALULSLFast,
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FeatureFuseAdrpAdd,
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FeatureFuseCCSelect,
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FeaturePostRAScheduler,
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FeatureEnableSelectOptimize,
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FeatureAvoidLDAPUR,

‎llvm/test/CodeGen/AArch64/misched-fusion-csel.ll

Lines changed: 38 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,42 @@
1-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-csel | FileCheck %s
2-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s
3-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s
4-
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s
1+
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-csel -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a710 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a715 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a720 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a725 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x4 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x925 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n2 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n3 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v1 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v2 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v3 -debug-only=machine-scheduler 2>&1 | FileCheck %s
17+
; REQUIRES: asserts
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6-
target triple = "aarch64-unknown"
19+
; Check that the scheduling model has an edge between the SUBS and the CSEL.
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; CHECK-LABEL: test_sub_cselw:%bb.0
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; CHECK: SU(2): %3:gpr32common = ADDWri %1:gpr32common, 7, 0
22+
; CHECK: SU(3): dead $wzr = SUBSWri %0:gpr32common, 13, 0, implicit-def $nzcv
23+
; CHECK: Successors:
24+
; CHECK: SU(4): Ord Latency=0 Cluster
25+
; CHECK: SU(4): %5:gpr32 = CSELWr %0:gpr32common, %3:gpr32common, 0, implicit killed $nzcv
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; CHECK: Predecessors:
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; CHECK: SU(3): Ord Latency=0 Cluster
28+
; CHECK: SU(5): $w0 = COPY %5:gpr32
29+
30+
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; CHECK-LABEL: test_sub_cselx:%bb.0
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; CHECK: SU(2): %3:gpr64common = ADDXri %1:gpr64common, 7, 0
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; CHECK: SU(3): dead $xzr = SUBSXri %0:gpr64common, 13, 0, implicit-def $nzcv
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; CHECK: Successors:
35+
; CHECK: SU(4): Ord Latency=0 Cluster
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; CHECK: SU(4): %5:gpr64 = CSELXr %0:gpr64common, %3:gpr64common, 0, implicit killed $nzcv
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; CHECK: Predecessors:
38+
; CHECK: SU(3): Ord Latency=0 Cluster
39+
; CHECK: SU(5): $x0 = COPY %5:gpr64
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841
define i32 @test_sub_cselw(i32 %a0, i32 %a1, i32 %a2) {
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entry:

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