Use a feature, switch to G_TRAP

Author: epilk

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -303,6 +303,12 @@ def FeatureMSAALoadDstSelBug : SubtargetFeature<"msaa-load-dst-sel-bug",
   "MSAA loads not honoring dst_sel bug"
 >;
 
+def FeaturePrivEnabledBug : SubtargetFeature<"priv-enabled-bug",
+  "HasPrivEnabledBug",
+  "true",
+  "Hardware that runs with PRIV=1 workaround"
+>;
+
 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
   "ldsbankcount"#Value,
   "LDSBankCount",
@@ -1489,7 +1495,8 @@ def FeatureISAVersion11_0_Common : FeatureSet<
   !listconcat(FeatureISAVersion11_Common.Features,
     [FeatureMSAALoadDstSelBug,
      FeatureVALUTransUseHazard,
-     FeatureMADIntraFwdBug])>;
+     FeatureMADIntraFwdBug,
+     FeaturePrivEnabledBug])>;
 
 def FeatureISAVersion11_0_0 : FeatureSet<
   !listconcat(FeatureISAVersion11_0_Common.Features,

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

@@ -6727,7 +6727,9 @@ bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(
 bool AMDGPULegalizerInfo::legalizeTrapHsa(MachineInstr &MI,
                                           MachineRegisterInfo &MRI,
                                           MachineIRBuilder &B) const {
-  if (ST.requiresSimulatedTrap()) {
+  // We need to simulate the 's_trap 2' instruction on targets that run in
+  // PRIV=1 (where it is treated as a nop).
+  if (ST.hasPrivEnabledBug()) {
     ST.getInstrInfo()->insertSimulatedTrap(MRI, B.getMBB(), MI,
                                            MI.getDebugLoc());
     MI.eraseFromParent();

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -23,7 +23,6 @@
 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/TargetParser/TargetParser.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "AMDGPUGenSubtargetInfo.inc"
@@ -224,6 +223,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   bool HasImageStoreD16Bug = false;
   bool HasImageGather4D16Bug = false;
   bool HasMSAALoadDstSelBug = false;
+  bool HasPrivEnabledBug = false;
   bool Has1_5xVGPRs = false;
   bool HasMADIntraFwdBug = false;
   bool HasVOPDInsts = false;
@@ -444,13 +444,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
     return isAmdHsaOS() ? TrapHandlerAbi::AMDHSA : TrapHandlerAbi::NONE;
   }
 
-  // True on hardware where 's_trap 2' is treated as a nop that must be
-  // simulated.
-  bool requiresSimulatedTrap() const {
-    AMDGPU::IsaVersion V = AMDGPU::getIsaVersion(getCPU());
-    return V.Major == 11 && V.Minor <= 3;
-  }
-
   bool supportsGetDoorbellID() const {
     // The S_GETREG DOORBELL_ID is supported by all GFX9 onward targets.
     return getGeneration() >= GFX9;
@@ -1034,6 +1027,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
 
   bool hasMSAALoadDstSelBug() const { return HasMSAALoadDstSelBug; }
 
+  bool hasPrivEnabledBug() const { return HasPrivEnabledBug; }
+
   bool hasNSAEncoding() const { return HasNSAEncoding; }
 
   bool hasNonNSAEncoding() const { return getGeneration() < GFX12; }

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5410,7 +5410,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
     return SplitBB;
   }
   case AMDGPU::SIMULATED_TRAP: {
-    assert(Subtarget->requiresSimulatedTrap());
+    assert(Subtarget->hasPrivEnabledBug());
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
     MachineBasicBlock *SplitBB =
         TII->insertSimulatedTrap(MRI, *BB, MI, MI.getDebugLoc());
@@ -6635,7 +6635,9 @@ SDValue SITargetLowering::lowerTrapHsa(
   SDLoc SL(Op);
   SDValue Chain = Op.getOperand(0);
 
-  if (Subtarget->requiresSimulatedTrap())
+  // We need to simulate the 's_trap 2' instruction on targets that run in
+  // PRIV=1 (where it is treated as a nop).
+  if (Subtarget->hasPrivEnabledBug())
     return DAG.getNode(AMDGPUISD::SIMULATED_TRAP, SL, MVT::Other, Chain);
 
   uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir

@@ -42,7 +42,7 @@ body: |
     %0:_(s8) = G_CONSTANT i8 0
     %1:_(p1) = G_CONSTANT i64 0
     G_STORE %0, %1 :: (store 1, addrspace 1)
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+    G_TRAP
     G_STORE %0, %1 :: (store 1, addrspace 1)
 
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