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[AArch64] Add the Ampere1B core
The Ampere1B is Ampere's third-generation core implementing a superscalar, out-of-order microarchitecture with nested virtualization, speculative side-channel mitigation and architectural support for defense against ROP/JOP style software attacks. Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all features of the second-generation Ampere1A, such as the Memory Tagging Extension and SM3/SM4 cryptography instructions. Signed-off-by: Philipp Tomsich <[email protected]>
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‎clang/test/Driver/aarch64-cssc.c

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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+cssc %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -mcpu=ampere1b %s 2>&1 | FileCheck %s
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// CHECK: "target-features"="{{.*}},+cssc
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// NO_CSSC: "target-features"="{{.*}},-cssc

‎clang/test/Misc/target-invalid-cpu-note.c

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// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
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// AARCH64: error: unknown target CPU 'not-a-cpu'
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// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
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// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
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// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
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// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
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// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
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// X86: error: unknown target CPU 'not-a-cpu'

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

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@@ -805,6 +805,12 @@ inline constexpr CpuInfo CpuInfos[] = {
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{AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4,
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AArch64::AEK_SHA3, AArch64::AEK_SHA2, AArch64::AEK_AES,
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AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS}))},
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{"ampere1b", ARMV8_7A,
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(AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_RAND,
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AArch64::AEK_SM4, AArch64::AEK_SHA3,
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AArch64::AEK_SHA2, AArch64::AEK_AES,
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AArch64::AEK_MTE, AArch64::AEK_SB,
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AArch64::AEK_SSBS, AArch64::AEK_CSSC}))},
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};
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// An alias for a CPU.

‎llvm/lib/Target/AArch64/AArch64.td

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@@ -1376,6 +1376,24 @@ def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
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FeatureLdpAlignedOnly,
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FeatureStpAlignedOnly]>;
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def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B",
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"Ampere Computing Ampere-1B processors", [
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FeaturePostRAScheduler,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureAddrLSLFast,
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FeatureALULSLFast,
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FeatureAggressiveFMA,
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FeatureArithmeticBccFusion,
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FeatureCmpBccFusion,
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FeatureFuseAddress,
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FeatureFuseLiterals,
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FeatureStorePairSuppress,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive,
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FeatureLdpAlignedOnly,
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FeatureStpAlignedOnly]>;
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def ProcessorFeatures {
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list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
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FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
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FeatureMTE, FeatureSSBS, FeatureRandGen,
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FeatureSB, FeatureSM4, FeatureSHA2,
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FeatureSHA3, FeatureAES];
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list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
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FeatureMTE, FeatureSSBS, FeatureRandGen,
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FeatureSB, FeatureSM4, FeatureSHA2,
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FeatureSHA3, FeatureAES, FeatureCSSC,
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FeatureWFxT];
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// ETE and TRBE are future architecture extensions. We temporarily enable them
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// by default for users targeting generic AArch64. The extensions do not
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def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
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[TuneAmpere1A]>;
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def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
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[TuneAmpere1B]>;
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

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break;
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case Ampere1:
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case Ampere1A:
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case Ampere1B:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(64);
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PrefLoopAlignment = Align(64);

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

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A64FX,
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Ampere1,
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Ampere1A,
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Ampere1B,
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AppleA7,
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AppleA10,
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AppleA11,

‎llvm/lib/TargetParser/Host.cpp

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return StringSwitch<const char *>(Part)
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.Case("0xac3", "ampere1")
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.Case("0xac4", "ampere1a")
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.Case("0xac5", "ampere1b")
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.Default("generic");
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}
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‎llvm/test/CodeGen/AArch64/cpus.ll

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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1a 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1b 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
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; CHECK-NOT: {{.*}} is not a recognized processor for this target

‎llvm/test/CodeGen/AArch64/neon-dot-product.ll

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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1a < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1b < %s | FileCheck %s
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declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)

‎llvm/test/CodeGen/AArch64/remat.ll

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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1a -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1b -o - %s | FileCheck %s
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%X = type { i64, i64, i64 }
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declare void @f(ptr)

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