Skip to content

Commit 2252cac

Browse files
jayfoadjayfoad
committed
[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr
Summary: This enables clustering for many more BUF instructions. Reviewers: rampitec, arsenm, nhaehnle Subscribers: jvesely, wdng, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73868
1 parent 2ddff6f commit 2252cac

File tree

10 files changed

+157
-153
lines changed

10 files changed

+157
-153
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -337,13 +337,15 @@ bool SIInstrInfo::getMemOperandsWithOffset(
337337
return true;
338338
}
339339

340-
BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
341-
if (!BaseOp)
340+
BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
341+
if (!BaseOp) // e.g. BUFFER_WBINVL1_VOL
342342
return false;
343-
const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
344-
BaseOps.push_back(RSrc);
345343
BaseOps.push_back(BaseOp);
346344

345+
BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
346+
if (BaseOp)
347+
BaseOps.push_back(BaseOp);
348+
347349
const MachineOperand *OffsetImm =
348350
getNamedOperand(LdSt, AMDGPU::OpName::offset);
349351
Offset = OffsetImm->getImm();

‎llvm/test/CodeGen/AMDGPU/bswap.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -668,7 +668,7 @@ define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
668668
; VI-NEXT: s_lshl_b32 s6, s6, 8
669669
; VI-NEXT: s_or_b32 s4, s6, s4
670670
; VI-NEXT: v_or_b32_e32 v1, v1, v3
671-
; VI-NEXT: v_or_b32_e32 v5, s4, v1
671+
; VI-NEXT: v_or_b32_e32 v6, s4, v1
672672
; VI-NEXT: v_mov_b32_e32 v1, s8
673673
; VI-NEXT: v_alignbit_b32 v3, s9, v1, 24
674674
; VI-NEXT: v_alignbit_b32 v1, s9, v1, 8
@@ -678,11 +678,11 @@ define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
678678
; VI-NEXT: v_and_b32_e32 v1, s17, v1
679679
; VI-NEXT: s_lshr_b32 s4, s9, 24
680680
; VI-NEXT: s_lshl_b32 s6, s6, 8
681-
; VI-NEXT: s_and_b32 s13, s15, s18
682-
; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 24
683681
; VI-NEXT: v_or_b32_e32 v1, v1, v3
684682
; VI-NEXT: s_or_b32 s4, s6, s4
685-
; VI-NEXT: v_or_b32_e32 v3, s4, v1
683+
; VI-NEXT: s_and_b32 s13, s15, s18
684+
; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 24
685+
; VI-NEXT: v_or_b32_e32 v4, s4, v1
686686
; VI-NEXT: s_lshl_b32 s4, s10, 8
687687
; VI-NEXT: s_and_b32 s15, s15, s19
688688
; VI-NEXT: s_mov_b32 s14, s12
@@ -704,11 +704,11 @@ define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i
704704
; VI-NEXT: s_mov_b32 s8, s12
705705
; VI-NEXT: s_or_b64 s[8:9], s[12:13], s[8:9]
706706
; VI-NEXT: s_or_b64 s[8:9], s[8:9], s[14:15]
707-
; VI-NEXT: v_mov_b32_e32 v4, s9
708-
; VI-NEXT: v_mov_b32_e32 v6, s11
709-
; VI-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:16
707+
; VI-NEXT: v_mov_b32_e32 v5, s9
708+
; VI-NEXT: v_mov_b32_e32 v7, s11
710709
; VI-NEXT: v_mov_b32_e32 v1, s5
711710
; VI-NEXT: v_mov_b32_e32 v3, s7
711+
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
712712
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
713713
; VI-NEXT: s_endpgm
714714
%val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32

‎llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -437,9 +437,9 @@ define amdgpu_kernel void @test_copy_v3i8_align4(<3 x i8> addrspace(1)* %out, <3
437437
; VI-NEXT: s_mov_b32 s4, s0
438438
; VI-NEXT: s_mov_b32 s5, s1
439439
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
440+
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
440441
; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
441-
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
442-
; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 offset:2
442+
; VI-NEXT: buffer_store_byte v1, off, s[4:7], 0 offset:2
443443
; VI-NEXT: s_endpgm
444444
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
445445
%gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid.x

‎llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -172,13 +172,19 @@ define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(i32 addrspace(1)* n
172172
; SI-NOSDWA: v_or_b32_e32
173173
; SI-NOSDWA: v_or_b32_e32
174174
; SI-NOSDWA: v_or_b32_e32
175-
; SI-SDWA: v_or_b32_sdwa
176175
; SI-NOSDWA: v_or_b32_e32
176+
; SI-NOSDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
177+
; SI-NOSDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
178+
; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
179+
; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
180+
; SI-SDWA: v_or_b32_e32
181+
; SI-SDWA: v_or_b32_sdwa
182+
; SI-SDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
183+
; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
184+
; SI-SDWA: v_or_b32_e32
177185
; SI-SDWA: v_or_b32_sdwa
178-
; SI: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
179-
; SI: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
180-
; SI-DAG: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
181-
; SI-DAG: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
186+
; SI-SDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
187+
; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
182188
; SI: v_cmp_eq_u32_e32 vcc, 0
183189
; SI: v_cmp_ne_u64_e32 vcc, 0
184190
; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]

‎llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll‎

Lines changed: 20 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -365,35 +365,34 @@ define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias
365365
; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
366366
; SI-NEXT: v_mov_b32_e32 v1, 0
367367
; SI-NEXT: s_waitcnt lgkmcnt(0)
368-
; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
369-
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
370-
; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:2
371-
; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:3
372-
; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:4
373-
; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:5
374-
; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:6
368+
; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64 offset:5
369+
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:6
370+
; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64
371+
; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:1
372+
; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:2
373+
; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:3
374+
; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 offset:4
375375
; SI-NEXT: s_mov_b32 s6, -1
376-
; SI-NEXT: s_waitcnt vmcnt(5)
377-
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v3
378-
; SI-NEXT: v_or_b32_e32 v1, v1, v2
376+
; SI-NEXT: s_waitcnt vmcnt(6)
377+
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
379378
; SI-NEXT: s_waitcnt vmcnt(3)
380-
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
381-
; SI-NEXT: v_or_b32_e32 v2, v2, v4
379+
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
380+
; SI-NEXT: v_or_b32_e32 v1, v1, v4
382381
; SI-NEXT: s_waitcnt vmcnt(1)
383-
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v7
382+
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v7
383+
; SI-NEXT: v_cvt_f32_ubyte0_e32 v7, v3
384+
; SI-NEXT: v_or_b32_e32 v3, v5, v6
384385
; SI-NEXT: s_waitcnt vmcnt(0)
385-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
386-
; SI-NEXT: v_or_b32_e32 v3, v3, v6
387-
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:24
388-
; SI-NEXT: s_waitcnt expcnt(0)
389-
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
390-
; SI-NEXT: v_or_b32_e32 v0, v0, v1
391-
; SI-NEXT: v_cvt_f32_ubyte1_e32 v5, v3
392-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v3
386+
; SI-NEXT: v_or_b32_e32 v0, v2, v0
387+
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
388+
; SI-NEXT: v_cvt_f32_ubyte1_e32 v5, v0
389+
; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v0
390+
; SI-NEXT: v_or_b32_e32 v0, v2, v1
393391
; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
394392
; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
395393
; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
396394
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
395+
; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:24
397396
; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
398397
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
399398
; SI-NEXT: s_endpgm

‎llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -911,9 +911,9 @@ define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %
911911
; SI-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
912912
; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
913913
; SI-NEXT: v_mov_b32_e32 v0, s5
914+
; SI-NEXT: v_mov_b32_e32 v1, s4
914915
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
915-
; SI-NEXT: v_mov_b32_e32 v0, s4
916-
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
916+
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
917917
; SI-NEXT: s_endpgm
918918
;
919919
; VI-LABEL: dynamic_insertelement_v3i16:

‎llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -348,7 +348,7 @@ define amdgpu_kernel void @test_memcpy_const_string_align4(i8 addrspace(1)* noal
348348

349349
; FUNC-LABEL: {{^}}test_memcpy_const_string_align1:
350350
; SI-NOT: buffer_load
351-
; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x69
351+
; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x
352352
; SI: buffer_store_byte
353353
; SI: buffer_store_byte
354354
; SI: buffer_store_byte

‎llvm/test/CodeGen/AMDGPU/merge-stores.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -529,8 +529,8 @@ define amdgpu_kernel void @merge_local_store_4_constants_i32(i32 addrspace(3)* %
529529
; GCN-LABEL: {{^}}merge_global_store_5_constants_i32:
530530
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 9{{$}}
531531
; GCN-DAG: v_mov_b32_e32 v[[HI4:[0-9]+]], -12{{$}}
532-
; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI4]]{{\]}}
533532
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 11{{$}}
533+
; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI4]]{{\]}}
534534
; GCN: buffer_store_dword v[[HI]]
535535
define amdgpu_kernel void @merge_global_store_5_constants_i32(i32 addrspace(1)* %out) {
536536
store i32 9, i32 addrspace(1)* %out, align 4

0 commit comments

Comments
 (0)