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[AMDGPU] Port amdgpu-isel to new pass manager
1 parent f6ceec4 commit 1fd885b

33 files changed

+77
-9
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,9 @@
77
//===----------------------------------------------------------------------===//
88

99
#include "AMDGPUCodeGenPassBuilder.h"
10+
#include "AMDGPUISelDAGToDAG.h"
1011
#include "AMDGPUTargetMachine.h"
12+
#include "llvm/Analysis/UniformityAnalysis.h"
1113

1214
using namespace llvm;
1315

@@ -25,14 +27,16 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
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2628
void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const {
2729
// TODO: Add passes pre instruction selection.
30+
// Test only, convert to real IR passes in future.
31+
addPass(RequireAnalysisPass<UniformityInfoAnalysis, Function>());
2832
}
2933

3034
void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
3135
CreateMCStreamer) const {
3236
// TODO: Add AsmPrinter.
3337
}
3438

35-
Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &) const {
36-
// TODO: Add instruction selector.
39+
Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
40+
addPass(AMDGPUISelDAGToDAGPass(TM));
3741
return Error::success();
3842
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -777,6 +777,10 @@ StringRef AMDGPUDAGToDAGISelLegacy::getPassName() const {
777777
return "AMDGPU DAG->DAG Pattern Instruction Selection";
778778
}
779779

780+
AMDGPUISelDAGToDAGPass::AMDGPUISelDAGToDAGPass(TargetMachine &TM)
781+
: SelectionDAGISelPass(
782+
std::make_unique<AMDGPUDAGToDAGISel>(TM, TM.getOptLevel())) {}
783+
780784
//===----------------------------------------------------------------------===//
781785
// Complex Patterns
782786
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -280,6 +280,11 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
280280
#include "AMDGPUGenDAGISel.inc"
281281
};
282282

283+
class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {
284+
public:
285+
AMDGPUISelDAGToDAGPass(TargetMachine &TM);
286+
};
287+
283288
class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
284289
public:
285290
static char ID;

‎llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,3 +71,9 @@ FUNCTION_PASS_WITH_PARAMS(
7171
},
7272
parseAMDGPUAtomicOptimizerStrategy, "strategy=dpp|iterative|none")
7373
#undef FUNCTION_PASS_WITH_PARAMS
74+
75+
#ifndef MACHINE_FUNCTION_PASS
76+
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
77+
#endif
78+
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
79+
#undef MACHINE_FUNCTION_PASS

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "AMDGPUCtorDtorLowering.h"
2020
#include "AMDGPUExportClustering.h"
2121
#include "AMDGPUIGroupLP.h"
22+
#include "AMDGPUISelDAGToDAG.h"
2223
#include "AMDGPUMacroFusion.h"
2324
#include "AMDGPURegBankSelect.h"
2425
#include "AMDGPUTargetObjectFile.h"

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3074,9 +3074,10 @@ SDValue SITargetLowering::LowerFormalArguments(
30743074
if (IsEntryFunc)
30753075
allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
30763076

3077-
auto &ArgUsageInfo =
3078-
DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
3079-
ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
3077+
if (DAG.getPass()) {
3078+
auto &ArgUsageInfo = DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
3079+
ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
3080+
}
30803081

30813082
unsigned StackArgSize = CCInfo.getStackSize();
30823083
Info->setBytesInStackArgArea(StackArgSize);
@@ -3288,9 +3289,11 @@ void SITargetLowering::passSpecialInputs(
32883289
const AMDGPUFunctionArgInfo *CalleeArgInfo
32893290
= &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
32903291
if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) {
3291-
auto &ArgUsageInfo =
3292-
DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
3293-
CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
3292+
if (DAG.getPass()) {
3293+
auto &ArgUsageInfo =
3294+
DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
3295+
CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
3296+
}
32943297
}
32953298

32963299
// TODO: Unify with private memory register handling. This is complicated by

‎llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,10 @@
33
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
44
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
55
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908_GFX11 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908_GFX11 %s
7+
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
8+
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
9+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908_GFX11 %s
610

711
define amdgpu_ps void @buffer_atomic_fadd_f32_offset_no_rtn(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
812
; GFX908_GFX11-LABEL: name: buffer_atomic_fadd_f32_offset_no_rtn

‎llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,10 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
33
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
4-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
7+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
58

69
define amdgpu_ps float @buffer_atomic_fadd_f32_offset_rtn(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
710
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_f32_offset_rtn

‎llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
33
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
46

57
define amdgpu_ps void @buffer_atomic_fadd_f64_offset_no_rtn(double %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
68
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_f64_offset_no_rtn

‎llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,9 @@
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908 %s
33
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
44
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908 %s
6+
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
7+
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
58

69
define amdgpu_ps void @buffer_atomic_fadd_v2f16_offset_no_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
710
; GFX908-LABEL: name: buffer_atomic_fadd_v2f16_offset_no_rtn

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