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Revert "[LoongArch] Remove spurious mask operations from andn->icmp on 16 and 8 bit values" (#99792)
Reverts #99272
1 parent b828c13 commit 1d5d189

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2 files changed

+40
-178
lines changed

2 files changed

+40
-178
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp‎

Lines changed: 0 additions & 162 deletions
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
335335
setTargetDAGCombine(ISD::AND);
336336
setTargetDAGCombine(ISD::OR);
337337
setTargetDAGCombine(ISD::SRL);
338-
setTargetDAGCombine(ISD::SETCC);
339338

340339
// Set DAG combine for 'LSX' feature.
341340

@@ -2529,165 +2528,6 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
25292528
return SDValue();
25302529
}
25312530

2532-
static bool checkValueWidth(SDValue V, ISD::LoadExtType &ExtType) {
2533-
ExtType = ISD::NON_EXTLOAD;
2534-
2535-
switch (V.getNode()->getOpcode()) {
2536-
case ISD::LOAD: {
2537-
LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
2538-
if ((LoadNode->getMemoryVT() == MVT::i8) ||
2539-
(LoadNode->getMemoryVT() == MVT::i16)) {
2540-
ExtType = LoadNode->getExtensionType();
2541-
return true;
2542-
}
2543-
return false;
2544-
}
2545-
case ISD::AssertSext: {
2546-
VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
2547-
if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) {
2548-
ExtType = ISD::SEXTLOAD;
2549-
return true;
2550-
}
2551-
return false;
2552-
}
2553-
case ISD::AssertZext: {
2554-
VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
2555-
if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) {
2556-
ExtType = ISD::ZEXTLOAD;
2557-
return true;
2558-
}
2559-
return false;
2560-
}
2561-
default:
2562-
return false;
2563-
}
2564-
2565-
return false;
2566-
}
2567-
2568-
// Eliminate redundant truncation and zero-extension nodes.
2569-
// * Case 1:
2570-
// +------------+ +------------+ +------------+
2571-
// | Input1 | | Input2 | | CC |
2572-
// +------------+ +------------+ +------------+
2573-
// | | |
2574-
// V V +----+
2575-
// +------------+ +------------+ |
2576-
// | TRUNCATE | | TRUNCATE | |
2577-
// +------------+ +------------+ |
2578-
// | | |
2579-
// V V |
2580-
// +------------+ +------------+ |
2581-
// | ZERO_EXT | | ZERO_EXT | |
2582-
// +------------+ +------------+ |
2583-
// | | |
2584-
// | +-------------+ |
2585-
// V V | |
2586-
// +----------------+ | |
2587-
// | AND | | |
2588-
// +----------------+ | |
2589-
// | | |
2590-
// +---------------+ | |
2591-
// | | |
2592-
// V V V
2593-
// +-------------+
2594-
// | CMP |
2595-
// +-------------+
2596-
// * Case 2:
2597-
// +------------+ +------------+ +-------------+ +------------+ +------------+
2598-
// | Input1 | | Input2 | | Constant -1 | | Constant 0 | | CC |
2599-
// +------------+ +------------+ +-------------+ +------------+ +------------+
2600-
// | | | | |
2601-
// V | | | |
2602-
// +------------+ | | | |
2603-
// | XOR |<---------------------+ | |
2604-
// +------------+ | | |
2605-
// | | | |
2606-
// V V +---------------+ |
2607-
// +------------+ +------------+ | |
2608-
// | TRUNCATE | | TRUNCATE | | +-------------------------+
2609-
// +------------+ +------------+ | |
2610-
// | | | |
2611-
// V V | |
2612-
// +------------+ +------------+ | |
2613-
// | ZERO_EXT | | ZERO_EXT | | |
2614-
// +------------+ +------------+ | |
2615-
// | | | |
2616-
// V V | |
2617-
// +----------------+ | |
2618-
// | AND | | |
2619-
// +----------------+ | |
2620-
// | | |
2621-
// +---------------+ | |
2622-
// | | |
2623-
// V V V
2624-
// +-------------+
2625-
// | CMP |
2626-
// +-------------+
2627-
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
2628-
TargetLowering::DAGCombinerInfo &DCI,
2629-
const LoongArchSubtarget &Subtarget) {
2630-
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2631-
2632-
SDNode *AndNode = N->getOperand(0).getNode();
2633-
if (AndNode->getOpcode() != ISD::AND)
2634-
return SDValue();
2635-
2636-
SDValue AndInputValue2 = AndNode->getOperand(1);
2637-
if (AndInputValue2.getOpcode() != ISD::ZERO_EXTEND)
2638-
return SDValue();
2639-
2640-
SDValue CmpInputValue = N->getOperand(1);
2641-
SDValue AndInputValue1 = AndNode->getOperand(0);
2642-
if (AndInputValue1.getOpcode() == ISD::XOR) {
2643-
if (CC != ISD::SETEQ && CC != ISD::SETNE)
2644-
return SDValue();
2645-
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndInputValue1.getOperand(1));
2646-
if (!CN || CN->getSExtValue() != -1)
2647-
return SDValue();
2648-
CN = dyn_cast<ConstantSDNode>(CmpInputValue);
2649-
if (!CN || CN->getSExtValue() != 0)
2650-
return SDValue();
2651-
AndInputValue1 = AndInputValue1.getOperand(0);
2652-
if (AndInputValue1.getOpcode() != ISD::ZERO_EXTEND)
2653-
return SDValue();
2654-
} else if (AndInputValue1.getOpcode() == ISD::ZERO_EXTEND) {
2655-
if (AndInputValue2 != CmpInputValue)
2656-
return SDValue();
2657-
} else {
2658-
return SDValue();
2659-
}
2660-
2661-
SDValue TruncValue1 = AndInputValue1.getNode()->getOperand(0);
2662-
if (TruncValue1.getOpcode() != ISD::TRUNCATE)
2663-
return SDValue();
2664-
2665-
SDValue TruncValue2 = AndInputValue2.getNode()->getOperand(0);
2666-
if (TruncValue2.getOpcode() != ISD::TRUNCATE)
2667-
return SDValue();
2668-
2669-
SDValue TruncInputValue1 = TruncValue1.getNode()->getOperand(0);
2670-
SDValue TruncInputValue2 = TruncValue2.getNode()->getOperand(0);
2671-
ISD::LoadExtType ExtType1;
2672-
ISD::LoadExtType ExtType2;
2673-
2674-
if (!checkValueWidth(TruncInputValue1, ExtType1) ||
2675-
!checkValueWidth(TruncInputValue2, ExtType2))
2676-
return SDValue();
2677-
2678-
if ((ExtType2 != ISD::ZEXTLOAD) &&
2679-
((ExtType2 != ISD::SEXTLOAD) && (ExtType1 != ISD::SEXTLOAD)))
2680-
return SDValue();
2681-
2682-
// These truncation and zero-extension nodes are not necessary, remove them.
2683-
SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N), AndNode->getValueType(0),
2684-
TruncInputValue1, TruncInputValue2);
2685-
SDValue NewSetCC =
2686-
DAG.getSetCC(SDLoc(N), N->getValueType(0), NewAnd, TruncInputValue2, CC);
2687-
DAG.ReplaceAllUsesWith(N, NewSetCC.getNode());
2688-
return SDValue(N, 0);
2689-
}
2690-
26912531
// Combine (loongarch_bitrev_w (loongarch_revb_2w X)) to loongarch_bitrev_4b.
26922532
static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG,
26932533
TargetLowering::DAGCombinerInfo &DCI,
@@ -3315,8 +3155,6 @@ SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N,
33153155
return performANDCombine(N, DAG, DCI, Subtarget);
33163156
case ISD::OR:
33173157
return performORCombine(N, DAG, DCI, Subtarget);
3318-
case ISD::SETCC:
3319-
return performSETCCCombine(N, DAG, DCI, Subtarget);
33203158
case ISD::SRL:
33213159
return performSRLCombine(N, DAG, DCI, Subtarget);
33223160
case LoongArchISD::BITREV_W:

‎llvm/test/CodeGen/LoongArch/andn-icmp.ll‎

Lines changed: 40 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,14 @@ define i1 @andn_icmp_eq_i8(i8 signext %a, i8 signext %b) nounwind {
66
; LA32-LABEL: andn_icmp_eq_i8:
77
; LA32: # %bb.0:
88
; LA32-NEXT: andn $a0, $a1, $a0
9+
; LA32-NEXT: andi $a0, $a0, 255
910
; LA32-NEXT: sltui $a0, $a0, 1
1011
; LA32-NEXT: ret
1112
;
1213
; LA64-LABEL: andn_icmp_eq_i8:
1314
; LA64: # %bb.0:
1415
; LA64-NEXT: andn $a0, $a1, $a0
16+
; LA64-NEXT: andi $a0, $a0, 255
1517
; LA64-NEXT: sltui $a0, $a0, 1
1618
; LA64-NEXT: ret
1719
%and = and i8 %a, %b
@@ -23,12 +25,14 @@ define i1 @andn_icmp_eq_i16(i16 signext %a, i16 signext %b) nounwind {
2325
; LA32-LABEL: andn_icmp_eq_i16:
2426
; LA32: # %bb.0:
2527
; LA32-NEXT: andn $a0, $a1, $a0
28+
; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
2629
; LA32-NEXT: sltui $a0, $a0, 1
2730
; LA32-NEXT: ret
2831
;
2932
; LA64-LABEL: andn_icmp_eq_i16:
3033
; LA64: # %bb.0:
3134
; LA64-NEXT: andn $a0, $a1, $a0
35+
; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
3236
; LA64-NEXT: sltui $a0, $a0, 1
3337
; LA64-NEXT: ret
3438
%and = and i16 %a, %b
@@ -76,12 +80,14 @@ define i1 @andn_icmp_ne_i8(i8 signext %a, i8 signext %b) nounwind {
7680
; LA32-LABEL: andn_icmp_ne_i8:
7781
; LA32: # %bb.0:
7882
; LA32-NEXT: andn $a0, $a1, $a0
83+
; LA32-NEXT: andi $a0, $a0, 255
7984
; LA32-NEXT: sltu $a0, $zero, $a0
8085
; LA32-NEXT: ret
8186
;
8287
; LA64-LABEL: andn_icmp_ne_i8:
8388
; LA64: # %bb.0:
8489
; LA64-NEXT: andn $a0, $a1, $a0
90+
; LA64-NEXT: andi $a0, $a0, 255
8591
; LA64-NEXT: sltu $a0, $zero, $a0
8692
; LA64-NEXT: ret
8793
%and = and i8 %a, %b
@@ -93,12 +99,14 @@ define i1 @andn_icmp_ne_i16(i16 signext %a, i16 signext %b) nounwind {
9399
; LA32-LABEL: andn_icmp_ne_i16:
94100
; LA32: # %bb.0:
95101
; LA32-NEXT: andn $a0, $a1, $a0
102+
; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
96103
; LA32-NEXT: sltu $a0, $zero, $a0
97104
; LA32-NEXT: ret
98105
;
99106
; LA64-LABEL: andn_icmp_ne_i16:
100107
; LA64: # %bb.0:
101108
; LA64-NEXT: andn $a0, $a1, $a0
109+
; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
102110
; LA64-NEXT: sltu $a0, $zero, $a0
103111
; LA64-NEXT: ret
104112
%and = and i16 %a, %b
@@ -145,13 +153,15 @@ define i1 @andn_icmp_ne_i64(i64 %a, i64 %b) nounwind {
145153
define i1 @andn_icmp_ult_i8(i8 signext %a, i8 signext %b) nounwind {
146154
; LA32-LABEL: andn_icmp_ult_i8:
147155
; LA32: # %bb.0:
148-
; LA32-NEXT: and $a0, $a0, $a1
156+
; LA32-NEXT: andi $a1, $a1, 255
157+
; LA32-NEXT: and $a0, $a1, $a0
149158
; LA32-NEXT: sltu $a0, $a0, $a1
150159
; LA32-NEXT: ret
151160
;
152161
; LA64-LABEL: andn_icmp_ult_i8:
153162
; LA64: # %bb.0:
154-
; LA64-NEXT: and $a0, $a0, $a1
163+
; LA64-NEXT: andi $a1, $a1, 255
164+
; LA64-NEXT: and $a0, $a1, $a0
155165
; LA64-NEXT: sltu $a0, $a0, $a1
156166
; LA64-NEXT: ret
157167
%and = and i8 %a, %b
@@ -162,13 +172,15 @@ define i1 @andn_icmp_ult_i8(i8 signext %a, i8 signext %b) nounwind {
162172
define i1 @andn_icmp_ult_i16(i16 signext %a, i16 signext %b) nounwind {
163173
; LA32-LABEL: andn_icmp_ult_i16:
164174
; LA32: # %bb.0:
165-
; LA32-NEXT: and $a0, $a0, $a1
175+
; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
176+
; LA32-NEXT: and $a0, $a1, $a0
166177
; LA32-NEXT: sltu $a0, $a0, $a1
167178
; LA32-NEXT: ret
168179
;
169180
; LA64-LABEL: andn_icmp_ult_i16:
170181
; LA64: # %bb.0:
171-
; LA64-NEXT: and $a0, $a0, $a1
182+
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
183+
; LA64-NEXT: and $a0, $a1, $a0
172184
; LA64-NEXT: sltu $a0, $a0, $a1
173185
; LA64-NEXT: ret
174186
%and = and i16 %a, %b
@@ -179,14 +191,16 @@ define i1 @andn_icmp_ult_i16(i16 signext %a, i16 signext %b) nounwind {
179191
define i1 @andn_icmp_uge_i8(i8 signext %a, i8 signext %b) nounwind {
180192
; LA32-LABEL: andn_icmp_uge_i8:
181193
; LA32: # %bb.0:
182-
; LA32-NEXT: and $a0, $a0, $a1
194+
; LA32-NEXT: andi $a1, $a1, 255
195+
; LA32-NEXT: and $a0, $a1, $a0
183196
; LA32-NEXT: sltu $a0, $a0, $a1
184197
; LA32-NEXT: xori $a0, $a0, 1
185198
; LA32-NEXT: ret
186199
;
187200
; LA64-LABEL: andn_icmp_uge_i8:
188201
; LA64: # %bb.0:
189-
; LA64-NEXT: and $a0, $a0, $a1
202+
; LA64-NEXT: andi $a1, $a1, 255
203+
; LA64-NEXT: and $a0, $a1, $a0
190204
; LA64-NEXT: sltu $a0, $a0, $a1
191205
; LA64-NEXT: xori $a0, $a0, 1
192206
; LA64-NEXT: ret
@@ -198,14 +212,16 @@ define i1 @andn_icmp_uge_i8(i8 signext %a, i8 signext %b) nounwind {
198212
define i1 @andn_icmp_uge_i16(i16 signext %a, i16 signext %b) nounwind {
199213
; LA32-LABEL: andn_icmp_uge_i16:
200214
; LA32: # %bb.0:
201-
; LA32-NEXT: and $a0, $a0, $a1
215+
; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
216+
; LA32-NEXT: and $a0, $a1, $a0
202217
; LA32-NEXT: sltu $a0, $a0, $a1
203218
; LA32-NEXT: xori $a0, $a0, 1
204219
; LA32-NEXT: ret
205220
;
206221
; LA64-LABEL: andn_icmp_uge_i16:
207222
; LA64: # %bb.0:
208-
; LA64-NEXT: and $a0, $a0, $a1
223+
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
224+
; LA64-NEXT: and $a0, $a1, $a0
209225
; LA64-NEXT: sltu $a0, $a0, $a1
210226
; LA64-NEXT: xori $a0, $a0, 1
211227
; LA64-NEXT: ret
@@ -217,13 +233,15 @@ define i1 @andn_icmp_uge_i16(i16 signext %a, i16 signext %b) nounwind {
217233
define i1 @andn_icmp_ugt_i8(i8 signext %a, i8 signext %b) nounwind {
218234
; LA32-LABEL: andn_icmp_ugt_i8:
219235
; LA32: # %bb.0:
220-
; LA32-NEXT: and $a0, $a0, $a1
236+
; LA32-NEXT: andi $a1, $a1, 255
237+
; LA32-NEXT: and $a0, $a1, $a0
221238
; LA32-NEXT: sltu $a0, $a1, $a0
222239
; LA32-NEXT: ret
223240
;
224241
; LA64-LABEL: andn_icmp_ugt_i8:
225242
; LA64: # %bb.0:
226-
; LA64-NEXT: and $a0, $a0, $a1
243+
; LA64-NEXT: andi $a1, $a1, 255
244+
; LA64-NEXT: and $a0, $a1, $a0
227245
; LA64-NEXT: sltu $a0, $a1, $a0
228246
; LA64-NEXT: ret
229247
%and = and i8 %a, %b
@@ -234,13 +252,15 @@ define i1 @andn_icmp_ugt_i8(i8 signext %a, i8 signext %b) nounwind {
234252
define i1 @andn_icmp_ugt_i16(i16 signext %a, i16 signext %b) nounwind {
235253
; LA32-LABEL: andn_icmp_ugt_i16:
236254
; LA32: # %bb.0:
237-
; LA32-NEXT: and $a0, $a0, $a1
255+
; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
256+
; LA32-NEXT: and $a0, $a1, $a0
238257
; LA32-NEXT: sltu $a0, $a1, $a0
239258
; LA32-NEXT: ret
240259
;
241260
; LA64-LABEL: andn_icmp_ugt_i16:
242261
; LA64: # %bb.0:
243-
; LA64-NEXT: and $a0, $a0, $a1
262+
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
263+
; LA64-NEXT: and $a0, $a1, $a0
244264
; LA64-NEXT: sltu $a0, $a1, $a0
245265
; LA64-NEXT: ret
246266
%and = and i16 %a, %b
@@ -251,14 +271,16 @@ define i1 @andn_icmp_ugt_i16(i16 signext %a, i16 signext %b) nounwind {
251271
define i1 @andn_icmp_ule_i8(i8 signext %a, i8 signext %b) nounwind {
252272
; LA32-LABEL: andn_icmp_ule_i8:
253273
; LA32: # %bb.0:
254-
; LA32-NEXT: and $a0, $a0, $a1
274+
; LA32-NEXT: andi $a1, $a1, 255
275+
; LA32-NEXT: and $a0, $a1, $a0
255276
; LA32-NEXT: sltu $a0, $a1, $a0
256277
; LA32-NEXT: xori $a0, $a0, 1
257278
; LA32-NEXT: ret
258279
;
259280
; LA64-LABEL: andn_icmp_ule_i8:
260281
; LA64: # %bb.0:
261-
; LA64-NEXT: and $a0, $a0, $a1
282+
; LA64-NEXT: andi $a1, $a1, 255
283+
; LA64-NEXT: and $a0, $a1, $a0
262284
; LA64-NEXT: sltu $a0, $a1, $a0
263285
; LA64-NEXT: xori $a0, $a0, 1
264286
; LA64-NEXT: ret
@@ -270,14 +292,16 @@ define i1 @andn_icmp_ule_i8(i8 signext %a, i8 signext %b) nounwind {
270292
define i1 @andn_icmp_ule_i16(i16 signext %a, i16 signext %b) nounwind {
271293
; LA32-LABEL: andn_icmp_ule_i16:
272294
; LA32: # %bb.0:
273-
; LA32-NEXT: and $a0, $a0, $a1
295+
; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
296+
; LA32-NEXT: and $a0, $a1, $a0
274297
; LA32-NEXT: sltu $a0, $a1, $a0
275298
; LA32-NEXT: xori $a0, $a0, 1
276299
; LA32-NEXT: ret
277300
;
278301
; LA64-LABEL: andn_icmp_ule_i16:
279302
; LA64: # %bb.0:
280-
; LA64-NEXT: and $a0, $a0, $a1
303+
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
304+
; LA64-NEXT: and $a0, $a1, $a0
281305
; LA64-NEXT: sltu $a0, $a1, $a0
282306
; LA64-NEXT: xori $a0, $a0, 1
283307
; LA64-NEXT: ret

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