Skip to content

Commit 1cff741

Browse files
lukel97lukel97
authored
[RISCV] Merge RISCVCoalesceVSETVLI back into RISCVInsertVSETVLI (#92869)
We no longer need to separate the passes now that #70549 is landed and this will unblock #89089. It's not strictly NFC because it will move coalescing before register allocation when -riscv-vsetvl-after-rvv-regalloc is disabled. But this makes it closer to the original behaviour.
1 parent 7348bb2 commit 1cff741

File tree

7 files changed

+92
-144
lines changed

7 files changed

+92
-144
lines changed

‎llvm/lib/Target/RISCV/RISCV.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,6 @@ FunctionPass *createRISCVInsertVSETVLIPass();
6262
void initializeRISCVInsertVSETVLIPass(PassRegistry &);
6363
extern char &RISCVInsertVSETVLIID;
6464

65-
FunctionPass *createRISCVCoalesceVSETVLIPass();
66-
void initializeRISCVCoalesceVSETVLIPass(PassRegistry &);
67-
6865
FunctionPass *createRISCVPostRAExpandPseudoPass();
6966
void initializeRISCVPostRAExpandPseudoPass(PassRegistry &);
7067
FunctionPass *createRISCVInsertReadWriteCSRPass();

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 15 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -378,10 +378,10 @@ static bool areCompatibleVTYPEs(uint64_t CurVType, uint64_t NewVType,
378378

379379
/// Return the fields and properties demanded by the provided instruction.
380380
DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
381-
// This function works in RISCVCoalesceVSETVLI too. We can still use the value
382-
// of a SEW, VL, or Policy operand even though it might not be the exact value
383-
// in the VL or VTYPE, since we only care about what the instruction
384-
// originally demanded.
381+
// This function works in coalesceVSETVLI too. We can still use the value of a
382+
// SEW, VL, or Policy operand even though it might not be the exact value in
383+
// the VL or VTYPE, since we only care about what the instruction originally
384+
// demanded.
385385

386386
// Most instructions don't use any of these subfeilds.
387387
DemandedFields Res;
@@ -900,36 +900,7 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
900900
void emitVSETVLIs(MachineBasicBlock &MBB);
901901
void doPRE(MachineBasicBlock &MBB);
902902
void insertReadVL(MachineBasicBlock &MBB);
903-
};
904-
905-
class RISCVCoalesceVSETVLI : public MachineFunctionPass {
906-
public:
907-
static char ID;
908-
const RISCVSubtarget *ST;
909-
const TargetInstrInfo *TII;
910-
MachineRegisterInfo *MRI;
911-
LiveIntervals *LIS;
912-
913-
RISCVCoalesceVSETVLI() : MachineFunctionPass(ID) {}
914-
bool runOnMachineFunction(MachineFunction &MF) override;
915-
916-
void getAnalysisUsage(AnalysisUsage &AU) const override {
917-
AU.setPreservesCFG();
918-
919-
AU.addRequired<LiveIntervals>();
920-
AU.addPreserved<LiveIntervals>();
921-
AU.addRequired<SlotIndexes>();
922-
AU.addPreserved<SlotIndexes>();
923-
AU.addPreserved<LiveDebugVariables>();
924-
AU.addPreserved<LiveStacks>();
925-
926-
MachineFunctionPass::getAnalysisUsage(AU);
927-
}
928-
929-
StringRef getPassName() const override { return RISCV_COALESCE_VSETVLI_NAME; }
930-
931-
private:
932-
bool coalesceVSETVLIs(MachineBasicBlock &MBB);
903+
void coalesceVSETVLIs(MachineBasicBlock &MBB) const;
933904
};
934905

935906
} // end anonymous namespace
@@ -940,11 +911,6 @@ char &llvm::RISCVInsertVSETVLIID = RISCVInsertVSETVLI::ID;
940911
INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
941912
false, false)
942913

943-
char RISCVCoalesceVSETVLI::ID = 0;
944-
945-
INITIALIZE_PASS(RISCVCoalesceVSETVLI, "riscv-coalesce-vsetvli",
946-
RISCV_COALESCE_VSETVLI_NAME, false, false)
947-
948914
// Return a VSETVLIInfo representing the changes made by this VSETVLI or
949915
// VSETIVLI instruction.
950916
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
@@ -1650,7 +1616,7 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
16501616
return areCompatibleVTYPEs(PriorVType, VType, Used);
16511617
}
16521618

1653-
bool RISCVCoalesceVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) {
1619+
void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
16541620
MachineInstr *NextMI = nullptr;
16551621
// We can have arbitrary code in successors, so VL and VTYPE
16561622
// must be considered demanded.
@@ -1742,8 +1708,6 @@ bool RISCVCoalesceVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) {
17421708
LIS->RemoveMachineInstrFromMaps(*MI);
17431709
MI->eraseFromParent();
17441710
}
1745-
1746-
return !ToDelete.empty();
17471711
}
17481712

17491713
void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
@@ -1833,6 +1797,15 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
18331797
for (MachineBasicBlock &MBB : MF)
18341798
insertReadVL(MBB);
18351799

1800+
// Now that all vsetvlis are explicit, go through and do block local
1801+
// DSE and peephole based demanded fields based transforms. Note that
1802+
// this *must* be done outside the main dataflow so long as we allow
1803+
// any cross block analysis within the dataflow. We can't have both
1804+
// demanded fields based mutation and non-local analysis in the
1805+
// dataflow at the same time without introducing inconsistencies.
1806+
for (MachineBasicBlock &MBB : MF)
1807+
coalesceVSETVLIs(MBB);
1808+
18361809
BlockInfo.clear();
18371810
return HaveVectorOp;
18381811
}
@@ -1841,29 +1814,3 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
18411814
FunctionPass *llvm::createRISCVInsertVSETVLIPass() {
18421815
return new RISCVInsertVSETVLI();
18431816
}
1844-
1845-
// Now that all vsetvlis are explicit, go through and do block local
1846-
// DSE and peephole based demanded fields based transforms. Note that
1847-
// this *must* be done outside the main dataflow so long as we allow
1848-
// any cross block analysis within the dataflow. We can't have both
1849-
// demanded fields based mutation and non-local analysis in the
1850-
// dataflow at the same time without introducing inconsistencies.
1851-
bool RISCVCoalesceVSETVLI::runOnMachineFunction(MachineFunction &MF) {
1852-
// Skip if the vector extension is not enabled.
1853-
ST = &MF.getSubtarget<RISCVSubtarget>();
1854-
if (!ST->hasVInstructions())
1855-
return false;
1856-
TII = ST->getInstrInfo();
1857-
MRI = &MF.getRegInfo();
1858-
LIS = &getAnalysis<LiveIntervals>();
1859-
1860-
bool Changed = false;
1861-
for (MachineBasicBlock &MBB : MF)
1862-
Changed |= coalesceVSETVLIs(MBB);
1863-
1864-
return Changed;
1865-
}
1866-
1867-
FunctionPass *llvm::createRISCVCoalesceVSETVLIPass() {
1868-
return new RISCVCoalesceVSETVLI();
1869-
}

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
121121
initializeRISCVExpandPseudoPass(*PR);
122122
initializeRISCVFoldMasksPass(*PR);
123123
initializeRISCVInsertVSETVLIPass(*PR);
124-
initializeRISCVCoalesceVSETVLIPass(*PR);
125124
initializeRISCVInsertReadWriteCSRPass(*PR);
126125
initializeRISCVInsertWriteVXRMPass(*PR);
127126
initializeRISCVDAGToDAGISelPass(*PR);
@@ -396,7 +395,6 @@ bool RISCVPassConfig::addRegAssignAndRewriteFast() {
396395
addPass(createRVVRegAllocPass(false));
397396
if (EnableVSETVLIAfterRVVRegAlloc)
398397
addPass(createRISCVInsertVSETVLIPass());
399-
addPass(createRISCVCoalesceVSETVLIPass());
400398
if (TM->getOptLevel() != CodeGenOptLevel::None &&
401399
EnableRISCVDeadRegisterElimination)
402400
addPass(createRISCVDeadRegisterDefinitionsPass());
@@ -408,7 +406,6 @@ bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
408406
addPass(createVirtRegRewriter(false));
409407
if (EnableVSETVLIAfterRVVRegAlloc)
410408
addPass(createRISCVInsertVSETVLIPass());
411-
addPass(createRISCVCoalesceVSETVLIPass());
412409
if (TM->getOptLevel() != CodeGenOptLevel::None &&
413410
EnableRISCVDeadRegisterElimination)
414411
addPass(createRISCVDeadRegisterDefinitionsPass());

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@
5050
; CHECK-NEXT: Slot index numbering
5151
; CHECK-NEXT: Live Interval Analysis
5252
; CHECK-NEXT: RISC-V Insert VSETVLI pass
53-
; CHECK-NEXT: RISC-V Coalesce VSETVLI pass
5453
; CHECK-NEXT: Fast Register Allocator
5554
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
5655
; CHECK-NEXT: Fixup Statepoint Caller Saved

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,6 @@
142142
; CHECK-NEXT: Greedy Register Allocator
143143
; CHECK-NEXT: Virtual Register Rewriter
144144
; CHECK-NEXT: RISC-V Insert VSETVLI pass
145-
; CHECK-NEXT: RISC-V Coalesce VSETVLI pass
146145
; CHECK-NEXT: RISC-V Dead register definitions
147146
; CHECK-NEXT: Virtual Register Map
148147
; CHECK-NEXT: Live Register Matrix

‎llvm/test/CodeGen/RISCV/rvv/coalesce-vsetvli.mir‎

Lines changed: 0 additions & 66 deletions
This file was deleted.

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir‎

Lines changed: 77 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc %s -o - -mtriple=riscv64 -mattr=v \
3-
# RUN: -run-pass=riscv-insert-vsetvli,riscv-coalesce-vsetvli | FileCheck %s
2+
# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=riscv-insert-vsetvli \
3+
# RUN: | FileCheck %s
44

55
--- |
66
source_filename = "vsetvli-insert.ll"
@@ -80,6 +80,18 @@
8080
ret void
8181
}
8282

83+
define void @coalesce_dead_avl_addi() {
84+
ret void
85+
}
86+
87+
define void @coalesce_dead_avl_nonvolatile_load() {
88+
ret void
89+
}
90+
91+
define void @coalesce_dead_avl_volatile_load() {
92+
ret void
93+
}
94+
8395
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
8496

8597
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, ptr nocapture, i64) #4
@@ -501,3 +513,66 @@ body: |
501513
%4:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3, 6, 0
502514
PseudoRET
503515
...
516+
---
517+
name: coalesce_dead_avl_addi
518+
tracksRegLiveness: true
519+
body: |
520+
bb.0:
521+
; CHECK-LABEL: name: coalesce_dead_avl_addi
522+
; CHECK: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
523+
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
524+
; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
525+
; CHECK-NEXT: PseudoRET
526+
%avl:gprnox0 = ADDI $x0, 42
527+
dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype
528+
%x:gpr = PseudoVMV_X_S $noreg, 6
529+
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
530+
$v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0
531+
PseudoRET
532+
...
533+
---
534+
name: coalesce_dead_avl_nonvolatile_load
535+
tracksRegLiveness: true
536+
body: |
537+
bb.0:
538+
liveins: $x1
539+
; CHECK-LABEL: name: coalesce_dead_avl_nonvolatile_load
540+
; CHECK: liveins: $x1
541+
; CHECK-NEXT: {{ $}}
542+
; CHECK-NEXT: %ptr:gpr = COPY $x1
543+
; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (dereferenceable load (s32))
544+
; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
545+
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
546+
; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
547+
; CHECK-NEXT: PseudoRET
548+
%ptr:gpr = COPY $x1
549+
%avl:gprnox0 = LW killed %ptr, 0 :: (dereferenceable load (s32))
550+
dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype
551+
%x:gpr = PseudoVMV_X_S $noreg, 6
552+
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
553+
$v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0
554+
PseudoRET
555+
...
556+
---
557+
name: coalesce_dead_avl_volatile_load
558+
tracksRegLiveness: true
559+
body: |
560+
bb.0:
561+
liveins: $x1
562+
; CHECK-LABEL: name: coalesce_dead_avl_volatile_load
563+
; CHECK: liveins: $x1
564+
; CHECK-NEXT: {{ $}}
565+
; CHECK-NEXT: %ptr:gpr = COPY $x1
566+
; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (volatile dereferenceable load (s32))
567+
; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
568+
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
569+
; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
570+
; CHECK-NEXT: PseudoRET
571+
%ptr:gpr = COPY $x1
572+
%avl:gprnox0 = LW killed %ptr, 0 :: (volatile dereferenceable load (s32))
573+
dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype
574+
%x:gpr = PseudoVMV_X_S $noreg, 6
575+
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
576+
$v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0
577+
PseudoRET
578+
...

0 commit comments

Comments
 (0)