Skip to content

Commit 1c3a3f0

Browse files
topperctopperc
authored
[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)
This adds VPSExtPromotedInteger and VPZExtPromotedInteger and uses them to promote many arithmetic operations. VPSExtPromotedInteger uses a shift pair because we don't have VP_SIGN_EXTEND_INREG yet.
1 parent bc247ba commit 1c3a3f0

27 files changed

+201
-136
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp‎

Lines changed: 78 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -646,18 +646,21 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
646646
}
647647
}
648648

649-
// Zero extend to the promoted type and do the count there.
650-
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
651-
652649
// Subtract off the extra leading bits in the bigger type.
653650
SDValue ExtractLeadingBits = DAG.getConstant(
654651
NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl, NVT);
655-
if (!N->isVPOpcode())
652+
if (!N->isVPOpcode()) {
653+
// Zero extend to the promoted type and do the count there.
654+
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
656655
return DAG.getNode(ISD::SUB, dl, NVT,
657656
DAG.getNode(N->getOpcode(), dl, NVT, Op),
658657
ExtractLeadingBits);
658+
}
659+
659660
SDValue Mask = N->getOperand(1);
660661
SDValue EVL = N->getOperand(2);
662+
// Zero extend to the promoted type and do the count there.
663+
SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
661664
return DAG.getNode(ISD::VP_SUB, dl, NVT,
662665
DAG.getNode(N->getOpcode(), dl, NVT, Op, Mask, EVL),
663666
ExtractLeadingBits, Mask, EVL);
@@ -681,11 +684,16 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
681684
}
682685

683686
// Zero extend to the promoted type and do the count or parity there.
684-
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
685-
if (!N->isVPOpcode())
687+
if (!N->isVPOpcode()) {
688+
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
686689
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
687-
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op,
688-
N->getOperand(1), N->getOperand(2));
690+
}
691+
692+
SDValue Mask = N->getOperand(1);
693+
SDValue EVL = N->getOperand(2);
694+
SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
695+
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op, Mask,
696+
EVL);
689697
}
690698

691699
SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
@@ -1335,12 +1343,19 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
13351343
SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
13361344
SDValue LHS = GetPromotedInteger(N->getOperand(0));
13371345
SDValue RHS = N->getOperand(1);
1338-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1339-
RHS = ZExtPromotedInteger(RHS);
1340-
if (N->getOpcode() != ISD::VP_SHL)
1346+
if (N->getOpcode() != ISD::VP_SHL) {
1347+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1348+
RHS = ZExtPromotedInteger(RHS);
1349+
13411350
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1351+
}
1352+
1353+
SDValue Mask = N->getOperand(2);
1354+
SDValue EVL = N->getOperand(3);
1355+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1356+
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
13421357
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1343-
N->getOperand(2), N->getOperand(3));
1358+
Mask, EVL);
13441359
}
13451360

13461361
SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
@@ -1364,27 +1379,39 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
13641379
}
13651380

13661381
SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1367-
// Sign extend the input.
1368-
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1369-
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1370-
if (N->getNumOperands() == 2)
1382+
if (N->getNumOperands() == 2) {
1383+
// Sign extend the input.
1384+
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1385+
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
13711386
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1387+
}
13721388
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
13731389
assert(N->isVPOpcode() && "Expected VP opcode");
1390+
SDValue Mask = N->getOperand(2);
1391+
SDValue EVL = N->getOperand(3);
1392+
// Sign extend the input.
1393+
SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL);
1394+
SDValue RHS = VPSExtPromotedInteger(N->getOperand(1), Mask, EVL);
13741395
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1375-
N->getOperand(2), N->getOperand(3));
1396+
Mask, EVL);
13761397
}
13771398

13781399
SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1379-
// Zero extend the input.
1380-
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1381-
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1382-
if (N->getNumOperands() == 2)
1400+
if (N->getNumOperands() == 2) {
1401+
// Zero extend the input.
1402+
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1403+
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
13831404
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1405+
}
13841406
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
13851407
assert(N->isVPOpcode() && "Expected VP opcode");
1408+
// Zero extend the input.
1409+
SDValue Mask = N->getOperand(2);
1410+
SDValue EVL = N->getOperand(3);
1411+
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
1412+
SDValue RHS = VPZExtPromotedInteger(N->getOperand(1), Mask, EVL);
13861413
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1387-
N->getOperand(2), N->getOperand(3));
1414+
Mask, EVL);
13881415
}
13891416

13901417
SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
@@ -1400,27 +1427,43 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
14001427
}
14011428

14021429
SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1403-
// The input value must be properly sign extended.
1404-
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
14051430
SDValue RHS = N->getOperand(1);
1406-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1407-
RHS = ZExtPromotedInteger(RHS);
1408-
if (N->getOpcode() != ISD::VP_SRA)
1431+
if (N->getOpcode() != ISD::VP_SRA) {
1432+
// The input value must be properly sign extended.
1433+
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1434+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1435+
RHS = ZExtPromotedInteger(RHS);
14091436
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1437+
}
1438+
1439+
SDValue Mask = N->getOperand(2);
1440+
SDValue EVL = N->getOperand(3);
1441+
// The input value must be properly sign extended.
1442+
SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL);
1443+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1444+
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
14101445
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1411-
N->getOperand(2), N->getOperand(3));
1446+
Mask, EVL);
14121447
}
14131448

14141449
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1415-
// The input value must be properly zero extended.
1416-
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
14171450
SDValue RHS = N->getOperand(1);
1418-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1419-
RHS = ZExtPromotedInteger(RHS);
1420-
if (N->getOpcode() != ISD::VP_SRL)
1451+
if (N->getOpcode() != ISD::VP_SRL) {
1452+
// The input value must be properly zero extended.
1453+
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1454+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1455+
RHS = ZExtPromotedInteger(RHS);
14211456
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1457+
}
1458+
1459+
SDValue Mask = N->getOperand(2);
1460+
SDValue EVL = N->getOperand(3);
1461+
// The input value must be properly zero extended.
1462+
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
1463+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1464+
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
14221465
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1423-
N->getOperand(2), N->getOperand(3));
1466+
Mask, EVL);
14241467
}
14251468

14261469
SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
@@ -1487,7 +1530,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
14871530
SDValue Mask = N->getOperand(3);
14881531
SDValue EVL = N->getOperand(4);
14891532
if (getTypeAction(Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1490-
Amt = ZExtPromotedInteger(Amt);
1533+
Amt = VPZExtPromotedInteger(Amt, Mask, EVL);
14911534
EVT AmtVT = Amt.getValueType();
14921535

14931536
SDLoc DL(N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -275,6 +275,27 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
275275
return DAG.getZeroExtendInReg(Op, dl, OldVT);
276276
}
277277

278+
/// Get a promoted operand and zero extend it to the final size.
279+
SDValue VPSExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) {
280+
EVT OldVT = Op.getValueType();
281+
SDLoc dl(Op);
282+
Op = GetPromotedInteger(Op);
283+
// FIXME: Add VP_SIGN_EXTEND_INREG.
284+
EVT VT = Op.getValueType();
285+
unsigned BitsDiff = VT.getScalarSizeInBits() - OldVT.getScalarSizeInBits();
286+
SDValue ShiftCst = DAG.getShiftAmountConstant(BitsDiff, VT, dl);
287+
SDValue Shl = DAG.getNode(ISD::VP_SHL, dl, VT, Op, ShiftCst, Mask, EVL);
288+
return DAG.getNode(ISD::VP_SRA, dl, VT, Shl, ShiftCst, Mask, EVL);
289+
}
290+
291+
/// Get a promoted operand and zero extend it to the final size.
292+
SDValue VPZExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) {
293+
EVT OldVT = Op.getValueType();
294+
SDLoc dl(Op);
295+
Op = GetPromotedInteger(Op);
296+
return DAG.getVPZeroExtendInReg(Op, Mask, EVL, dl, OldVT);
297+
}
298+
278299
// Promote the given operand V (vector or scalar) according to N's specific
279300
// reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns
280301
// the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2574,9 +2574,8 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
25742574
; CHECK-LABEL: vp_ctlz_nxv1i9:
25752575
; CHECK: # %bb.0:
25762576
; CHECK-NEXT: li a1, 511
2577-
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2578-
; CHECK-NEXT: vand.vx v8, v8, a1
25792577
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2578+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
25802579
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
25812580
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
25822581
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
@@ -2593,9 +2592,8 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
25932592
; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i9:
25942593
; CHECK-ZVBB: # %bb.0:
25952594
; CHECK-ZVBB-NEXT: li a1, 511
2596-
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2597-
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
25982595
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2596+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
25992597
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
26002598
; CHECK-ZVBB-NEXT: li a0, 7
26012599
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0, v0.t
@@ -2607,9 +2605,8 @@ define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26072605
; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i9:
26082606
; CHECK: # %bb.0:
26092607
; CHECK-NEXT: li a1, 511
2610-
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2611-
; CHECK-NEXT: vand.vx v8, v8, a1
26122608
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2609+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
26132610
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
26142611
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
26152612
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
@@ -2624,9 +2621,8 @@ define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26242621
; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i9:
26252622
; CHECK-ZVBB: # %bb.0:
26262623
; CHECK-ZVBB-NEXT: li a1, 511
2627-
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2628-
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
26292624
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2625+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
26302626
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
26312627
; CHECK-ZVBB-NEXT: li a0, 7
26322628
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0, v0.t

‎llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2549,9 +2549,8 @@ define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i
25492549
; CHECK-LABEL: vp_ctpop_nxv1i9:
25502550
; CHECK: # %bb.0:
25512551
; CHECK-NEXT: li a1, 511
2552-
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2553-
; CHECK-NEXT: vand.vx v8, v8, a1
25542552
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2553+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
25552554
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
25562555
; CHECK-NEXT: lui a0, 5
25572556
; CHECK-NEXT: addi a0, a0, 1365
@@ -2576,9 +2575,8 @@ define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i
25762575
; CHECK-ZVBB-LABEL: vp_ctpop_nxv1i9:
25772576
; CHECK-ZVBB: # %bb.0:
25782577
; CHECK-ZVBB-NEXT: li a1, 511
2579-
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2580-
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
25812578
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2579+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
25822580
; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t
25832581
; CHECK-ZVBB-NEXT: ret
25842582
%v = call <vscale x 1 x i9> @llvm.vp.ctpop.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,11 @@ declare <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
99
define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
1010
; CHECK-LABEL: vdiv_vv_v8i7:
1111
; CHECK: # %bb.0:
12-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
13-
; CHECK-NEXT: vadd.vv v9, v9, v9
14-
; CHECK-NEXT: vsra.vi v9, v9, 1
15-
; CHECK-NEXT: vadd.vv v8, v8, v8
16-
; CHECK-NEXT: vsra.vi v8, v8, 1
1712
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
13+
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
14+
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
15+
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
16+
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
1817
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
1918
; CHECK-NEXT: ret
2019
%v = call <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
1010
; CHECK-LABEL: vdivu_vv_v8i7:
1111
; CHECK: # %bb.0:
1212
; CHECK-NEXT: li a1, 127
13-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14-
; CHECK-NEXT: vand.vx v9, v9, a1
15-
; CHECK-NEXT: vand.vx v8, v8, a1
1613
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
14+
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
15+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1716
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
1817
; CHECK-NEXT: ret
1918
%v = call <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,11 @@ declare <8 x i7> @llvm.vp.smax.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
99
define <8 x i7> @vmax_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
1010
; CHECK-LABEL: vmax_vv_v8i7:
1111
; CHECK: # %bb.0:
12-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
13-
; CHECK-NEXT: vadd.vv v9, v9, v9
14-
; CHECK-NEXT: vsra.vi v9, v9, 1
15-
; CHECK-NEXT: vadd.vv v8, v8, v8
16-
; CHECK-NEXT: vsra.vi v8, v8, 1
1712
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
13+
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
14+
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
15+
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
16+
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
1817
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
1918
; CHECK-NEXT: ret
2019
%v = call <8 x i7> @llvm.vp.smax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@ define <8 x i7> @vmaxu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
1010
; CHECK-LABEL: vmaxu_vv_v8i7:
1111
; CHECK: # %bb.0:
1212
; CHECK-NEXT: li a1, 127
13-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14-
; CHECK-NEXT: vand.vx v9, v9, a1
15-
; CHECK-NEXT: vand.vx v8, v8, a1
1613
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
14+
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
15+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1716
; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t
1817
; CHECK-NEXT: ret
1918
%v = call <8 x i7> @llvm.vp.umax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,11 @@ declare <8 x i7> @llvm.vp.smin.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
99
define <8 x i7> @vmin_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
1010
; CHECK-LABEL: vmin_vv_v8i7:
1111
; CHECK: # %bb.0:
12-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
13-
; CHECK-NEXT: vadd.vv v9, v9, v9
14-
; CHECK-NEXT: vsra.vi v9, v9, 1
15-
; CHECK-NEXT: vadd.vv v8, v8, v8
16-
; CHECK-NEXT: vsra.vi v8, v8, 1
1712
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
13+
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
14+
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
15+
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
16+
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
1817
; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t
1918
; CHECK-NEXT: ret
2019
%v = call <8 x i7> @llvm.vp.smin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@ define <8 x i7> @vminu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
1010
; CHECK-LABEL: vminu_vv_v8i7:
1111
; CHECK: # %bb.0:
1212
; CHECK-NEXT: li a1, 127
13-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
14-
; CHECK-NEXT: vand.vx v9, v9, a1
15-
; CHECK-NEXT: vand.vx v8, v8, a1
1613
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
14+
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
15+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1716
; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t
1817
; CHECK-NEXT: ret
1918
%v = call <8 x i7> @llvm.vp.umin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

0 commit comments

Comments
 (0)