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[Clang][SVE2p1] Add svpsel builtins
 As described in: ARM-software/acle#257 Patch by : Sander de Smalen<[email protected]> Reviewed By: kmclaughlin Differential Revision: https://reviews.llvm.org/D151197
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‎clang/include/clang/Basic/arm_sve.td

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1865,10 +1865,21 @@ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, "aarch64_
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def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
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def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
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def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone, "", [], []>;
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def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [], []>;
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def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [], []>;
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def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [], []>;
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}
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let TargetGuard = "sve2p1" in {
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def SVSCLAMP : SInst<"svclamp[_{d}]", "dddd", "csil", MergeNone, "aarch64_sve_sclamp", [], []>;
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def SVUCLAMP : SInst<"svclamp[_{d}]", "dddd", "UcUsUiUl", MergeNone, "aarch64_sve_uclamp", [], []>;
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def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc", MergeNone, "", [], []>;
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def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [], []>;
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def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [], []>;
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def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>;
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def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, "aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
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}

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10007,7 +10007,33 @@ Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
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switch (BuiltinID) {
1000810008
default:
1000910009
return nullptr;
10010-
10010+
case SVE::BI__builtin_sve_svpsel_lane_b8:
10011+
case SVE::BI__builtin_sve_svpsel_lane_b16:
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case SVE::BI__builtin_sve_svpsel_lane_b32:
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case SVE::BI__builtin_sve_svpsel_lane_b64:
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case SVE::BI__builtin_sve_svpsel_lane_c8:
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case SVE::BI__builtin_sve_svpsel_lane_c16:
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case SVE::BI__builtin_sve_svpsel_lane_c32:
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case SVE::BI__builtin_sve_svpsel_lane_c64: {
10018+
bool IsSVCount = isa<TargetExtType>(Ops[0]->getType());
10019+
assert(((!IsSVCount || cast<TargetExtType>(Ops[0]->getType())->getName() ==
10020+
"aarch64.svcount")) &&
10021+
"Unexpected TargetExtType");
10022+
auto SVCountTy =
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llvm::TargetExtType::get(getLLVMContext(), "aarch64.svcount");
10024+
Function *CastFromSVCountF =
10025+
CGM.getIntrinsic(Intrinsic::aarch64_sve_convert_to_svbool, SVCountTy);
10026+
Function *CastToSVCountF =
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CGM.getIntrinsic(Intrinsic::aarch64_sve_convert_from_svbool, SVCountTy);
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10029+
auto OverloadedTy = getSVEType(SVETypeFlags(Builtin->TypeModifier));
10030+
Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_psel, OverloadedTy);
10031+
llvm::Value *Ops0 =
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IsSVCount ? Builder.CreateCall(CastFromSVCountF, Ops[0]) : Ops[0];
10033+
llvm::Value *Ops1 = EmitSVEPredicateCast(Ops[1], OverloadedTy);
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llvm::Value *PSel = Builder.CreateCall(F, {Ops0, Ops1, Ops[2]});
10035+
return IsSVCount ? Builder.CreateCall(CastToSVCountF, PSel) : PSel;
10036+
}
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case SVE::BI__builtin_sve_svmov_b_z: {
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// svmov_b_z(pg, op) <=> svand_b_z(pg, op, op)
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SVETypeFlags TypeFlags(Builtin->TypeModifier);

‎clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c

Lines changed: 165 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,165 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
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// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
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// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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#include <arm_sve.h>
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// CHECK-LABEL: @test_svpsel_lane_b8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 15
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 16 x i1> [[P2:%.*]], i32 [[ADD]])
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z19test_svpsel_lane_b8u10__SVBool_tu10__SVBool_tj(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 15
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 16 x i1> [[P2:%.*]], i32 [[ADD]])
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// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
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//
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svbool_t test_svpsel_lane_b8(svbool_t p1, svbool_t p2, uint32_t idx) {
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return svpsel_lane_b8(p1, p2, idx + 15);
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}
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// CHECK-LABEL: @test_svpsel_lane_b16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 7
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[P2:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 8 x i1> [[TMP0]], i32 [[ADD]])
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
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//
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// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b16u10__SVBool_tu10__SVBool_tj(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 7
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[P2:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 8 x i1> [[TMP0]], i32 [[ADD]])
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// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
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//
41+
svbool_t test_svpsel_lane_b16(svbool_t p1, svbool_t p2, uint32_t idx) {
42+
return svpsel_lane_b16(p1, p2, idx + 7);
43+
}
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// CHECK-LABEL: @test_svpsel_lane_b32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 3
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[P2:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 4 x i1> [[TMP0]], i32 [[ADD]])
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
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//
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// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b32u10__SVBool_tu10__SVBool_tj(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 3
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[P2:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 4 x i1> [[TMP0]], i32 [[ADD]])
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// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
58+
//
59+
svbool_t test_svpsel_lane_b32(svbool_t p1, svbool_t p2, uint32_t idx) {
60+
return svpsel_lane_b32(p1, p2, idx + 3);
61+
}
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63+
// CHECK-LABEL: @test_svpsel_lane_b64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 1
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[P2:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 2 x i1> [[TMP0]], i32 [[ADD]])
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
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//
70+
// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_b64u10__SVBool_tu10__SVBool_tj(
71+
// CPP-CHECK-NEXT: entry:
72+
// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 1
73+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[P2:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> [[P1:%.*]], <vscale x 2 x i1> [[TMP0]], i32 [[ADD]])
75+
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
76+
//
77+
svbool_t test_svpsel_lane_b64(svbool_t p1, svbool_t p2, uint32_t idx) {
78+
return svpsel_lane_b64(p1, p2, idx + 1);
79+
}
80+
81+
// CHECK-LABEL: @test_svpsel_lane_c8(
82+
// CHECK-NEXT: entry:
83+
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 15
84+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
85+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[P2:%.*]], i32 [[ADD]])
86+
// CHECK-NEXT: [[TMP2:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP1]])
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// CHECK-NEXT: ret target("aarch64.svcount") [[TMP2]]
88+
//
89+
// CPP-CHECK-LABEL: @_Z19test_svpsel_lane_c8u11__SVCount_tu10__SVBool_tj(
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// CPP-CHECK-NEXT: entry:
91+
// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 15
92+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[P2:%.*]], i32 [[ADD]])
94+
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP1]])
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// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP2]]
96+
//
97+
svcount_t test_svpsel_lane_c8(svcount_t p1, svbool_t p2, uint32_t idx) {
98+
return svpsel_lane_c8(p1, p2, idx + 15);
99+
}
100+
101+
// CHECK-LABEL: @test_svpsel_lane_c16(
102+
// CHECK-NEXT: entry:
103+
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 7
104+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[P2:%.*]])
106+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> [[TMP0]], <vscale x 8 x i1> [[TMP1]], i32 [[ADD]])
107+
// CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
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// CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
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//
110+
// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_c16u11__SVCount_tu10__SVBool_tj(
111+
// CPP-CHECK-NEXT: entry:
112+
// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 7
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[P2:%.*]])
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// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> [[TMP0]], <vscale x 8 x i1> [[TMP1]], i32 [[ADD]])
116+
// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
117+
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
118+
//
119+
svcount_t test_svpsel_lane_c16(svcount_t p1, svbool_t p2, uint32_t idx) {
120+
return svpsel_lane_c16(p1, p2, idx + 7);
121+
}
122+
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// CHECK-LABEL: @test_svpsel_lane_c32(
124+
// CHECK-NEXT: entry:
125+
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 3
126+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
127+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[P2:%.*]])
128+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> [[TMP0]], <vscale x 4 x i1> [[TMP1]], i32 [[ADD]])
129+
// CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
130+
// CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
131+
//
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// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_c32u11__SVCount_tu10__SVBool_tj(
133+
// CPP-CHECK-NEXT: entry:
134+
// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 3
135+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
136+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[P2:%.*]])
137+
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> [[TMP0]], <vscale x 4 x i1> [[TMP1]], i32 [[ADD]])
138+
// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
139+
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
140+
//
141+
svcount_t test_svpsel_lane_c32(svcount_t p1, svbool_t p2, uint32_t idx) {
142+
return svpsel_lane_c32(p1, p2, idx + 3);
143+
}
144+
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// CHECK-LABEL: @test_svpsel_lane_c64(
146+
// CHECK-NEXT: entry:
147+
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 1
148+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
149+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[P2:%.*]])
150+
// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> [[TMP0]], <vscale x 2 x i1> [[TMP1]], i32 [[ADD]])
151+
// CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
152+
// CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
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//
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// CPP-CHECK-LABEL: @_Z20test_svpsel_lane_c64u11__SVCount_tu10__SVBool_tj(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[ADD:%.*]] = add i32 [[IDX:%.*]], 1
157+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.taarch64.svcountt(target("aarch64.svcount") [[P1:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[P2:%.*]])
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// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> [[TMP0]], <vscale x 2 x i1> [[TMP1]], i32 [[ADD]])
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// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1> [[TMP2]])
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// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP3]]
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//
163+
svcount_t test_svpsel_lane_c64(svcount_t p1, svbool_t p2, uint32_t idx) {
164+
return svpsel_lane_c64(p1, p2, idx + 1);
165+
}

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