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[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax (#160637)
Fix Issue #160611
1 parent b86fef8 commit 178e2a7

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11 files changed

+715
-175
lines changed

11 files changed

+715
-175
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6046,7 +6046,7 @@ static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2,
60466046
return N02;
60476047
}
60486048

6049-
if (MaxC == 0 && MinCPlus1.isPowerOf2()) {
6049+
if (MaxC == 0 && MinC != 0 && MinCPlus1.isPowerOf2()) {
60506050
BW = MinCPlus1.exactLogBase2();
60516051
Unsigned = true;
60526052
return N02;

‎llvm/test/CodeGen/AArch64/fpclamptosat.ll‎

Lines changed: 39 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -111,14 +111,14 @@ entry:
111111
ret i32 %conv6
112112
}
113113

114-
define i32 @utesth_f16i32(half %x) {
115-
; CHECK-CVT-LABEL: utesth_f16i32:
114+
define i32 @utest_f16i32(half %x) {
115+
; CHECK-CVT-LABEL: utest_f16i32:
116116
; CHECK-CVT: // %bb.0: // %entry
117117
; CHECK-CVT-NEXT: fcvt s0, h0
118118
; CHECK-CVT-NEXT: fcvtzu w0, s0
119119
; CHECK-CVT-NEXT: ret
120120
;
121-
; CHECK-FP16-LABEL: utesth_f16i32:
121+
; CHECK-FP16-LABEL: utest_f16i32:
122122
; CHECK-FP16: // %bb.0: // %entry
123123
; CHECK-FP16-NEXT: fcvtzu w0, h0
124124
; CHECK-FP16-NEXT: ret
@@ -298,8 +298,8 @@ entry:
298298
ret i16 %conv6
299299
}
300300

301-
define i16 @utesth_f16i16(half %x) {
302-
; CHECK-CVT-LABEL: utesth_f16i16:
301+
define i16 @utest_f16i16(half %x) {
302+
; CHECK-CVT-LABEL: utest_f16i16:
303303
; CHECK-CVT: // %bb.0: // %entry
304304
; CHECK-CVT-NEXT: fcvt s0, h0
305305
; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff
@@ -308,7 +308,7 @@ define i16 @utesth_f16i16(half %x) {
308308
; CHECK-CVT-NEXT: csel w0, w8, w9, lo
309309
; CHECK-CVT-NEXT: ret
310310
;
311-
; CHECK-FP16-LABEL: utesth_f16i16:
311+
; CHECK-FP16-LABEL: utest_f16i16:
312312
; CHECK-FP16: // %bb.0: // %entry
313313
; CHECK-FP16-NEXT: fcvtzu w8, h0
314314
; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff
@@ -493,8 +493,8 @@ entry:
493493
ret i64 %conv6
494494
}
495495

496-
define i64 @utesth_f16i64(half %x) {
497-
; CHECK-LABEL: utesth_f16i64:
496+
define i64 @utest_f16i64(half %x) {
497+
; CHECK-LABEL: utest_f16i64:
498498
; CHECK: // %bb.0: // %entry
499499
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
500500
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -636,14 +636,14 @@ entry:
636636
ret i32 %conv6
637637
}
638638

639-
define i32 @utesth_f16i32_mm(half %x) {
640-
; CHECK-CVT-LABEL: utesth_f16i32_mm:
639+
define i32 @utest_f16i32_mm(half %x) {
640+
; CHECK-CVT-LABEL: utest_f16i32_mm:
641641
; CHECK-CVT: // %bb.0: // %entry
642642
; CHECK-CVT-NEXT: fcvt s0, h0
643643
; CHECK-CVT-NEXT: fcvtzu w0, s0
644644
; CHECK-CVT-NEXT: ret
645645
;
646-
; CHECK-FP16-LABEL: utesth_f16i32_mm:
646+
; CHECK-FP16-LABEL: utest_f16i32_mm:
647647
; CHECK-FP16: // %bb.0: // %entry
648648
; CHECK-FP16-NEXT: fcvtzu w0, h0
649649
; CHECK-FP16-NEXT: ret
@@ -808,8 +808,8 @@ entry:
808808
ret i16 %conv6
809809
}
810810

811-
define i16 @utesth_f16i16_mm(half %x) {
812-
; CHECK-CVT-LABEL: utesth_f16i16_mm:
811+
define i16 @utest_f16i16_mm(half %x) {
812+
; CHECK-CVT-LABEL: utest_f16i16_mm:
813813
; CHECK-CVT: // %bb.0: // %entry
814814
; CHECK-CVT-NEXT: fcvt s0, h0
815815
; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff
@@ -818,7 +818,7 @@ define i16 @utesth_f16i16_mm(half %x) {
818818
; CHECK-CVT-NEXT: csel w0, w8, w9, lo
819819
; CHECK-CVT-NEXT: ret
820820
;
821-
; CHECK-FP16-LABEL: utesth_f16i16_mm:
821+
; CHECK-FP16-LABEL: utest_f16i16_mm:
822822
; CHECK-FP16: // %bb.0: // %entry
823823
; CHECK-FP16-NEXT: fcvtzu w8, h0
824824
; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff
@@ -986,8 +986,8 @@ entry:
986986
ret i64 %conv6
987987
}
988988

989-
define i64 @utesth_f16i64_mm(half %x) {
990-
; CHECK-LABEL: utesth_f16i64_mm:
989+
define i64 @utest_f16i64_mm(half %x) {
990+
; CHECK-LABEL: utest_f16i64_mm:
991991
; CHECK: // %bb.0: // %entry
992992
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
993993
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -1026,6 +1026,29 @@ entry:
10261026
ret i64 %conv6
10271027
}
10281028

1029+
; i32 non saturate
1030+
1031+
define i32 @ustest_f16i32_nsat(half %x) {
1032+
; CHECK-CVT-LABEL: ustest_f16i32_nsat:
1033+
; CHECK-CVT: // %bb.0:
1034+
; CHECK-CVT-NEXT: fcvt s0, h0
1035+
; CHECK-CVT-NEXT: fcvtzs w8, s0
1036+
; CHECK-CVT-NEXT: and w8, w8, w8, asr #31
1037+
; CHECK-CVT-NEXT: bic w0, w8, w8, asr #31
1038+
; CHECK-CVT-NEXT: ret
1039+
;
1040+
; CHECK-FP16-LABEL: ustest_f16i32_nsat:
1041+
; CHECK-FP16: // %bb.0:
1042+
; CHECK-FP16-NEXT: fcvtzs w8, h0
1043+
; CHECK-FP16-NEXT: and w8, w8, w8, asr #31
1044+
; CHECK-FP16-NEXT: bic w0, w8, w8, asr #31
1045+
; CHECK-FP16-NEXT: ret
1046+
%conv = fptosi half %x to i32
1047+
%spec.store.select = call i32 @llvm.smin.i32(i32 0, i32 %conv)
1048+
%spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
1049+
ret i32 %spec.store.select7
1050+
}
1051+
10291052
declare i32 @llvm.smin.i32(i32, i32)
10301053
declare i32 @llvm.smax.i32(i32, i32)
10311054
declare i32 @llvm.umin.i32(i32, i32)

‎llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll‎

Lines changed: 73 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -321,20 +321,20 @@ entry:
321321
ret <4 x i32> %conv6
322322
}
323323

324-
define <4 x i32> @utesth_f16i32(<4 x half> %x) {
325-
; CHECK-CVT-SD-LABEL: utesth_f16i32:
324+
define <4 x i32> @utest_f16i32(<4 x half> %x) {
325+
; CHECK-CVT-SD-LABEL: utest_f16i32:
326326
; CHECK-CVT-SD: // %bb.0: // %entry
327327
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
328328
; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
329329
; CHECK-CVT-SD-NEXT: ret
330330
;
331-
; CHECK-FP16-SD-LABEL: utesth_f16i32:
331+
; CHECK-FP16-SD-LABEL: utest_f16i32:
332332
; CHECK-FP16-SD: // %bb.0: // %entry
333333
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
334334
; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
335335
; CHECK-FP16-SD-NEXT: ret
336336
;
337-
; CHECK-CVT-GI-LABEL: utesth_f16i32:
337+
; CHECK-CVT-GI-LABEL: utest_f16i32:
338338
; CHECK-CVT-GI: // %bb.0: // %entry
339339
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
340340
; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
@@ -349,7 +349,7 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) {
349349
; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
350350
; CHECK-CVT-GI-NEXT: ret
351351
;
352-
; CHECK-FP16-GI-LABEL: utesth_f16i32:
352+
; CHECK-FP16-GI-LABEL: utest_f16i32:
353353
; CHECK-FP16-GI: // %bb.0: // %entry
354354
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
355355
; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
@@ -614,8 +614,8 @@ entry:
614614
ret <8 x i16> %conv6
615615
}
616616

617-
define <8 x i16> @utesth_f16i16(<8 x half> %x) {
618-
; CHECK-CVT-LABEL: utesth_f16i16:
617+
define <8 x i16> @utest_f16i16(<8 x half> %x) {
618+
; CHECK-CVT-LABEL: utest_f16i16:
619619
; CHECK-CVT: // %bb.0: // %entry
620620
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
621621
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
@@ -625,12 +625,12 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) {
625625
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
626626
; CHECK-CVT-NEXT: ret
627627
;
628-
; CHECK-FP16-SD-LABEL: utesth_f16i16:
628+
; CHECK-FP16-SD-LABEL: utest_f16i16:
629629
; CHECK-FP16-SD: // %bb.0: // %entry
630630
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
631631
; CHECK-FP16-SD-NEXT: ret
632632
;
633-
; CHECK-FP16-GI-LABEL: utesth_f16i16:
633+
; CHECK-FP16-GI-LABEL: utest_f16i16:
634634
; CHECK-FP16-GI: // %bb.0: // %entry
635635
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
636636
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
@@ -1746,8 +1746,8 @@ entry:
17461746
ret <2 x i64> %conv6
17471747
}
17481748

1749-
define <2 x i64> @utesth_f16i64(<2 x half> %x) {
1750-
; CHECK-CVT-SD-LABEL: utesth_f16i64:
1749+
define <2 x i64> @utest_f16i64(<2 x half> %x) {
1750+
; CHECK-CVT-SD-LABEL: utest_f16i64:
17511751
; CHECK-CVT-SD: // %bb.0: // %entry
17521752
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
17531753
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
@@ -1777,7 +1777,7 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) {
17771777
; CHECK-CVT-SD-NEXT: add sp, sp, #48
17781778
; CHECK-CVT-SD-NEXT: ret
17791779
;
1780-
; CHECK-FP16-SD-LABEL: utesth_f16i64:
1780+
; CHECK-FP16-SD-LABEL: utest_f16i64:
17811781
; CHECK-FP16-SD: // %bb.0: // %entry
17821782
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
17831783
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
@@ -1807,7 +1807,7 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) {
18071807
; CHECK-FP16-SD-NEXT: add sp, sp, #48
18081808
; CHECK-FP16-SD-NEXT: ret
18091809
;
1810-
; CHECK-CVT-GI-LABEL: utesth_f16i64:
1810+
; CHECK-CVT-GI-LABEL: utest_f16i64:
18111811
; CHECK-CVT-GI: // %bb.0: // %entry
18121812
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
18131813
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
@@ -1819,7 +1819,7 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) {
18191819
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
18201820
; CHECK-CVT-GI-NEXT: ret
18211821
;
1822-
; CHECK-FP16-GI-LABEL: utesth_f16i64:
1822+
; CHECK-FP16-GI-LABEL: utest_f16i64:
18231823
; CHECK-FP16-GI: // %bb.0: // %entry
18241824
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
18251825
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
@@ -2307,20 +2307,20 @@ entry:
23072307
ret <4 x i32> %conv6
23082308
}
23092309

2310-
define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
2311-
; CHECK-CVT-SD-LABEL: utesth_f16i32_mm:
2310+
define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {
2311+
; CHECK-CVT-SD-LABEL: utest_f16i32_mm:
23122312
; CHECK-CVT-SD: // %bb.0: // %entry
23132313
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
23142314
; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
23152315
; CHECK-CVT-SD-NEXT: ret
23162316
;
2317-
; CHECK-FP16-SD-LABEL: utesth_f16i32_mm:
2317+
; CHECK-FP16-SD-LABEL: utest_f16i32_mm:
23182318
; CHECK-FP16-SD: // %bb.0: // %entry
23192319
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
23202320
; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
23212321
; CHECK-FP16-SD-NEXT: ret
23222322
;
2323-
; CHECK-CVT-GI-LABEL: utesth_f16i32_mm:
2323+
; CHECK-CVT-GI-LABEL: utest_f16i32_mm:
23242324
; CHECK-CVT-GI: // %bb.0: // %entry
23252325
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
23262326
; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
@@ -2335,7 +2335,7 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
23352335
; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
23362336
; CHECK-CVT-GI-NEXT: ret
23372337
;
2338-
; CHECK-FP16-GI-LABEL: utesth_f16i32_mm:
2338+
; CHECK-FP16-GI-LABEL: utest_f16i32_mm:
23392339
; CHECK-FP16-GI: // %bb.0: // %entry
23402340
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
23412341
; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
@@ -2585,8 +2585,8 @@ entry:
25852585
ret <8 x i16> %conv6
25862586
}
25872587

2588-
define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
2589-
; CHECK-CVT-LABEL: utesth_f16i16_mm:
2588+
define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
2589+
; CHECK-CVT-LABEL: utest_f16i16_mm:
25902590
; CHECK-CVT: // %bb.0: // %entry
25912591
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
25922592
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
@@ -2596,12 +2596,12 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
25962596
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
25972597
; CHECK-CVT-NEXT: ret
25982598
;
2599-
; CHECK-FP16-SD-LABEL: utesth_f16i16_mm:
2599+
; CHECK-FP16-SD-LABEL: utest_f16i16_mm:
26002600
; CHECK-FP16-SD: // %bb.0: // %entry
26012601
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
26022602
; CHECK-FP16-SD-NEXT: ret
26032603
;
2604-
; CHECK-FP16-GI-LABEL: utesth_f16i16_mm:
2604+
; CHECK-FP16-GI-LABEL: utest_f16i16_mm:
26052605
; CHECK-FP16-GI: // %bb.0: // %entry
26062606
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
26072607
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
@@ -3694,8 +3694,8 @@ entry:
36943694
ret <2 x i64> %conv6
36953695
}
36963696

3697-
define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
3698-
; CHECK-CVT-SD-LABEL: utesth_f16i64_mm:
3697+
define <2 x i64> @utest_f16i64_mm(<2 x half> %x) {
3698+
; CHECK-CVT-SD-LABEL: utest_f16i64_mm:
36993699
; CHECK-CVT-SD: // %bb.0: // %entry
37003700
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
37013701
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
@@ -3725,7 +3725,7 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
37253725
; CHECK-CVT-SD-NEXT: add sp, sp, #48
37263726
; CHECK-CVT-SD-NEXT: ret
37273727
;
3728-
; CHECK-FP16-SD-LABEL: utesth_f16i64_mm:
3728+
; CHECK-FP16-SD-LABEL: utest_f16i64_mm:
37293729
; CHECK-FP16-SD: // %bb.0: // %entry
37303730
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
37313731
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
@@ -3755,7 +3755,7 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
37553755
; CHECK-FP16-SD-NEXT: add sp, sp, #48
37563756
; CHECK-FP16-SD-NEXT: ret
37573757
;
3758-
; CHECK-CVT-GI-LABEL: utesth_f16i64_mm:
3758+
; CHECK-CVT-GI-LABEL: utest_f16i64_mm:
37593759
; CHECK-CVT-GI: // %bb.0: // %entry
37603760
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
37613761
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
@@ -3767,7 +3767,7 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
37673767
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
37683768
; CHECK-CVT-GI-NEXT: ret
37693769
;
3770-
; CHECK-FP16-GI-LABEL: utesth_f16i64_mm:
3770+
; CHECK-FP16-GI-LABEL: utest_f16i64_mm:
37713771
; CHECK-FP16-GI: // %bb.0: // %entry
37723772
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
37733773
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
@@ -3941,6 +3941,51 @@ entry:
39413941
ret <2 x i64> %conv6
39423942
}
39433943

3944+
; i32 non saturate
3945+
3946+
define <4 x i32> @ustest_f16i32_nsat(<4 x half> %x) {
3947+
; CHECK-CVT-SD-LABEL: ustest_f16i32_nsat:
3948+
; CHECK-CVT-SD: // %bb.0: // %entry
3949+
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
3950+
; CHECK-CVT-SD-NEXT: movi v1.2d, #0000000000000000
3951+
; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
3952+
; CHECK-CVT-SD-NEXT: smin v0.4s, v0.4s, v1.4s
3953+
; CHECK-CVT-SD-NEXT: smax v0.4s, v0.4s, v1.4s
3954+
; CHECK-CVT-SD-NEXT: ret
3955+
;
3956+
; CHECK-FP16-SD-LABEL: ustest_f16i32_nsat:
3957+
; CHECK-FP16-SD: // %bb.0: // %entry
3958+
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
3959+
; CHECK-FP16-SD-NEXT: movi v1.2d, #0000000000000000
3960+
; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
3961+
; CHECK-FP16-SD-NEXT: smin v0.4s, v0.4s, v1.4s
3962+
; CHECK-FP16-SD-NEXT: smax v0.4s, v0.4s, v1.4s
3963+
; CHECK-FP16-SD-NEXT: ret
3964+
;
3965+
; CHECK-CVT-GI-LABEL: ustest_f16i32_nsat:
3966+
; CHECK-CVT-GI: // %bb.0: // %entry
3967+
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
3968+
; CHECK-CVT-GI-NEXT: movi v1.2d, #0000000000000000
3969+
; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
3970+
; CHECK-CVT-GI-NEXT: smin v0.4s, v1.4s, v0.4s
3971+
; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
3972+
; CHECK-CVT-GI-NEXT: ret
3973+
;
3974+
; CHECK-FP16-GI-LABEL: ustest_f16i32_nsat:
3975+
; CHECK-FP16-GI: // %bb.0: // %entry
3976+
; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
3977+
; CHECK-FP16-GI-NEXT: movi v1.2d, #0000000000000000
3978+
; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
3979+
; CHECK-FP16-GI-NEXT: smin v0.4s, v1.4s, v0.4s
3980+
; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
3981+
; CHECK-FP16-GI-NEXT: ret
3982+
entry:
3983+
%conv = fptosi <4 x half> %x to <4 x i32>
3984+
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> zeroinitializer, <4 x i32> %conv)
3985+
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
3986+
ret <4 x i32> %spec.store.select7
3987+
}
3988+
39443989
declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)
39453990
declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)
39463991
declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)

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