fixup! Apply pattern to basic case of 4 i64 loads into fpr128 register

Fix condition while checking for the pattern and add a negative test where the pattern is not applied

Author: jcohen-apple

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -7344,7 +7344,7 @@ static bool getLoadPatterns(MachineInstr &Root,
   auto *CurrInstr = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
   SmallSet<unsigned, 4> RemainingLanes({1, 2});
   while (RemainingLanes.begin() != RemainingLanes.end() &&
-         Root.getOpcode() == AArch64::LD1i32 &&
+         CurrInstr->getOpcode() == AArch64::LD1i32 &&
          MRI.hasOneNonDBGUse(CurrInstr->getOperand(0).getReg())) {
     RemainingLanes.erase(CurrInstr->getOperand(2).getImm());
     CurrInstr = MRI.getUniqueVRegDef(CurrInstr->getOperand(1).getReg());

llvm/test/CodeGen/AArch64/aarch64-combine-split-loads.mir

@@ -34,3 +34,19 @@ body:             |
     %9:fpr128 = LD1i32 %8, 3, killed %4
     $q0 = COPY %9
     RET_ReallyLR implicit $q0
+
+---
+name:            negative_pattern
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x1
+
+    ; CHECK-LABEL: name: negative_pattern
+    ; CHECK:      [[LD1:%.*]]:fpr128 = LDRQui $x1, 0
+    ; CHECK-NEXT: [[LD2:%.*]]:fpr128 = LD1i32 [[LD1]]
+  
+    %0:gpr64common = COPY $x0
+    %1:fpr128 = LDRQui $x1, 0
+    %2:fpr128 = LD1i32 %1, 3, %0
+    $q0 = COPY %2
+    RET_ReallyLR implicit $q0