Skip to content

Commit 0f0a89b

Browse files
AZero13AZero13
committed
Convert as many LivePhysRegs uses to LiveRegUnits
1 parent 929ceec commit 0f0a89b

File tree

14 files changed

+101
-110
lines changed

14 files changed

+101
-110
lines changed

‎llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
#include "llvm/ADT/SparseMultiSet.h"
2121
#include "llvm/ADT/SparseSet.h"
2222
#include "llvm/ADT/identity.h"
23-
#include "llvm/CodeGen/LivePhysRegs.h"
23+
#include "llvm/CodeGen/LiveRegUnits.h"
2424
#include "llvm/CodeGen/MachineBasicBlock.h"
2525
#include "llvm/CodeGen/ScheduleDAG.h"
2626
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -263,7 +263,7 @@ namespace llvm {
263263
MachineInstr *FirstDbgValue = nullptr;
264264

265265
/// Set of live physical registers for updating kill flags.
266-
LivePhysRegs LiveRegs;
266+
LiveRegUnits LiveRegs;
267267

268268
public:
269269
explicit ScheduleDAGInstrs(MachineFunction &mf,

‎llvm/lib/CodeGen/ReachingDefAnalysis.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,10 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
#include "llvm/ADT/SmallSet.h"
10-
#include "llvm/ADT/SetOperations.h"
11-
#include "llvm/CodeGen/LivePhysRegs.h"
129
#include "llvm/CodeGen/ReachingDefAnalysis.h"
10+
#include "llvm/ADT/SetOperations.h"
11+
#include "llvm/ADT/SmallSet.h"
12+
#include "llvm/CodeGen/LiveRegUnits.h"
1313
#include "llvm/CodeGen/TargetRegisterInfo.h"
1414
#include "llvm/CodeGen/TargetSubtargetInfo.h"
1515
#include "llvm/Support/Debug.h"
@@ -421,9 +421,9 @@ void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB,
421421
return;
422422

423423
VisitedBBs.insert(MBB);
424-
LivePhysRegs LiveRegs(*TRI);
424+
LiveRegUnits LiveRegs(*TRI);
425425
LiveRegs.addLiveOuts(*MBB);
426-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
426+
if (LiveRegs.available(PhysReg))
427427
return;
428428

429429
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
@@ -469,19 +469,19 @@ MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
469469
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI,
470470
MCRegister PhysReg) const {
471471
MachineBasicBlock *MBB = MI->getParent();
472-
LivePhysRegs LiveRegs(*TRI);
472+
LiveRegUnits LiveRegs(*TRI);
473473
LiveRegs.addLiveOuts(*MBB);
474474

475475
// Yes if the register is live out of the basic block.
476-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
476+
if (!LiveRegs.available(PhysReg))
477477
return true;
478478

479479
// Walk backwards through the block to see if the register is live at some
480480
// point.
481481
for (MachineInstr &Last :
482482
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
483483
LiveRegs.stepBackward(Last);
484-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
484+
if (!LiveRegs.available(PhysReg))
485485
return InstIds.lookup(&Last) > InstIds.lookup(MI);
486486
}
487487
return false;
@@ -504,9 +504,9 @@ bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
504504
bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
505505
MCRegister PhysReg) const {
506506
MachineBasicBlock *MBB = MI->getParent();
507-
LivePhysRegs LiveRegs(*TRI);
507+
LiveRegUnits LiveRegs(*TRI);
508508
LiveRegs.addLiveOuts(*MBB);
509-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
509+
if (LiveRegs.available(PhysReg))
510510
return false;
511511

512512
auto Last = MBB->getLastNonDebugInstr();
@@ -525,9 +525,9 @@ bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
525525
MachineInstr *
526526
ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
527527
MCRegister PhysReg) const {
528-
LivePhysRegs LiveRegs(*TRI);
528+
LiveRegUnits LiveRegs(*TRI);
529529
LiveRegs.addLiveOuts(*MBB);
530-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
530+
if (LiveRegs.available(PhysReg))
531531
return nullptr;
532532

533533
auto Last = MBB->getLastNonDebugInstr();

‎llvm/lib/CodeGen/ScheduleDAGInstrs.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
#include "llvm/Analysis/AliasAnalysis.h"
2222
#include "llvm/Analysis/ValueTracking.h"
2323
#include "llvm/CodeGen/LiveIntervals.h"
24-
#include "llvm/CodeGen/LivePhysRegs.h"
2524
#include "llvm/CodeGen/MachineBasicBlock.h"
2625
#include "llvm/CodeGen/MachineFrameInfo.h"
2726
#include "llvm/CodeGen/MachineFunction.h"
@@ -1103,7 +1102,7 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
11031102
dbgs() << "Loading SUnits:\n"; loads.dump());
11041103
}
11051104

1106-
static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
1105+
static void toggleKills(const MachineRegisterInfo &MRI, LiveRegUnits &LiveRegs,
11071106
MachineInstr &MI, bool addToLiveRegs) {
11081107
for (MachineOperand &MO : MI.operands()) {
11091108
if (!MO.isReg() || !MO.readsReg())
@@ -1113,7 +1112,7 @@ static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
11131112
continue;
11141113

11151114
// Things that are available after the instruction are killed by it.
1116-
bool IsKill = LiveRegs.available(MRI, Reg);
1115+
bool IsKill = LiveRegs.available(Reg);
11171116
MO.setIsKill(IsKill);
11181117
if (addToLiveRegs)
11191118
LiveRegs.addReg(Reg);
@@ -1144,7 +1143,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
11441143
continue;
11451144
LiveRegs.removeReg(Reg);
11461145
} else if (MO.isRegMask()) {
1147-
LiveRegs.removeRegsInMask(MO);
1146+
LiveRegs.removeRegsNotPreserved(MO.getRegMask());
11481147
}
11491148
}
11501149

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp‎

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,7 @@
197197
#include "llvm/ADT/SmallVector.h"
198198
#include "llvm/ADT/Statistic.h"
199199
#include "llvm/CodeGen/LivePhysRegs.h"
200+
#include "llvm/CodeGen/LiveRegUnits.h"
200201
#include "llvm/CodeGen/MachineBasicBlock.h"
201202
#include "llvm/CodeGen/MachineFrameInfo.h"
202203
#include "llvm/CodeGen/MachineFunction.h"
@@ -988,7 +989,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
988989
}
989990
}
990991

991-
static void getLiveRegsForEntryMBB(LivePhysRegs &LiveRegs,
992+
static void getLiveRegsForEntryMBB(LiveRegUnits &LiveRegs,
992993
const MachineBasicBlock &MBB) {
993994
const MachineFunction *MF = MBB.getParent();
994995
LiveRegs.addLiveIns(MBB);
@@ -1018,16 +1019,15 @@ static Register findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {
10181019

10191020
const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
10201021
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
1021-
LivePhysRegs LiveRegs(TRI);
1022+
LiveRegUnits LiveRegs(TRI);
10221023
getLiveRegsForEntryMBB(LiveRegs, *MBB);
10231024

10241025
// Prefer X9 since it was historically used for the prologue scratch reg.
1025-
const MachineRegisterInfo &MRI = MF->getRegInfo();
1026-
if (LiveRegs.available(MRI, AArch64::X9))
1026+
if (LiveRegs.available(AArch64::X9))
10271027
return AArch64::X9;
10281028

1029-
for (unsigned Reg : AArch64::GPR64RegClass) {
1030-
if (LiveRegs.available(MRI, Reg))
1029+
for (Register Reg : AArch64::GPR64RegClass) {
1030+
if (LiveRegs.available(Reg))
10311031
return Reg;
10321032
}
10331033
return AArch64::NoRegister;
@@ -1044,13 +1044,11 @@ bool AArch64FrameLowering::canUseAsPrologue(
10441044

10451045
if (AFI->hasSwiftAsyncContext()) {
10461046
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
1047-
const MachineRegisterInfo &MRI = MF->getRegInfo();
1048-
LivePhysRegs LiveRegs(TRI);
1047+
LiveRegUnits LiveRegs(TRI);
10491048
getLiveRegsForEntryMBB(LiveRegs, MBB);
10501049
// The StoreSwiftAsyncContext clobbers X16 and X17. Make sure they are
10511050
// available.
1052-
if (!LiveRegs.available(MRI, AArch64::X16) ||
1053-
!LiveRegs.available(MRI, AArch64::X17))
1051+
if (!LiveRegs.available(AArch64::X16) || !LiveRegs.available(AArch64::X17))
10541052
return false;
10551053
}
10561054

@@ -1603,7 +1601,7 @@ static void emitDefineCFAWithFP(MachineFunction &MF, MachineBasicBlock &MBB,
16031601
/// Collect live registers from the end of \p MI's parent up to (including) \p
16041602
/// MI in \p LiveRegs.
16051603
static void getLivePhysRegsUpTo(MachineInstr &MI, const TargetRegisterInfo &TRI,
1606-
LivePhysRegs &LiveRegs) {
1604+
LiveRegUnits &LiveRegs) {
16071605

16081606
MachineBasicBlock &MBB = *MI.getParent();
16091607
LiveRegs.addLiveOuts(MBB);
@@ -1641,7 +1639,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
16411639
NonFrameStart->getFlag(MachineInstr::FrameSetup))
16421640
++NonFrameStart;
16431641

1644-
LivePhysRegs LiveRegs(*TRI);
1642+
LiveRegUnits LiveRegs(*TRI);
16451643
if (NonFrameStart != MBB.end()) {
16461644
getLivePhysRegsUpTo(*NonFrameStart, *TRI, LiveRegs);
16471645
// Ignore registers used for stack management for now.
@@ -1659,7 +1657,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
16591657
make_range(MBB.instr_begin(), NonFrameStart->getIterator())) {
16601658
for (auto &Op : MI.operands())
16611659
if (Op.isReg() && Op.isDef())
1662-
assert(!LiveRegs.contains(Op.getReg()) &&
1660+
assert(LiveRegs.available(Op.getReg()) &&
16631661
"live register clobbered by inserted prologue instructions");
16641662
}
16651663
});
@@ -4014,7 +4012,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
40144012
// FIXME : This approach of bailing out from merge is conservative in
40154013
// some ways like even if stg loops are not present after merge the
40164014
// insert list, this liveness check is done (which is not needed).
4017-
LivePhysRegs LiveRegs(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
4015+
LiveRegUnits LiveRegs(*(MBB->getParent()->getSubtarget().getRegisterInfo()));
40184016
LiveRegs.addLiveOuts(*MBB);
40194017
for (auto I = MBB->rbegin();; ++I) {
40204018
MachineInstr &MI = *I;
@@ -4023,7 +4021,7 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
40234021
LiveRegs.stepBackward(*I);
40244022
}
40254023
InsertI++;
4026-
if (LiveRegs.contains(AArch64::NZCV))
4024+
if (!LiveRegs.available(AArch64::NZCV))
40274025
return InsertI;
40284026

40294027
llvm::stable_sort(Instrs,

‎llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1212
#include "SIRegisterInfo.h"
1313
#include "llvm/ADT/SmallVector.h"
14-
#include "llvm/CodeGen/LivePhysRegs.h"
14+
#include "llvm/CodeGen/LiveRegUnits.h"
1515
#include "llvm/CodeGen/MachineFunctionPass.h"
1616
#include "llvm/CodeGen/MachineOperand.h"
1717
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -313,7 +313,7 @@ MachineBasicBlock::reverse_iterator SIOptimizeExecMasking::findExecCopy(
313313
return E;
314314
}
315315

316-
// XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
316+
// XXX - Seems LiveRegUnits doesn't work correctly since it will incorrectly
317317
// report the register as unavailable because a super-register with a lane mask
318318
// is unavailable.
319319
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
@@ -383,7 +383,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
383383
MCRegister Reg,
384384
bool UseLiveOuts,
385385
bool IgnoreStart) const {
386-
LivePhysRegs LR(*TRI);
386+
LiveRegUnits LR(*TRI);
387387
if (UseLiveOuts)
388388
LR.addLiveOuts(*Stop.getParent());
389389

@@ -396,7 +396,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
396396
LR.stepBackward(*A);
397397
}
398398

399-
return !LR.available(*MRI, Reg);
399+
return !LR.available(Reg);
400400
}
401401

402402
// Determine if a register Reg is not re-defined and still in use

‎llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#include "llvm/ADT/Statistic.h"
3232
#include "llvm/ADT/iterator_range.h"
3333
#include "llvm/Analysis/AliasAnalysis.h"
34-
#include "llvm/CodeGen/LivePhysRegs.h"
34+
#include "llvm/CodeGen/LiveRegUnits.h"
3535
#include "llvm/CodeGen/MachineBasicBlock.h"
3636
#include "llvm/CodeGen/MachineDominators.h"
3737
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -109,7 +109,7 @@ namespace {
109109
const ARMSubtarget *STI;
110110
const TargetLowering *TL;
111111
ARMFunctionInfo *AFI;
112-
LivePhysRegs LiveRegs;
112+
LiveRegUnits LiveRegs;
113113
RegisterClassInfo RegClassInfo;
114114
MachineBasicBlock::const_iterator LiveRegPos;
115115
bool LiveRegsValid;
@@ -589,7 +589,7 @@ unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
589589
}
590590

591591
for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
592-
if (LiveRegs.available(MF->getRegInfo(), Reg))
592+
if (LiveRegs.available(Reg))
593593
return Reg;
594594
return 0;
595595
}

‎llvm/lib/Target/ARM/Thumb1FrameLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -612,11 +612,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
612612

613613
static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
614614
const BitVector &PopFriendly,
615-
const LivePhysRegs &UsedRegs, unsigned &PopReg,
615+
const LiveRegUnits &UsedRegs, unsigned &PopReg,
616616
unsigned &TmpReg, MachineRegisterInfo &MRI) {
617617
PopReg = TmpReg = 0;
618618
for (auto Reg : GPRsNoLRSP.set_bits()) {
619-
if (UsedRegs.available(MRI, Reg)) {
619+
if (UsedRegs.available(Reg)) {
620620
// Remember the first pop-friendly register and exit.
621621
if (PopFriendly.test(Reg)) {
622622
PopReg = Reg;
@@ -684,7 +684,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
684684
// Look for a temporary register to use.
685685
// First, compute the liveness information.
686686
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
687-
LivePhysRegs UsedRegs(TRI);
687+
LiveRegUnits UsedRegs(TRI);
688688
UsedRegs.addLiveOuts(MBB);
689689
// The semantic of pristines changed recently and now,
690690
// the callee-saved registers that are touched in the function

‎llvm/lib/Target/SystemZ/SystemZElimCompare.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
#include "llvm/ADT/SmallVector.h"
1919
#include "llvm/ADT/Statistic.h"
2020
#include "llvm/ADT/StringRef.h"
21-
#include "llvm/CodeGen/LivePhysRegs.h"
21+
#include "llvm/CodeGen/LiveRegUnits.h"
2222
#include "llvm/CodeGen/MachineBasicBlock.h"
2323
#include "llvm/CodeGen/MachineFunction.h"
2424
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -690,9 +690,9 @@ bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) {
690690
// Walk backwards through the block looking for comparisons, recording
691691
// all CC users as we go. The subroutines can delete Compare and
692692
// instructions before it.
693-
LivePhysRegs LiveRegs(*TRI);
693+
LiveRegUnits LiveRegs(*TRI);
694694
LiveRegs.addLiveOuts(MBB);
695-
bool CompleteCCUsers = !LiveRegs.contains(SystemZ::CC);
695+
bool CompleteCCUsers = LiveRegs.available(SystemZ::CC);
696696
SmallVector<MachineInstr *, 4> CCUsers;
697697
MachineBasicBlock::iterator MBBI = MBB.end();
698698
while (MBBI != MBB.begin()) {

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
#include "llvm/ADT/Statistic.h"
1919
#include "llvm/CodeGen/LiveInterval.h"
2020
#include "llvm/CodeGen/LiveIntervals.h"
21-
#include "llvm/CodeGen/LivePhysRegs.h"
21+
#include "llvm/CodeGen/LiveRegUnits.h"
2222
#include "llvm/CodeGen/LiveVariables.h"
2323
#include "llvm/CodeGen/MachineBasicBlock.h"
2424
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -1874,9 +1874,9 @@ prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
18741874
}
18751875
}
18761876
if (CCLive) {
1877-
LivePhysRegs LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
1877+
LiveRegUnits LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
18781878
LiveRegs.addLiveOuts(*MBB);
1879-
if (LiveRegs.contains(SystemZ::CC))
1879+
if (!LiveRegs.available(SystemZ::CC))
18801880
return false;
18811881
}
18821882

‎llvm/lib/Target/SystemZ/SystemZShortenInst.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
//===----------------------------------------------------------------------===//
1414

1515
#include "SystemZTargetMachine.h"
16-
#include "llvm/CodeGen/LivePhysRegs.h"
16+
#include "llvm/CodeGen/LiveRegUnits.h"
1717
#include "llvm/CodeGen/MachineFunctionPass.h"
1818
#include "llvm/CodeGen/MachineInstrBuilder.h"
1919
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -46,7 +46,7 @@ class SystemZShortenInst : public MachineFunctionPass {
4646

4747
const SystemZInstrInfo *TII;
4848
const TargetRegisterInfo *TRI;
49-
LivePhysRegs LiveRegs;
49+
LiveRegUnits LiveRegs;
5050
};
5151

5252
char SystemZShortenInst::ID = 0;
@@ -88,7 +88,7 @@ bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
8888
unsigned GR64BitReg =
8989
TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
9090
Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
91-
if (LiveRegs.contains(OtherReg))
91+
if (!LiveRegs.available(OtherReg))
9292
return false;
9393

9494
uint64_t Imm = MI.getOperand(1).getImm();
@@ -143,7 +143,7 @@ bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
143143
// Calls shortenOn001 if CCLive is false. CC def operand is added in
144144
// case of success.
145145
bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
146-
if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
146+
if (LiveRegs.available(SystemZ::CC) && shortenOn001(MI, Opcode)) {
147147
MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
148148
.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
149149
return true;

0 commit comments

Comments
 (0)