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[RISCV] Support scalar llvm.fmodf intrinsic. (#161743)
1 parent e7f47e7 commit 0efc083

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10 files changed

+511
-4
lines changed

10 files changed

+511
-4
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -629,7 +629,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
629629
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FTAN, G_FPOW, G_FLOG, G_FLOG2,
630630
G_FLOG10, G_FEXP, G_FEXP2, G_FEXP10, G_FACOS,
631631
G_FASIN, G_FATAN, G_FATAN2, G_FCOSH, G_FSINH,
632-
G_FTANH})
632+
G_FTANH, G_FMODF})
633633
.libcallFor({s32, s64})
634634
.libcallFor(ST.is64Bit(), {s128});
635635
getActionDefinitionsBuilder({G_FPOWI, G_FLDEXP})

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -533,7 +533,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
533533
setOperationAction({ISD::FREM, ISD::FPOW, ISD::FPOWI,
534534
ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP,
535535
ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
536-
ISD::FLOG10, ISD::FLDEXP, ISD::FFREXP},
536+
ISD::FLOG10, ISD::FLDEXP, ISD::FFREXP, ISD::FMODF},
537537
MVT::f16, Promote);
538538

539539
// FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have

‎llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1420,3 +1420,61 @@ define double @tanh_f64(double %a) nounwind {
14201420
%1 = call double @llvm.tanh.f64(double %a)
14211421
ret double %1
14221422
}
1423+
1424+
define { double, double } @test_modf_f64(double %a) nounwind {
1425+
; RV32IFD-LABEL: test_modf_f64:
1426+
; RV32IFD: # %bb.0:
1427+
; RV32IFD-NEXT: addi sp, sp, -16
1428+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1429+
; RV32IFD-NEXT: mv a0, sp
1430+
; RV32IFD-NEXT: call modf
1431+
; RV32IFD-NEXT: fld fa1, 0(sp)
1432+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1433+
; RV32IFD-NEXT: addi sp, sp, 16
1434+
; RV32IFD-NEXT: ret
1435+
;
1436+
; RV64IFD-LABEL: test_modf_f64:
1437+
; RV64IFD: # %bb.0:
1438+
; RV64IFD-NEXT: addi sp, sp, -16
1439+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1440+
; RV64IFD-NEXT: mv a0, sp
1441+
; RV64IFD-NEXT: call modf
1442+
; RV64IFD-NEXT: fld fa1, 0(sp)
1443+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1444+
; RV64IFD-NEXT: addi sp, sp, 16
1445+
; RV64IFD-NEXT: ret
1446+
;
1447+
; RV32I-LABEL: test_modf_f64:
1448+
; RV32I: # %bb.0:
1449+
; RV32I-NEXT: addi sp, sp, -16
1450+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1451+
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1452+
; RV32I-NEXT: mv s0, a0
1453+
; RV32I-NEXT: mv a0, a1
1454+
; RV32I-NEXT: mv a1, a2
1455+
; RV32I-NEXT: mv a2, sp
1456+
; RV32I-NEXT: call modf
1457+
; RV32I-NEXT: lw a2, 0(sp)
1458+
; RV32I-NEXT: lw a3, 4(sp)
1459+
; RV32I-NEXT: sw a0, 0(s0)
1460+
; RV32I-NEXT: sw a1, 4(s0)
1461+
; RV32I-NEXT: sw a2, 8(s0)
1462+
; RV32I-NEXT: sw a3, 12(s0)
1463+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1464+
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1465+
; RV32I-NEXT: addi sp, sp, 16
1466+
; RV32I-NEXT: ret
1467+
;
1468+
; RV64I-LABEL: test_modf_f64:
1469+
; RV64I: # %bb.0:
1470+
; RV64I-NEXT: addi sp, sp, -16
1471+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1472+
; RV64I-NEXT: mv a1, sp
1473+
; RV64I-NEXT: call modf
1474+
; RV64I-NEXT: ld a1, 0(sp)
1475+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1476+
; RV64I-NEXT: addi sp, sp, 16
1477+
; RV64I-NEXT: ret
1478+
%result = call { double, double } @llvm.modf.f64(double %a)
1479+
ret { double, double } %result
1480+
}

‎llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2118,3 +2118,62 @@ define float @tanh_f32(float %a) nounwind {
21182118
%1 = call float @llvm.tanh.f32(float %a)
21192119
ret float %1
21202120
}
2121+
2122+
define { float, float } @test_modf_f32(float %a) nounwind {
2123+
; RV32IF-LABEL: test_modf_f32:
2124+
; RV32IF: # %bb.0:
2125+
; RV32IF-NEXT: addi sp, sp, -16
2126+
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2127+
; RV32IF-NEXT: addi a0, sp, 8
2128+
; RV32IF-NEXT: call modff
2129+
; RV32IF-NEXT: flw fa1, 8(sp)
2130+
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2131+
; RV32IF-NEXT: addi sp, sp, 16
2132+
; RV32IF-NEXT: ret
2133+
;
2134+
; RV64IF-LABEL: test_modf_f32:
2135+
; RV64IF: # %bb.0:
2136+
; RV64IF-NEXT: addi sp, sp, -16
2137+
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2138+
; RV64IF-NEXT: addi a0, sp, 4
2139+
; RV64IF-NEXT: call modff
2140+
; RV64IF-NEXT: flw fa1, 4(sp)
2141+
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2142+
; RV64IF-NEXT: addi sp, sp, 16
2143+
; RV64IF-NEXT: ret
2144+
;
2145+
; RV64IFD-LABEL: test_modf_f32:
2146+
; RV64IFD: # %bb.0:
2147+
; RV64IFD-NEXT: addi sp, sp, -16
2148+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2149+
; RV64IFD-NEXT: addi a0, sp, 4
2150+
; RV64IFD-NEXT: call modff
2151+
; RV64IFD-NEXT: flw fa1, 4(sp)
2152+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2153+
; RV64IFD-NEXT: addi sp, sp, 16
2154+
; RV64IFD-NEXT: ret
2155+
;
2156+
; RV32I-LABEL: test_modf_f32:
2157+
; RV32I: # %bb.0:
2158+
; RV32I-NEXT: addi sp, sp, -16
2159+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2160+
; RV32I-NEXT: addi a1, sp, 8
2161+
; RV32I-NEXT: call modff
2162+
; RV32I-NEXT: lw a1, 8(sp)
2163+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2164+
; RV32I-NEXT: addi sp, sp, 16
2165+
; RV32I-NEXT: ret
2166+
;
2167+
; RV64I-LABEL: test_modf_f32:
2168+
; RV64I: # %bb.0:
2169+
; RV64I-NEXT: addi sp, sp, -16
2170+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2171+
; RV64I-NEXT: addi a1, sp, 4
2172+
; RV64I-NEXT: call modff
2173+
; RV64I-NEXT: lw a1, 4(sp)
2174+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2175+
; RV64I-NEXT: addi sp, sp, 16
2176+
; RV64I-NEXT: ret
2177+
%result = call { float, float } @llvm.modf.f32(float %a)
2178+
ret { float, float } %result
2179+
}

‎llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -911,3 +911,28 @@ define fp128 @tanh(fp128 %a) nounwind {
911911
%1 = call fp128 @llvm.tanh.f128(fp128 %a)
912912
ret fp128 %1
913913
}
914+
915+
define { fp128, fp128 } @modf(fp128 %a) nounwind {
916+
; CHECK-LABEL: modf:
917+
; CHECK: # %bb.0:
918+
; CHECK-NEXT: addi sp, sp, -32
919+
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
920+
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
921+
; CHECK-NEXT: mv s0, a0
922+
; CHECK-NEXT: mv a0, a1
923+
; CHECK-NEXT: mv a1, a2
924+
; CHECK-NEXT: mv a2, sp
925+
; CHECK-NEXT: call modfl
926+
; CHECK-NEXT: ld a2, 0(sp)
927+
; CHECK-NEXT: ld a3, 8(sp)
928+
; CHECK-NEXT: sd a0, 0(s0)
929+
; CHECK-NEXT: sd a1, 8(s0)
930+
; CHECK-NEXT: sd a2, 16(s0)
931+
; CHECK-NEXT: sd a3, 24(s0)
932+
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
933+
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
934+
; CHECK-NEXT: addi sp, sp, 32
935+
; CHECK-NEXT: ret
936+
%result = call { fp128, fp128 } @llvm.modf.f128(fp128 %a)
937+
ret { fp128, fp128 } %result
938+
}

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -506,8 +506,9 @@
506506
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
507507
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
508508
# DEBUG-NEXT: G_FMODF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
509-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
510-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
509+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
510+
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
511+
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
511512
# DEBUG-NEXT: G_FPOW (opcode {{[0-9]+}}): 1 type index, 0 imm indices
512513
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
513514
# DEBUG-NEXT: .. the first uncovered type index: 1, OK

‎llvm/test/CodeGen/RISCV/double-intrinsics.ll‎

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2109,3 +2109,85 @@ define double @tanh_f64(double %a) nounwind {
21092109
%1 = call double @llvm.tanh.f64(double %a)
21102110
ret double %1
21112111
}
2112+
2113+
define { double, double } @test_modf_f64(double %a) nounwind {
2114+
; RV32IFD-LABEL: test_modf_f64:
2115+
; RV32IFD: # %bb.0:
2116+
; RV32IFD-NEXT: addi sp, sp, -16
2117+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2118+
; RV32IFD-NEXT: mv a0, sp
2119+
; RV32IFD-NEXT: call modf
2120+
; RV32IFD-NEXT: fld fa1, 0(sp)
2121+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2122+
; RV32IFD-NEXT: addi sp, sp, 16
2123+
; RV32IFD-NEXT: ret
2124+
;
2125+
; RV64IFD-LABEL: test_modf_f64:
2126+
; RV64IFD: # %bb.0:
2127+
; RV64IFD-NEXT: addi sp, sp, -16
2128+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2129+
; RV64IFD-NEXT: mv a0, sp
2130+
; RV64IFD-NEXT: call modf
2131+
; RV64IFD-NEXT: fld fa1, 0(sp)
2132+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2133+
; RV64IFD-NEXT: addi sp, sp, 16
2134+
; RV64IFD-NEXT: ret
2135+
;
2136+
; RV32IZFINXZDINX-LABEL: test_modf_f64:
2137+
; RV32IZFINXZDINX: # %bb.0:
2138+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
2139+
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2140+
; RV32IZFINXZDINX-NEXT: mv a2, sp
2141+
; RV32IZFINXZDINX-NEXT: call modf
2142+
; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
2143+
; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
2144+
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2145+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
2146+
; RV32IZFINXZDINX-NEXT: ret
2147+
;
2148+
; RV64IZFINXZDINX-LABEL: test_modf_f64:
2149+
; RV64IZFINXZDINX: # %bb.0:
2150+
; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
2151+
; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2152+
; RV64IZFINXZDINX-NEXT: mv a1, sp
2153+
; RV64IZFINXZDINX-NEXT: call modf
2154+
; RV64IZFINXZDINX-NEXT: ld a1, 0(sp)
2155+
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2156+
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
2157+
; RV64IZFINXZDINX-NEXT: ret
2158+
;
2159+
; RV32I-LABEL: test_modf_f64:
2160+
; RV32I: # %bb.0:
2161+
; RV32I-NEXT: addi sp, sp, -16
2162+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2163+
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2164+
; RV32I-NEXT: mv a3, a2
2165+
; RV32I-NEXT: mv s0, a0
2166+
; RV32I-NEXT: mv a2, sp
2167+
; RV32I-NEXT: mv a0, a1
2168+
; RV32I-NEXT: mv a1, a3
2169+
; RV32I-NEXT: call modf
2170+
; RV32I-NEXT: lw a2, 0(sp)
2171+
; RV32I-NEXT: lw a3, 4(sp)
2172+
; RV32I-NEXT: sw a0, 0(s0)
2173+
; RV32I-NEXT: sw a1, 4(s0)
2174+
; RV32I-NEXT: sw a2, 8(s0)
2175+
; RV32I-NEXT: sw a3, 12(s0)
2176+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2177+
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2178+
; RV32I-NEXT: addi sp, sp, 16
2179+
; RV32I-NEXT: ret
2180+
;
2181+
; RV64I-LABEL: test_modf_f64:
2182+
; RV64I: # %bb.0:
2183+
; RV64I-NEXT: addi sp, sp, -16
2184+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2185+
; RV64I-NEXT: mv a1, sp
2186+
; RV64I-NEXT: call modf
2187+
; RV64I-NEXT: ld a1, 0(sp)
2188+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2189+
; RV64I-NEXT: addi sp, sp, 16
2190+
; RV64I-NEXT: ret
2191+
%result = call { double, double } @llvm.modf.f64(double %a)
2192+
ret { double, double } %result
2193+
}

‎llvm/test/CodeGen/RISCV/float-intrinsics.ll‎

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3050,3 +3050,84 @@ define float @tanh_f32(float %a) nounwind {
30503050
%1 = call float @llvm.tanh.f32(float %a)
30513051
ret float %1
30523052
}
3053+
3054+
define { float, float } @test_modf_f32(float %a) nounwind {
3055+
; RV32IF-LABEL: test_modf_f32:
3056+
; RV32IF: # %bb.0:
3057+
; RV32IF-NEXT: addi sp, sp, -16
3058+
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3059+
; RV32IF-NEXT: addi a0, sp, 8
3060+
; RV32IF-NEXT: call modff
3061+
; RV32IF-NEXT: flw fa1, 8(sp)
3062+
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3063+
; RV32IF-NEXT: addi sp, sp, 16
3064+
; RV32IF-NEXT: ret
3065+
;
3066+
; RV32IZFINX-LABEL: test_modf_f32:
3067+
; RV32IZFINX: # %bb.0:
3068+
; RV32IZFINX-NEXT: addi sp, sp, -16
3069+
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3070+
; RV32IZFINX-NEXT: addi a1, sp, 8
3071+
; RV32IZFINX-NEXT: call modff
3072+
; RV32IZFINX-NEXT: lw a1, 8(sp)
3073+
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3074+
; RV32IZFINX-NEXT: addi sp, sp, 16
3075+
; RV32IZFINX-NEXT: ret
3076+
;
3077+
; RV64IF-LABEL: test_modf_f32:
3078+
; RV64IF: # %bb.0:
3079+
; RV64IF-NEXT: addi sp, sp, -16
3080+
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3081+
; RV64IF-NEXT: addi a0, sp, 4
3082+
; RV64IF-NEXT: call modff
3083+
; RV64IF-NEXT: flw fa1, 4(sp)
3084+
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3085+
; RV64IF-NEXT: addi sp, sp, 16
3086+
; RV64IF-NEXT: ret
3087+
;
3088+
; RV64IZFINX-LABEL: test_modf_f32:
3089+
; RV64IZFINX: # %bb.0:
3090+
; RV64IZFINX-NEXT: addi sp, sp, -16
3091+
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3092+
; RV64IZFINX-NEXT: addi a1, sp, 4
3093+
; RV64IZFINX-NEXT: call modff
3094+
; RV64IZFINX-NEXT: lw a1, 4(sp)
3095+
; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3096+
; RV64IZFINX-NEXT: addi sp, sp, 16
3097+
; RV64IZFINX-NEXT: ret
3098+
;
3099+
; RV64IFD-LABEL: test_modf_f32:
3100+
; RV64IFD: # %bb.0:
3101+
; RV64IFD-NEXT: addi sp, sp, -16
3102+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3103+
; RV64IFD-NEXT: addi a0, sp, 4
3104+
; RV64IFD-NEXT: call modff
3105+
; RV64IFD-NEXT: flw fa1, 4(sp)
3106+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3107+
; RV64IFD-NEXT: addi sp, sp, 16
3108+
; RV64IFD-NEXT: ret
3109+
;
3110+
; RV32I-LABEL: test_modf_f32:
3111+
; RV32I: # %bb.0:
3112+
; RV32I-NEXT: addi sp, sp, -16
3113+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3114+
; RV32I-NEXT: addi a1, sp, 8
3115+
; RV32I-NEXT: call modff
3116+
; RV32I-NEXT: lw a1, 8(sp)
3117+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3118+
; RV32I-NEXT: addi sp, sp, 16
3119+
; RV32I-NEXT: ret
3120+
;
3121+
; RV64I-LABEL: test_modf_f32:
3122+
; RV64I: # %bb.0:
3123+
; RV64I-NEXT: addi sp, sp, -16
3124+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3125+
; RV64I-NEXT: addi a1, sp, 4
3126+
; RV64I-NEXT: call modff
3127+
; RV64I-NEXT: lw a1, 4(sp)
3128+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3129+
; RV64I-NEXT: addi sp, sp, 16
3130+
; RV64I-NEXT: ret
3131+
%result = call { float, float } @llvm.modf.f32(float %a)
3132+
ret { float, float } %result
3133+
}

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