[gn] port 32dffdc (more RISCV depedency things)

Looks like RISCV is picking up AMDGPU's bad habits wrt generated files.

Author: nico

llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

@@ -72,6 +72,7 @@ tablegen("RISCVGenPostLegalizeGICombiner") {
 tablegen("RISCVGenRegisterBank") {
   visibility = [
     ":LLVMRISCVCodeGen",
+    "MCA",
     "//llvm/tools/llvm-exegesis/lib/RISCV",
   ]
   args = [ "-gen-register-bank" ]

llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn

@@ -8,6 +8,10 @@ static_library("MCA") {
     "//llvm/lib/Support",
     "//llvm/lib/Target/RISCV/MCTargetDesc",
     "//llvm/lib/Target/RISCV/TargetInfo",
+
+    # RISCVCustomBehaviour.cpp after 32dffdce0511 includes
+    # RISCVGenRegisterBank.inc via RISCVSubtarget.h :/
+    "../:RISCVGenRegisterBank",
   ]
   include_dirs = [ ".." ]
   sources = [ "RISCVCustomBehaviour.cpp" ]