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[Sparc] Replace some CAS instructions with InstAlias (#65588)
According to the manual, cas, casl, casx and casxl are synthetic instructions. They map to casa and casxa with certain ASI tags.
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5 files changed

+38
-57
lines changed

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td‎

Lines changed: 3 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -476,21 +476,6 @@ def SETHIXi : F2_1<0b100,
476476

477477
// ATOMICS.
478478
let Predicates = [Is64Bit, HasV9], Constraints = "$swap = $rd" in {
479-
let asi = 0b10000000 in
480-
def CASXrr: F3_1_asi<3, 0b111110,
481-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
482-
I64Regs:$swap),
483-
"casx [$rs1], $rs2, $rd",
484-
[(set i64:$rd,
485-
(atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
486-
487-
let asi = 0b10001000 in
488-
def CASXLrr: F3_1_asi<3, 0b111110,
489-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
490-
I64Regs:$swap),
491-
"casxl [$rs1], $rs2, $rd",
492-
[]>;
493-
494479
def CASXArr: F3_1_asi<3, 0b111110,
495480
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
496481
I64Regs:$swap, ASITag:$asi),
@@ -515,6 +500,9 @@ def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
515500
def : Pat<(atomic_store_64 i64:$val, ADDRrr:$dst), (STXrr ADDRrr:$dst, $val)>;
516501
def : Pat<(atomic_store_64 i64:$val, ADDRri:$dst), (STXri ADDRri:$dst, $val)>;
517502

503+
def : Pat<(atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap),
504+
(CASXArr $rs1, $rs2, $swap, 0x80)>;
505+
518506
} // Predicates = [Is64Bit]
519507

520508
let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in

‎llvm/lib/Target/Sparc/SparcInstrAliases.td‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -464,6 +464,24 @@ def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
464464
// neg reg, rd -> sub %g0, reg, rd
465465
def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
466466

467+
let Predicates = [HasV9] in {
468+
// cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
469+
def : InstAlias<"cas [$rs1], $rs2, $rd",
470+
(CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;
471+
472+
// casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
473+
def : InstAlias<"casl [$rs1], $rs2, $rd",
474+
(CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;
475+
476+
// casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
477+
def : InstAlias<"casx [$rs1], $rs2, $rd",
478+
(CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;
479+
480+
// casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
481+
def : InstAlias<"casxl [$rs1], $rs2, $rd",
482+
(CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;
483+
}
484+
467485
// inc rd -> add rd, 1, rd
468486
def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
469487

‎llvm/lib/Target/Sparc/SparcInstrInfo.td‎

Lines changed: 9 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1703,41 +1703,7 @@ let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
17031703
(ins simm13Op:$simm13),
17041704
"sir $simm13", []>;
17051705

1706-
// The CAS instruction, unlike other instructions, only comes in a
1707-
// form which requires an ASI be provided.
1708-
let Predicates = [HasV9], Constraints = "$swap = $rd" in {
1709-
// The ASI value hardcoded here is ASI_PRIMARY, the default
1710-
// unprivileged ASI for SparcV9.
1711-
let asi = 0b10000000 in
1712-
def CASrr: F3_1_asi<3, 0b111100,
1713-
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1714-
IntRegs:$swap),
1715-
"cas [$rs1], $rs2, $rd",
1716-
[(set i32:$rd,
1717-
(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1718-
1719-
// SparcV9 also specifies a CASL alias, which uses ASI_PRIMARY_LITTLE.
1720-
let asi = 0b10001000 in
1721-
def CASLrr: F3_1_asi<3, 0b111100,
1722-
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1723-
IntRegs:$swap),
1724-
"casl [$rs1], $rs2, $rd",
1725-
[]>;
1726-
}
1727-
1728-
// CASA is supported as an instruction on some LEON3 and all LEON4 processors.
1729-
// This version can be automatically lowered from C code, selecting ASI 10
1730-
let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
1731-
def CASAasi10: F3_1_asi<3, 0b111100,
1732-
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1733-
IntRegs:$swap),
1734-
"casa [$rs1] 10, $rs2, $rd",
1735-
[(set i32:$rd,
1736-
(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1737-
17381706
// CASA supported on all V9, some LEON3 and all LEON4 processors.
1739-
// Same pattern as CASrr above, but with a different ASI.
1740-
// This version is supported for inline assembly lowering only.
17411707
let Predicates = [HasCASA], Constraints = "$swap = $rd" in
17421708
def CASArr: F3_1_asi<3, 0b111100,
17431709
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
@@ -1938,6 +1904,15 @@ def : Pat<(atomic_store_16 i32:$val, ADDRri:$dst), (STHri ADDRri:$dst, $val)>;
19381904
def : Pat<(atomic_store_32 i32:$val, ADDRrr:$dst), (STrr ADDRrr:$dst, $val)>;
19391905
def : Pat<(atomic_store_32 i32:$val, ADDRri:$dst), (STri ADDRri:$dst, $val)>;
19401906

1907+
let Predicates = [HasV9] in
1908+
def : Pat<(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap),
1909+
(CASArr $rs1, $rs2, $swap, 0x80)>;
1910+
1911+
// Same pattern as CASArr above, but with a different ASI.
1912+
let Predicates = [HasLeonCASA] in
1913+
def : Pat<(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap),
1914+
(CASArr $rs1, $rs2, $swap, 0x0A)>;
1915+
19411916
// A register pair with zero upper half.
19421917
// The upper part is done with ORrr instead of `COPY G0`
19431918
// or a normal register copy, since `COPY G0`s in that place

‎llvm/test/MC/Sparc/sparc-cas-instructions.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,12 @@ casxl [%i0], %l6, %o2
2828
casxa [%i0] %asi, %l6, %o2
2929

3030
! V8: error: instruction requires a CPU feature not currently enabled
31-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
31+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
3232
! LEON: error: instruction requires a CPU feature not currently enabled
3333
casxa [%i0] 0x80, %l6, %o2
3434

3535
! V8: error: instruction requires a CPU feature not currently enabled
36-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
36+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
3737
! LEON: error: instruction requires a CPU feature not currently enabled
3838
casxa [%i0] (0x40+0x40), %l6, %o2
3939

@@ -43,11 +43,11 @@ casxa [%i0] (0x40+0x40), %l6, %o2
4343
casa [%i0] %asi, %l6, %o2
4444

4545
! V8: error: instruction requires a CPU feature not currently enabled
46-
! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
46+
! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
4747
! LEON: casa [%i0] 128, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
4848
casa [%i0] 0x80, %l6, %o2
4949

5050
! V8: error: instruction requires a CPU feature not currently enabled
51-
! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
51+
! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
5252
! LEON: casa [%i0] 128, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
5353
casa [%i0] (0x40+0x40), %l6, %o2

‎llvm/test/MC/Sparc/sparcv9-asi-names.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,15 +13,15 @@ casxa [%i0] #ASI_AIUS, %l6, %o2
1313
casxa [%i0] #ASI_AIUP_L, %l6, %o2
1414
! V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x03,0x36]
1515
casxa [%i0] #ASI_AIUS_L, %l6, %o2
16-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
16+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
1717
casxa [%i0] #ASI_P, %l6, %o2
1818
! V9: casxa [%i0] #ASI_S, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x36]
1919
casxa [%i0] #ASI_S, %l6, %o2
2020
! V9: casxa [%i0] #ASI_PNF, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x56]
2121
casxa [%i0] #ASI_PNF, %l6, %o2
2222
! V9: casxa [%i0] #ASI_SNF, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x76]
2323
casxa [%i0] #ASI_SNF, %l6, %o2
24-
! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
24+
! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
2525
casxa [%i0] #ASI_P_L, %l6, %o2
2626
! V9: casxa [%i0] #ASI_S_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x36]
2727
casxa [%i0] #ASI_S_L, %l6, %o2
@@ -43,15 +43,15 @@ casxa [%i0] #ASI_AS_IF_USER_SECONDARY, %l6, %o2
4343
casxa [%i0] #ASI_AS_IF_USER_PRIMARY_LITTLE, %l6, %o2
4444
! V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x03,0x36]
4545
casxa [%i0] #ASI_AS_IF_USER_SECONDARY_LITTLE, %l6, %o2
46-
! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
46+
! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
4747
casxa [%i0] #ASI_PRIMARY, %l6, %o2
4848
! V9: casxa [%i0] #ASI_S, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x36]
4949
casxa [%i0] #ASI_SECONDARY, %l6, %o2
5050
! V9: casxa [%i0] #ASI_PNF, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x56]
5151
casxa [%i0] #ASI_PRIMARY_NOFAULT, %l6, %o2
5252
! V9: casxa [%i0] #ASI_SNF, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x76]
5353
casxa [%i0] #ASI_SECONDARY_NOFAULT, %l6, %o2
54-
! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
54+
! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
5555
casxa [%i0] #ASI_PRIMARY_LITTLE, %l6, %o2
5656
! V9: casxa [%i0] #ASI_S_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x36]
5757
casxa [%i0] #ASI_SECONDARY_LITTLE, %l6, %o2

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