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[NFC][AMDGPU] Auto-generate check lines for llvm/test/CodeGen/AMDGPU/andorbitset.ll 
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‎llvm/test/CodeGen/AMDGPU/andorbitset.ll‎

Lines changed: 87 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,48 +1,103 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
23

3-
; SI-LABEL: {{^}}s_clear_msb:
4-
; SI: s_bitset0_b32 s{{[0-9]+}}, 31
54
define amdgpu_kernel void @s_clear_msb(ptr addrspace(1) %out, i32 %in) {
5+
; SI-LABEL: s_clear_msb:
6+
; SI: ; %bb.0:
7+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
8+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
9+
; SI-NEXT: s_mov_b32 s3, 0xf000
10+
; SI-NEXT: s_mov_b32 s2, -1
11+
; SI-NEXT: s_waitcnt lgkmcnt(0)
12+
; SI-NEXT: s_bitset0_b32 s4, 31
13+
; SI-NEXT: v_mov_b32_e32 v0, s4
14+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
15+
; SI-NEXT: s_endpgm
616
%x = and i32 %in, 2147483647
717
store i32 %x, ptr addrspace(1) %out
818
ret void
919
}
1020

11-
; SI-LABEL: {{^}}s_set_msb:
12-
; SI: s_bitset1_b32 s{{[0-9]+}}, 31
1321
define amdgpu_kernel void @s_set_msb(ptr addrspace(1) %out, i32 %in) {
22+
; SI-LABEL: s_set_msb:
23+
; SI: ; %bb.0:
24+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
25+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
26+
; SI-NEXT: s_mov_b32 s3, 0xf000
27+
; SI-NEXT: s_mov_b32 s2, -1
28+
; SI-NEXT: s_waitcnt lgkmcnt(0)
29+
; SI-NEXT: s_bitset1_b32 s4, 31
30+
; SI-NEXT: v_mov_b32_e32 v0, s4
31+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
32+
; SI-NEXT: s_endpgm
1433
%x = or i32 %in, 2147483648
1534
store i32 %x, ptr addrspace(1) %out
1635
ret void
1736
}
1837

19-
; SI-LABEL: {{^}}s_clear_lsb:
20-
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, -2
2138
define amdgpu_kernel void @s_clear_lsb(ptr addrspace(1) %out, i32 %in) {
39+
; SI-LABEL: s_clear_lsb:
40+
; SI: ; %bb.0:
41+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
42+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
43+
; SI-NEXT: s_mov_b32 s3, 0xf000
44+
; SI-NEXT: s_mov_b32 s2, -1
45+
; SI-NEXT: s_waitcnt lgkmcnt(0)
46+
; SI-NEXT: s_and_b32 s4, s4, -2
47+
; SI-NEXT: v_mov_b32_e32 v0, s4
48+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
49+
; SI-NEXT: s_endpgm
2250
%x = and i32 %in, 4294967294
2351
store i32 %x, ptr addrspace(1) %out
2452
ret void
2553
}
2654

27-
; SI-LABEL: {{^}}s_set_lsb:
28-
; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
2955
define amdgpu_kernel void @s_set_lsb(ptr addrspace(1) %out, i32 %in) {
56+
; SI-LABEL: s_set_lsb:
57+
; SI: ; %bb.0:
58+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
59+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
60+
; SI-NEXT: s_mov_b32 s3, 0xf000
61+
; SI-NEXT: s_mov_b32 s2, -1
62+
; SI-NEXT: s_waitcnt lgkmcnt(0)
63+
; SI-NEXT: s_or_b32 s4, s4, 1
64+
; SI-NEXT: v_mov_b32_e32 v0, s4
65+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
66+
; SI-NEXT: s_endpgm
3067
%x = or i32 %in, 1
3168
store i32 %x, ptr addrspace(1) %out
3269
ret void
3370
}
3471

35-
; SI-LABEL: {{^}}s_clear_midbit:
36-
; SI: s_bitset0_b32 s{{[0-9]+}}, 8
3772
define amdgpu_kernel void @s_clear_midbit(ptr addrspace(1) %out, i32 %in) {
73+
; SI-LABEL: s_clear_midbit:
74+
; SI: ; %bb.0:
75+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
76+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
77+
; SI-NEXT: s_mov_b32 s3, 0xf000
78+
; SI-NEXT: s_mov_b32 s2, -1
79+
; SI-NEXT: s_waitcnt lgkmcnt(0)
80+
; SI-NEXT: s_bitset0_b32 s4, 8
81+
; SI-NEXT: v_mov_b32_e32 v0, s4
82+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
83+
; SI-NEXT: s_endpgm
3884
%x = and i32 %in, 4294967039
3985
store i32 %x, ptr addrspace(1) %out
4086
ret void
4187
}
4288

43-
; SI-LABEL: {{^}}s_set_midbit:
44-
; SI: s_bitset1_b32 s{{[0-9]+}}, 8
4589
define amdgpu_kernel void @s_set_midbit(ptr addrspace(1) %out, i32 %in) {
90+
; SI-LABEL: s_set_midbit:
91+
; SI: ; %bb.0:
92+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
93+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
94+
; SI-NEXT: s_mov_b32 s3, 0xf000
95+
; SI-NEXT: s_mov_b32 s2, -1
96+
; SI-NEXT: s_waitcnt lgkmcnt(0)
97+
; SI-NEXT: s_bitset1_b32 s4, 8
98+
; SI-NEXT: v_mov_b32_e32 v0, s4
99+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
100+
; SI-NEXT: s_endpgm
46101
%x = or i32 %in, 256
47102
store i32 %x, ptr addrspace(1) %out
48103
ret void
@@ -51,10 +106,27 @@ define amdgpu_kernel void @s_set_midbit(ptr addrspace(1) %out, i32 %in) {
51106
@gv = external addrspace(1) global i32
52107

53108
; Make sure there's no verifier error with an undef source.
54-
; SI-LABEL: {{^}}bitset_verifier_error:
55-
; SI-NOT: %bb.1:
56-
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
57109
define void @bitset_verifier_error() local_unnamed_addr #0 {
110+
; SI-LABEL: bitset_verifier_error:
111+
; SI: ; %bb.0: ; %bb
112+
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113+
; SI-NEXT: s_getpc_b64 s[4:5]
114+
; SI-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4
115+
; SI-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12
116+
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
117+
; SI-NEXT: s_mov_b32 s7, 0xf000
118+
; SI-NEXT: s_mov_b32 s6, -1
119+
; SI-NEXT: s_waitcnt lgkmcnt(0)
120+
; SI-NEXT: s_and_b32 s8, s4, 0x7fffffff
121+
; SI-NEXT: v_mov_b32_e32 v0, s8
122+
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
123+
; SI-NEXT: s_waitcnt expcnt(0)
124+
; SI-NEXT: v_mov_b32_e32 v0, 0x3f7fbe77
125+
; SI-NEXT: v_cmp_ge_f32_e64 s[4:5], |s4|, v0
126+
; SI-NEXT: s_and_b64 vcc, exec, s[4:5]
127+
; SI-NEXT: s_cbranch_vccnz .LBB6_2
128+
; SI-NEXT: ; %bb.1: ; %bb5
129+
; SI-NEXT: .LBB6_2: ; %bb6
58130
bb:
59131
%i = call float @llvm.fabs.f32(float undef) #0
60132
%i1 = bitcast float %i to i32

‎llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll‎

Lines changed: 67 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,48 +1,103 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
23

3-
; SI-LABEL: {{^}}s_or_to_orn2:
4-
; SI: s_orn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
54
define amdgpu_kernel void @s_or_to_orn2(ptr addrspace(1) %out, i32 %in) {
5+
; SI-LABEL: s_or_to_orn2:
6+
; SI: ; %bb.0:
7+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
8+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
9+
; SI-NEXT: s_mov_b32 s3, 0xf000
10+
; SI-NEXT: s_mov_b32 s2, -1
11+
; SI-NEXT: s_waitcnt lgkmcnt(0)
12+
; SI-NEXT: s_orn2_b32 s4, s4, 50
13+
; SI-NEXT: v_mov_b32_e32 v0, s4
14+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
15+
; SI-NEXT: s_endpgm
616
%x = or i32 %in, -51
717
store i32 %x, ptr addrspace(1) %out
818
ret void
919
}
1020

11-
; SI-LABEL: {{^}}s_or_to_orn2_imm0:
12-
; SI: s_orn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
1321
define amdgpu_kernel void @s_or_to_orn2_imm0(ptr addrspace(1) %out, i32 %in) {
22+
; SI-LABEL: s_or_to_orn2_imm0:
23+
; SI: ; %bb.0:
24+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
25+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
26+
; SI-NEXT: s_mov_b32 s3, 0xf000
27+
; SI-NEXT: s_mov_b32 s2, -1
28+
; SI-NEXT: s_waitcnt lgkmcnt(0)
29+
; SI-NEXT: s_orn2_b32 s4, s4, 50
30+
; SI-NEXT: v_mov_b32_e32 v0, s4
31+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
32+
; SI-NEXT: s_endpgm
1433
%x = or i32 -51, %in
1534
store i32 %x, ptr addrspace(1) %out
1635
ret void
1736
}
1837

19-
; SI-LABEL: {{^}}s_and_to_andn2:
20-
; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
2138
define amdgpu_kernel void @s_and_to_andn2(ptr addrspace(1) %out, i32 %in) {
39+
; SI-LABEL: s_and_to_andn2:
40+
; SI: ; %bb.0:
41+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
42+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
43+
; SI-NEXT: s_mov_b32 s3, 0xf000
44+
; SI-NEXT: s_mov_b32 s2, -1
45+
; SI-NEXT: s_waitcnt lgkmcnt(0)
46+
; SI-NEXT: s_andn2_b32 s4, s4, 50
47+
; SI-NEXT: v_mov_b32_e32 v0, s4
48+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
49+
; SI-NEXT: s_endpgm
2250
%x = and i32 %in, -51
2351
store i32 %x, ptr addrspace(1) %out
2452
ret void
2553
}
2654

27-
; SI-LABEL: {{^}}s_and_to_andn2_imm0:
28-
; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
2955
define amdgpu_kernel void @s_and_to_andn2_imm0(ptr addrspace(1) %out, i32 %in) {
56+
; SI-LABEL: s_and_to_andn2_imm0:
57+
; SI: ; %bb.0:
58+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
59+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
60+
; SI-NEXT: s_mov_b32 s3, 0xf000
61+
; SI-NEXT: s_mov_b32 s2, -1
62+
; SI-NEXT: s_waitcnt lgkmcnt(0)
63+
; SI-NEXT: s_andn2_b32 s4, s4, 50
64+
; SI-NEXT: v_mov_b32_e32 v0, s4
65+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
66+
; SI-NEXT: s_endpgm
3067
%x = and i32 -51, %in
3168
store i32 %x, ptr addrspace(1) %out
3269
ret void
3370
}
3471

35-
; SI-LABEL: {{^}}s_xor_to_xnor:
36-
; SI: s_xnor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
3772
define amdgpu_kernel void @s_xor_to_xnor(ptr addrspace(1) %out, i32 %in) {
73+
; SI-LABEL: s_xor_to_xnor:
74+
; SI: ; %bb.0:
75+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
76+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
77+
; SI-NEXT: s_mov_b32 s3, 0xf000
78+
; SI-NEXT: s_mov_b32 s2, -1
79+
; SI-NEXT: s_waitcnt lgkmcnt(0)
80+
; SI-NEXT: s_xnor_b32 s4, s4, 50
81+
; SI-NEXT: v_mov_b32_e32 v0, s4
82+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
83+
; SI-NEXT: s_endpgm
3884
%x = xor i32 %in, -51
3985
store i32 %x, ptr addrspace(1) %out
4086
ret void
4187
}
4288

43-
; SI-LABEL: {{^}}s_xor_to_xnor_imm0:
44-
; SI: s_xnor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
4589
define amdgpu_kernel void @s_xor_to_xnor_imm0(ptr addrspace(1) %out, i32 %in) {
90+
; SI-LABEL: s_xor_to_xnor_imm0:
91+
; SI: ; %bb.0:
92+
; SI-NEXT: s_load_dword s4, s[2:3], 0xb
93+
; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
94+
; SI-NEXT: s_mov_b32 s3, 0xf000
95+
; SI-NEXT: s_mov_b32 s2, -1
96+
; SI-NEXT: s_waitcnt lgkmcnt(0)
97+
; SI-NEXT: s_xnor_b32 s4, s4, 50
98+
; SI-NEXT: v_mov_b32_e32 v0, s4
99+
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
100+
; SI-NEXT: s_endpgm
46101
%x = xor i32 -51, %in
47102
store i32 %x, ptr addrspace(1) %out
48103
ret void

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