Address review feedback

Author: mmha

clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp

@@ -157,19 +157,19 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl &gd, unsigned builtinID,
     mlir::Value size = emitScalarExpr(e->getArg(0));
 
     // The alignment of the alloca should correspond to __BIGGEST_ALIGNMENT__.
-    const TargetInfo &TI = getContext().getTargetInfo();
-    const CharUnits SuitableAlignmentInBytes =
-        getContext().toCharUnitsFromBits(TI.getSuitableAlign());
+    const TargetInfo &ti = getContext().getTargetInfo();
+    const CharUnits suitableAlignmentInBytes =
+        getContext().toCharUnitsFromBits(ti.getSuitableAlign());
 
     // Emit the alloca op with type `u8 *` to match the semantics of
     // `llvm.alloca`. We later bitcast the type to `void *` to match the
     // semantics of C/C++
     // FIXME(cir): It may make sense to allow AllocaOp of type `u8` to return a
     // pointer of type `void *`. This will require a change to the allocaOp
     // verifier.
-    auto allocaAddr = builder.createAlloca(
+    mlir::Value allocaAddr = builder.createAlloca(
         getLoc(e->getSourceRange()), builder.getUInt8PtrTy(),
-        builder.getUInt8Ty(), "bi_alloca", SuitableAlignmentInBytes, size);
+        builder.getUInt8Ty(), "bi_alloca", suitableAlignmentInBytes, size);
 
     // Initialize the allocated buffer if required.
     if (builtinID != Builtin::BI__builtin_alloca_uninitialized) {

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -1054,11 +1054,11 @@ mlir::LogicalResult CIRToLLVMAllocaOpLowering::matchAndRewrite(
     cir::AllocaOp op, OpAdaptor adaptor,
     mlir::ConversionPatternRewriter &rewriter) const {
   mlir::Value size =
-      op.isDynamic() ? adaptor.getDynAllocSize()
-                     : rewriter.create<mlir::LLVM::ConstantOp>(
-                           op.getLoc(),
-                           typeConverter->convertType(rewriter.getIndexType()),
-                           rewriter.getIntegerAttr(rewriter.getIndexType(), 1));
+      op.isDynamic()
+          ? adaptor.getDynAllocSize()
+          : rewriter.create<mlir::LLVM::ConstantOp>(
+                op.getLoc(),
+                typeConverter->convertType(rewriter.getIndexType()), 1);
   mlir::Type elementTy =
       convertTypeForMemory(*getTypeConverter(), dataLayout, op.getAllocaType());
   mlir::Type resultTy =

clang/test/CIR/CodeGen/builtin_call.cpp

@@ -211,6 +211,10 @@ void unreachable() {
 // LLVM:         unreachable
 // LLVM:       }
 
+// OGCG-LABEL: @_Z11unreachablev
+// OGCG:         unreachable
+// OGCG:       }
+
 void f1();
 void unreachable2() {
   __builtin_unreachable();
@@ -229,6 +233,9 @@ void unreachable2() {
 // LLVM-NEXT:    call void @_Z2f1v()
 // LLVM:       }
 
+// OGCG-LABEL: @_Z12unreachable2v
+// OGCG:         unreachable
+
 void trap() {
   __builtin_trap();
 }
@@ -241,6 +248,10 @@ void trap() {
 // LLVM:         call void @llvm.trap()
 // LLVM:       }
 
+// OGCG-LABEL: @_Z4trapv
+// OGCG:         call void @llvm.trap()
+// OGCG:       }
+
 void trap2() {
   __builtin_trap();
   f1();
@@ -259,6 +270,12 @@ void trap2() {
 // LLVM-NEXT:    call void @_Z2f1v()
 // LLVM:       }
 
+// OGCG-LABEL: define{{.*}} void @_Z5trap2v
+// OGCG:         call void @llvm.trap()
+// OGCG-NEXT:    call void @_Z2f1v()
+// OGCG:         ret void
+// OGCG:       }
+
 void *test_alloca(unsigned long n) {
   return __builtin_alloca(n);
 }
@@ -268,3 +285,24 @@ void *test_alloca(unsigned long n) {
 
 // LLVM-LABEL: @_Z11test_allocam(
 // LLVM:         alloca i8, i64 %{{.+}}
+
+// OGCG-LABEL: @_Z11test_allocam(
+// OGCG:         alloca i8, i64 %{{.+}}
+
+bool test_multiple_allocas(unsigned long n) {
+  void *a = __builtin_alloca(n);
+  void *b = __builtin_alloca(n);
+  return a != b;
+}
+
+// CIR-LABEL: @_Z21test_multiple_allocasm(
+// CIR:         %{{.+}} = cir.alloca !u8i, !cir.ptr<!u8i>, %{{.+}} : !u64i, ["bi_alloca"]
+// CIR:         %{{.+}} = cir.alloca !u8i, !cir.ptr<!u8i>, %{{.+}} : !u64i, ["bi_alloca"]
+
+// LLVM-LABEL: @_Z21test_multiple_allocasm(
+// LLVM:         alloca i8, i64 %{{.+}}
+// LLVM:         alloca i8, i64 %{{.+}}
+
+// OGCG-LABEL: @_Z21test_multiple_allocasm(
+// OGCG:         alloca i8, i64 %{{.+}}
+// OGCG:         alloca i8, i64 %{{.+}}