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[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
This converts them to what clang is now using for codegen. Unfortunately, there seem to be a few kinks to work out still. I'll try to address with follow up patches. llvm-svn: 336871
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13 files changed

+1710
-462
lines changed

13 files changed

+1710
-462
lines changed

‎llvm/include/llvm/IR/IntrinsicsX86.td‎

Lines changed: 0 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1933,57 +1933,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
19331933
[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty],
19341934
[IntrNoMem]>;
19351935

1936-
1937-
def int_x86_avx512_mask_vfmadd_sd : // FIXME: Remove
1938-
Intrinsic<[llvm_v2f64_ty],
1939-
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty,
1940-
llvm_i32_ty], [IntrNoMem]>;
1941-
1942-
def int_x86_avx512_mask_vfmadd_ss : // FIXME: Remove
1943-
Intrinsic<[llvm_v4f32_ty],
1944-
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty,
1945-
llvm_i32_ty], [IntrNoMem]>;
1946-
1947-
def int_x86_avx512_maskz_vfmadd_sd : // FIXME: Remove
1948-
Intrinsic<[llvm_v2f64_ty],
1949-
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty,
1950-
llvm_i32_ty], [IntrNoMem]>;
1951-
1952-
def int_x86_avx512_maskz_vfmadd_ss : // FIXME: Remove
1953-
Intrinsic<[llvm_v4f32_ty],
1954-
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty,
1955-
llvm_i32_ty], [IntrNoMem]>;
1956-
1957-
def int_x86_avx512_mask3_vfmadd_sd : // FIXME: Remove
1958-
Intrinsic<[llvm_v2f64_ty],
1959-
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty,
1960-
llvm_i32_ty], [IntrNoMem]>;
1961-
1962-
def int_x86_avx512_mask3_vfmadd_ss : // FIXME: Remove
1963-
Intrinsic<[llvm_v4f32_ty],
1964-
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty,
1965-
llvm_i32_ty], [IntrNoMem]>;
1966-
1967-
def int_x86_avx512_mask3_vfmsub_sd : // FIXME: Remove
1968-
Intrinsic<[llvm_v2f64_ty],
1969-
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty,
1970-
llvm_i32_ty], [IntrNoMem]>;
1971-
1972-
def int_x86_avx512_mask3_vfmsub_ss : // FIXME: Remove
1973-
Intrinsic<[llvm_v4f32_ty],
1974-
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty,
1975-
llvm_i32_ty], [IntrNoMem]>;
1976-
1977-
def int_x86_avx512_mask3_vfnmsub_sd : // FIXME: Remove
1978-
Intrinsic<[llvm_v2f64_ty],
1979-
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty,
1980-
llvm_i32_ty], [IntrNoMem]>;
1981-
1982-
def int_x86_avx512_mask3_vfnmsub_ss : // FIXME: Remove
1983-
Intrinsic<[llvm_v4f32_ty],
1984-
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty,
1985-
llvm_i32_ty], [IntrNoMem]>;
1986-
19871936
def int_x86_avx512_vpmadd52h_uq_128 :
19881937
GCCBuiltin<"__builtin_ia32_vpmadd52huq128">,
19891938
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 99 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -81,17 +81,17 @@ static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
8181
Name.startswith("fma.vfmsubadd.") || // Added in 7.0
8282
Name.startswith("fma.vfnmadd.") || // Added in 7.0
8383
Name.startswith("fma.vfnmsub.") || // Added in 7.0
84-
Name.startswith("avx512.mask.vfmadd.p") || // Added in 7.0
85-
Name.startswith("avx512.mask.vfnmadd.p") || // Added in 7.0
86-
Name.startswith("avx512.mask.vfnmsub.p") || // Added in 7.0
87-
Name.startswith("avx512.mask3.vfmadd.p") || // Added in 7.0
88-
Name.startswith("avx512.maskz.vfmadd.p") || // Added in 7.0
89-
Name.startswith("avx512.mask3.vfmsub.p") || // Added in 7.0
90-
Name.startswith("avx512.mask3.vfnmsub.p") || // Added in 7.0
91-
Name.startswith("avx512.mask.vfmaddsub.p") || // Added in 7.0
92-
Name.startswith("avx512.maskz.vfmaddsub.p") || // Added in 7.0
93-
Name.startswith("avx512.mask3.vfmaddsub.p") || // Added in 7.0
94-
Name.startswith("avx512.mask3.vfmsubadd.p") || // Added in 7.0
84+
Name.startswith("avx512.mask.vfmadd.") || // Added in 7.0
85+
Name.startswith("avx512.mask.vfnmadd.") || // Added in 7.0
86+
Name.startswith("avx512.mask.vfnmsub.") || // Added in 7.0
87+
Name.startswith("avx512.mask3.vfmadd.") || // Added in 7.0
88+
Name.startswith("avx512.maskz.vfmadd.") || // Added in 7.0
89+
Name.startswith("avx512.mask3.vfmsub.") || // Added in 7.0
90+
Name.startswith("avx512.mask3.vfnmsub.") || // Added in 7.0
91+
Name.startswith("avx512.mask.vfmaddsub.") || // Added in 7.0
92+
Name.startswith("avx512.maskz.vfmaddsub.") || // Added in 7.0
93+
Name.startswith("avx512.mask3.vfmaddsub.") || // Added in 7.0
94+
Name.startswith("avx512.mask3.vfmsubadd.") || // Added in 7.0
9595
Name.startswith("avx512.mask.shuf.i") || // Added in 6.0
9696
Name.startswith("avx512.mask.shuf.f") || // Added in 6.0
9797
Name.startswith("avx512.kunpck") || //added in 6.0
@@ -826,7 +826,7 @@ static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask,
826826

827827
static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask,
828828
Value *Op0, Value *Op1) {
829-
// If the mask is all ones just emit the align operation.
829+
// If the mask is all ones just emit the first operation.
830830
if (const auto *C = dyn_cast<Constant>(Mask))
831831
if (C->isAllOnesValue())
832832
return Op0;
@@ -835,6 +835,21 @@ static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask,
835835
return Builder.CreateSelect(Mask, Op0, Op1);
836836
}
837837

838+
static Value *EmitX86ScalarSelect(IRBuilder<> &Builder, Value *Mask,
839+
Value *Op0, Value *Op1) {
840+
// If the mask is all ones just emit the first operation.
841+
if (const auto *C = dyn_cast<Constant>(Mask))
842+
if (C->isAllOnesValue())
843+
return Op0;
844+
845+
llvm::VectorType *MaskTy =
846+
llvm::VectorType::get(Builder.getInt1Ty(),
847+
Mask->getType()->getIntegerBitWidth());
848+
Mask = Builder.CreateBitCast(Mask, MaskTy);
849+
Mask = Builder.CreateExtractElement(Mask, (uint64_t)0);
850+
return Builder.CreateSelect(Mask, Op0, Op1);
851+
}
852+
838853
// Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics.
839854
// PALIGNR handles large immediates by shifting while VALIGN masks the immediate
840855
// so we need to handle both cases. VALIGN also doesn't have 128-bit lanes.
@@ -2806,6 +2821,64 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
28062821

28072822
Rep = Builder.CreateInsertElement(Constant::getNullValue(CI->getType()),
28082823
Rep, (uint64_t)0);
2824+
} else if (IsX86 && (Name.startswith("avx512.mask.vfmadd.s") ||
2825+
Name.startswith("avx512.maskz.vfmadd.s") ||
2826+
Name.startswith("avx512.mask3.vfmadd.s") ||
2827+
Name.startswith("avx512.mask3.vfmsub.s") ||
2828+
Name.startswith("avx512.mask3.vfnmsub.s"))) {
2829+
bool IsMask3 = Name[11] == '3';
2830+
bool IsMaskZ = Name[11] == 'z';
2831+
// Drop the "avx512.mask." to make it easier.
2832+
Name = Name.drop_front(IsMask3 || IsMaskZ ? 13 : 12);
2833+
bool NegMul = Name[2] == 'n';
2834+
bool NegAcc = NegMul ? Name[4] == 's' : Name[3] == 's';
2835+
2836+
Value *A = CI->getArgOperand(0);
2837+
Value *B = CI->getArgOperand(1);
2838+
Value *C = CI->getArgOperand(2);
2839+
2840+
if (NegMul && (IsMask3 || IsMaskZ))
2841+
A = Builder.CreateFNeg(A);
2842+
if (NegMul && !(IsMask3 || IsMaskZ))
2843+
B = Builder.CreateFNeg(B);
2844+
if (NegAcc)
2845+
C = Builder.CreateFNeg(C);
2846+
2847+
A = Builder.CreateExtractElement(A, (uint64_t)0);
2848+
B = Builder.CreateExtractElement(B, (uint64_t)0);
2849+
C = Builder.CreateExtractElement(C, (uint64_t)0);
2850+
2851+
if (!isa<ConstantInt>(CI->getArgOperand(4)) ||
2852+
cast<ConstantInt>(CI->getArgOperand(4))->getZExtValue() != 4) {
2853+
Value *Ops[] = { A, B, C, CI->getArgOperand(4) };
2854+
2855+
Intrinsic::ID IID;
2856+
if (Name.back() == 'd')
2857+
IID = Intrinsic::x86_avx512_vfmadd_f64;
2858+
else
2859+
IID = Intrinsic::x86_avx512_vfmadd_f32;
2860+
Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID);
2861+
Rep = Builder.CreateCall(FMA, Ops);
2862+
} else {
2863+
Function *FMA = Intrinsic::getDeclaration(CI->getModule(),
2864+
Intrinsic::fma,
2865+
A->getType());
2866+
Rep = Builder.CreateCall(FMA, { A, B, C });
2867+
}
2868+
2869+
Value *PassThru = IsMaskZ ? Constant::getNullValue(Rep->getType()) :
2870+
IsMask3 ? C : A;
2871+
2872+
// For Mask3 with NegAcc, we need to create a new extractelement that
2873+
// avoids the negation above.
2874+
if (NegAcc && IsMask3)
2875+
PassThru = Builder.CreateExtractElement(CI->getArgOperand(2),
2876+
(uint64_t)0);
2877+
2878+
Rep = EmitX86ScalarSelect(Builder, CI->getArgOperand(3),
2879+
Rep, PassThru);
2880+
Rep = Builder.CreateInsertElement(CI->getArgOperand(IsMask3 ? 2 : 0),
2881+
Rep, (uint64_t)0);
28092882
} else if (IsX86 && (Name.startswith("avx512.mask.vfmadd.p") ||
28102883
Name.startswith("avx512.mask.vfnmadd.p") ||
28112884
Name.startswith("avx512.mask.vfnmsub.p") ||
@@ -2820,6 +2893,17 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
28202893
bool NegMul = Name[2] == 'n';
28212894
bool NegAcc = NegMul ? Name[4] == 's' : Name[3] == 's';
28222895

2896+
Value *A = CI->getArgOperand(0);
2897+
Value *B = CI->getArgOperand(1);
2898+
Value *C = CI->getArgOperand(2);
2899+
2900+
if (NegMul && (IsMask3 || IsMaskZ))
2901+
A = Builder.CreateFNeg(A);
2902+
if (NegMul && !(IsMask3 || IsMaskZ))
2903+
B = Builder.CreateFNeg(B);
2904+
if (NegAcc)
2905+
C = Builder.CreateFNeg(C);
2906+
28232907
if (CI->getNumArgOperands() == 5 &&
28242908
(!isa<ConstantInt>(CI->getArgOperand(4)) ||
28252909
cast<ConstantInt>(CI->getArgOperand(4))->getZExtValue() != 4)) {
@@ -2830,38 +2914,13 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
28302914
else
28312915
IID = Intrinsic::x86_avx512_vfmadd_pd_512;
28322916

2833-
Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1),
2834-
CI->getArgOperand(2), CI->getArgOperand(4) };
2835-
2836-
if (NegMul) {
2837-
if (IsMaskZ || IsMask3)
2838-
Ops[0] = Builder.CreateFNeg(Ops[0]);
2839-
else
2840-
Ops[1] = Builder.CreateFNeg(Ops[1]);
2841-
}
2842-
if (NegAcc)
2843-
Ops[2] = Builder.CreateFNeg(Ops[2]);
2844-
28452917
Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
2846-
Ops);
2918+
{ A, B, C, CI->getArgOperand(4) });
28472919
} else {
2848-
2849-
Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1),
2850-
CI->getArgOperand(2) };
2851-
2852-
if (NegMul) {
2853-
if (IsMaskZ || IsMask3)
2854-
Ops[0] = Builder.CreateFNeg(Ops[0]);
2855-
else
2856-
Ops[1] = Builder.CreateFNeg(Ops[1]);
2857-
}
2858-
if (NegAcc)
2859-
Ops[2] = Builder.CreateFNeg(Ops[2]);
2860-
28612920
Function *FMA = Intrinsic::getDeclaration(CI->getModule(),
28622921
Intrinsic::fma,
2863-
Ops[0]->getType());
2864-
Rep = Builder.CreateCall(FMA, Ops);
2922+
A->getType());
2923+
Rep = Builder.CreateCall(FMA, { A, B, C });
28652924
}
28662925

28672926
Value *PassThru = IsMaskZ ? llvm::Constant::getNullValue(CI->getType()) :

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -20710,39 +20710,6 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2071020710
Src1, Src2, Src3),
2071120711
Mask, PassThru, Subtarget, DAG);
2071220712
}
20713-
case FMA_OP_SCALAR_MASK:
20714-
case FMA_OP_SCALAR_MASK3:
20715-
case FMA_OP_SCALAR_MASKZ: {
20716-
SDValue Src1 = Op.getOperand(1);
20717-
SDValue Src2 = Op.getOperand(2);
20718-
SDValue Src3 = Op.getOperand(3);
20719-
SDValue Mask = Op.getOperand(4);
20720-
MVT VT = Op.getSimpleValueType();
20721-
SDValue PassThru = SDValue();
20722-
20723-
// set PassThru element
20724-
if (IntrData->Type == FMA_OP_SCALAR_MASKZ)
20725-
PassThru = getZeroVector(VT, Subtarget, DAG, dl);
20726-
else if (IntrData->Type == FMA_OP_SCALAR_MASK3)
20727-
PassThru = Src3;
20728-
else
20729-
PassThru = Src1;
20730-
20731-
unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
20732-
if (IntrWithRoundingModeOpcode != 0) {
20733-
SDValue Rnd = Op.getOperand(5);
20734-
if (!isRoundModeCurDirection(Rnd))
20735-
return getScalarMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode, dl,
20736-
Op.getValueType(), Src1, Src2,
20737-
Src3, Rnd),
20738-
Mask, PassThru, Subtarget, DAG);
20739-
}
20740-
20741-
return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl,
20742-
Op.getValueType(), Src1, Src2,
20743-
Src3),
20744-
Mask, PassThru, Subtarget, DAG);
20745-
}
2074620713
case IFMA_OP:
2074720714
// NOTE: We need to swizzle the operands to pass the multiply operands
2074820715
// first.

‎llvm/lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6825,6 +6825,13 @@ multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode RndOp, string Prefix,
68256825
VR128X:$src1, (COPY_TO_REGCLASS _.FRC:$src2, VR128X),
68266826
(COPY_TO_REGCLASS _.FRC:$src3, VR128X))>;
68276827

6828+
def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6829+
(Op _.FRC:$src2, _.FRC:$src3,
6830+
(_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
6831+
(!cast<I>(Prefix#"231"#Suffix#"Zr_Int")
6832+
VR128X:$src1, (COPY_TO_REGCLASS _.FRC:$src2, VR128X),
6833+
(COPY_TO_REGCLASS _.FRC:$src3, VR128X))>;
6834+
68286835
def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
68296836
(Op _.FRC:$src2,
68306837
(_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
@@ -6840,6 +6847,13 @@ multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode RndOp, string Prefix,
68406847
VR128X:$src1, (COPY_TO_REGCLASS _.FRC:$src2, VR128X),
68416848
addr:$src3)>;
68426849

6850+
def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6851+
(Op _.FRC:$src2, (_.ScalarLdFrag addr:$src3),
6852+
(_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
6853+
(!cast<I>(Prefix#"231"#Suffix#"Zm_Int")
6854+
VR128X:$src1, (COPY_TO_REGCLASS _.FRC:$src2, VR128X),
6855+
addr:$src3)>;
6856+
68436857
def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
68446858
(X86selects VK1WM:$mask,
68456859
(Op _.FRC:$src2,
@@ -6947,6 +6961,14 @@ multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode RndOp, string Prefix,
69476961
VR128X:$src1, (COPY_TO_REGCLASS _.FRC:$src2, VR128X),
69486962
(COPY_TO_REGCLASS _.FRC:$src3, VR128X), imm:$rc)>;
69496963

6964+
def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6965+
(RndOp _.FRC:$src2, _.FRC:$src3,
6966+
(_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
6967+
(i32 imm:$rc)))))),
6968+
(!cast<I>(Prefix#"231"#Suffix#"Zrb_Int")
6969+
VR128X:$src1, (COPY_TO_REGCLASS _.FRC:$src2, VR128X),
6970+
(COPY_TO_REGCLASS _.FRC:$src3, VR128X), imm:$rc)>;
6971+
69506972
def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
69516973
(X86selects VK1WM:$mask,
69526974
(RndOp _.FRC:$src2,

‎llvm/lib/Target/X86/X86InstrFMA.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -355,6 +355,13 @@ multiclass scalar_fma_patterns<SDNode Op, string Prefix, string Suffix,
355355
(!cast<Instruction>(Prefix#"132"#Suffix#"m_Int")
356356
VR128:$src1, (COPY_TO_REGCLASS RC:$src2, VR128),
357357
addr:$src3)>;
358+
359+
def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector
360+
(Op RC:$src2, (mem_frag addr:$src3),
361+
(EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))),
362+
(!cast<Instruction>(Prefix#"231"#Suffix#"m_Int")
363+
VR128:$src1, (COPY_TO_REGCLASS RC:$src2, VR128),
364+
addr:$src3)>;
358365
}
359366
}
360367

‎llvm/lib/Target/X86/X86IntrinsicsInfo.h‎

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,7 @@ enum IntrinsicType : uint16_t {
2828
INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
2929
INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
3030
INTR_TYPE_3OP_MASK,
31-
FMA_OP_MASK, FMA_OP_MASKZ,
32-
FMA_OP_SCALAR_MASK, FMA_OP_SCALAR_MASKZ, FMA_OP_SCALAR_MASK3,
31+
FMA_OP_MASK, FMA_OP_MASKZ, FMA_OP_SCALAR,
3332
IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK,
3433
INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK,
3534
COMPRESS_EXPAND_IN_REG,
@@ -879,9 +878,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
879878
X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_512, INTR_TYPE_2OP_MASK,
880879
X86ISD::CVTPS2PH, 0),
881880

882-
X86_INTRINSIC_DATA(avx512_mask_vfmadd_sd, FMA_OP_SCALAR_MASK, X86ISD::FMADDS1, X86ISD::FMADDS1_RND),
883-
X86_INTRINSIC_DATA(avx512_mask_vfmadd_ss, FMA_OP_SCALAR_MASK, X86ISD::FMADDS1, X86ISD::FMADDS1_RND),
884-
885881
X86_INTRINSIC_DATA(avx512_mask_vpshldv_d_128, FMA_OP_MASK, X86ISD::VSHLDV, 0),
886882
X86_INTRINSIC_DATA(avx512_mask_vpshldv_d_256, FMA_OP_MASK, X86ISD::VSHLDV, 0),
887883
X86_INTRINSIC_DATA(avx512_mask_vpshldv_d_512, FMA_OP_MASK, X86ISD::VSHLDV, 0),
@@ -908,14 +904,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
908904
X86_INTRINSIC_DATA(avx512_mask_vpshufbitqmb_512, CMP_MASK,
909905
X86ISD::VPSHUFBITQMB, 0),
910906

911-
X86_INTRINSIC_DATA(avx512_mask3_vfmadd_sd, FMA_OP_SCALAR_MASK3, X86ISD::FMADDS3, X86ISD::FMADDS3_RND),
912-
X86_INTRINSIC_DATA(avx512_mask3_vfmadd_ss, FMA_OP_SCALAR_MASK3, X86ISD::FMADDS3, X86ISD::FMADDS3_RND),
913-
914-
X86_INTRINSIC_DATA(avx512_mask3_vfmsub_sd, FMA_OP_SCALAR_MASK3, X86ISD::FMSUBS3, X86ISD::FMSUBS3_RND),
915-
X86_INTRINSIC_DATA(avx512_mask3_vfmsub_ss, FMA_OP_SCALAR_MASK3, X86ISD::FMSUBS3, X86ISD::FMSUBS3_RND),
916-
917-
X86_INTRINSIC_DATA(avx512_mask3_vfnmsub_sd, FMA_OP_SCALAR_MASK3, X86ISD::FNMSUBS3, X86ISD::FNMSUBS3_RND),
918-
X86_INTRINSIC_DATA(avx512_mask3_vfnmsub_ss, FMA_OP_SCALAR_MASK3, X86ISD::FNMSUBS3, X86ISD::FNMSUBS3_RND),
919907
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_128, FIXUPIMM_MASKZ,
920908
X86ISD::VFIXUPIMM, 0),
921909
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_256, FIXUPIMM_MASKZ,
@@ -933,9 +921,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
933921
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ss, FIXUPIMMS_MASKZ,
934922
X86ISD::VFIXUPIMMS, 0),
935923

936-
X86_INTRINSIC_DATA(avx512_maskz_vfmadd_sd, FMA_OP_SCALAR_MASKZ, X86ISD::FMADDS1, X86ISD::FMADDS1_RND),
937-
X86_INTRINSIC_DATA(avx512_maskz_vfmadd_ss, FMA_OP_SCALAR_MASKZ, X86ISD::FMADDS1, X86ISD::FMADDS1_RND),
938-
939924
X86_INTRINSIC_DATA(avx512_maskz_vpshldv_d_128, FMA_OP_MASKZ, X86ISD::VSHLDV, 0),
940925
X86_INTRINSIC_DATA(avx512_maskz_vpshldv_d_256, FMA_OP_MASKZ, X86ISD::VSHLDV, 0),
941926
X86_INTRINSIC_DATA(avx512_maskz_vpshldv_d_512, FMA_OP_MASKZ, X86ISD::VSHLDV, 0),

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