Lower neon_vabs_v and neon_vabsq_v

Author: ghehg

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

@@ -2484,6 +2484,14 @@ mlir::Value CIRGenFunction::buildCommonNeonBuiltinExpr(
                        : "aarch64.neon.addp";
     break;
   }
+  case NEON::BI__builtin_neon_vabs_v:
+  case NEON::BI__builtin_neon_vabsq_v: {
+    intrincsName = mlir::isa<mlir::FloatType>(vTy.getEltType())
+                       ? "aarch64.neon.fabs"
+                       : "aarch64.neon.abs";
+    argTypes.push_back(vTy);
+    break;
+  }
   case NEON::BI__builtin_neon_vqadd_v:
   case NEON::BI__builtin_neon_vqaddq_v: {
     intrincsName = (intrinicId != altLLVMIntrinsic) ? "aarch64.neon.uqadd"

clang/test/CIR/CodeGen/AArch64/neon-misc.c

@@ -788,3 +788,29 @@ uint64x2_t test_vtstq_u64(uint64x2_t v1, uint64x2_t v2) {
   // LLVM:   [[VTST_I:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i64>
   // LLVM:   ret <2 x i64> [[VTST_I]]
 }
+
+int16x4_t test_vabs_s16(int16x4_t a) {
+  return vabs_s16(a);
+
+  // CIR-LABEL: vabs_s16
+  // CIR: {{%.*}} = cir.llvm.intrinsic "aarch64.neon.abs" {{%.*}} : 
+  // CIR-SAME: (!cir.vector<!s16i x 4>) -> !cir.vector<!s16i x 4>
+
+  // LLVM: {{.*}}test_vabs_s16(<4 x i16>{{.*}}[[A:%.*]])
+  // LLVM:   [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+  // LLVM:   [[VABS1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> [[A]])
+  // LLVM:   ret <4 x i16> [[VABS1_I]]
+} 
+
+int16x8_t test_vabsq_s16(int16x8_t a) {
+  return vabsq_s16(a);
+
+  // CIR-LABEL: vabsq_s16
+  // CIR: {{%.*}} = cir.llvm.intrinsic "aarch64.neon.abs" {{%.*}} : 
+  // CIR-SAME: (!cir.vector<!s16i x 8>) -> !cir.vector<!s16i x 8>
+
+  // LLVM: {{.*}}test_vabsq_s16(<8 x i16>{{.*}}[[A:%.*]])
+  // LLVM:   [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+  // LLVM:   [[VABS1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> [[A]])
+  // LLVM:   ret <8 x i16> [[VABS1_I]]
+}