@@ -571,37 +571,20 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
571571
572572 old_ctrl = ctrl = macb_or_gem_readl (bp , NCFGR );
573573
574- /* Clear all the bits we might set later */
575- ctrl &= ~(MACB_BIT (SPD ) | MACB_BIT (FD ) | MACB_BIT (PAE ));
576-
577574 if (bp -> caps & MACB_CAPS_MACB_IS_EMAC ) {
578575 if (state -> interface == PHY_INTERFACE_MODE_RMII )
579576 ctrl |= MACB_BIT (RM9200_RMII );
580577 } else {
581- ctrl &= ~(GEM_BIT (GBE ) | GEM_BIT (SGMIIEN ) | GEM_BIT (PCSSEL ));
582-
583- /* We do not support MLO_PAUSE_RX yet */
584- if (state -> pause & MLO_PAUSE_TX )
585- ctrl |= MACB_BIT (PAE );
578+ ctrl &= ~(GEM_BIT (SGMIIEN ) | GEM_BIT (PCSSEL ));
586579
587580 if (state -> interface == PHY_INTERFACE_MODE_SGMII )
588581 ctrl |= GEM_BIT (SGMIIEN ) | GEM_BIT (PCSSEL );
589582 }
590583
591- if (state -> speed == SPEED_1000 )
592- ctrl |= GEM_BIT (GBE );
593- else if (state -> speed == SPEED_100 )
594- ctrl |= MACB_BIT (SPD );
595-
596- if (state -> duplex )
597- ctrl |= MACB_BIT (FD );
598-
599584 /* Apply the new configuration, if any */
600585 if (old_ctrl ^ ctrl )
601586 macb_or_gem_writel (bp , NCFGR , ctrl );
602587
603- bp -> speed = state -> speed ;
604-
605588 spin_unlock_irqrestore (& bp -> lock , flags );
606589}
607590
@@ -635,10 +618,33 @@ static void macb_mac_link_up(struct phylink_config *config,
635618 struct net_device * ndev = to_net_dev (config -> dev );
636619 struct macb * bp = netdev_priv (ndev );
637620 struct macb_queue * queue ;
621+ unsigned long flags ;
638622 unsigned int q ;
623+ u32 ctrl ;
624+
625+ spin_lock_irqsave (& bp -> lock , flags );
626+
627+ ctrl = macb_or_gem_readl (bp , NCFGR );
628+
629+ ctrl &= ~(MACB_BIT (SPD ) | MACB_BIT (FD ));
630+
631+ if (speed == SPEED_100 )
632+ ctrl |= MACB_BIT (SPD );
633+
634+ if (duplex )
635+ ctrl |= MACB_BIT (FD );
639636
640637 if (!(bp -> caps & MACB_CAPS_MACB_IS_EMAC )) {
641- macb_set_tx_clk (bp -> tx_clk , bp -> speed , ndev );
638+ ctrl &= ~(GEM_BIT (GBE ) | MACB_BIT (PAE ));
639+
640+ if (speed == SPEED_1000 )
641+ ctrl |= GEM_BIT (GBE );
642+
643+ /* We do not support MLO_PAUSE_RX yet */
644+ if (tx_pause )
645+ ctrl |= MACB_BIT (PAE );
646+
647+ macb_set_tx_clk (bp -> tx_clk , speed , ndev );
642648
643649 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
644650 * cleared the pipeline and control registers.
@@ -651,6 +657,10 @@ static void macb_mac_link_up(struct phylink_config *config,
651657 bp -> rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT (HRESP ));
652658 }
653659
660+ macb_or_gem_writel (bp , NCFGR , ctrl );
661+
662+ spin_unlock_irqrestore (& bp -> lock , flags );
663+
654664 /* Enable Rx and Tx */
655665 macb_writel (bp , NCR , macb_readl (bp , NCR ) | MACB_BIT (RE ) | MACB_BIT (TE ));
656666
@@ -4432,8 +4442,6 @@ static int macb_probe(struct platform_device *pdev)
44324442 else
44334443 bp -> phy_interface = interface ;
44344444
4435- bp -> speed = SPEED_UNKNOWN ;
4436-
44374445 /* IP specific init */
44384446 err = init (pdev );
44394447 if (err )
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