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schspabrgl
schspa
authored and
brgl
committed
gpio: use raw spinlock for gpio chip shadowed data
In case of PREEMPT_RT, there is a raw_spinlock -> spinlock dependency as the lockdep report shows. __irq_set_handler irq_get_desc_buslock __irq_get_desc_lock raw_spin_lock_irqsave(&desc->lock, *flags); // raw spinlock get here __irq_do_set_handler mask_ack_irq dwapb_irq_ack spin_lock_irqsave(&gc->bgpio_lock, flags); // sleep able spinlock irq_put_desc_busunlock Replace with a raw lock to avoid BUGs. This lock is only used to access registers, and It's safe to replace with the raw lock without bad influence. [ 15.090359][ T1] ============================= [ 15.090365][ T1] [ BUG: Invalid wait context ] [ 15.090373][ T1] 5.10.59-rt52-00983-g186a6841c682-dirty #3 Not tainted [ 15.090386][ T1] ----------------------------- [ 15.090392][ T1] swapper/0/1 is trying to lock: [ 15.090402][ T1] 70ff00018507c188 (&gc->bgpio_lock){....}-{3:3}, at: _raw_spin_lock_irqsave+0x1c/0x28 [ 15.090470][ T1] other info that might help us debug this: [ 15.090477][ T1] context-{5:5} [ 15.090485][ T1] 3 locks held by swapper/0/1: [ 15.090497][ T1] #0: c2ff0001816de1a0 (&dev->mutex){....}-{4:4}, at: __device_driver_lock+0x98/0x104 [ 15.090553][ T1] #1: ffff90001485b4b8 (irq_domain_mutex){+.+.}-{4:4}, at: irq_domain_associate+0xbc/0x6d4 [ 15.090606][ T1] #2: 4bff000185d7a8e0 (lock_class){....}-{2:2}, at: _raw_spin_lock_irqsave+0x1c/0x28 [ 15.090654][ T1] stack backtrace: [ 15.090661][ T1] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.59-rt52-00983-g186a6841c682-dirty #3 [ 15.090682][ T1] Hardware name: Horizon Robotics Journey 5 DVB (DT) [ 15.090692][ T1] Call trace: ...... [ 15.090811][ T1] _raw_spin_lock_irqsave+0x1c/0x28 [ 15.090828][ T1] dwapb_irq_ack+0xb4/0x300 [ 15.090846][ T1] __irq_do_set_handler+0x494/0xb2c [ 15.090864][ T1] __irq_set_handler+0x74/0x114 [ 15.090881][ T1] irq_set_chip_and_handler_name+0x44/0x58 [ 15.090900][ T1] gpiochip_irq_map+0x210/0x644 Signed-off-by: Schspa Shi <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Doug Berger <[email protected]> Acked-by: Serge Semin <[email protected]> Signed-off-by: Bartosz Golaszewski <[email protected]>
1 parent 4f3e79b commit 3c938cc

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16 files changed

+108
-108
lines changed

16 files changed

+108
-108
lines changed

‎drivers/gpio/gpio-amdpt.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,19 +36,19 @@ static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
3636

3737
dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset);
3838

39-
spin_lock_irqsave(&gc->bgpio_lock, flags);
39+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
4040

4141
using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
4242
if (using_pins & BIT(offset)) {
4343
dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n",
4444
offset);
45-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
45+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
4646
return -EINVAL;
4747
}
4848

4949
writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
5050

51-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
51+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
5252

5353
return 0;
5454
}
@@ -59,13 +59,13 @@ static void pt_gpio_free(struct gpio_chip *gc, unsigned offset)
5959
unsigned long flags;
6060
u32 using_pins;
6161

62-
spin_lock_irqsave(&gc->bgpio_lock, flags);
62+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
6363

6464
using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
6565
using_pins &= ~BIT(offset);
6666
writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
6767

68-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
68+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
6969

7070
dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset);
7171
}

‎drivers/gpio/gpio-brcmstb.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -92,9 +92,9 @@ brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
9292
unsigned long status;
9393
unsigned long flags;
9494

95-
spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
95+
raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
9696
status = __brcmstb_gpio_get_active_irqs(bank);
97-
spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
97+
raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
9898

9999
return status;
100100
}
@@ -114,14 +114,14 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
114114
u32 imask;
115115
unsigned long flags;
116116

117-
spin_lock_irqsave(&gc->bgpio_lock, flags);
117+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
118118
imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
119119
if (enable)
120120
imask |= mask;
121121
else
122122
imask &= ~mask;
123123
gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
124-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
124+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
125125
}
126126

127127
static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
@@ -204,7 +204,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
204204
return -EINVAL;
205205
}
206206

207-
spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
207+
raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
208208

209209
iedge_config = bank->gc.read_reg(priv->reg_base +
210210
GIO_EC(bank->id)) & ~mask;
@@ -220,7 +220,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
220220
bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
221221
ilevel | level);
222222

223-
spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
223+
raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
224224
return 0;
225225
}
226226

‎drivers/gpio/gpio-cadence.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -41,12 +41,12 @@ static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)
4141
struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
4242
unsigned long flags;
4343

44-
spin_lock_irqsave(&chip->bgpio_lock, flags);
44+
raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
4545

4646
iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
4747
cgpio->regs + CDNS_GPIO_BYPASS_MODE);
4848

49-
spin_unlock_irqrestore(&chip->bgpio_lock, flags);
49+
raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
5050
return 0;
5151
}
5252

@@ -55,13 +55,13 @@ static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)
5555
struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
5656
unsigned long flags;
5757

58-
spin_lock_irqsave(&chip->bgpio_lock, flags);
58+
raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
5959

6060
iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
6161
(BIT(offset) & cgpio->bypass_orig),
6262
cgpio->regs + CDNS_GPIO_BYPASS_MODE);
6363

64-
spin_unlock_irqrestore(&chip->bgpio_lock, flags);
64+
raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
6565
}
6666

6767
static void cdns_gpio_irq_mask(struct irq_data *d)
@@ -90,7 +90,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
9090
u32 mask = BIT(d->hwirq);
9191
int ret = 0;
9292

93-
spin_lock_irqsave(&chip->bgpio_lock, flags);
93+
raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
9494

9595
int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
9696
int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
@@ -115,7 +115,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
115115
iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
116116

117117
err_irq_type:
118-
spin_unlock_irqrestore(&chip->bgpio_lock, flags);
118+
raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
119119
return ret;
120120
}
121121

‎drivers/gpio/gpio-dwapb.c‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -243,9 +243,9 @@ static void dwapb_irq_ack(struct irq_data *d)
243243
u32 val = BIT(irqd_to_hwirq(d));
244244
unsigned long flags;
245245

246-
spin_lock_irqsave(&gc->bgpio_lock, flags);
246+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
247247
dwapb_write(gpio, GPIO_PORTA_EOI, val);
248-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
248+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
249249
}
250250

251251
static void dwapb_irq_mask(struct irq_data *d)
@@ -255,10 +255,10 @@ static void dwapb_irq_mask(struct irq_data *d)
255255
unsigned long flags;
256256
u32 val;
257257

258-
spin_lock_irqsave(&gc->bgpio_lock, flags);
258+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
259259
val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
260260
dwapb_write(gpio, GPIO_INTMASK, val);
261-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
261+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
262262
}
263263

264264
static void dwapb_irq_unmask(struct irq_data *d)
@@ -268,10 +268,10 @@ static void dwapb_irq_unmask(struct irq_data *d)
268268
unsigned long flags;
269269
u32 val;
270270

271-
spin_lock_irqsave(&gc->bgpio_lock, flags);
271+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
272272
val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
273273
dwapb_write(gpio, GPIO_INTMASK, val);
274-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
274+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
275275
}
276276

277277
static void dwapb_irq_enable(struct irq_data *d)
@@ -281,11 +281,11 @@ static void dwapb_irq_enable(struct irq_data *d)
281281
unsigned long flags;
282282
u32 val;
283283

284-
spin_lock_irqsave(&gc->bgpio_lock, flags);
284+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
285285
val = dwapb_read(gpio, GPIO_INTEN);
286286
val |= BIT(irqd_to_hwirq(d));
287287
dwapb_write(gpio, GPIO_INTEN, val);
288-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
288+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
289289
}
290290

291291
static void dwapb_irq_disable(struct irq_data *d)
@@ -295,11 +295,11 @@ static void dwapb_irq_disable(struct irq_data *d)
295295
unsigned long flags;
296296
u32 val;
297297

298-
spin_lock_irqsave(&gc->bgpio_lock, flags);
298+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
299299
val = dwapb_read(gpio, GPIO_INTEN);
300300
val &= ~BIT(irqd_to_hwirq(d));
301301
dwapb_write(gpio, GPIO_INTEN, val);
302-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
302+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
303303
}
304304

305305
static int dwapb_irq_set_type(struct irq_data *d, u32 type)
@@ -309,7 +309,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
309309
irq_hw_number_t bit = irqd_to_hwirq(d);
310310
unsigned long level, polarity, flags;
311311

312-
spin_lock_irqsave(&gc->bgpio_lock, flags);
312+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
313313
level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
314314
polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
315315

@@ -344,7 +344,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
344344
dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
345345
if (type != IRQ_TYPE_EDGE_BOTH)
346346
dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
347-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
347+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
348348

349349
return 0;
350350
}
@@ -374,7 +374,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
374374
unsigned long flags, val_deb;
375375
unsigned long mask = BIT(offset);
376376

377-
spin_lock_irqsave(&gc->bgpio_lock, flags);
377+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
378378

379379
val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
380380
if (debounce)
@@ -383,7 +383,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
383383
val_deb &= ~mask;
384384
dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
385385

386-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
386+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
387387

388388
return 0;
389389
}
@@ -738,7 +738,7 @@ static int dwapb_gpio_suspend(struct device *dev)
738738
unsigned long flags;
739739
int i;
740740

741-
spin_lock_irqsave(&gc->bgpio_lock, flags);
741+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
742742
for (i = 0; i < gpio->nr_ports; i++) {
743743
unsigned int offset;
744744
unsigned int idx = gpio->ports[i].idx;
@@ -765,7 +765,7 @@ static int dwapb_gpio_suspend(struct device *dev)
765765
dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
766766
}
767767
}
768-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
768+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
769769

770770
clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
771771

@@ -785,7 +785,7 @@ static int dwapb_gpio_resume(struct device *dev)
785785
return err;
786786
}
787787

788-
spin_lock_irqsave(&gc->bgpio_lock, flags);
788+
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
789789
for (i = 0; i < gpio->nr_ports; i++) {
790790
unsigned int offset;
791791
unsigned int idx = gpio->ports[i].idx;
@@ -812,7 +812,7 @@ static int dwapb_gpio_resume(struct device *dev)
812812
dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
813813
}
814814
}
815-
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
815+
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
816816

817817
return 0;
818818
}

‎drivers/gpio/gpio-grgpio.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -145,15 +145,15 @@ static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
145145
return -EINVAL;
146146
}
147147

148-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
148+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
149149

150150
ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
151151
iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
152152

153153
priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
154154
priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
155155

156-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
156+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
157157

158158
return 0;
159159
}
@@ -164,11 +164,11 @@ static void grgpio_irq_mask(struct irq_data *d)
164164
int offset = d->hwirq;
165165
unsigned long flags;
166166

167-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
167+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
168168

169169
grgpio_set_imask(priv, offset, 0);
170170

171-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
171+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
172172
}
173173

174174
static void grgpio_irq_unmask(struct irq_data *d)
@@ -177,11 +177,11 @@ static void grgpio_irq_unmask(struct irq_data *d)
177177
int offset = d->hwirq;
178178
unsigned long flags;
179179

180-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
180+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
181181

182182
grgpio_set_imask(priv, offset, 1);
183183

184-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
184+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
185185
}
186186

187187
static struct irq_chip grgpio_irq_chip = {
@@ -199,7 +199,7 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev)
199199
int i;
200200
int match = 0;
201201

202-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
202+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
203203

204204
/*
205205
* For each gpio line, call its interrupt handler if it its underlying
@@ -215,7 +215,7 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev)
215215
}
216216
}
217217

218-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
218+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
219219

220220
if (!match)
221221
dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
@@ -247,13 +247,13 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
247247
dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
248248
irq, offset);
249249

250-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
250+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
251251

252252
/* Request underlying irq if not already requested */
253253
lirq->irq = irq;
254254
uirq = &priv->uirqs[lirq->index];
255255
if (uirq->refcnt == 0) {
256-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
256+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
257257
ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
258258
dev_name(priv->dev), priv);
259259
if (ret) {
@@ -262,11 +262,11 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
262262
uirq->uirq);
263263
return ret;
264264
}
265-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
265+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
266266
}
267267
uirq->refcnt++;
268268

269-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
269+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
270270

271271
/* Setup irq */
272272
irq_set_chip_data(irq, priv);
@@ -290,7 +290,7 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
290290
irq_set_chip_and_handler(irq, NULL, NULL);
291291
irq_set_chip_data(irq, NULL);
292292

293-
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
293+
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
294294

295295
/* Free underlying irq if last user unmapped */
296296
index = -1;
@@ -309,13 +309,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
309309
uirq = &priv->uirqs[lirq->index];
310310
uirq->refcnt--;
311311
if (uirq->refcnt == 0) {
312-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
312+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
313313
free_irq(uirq->uirq, priv);
314314
return;
315315
}
316316
}
317317

318-
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
318+
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
319319
}
320320

321321
static const struct irq_domain_ops grgpio_irq_domain_ops = {

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