@@ -462,32 +462,53 @@ static int lan78xx_read_raw_eeprom(struct lan78xx_net *dev, u32 offset,
462462 u32 length , u8 * data )
463463{
464464 u32 val ;
465+ u32 saved ;
465466 int i , ret ;
467+ int retval ;
466468
467- ret = lan78xx_eeprom_confirm_not_busy (dev );
468- if (ret )
469- return ret ;
469+ /* depends on chip, some EEPROM pins are muxed with LED function.
470+ * disable & restore LED function to access EEPROM.
471+ */
472+ ret = lan78xx_read_reg (dev , HW_CFG , & val );
473+ saved = val ;
474+ if ((dev -> devid & ID_REV_CHIP_ID_MASK_ ) == 0x78000000 ) {
475+ val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_ );
476+ ret = lan78xx_write_reg (dev , HW_CFG , val );
477+ }
478+
479+ retval = lan78xx_eeprom_confirm_not_busy (dev );
480+ if (retval )
481+ return retval ;
470482
471483 for (i = 0 ; i < length ; i ++ ) {
472484 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ ;
473485 val |= (offset & E2P_CMD_EPC_ADDR_MASK_ );
474486 ret = lan78xx_write_reg (dev , E2P_CMD , val );
475- if (unlikely (ret < 0 ))
476- return - EIO ;
487+ if (unlikely (ret < 0 )) {
488+ retval = - EIO ;
489+ goto exit ;
490+ }
477491
478- ret = lan78xx_wait_eeprom (dev );
479- if (ret < 0 )
480- return ret ;
492+ retval = lan78xx_wait_eeprom (dev );
493+ if (retval < 0 )
494+ goto exit ;
481495
482496 ret = lan78xx_read_reg (dev , E2P_DATA , & val );
483- if (unlikely (ret < 0 ))
484- return - EIO ;
497+ if (unlikely (ret < 0 )) {
498+ retval = - EIO ;
499+ goto exit ;
500+ }
485501
486502 data [i ] = val & 0xFF ;
487503 offset ++ ;
488504 }
489505
490- return 0 ;
506+ retval = 0 ;
507+ exit :
508+ if ((dev -> devid & ID_REV_CHIP_ID_MASK_ ) == 0x78000000 )
509+ ret = lan78xx_write_reg (dev , HW_CFG , saved );
510+
511+ return retval ;
491512}
492513
493514static int lan78xx_read_eeprom (struct lan78xx_net * dev , u32 offset ,
@@ -509,44 +530,67 @@ static int lan78xx_write_raw_eeprom(struct lan78xx_net *dev, u32 offset,
509530 u32 length , u8 * data )
510531{
511532 u32 val ;
533+ u32 saved ;
512534 int i , ret ;
535+ int retval ;
513536
514- ret = lan78xx_eeprom_confirm_not_busy (dev );
515- if (ret )
516- return ret ;
537+ /* depends on chip, some EEPROM pins are muxed with LED function.
538+ * disable & restore LED function to access EEPROM.
539+ */
540+ ret = lan78xx_read_reg (dev , HW_CFG , & val );
541+ saved = val ;
542+ if ((dev -> devid & ID_REV_CHIP_ID_MASK_ ) == 0x78000000 ) {
543+ val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_ );
544+ ret = lan78xx_write_reg (dev , HW_CFG , val );
545+ }
546+
547+ retval = lan78xx_eeprom_confirm_not_busy (dev );
548+ if (retval )
549+ goto exit ;
517550
518551 /* Issue write/erase enable command */
519552 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_ ;
520553 ret = lan78xx_write_reg (dev , E2P_CMD , val );
521- if (unlikely (ret < 0 ))
522- return - EIO ;
554+ if (unlikely (ret < 0 )) {
555+ retval = - EIO ;
556+ goto exit ;
557+ }
523558
524- ret = lan78xx_wait_eeprom (dev );
525- if (ret < 0 )
526- return ret ;
559+ retval = lan78xx_wait_eeprom (dev );
560+ if (retval < 0 )
561+ goto exit ;
527562
528563 for (i = 0 ; i < length ; i ++ ) {
529564 /* Fill data register */
530565 val = data [i ];
531566 ret = lan78xx_write_reg (dev , E2P_DATA , val );
532- if (ret < 0 )
533- return ret ;
567+ if (ret < 0 ) {
568+ retval = - EIO ;
569+ goto exit ;
570+ }
534571
535572 /* Send "write" command */
536573 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ ;
537574 val |= (offset & E2P_CMD_EPC_ADDR_MASK_ );
538575 ret = lan78xx_write_reg (dev , E2P_CMD , val );
539- if (ret < 0 )
540- return ret ;
576+ if (ret < 0 ) {
577+ retval = - EIO ;
578+ goto exit ;
579+ }
541580
542- ret = lan78xx_wait_eeprom (dev );
543- if (ret < 0 )
544- return ret ;
581+ retval = lan78xx_wait_eeprom (dev );
582+ if (retval < 0 )
583+ goto exit ;
545584
546585 offset ++ ;
547586 }
548587
549- return 0 ;
588+ retval = 0 ;
589+ exit :
590+ if ((dev -> devid & ID_REV_CHIP_ID_MASK_ ) == 0x78000000 )
591+ ret = lan78xx_write_reg (dev , HW_CFG , saved );
592+
593+ return retval ;
550594}
551595
552596static int lan78xx_read_raw_otp (struct lan78xx_net * dev , u32 offset ,
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