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[LLVM Pulldown] Bump to LLVM rev 92164faf17d553359418b9f49c1a41d680d0… (#1104)
Brings Slice attribute def (llvm/llvm-project#150146)
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15 files changed

+144
-166
lines changed

15 files changed

+144
-166
lines changed

‎build_tools/llvm_version.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
228e96b28a84828e1720c387a339a7e68dbdc029
1+
92164faf17d553359418b9f49c1a41d680d0de49

‎build_tools/patches/0001-Add-support-for-VectorAnyINTEL-capability.patch‎

Lines changed: 68 additions & 70 deletions
Large diffs are not rendered by default.

‎build_tools/patches/0004-Add-serialization-and-de-serialization-support-for-s.patch‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,37 @@
1-
From 89e527e48b727a1479aa47fdbe3d2d178d8969a7 Mon Sep 17 00:00:00 2001
1+
From 5900db1c91d40157c2724d324ea65e22936e3354 Mon Sep 17 00:00:00 2001
22
From: Garra1980 <[email protected]>
3-
Date: Mon, 4 Aug 2025 17:50:56 +0200
4-
Subject: [PATCH] Add serilialization and deserialization for spirv
3+
Date: Tue, 12 Aug 2025 23:41:51 +0200
4+
Subject: [PATCH] Add serialization and de-serialization support for spirv
55

66
---
77
mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp | 6 ++++++
88
mlir/lib/Target/SPIRV/Serialization/Serializer.cpp | 6 ++++++
99
2 files changed, 12 insertions(+)
1010

1111
diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
12-
index 88931b53a688..f1c22d09cc8e 100644
12+
index d8c54ec5f88c..3b539382dedd 100644
1313
--- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
1414
+++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
15-
@@ -282,6 +282,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
15+
@@ -283,6 +283,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
1616
symbol, FPRoundingModeAttr::get(opBuilder.getContext(),
1717
static_cast<FPRoundingMode>(words[2])));
1818
break;
1919
+ case spirv::Decoration::Alignment:
2020
case spirv::Decoration::DescriptorSet:
2121
case spirv::Decoration::Binding:
2222
if (words.size() != 3) {
23-
@@ -343,6 +344,10 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
24-
case spirv::Decoration::RestrictPointer:
25-
case spirv::Decoration::NoContraction:
23+
@@ -346,6 +347,10 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
2624
case spirv::Decoration::Constant:
25+
case spirv::Decoration::Invariant:
26+
case spirv::Decoration::Patch:
2727
+ case spirv::Decoration::SingleElementVectorINTEL:
2828
+ case spirv::Decoration::VectorComputeCallableFunctionINTEL:
2929
+ case spirv::Decoration::VectorComputeFunctionINTEL:
3030
+ case spirv::Decoration::VectorComputeVariableINTEL:
3131
if (words.size() != 2) {
3232
return emitError(unknownLoc, "OpDecoration with ")
3333
<< decorationName << "needs a single target <id>";
34-
@@ -351,6 +356,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
34+
@@ -354,6 +359,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
3535
break;
3636
case spirv::Decoration::Location:
3737
case spirv::Decoration::SpecId:
@@ -40,10 +40,10 @@ index 88931b53a688..f1c22d09cc8e 100644
4040
return emitError(unknownLoc, "OpDecoration with ")
4141
<< decorationName << "needs a single integer literal";
4242
diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
43-
index 737f29662f64..cd925b02b6a6 100644
43+
index 7c007de31558..3aa26ab923a9 100644
4444
--- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
4545
+++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
46-
@@ -283,8 +283,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
46+
@@ -302,8 +302,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
4747
}
4848
return emitError(loc, "expected FPRoundingModeAttr attribute for ")
4949
<< stringifyDecoration(decoration);
@@ -54,17 +54,16 @@ index 737f29662f64..cd925b02b6a6 100644
5454
case spirv::Decoration::Location:
5555
if (auto intAttr = dyn_cast<IntegerAttr>(attr)) {
5656
args.push_back(intAttr.getValue().getZExtValue());
57-
@@ -318,6 +320,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
58-
case spirv::Decoration::RestrictPointer:
59-
case spirv::Decoration::NoContraction:
60-
case spirv::Decoration::Constant:
57+
@@ -340,6 +342,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
58+
case spirv::Decoration::Block:
59+
case spirv::Decoration::Invariant:
60+
case spirv::Decoration::Patch:
6161
+ case spirv::Decoration::SingleElementVectorINTEL:
6262
+ case spirv::Decoration::VectorComputeCallableFunctionINTEL:
6363
+ case spirv::Decoration::VectorComputeFunctionINTEL:
6464
+ case spirv::Decoration::VectorComputeVariableINTEL:
65-
case spirv::Decoration::Block:
6665
// For unit attributes and decoration attributes, the args list
6766
// has no values so we do nothing.
68-
--
67+
if (isa<UnitAttr, DecorationAttr>(attr))
68+
--
6969
2.34.1
70-

‎build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ index 7f4d4f1381df..ebd4f1a3f66a 100644
1414
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
1515
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
1616
@@ -373,6 +373,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
17-
OptionalAttr<DenseI64ArrayAttr>: $const_offsets,
17+
OptionalAttr<DenseI64ArrayAttr>: $const_offsets,
1818
OptionalAttr<UnitAttr>: $packed,
1919
OptionalAttr<DenseI64ArrayAttr>: $transpose,
2020
+ OptionalAttr<I32Attr>: $transpose_bit_width,
@@ -24,7 +24,7 @@ index 7f4d4f1381df..ebd4f1a3f66a 100644
2424
@@ -1147,4 +1148,9 @@ def XeGPU_ConvertLayoutOp: XeGPU_Op<"convert_layout", [Pure, AllTypesMatch<["sou
2525
let hasCanonicalizer = 1;
2626
}
27-
27+
2828
+def XeGPU_CompileHintOp : XeGPU_Op<"compile_hint", []> {
2929
+ let summary = "prevents the compiler from scheduling.";
3030
+ let assemblyFormat = [{ attr-dict }];
@@ -68,27 +68,26 @@ index 33450f3fa229..528b9d55ee61 100644
6868
+ kind == CachePolicy::STREAMING ||
6969
kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
7070
}
71-
71+
7272
@@ -419,8 +420,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
7373
xegpu::CachePolicyAttr l3_hint) {
74-
74+
7575
return build(builder, state, retType, tensorDesc, ValueRange(),
7676
- DenseI64ArrayAttr(), packed, transpose, l1_hint, l2_hint,
7777
- l3_hint);
7878
+ DenseI64ArrayAttr(), packed, transpose, nullptr,
7979
+ l1_hint, l2_hint, l3_hint);
8080
}
81-
81+
8282
LogicalResult LoadNdOp::verify() {
8383
@@ -482,7 +483,7 @@ LogicalResult LoadNdOp::verify() {
8484
mlir::emitWarning(getLoc()) << "Invalid transpose attr. It is ignored.";
8585
}
86-
86+
8787
- if (getPacked()) {
8888
+ if (getPacked() || getTransposeBitWidth() == 32) {
8989
if (tdescTy.getRank() == 2) {
9090
const int axis = 0;
9191
auto vnni_factor = valueShape.back();
92-
--
92+
--
9393
2.34.1
94-

‎lib/Conversion/XeGPUToVC/LSCPatterns.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1198,9 +1198,9 @@ class PrefetchPattern : public OpConversionPattern<PrefetchOp> {
11981198
// auto l2hint = op.getL2Hint();
11991199
auto l3hint = op.getL3Hint();
12001200

1201-
auto callOp = genPrefetchIntrinsicCall(rewriter, loc, simd_lanes, l1hint,
1202-
l3hint, elemTy, chunkSize, scope,
1203-
adaptor.getSource());
1201+
auto callOp =
1202+
genPrefetchIntrinsicCall(rewriter, loc, simd_lanes, l1hint, l3hint,
1203+
elemTy, chunkSize, scope, adaptor.getSource());
12041204

12051205
rewriter.replaceOp(op, callOp);
12061206
return success();

‎lib/Conversion/XeTileToXeGPU/XeTileToXeGPU.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -491,10 +491,9 @@ class LoadOpPattern : public OpConversionPattern<xetile::LoadTileOp> {
491491
auto packAttr = UnitAttr();
492492
auto transAttr = DenseI64ArrayAttr();
493493
auto bitWidthAttr = IntegerAttr();
494-
auto ldOp = rewriter.create<xegpu::LoadNdOp>(loc, vecTy, adaptor.getTile(),
495-
ValueRange(), DenseI64ArrayAttr(),
496-
packAttr, transAttr,
497-
bitWidthAttr, L1, L2, L3);
494+
auto ldOp = rewriter.create<xegpu::LoadNdOp>(
495+
loc, vecTy, adaptor.getTile(), ValueRange(), DenseI64ArrayAttr(),
496+
packAttr, transAttr, bitWidthAttr, L1, L2, L3);
498497

499498
llvm::SmallVector<Value> results({ldOp.getResult()});
500499
if (memSpace == xegpu::MemorySpace::SLM) {

‎lib/Dialect/NDArray/Extensions/MeshShardingExtensions.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ static T getBaseShardDimOff(T shard, T numShards, T extend) {
100100
}
101101

102102
static Sharding ShardingFromOption(const ShardingOption &option,
103-
MLIRContext *ctxt) {
103+
MLIRContext *ctxt) {
104104
SmallVector<GridAxesAttr> res;
105105
for (const auto &v : option.shardingArray) {
106106
res.emplace_back(GridAxesAttr::get(ctxt, v));
@@ -141,7 +141,8 @@ getShardingWithShardedDimsOffs(Value ary, OffsetSizeAndStrideOpInterface op) {
141141
ShapedType::isDynamicShape(strides))
142142
return op->emitOpError("Dynamic offsets/sizes/strides are not supported");
143143

144-
auto arySharding = aryShardOp.getSharding().getDefiningOp<shard::ShardingOp>();
144+
auto arySharding =
145+
aryShardOp.getSharding().getDefiningOp<shard::ShardingOp>();
145146
// currently no support for sharding dims sizes on input
146147
if (!arySharding.getStaticShardedDimsOffsets().empty())
147148
return op->emitOpError(
@@ -190,10 +191,9 @@ getShardingWithShardedDimsOffs(Value ary, OffsetSizeAndStrideOpInterface op) {
190191
}
191192
}
192193

193-
return Sharding::get(
194-
arySharding.getGridAttr(), arySharding.getSplitAxes().getAxes(),
195-
{}, // static halo
196-
splitOffs, {}, {});
194+
return Sharding::get(arySharding.getGridAttr(),
195+
arySharding.getSplitAxes().getAxes(), {}, // static halo
196+
splitOffs, {}, {});
197197
}
198198

199199
static std::pair<Value, Value>

‎lib/Dialect/XeTile/Transforms/Blocking.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1042,8 +1042,8 @@ class RewriteTileReductionOp
10421042
for (auto v : intermediates) {
10431043
auto resultTy = VectorType::get({1, 1}, elemTy);
10441044
for (auto i = 0; i < blkSize[1]; i++) {
1045-
auto extractOp =
1046-
rewriter.create<vector::ExtractOp>(loc, v, rewriter.getIndexAttr(i));
1045+
auto extractOp = rewriter.create<vector::ExtractOp>(
1046+
loc, v, rewriter.getIndexAttr(i));
10471047
auto splatOp = rewriter.create<vector::SplatOp>(op.getLoc(), resultTy,
10481048
extractOp);
10491049
newOps.push_back(splatOp);

‎lib/Target/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
add_subdirectory(LLVM)
1+
add_subdirectory(LLVM)

‎lib/Transforms/OptimizeTranspose.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -516,10 +516,10 @@ struct LoadNdOpPattern : public OpConversionPattern<xegpu::LoadNdOp> {
516516
op.getType().getElementType());
517517
for (auto source : tdescSources) {
518518
auto loadNdOp = rewriter.create<xegpu::LoadNdOp>(
519-
op.getLoc(), newLoadTy, source,
520-
ValueRange(), DenseI64ArrayAttr(), op.getPackedAttr(),
521-
op.getTransposeAttr(), op.getTransposeBitWidthAttr(),
522-
op.getL1HintAttr(), op.getL2HintAttr(), op.getL3HintAttr());
519+
op.getLoc(), newLoadTy, source, ValueRange(), DenseI64ArrayAttr(),
520+
op.getPackedAttr(), op.getTransposeAttr(),
521+
op.getTransposeBitWidthAttr(), op.getL1HintAttr(), op.getL2HintAttr(),
522+
op.getL3HintAttr());
523523
loadNdOps.push_back(loadNdOp);
524524
}
525525
rewriter.replaceOpWithMultiple(op, {loadNdOps});
@@ -847,10 +847,10 @@ struct TransposeRewritePattern : public OpRewritePattern<vector::TransposeOp> {
847847
rewriter.getIntegerType(32),
848848
32); // need to do a 32 bit transpose to get the packed layout.
849849
auto newLoadOp = rewriter.create<xegpu::LoadNdOp>(
850-
loadOp.getLoc(), newVectorTy, loadOp.getTensorDesc(),
851-
ValueRange(), DenseI64ArrayAttr(), packedAttr,
852-
transposeAttr, transposeBitWidthAttr, loadOp.getL1HintAttr(),
853-
loadOp.getL2HintAttr(), loadOp.getL3HintAttr());
850+
loadOp.getLoc(), newVectorTy, loadOp.getTensorDesc(), ValueRange(),
851+
DenseI64ArrayAttr(), packedAttr, transposeAttr, transposeBitWidthAttr,
852+
loadOp.getL1HintAttr(), loadOp.getL2HintAttr(),
853+
loadOp.getL3HintAttr());
854854
// Replace the uses of the packed layout conversion with new load.
855855
rewriter.replaceAllUsesWith(packedLayoutOps.back()->getResult(0),
856856
newLoadOp.getResult());
@@ -872,10 +872,10 @@ struct TransposeRewritePattern : public OpRewritePattern<vector::TransposeOp> {
872872
auto transposeAttr =
873873
DenseI64ArrayAttr::get(rewriter.getContext(), {1, 0});
874874
auto newLoadOp = rewriter.create<xegpu::LoadNdOp>(
875-
loadOp.getLoc(), newVectorTy, loadOp.getTensorDesc(),
876-
ValueRange(), DenseI64ArrayAttr(), packedAttr,
877-
transposeAttr, IntegerAttr(), loadOp.getL1HintAttr(),
878-
loadOp.getL2HintAttr(), loadOp.getL3HintAttr());
875+
loadOp.getLoc(), newVectorTy, loadOp.getTensorDesc(), ValueRange(),
876+
DenseI64ArrayAttr(), packedAttr, transposeAttr, IntegerAttr(),
877+
loadOp.getL1HintAttr(), loadOp.getL2HintAttr(),
878+
loadOp.getL3HintAttr());
879879
rewriter.replaceAllUsesWith(op.getResult(), newLoadOp.getResult());
880880
}
881881

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