diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs
index 19a29edff236d..71d0488b32790 100644
--- a/.git-blame-ignore-revs
+++ b/.git-blame-ignore-revs
@@ -16,3 +16,9 @@
 
 # r280751: [Coding style change][lldb] Moved LLDB code base to use LLVM style
 b9c1b51e45b845debb76d8658edabca70ca56079
+
+# r302421: That change incorrectly changed line endings in some libc++ files
+9669df28d4fd3c52d09f451186bd217cdc3322c0
+
+# r302496: That is the revert of r302421
+ff63090b0e1072bd398b8efef8ae2291613a6ec9
diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp
index 6ff60495a72be..b7f5eb6e1e334 100644
--- a/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp
+++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp
@@ -25,12 +25,16 @@ SpecialMemberFunctionsCheck::SpecialMemberFunctionsCheck(
     StringRef Name, ClangTidyContext *Context)
     : ClangTidyCheck(Name, Context),
       AllowMissingMoveFunctions(Options.get("AllowMissingMoveFunctions", 0)),
-      AllowSoleDefaultDtor(Options.get("AllowSoleDefaultDtor", 0)) {}
+      AllowSoleDefaultDtor(Options.get("AllowSoleDefaultDtor", 0)),
+      AllowMissingMoveFunctionsWhenCopyIsDeleted(
+          Options.get("AllowMissingMoveFunctionsWhenCopyIsDeleted", 0)) {}
 
 void SpecialMemberFunctionsCheck::storeOptions(
     ClangTidyOptions::OptionMap &Opts) {
   Options.store(Opts, "AllowMissingMoveFunctions", AllowMissingMoveFunctions);
   Options.store(Opts, "AllowSoleDefaultDtor", AllowSoleDefaultDtor);
+  Options.store(Opts, "AllowMissingMoveFunctionsWhenCopyIsDeleted",
+                AllowMissingMoveFunctionsWhenCopyIsDeleted);
 }
 
 void SpecialMemberFunctionsCheck::registerMatchers(MatchFinder *Finder) {
@@ -103,17 +107,18 @@ void SpecialMemberFunctionsCheck::check(
 
   ClassDefId ID(MatchedDecl->getLocation(), std::string(MatchedDecl->getName()));
 
-  auto StoreMember = [this, &ID](SpecialMemberFunctionKind Kind) {
-    llvm::SmallVectorImpl<SpecialMemberFunctionKind> &Members =
+  auto StoreMember = [this, &ID](SpecialMemberFunctionData data) {
+    llvm::SmallVectorImpl<SpecialMemberFunctionData> &Members =
         ClassWithSpecialMembers[ID];
-    if (!llvm::is_contained(Members, Kind))
-      Members.push_back(Kind);
+    if (!llvm::is_contained(Members, data))
+      Members.push_back(std::move(data));
   };
 
   if (const auto *Dtor = Result.Nodes.getNodeAs<CXXMethodDecl>("dtor")) {
-    StoreMember(Dtor->isDefaulted()
-                    ? SpecialMemberFunctionKind::DefaultDestructor
-                    : SpecialMemberFunctionKind::NonDefaultDestructor);
+    StoreMember({Dtor->isDefaulted()
+                     ? SpecialMemberFunctionKind::DefaultDestructor
+                     : SpecialMemberFunctionKind::NonDefaultDestructor,
+                 Dtor->isDeleted()});
   }
 
   std::initializer_list<std::pair<std::string, SpecialMemberFunctionKind>>
@@ -123,8 +128,9 @@ void SpecialMemberFunctionsCheck::check(
                   {"move-assign", SpecialMemberFunctionKind::MoveAssignment}};
 
   for (const auto &KV : Matchers)
-    if (Result.Nodes.getNodeAs<CXXMethodDecl>(KV.first)) {
-      StoreMember(KV.second);
+    if (const auto *MethodDecl =
+            Result.Nodes.getNodeAs<CXXMethodDecl>(KV.first)) {
+      StoreMember({KV.second, MethodDecl->isDeleted()});
     }
 }
 
@@ -136,11 +142,19 @@ void SpecialMemberFunctionsCheck::onEndOfTranslationUnit() {
 
 void SpecialMemberFunctionsCheck::checkForMissingMembers(
     const ClassDefId &ID,
-    llvm::ArrayRef<SpecialMemberFunctionKind> DefinedMembers) {
+    llvm::ArrayRef<SpecialMemberFunctionData> DefinedMembers) {
   llvm::SmallVector<SpecialMemberFunctionKind, 5> MissingMembers;
 
   auto HasMember = [&](SpecialMemberFunctionKind Kind) {
-    return llvm::is_contained(DefinedMembers, Kind);
+    return llvm::any_of(DefinedMembers, [Kind](const auto &data) {
+      return data.FunctionKind == Kind;
+    });
+  };
+
+  auto IsDeleted = [&](SpecialMemberFunctionKind Kind) {
+    return llvm::any_of(DefinedMembers, [Kind](const auto &data) {
+      return data.FunctionKind == Kind && data.IsDeleted;
+    });
   };
 
   auto RequireMember = [&](SpecialMemberFunctionKind Kind) {
@@ -171,16 +185,23 @@ void SpecialMemberFunctionsCheck::checkForMissingMembers(
     RequireMember(SpecialMemberFunctionKind::CopyAssignment);
   }
 
-  if (RequireFive) {
+  if (RequireFive &&
+      !(AllowMissingMoveFunctionsWhenCopyIsDeleted &&
+        (IsDeleted(SpecialMemberFunctionKind::CopyConstructor) &&
+         IsDeleted(SpecialMemberFunctionKind::CopyAssignment)))) {
     assert(RequireThree);
     RequireMember(SpecialMemberFunctionKind::MoveConstructor);
     RequireMember(SpecialMemberFunctionKind::MoveAssignment);
   }
 
-  if (!MissingMembers.empty())
+  if (!MissingMembers.empty()) {
+    llvm::SmallVector<SpecialMemberFunctionKind, 5> DefinedMemberKinds;
+    llvm::transform(DefinedMembers, std::back_inserter(DefinedMemberKinds),
+                    [](const auto &data) { return data.FunctionKind; });
     diag(ID.first, "class '%0' defines %1 but does not define %2")
-        << ID.second << cppcoreguidelines::join(DefinedMembers, " and ")
+        << ID.second << cppcoreguidelines::join(DefinedMemberKinds, " and ")
         << cppcoreguidelines::join(MissingMembers, " or ");
+  }
 }
 
 } // namespace cppcoreguidelines
diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h b/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
index 29982ba4796ae..78468cc5c31ef 100644
--- a/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
+++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
@@ -43,19 +43,30 @@ class SpecialMemberFunctionsCheck : public ClangTidyCheck {
     MoveAssignment
   };
 
+  struct SpecialMemberFunctionData {
+    SpecialMemberFunctionKind FunctionKind;
+    bool IsDeleted;
+
+    bool operator==(const SpecialMemberFunctionData &Other) {
+      return (Other.FunctionKind == FunctionKind) &&
+             (Other.IsDeleted == IsDeleted);
+    }
+  };
+
   using ClassDefId = std::pair<SourceLocation, std::string>;
 
   using ClassDefiningSpecialMembersMap =
       llvm::DenseMap<ClassDefId,
-                     llvm::SmallVector<SpecialMemberFunctionKind, 5>>;
+                     llvm::SmallVector<SpecialMemberFunctionData, 5>>;
 
 private:
   void checkForMissingMembers(
       const ClassDefId &ID,
-      llvm::ArrayRef<SpecialMemberFunctionKind> DefinedSpecialMembers);
+      llvm::ArrayRef<SpecialMemberFunctionData> DefinedSpecialMembers);
 
   const bool AllowMissingMoveFunctions;
   const bool AllowSoleDefaultDtor;
+  const bool AllowMissingMoveFunctionsWhenCopyIsDeleted;
   ClassDefiningSpecialMembersMap ClassWithSpecialMembers;
 };
 
diff --git a/clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp b/clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp
index cbec56fbf7a59..fefa56ae5ef5e 100644
--- a/clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp
+++ b/clang-tools-extra/clang-tidy/modernize/LoopConvertCheck.cpp
@@ -649,9 +649,14 @@ StringRef LoopConvertCheck::getContainerString(ASTContext *Context,
                                                const ForStmt *Loop,
                                                const Expr *ContainerExpr) {
   StringRef ContainerString;
-  if (isa<CXXThisExpr>(ContainerExpr->IgnoreParenImpCasts())) {
+  ContainerExpr = ContainerExpr->IgnoreParenImpCasts();
+  if (isa<CXXThisExpr>(ContainerExpr)) {
     ContainerString = "this";
   } else {
+    // For CXXOperatorCallExpr (e.g. vector_ptr->size()), its first argument is
+    // the class object (vector_ptr) we are targeting.
+    if (const auto* E = dyn_cast<CXXOperatorCallExpr>(ContainerExpr))
+      ContainerExpr = E->getArg(0);
     ContainerString =
         getStringFromRange(Context->getSourceManager(), Context->getLangOpts(),
                            ContainerExpr->getSourceRange());
diff --git a/clang-tools-extra/clangd/FindTarget.cpp b/clang-tools-extra/clangd/FindTarget.cpp
index 4528e2a771648..3757f4da97f94 100644
--- a/clang-tools-extra/clangd/FindTarget.cpp
+++ b/clang-tools-extra/clangd/FindTarget.cpp
@@ -37,6 +37,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/raw_ostream.h"
+#include <iterator>
 #include <utility>
 #include <vector>
 
@@ -76,6 +77,11 @@ std::vector<const NamedDecl *> getMembersReferencedViaDependentName(
     bool IsNonstaticMember) {
   if (!T)
     return {};
+  if (auto *ET = T->getAs<EnumType>()) {
+    auto Result =
+        ET->getDecl()->lookup(NameFactory(ET->getDecl()->getASTContext()));
+    return {Result.begin(), Result.end()};
+  }
   if (auto *ICNT = T->getAs<InjectedClassNameType>()) {
     T = ICNT->getInjectedSpecializationType().getTypePtrOrNull();
   }
diff --git a/clang-tools-extra/clangd/FormattedString.cpp b/clang-tools-extra/clangd/FormattedString.cpp
index 9cb732eabcf84..ecbc060a870a4 100644
--- a/clang-tools-extra/clangd/FormattedString.cpp
+++ b/clang-tools-extra/clangd/FormattedString.cpp
@@ -12,6 +12,7 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/raw_ostream.h"
@@ -26,23 +27,143 @@ namespace clangd {
 namespace markup {
 
 namespace {
+
+// Is <contents a plausible start to an HTML tag?
+// Contents may not be the rest of the line, but it's the rest of the plain
+// text, so we expect to see at least the tag name.
+bool looksLikeTag(llvm::StringRef Contents) {
+  if (Contents.empty())
+    return false;
+  if (Contents.front() == '!' || Contents.front() == '?' ||
+      Contents.front() == '/')
+    return true;
+  // Check the start of the tag name.
+  if (!llvm::isAlpha(Contents.front()))
+    return false;
+  // Drop rest of the tag name, and following whitespace.
+  Contents = Contents
+                 .drop_while([](char C) {
+                   return llvm::isAlnum(C) || C == '-' || C == '_' || C == ':';
+                 })
+                 .drop_while(isWhitespace);
+  // The rest of the tag consists of attributes, which have restrictive names.
+  // If we hit '=', all bets are off (attribute values can contain anything).
+  for (; !Contents.empty(); Contents = Contents.drop_front()) {
+    if (llvm::isAlnum(Contents.front()) || isWhitespace(Contents.front()))
+      continue;
+    if (Contents.front() == '>' || Contents.startswith("/>"))
+      return true; // May close the tag.
+    if (Contents.front() == '=')
+      return true; // Don't try to parse attribute values.
+    return false;  // Random punctuation means this isn't a tag.
+  }
+  return true; // Potentially incomplete tag.
+}
+
+// Tests whether C should be backslash-escaped in markdown.
+// The string being escaped is Before + C + After. This is part of a paragraph.
+// StartsLine indicates whether `Before` is the start of the line.
+// After may not be everything until the end of the line.
+//
+// It's always safe to escape punctuation, but want minimal escaping.
+// The strategy is to escape the first character of anything that might start
+// a markdown grammar construct.
+bool needsLeadingEscape(char C, llvm::StringRef Before, llvm::StringRef After,
+                        bool StartsLine) {
+  assert(Before.take_while(isWhitespace).empty());
+  auto RulerLength = [&]() -> /*Length*/ unsigned {
+    if (!StartsLine || !Before.empty())
+      return false;
+    llvm::StringRef A = After.rtrim();
+    return llvm::all_of(A, [C](char D) { return C == D; }) ? 1 + A.size() : 0;
+  };
+  auto IsBullet = [&]() {
+    return StartsLine && Before.empty() &&
+           (After.empty() || After.startswith(" "));
+  };
+  auto SpaceSurrounds = [&]() {
+    return (After.empty() || isWhitespace(After.front())) &&
+           (Before.empty() || isWhitespace(Before.back()));
+  };
+  auto WordSurrounds = [&]() {
+    return (!After.empty() && llvm::isAlnum(After.front())) &&
+           (!Before.empty() && llvm::isAlnum(Before.back()));
+  };
+
+  switch (C) {
+  case '\\': // Escaped character.
+    return true;
+  case '`': // Code block or inline code
+    // Any number of backticks can delimit an inline code block that can end
+    // anywhere (including on another line). We must escape them all.
+    return true;
+  case '~': // Code block
+    return StartsLine && Before.empty() && After.startswith("~~");
+  case '#': { // ATX heading.
+    if (!StartsLine || !Before.empty())
+      return false;
+    llvm::StringRef Rest = After.ltrim(C);
+    return Rest.empty() || Rest.startswith(" ");
+  }
+  case ']': // Link or link reference.
+    // We escape ] rather than [ here, because it's more constrained:
+    //   ](...) is an in-line link
+    //   ]: is a link reference
+    // The following are only links if the link reference exists:
+    //   ] by itself is a shortcut link
+    //   ][...] is an out-of-line link
+    // Because we never emit link references, we don't need to handle these.
+    return After.startswith(":") || After.startswith("(");
+  case '=': // Setex heading.
+    return RulerLength() > 0;
+  case '_': // Horizontal ruler or matched delimiter.
+    if (RulerLength() >= 3)
+      return true;
+    // Not a delimiter if surrounded by space, or inside a word.
+    // (The rules at word boundaries are subtle).
+    return !(SpaceSurrounds() || WordSurrounds());
+  case '-': // Setex heading, horizontal ruler, or bullet.
+    if (RulerLength() > 0)
+      return true;
+    return IsBullet();
+  case '+': // Bullet list.
+    return IsBullet();
+  case '*': // Bullet list, horizontal ruler, or delimiter.
+    return IsBullet() || RulerLength() >= 3 || !SpaceSurrounds();
+  case '<': // HTML tag (or autolink, which we choose not to escape)
+    return looksLikeTag(After);
+  case '>': // Quote marker. Needs escaping at start of line.
+    return StartsLine && Before.empty();
+  case '&': { // HTML entity reference
+    auto End = After.find(';');
+    if (End == llvm::StringRef::npos)
+      return false;
+    llvm::StringRef Content = After.substr(0, End);
+    if (Content.consume_front("#")) {
+      if (Content.consume_front("x") || Content.consume_front("X"))
+        return llvm::all_of(Content, llvm::isHexDigit);
+      return llvm::all_of(Content, llvm::isDigit);
+    }
+    return llvm::all_of(Content, llvm::isAlpha);
+  }
+  case '.': // Numbered list indicator. Escape 12. -> 12\. at start of line.
+  case ')':
+    return StartsLine && !Before.empty() &&
+           llvm::all_of(Before, llvm::isDigit) && After.startswith(" ");
+  default:
+    return false;
+  }
+}
+
 /// Escape a markdown text block. Ensures the punctuation will not introduce
 /// any of the markdown constructs.
-std::string renderText(llvm::StringRef Input) {
-  // Escaping ASCII punctuation ensures we can't start a markdown construct.
-  constexpr llvm::StringLiteral Punctuation =
-      R"txt(!"#$%&'()*+,-./:;<=>?@[\]^_`{|}~)txt";
-
+std::string renderText(llvm::StringRef Input, bool StartsLine) {
   std::string R;
-  for (size_t From = 0; From < Input.size();) {
-    size_t Next = Input.find_first_of(Punctuation, From);
-    R += Input.substr(From, Next - From);
-    if (Next == llvm::StringRef::npos)
-      break;
-    R += "\\";
-    R += Input[Next];
-
-    From = Next + 1;
+  for (unsigned I = 0; I < Input.size(); ++I) {
+    if (needsLeadingEscape(Input[I], Input.substr(0, I), Input.substr(I + 1),
+                           StartsLine))
+      R.push_back('\\');
+    R.push_back(Input[I]);
   }
   return R;
 }
@@ -236,7 +357,7 @@ void Paragraph::renderMarkdown(llvm::raw_ostream &OS) const {
     OS << Sep;
     switch (C.Kind) {
     case Chunk::PlainText:
-      OS << renderText(C.Contents);
+      OS << renderText(C.Contents, Sep.empty());
       break;
     case Chunk::InlineCode:
       OS << renderInlineBlock(C.Contents);
diff --git a/clang-tools-extra/clangd/FormattedString.h b/clang-tools-extra/clangd/FormattedString.h
index effd03725925b..fe864ba575681 100644
--- a/clang-tools-extra/clangd/FormattedString.h
+++ b/clang-tools-extra/clangd/FormattedString.h
@@ -95,6 +95,8 @@ class Document {
   BulletList &addBulletList();
 
   /// Doesn't contain any trailing newlines.
+  /// We try to make the markdown human-readable, e.g. avoid extra escaping.
+  /// At least one client (coc.nvim) displays the markdown verbatim!
   std::string asMarkdown() const;
   /// Doesn't contain any trailing newlines.
   std::string asPlainText() const;
diff --git a/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp b/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp
index 6489aa05f8440..d3fa1aa8c0a74 100644
--- a/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp
@@ -17,25 +17,96 @@ namespace clangd {
 namespace markup {
 namespace {
 
-TEST(Render, Escaping) {
-  // Check some ASCII punctuation
-  Paragraph P;
-  P.appendText("*!`");
-  EXPECT_EQ(P.asMarkdown(), "\\*\\!\\`");
+std::string escape(llvm::StringRef Text) {
+  return Paragraph().appendText(Text.str()).asMarkdown();
+}
+
+MATCHER_P(escaped, C, "") {
+  return testing::ExplainMatchResult(::testing::HasSubstr(std::string{'\\', C}),
+                                     arg, result_listener);
+}
 
+MATCHER(escapedNone, "") {
+  return testing::ExplainMatchResult(::testing::Not(::testing::HasSubstr("\\")),
+                                     arg, result_listener);
+}
+
+TEST(Render, Escaping) {
   // Check all ASCII punctuation.
-  P = Paragraph();
   std::string Punctuation = R"txt(!"#$%&'()*+,-./:;<=>?@[\]^_`{|}~)txt";
-  // Same text, with each character escaped.
-  std::string EscapedPunctuation;
-  EscapedPunctuation.reserve(2 * Punctuation.size());
-  for (char C : Punctuation)
-    EscapedPunctuation += std::string("\\") + C;
-  P.appendText(Punctuation);
-  EXPECT_EQ(P.asMarkdown(), EscapedPunctuation);
+  std::string EscapedPunc = R"txt(!"#$%&'()\*+,-./:;<=>?@[\\]^\_\`{|}~)txt";
+  EXPECT_EQ(escape(Punctuation), EscapedPunc);
+
+  // Inline code
+  EXPECT_EQ(escape("`foo`"), R"(\`foo\`)");
+  EXPECT_EQ(escape("`foo"), R"(\`foo)");
+  EXPECT_EQ(escape("foo`"), R"(foo\`)");
+  EXPECT_EQ(escape("``foo``"), R"(\`\`foo\`\`)");
+  // Code blocks
+  EXPECT_EQ(escape("```"), R"(\`\`\`)"); // This could also be inline code!
+  EXPECT_EQ(escape("~~~"), R"(\~~~)");
+
+  // Rulers and headings
+  EXPECT_THAT(escape("## Heading"), escaped('#'));
+  EXPECT_THAT(escape("Foo # bar"), escapedNone());
+  EXPECT_EQ(escape("---"), R"(\---)");
+  EXPECT_EQ(escape("-"), R"(\-)");
+  EXPECT_EQ(escape("==="), R"(\===)");
+  EXPECT_EQ(escape("="), R"(\=)");
+  EXPECT_EQ(escape("***"), R"(\*\*\*)"); // \** could start emphasis!
+
+  // HTML tags.
+  EXPECT_THAT(escape("<pre"), escaped('<'));
+  EXPECT_THAT(escape("< pre"), escapedNone());
+  EXPECT_THAT(escape("if a<b then"), escaped('<'));
+  EXPECT_THAT(escape("if a<b then c."), escapedNone());
+  EXPECT_THAT(escape("if a<b then c='foo'."), escaped('<'));
+  EXPECT_THAT(escape("std::vector<T>"), escaped('<'));
+  EXPECT_THAT(escape("std::vector<std::string>"), escaped('<'));
+  EXPECT_THAT(escape("std::map<int, int>"), escapedNone());
+  // Autolinks
+  EXPECT_THAT(escape("Email <foo@bar.com>"), escapedNone());
+  EXPECT_THAT(escape("Website <http://foo.bar>"), escapedNone());
+
+  // Bullet lists.
+  EXPECT_THAT(escape("- foo"), escaped('-'));
+  EXPECT_THAT(escape("* foo"), escaped('*'));
+  EXPECT_THAT(escape("+ foo"), escaped('+'));
+  EXPECT_THAT(escape("+"), escaped('+'));
+  EXPECT_THAT(escape("a + foo"), escapedNone());
+  EXPECT_THAT(escape("a+ foo"), escapedNone());
+  EXPECT_THAT(escape("1. foo"), escaped('.'));
+  EXPECT_THAT(escape("a. foo"), escapedNone());
+
+  // Emphasis.
+  EXPECT_EQ(escape("*foo*"), R"(\*foo\*)");
+  EXPECT_EQ(escape("**foo**"), R"(\*\*foo\*\*)");
+  EXPECT_THAT(escape("*foo"), escaped('*'));
+  EXPECT_THAT(escape("foo *"), escapedNone());
+  EXPECT_THAT(escape("foo * bar"), escapedNone());
+  EXPECT_THAT(escape("foo_bar"), escapedNone());
+  EXPECT_THAT(escape("foo _bar"), escaped('_'));
+  EXPECT_THAT(escape("foo_ bar"), escaped('_'));
+  EXPECT_THAT(escape("foo _ bar"), escapedNone());
+
+  // HTML entities.
+  EXPECT_THAT(escape("fish &chips;"), escaped('&'));
+  EXPECT_THAT(escape("fish & chips;"), escapedNone());
+  EXPECT_THAT(escape("fish &chips"), escapedNone());
+  EXPECT_THAT(escape("foo &#42; bar"), escaped('&'));
+  EXPECT_THAT(escape("foo &#xaf; bar"), escaped('&'));
+  EXPECT_THAT(escape("foo &?; bar"), escapedNone());
+
+  // Links.
+  EXPECT_THAT(escape("[foo](bar)"), escaped(']'));
+  EXPECT_THAT(escape("[foo]: bar"), escaped(']'));
+  // No need to escape these, as the target never exists.
+  EXPECT_THAT(escape("[foo][]"), escapedNone());
+  EXPECT_THAT(escape("[foo][bar]"), escapedNone());
+  EXPECT_THAT(escape("[foo]"), escapedNone());
 
   // In code blocks we don't need to escape ASCII punctuation.
-  P = Paragraph();
+  Paragraph P = Paragraph();
   P.appendCode("* foo !+ bar * baz");
   EXPECT_EQ(P.asMarkdown(), "`* foo !+ bar * baz`");
 
diff --git a/clang-tools-extra/clangd/unittests/HoverTests.cpp b/clang-tools-extra/clangd/unittests/HoverTests.cpp
index 51f8eac1bfb4d..c243346a73f6b 100644
--- a/clang-tools-extra/clangd/unittests/HoverTests.cpp
+++ b/clang-tools-extra/clangd/unittests/HoverTests.cpp
@@ -1905,7 +1905,7 @@ TEST(Hover, PresentRulers) {
   llvm::StringRef ExpectedMarkdown = R"md(### variable `foo`  
 
 ---
-Value \= `val`  
+Value = `val`  
 
 ---
 ```cpp
diff --git a/clang-tools-extra/clangd/unittests/SelectionTests.cpp b/clang-tools-extra/clangd/unittests/SelectionTests.cpp
index 7316dea42bd2b..e1c873a22b13a 100644
--- a/clang-tools-extra/clangd/unittests/SelectionTests.cpp
+++ b/clang-tools-extra/clangd/unittests/SelectionTests.cpp
@@ -380,6 +380,14 @@ TEST(SelectionTest, CommonAncestor) {
       {"struct foo { [[^~foo()]]; };", "CXXDestructorDecl"},
       // FIXME: The following to should be class itself instead.
       {"struct foo { [[fo^o(){}]] };", "CXXConstructorDecl"},
+
+      {R"cpp(
+        struct S1 { void f(); };
+        struct S2 { S1 * operator->(); };
+        void test(S2 s2) {
+          s2[[-^>]]f();
+        }
+      )cpp", "DeclRefExpr"} // DeclRefExpr to the "operator->" method.
   };
   for (const Case &C : Cases) {
     Annotations Test(C.Code);
diff --git a/clang-tools-extra/clangd/unittests/XRefsTests.cpp b/clang-tools-extra/clangd/unittests/XRefsTests.cpp
index d387fd219a08b..32a89df424e41 100644
--- a/clang-tools-extra/clangd/unittests/XRefsTests.cpp
+++ b/clang-tools-extra/clangd/unittests/XRefsTests.cpp
@@ -452,6 +452,14 @@ TEST(LocateSymbol, All) {
         }
       )cpp",
 
+      R"cpp(
+        struct S1 { void f(); };
+        struct S2 { S1 * $decl[[operator]]->(); };
+        void test(S2 s2) {
+          s2-^>f();
+        }
+      )cpp",
+
       R"cpp(// Declaration of explicit template specialization
         template <typename T>
         struct $decl[[Foo]] {};
@@ -521,6 +529,14 @@ TEST(LocateSymbol, All) {
         void test(unique_ptr<S<T>>& V) {
           V->fo^o();
         }
+      )cpp",
+
+      R"cpp(// Heuristic resolution of dependent enumerator
+        template <typename T>
+        struct Foo {
+          enum class E { [[A]], B };
+          E e = E::A^;
+        };
       )cpp"};
   for (const char *Test : Tests) {
     Annotations T(Test);
diff --git a/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-special-member-functions.rst b/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-special-member-functions.rst
index 28a5e8e5a0df0..4ced6c1bc563b 100644
--- a/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-special-member-functions.rst
+++ b/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-special-member-functions.rst
@@ -46,4 +46,19 @@ Options
        A(const A&);
        A& operator=(const A&);
        ~A();
-     }
+     };
+
+.. option:: AllowMissingMoveFunctionsWhenCopyIsDeleted
+
+   When set to `1` (default is `0`), this check doesn't flag classes which define deleted copy
+   operations but don't define move operations. This flags is related to Google C++ Style Guide
+   https://google.github.io/styleguide/cppguide.html#Copyable_Movable_Types. With this option enabled, the 
+   following class won't be flagged:
+   
+   .. code-block:: c++
+   
+     struct A {
+       A(const A&) = delete;
+       A& operator=(const A&) = delete;
+       ~A();
+     };
diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-special-member-functions-allow-missing-move-when-copy-is-deleted.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-special-member-functions-allow-missing-move-when-copy-is-deleted.cpp
new file mode 100644
index 0000000000000..216a49a44eff6
--- /dev/null
+++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-special-member-functions-allow-missing-move-when-copy-is-deleted.cpp
@@ -0,0 +1,49 @@
+// RUN: %check_clang_tidy %s cppcoreguidelines-special-member-functions %t -- -config="{CheckOptions: [{key: cppcoreguidelines-special-member-functions.AllowMissingMoveFunctionsWhenCopyIsDeleted, value: 1}]}" --
+
+class DefinesEverything {
+  DefinesEverything(const DefinesEverything &);
+  DefinesEverything(DefinesEverything &&);
+  DefinesEverything &operator=(const DefinesEverything &);
+  DefinesEverything &operator=(DefinesEverything &&);
+  ~DefinesEverything();
+};
+
+class DefinesNothing {
+};
+
+class DeletedCopyCtorAndOperator {
+  ~DeletedCopyCtorAndOperator() = default;
+  DeletedCopyCtorAndOperator(const DeletedCopyCtorAndOperator &) = delete;
+  DeletedCopyCtorAndOperator &operator=(const DeletedCopyCtorAndOperator &) = delete;
+};
+
+// CHECK-MESSAGES: [[@LINE+1]]:7: warning: class 'DefaultedCopyCtorAndOperator' defines a default destructor, a copy constructor and a copy assignment operator but does not define a move constructor or a move assignment operator [cppcoreguidelines-special-member-functions]
+class DefaultedCopyCtorAndOperator {
+  ~DefaultedCopyCtorAndOperator() = default;
+  DefaultedCopyCtorAndOperator(const DefaultedCopyCtorAndOperator &) = default;
+  DefaultedCopyCtorAndOperator &operator=(const DefaultedCopyCtorAndOperator &) = default;
+};
+
+// CHECK-MESSAGES: [[@LINE+1]]:7: warning: class 'DefinedCopyCtorAndOperator' defines a default destructor, a copy constructor and a copy assignment operator but does not define a move constructor or a move assignment operator [cppcoreguidelines-special-member-functions]
+class DefinedCopyCtorAndOperator {
+  ~DefinedCopyCtorAndOperator() = default;
+  DefinedCopyCtorAndOperator(const DefinedCopyCtorAndOperator &);
+  DefinedCopyCtorAndOperator &operator=(const DefinedCopyCtorAndOperator &);
+};
+
+// CHECK-MESSAGES: [[@LINE+1]]:7: warning: class 'MissingCopyCtor' defines a default destructor and a copy assignment operator but does not define a copy constructor, a move constructor or a move assignment operator [cppcoreguidelines-special-member-functions]
+class MissingCopyCtor {
+  ~MissingCopyCtor() = default;
+  MissingCopyCtor &operator=(const MissingCopyCtor &) = delete;
+};
+
+// CHECK-MESSAGES: [[@LINE+1]]:7:  warning: class 'MissingCopyOperator' defines a default destructor and a copy constructor but does not define a copy assignment operator, a move constructor or a move assignment operator [cppcoreguidelines-special-member-functions]
+class MissingCopyOperator {
+  ~MissingCopyOperator() = default;
+  MissingCopyOperator(const MissingCopyOperator &) = delete;
+};
+
+// CHECK-MESSAGES: [[@LINE+1]]:7:  warning: class 'MissingAll' defines a default destructor but does not define a copy constructor, a copy assignment operator, a move constructor or a move assignment operator [cppcoreguidelines-special-member-functions]
+class MissingAll {
+  ~MissingAll() = default;
+};
diff --git a/clang/cmake/caches/Fuchsia-stage2.cmake b/clang/cmake/caches/Fuchsia-stage2.cmake
index b338f1b8a08f6..7733e55ab229c 100644
--- a/clang/cmake/caches/Fuchsia-stage2.cmake
+++ b/clang/cmake/caches/Fuchsia-stage2.cmake
@@ -195,6 +195,7 @@ set(LLVM_TOOLCHAIN_TOOLS
   llvm-cxxfilt
   llvm-dwarfdump
   llvm-dwp
+  llvm-gsymutil
   llvm-lib
   llvm-nm
   llvm-objcopy
diff --git a/clang/docs/HowToSetupToolingForLLVM.rst b/clang/docs/HowToSetupToolingForLLVM.rst
index 58f10cfeffc12..cbe15abaab3b4 100644
--- a/clang/docs/HowToSetupToolingForLLVM.rst
+++ b/clang/docs/HowToSetupToolingForLLVM.rst
@@ -37,7 +37,7 @@ make a build directory and run CMake from it:
 If you want to use clang instead of GCC, you can add
 ``-DCMAKE_C_COMPILER=/path/to/clang -DCMAKE_CXX_COMPILER=/path/to/clang++``.
 You can also use ``ccmake``, which provides a curses interface to configure
-CMake variables for lazy people.
+CMake variables.
 
 As a result, the new ``compile_commands.json`` file should appear in the
 current directory. You should link it to the LLVM source tree so that
diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index 75ab911d24597..d74edb8a8adb8 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -1275,6 +1275,12 @@ class ASTContext : public RefCountedBase<ASTContext> {
   /// Returns a vla type where known sizes are replaced with [*].
   QualType getVariableArrayDecayedType(QualType Ty) const;
 
+  /// Return the unique reference to a scalable vector type of the specified
+  /// element type and scalable number of elements.
+  ///
+  /// \pre \p EltTy must be a built-in type.
+  QualType getScalableVectorType(QualType EltTy, unsigned NumElts) const;
+
   /// Return the unique reference to a vector type of the specified
   /// element type and size.
   ///
diff --git a/clang/include/clang/AST/ComputeDependence.h b/clang/include/clang/AST/ComputeDependence.h
new file mode 100644
index 0000000000000..593ff3a6eb163
--- /dev/null
+++ b/clang/include/clang/AST/ComputeDependence.h
@@ -0,0 +1,182 @@
+//===--- ComputeDependence.h -------------------------------------- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//  Calculate various template dependency flags for the AST.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_AST_COMPUTE_DEPENDENCE_H
+#define LLVM_CLANG_AST_COMPUTE_DEPENDENCE_H
+
+#include "clang/AST/DependenceFlags.h"
+#include "clang/Basic/ExceptionSpecificationType.h"
+#include "llvm/ADT/ArrayRef.h"
+
+namespace clang {
+
+class ASTContext;
+
+class Expr;
+class FullExpr;
+class OpaqueValueExpr;
+class ParenExpr;
+class UnaryOperator;
+class UnaryExprOrTypeTraitExpr;
+class ArraySubscriptExpr;
+class CompoundLiteralExpr;
+class CastExpr;
+class BinaryOperator;
+class ConditionalOperator;
+class BinaryConditionalOperator;
+class StmtExpr;
+class ConvertVectorExpr;
+class VAArgExpr;
+class ChooseExpr;
+class NoInitExpr;
+class ArrayInitLoopExpr;
+class ImplicitValueInitExpr;
+class InitListExpr;
+class ExtVectorElementExpr;
+class BlockExpr;
+class AsTypeExpr;
+class DeclRefExpr;
+class CXXRewrittenBinaryOperator;
+class CXXStdInitializerListExpr;
+class CXXTypeidExpr;
+class MSPropertyRefExpr;
+class MSPropertySubscriptExpr;
+class CXXUuidofExpr;
+class CXXThisExpr;
+class CXXThrowExpr;
+class CXXBindTemporaryExpr;
+class CXXScalarValueInitExpr;
+class CXXDeleteExpr;
+class ArrayTypeTraitExpr;
+class ExpressionTraitExpr;
+class CXXNoexceptExpr;
+class SubstNonTypeTemplateParmExpr;
+class CoroutineSuspendExpr;
+class DependentCoawaitExpr;
+class CXXNewExpr;
+class CXXPseudoDestructorExpr;
+class OverloadExpr;
+class DependentScopeDeclRefExpr;
+class CXXConstructExpr;
+class LambdaExpr;
+class CXXUnresolvedConstructExpr;
+class CXXDependentScopeMemberExpr;
+class MaterializeTemporaryExpr;
+class TypeTraitExpr;
+class ConceptSpecializationExpr;
+class PredefinedExpr;
+class CallExpr;
+class OffsetOfExpr;
+class MemberExpr;
+class ShuffleVectorExpr;
+class GenericSelectionExpr;
+class DesignatedInitExpr;
+class ParenListExpr;
+class PseudoObjectExpr;
+class AtomicExpr;
+class OMPArraySectionExpr;
+class ObjCArrayLiteral;
+class ObjCDictionaryLiteral;
+class ObjCBoxedExpr;
+class ObjCEncodeExpr;
+class ObjCIvarRefExpr;
+class ObjCPropertyRefExpr;
+class ObjCSubscriptRefExpr;
+class ObjCIsaExpr;
+class ObjCIndirectCopyRestoreExpr;
+class ObjCMessageExpr;
+
+// The following functions are called from constructors of `Expr`, so they
+// should not access anything beyond basic
+ExprDependence computeDependence(FullExpr *E);
+ExprDependence computeDependence(OpaqueValueExpr *E);
+ExprDependence computeDependence(ParenExpr *E);
+ExprDependence computeDependence(UnaryOperator *E);
+ExprDependence computeDependence(UnaryExprOrTypeTraitExpr *E);
+ExprDependence computeDependence(ArraySubscriptExpr *E);
+ExprDependence computeDependence(CompoundLiteralExpr *E);
+ExprDependence computeDependence(CastExpr *E);
+ExprDependence computeDependence(BinaryOperator *E);
+ExprDependence computeDependence(ConditionalOperator *E);
+ExprDependence computeDependence(BinaryConditionalOperator *E);
+ExprDependence computeDependence(StmtExpr *E, unsigned TemplateDepth);
+ExprDependence computeDependence(ConvertVectorExpr *E);
+ExprDependence computeDependence(VAArgExpr *E);
+ExprDependence computeDependence(ChooseExpr *E);
+ExprDependence computeDependence(NoInitExpr *E);
+ExprDependence computeDependence(ArrayInitLoopExpr *E);
+ExprDependence computeDependence(ImplicitValueInitExpr *E);
+ExprDependence computeDependence(InitListExpr *E);
+ExprDependence computeDependence(ExtVectorElementExpr *E);
+ExprDependence computeDependence(BlockExpr *E);
+ExprDependence computeDependence(AsTypeExpr *E);
+ExprDependence computeDependence(DeclRefExpr *E, const ASTContext &Ctx);
+ExprDependence computeDependence(CXXRewrittenBinaryOperator *E);
+ExprDependence computeDependence(CXXStdInitializerListExpr *E);
+ExprDependence computeDependence(CXXTypeidExpr *E);
+ExprDependence computeDependence(MSPropertyRefExpr *E);
+ExprDependence computeDependence(MSPropertySubscriptExpr *E);
+ExprDependence computeDependence(CXXUuidofExpr *E);
+ExprDependence computeDependence(CXXThisExpr *E);
+ExprDependence computeDependence(CXXThrowExpr *E);
+ExprDependence computeDependence(CXXBindTemporaryExpr *E);
+ExprDependence computeDependence(CXXScalarValueInitExpr *E);
+ExprDependence computeDependence(CXXDeleteExpr *E);
+ExprDependence computeDependence(ArrayTypeTraitExpr *E);
+ExprDependence computeDependence(ExpressionTraitExpr *E);
+ExprDependence computeDependence(CXXNoexceptExpr *E, CanThrowResult CT);
+ExprDependence computeDependence(SubstNonTypeTemplateParmExpr *E);
+ExprDependence computeDependence(CoroutineSuspendExpr *E);
+ExprDependence computeDependence(DependentCoawaitExpr *E);
+ExprDependence computeDependence(CXXNewExpr *E);
+ExprDependence computeDependence(CXXPseudoDestructorExpr *E);
+ExprDependence computeDependence(OverloadExpr *E, bool KnownDependent,
+                                 bool KnownInstantiationDependent,
+                                 bool KnownContainsUnexpandedParameterPack);
+ExprDependence computeDependence(DependentScopeDeclRefExpr *E);
+ExprDependence computeDependence(CXXConstructExpr *E);
+ExprDependence computeDependence(LambdaExpr *E,
+                                 bool ContainsUnexpandedParameterPack);
+ExprDependence computeDependence(CXXUnresolvedConstructExpr *E);
+ExprDependence computeDependence(CXXDependentScopeMemberExpr *E);
+ExprDependence computeDependence(MaterializeTemporaryExpr *E);
+ExprDependence computeDependence(TypeTraitExpr *E);
+ExprDependence computeDependence(ConceptSpecializationExpr *E,
+                                 bool ValueDependent);
+
+ExprDependence computeDependence(PredefinedExpr *E);
+ExprDependence computeDependence(CallExpr *E, llvm::ArrayRef<Expr *> PreArgs);
+ExprDependence computeDependence(OffsetOfExpr *E);
+ExprDependence computeDependence(MemberExpr *E);
+ExprDependence computeDependence(ShuffleVectorExpr *E);
+ExprDependence computeDependence(GenericSelectionExpr *E,
+                                 bool ContainsUnexpandedPack);
+ExprDependence computeDependence(DesignatedInitExpr *E);
+ExprDependence computeDependence(ParenListExpr *E);
+ExprDependence computeDependence(PseudoObjectExpr *E);
+ExprDependence computeDependence(AtomicExpr *E);
+
+ExprDependence computeDependence(OMPArraySectionExpr *E);
+
+ExprDependence computeDependence(ObjCArrayLiteral *E);
+ExprDependence computeDependence(ObjCDictionaryLiteral *E);
+ExprDependence computeDependence(ObjCBoxedExpr *E);
+ExprDependence computeDependence(ObjCEncodeExpr *E);
+ExprDependence computeDependence(ObjCIvarRefExpr *E);
+ExprDependence computeDependence(ObjCPropertyRefExpr *E);
+ExprDependence computeDependence(ObjCSubscriptRefExpr *E);
+ExprDependence computeDependence(ObjCIsaExpr *E);
+ExprDependence computeDependence(ObjCIndirectCopyRestoreExpr *E);
+ExprDependence computeDependence(ObjCMessageExpr *E);
+
+} // namespace clang
+#endif
diff --git a/clang/include/clang/AST/DeclCXX.h b/clang/include/clang/AST/DeclCXX.h
index 987738f73676b..60d99f1a487f8 100644
--- a/clang/include/clang/AST/DeclCXX.h
+++ b/clang/include/clang/AST/DeclCXX.h
@@ -2415,17 +2415,6 @@ class CXXConstructorDecl final
                      : ExplicitSpecKind::ResolvedFalse);
   }
 
-  void setExplicitSpecifier(ExplicitSpecifier ES) {
-    assert((!ES.getExpr() ||
-            CXXConstructorDeclBits.HasTrailingExplicitSpecifier) &&
-           "cannot set this explicit specifier. no trail-allocated space for "
-           "explicit");
-    if (ES.getExpr())
-      *getCanonicalDecl()->getTrailingObjects<ExplicitSpecifier>() = ES;
-    else
-      CXXConstructorDeclBits.IsSimpleExplicit = ES.isExplicit();
-  }
-
   enum TraillingAllocKind {
     TAKInheritsConstructor = 1,
     TAKHasTailExplicit = 1 << 1,
@@ -2451,6 +2440,17 @@ class CXXConstructorDecl final
          InheritedConstructor Inherited = InheritedConstructor(),
          Expr *TrailingRequiresClause = nullptr);
 
+  void setExplicitSpecifier(ExplicitSpecifier ES) {
+    assert((!ES.getExpr() ||
+            CXXConstructorDeclBits.HasTrailingExplicitSpecifier) &&
+           "cannot set this explicit specifier. no trail-allocated space for "
+           "explicit");
+    if (ES.getExpr())
+      *getCanonicalDecl()->getTrailingObjects<ExplicitSpecifier>() = ES;
+    else
+      CXXConstructorDeclBits.IsSimpleExplicit = ES.isExplicit();
+  }
+
   ExplicitSpecifier getExplicitSpecifier() {
     return getCanonicalDecl()->getExplicitSpecifierInternal();
   }
diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h
index def1ab18706c1..e9c4879b41e89 100755
--- a/clang/include/clang/AST/DeclTemplate.h
+++ b/clang/include/clang/AST/DeclTemplate.h
@@ -1927,6 +1927,10 @@ class ClassTemplateSpecializationDecl
         getTemplateSpecializationKind());
   }
 
+  void setSpecializedTemplate(ClassTemplateDecl *Specialized) {
+    SpecializedTemplate = Specialized;
+  }
+
   void setSpecializationKind(TemplateSpecializationKind TSK) {
     SpecializationKind = TSK;
   }
diff --git a/clang/include/clang/AST/DependencyFlags.h b/clang/include/clang/AST/DependenceFlags.h
similarity index 91%
rename from clang/include/clang/AST/DependencyFlags.h
rename to clang/include/clang/AST/DependenceFlags.h
index c27016aa9aec4..21daf0a203ac8 100644
--- a/clang/include/clang/AST/DependencyFlags.h
+++ b/clang/include/clang/AST/DependenceFlags.h
@@ -1,12 +1,12 @@
-//===--- DependencyFlags.h ------------------------------------------------===//
+//===--- DependenceFlags.h ------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
-#ifndef LLVM_CLANG_AST_DEPENDENCYFLAGS_H
-#define LLVM_CLANG_AST_DEPENDENCYFLAGS_H
+#ifndef LLVM_CLANG_AST_DEPENDENCEFLAGS_H
+#define LLVM_CLANG_AST_DEPENDENCEFLAGS_H
 
 #include "clang/Basic/BitmaskEnum.h"
 #include "llvm/ADT/BitmaskEnum.h"
@@ -23,6 +23,7 @@ struct ExprDependenceScope {
     None = 0,
     All = 15,
 
+    TypeValue = Type | Value,
     TypeInstantiation = Type | Instantiation,
     ValueInstantiation = Value | Instantiation,
     TypeValueInstantiation = Type | Value | Instantiation,
@@ -94,6 +95,12 @@ inline ExprDependence toExprDependence(TypeDependence TD) {
   return toExprDependence(static_cast<TemplateArgumentDependence>(
       TD & ~TypeDependence::VariablyModified));
 }
+inline ExprDependence toExprDependence(NestedNameSpecifierDependence NSD) {
+  // This hack works because TypeDependence and TemplateArgumentDependence
+  // share the same bit representation.
+  return toExprDependence(static_cast<TemplateArgumentDependence>(NSD)) &
+         ~ExprDependence::TypeValue;
+}
 inline ExprDependence turnTypeToValueDependence(ExprDependence D) {
   // Type-dependent expressions are always be value-dependent, so we simply drop
   // type dependency.
diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h
index eaea25a446ffe..4a1d2f91b8673 100644
--- a/clang/include/clang/AST/Expr.h
+++ b/clang/include/clang/AST/Expr.h
@@ -15,9 +15,10 @@
 
 #include "clang/AST/APValue.h"
 #include "clang/AST/ASTVector.h"
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclAccessPair.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/OperationKinds.h"
 #include "clang/AST/Stmt.h"
 #include "clang/AST/TemplateBase.h"
@@ -117,21 +118,9 @@ class Expr : public ValueStmt {
   Expr &operator=(Expr&&) = delete;
 
 protected:
-  Expr(StmtClass SC, QualType T, ExprValueKind VK, ExprObjectKind OK,
-       bool TD, bool VD, bool ID, bool ContainsUnexpandedParameterPack)
-    : ValueStmt(SC)
-  {
-    auto D = ExprDependence::None;
-    if (TD)
-      D |= ExprDependence::Type;
-    if (VD)
-      D |= ExprDependence::Value;
-    if (ID)
-      D |= ExprDependence::Instantiation;
-    if (ContainsUnexpandedParameterPack)
-      D |= ExprDependence::UnexpandedPack;
-
-    ExprBits.Dependent = static_cast<unsigned>(D);
+  Expr(StmtClass SC, QualType T, ExprValueKind VK, ExprObjectKind OK)
+      : ValueStmt(SC) {
+    ExprBits.Dependent = 0;
     ExprBits.ValueKind = VK;
     ExprBits.ObjectKind = OK;
     assert(ExprBits.ObjectKind == OK && "truncated kind");
@@ -160,6 +149,8 @@ class Expr : public ValueStmt {
     return static_cast<ExprDependence>(ExprBits.Dependent);
   }
 
+  /// Each concrete expr subclass is expected to compute its dependence and call
+  /// this in the constructor.
   void setDependence(ExprDependence Deps) {
     ExprBits.Dependent = static_cast<unsigned>(Deps);
   }
@@ -958,11 +949,11 @@ class FullExpr : public Expr {
  Stmt *SubExpr;
 
  FullExpr(StmtClass SC, Expr *subexpr)
-    : Expr(SC, subexpr->getType(),
-           subexpr->getValueKind(), subexpr->getObjectKind(),
-           subexpr->isTypeDependent(), subexpr->isValueDependent(),
-           subexpr->isInstantiationDependent(),
-           subexpr->containsUnexpandedParameterPack()), SubExpr(subexpr) {}
+     : Expr(SC, subexpr->getType(), subexpr->getValueKind(),
+            subexpr->getObjectKind()),
+       SubExpr(subexpr) {
+   setDependence(computeDependence(this));
+ }
   FullExpr(StmtClass SC, EmptyShell Empty)
     : Expr(SC, Empty) {}
 public:
@@ -1088,19 +1079,11 @@ class OpaqueValueExpr : public Expr {
 
 public:
   OpaqueValueExpr(SourceLocation Loc, QualType T, ExprValueKind VK,
-                  ExprObjectKind OK = OK_Ordinary,
-                  Expr *SourceExpr = nullptr)
-    : Expr(OpaqueValueExprClass, T, VK, OK,
-           T->isDependentType() ||
-           (SourceExpr && SourceExpr->isTypeDependent()),
-           T->isDependentType() ||
-           (SourceExpr && SourceExpr->isValueDependent()),
-           T->isInstantiationDependentType() ||
-           (SourceExpr && SourceExpr->isInstantiationDependent()),
-           false),
-      SourceExpr(SourceExpr) {
+                  ExprObjectKind OK = OK_Ordinary, Expr *SourceExpr = nullptr)
+      : Expr(OpaqueValueExprClass, T, VK, OK), SourceExpr(SourceExpr) {
     setIsUnique(false);
     OpaqueValueExprBits.Loc = Loc;
+    setDependence(computeDependence(this));
   }
 
   /// Given an expression which invokes a copy constructor --- i.e.  a
@@ -1550,10 +1533,10 @@ class CharacterLiteral : public Expr {
   // type should be IntTy
   CharacterLiteral(unsigned value, CharacterKind kind, QualType type,
                    SourceLocation l)
-    : Expr(CharacterLiteralClass, type, VK_RValue, OK_Ordinary, false, false,
-           false, false),
-      Value(value), Loc(l) {
+      : Expr(CharacterLiteralClass, type, VK_RValue, OK_Ordinary), Value(value),
+        Loc(l) {
     CharacterLiteralBits.Kind = kind;
+    setDependence(ExprDependence::None);
   }
 
   /// Construct an empty character literal.
@@ -1669,9 +1652,9 @@ class ImaginaryLiteral : public Expr {
   Stmt *Val;
 public:
   ImaginaryLiteral(Expr *val, QualType Ty)
-    : Expr(ImaginaryLiteralClass, Ty, VK_RValue, OK_Ordinary, false, false,
-           false, false),
-      Val(val) {}
+      : Expr(ImaginaryLiteralClass, Ty, VK_RValue, OK_Ordinary), Val(val) {
+    setDependence(ExprDependence::None);
+  }
 
   /// Build an empty imaginary literal.
   explicit ImaginaryLiteral(EmptyShell Empty)
@@ -2063,12 +2046,11 @@ class ParenExpr : public Expr {
   Stmt *Val;
 public:
   ParenExpr(SourceLocation l, SourceLocation r, Expr *val)
-    : Expr(ParenExprClass, val->getType(),
-           val->getValueKind(), val->getObjectKind(),
-           val->isTypeDependent(), val->isValueDependent(),
-           val->isInstantiationDependent(),
-           val->containsUnexpandedParameterPack()),
-      L(l), R(r), Val(val) {}
+      : Expr(ParenExprClass, val->getType(), val->getValueKind(),
+             val->getObjectKind()),
+        L(l), R(r), Val(val) {
+    setDependence(computeDependence(this));
+  }
 
   /// Construct an empty parenthesized expression.
   explicit ParenExpr(EmptyShell Empty)
@@ -2118,16 +2100,11 @@ class UnaryOperator : public Expr {
 
   UnaryOperator(Expr *input, Opcode opc, QualType type, ExprValueKind VK,
                 ExprObjectKind OK, SourceLocation l, bool CanOverflow)
-      : Expr(UnaryOperatorClass, type, VK, OK,
-             input->isTypeDependent() || type->isDependentType(),
-             input->isValueDependent(),
-             (input->isInstantiationDependent() ||
-              type->isInstantiationDependentType()),
-             input->containsUnexpandedParameterPack()),
-        Val(input) {
+      : Expr(UnaryOperatorClass, type, VK, OK), Val(input) {
     UnaryOperatorBits.Opc = opc;
     UnaryOperatorBits.CanOverflow = CanOverflow;
     UnaryOperatorBits.Loc = l;
+    setDependence(computeDependence(this));
   }
 
   /// Build an empty unary operator.
@@ -2446,17 +2423,13 @@ class UnaryExprOrTypeTraitExpr : public Expr {
 public:
   UnaryExprOrTypeTraitExpr(UnaryExprOrTypeTrait ExprKind, TypeSourceInfo *TInfo,
                            QualType resultType, SourceLocation op,
-                           SourceLocation rp) :
-      Expr(UnaryExprOrTypeTraitExprClass, resultType, VK_RValue, OK_Ordinary,
-           false, // Never type-dependent (C++ [temp.dep.expr]p3).
-           // Value-dependent if the argument is type-dependent.
-           TInfo->getType()->isDependentType(),
-           TInfo->getType()->isInstantiationDependentType(),
-           TInfo->getType()->containsUnexpandedParameterPack()),
-      OpLoc(op), RParenLoc(rp) {
+                           SourceLocation rp)
+      : Expr(UnaryExprOrTypeTraitExprClass, resultType, VK_RValue, OK_Ordinary),
+        OpLoc(op), RParenLoc(rp) {
     UnaryExprOrTypeTraitExprBits.Kind = ExprKind;
     UnaryExprOrTypeTraitExprBits.IsType = true;
     Argument.Ty = TInfo;
+    setDependence(computeDependence(this));
   }
 
   UnaryExprOrTypeTraitExpr(UnaryExprOrTypeTrait ExprKind, Expr *E,
@@ -2533,19 +2506,13 @@ class ArraySubscriptExpr : public Expr {
   bool lhsIsBase() const { return getRHS()->getType()->isIntegerType(); }
 
 public:
-  ArraySubscriptExpr(Expr *lhs, Expr *rhs, QualType t,
-                     ExprValueKind VK, ExprObjectKind OK,
-                     SourceLocation rbracketloc)
-  : Expr(ArraySubscriptExprClass, t, VK, OK,
-         lhs->isTypeDependent() || rhs->isTypeDependent(),
-         lhs->isValueDependent() || rhs->isValueDependent(),
-         (lhs->isInstantiationDependent() ||
-          rhs->isInstantiationDependent()),
-         (lhs->containsUnexpandedParameterPack() ||
-          rhs->containsUnexpandedParameterPack())) {
+  ArraySubscriptExpr(Expr *lhs, Expr *rhs, QualType t, ExprValueKind VK,
+                     ExprObjectKind OK, SourceLocation rbracketloc)
+      : Expr(ArraySubscriptExprClass, t, VK, OK) {
     SubExprs[LHS] = lhs;
     SubExprs[RHS] = rhs;
     ArraySubscriptExprBits.RBracketLoc = rbracketloc;
+    setDependence(computeDependence(this));
   }
 
   /// Create an empty array subscript expression.
@@ -3153,13 +3120,10 @@ class CompoundLiteralExpr : public Expr {
 public:
   CompoundLiteralExpr(SourceLocation lparenloc, TypeSourceInfo *tinfo,
                       QualType T, ExprValueKind VK, Expr *init, bool fileScope)
-    : Expr(CompoundLiteralExprClass, T, VK, OK_Ordinary,
-           tinfo->getType()->isDependentType(),
-           init->isValueDependent(),
-           (init->isInstantiationDependent() ||
-            tinfo->getType()->isInstantiationDependentType()),
-           init->containsUnexpandedParameterPack()),
-      LParenLoc(lparenloc), TInfoAndScope(tinfo, fileScope), Init(init) {}
+      : Expr(CompoundLiteralExprClass, T, VK, OK_Ordinary),
+        LParenLoc(lparenloc), TInfoAndScope(tinfo, fileScope), Init(init) {
+    setDependence(computeDependence(this));
+  }
 
   /// Construct an empty compound literal.
   explicit CompoundLiteralExpr(EmptyShell Empty)
@@ -3225,26 +3189,13 @@ class CastExpr : public Expr {
 protected:
   CastExpr(StmtClass SC, QualType ty, ExprValueKind VK, const CastKind kind,
            Expr *op, unsigned BasePathSize)
-      : Expr(SC, ty, VK, OK_Ordinary,
-             // Cast expressions are type-dependent if the type is
-             // dependent (C++ [temp.dep.expr]p3).
-             ty->isDependentType(),
-             // Cast expressions are value-dependent if the type is
-             // dependent or if the subexpression is value-dependent.
-             ty->isDependentType() || (op && op->isValueDependent()),
-             (ty->isInstantiationDependentType() ||
-              (op && op->isInstantiationDependent())),
-             // An implicit cast expression doesn't (lexically) contain an
-             // unexpanded pack, even if its target type does.
-             ((SC != ImplicitCastExprClass &&
-               ty->containsUnexpandedParameterPack()) ||
-              (op && op->containsUnexpandedParameterPack()))),
-        Op(op) {
+      : Expr(SC, ty, VK, OK_Ordinary), Op(op) {
     CastExprBits.Kind = kind;
     CastExprBits.PartOfExplicitCast = false;
     CastExprBits.BasePathSize = BasePathSize;
     assert((CastExprBits.BasePathSize == BasePathSize) &&
            "BasePathSize overflow!");
+    setDependence(computeDependence(this));
     assert(CastConsistency());
   }
 
@@ -3504,15 +3455,9 @@ class BinaryOperator : public Expr {
   typedef BinaryOperatorKind Opcode;
 
   BinaryOperator(Expr *lhs, Expr *rhs, Opcode opc, QualType ResTy,
-                 ExprValueKind VK, ExprObjectKind OK,
-                 SourceLocation opLoc, FPOptions FPFeatures)
-    : Expr(BinaryOperatorClass, ResTy, VK, OK,
-           lhs->isTypeDependent() || rhs->isTypeDependent(),
-           lhs->isValueDependent() || rhs->isValueDependent(),
-           (lhs->isInstantiationDependent() ||
-            rhs->isInstantiationDependent()),
-           (lhs->containsUnexpandedParameterPack() ||
-            rhs->containsUnexpandedParameterPack())) {
+                 ExprValueKind VK, ExprObjectKind OK, SourceLocation opLoc,
+                 FPOptions FPFeatures)
+      : Expr(BinaryOperatorClass, ResTy, VK, OK) {
     BinaryOperatorBits.Opc = opc;
     BinaryOperatorBits.FPFeatures = FPFeatures.getInt();
     BinaryOperatorBits.OpLoc = opLoc;
@@ -3520,6 +3465,7 @@ class BinaryOperator : public Expr {
     SubExprs[RHS] = rhs;
     assert(!isCompoundAssignmentOp() &&
            "Use CompoundAssignOperator for compound assignments");
+    setDependence(computeDependence(this));
   }
 
   /// Construct an empty binary operator.
@@ -3689,20 +3635,15 @@ class BinaryOperator : public Expr {
 
 protected:
   BinaryOperator(Expr *lhs, Expr *rhs, Opcode opc, QualType ResTy,
-                 ExprValueKind VK, ExprObjectKind OK,
-                 SourceLocation opLoc, FPOptions FPFeatures, bool dead2)
-    : Expr(CompoundAssignOperatorClass, ResTy, VK, OK,
-           lhs->isTypeDependent() || rhs->isTypeDependent(),
-           lhs->isValueDependent() || rhs->isValueDependent(),
-           (lhs->isInstantiationDependent() ||
-            rhs->isInstantiationDependent()),
-           (lhs->containsUnexpandedParameterPack() ||
-            rhs->containsUnexpandedParameterPack())) {
+                 ExprValueKind VK, ExprObjectKind OK, SourceLocation opLoc,
+                 FPOptions FPFeatures, bool dead2)
+      : Expr(CompoundAssignOperatorClass, ResTy, VK, OK) {
     BinaryOperatorBits.Opc = opc;
     BinaryOperatorBits.FPFeatures = FPFeatures.getInt();
     BinaryOperatorBits.OpLoc = opLoc;
     SubExprs[LHS] = lhs;
     SubExprs[RHS] = rhs;
+    setDependence(computeDependence(this));
   }
 
   BinaryOperator(StmtClass SC, EmptyShell Empty) : Expr(SC, Empty) {
@@ -3757,14 +3698,10 @@ class AbstractConditionalOperator : public Expr {
   friend class ASTStmtReader;
 
 protected:
-  AbstractConditionalOperator(StmtClass SC, QualType T,
-                              ExprValueKind VK, ExprObjectKind OK,
-                              bool TD, bool VD, bool ID,
-                              bool ContainsUnexpandedParameterPack,
-                              SourceLocation qloc,
+  AbstractConditionalOperator(StmtClass SC, QualType T, ExprValueKind VK,
+                              ExprObjectKind OK, SourceLocation qloc,
                               SourceLocation cloc)
-    : Expr(SC, T, VK, OK, TD, VD, ID, ContainsUnexpandedParameterPack),
-      QuestionLoc(qloc), ColonLoc(cloc) {}
+      : Expr(SC, T, VK, OK), QuestionLoc(qloc), ColonLoc(cloc) {}
 
   AbstractConditionalOperator(StmtClass SC, EmptyShell Empty)
     : Expr(SC, Empty) { }
@@ -3803,26 +3740,12 @@ class ConditionalOperator : public AbstractConditionalOperator {
   ConditionalOperator(Expr *cond, SourceLocation QLoc, Expr *lhs,
                       SourceLocation CLoc, Expr *rhs, QualType t,
                       ExprValueKind VK, ExprObjectKind OK)
-      : AbstractConditionalOperator(
-            ConditionalOperatorClass, t, VK, OK,
-            // The type of the conditional operator depends on the type
-            // of the conditional to support the GCC vector conditional
-            // extension. Additionally, [temp.dep.expr] does specify state that
-            // this should be dependent on ALL sub expressions.
-            (cond->isTypeDependent() || lhs->isTypeDependent() ||
-             rhs->isTypeDependent()),
-            (cond->isValueDependent() || lhs->isValueDependent() ||
-             rhs->isValueDependent()),
-            (cond->isInstantiationDependent() ||
-             lhs->isInstantiationDependent() ||
-             rhs->isInstantiationDependent()),
-            (cond->containsUnexpandedParameterPack() ||
-             lhs->containsUnexpandedParameterPack() ||
-             rhs->containsUnexpandedParameterPack()),
-            QLoc, CLoc) {
+      : AbstractConditionalOperator(ConditionalOperatorClass, t, VK, OK, QLoc,
+                                    CLoc) {
     SubExprs[COND] = cond;
     SubExprs[LHS] = lhs;
     SubExprs[RHS] = rhs;
+    setDependence(computeDependence(this));
   }
 
   /// Build an empty conditional operator.
@@ -3887,20 +3810,15 @@ class BinaryConditionalOperator : public AbstractConditionalOperator {
                             Expr *cond, Expr *lhs, Expr *rhs,
                             SourceLocation qloc, SourceLocation cloc,
                             QualType t, ExprValueKind VK, ExprObjectKind OK)
-    : AbstractConditionalOperator(BinaryConditionalOperatorClass, t, VK, OK,
-           (common->isTypeDependent() || rhs->isTypeDependent()),
-           (common->isValueDependent() || rhs->isValueDependent()),
-           (common->isInstantiationDependent() ||
-            rhs->isInstantiationDependent()),
-           (common->containsUnexpandedParameterPack() ||
-            rhs->containsUnexpandedParameterPack()),
-                                  qloc, cloc),
-      OpaqueValue(opaqueValue) {
+      : AbstractConditionalOperator(BinaryConditionalOperatorClass, t, VK, OK,
+                                    qloc, cloc),
+        OpaqueValue(opaqueValue) {
     SubExprs[COMMON] = common;
     SubExprs[COND] = cond;
     SubExprs[LHS] = lhs;
     SubExprs[RHS] = rhs;
     assert(OpaqueValue->getSourceExpr() == common && "Wrong opaque value");
+    setDependence(computeDependence(this));
   }
 
   /// Build an empty conditional operator.
@@ -3978,9 +3896,10 @@ class AddrLabelExpr : public Expr {
 public:
   AddrLabelExpr(SourceLocation AALoc, SourceLocation LLoc, LabelDecl *L,
                 QualType t)
-    : Expr(AddrLabelExprClass, t, VK_RValue, OK_Ordinary, false, false, false,
-           false),
-      AmpAmpLoc(AALoc), LabelLoc(LLoc), Label(L) {}
+      : Expr(AddrLabelExprClass, t, VK_RValue, OK_Ordinary), AmpAmpLoc(AALoc),
+        LabelLoc(LLoc), Label(L) {
+    setDependence(ExprDependence::None);
+  }
 
   /// Build an empty address of a label expression.
   explicit AddrLabelExpr(EmptyShell Empty)
@@ -4022,12 +3941,9 @@ class StmtExpr : public Expr {
 public:
   StmtExpr(CompoundStmt *SubStmt, QualType T, SourceLocation LParenLoc,
            SourceLocation RParenLoc, unsigned TemplateDepth)
-      : // We treat a statement-expression in a dependent context as
-        // always being value- and instantiation-dependent. This matches the
-        // behavior of lambda-expressions and GCC.
-        Expr(StmtExprClass, T, VK_RValue, OK_Ordinary, T->isDependentType(),
-             TemplateDepth != 0, TemplateDepth != 0, false),
-        SubStmt(SubStmt), LParenLoc(LParenLoc), RParenLoc(RParenLoc) {
+      : Expr(StmtExprClass, T, VK_RValue, OK_Ordinary), SubStmt(SubStmt),
+        LParenLoc(LParenLoc), RParenLoc(RParenLoc) {
+    setDependence(computeDependence(this, TemplateDepth));
     // FIXME: A templated statement expression should have an associated
     // DeclContext so that nested declarations always have a dependent context.
     StmtExprBits.TemplateDepth = TemplateDepth;
@@ -4146,17 +4062,13 @@ class ConvertVectorExpr : public Expr {
   explicit ConvertVectorExpr(EmptyShell Empty) : Expr(ConvertVectorExprClass, Empty) {}
 
 public:
-  ConvertVectorExpr(Expr* SrcExpr, TypeSourceInfo *TI, QualType DstType,
-             ExprValueKind VK, ExprObjectKind OK,
-             SourceLocation BuiltinLoc, SourceLocation RParenLoc)
-    : Expr(ConvertVectorExprClass, DstType, VK, OK,
-           DstType->isDependentType(),
-           DstType->isDependentType() || SrcExpr->isValueDependent(),
-           (DstType->isInstantiationDependentType() ||
-            SrcExpr->isInstantiationDependent()),
-           (DstType->containsUnexpandedParameterPack() ||
-            SrcExpr->containsUnexpandedParameterPack())),
-  SrcExpr(SrcExpr), TInfo(TI), BuiltinLoc(BuiltinLoc), RParenLoc(RParenLoc) {}
+  ConvertVectorExpr(Expr *SrcExpr, TypeSourceInfo *TI, QualType DstType,
+                    ExprValueKind VK, ExprObjectKind OK,
+                    SourceLocation BuiltinLoc, SourceLocation RParenLoc)
+      : Expr(ConvertVectorExprClass, DstType, VK, OK), SrcExpr(SrcExpr),
+        TInfo(TI), BuiltinLoc(BuiltinLoc), RParenLoc(RParenLoc) {
+    setDependence(computeDependence(this));
+  }
 
   /// getSrcExpr - Return the Expr to be converted.
   Expr *getSrcExpr() const { return cast<Expr>(SrcExpr); }
@@ -4204,22 +4116,17 @@ class ChooseExpr : public Expr {
   SourceLocation BuiltinLoc, RParenLoc;
   bool CondIsTrue;
 public:
-  ChooseExpr(SourceLocation BLoc, Expr *cond, Expr *lhs, Expr *rhs,
-             QualType t, ExprValueKind VK, ExprObjectKind OK,
-             SourceLocation RP, bool condIsTrue,
-             bool TypeDependent, bool ValueDependent)
-    : Expr(ChooseExprClass, t, VK, OK, TypeDependent, ValueDependent,
-           (cond->isInstantiationDependent() ||
-            lhs->isInstantiationDependent() ||
-            rhs->isInstantiationDependent()),
-           (cond->containsUnexpandedParameterPack() ||
-            lhs->containsUnexpandedParameterPack() ||
-            rhs->containsUnexpandedParameterPack())),
-      BuiltinLoc(BLoc), RParenLoc(RP), CondIsTrue(condIsTrue) {
-      SubExprs[COND] = cond;
-      SubExprs[LHS] = lhs;
-      SubExprs[RHS] = rhs;
-    }
+  ChooseExpr(SourceLocation BLoc, Expr *cond, Expr *lhs, Expr *rhs, QualType t,
+             ExprValueKind VK, ExprObjectKind OK, SourceLocation RP,
+             bool condIsTrue)
+      : Expr(ChooseExprClass, t, VK, OK), BuiltinLoc(BLoc), RParenLoc(RP),
+        CondIsTrue(condIsTrue) {
+    SubExprs[COND] = cond;
+    SubExprs[LHS] = lhs;
+    SubExprs[RHS] = rhs;
+
+    setDependence(computeDependence(this));
+  }
 
   /// Build an empty __builtin_choose_expr.
   explicit ChooseExpr(EmptyShell Empty) : Expr(ChooseExprClass, Empty) { }
@@ -4284,9 +4191,9 @@ class GNUNullExpr : public Expr {
 
 public:
   GNUNullExpr(QualType Ty, SourceLocation Loc)
-    : Expr(GNUNullExprClass, Ty, VK_RValue, OK_Ordinary, false, false, false,
-           false),
-      TokenLoc(Loc) { }
+      : Expr(GNUNullExprClass, Ty, VK_RValue, OK_Ordinary), TokenLoc(Loc) {
+    setDependence(ExprDependence::None);
+  }
 
   /// Build an empty GNU __null expression.
   explicit GNUNullExpr(EmptyShell Empty) : Expr(GNUNullExprClass, Empty) { }
@@ -4319,12 +4226,10 @@ class VAArgExpr : public Expr {
 public:
   VAArgExpr(SourceLocation BLoc, Expr *e, TypeSourceInfo *TInfo,
             SourceLocation RPLoc, QualType t, bool IsMS)
-      : Expr(VAArgExprClass, t, VK_RValue, OK_Ordinary, t->isDependentType(),
-             false, (TInfo->getType()->isInstantiationDependentType() ||
-                     e->isInstantiationDependent()),
-             (TInfo->getType()->containsUnexpandedParameterPack() ||
-              e->containsUnexpandedParameterPack())),
-        Val(e), TInfo(TInfo, IsMS), BuiltinLoc(BLoc), RParenLoc(RPLoc) {}
+      : Expr(VAArgExprClass, t, VK_RValue, OK_Ordinary), Val(e),
+        TInfo(TInfo, IsMS), BuiltinLoc(BLoc), RParenLoc(RPLoc) {
+    setDependence(computeDependence(this));
+  }
 
   /// Create an empty __builtin_va_arg expression.
   explicit VAArgExpr(EmptyShell Empty)
@@ -5003,8 +4908,9 @@ class DesignatedInitExpr final
 class NoInitExpr : public Expr {
 public:
   explicit NoInitExpr(QualType ty)
-    : Expr(NoInitExprClass, ty, VK_RValue, OK_Ordinary,
-           false, false, ty->isInstantiationDependentType(), false) { }
+      : Expr(NoInitExprClass, ty, VK_RValue, OK_Ordinary) {
+    setDependence(computeDependence(this));
+  }
 
   explicit NoInitExpr(EmptyShell Empty)
     : Expr(NoInitExprClass, Empty) { }
@@ -5098,12 +5004,10 @@ class ArrayInitLoopExpr : public Expr {
 
 public:
   explicit ArrayInitLoopExpr(QualType T, Expr *CommonInit, Expr *ElementInit)
-      : Expr(ArrayInitLoopExprClass, T, VK_RValue, OK_Ordinary, false,
-             CommonInit->isValueDependent() || ElementInit->isValueDependent(),
-             T->isInstantiationDependentType(),
-             CommonInit->containsUnexpandedParameterPack() ||
-                 ElementInit->containsUnexpandedParameterPack()),
-        SubExprs{CommonInit, ElementInit} {}
+      : Expr(ArrayInitLoopExprClass, T, VK_RValue, OK_Ordinary),
+        SubExprs{CommonInit, ElementInit} {
+    setDependence(computeDependence(this));
+  }
 
   /// Get the common subexpression shared by all initializations (the source
   /// array).
@@ -5151,8 +5055,9 @@ class ArrayInitIndexExpr : public Expr {
 
 public:
   explicit ArrayInitIndexExpr(QualType T)
-      : Expr(ArrayInitIndexExprClass, T, VK_RValue, OK_Ordinary,
-             false, false, false, false) {}
+      : Expr(ArrayInitIndexExprClass, T, VK_RValue, OK_Ordinary) {
+    setDependence(ExprDependence::None);
+  }
 
   static bool classof(const Stmt *S) {
     return S->getStmtClass() == ArrayInitIndexExprClass;
@@ -5183,8 +5088,9 @@ class ArrayInitIndexExpr : public Expr {
 class ImplicitValueInitExpr : public Expr {
 public:
   explicit ImplicitValueInitExpr(QualType ty)
-    : Expr(ImplicitValueInitExprClass, ty, VK_RValue, OK_Ordinary,
-           false, false, ty->isInstantiationDependentType(), false) { }
+      : Expr(ImplicitValueInitExprClass, ty, VK_RValue, OK_Ordinary) {
+    setDependence(computeDependence(this));
+  }
 
   /// Construct an empty implicit value initialization.
   explicit ImplicitValueInitExpr(EmptyShell Empty)
@@ -5586,12 +5492,11 @@ class ExtVectorElementExpr : public Expr {
 public:
   ExtVectorElementExpr(QualType ty, ExprValueKind VK, Expr *base,
                        IdentifierInfo &accessor, SourceLocation loc)
-    : Expr(ExtVectorElementExprClass, ty, VK,
-           (VK == VK_RValue ? OK_Ordinary : OK_VectorComponent),
-           base->isTypeDependent(), base->isValueDependent(),
-           base->isInstantiationDependent(),
-           base->containsUnexpandedParameterPack()),
-      Base(base), Accessor(&accessor), AccessorLoc(loc) {}
+      : Expr(ExtVectorElementExprClass, ty, VK,
+             (VK == VK_RValue ? OK_Ordinary : OK_VectorComponent)),
+        Base(base), Accessor(&accessor), AccessorLoc(loc) {
+    setDependence(computeDependence(this));
+  }
 
   /// Build an empty vector element expression.
   explicit ExtVectorElementExpr(EmptyShell Empty)
@@ -5645,11 +5550,9 @@ class BlockExpr : public Expr {
   BlockDecl *TheBlock;
 public:
   BlockExpr(BlockDecl *BD, QualType ty)
-    : Expr(BlockExprClass, ty, VK_RValue, OK_Ordinary,
-           ty->isDependentType(), ty->isDependentType(),
-           ty->isInstantiationDependentType() || BD->isDependentContext(),
-           false),
-      TheBlock(BD) {}
+      : Expr(BlockExprClass, ty, VK_RValue, OK_Ordinary), TheBlock(BD) {
+    setDependence(computeDependence(this));
+  }
 
   /// Build an empty block expression.
   explicit BlockExpr(EmptyShell Empty) : Expr(BlockExprClass, Empty) { }
@@ -5713,17 +5616,13 @@ class AsTypeExpr : public Expr {
   explicit AsTypeExpr(EmptyShell Empty) : Expr(AsTypeExprClass, Empty) {}
 
 public:
-  AsTypeExpr(Expr* SrcExpr, QualType DstType,
-             ExprValueKind VK, ExprObjectKind OK,
-             SourceLocation BuiltinLoc, SourceLocation RParenLoc)
-    : Expr(AsTypeExprClass, DstType, VK, OK,
-           DstType->isDependentType(),
-           DstType->isDependentType() || SrcExpr->isValueDependent(),
-           (DstType->isInstantiationDependentType() ||
-            SrcExpr->isInstantiationDependent()),
-           (DstType->containsUnexpandedParameterPack() ||
-            SrcExpr->containsUnexpandedParameterPack())),
-  SrcExpr(SrcExpr), BuiltinLoc(BuiltinLoc), RParenLoc(RParenLoc) {}
+  AsTypeExpr(Expr *SrcExpr, QualType DstType, ExprValueKind VK,
+             ExprObjectKind OK, SourceLocation BuiltinLoc,
+             SourceLocation RParenLoc)
+      : Expr(AsTypeExprClass, DstType, VK, OK), SrcExpr(SrcExpr),
+        BuiltinLoc(BuiltinLoc), RParenLoc(RParenLoc) {
+    setDependence(computeDependence(this));
+  }
 
   /// getSrcExpr - Return the Expr to be converted.
   Expr *getSrcExpr() const { return cast<Expr>(SrcExpr); }
@@ -6041,13 +5940,9 @@ class AtomicExpr : public Expr {
 /// still needs to be performed and/or an error diagnostic emitted.
 class TypoExpr : public Expr {
 public:
-  TypoExpr(QualType T)
-      : Expr(TypoExprClass, T, VK_LValue, OK_Ordinary,
-             /*isTypeDependent*/ true,
-             /*isValueDependent*/ true,
-             /*isInstantiationDependent*/ true,
-             /*containsUnexpandedParameterPack*/ false) {
+  TypoExpr(QualType T) : Expr(TypoExprClass, T, VK_LValue, OK_Ordinary) {
     assert(T->isDependentType() && "TypoExpr given a non-dependent type");
+    setDependence(ExprDependence::TypeValueInstantiation);
   }
 
   child_range children() {
diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h
index 694575790f48b..33ea3f6346b22 100644
--- a/clang/include/clang/AST/ExprCXX.h
+++ b/clang/include/clang/AST/ExprCXX.h
@@ -14,11 +14,14 @@
 #ifndef LLVM_CLANG_AST_EXPRCXX_H
 #define LLVM_CLANG_AST_EXPRCXX_H
 
+#include "clang/AST/ASTConcept.h"
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclBase.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/DeclarationName.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/NestedNameSpecifier.h"
 #include "clang/AST/OperationKinds.h"
@@ -295,12 +298,10 @@ class CXXRewrittenBinaryOperator : public Expr {
 public:
   CXXRewrittenBinaryOperator(Expr *SemanticForm, bool IsReversed)
       : Expr(CXXRewrittenBinaryOperatorClass, SemanticForm->getType(),
-             SemanticForm->getValueKind(), SemanticForm->getObjectKind(),
-             SemanticForm->isTypeDependent(), SemanticForm->isValueDependent(),
-             SemanticForm->isInstantiationDependent(),
-             SemanticForm->containsUnexpandedParameterPack()),
+             SemanticForm->getValueKind(), SemanticForm->getObjectKind()),
         SemanticForm(SemanticForm) {
     CXXRewrittenBinaryOperatorBits.IsReversed = IsReversed;
+    setDependence(computeDependence(this));
   }
   CXXRewrittenBinaryOperator(EmptyShell Empty)
       : Expr(CXXRewrittenBinaryOperatorClass, Empty), SemanticForm() {}
@@ -661,10 +662,10 @@ class UserDefinedLiteral final : public CallExpr {
 class CXXBoolLiteralExpr : public Expr {
 public:
   CXXBoolLiteralExpr(bool Val, QualType Ty, SourceLocation Loc)
-      : Expr(CXXBoolLiteralExprClass, Ty, VK_RValue, OK_Ordinary, false, false,
-             false, false) {
+      : Expr(CXXBoolLiteralExprClass, Ty, VK_RValue, OK_Ordinary) {
     CXXBoolLiteralExprBits.Value = Val;
     CXXBoolLiteralExprBits.Loc = Loc;
+    setDependence(ExprDependence::None);
   }
 
   explicit CXXBoolLiteralExpr(EmptyShell Empty)
@@ -699,9 +700,9 @@ class CXXBoolLiteralExpr : public Expr {
 class CXXNullPtrLiteralExpr : public Expr {
 public:
   CXXNullPtrLiteralExpr(QualType Ty, SourceLocation Loc)
-      : Expr(CXXNullPtrLiteralExprClass, Ty, VK_RValue, OK_Ordinary, false,
-             false, false, false) {
+      : Expr(CXXNullPtrLiteralExprClass, Ty, VK_RValue, OK_Ordinary) {
     CXXNullPtrLiteralExprBits.Loc = Loc;
+    setDependence(ExprDependence::None);
   }
 
   explicit CXXNullPtrLiteralExpr(EmptyShell Empty)
@@ -739,11 +740,10 @@ class CXXStdInitializerListExpr : public Expr {
   friend class ASTStmtReader;
 
   CXXStdInitializerListExpr(QualType Ty, Expr *SubExpr)
-      : Expr(CXXStdInitializerListExprClass, Ty, VK_RValue, OK_Ordinary,
-             Ty->isDependentType(), SubExpr->isValueDependent(),
-             SubExpr->isInstantiationDependent(),
-             SubExpr->containsUnexpandedParameterPack()),
-        SubExpr(SubExpr) {}
+      : Expr(CXXStdInitializerListExprClass, Ty, VK_RValue, OK_Ordinary),
+        SubExpr(SubExpr) {
+    setDependence(computeDependence(this));
+  }
 
   Expr *getSubExpr() { return static_cast<Expr*>(SubExpr); }
   const Expr *getSubExpr() const { return static_cast<const Expr*>(SubExpr); }
@@ -784,26 +784,16 @@ class CXXTypeidExpr : public Expr {
 
 public:
   CXXTypeidExpr(QualType Ty, TypeSourceInfo *Operand, SourceRange R)
-      : Expr(CXXTypeidExprClass, Ty, VK_LValue, OK_Ordinary,
-             // typeid is never type-dependent (C++ [temp.dep.expr]p4)
-             false,
-             // typeid is value-dependent if the type or expression are
-             // dependent
-             Operand->getType()->isDependentType(),
-             Operand->getType()->isInstantiationDependentType(),
-             Operand->getType()->containsUnexpandedParameterPack()),
-        Operand(Operand), Range(R) {}
+      : Expr(CXXTypeidExprClass, Ty, VK_LValue, OK_Ordinary), Operand(Operand),
+        Range(R) {
+    setDependence(computeDependence(this));
+  }
 
   CXXTypeidExpr(QualType Ty, Expr *Operand, SourceRange R)
-      : Expr(CXXTypeidExprClass, Ty, VK_LValue, OK_Ordinary,
-             // typeid is never type-dependent (C++ [temp.dep.expr]p4)
-             false,
-             // typeid is value-dependent if the type or expression are
-             // dependent
-             Operand->isTypeDependent() || Operand->isValueDependent(),
-             Operand->isInstantiationDependent(),
-             Operand->containsUnexpandedParameterPack()),
-        Operand(Operand), Range(R) {}
+      : Expr(CXXTypeidExprClass, Ty, VK_LValue, OK_Ordinary), Operand(Operand),
+        Range(R) {
+    setDependence(computeDependence(this));
+  }
 
   CXXTypeidExpr(EmptyShell Empty, bool isExpr)
       : Expr(CXXTypeidExprClass, Empty) {
@@ -888,15 +878,12 @@ class MSPropertyRefExpr : public Expr {
 
   MSPropertyRefExpr(Expr *baseExpr, MSPropertyDecl *decl, bool isArrow,
                     QualType ty, ExprValueKind VK,
-                    NestedNameSpecifierLoc qualifierLoc,
-                    SourceLocation nameLoc)
-      : Expr(MSPropertyRefExprClass, ty, VK, OK_Ordinary,
-             /*type-dependent*/ false, baseExpr->isValueDependent(),
-             baseExpr->isInstantiationDependent(),
-             baseExpr->containsUnexpandedParameterPack()),
-        BaseExpr(baseExpr), TheDecl(decl),
-        MemberLoc(nameLoc), IsArrow(isArrow),
-        QualifierLoc(qualifierLoc) {}
+                    NestedNameSpecifierLoc qualifierLoc, SourceLocation nameLoc)
+      : Expr(MSPropertyRefExprClass, ty, VK, OK_Ordinary), BaseExpr(baseExpr),
+        TheDecl(decl), MemberLoc(nameLoc), IsArrow(isArrow),
+        QualifierLoc(qualifierLoc) {
+    setDependence(computeDependence(this));
+  }
 
   MSPropertyRefExpr(EmptyShell Empty) : Expr(MSPropertyRefExprClass, Empty) {}
 
@@ -964,12 +951,11 @@ class MSPropertySubscriptExpr : public Expr {
 public:
   MSPropertySubscriptExpr(Expr *Base, Expr *Idx, QualType Ty, ExprValueKind VK,
                           ExprObjectKind OK, SourceLocation RBracketLoc)
-      : Expr(MSPropertySubscriptExprClass, Ty, VK, OK, Idx->isTypeDependent(),
-             Idx->isValueDependent(), Idx->isInstantiationDependent(),
-             Idx->containsUnexpandedParameterPack()),
+      : Expr(MSPropertySubscriptExprClass, Ty, VK, OK),
         RBracketLoc(RBracketLoc) {
     SubExprs[BASE_EXPR] = Base;
     SubExprs[IDX_EXPR] = Idx;
+    setDependence(computeDependence(this));
   }
 
   /// Create an empty array subscript expression.
@@ -1022,17 +1008,16 @@ class CXXUuidofExpr : public Expr {
 public:
   CXXUuidofExpr(QualType Ty, TypeSourceInfo *Operand, StringRef UuidStr,
                 SourceRange R)
-      : Expr(CXXUuidofExprClass, Ty, VK_LValue, OK_Ordinary, false,
-             Operand->getType()->isDependentType(),
-             Operand->getType()->isInstantiationDependentType(),
-             Operand->getType()->containsUnexpandedParameterPack()),
-        Operand(Operand), UuidStr(UuidStr), Range(R) {}
+      : Expr(CXXUuidofExprClass, Ty, VK_LValue, OK_Ordinary), Operand(Operand),
+        UuidStr(UuidStr), Range(R) {
+    setDependence(computeDependence(this));
+  }
 
   CXXUuidofExpr(QualType Ty, Expr *Operand, StringRef UuidStr, SourceRange R)
-      : Expr(CXXUuidofExprClass, Ty, VK_LValue, OK_Ordinary, false,
-             Operand->isTypeDependent(), Operand->isInstantiationDependent(),
-             Operand->containsUnexpandedParameterPack()),
-        Operand(Operand), UuidStr(UuidStr), Range(R) {}
+      : Expr(CXXUuidofExprClass, Ty, VK_LValue, OK_Ordinary), Operand(Operand),
+        UuidStr(UuidStr), Range(R) {
+    setDependence(computeDependence(this));
+  }
 
   CXXUuidofExpr(EmptyShell Empty, bool isExpr)
     : Expr(CXXUuidofExprClass, Empty) {
@@ -1113,14 +1098,10 @@ class CXXUuidofExpr : public Expr {
 class CXXThisExpr : public Expr {
 public:
   CXXThisExpr(SourceLocation L, QualType Ty, bool IsImplicit)
-      : Expr(CXXThisExprClass, Ty, VK_RValue, OK_Ordinary,
-             // 'this' is type-dependent if the class type of the enclosing
-             // member function is dependent (C++ [temp.dep.expr]p2)
-             Ty->isDependentType(), Ty->isDependentType(),
-             Ty->isInstantiationDependentType(),
-             /*ContainsUnexpandedParameterPack=*/false) {
+      : Expr(CXXThisExprClass, Ty, VK_RValue, OK_Ordinary) {
     CXXThisExprBits.IsImplicit = IsImplicit;
     CXXThisExprBits.Loc = L;
+    setDependence(computeDependence(this));
   }
 
   CXXThisExpr(EmptyShell Empty) : Expr(CXXThisExprClass, Empty) {}
@@ -1166,12 +1147,10 @@ class CXXThrowExpr : public Expr {
   // null if not present.
   CXXThrowExpr(Expr *Operand, QualType Ty, SourceLocation Loc,
                bool IsThrownVariableInScope)
-      : Expr(CXXThrowExprClass, Ty, VK_RValue, OK_Ordinary, false, false,
-             Operand && Operand->isInstantiationDependent(),
-             Operand && Operand->containsUnexpandedParameterPack()),
-        Operand(Operand) {
+      : Expr(CXXThrowExprClass, Ty, VK_RValue, OK_Ordinary), Operand(Operand) {
     CXXThrowExprBits.ThrowLoc = Loc;
     CXXThrowExprBits.IsThrownVariableInScope = IsThrownVariableInScope;
+    setDependence(computeDependence(this));
   }
   CXXThrowExpr(EmptyShell Empty) : Expr(CXXThrowExprClass, Empty) {}
 
@@ -1225,16 +1204,16 @@ class CXXDefaultArgExpr final : public Expr {
   DeclContext *UsedContext;
 
   CXXDefaultArgExpr(StmtClass SC, SourceLocation Loc, ParmVarDecl *Param,
-      DeclContext *UsedContext)
+                    DeclContext *UsedContext)
       : Expr(SC,
              Param->hasUnparsedDefaultArg()
                  ? Param->getType().getNonReferenceType()
                  : Param->getDefaultArg()->getType(),
              Param->getDefaultArg()->getValueKind(),
-             Param->getDefaultArg()->getObjectKind(), false, false, false,
-             false),
+             Param->getDefaultArg()->getObjectKind()),
         Param(Param), UsedContext(UsedContext) {
     CXXDefaultArgExprBits.Loc = Loc;
+    setDependence(ExprDependence::None);
   }
 
 public:
@@ -1390,13 +1369,12 @@ class CXXBindTemporaryExpr : public Expr {
   CXXTemporary *Temp = nullptr;
   Stmt *SubExpr = nullptr;
 
-  CXXBindTemporaryExpr(CXXTemporary *temp, Expr* SubExpr)
-      : Expr(CXXBindTemporaryExprClass, SubExpr->getType(),
-             VK_RValue, OK_Ordinary, SubExpr->isTypeDependent(),
-             SubExpr->isValueDependent(),
-             SubExpr->isInstantiationDependent(),
-             SubExpr->containsUnexpandedParameterPack()),
-        Temp(temp), SubExpr(SubExpr) {}
+  CXXBindTemporaryExpr(CXXTemporary *temp, Expr *SubExpr)
+      : Expr(CXXBindTemporaryExprClass, SubExpr->getType(), VK_RValue,
+             OK_Ordinary),
+        Temp(temp), SubExpr(SubExpr) {
+    setDependence(computeDependence(this));
+  }
 
 public:
   CXXBindTemporaryExpr(EmptyShell Empty)
@@ -1647,12 +1625,12 @@ class CXXInheritedCtorInitExpr : public Expr {
   CXXInheritedCtorInitExpr(SourceLocation Loc, QualType T,
                            CXXConstructorDecl *Ctor, bool ConstructsVirtualBase,
                            bool InheritedFromVirtualBase)
-      : Expr(CXXInheritedCtorInitExprClass, T, VK_RValue, OK_Ordinary, false,
-             false, false, false),
+      : Expr(CXXInheritedCtorInitExprClass, T, VK_RValue, OK_Ordinary),
         Constructor(Ctor), Loc(Loc),
         ConstructsVirtualBase(ConstructsVirtualBase),
         InheritedFromVirtualBase(InheritedFromVirtualBase) {
     assert(!T->isDependentType());
+    setDependence(ExprDependence::None);
   }
 
   /// Construct an empty C++ inheriting construction expression.
@@ -2076,11 +2054,10 @@ class CXXScalarValueInitExpr : public Expr {
   /// expression.
   CXXScalarValueInitExpr(QualType Type, TypeSourceInfo *TypeInfo,
                          SourceLocation RParenLoc)
-      : Expr(CXXScalarValueInitExprClass, Type, VK_RValue, OK_Ordinary, false,
-             false, Type->isInstantiationDependentType(),
-             Type->containsUnexpandedParameterPack()),
+      : Expr(CXXScalarValueInitExprClass, Type, VK_RValue, OK_Ordinary),
         TypeInfo(TypeInfo) {
     CXXScalarValueInitExprBits.RParenLoc = RParenLoc;
+    setDependence(computeDependence(this));
   }
 
   explicit CXXScalarValueInitExpr(EmptyShell Shell)
@@ -2385,15 +2362,14 @@ class CXXDeleteExpr : public Expr {
   CXXDeleteExpr(QualType Ty, bool GlobalDelete, bool ArrayForm,
                 bool ArrayFormAsWritten, bool UsualArrayDeleteWantsSize,
                 FunctionDecl *OperatorDelete, Expr *Arg, SourceLocation Loc)
-      : Expr(CXXDeleteExprClass, Ty, VK_RValue, OK_Ordinary, false,
-             Arg->isValueDependent(), Arg->isInstantiationDependent(),
-             Arg->containsUnexpandedParameterPack()),
+      : Expr(CXXDeleteExprClass, Ty, VK_RValue, OK_Ordinary),
         OperatorDelete(OperatorDelete), Argument(Arg) {
     CXXDeleteExprBits.GlobalDelete = GlobalDelete;
     CXXDeleteExprBits.ArrayForm = ArrayForm;
     CXXDeleteExprBits.ArrayFormAsWritten = ArrayFormAsWritten;
     CXXDeleteExprBits.UsualArrayDeleteWantsSize = UsualArrayDeleteWantsSize;
     CXXDeleteExprBits.Loc = Loc;
+    setDependence(computeDependence(this));
   }
 
   explicit CXXDeleteExpr(EmptyShell Shell) : Expr(CXXDeleteExprClass, Shell) {}
@@ -2751,15 +2727,13 @@ class ArrayTypeTraitExpr : public Expr {
   friend class ASTStmtReader;
 
   ArrayTypeTraitExpr(SourceLocation loc, ArrayTypeTrait att,
-                     TypeSourceInfo *queried, uint64_t value,
-                     Expr *dimension, SourceLocation rparen, QualType ty)
-      : Expr(ArrayTypeTraitExprClass, ty, VK_RValue, OK_Ordinary,
-             false, queried->getType()->isDependentType(),
-             (queried->getType()->isInstantiationDependentType() ||
-              (dimension && dimension->isInstantiationDependent())),
-             queried->getType()->containsUnexpandedParameterPack()),
-        ATT(att), Value(value), Dimension(dimension),
-        Loc(loc), RParen(rparen), QueriedType(queried) {}
+                     TypeSourceInfo *queried, uint64_t value, Expr *dimension,
+                     SourceLocation rparen, QualType ty)
+      : Expr(ArrayTypeTraitExprClass, ty, VK_RValue, OK_Ordinary), ATT(att),
+        Value(value), Dimension(dimension), Loc(loc), RParen(rparen),
+        QueriedType(queried) {
+    setDependence(computeDependence(this));
+  }
 
   explicit ArrayTypeTraitExpr(EmptyShell Empty)
       : Expr(ArrayTypeTraitExprClass, Empty), ATT(0) {}
@@ -2817,17 +2791,13 @@ class ExpressionTraitExpr : public Expr {
 public:
   friend class ASTStmtReader;
 
-  ExpressionTraitExpr(SourceLocation loc, ExpressionTrait et,
-                     Expr *queried, bool value,
-                     SourceLocation rparen, QualType resultType)
-      : Expr(ExpressionTraitExprClass, resultType, VK_RValue, OK_Ordinary,
-             false, // Not type-dependent
-             // Value-dependent if the argument is type-dependent.
-             queried->isTypeDependent(),
-             queried->isInstantiationDependent(),
-             queried->containsUnexpandedParameterPack()),
+  ExpressionTraitExpr(SourceLocation loc, ExpressionTrait et, Expr *queried,
+                      bool value, SourceLocation rparen, QualType resultType)
+      : Expr(ExpressionTraitExprClass, resultType, VK_RValue, OK_Ordinary),
         ET(et), Value(value), Loc(loc), RParen(rparen),
-        QueriedExpression(queried) {}
+        QueriedExpression(queried) {
+    setDependence(computeDependence(this));
+  }
 
   explicit ExpressionTraitExpr(EmptyShell Empty)
       : Expr(ExpressionTraitExprClass, Empty), ET(0), Value(false) {}
@@ -3982,13 +3952,10 @@ class CXXNoexceptExpr : public Expr {
 public:
   CXXNoexceptExpr(QualType Ty, Expr *Operand, CanThrowResult Val,
                   SourceLocation Keyword, SourceLocation RParen)
-      : Expr(CXXNoexceptExprClass, Ty, VK_RValue, OK_Ordinary,
-             /*TypeDependent*/ false,
-             /*ValueDependent*/ Val == CT_Dependent,
-             Val == CT_Dependent || Operand->isInstantiationDependent(),
-             Operand->containsUnexpandedParameterPack()),
+      : Expr(CXXNoexceptExprClass, Ty, VK_RValue, OK_Ordinary),
         Operand(Operand), Range(Keyword, RParen) {
     CXXNoexceptExprBits.Value = Val == CT_Cannot;
+    setDependence(computeDependence(this, Val));
   }
 
   CXXNoexceptExpr(EmptyShell Empty) : Expr(CXXNoexceptExprClass, Empty) {}
@@ -4049,12 +4016,12 @@ class PackExpansionExpr : public Expr {
   PackExpansionExpr(QualType T, Expr *Pattern, SourceLocation EllipsisLoc,
                     Optional<unsigned> NumExpansions)
       : Expr(PackExpansionExprClass, T, Pattern->getValueKind(),
-             Pattern->getObjectKind(), /*TypeDependent=*/true,
-             /*ValueDependent=*/true, /*InstantiationDependent=*/true,
-             /*ContainsUnexpandedParameterPack=*/false),
+             Pattern->getObjectKind()),
         EllipsisLoc(EllipsisLoc),
         NumExpansions(NumExpansions ? *NumExpansions + 1 : 0),
-        Pattern(Pattern) {}
+        Pattern(Pattern) {
+    setDependence(ExprDependence::TypeValueInstantiation);
+  }
 
   PackExpansionExpr(EmptyShell Empty) : Expr(PackExpansionExprClass, Empty) {}
 
@@ -4141,17 +4108,17 @@ class SizeOfPackExpr final
   /// the given parameter pack.
   SizeOfPackExpr(QualType SizeType, SourceLocation OperatorLoc, NamedDecl *Pack,
                  SourceLocation PackLoc, SourceLocation RParenLoc,
-                 Optional<unsigned> Length, ArrayRef<TemplateArgument> PartialArgs)
-      : Expr(SizeOfPackExprClass, SizeType, VK_RValue, OK_Ordinary,
-             /*TypeDependent=*/false, /*ValueDependent=*/!Length,
-             /*InstantiationDependent=*/!Length,
-             /*ContainsUnexpandedParameterPack=*/false),
+                 Optional<unsigned> Length,
+                 ArrayRef<TemplateArgument> PartialArgs)
+      : Expr(SizeOfPackExprClass, SizeType, VK_RValue, OK_Ordinary),
         OperatorLoc(OperatorLoc), PackLoc(PackLoc), RParenLoc(RParenLoc),
         Length(Length ? *Length : PartialArgs.size()), Pack(Pack) {
     assert((!Length || PartialArgs.empty()) &&
            "have partial args for non-dependent sizeof... expression");
     auto *Args = getTrailingObjects<TemplateArgument>();
     std::uninitialized_copy(PartialArgs.begin(), PartialArgs.end(), Args);
+    setDependence(Length ? ExprDependence::None
+                         : ExprDependence::ValueInstantiation);
   }
 
   /// Create an empty expression.
@@ -4242,12 +4209,10 @@ class SubstNonTypeTemplateParmExpr : public Expr {
                                SourceLocation Loc,
                                NonTypeTemplateParmDecl *Param,
                                Expr *Replacement)
-      : Expr(SubstNonTypeTemplateParmExprClass, Ty, ValueKind, OK_Ordinary,
-             Replacement->isTypeDependent(), Replacement->isValueDependent(),
-             Replacement->isInstantiationDependent(),
-             Replacement->containsUnexpandedParameterPack()),
+      : Expr(SubstNonTypeTemplateParmExprClass, Ty, ValueKind, OK_Ordinary),
         Param(Param), Replacement(Replacement) {
     SubstNonTypeTemplateParmExprBits.NameLoc = Loc;
+    setDependence(computeDependence(this));
   }
 
   SourceLocation getNameLoc() const {
@@ -4561,13 +4526,12 @@ class CXXFoldExpr : public Expr {
   CXXFoldExpr(QualType T, SourceLocation LParenLoc, Expr *LHS,
               BinaryOperatorKind Opcode, SourceLocation EllipsisLoc, Expr *RHS,
               SourceLocation RParenLoc, Optional<unsigned> NumExpansions)
-      : Expr(CXXFoldExprClass, T, VK_RValue, OK_Ordinary,
-             /*Dependent*/ true, true, true,
-             /*ContainsUnexpandedParameterPack*/ false),
-        LParenLoc(LParenLoc), EllipsisLoc(EllipsisLoc), RParenLoc(RParenLoc),
+      : Expr(CXXFoldExprClass, T, VK_RValue, OK_Ordinary), LParenLoc(LParenLoc),
+        EllipsisLoc(EllipsisLoc), RParenLoc(RParenLoc),
         NumExpansions(NumExpansions ? *NumExpansions + 1 : 0), Opcode(Opcode) {
     SubExprs[0] = LHS;
     SubExprs[1] = RHS;
+    setDependence(ExprDependence::TypeValueInstantiation);
   }
 
   CXXFoldExpr(EmptyShell Empty) : Expr(CXXFoldExprClass, Empty) {}
@@ -4642,27 +4606,25 @@ class CoroutineSuspendExpr : public Expr {
                        Expr *Ready, Expr *Suspend, Expr *Resume,
                        OpaqueValueExpr *OpaqueValue)
       : Expr(SC, Resume->getType(), Resume->getValueKind(),
-             Resume->getObjectKind(), Resume->isTypeDependent(),
-             Resume->isValueDependent(), Common->isInstantiationDependent(),
-             Common->containsUnexpandedParameterPack()),
+             Resume->getObjectKind()),
         KeywordLoc(KeywordLoc), OpaqueValue(OpaqueValue) {
     SubExprs[SubExpr::Common] = Common;
     SubExprs[SubExpr::Ready] = Ready;
     SubExprs[SubExpr::Suspend] = Suspend;
     SubExprs[SubExpr::Resume] = Resume;
+    setDependence(computeDependence(this));
   }
 
   CoroutineSuspendExpr(StmtClass SC, SourceLocation KeywordLoc, QualType Ty,
                        Expr *Common)
-      : Expr(SC, Ty, VK_RValue, OK_Ordinary, true, true, true,
-             Common->containsUnexpandedParameterPack()),
-        KeywordLoc(KeywordLoc) {
+      : Expr(SC, Ty, VK_RValue, OK_Ordinary), KeywordLoc(KeywordLoc) {
     assert(Common->isTypeDependent() && Ty->isDependentType() &&
            "wrong constructor for non-dependent co_await/co_yield expression");
     SubExprs[SubExpr::Common] = Common;
     SubExprs[SubExpr::Ready] = nullptr;
     SubExprs[SubExpr::Suspend] = nullptr;
     SubExprs[SubExpr::Resume] = nullptr;
+    setDependence(computeDependence(this));
   }
 
   CoroutineSuspendExpr(StmtClass SC, EmptyShell Empty) : Expr(SC, Empty) {
@@ -4759,10 +4721,7 @@ class DependentCoawaitExpr : public Expr {
 public:
   DependentCoawaitExpr(SourceLocation KeywordLoc, QualType Ty, Expr *Op,
                        UnresolvedLookupExpr *OpCoawait)
-      : Expr(DependentCoawaitExprClass, Ty, VK_RValue, OK_Ordinary,
-             /*TypeDependent*/ true, /*ValueDependent*/ true,
-             /*InstantiationDependent*/ true,
-             Op->containsUnexpandedParameterPack()),
+      : Expr(DependentCoawaitExprClass, Ty, VK_RValue, OK_Ordinary),
         KeywordLoc(KeywordLoc) {
     // NOTE: A co_await expression is dependent on the coroutines promise
     // type and may be dependent even when the `Op` expression is not.
@@ -4770,6 +4729,7 @@ class DependentCoawaitExpr : public Expr {
            "wrong constructor for non-dependent co_await/co_yield expression");
     SubExprs[0] = Op;
     SubExprs[1] = OpCoawait;
+    setDependence(computeDependence(this));
   }
 
   DependentCoawaitExpr(EmptyShell Empty)
diff --git a/clang/include/clang/AST/ExprObjC.h b/clang/include/clang/AST/ExprObjC.h
index d76b3a26b1f94..4b39d9ab96a6a 100644
--- a/clang/include/clang/AST/ExprObjC.h
+++ b/clang/include/clang/AST/ExprObjC.h
@@ -13,8 +13,10 @@
 #ifndef LLVM_CLANG_AST_EXPROBJC_H
 #define LLVM_CLANG_AST_EXPROBJC_H
 
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclObjC.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/OperationKinds.h"
 #include "clang/AST/SelectorLocationsKind.h"
@@ -53,9 +55,10 @@ class ObjCStringLiteral : public Expr {
 
 public:
   ObjCStringLiteral(StringLiteral *SL, QualType T, SourceLocation L)
-      : Expr(ObjCStringLiteralClass, T, VK_RValue, OK_Ordinary, false, false,
-             false, false),
-        String(SL), AtLoc(L) {}
+      : Expr(ObjCStringLiteralClass, T, VK_RValue, OK_Ordinary), String(SL),
+        AtLoc(L) {
+    setDependence(ExprDependence::None);
+  }
   explicit ObjCStringLiteral(EmptyShell Empty)
       : Expr(ObjCStringLiteralClass, Empty) {}
 
@@ -88,9 +91,10 @@ class ObjCBoolLiteralExpr : public Expr {
 
 public:
   ObjCBoolLiteralExpr(bool val, QualType Ty, SourceLocation l)
-      : Expr(ObjCBoolLiteralExprClass, Ty, VK_RValue, OK_Ordinary, false, false,
-             false, false),
-        Value(val), Loc(l) {}
+      : Expr(ObjCBoolLiteralExprClass, Ty, VK_RValue, OK_Ordinary), Value(val),
+        Loc(l) {
+    setDependence(ExprDependence::None);
+  }
   explicit ObjCBoolLiteralExpr(EmptyShell Empty)
       : Expr(ObjCBoolLiteralExprClass, Empty) {}
 
@@ -129,13 +133,11 @@ class ObjCBoxedExpr : public Expr {
 public:
   friend class ASTStmtReader;
 
-  ObjCBoxedExpr(Expr *E, QualType T, ObjCMethodDecl *method,
-                     SourceRange R)
-      : Expr(ObjCBoxedExprClass, T, VK_RValue, OK_Ordinary,
-             E->isTypeDependent(), E->isValueDependent(),
-             E->isInstantiationDependent(),
-             E->containsUnexpandedParameterPack()),
-        SubExpr(E), BoxingMethod(method), Range(R) {}
+  ObjCBoxedExpr(Expr *E, QualType T, ObjCMethodDecl *method, SourceRange R)
+      : Expr(ObjCBoxedExprClass, T, VK_RValue, OK_Ordinary), SubExpr(E),
+        BoxingMethod(method), Range(R) {
+    setDependence(computeDependence(this));
+  }
   explicit ObjCBoxedExpr(EmptyShell Empty)
       : Expr(ObjCBoxedExprClass, Empty) {}
 
@@ -409,14 +411,12 @@ class ObjCEncodeExpr : public Expr {
   SourceLocation AtLoc, RParenLoc;
 
 public:
-  ObjCEncodeExpr(QualType T, TypeSourceInfo *EncodedType,
-                 SourceLocation at, SourceLocation rp)
-      : Expr(ObjCEncodeExprClass, T, VK_LValue, OK_Ordinary,
-             EncodedType->getType()->isDependentType(),
-             EncodedType->getType()->isDependentType(),
-             EncodedType->getType()->isInstantiationDependentType(),
-             EncodedType->getType()->containsUnexpandedParameterPack()),
-        EncodedType(EncodedType), AtLoc(at), RParenLoc(rp) {}
+  ObjCEncodeExpr(QualType T, TypeSourceInfo *EncodedType, SourceLocation at,
+                 SourceLocation rp)
+      : Expr(ObjCEncodeExprClass, T, VK_LValue, OK_Ordinary),
+        EncodedType(EncodedType), AtLoc(at), RParenLoc(rp) {
+    setDependence(computeDependence(this));
+  }
 
   explicit ObjCEncodeExpr(EmptyShell Empty) : Expr(ObjCEncodeExprClass, Empty){}
 
@@ -456,11 +456,12 @@ class ObjCSelectorExpr : public Expr {
   SourceLocation AtLoc, RParenLoc;
 
 public:
-  ObjCSelectorExpr(QualType T, Selector selInfo,
-                   SourceLocation at, SourceLocation rp)
-      : Expr(ObjCSelectorExprClass, T, VK_RValue, OK_Ordinary, false, false,
-             false, false),
-        SelName(selInfo), AtLoc(at), RParenLoc(rp) {}
+  ObjCSelectorExpr(QualType T, Selector selInfo, SourceLocation at,
+                   SourceLocation rp)
+      : Expr(ObjCSelectorExprClass, T, VK_RValue, OK_Ordinary),
+        SelName(selInfo), AtLoc(at), RParenLoc(rp) {
+    setDependence(ExprDependence::None);
+  }
   explicit ObjCSelectorExpr(EmptyShell Empty)
       : Expr(ObjCSelectorExprClass, Empty) {}
 
@@ -508,11 +509,12 @@ class ObjCProtocolExpr : public Expr {
   friend class ASTStmtReader;
   friend class ASTStmtWriter;
 
-  ObjCProtocolExpr(QualType T, ObjCProtocolDecl *protocol,
-                 SourceLocation at, SourceLocation protoLoc, SourceLocation rp)
-      : Expr(ObjCProtocolExprClass, T, VK_RValue, OK_Ordinary, false, false,
-             false, false),
-        TheProtocol(protocol), AtLoc(at), ProtoLoc(protoLoc), RParenLoc(rp) {}
+  ObjCProtocolExpr(QualType T, ObjCProtocolDecl *protocol, SourceLocation at,
+                   SourceLocation protoLoc, SourceLocation rp)
+      : Expr(ObjCProtocolExprClass, T, VK_RValue, OK_Ordinary),
+        TheProtocol(protocol), AtLoc(at), ProtoLoc(protoLoc), RParenLoc(rp) {
+    setDependence(ExprDependence::None);
+  }
   explicit ObjCProtocolExpr(EmptyShell Empty)
       : Expr(ObjCProtocolExprClass, Empty) {}
 
@@ -558,17 +560,15 @@ class ObjCIvarRefExpr : public Expr {
   bool IsFreeIvar : 1;
 
 public:
-  ObjCIvarRefExpr(ObjCIvarDecl *d, QualType t,
-                  SourceLocation l, SourceLocation oploc,
-                  Expr *base,
-                  bool arrow = false, bool freeIvar = false)
+  ObjCIvarRefExpr(ObjCIvarDecl *d, QualType t, SourceLocation l,
+                  SourceLocation oploc, Expr *base, bool arrow = false,
+                  bool freeIvar = false)
       : Expr(ObjCIvarRefExprClass, t, VK_LValue,
-             d->isBitField() ? OK_BitField : OK_Ordinary,
-             /*TypeDependent=*/false, base->isValueDependent(),
-             base->isInstantiationDependent(),
-             base->containsUnexpandedParameterPack()),
+             d->isBitField() ? OK_BitField : OK_Ordinary),
         D(d), Base(base), Loc(l), OpLoc(oploc), IsArrow(arrow),
-        IsFreeIvar(freeIvar) {}
+        IsFreeIvar(freeIvar) {
+    setDependence(computeDependence(this));
+  }
 
   explicit ObjCIvarRefExpr(EmptyShell Empty)
       : Expr(ObjCIvarRefExprClass, Empty) {}
@@ -645,57 +645,53 @@ class ObjCPropertyRefExpr : public Expr {
   llvm::PointerUnion<Stmt *, const Type *, ObjCInterfaceDecl *> Receiver;
 
 public:
-  ObjCPropertyRefExpr(ObjCPropertyDecl *PD, QualType t,
-                      ExprValueKind VK, ExprObjectKind OK,
-                      SourceLocation l, Expr *base)
-      : Expr(ObjCPropertyRefExprClass, t, VK, OK,
-             /*TypeDependent=*/false, base->isValueDependent(),
-             base->isInstantiationDependent(),
-             base->containsUnexpandedParameterPack()),
-        PropertyOrGetter(PD, false), IdLoc(l), Receiver(base) {
+  ObjCPropertyRefExpr(ObjCPropertyDecl *PD, QualType t, ExprValueKind VK,
+                      ExprObjectKind OK, SourceLocation l, Expr *base)
+      : Expr(ObjCPropertyRefExprClass, t, VK, OK), PropertyOrGetter(PD, false),
+        IdLoc(l), Receiver(base) {
     assert(t->isSpecificPlaceholderType(BuiltinType::PseudoObject));
+    setDependence(computeDependence(this));
   }
 
-  ObjCPropertyRefExpr(ObjCPropertyDecl *PD, QualType t,
-                      ExprValueKind VK, ExprObjectKind OK,
-                      SourceLocation l, SourceLocation sl, QualType st)
-      : Expr(ObjCPropertyRefExprClass, t, VK, OK,
-             /*TypeDependent=*/false, false, st->isInstantiationDependentType(),
-             st->containsUnexpandedParameterPack()),
-        PropertyOrGetter(PD, false), IdLoc(l), ReceiverLoc(sl),
-        Receiver(st.getTypePtr()) {
+  ObjCPropertyRefExpr(ObjCPropertyDecl *PD, QualType t, ExprValueKind VK,
+                      ExprObjectKind OK, SourceLocation l, SourceLocation sl,
+                      QualType st)
+      : Expr(ObjCPropertyRefExprClass, t, VK, OK), PropertyOrGetter(PD, false),
+        IdLoc(l), ReceiverLoc(sl), Receiver(st.getTypePtr()) {
     assert(t->isSpecificPlaceholderType(BuiltinType::PseudoObject));
+    setDependence(computeDependence(this));
   }
 
   ObjCPropertyRefExpr(ObjCMethodDecl *Getter, ObjCMethodDecl *Setter,
                       QualType T, ExprValueKind VK, ExprObjectKind OK,
                       SourceLocation IdLoc, Expr *Base)
-      : Expr(ObjCPropertyRefExprClass, T, VK, OK, false,
-             Base->isValueDependent(), Base->isInstantiationDependent(),
-             Base->containsUnexpandedParameterPack()),
+      : Expr(ObjCPropertyRefExprClass, T, VK, OK),
         PropertyOrGetter(Getter, true), SetterAndMethodRefFlags(Setter, 0),
         IdLoc(IdLoc), Receiver(Base) {
     assert(T->isSpecificPlaceholderType(BuiltinType::PseudoObject));
+    setDependence(computeDependence(this));
   }
 
   ObjCPropertyRefExpr(ObjCMethodDecl *Getter, ObjCMethodDecl *Setter,
                       QualType T, ExprValueKind VK, ExprObjectKind OK,
-                      SourceLocation IdLoc,
-                      SourceLocation SuperLoc, QualType SuperTy)
-      : Expr(ObjCPropertyRefExprClass, T, VK, OK, false, false, false, false),
+                      SourceLocation IdLoc, SourceLocation SuperLoc,
+                      QualType SuperTy)
+      : Expr(ObjCPropertyRefExprClass, T, VK, OK),
         PropertyOrGetter(Getter, true), SetterAndMethodRefFlags(Setter, 0),
         IdLoc(IdLoc), ReceiverLoc(SuperLoc), Receiver(SuperTy.getTypePtr()) {
     assert(T->isSpecificPlaceholderType(BuiltinType::PseudoObject));
+    setDependence(computeDependence(this));
   }
 
   ObjCPropertyRefExpr(ObjCMethodDecl *Getter, ObjCMethodDecl *Setter,
                       QualType T, ExprValueKind VK, ExprObjectKind OK,
-                      SourceLocation IdLoc,
-                      SourceLocation ReceiverLoc, ObjCInterfaceDecl *Receiver)
-      : Expr(ObjCPropertyRefExprClass, T, VK, OK, false, false, false, false),
+                      SourceLocation IdLoc, SourceLocation ReceiverLoc,
+                      ObjCInterfaceDecl *Receiver)
+      : Expr(ObjCPropertyRefExprClass, T, VK, OK),
         PropertyOrGetter(Getter, true), SetterAndMethodRefFlags(Setter, 0),
         IdLoc(IdLoc), ReceiverLoc(ReceiverLoc), Receiver(Receiver) {
     assert(T->isSpecificPlaceholderType(BuiltinType::PseudoObject));
+    setDependence(computeDependence(this));
   }
 
   explicit ObjCPropertyRefExpr(EmptyShell Empty)
@@ -859,20 +855,14 @@ class ObjCSubscriptRefExpr : public Expr {
   ObjCMethodDecl *SetAtIndexMethodDecl;
 
 public:
-  ObjCSubscriptRefExpr(Expr *base, Expr *key, QualType T,
-                       ExprValueKind VK, ExprObjectKind OK,
-                       ObjCMethodDecl *getMethod,
+  ObjCSubscriptRefExpr(Expr *base, Expr *key, QualType T, ExprValueKind VK,
+                       ExprObjectKind OK, ObjCMethodDecl *getMethod,
                        ObjCMethodDecl *setMethod, SourceLocation RB)
-      : Expr(ObjCSubscriptRefExprClass, T, VK, OK,
-             base->isTypeDependent() || key->isTypeDependent(),
-             base->isValueDependent() || key->isValueDependent(),
-             (base->isInstantiationDependent() ||
-              key->isInstantiationDependent()),
-             (base->containsUnexpandedParameterPack() ||
-              key->containsUnexpandedParameterPack())),
-        RBracket(RB), GetAtIndexMethodDecl(getMethod),
-        SetAtIndexMethodDecl(setMethod) {
-    SubExprs[BASE] = base; SubExprs[KEY] = key;
+      : Expr(ObjCSubscriptRefExprClass, T, VK, OK), RBracket(RB),
+        GetAtIndexMethodDecl(getMethod), SetAtIndexMethodDecl(setMethod) {
+    SubExprs[BASE] = base;
+    SubExprs[KEY] = key;
+    setDependence(computeDependence(this));
   }
 
   explicit ObjCSubscriptRefExpr(EmptyShell Empty)
@@ -1505,11 +1495,10 @@ class ObjCIsaExpr : public Expr {
 public:
   ObjCIsaExpr(Expr *base, bool isarrow, SourceLocation l, SourceLocation oploc,
               QualType ty)
-      : Expr(ObjCIsaExprClass, ty, VK_LValue, OK_Ordinary,
-             /*TypeDependent=*/false, base->isValueDependent(),
-             base->isInstantiationDependent(),
-             /*ContainsUnexpandedParameterPack=*/false),
-        Base(base), IsaMemberLoc(l), OpLoc(oploc), IsArrow(isarrow) {}
+      : Expr(ObjCIsaExprClass, ty, VK_LValue, OK_Ordinary), Base(base),
+        IsaMemberLoc(l), OpLoc(oploc), IsArrow(isarrow) {
+    setDependence(computeDependence(this));
+  }
 
   /// Build an empty expression.
   explicit ObjCIsaExpr(EmptyShell Empty) : Expr(ObjCIsaExprClass, Empty) {}
@@ -1591,12 +1580,10 @@ class ObjCIndirectCopyRestoreExpr : public Expr {
 
 public:
   ObjCIndirectCopyRestoreExpr(Expr *operand, QualType type, bool shouldCopy)
-      : Expr(ObjCIndirectCopyRestoreExprClass, type, VK_LValue, OK_Ordinary,
-             operand->isTypeDependent(), operand->isValueDependent(),
-             operand->isInstantiationDependent(),
-             operand->containsUnexpandedParameterPack()),
+      : Expr(ObjCIndirectCopyRestoreExprClass, type, VK_LValue, OK_Ordinary),
         Operand(operand) {
     setShouldCopy(shouldCopy);
+    setDependence(computeDependence(this));
   }
 
   Expr *getSubExpr() { return cast<Expr>(Operand); }
@@ -1705,9 +1692,10 @@ class ObjCAvailabilityCheckExpr : public Expr {
 public:
   ObjCAvailabilityCheckExpr(VersionTuple VersionToCheck, SourceLocation AtLoc,
                             SourceLocation RParen, QualType Ty)
-      : Expr(ObjCAvailabilityCheckExprClass, Ty, VK_RValue, OK_Ordinary, false,
-             false, false, false),
-        VersionToCheck(VersionToCheck), AtLoc(AtLoc), RParen(RParen) {}
+      : Expr(ObjCAvailabilityCheckExprClass, Ty, VK_RValue, OK_Ordinary),
+        VersionToCheck(VersionToCheck), AtLoc(AtLoc), RParen(RParen) {
+    setDependence(ExprDependence::None);
+  }
 
   explicit ObjCAvailabilityCheckExpr(EmptyShell Shell)
       : Expr(ObjCAvailabilityCheckExprClass, Shell) {}
diff --git a/clang/include/clang/AST/ExprOpenMP.h b/clang/include/clang/AST/ExprOpenMP.h
index 5607d2d1dc588..f971ed8457bcd 100644
--- a/clang/include/clang/AST/ExprOpenMP.h
+++ b/clang/include/clang/AST/ExprOpenMP.h
@@ -13,6 +13,7 @@
 #ifndef LLVM_CLANG_AST_EXPROPENMP_H
 #define LLVM_CLANG_AST_EXPROPENMP_H
 
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/Expr.h"
 
 namespace clang {
@@ -51,24 +52,12 @@ class OMPArraySectionExpr : public Expr {
   OMPArraySectionExpr(Expr *Base, Expr *LowerBound, Expr *Length, QualType Type,
                       ExprValueKind VK, ExprObjectKind OK,
                       SourceLocation ColonLoc, SourceLocation RBracketLoc)
-      : Expr(
-            OMPArraySectionExprClass, Type, VK, OK,
-            Base->isTypeDependent() ||
-                (LowerBound && LowerBound->isTypeDependent()) ||
-                (Length && Length->isTypeDependent()),
-            Base->isValueDependent() ||
-                (LowerBound && LowerBound->isValueDependent()) ||
-                (Length && Length->isValueDependent()),
-            Base->isInstantiationDependent() ||
-                (LowerBound && LowerBound->isInstantiationDependent()) ||
-                (Length && Length->isInstantiationDependent()),
-            Base->containsUnexpandedParameterPack() ||
-                (LowerBound && LowerBound->containsUnexpandedParameterPack()) ||
-                (Length && Length->containsUnexpandedParameterPack())),
-        ColonLoc(ColonLoc), RBracketLoc(RBracketLoc) {
+      : Expr(OMPArraySectionExprClass, Type, VK, OK), ColonLoc(ColonLoc),
+        RBracketLoc(RBracketLoc) {
     SubExprs[BASE] = Base;
     SubExprs[LOWER_BOUND] = LowerBound;
     SubExprs[LENGTH] = Length;
+    setDependence(computeDependence(this));
   }
 
   /// Create an empty array section expression.
diff --git a/clang/include/clang/AST/GlobalDecl.h b/clang/include/clang/AST/GlobalDecl.h
index d2b5566a4cfa8..bf30d9b942357 100644
--- a/clang/include/clang/AST/GlobalDecl.h
+++ b/clang/include/clang/AST/GlobalDecl.h
@@ -68,7 +68,15 @@ class GlobalDecl {
   GlobalDecl(const VarDecl *D) { Init(D);}
   GlobalDecl(const FunctionDecl *D, unsigned MVIndex = 0)
       : MultiVersionIndex(MVIndex) {
-    Init(D);
+    if (!D->hasAttr<CUDAGlobalAttr>()) {
+      Init(D);
+      return;
+    }
+    Value.setPointerAndInt(D, unsigned(getDefaultKernelReference(D)));
+  }
+  GlobalDecl(const FunctionDecl *D, KernelReferenceKind Kind)
+      : Value(D, unsigned(Kind)) {
+    assert(D->hasAttr<CUDAGlobalAttr>() && "Decl is not a GPU kernel!");
   }
   GlobalDecl(const NamedDecl *D) { Init(D); }
   GlobalDecl(const BlockDecl *D) { Init(D); }
@@ -80,10 +88,6 @@ class GlobalDecl {
   GlobalDecl(const CXXDestructorDecl *D, CXXDtorType Type) : Value(D, Type) {}
   GlobalDecl(const VarDecl *D, DynamicInitKind StubKind)
       : Value(D, unsigned(StubKind)) {}
-  GlobalDecl(const FunctionDecl *D, KernelReferenceKind Kind)
-      : Value(D, unsigned(Kind)) {
-    assert(D->hasAttr<CUDAGlobalAttr>() && "Decl is not a GPU kernel!");
-  }
 
   GlobalDecl getCanonicalDecl() const {
     GlobalDecl CanonGD;
@@ -145,10 +149,10 @@ class GlobalDecl {
     return GD;
   }
 
-  static GlobalDecl getDefaultKernelReference(const FunctionDecl *D) {
-    return GlobalDecl(D, D->getASTContext().getLangOpts().CUDAIsDevice
-                             ? KernelReferenceKind::Kernel
-                             : KernelReferenceKind::Stub);
+  static KernelReferenceKind getDefaultKernelReference(const FunctionDecl *D) {
+    return D->getASTContext().getLangOpts().CUDAIsDevice
+               ? KernelReferenceKind::Kernel
+               : KernelReferenceKind::Stub;
   }
 
   GlobalDecl getWithDecl(const Decl *D) {
diff --git a/clang/include/clang/AST/NestedNameSpecifier.h b/clang/include/clang/AST/NestedNameSpecifier.h
index e465c33e2cc5f..47f5268c938b5 100644
--- a/clang/include/clang/AST/NestedNameSpecifier.h
+++ b/clang/include/clang/AST/NestedNameSpecifier.h
@@ -14,7 +14,7 @@
 #ifndef LLVM_CLANG_AST_NESTEDNAMESPECIFIER_H
 #define LLVM_CLANG_AST_NESTEDNAMESPECIFIER_H
 
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/SourceLocation.h"
 #include "llvm/ADT/FoldingSet.h"
diff --git a/clang/include/clang/AST/OpenMPClause.h b/clang/include/clang/AST/OpenMPClause.h
index 086c6a232de7a..e82a5f09a32d1 100644
--- a/clang/include/clang/AST/OpenMPClause.h
+++ b/clang/include/clang/AST/OpenMPClause.h
@@ -4433,6 +4433,12 @@ class OMPDeviceClause : public OMPClause, public OMPClauseWithPreInit {
   /// Location of '('.
   SourceLocation LParenLoc;
 
+  /// Device clause modifier.
+  OpenMPDeviceClauseModifier Modifier = OMPC_DEVICE_unknown;
+
+  /// Location of the modifier.
+  SourceLocation ModifierLoc;
+
   /// Device number.
   Stmt *Device = nullptr;
 
@@ -4441,20 +4447,30 @@ class OMPDeviceClause : public OMPClause, public OMPClauseWithPreInit {
   /// \param E Device number.
   void setDevice(Expr *E) { Device = E; }
 
+  /// Sets modifier.
+  void setModifier(OpenMPDeviceClauseModifier M) { Modifier = M; }
+
+  /// Setst modifier location.
+  void setModifierLoc(SourceLocation Loc) { ModifierLoc = Loc; }
+
 public:
   /// Build 'device' clause.
   ///
+  /// \param Modifier Clause modifier.
   /// \param E Expression associated with this clause.
   /// \param CaptureRegion Innermost OpenMP region where expressions in this
   /// clause must be captured.
   /// \param StartLoc Starting location of the clause.
+  /// \param ModifierLoc Modifier location.
   /// \param LParenLoc Location of '('.
   /// \param EndLoc Ending location of the clause.
-  OMPDeviceClause(Expr *E, Stmt *HelperE, OpenMPDirectiveKind CaptureRegion,
-                  SourceLocation StartLoc, SourceLocation LParenLoc,
+  OMPDeviceClause(OpenMPDeviceClauseModifier Modifier, Expr *E, Stmt *HelperE,
+                  OpenMPDirectiveKind CaptureRegion, SourceLocation StartLoc,
+                  SourceLocation LParenLoc, SourceLocation ModifierLoc,
                   SourceLocation EndLoc)
       : OMPClause(OMPC_device, StartLoc, EndLoc), OMPClauseWithPreInit(this),
-        LParenLoc(LParenLoc), Device(E) {
+        LParenLoc(LParenLoc), Modifier(Modifier), ModifierLoc(ModifierLoc),
+        Device(E) {
     setPreInitStmt(HelperE, CaptureRegion);
   }
 
@@ -4475,6 +4491,12 @@ class OMPDeviceClause : public OMPClause, public OMPClauseWithPreInit {
   /// Return device number.
   Expr *getDevice() const { return cast<Expr>(Device); }
 
+  /// Gets modifier.
+  OpenMPDeviceClauseModifier getModifier() const { return Modifier; }
+
+  /// Gets modifier location.
+  SourceLocation getModifierLoc() const { return ModifierLoc; }
+
   child_range children() { return child_range(&Device, &Device + 1); }
 
   const_child_range children() const {
@@ -6827,6 +6849,68 @@ class OMPDestroyClause final : public OMPClause {
   }
 };
 
+/// This represents 'detach' clause in the '#pragma omp task' directive.
+///
+/// \code
+/// #pragma omp task detach(evt)
+/// \endcode
+/// In this example directive '#pragma omp detach' has simple 'detach' clause
+/// with the variable 'evt'.
+class OMPDetachClause final : public OMPClause {
+  friend class OMPClauseReader;
+
+  /// Location of '('.
+  SourceLocation LParenLoc;
+
+  /// Expression of the 'detach' clause.
+  Stmt *Evt = nullptr;
+
+  /// Set condition.
+  void setEventHandler(Expr *E) { Evt = E; }
+
+  /// Sets the location of '('.
+  void setLParenLoc(SourceLocation Loc) { LParenLoc = Loc; }
+
+public:
+  /// Build 'detach' clause with event-handler \a Evt.
+  ///
+  /// \param Evt Event handler expression.
+  /// \param StartLoc Starting location of the clause.
+  /// \param LParenLoc Location of '('.
+  /// \param EndLoc Ending location of the clause.
+  OMPDetachClause(Expr *Evt, SourceLocation StartLoc, SourceLocation LParenLoc,
+                  SourceLocation EndLoc)
+      : OMPClause(OMPC_detach, StartLoc, EndLoc), LParenLoc(LParenLoc),
+        Evt(Evt) {}
+
+  /// Build an empty clause.
+  OMPDetachClause()
+      : OMPClause(OMPC_detach, SourceLocation(), SourceLocation()) {}
+
+  /// Returns the location of '('.
+  SourceLocation getLParenLoc() const { return LParenLoc; }
+
+  /// Returns event-handler expression.
+  Expr *getEventHandler() const { return cast_or_null<Expr>(Evt); }
+
+  child_range children() { return child_range(&Evt, &Evt + 1); }
+
+  const_child_range children() const {
+    return const_child_range(&Evt, &Evt + 1);
+  }
+
+  child_range used_children() {
+    return child_range(child_iterator(), child_iterator());
+  }
+  const_child_range used_children() const {
+    return const_child_range(const_child_iterator(), const_child_iterator());
+  }
+
+  static bool classof(const OMPClause *T) {
+    return T->getClauseKind() == OMPC_detach;
+  }
+};
+
 /// This class implements a simple visitor for OMPClause
 /// subclasses.
 template<class ImplClass, template <typename> class Ptr, typename RetTy>
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index ce66eeef7a82e..27a0bc774184a 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3488,6 +3488,12 @@ bool RecursiveASTVisitor<Derived>::VisitOMPOrderClause(OMPOrderClause *) {
   return true;
 }
 
+template <typename Derived>
+bool RecursiveASTVisitor<Derived>::VisitOMPDetachClause(OMPDetachClause *C) {
+  TRY_TO(TraverseStmt(C->getEventHandler()));
+  return true;
+}
+
 // FIXME: look at the following tricky-seeming exprs to see if we
 // need to recurse on anything.  These are ones that have methods
 // returning decls or qualtypes or nestednamespecifier -- though I'm
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index d0efad03e42fc..87e1d7f26a168 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -14,7 +14,7 @@
 #define LLVM_CLANG_AST_STMT_H
 
 #include "clang/AST/DeclGroup.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/StmtIterator.h"
 #include "clang/Basic/CapturedStmt.h"
 #include "clang/Basic/IdentifierTable.h"
diff --git a/clang/include/clang/AST/TemplateBase.h b/clang/include/clang/AST/TemplateBase.h
index e5fd1ca9dd461..a8529dc2cf54c 100644
--- a/clang/include/clang/AST/TemplateBase.h
+++ b/clang/include/clang/AST/TemplateBase.h
@@ -14,7 +14,7 @@
 #ifndef LLVM_CLANG_AST_TEMPLATEBASE_H
 #define LLVM_CLANG_AST_TEMPLATEBASE_H
 
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/NestedNameSpecifier.h"
 #include "clang/AST/TemplateName.h"
 #include "clang/AST/Type.h"
@@ -669,6 +669,9 @@ struct alignas(void *) ASTTemplateKWAndArgsInfo {
   void initializeFrom(SourceLocation TemplateKWLoc,
                       const TemplateArgumentListInfo &List,
                       TemplateArgumentLoc *OutArgArray);
+  // FIXME: The parameter Deps is the result populated by this method, the
+  // caller doesn't need it since it is populated by computeDependence. remove
+  // it.
   void initializeFrom(SourceLocation TemplateKWLoc,
                       const TemplateArgumentListInfo &List,
                       TemplateArgumentLoc *OutArgArray,
diff --git a/clang/include/clang/AST/TemplateName.h b/clang/include/clang/AST/TemplateName.h
index bf917788477f7..9bcf2838dcf13 100644
--- a/clang/include/clang/AST/TemplateName.h
+++ b/clang/include/clang/AST/TemplateName.h
@@ -13,7 +13,7 @@
 #ifndef LLVM_CLANG_AST_TEMPLATENAME_H
 #define LLVM_CLANG_AST_TEMPLATENAME_H
 
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/NestedNameSpecifier.h"
 #include "clang/Basic/LLVM.h"
 #include "llvm/ADT/FoldingSet.h"
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index a241d372bd627..66722873477b7 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -17,7 +17,7 @@
 #ifndef LLVM_CLANG_AST_TYPE_H
 #define LLVM_CLANG_AST_TYPE_H
 
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/NestedNameSpecifier.h"
 #include "clang/AST/TemplateName.h"
 #include "clang/Basic/AddressSpaces.h"
diff --git a/clang/include/clang/Basic/AArch64SVEACLETypes.def b/clang/include/clang/Basic/AArch64SVEACLETypes.def
index 7d387587dc297..afa651841861c 100644
--- a/clang/include/clang/Basic/AArch64SVEACLETypes.def
+++ b/clang/include/clang/Basic/AArch64SVEACLETypes.def
@@ -38,32 +38,32 @@
 //===----------------------------------------------------------------------===//
 
 #ifndef SVE_VECTOR_TYPE
-#define SVE_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, IsSigned, IsFP)\
+#define SVE_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP) \
   SVE_TYPE(Name, Id, SingletonId)
 #endif
 
 #ifndef SVE_PREDICATE_TYPE
-#define SVE_PREDICATE_TYPE(Name, Id, SingletonId, ElKind)\
+#define SVE_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)\
   SVE_TYPE(Name, Id, SingletonId)
 #endif
 
 //===- Vector point types -----------------------------------------------===//
 
-SVE_VECTOR_TYPE("__SVInt8_t",  SveInt8, SveInt8Ty, SveElSInt8, 8, true, false)
-SVE_VECTOR_TYPE("__SVInt16_t", SveInt16, SveInt16Ty, SveElSInt16, 16, true, false)
-SVE_VECTOR_TYPE("__SVInt32_t", SveInt32, SveInt32Ty, SveElSInt32, 32, true, false)
-SVE_VECTOR_TYPE("__SVInt64_t", SveInt64, SveInt64Ty, SveElSInt64, 64, true, false)
+SVE_VECTOR_TYPE("__SVInt8_t",  SveInt8, SveInt8Ty, 16, 8, true, false)
+SVE_VECTOR_TYPE("__SVInt16_t", SveInt16, SveInt16Ty, 8, 16, true, false)
+SVE_VECTOR_TYPE("__SVInt32_t", SveInt32, SveInt32Ty, 4, 32, true, false)
+SVE_VECTOR_TYPE("__SVInt64_t", SveInt64, SveInt64Ty, 2, 64, true, false)
 
-SVE_VECTOR_TYPE("__SVUint8_t",  SveUint8, SveUint8Ty, SveElUInt8, 8, false, false)
-SVE_VECTOR_TYPE("__SVUint16_t", SveUint16, SveUint16Ty, SveElUInt16, 16, false, false)
-SVE_VECTOR_TYPE("__SVUint32_t", SveUint32, SveUint32Ty, SveElUInt32, 32, false, false)
-SVE_VECTOR_TYPE("__SVUint64_t", SveUint64, SveUint64Ty, SveElUInt64, 64, false, false)
+SVE_VECTOR_TYPE("__SVUint8_t",  SveUint8, SveUint8Ty, 16, 8, false, false)
+SVE_VECTOR_TYPE("__SVUint16_t", SveUint16, SveUint16Ty, 8, 16, false, false)
+SVE_VECTOR_TYPE("__SVUint32_t", SveUint32, SveUint32Ty, 4, 32, false, false)
+SVE_VECTOR_TYPE("__SVUint64_t", SveUint64, SveUint64Ty, 2, 64, false, false)
 
-SVE_VECTOR_TYPE("__SVFloat16_t", SveFloat16, SveFloat16Ty, SveElHalf, 16, true, true)
-SVE_VECTOR_TYPE("__SVFloat32_t", SveFloat32, SveFloat32Ty, SveElFloat, 32, true, true)
-SVE_VECTOR_TYPE("__SVFloat64_t", SveFloat64, SveFloat64Ty, SveElDouble, 64, true, true)
+SVE_VECTOR_TYPE("__SVFloat16_t", SveFloat16, SveFloat16Ty, 8, 16, true, true)
+SVE_VECTOR_TYPE("__SVFloat32_t", SveFloat32, SveFloat32Ty, 4, 32, true, true)
+SVE_VECTOR_TYPE("__SVFloat64_t", SveFloat64, SveFloat64Ty, 2, 64, true, true)
 
-SVE_PREDICATE_TYPE("__SVBool_t", SveBool, SveBoolTy, SveElBool)
+SVE_PREDICATE_TYPE("__SVBool_t", SveBool, SveBoolTy, 16)
 
 #undef SVE_VECTOR_TYPE
 #undef SVE_PREDICATE_TYPE
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index a063a652b66b2..0e3921cdf23c7 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3703,6 +3703,12 @@ def Uninitialized : InheritableAttr {
   let Documentation = [UninitializedDocs];
 }
 
+def LoaderUninitialized : Attr {
+  let Spellings = [Clang<"loader_uninitialized">];
+  let Subjects = SubjectList<[GlobalVar]>;
+  let Documentation = [LoaderUninitializedDocs];
+}
+
 def ObjCExternallyRetained : InheritableAttr {
   let LangOpts = [ObjCAutoRefCount];
   let Spellings = [Clang<"objc_externally_retained">];
diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td
index a529db68be88d..08280730b7d32 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -4720,6 +4720,29 @@ it rather documents the programmer's intent.
   }];
 }
 
+def LoaderUninitializedDocs : Documentation {
+  let Category = DocCatVariable;
+  let Content = [{
+The ``loader_uninitialized`` attribute can be placed on global variables to
+indicate that the variable does not need to be zero initialized by the loader.
+On most targets, zero-initialization does not incur any additional cost.
+For example, most general purpose operating systems deliberately ensure
+that all memory is properly initialized in order to avoid leaking privileged
+information from the kernel or other programs. However, some targets
+do not make this guarantee, and on these targets, avoiding an unnecessary
+zero-initialization can have a significant impact on load times and/or code
+size.
+
+A declaration with this attribute is a non-tentative definition just as if it
+provided an initializer. Variables with this attribute are considered to be
+uninitialized in the same sense as a local variable, and the programs must
+write to them before reading from them. If the variable's type is a C++ class
+type with a non-trivial default constructor, or an array thereof, this attribute
+only suppresses the static zero-initialization of the variable, not the dynamic
+initialization provided by executing the default constructor.
+  }];
+}
+
 def CallbackDocs : Documentation {
   let Category = DocCatFunction;
   let Content = [{
diff --git a/clang/include/clang/Basic/Builtins.def b/clang/include/clang/Basic/Builtins.def
index cc19c403a0cd7..0aa11fa6ac177 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -36,6 +36,7 @@
 //  a -> __builtin_va_list
 //  A -> "reference" to __builtin_va_list
 //  V -> Vector, followed by the number of elements and the base type.
+//  q -> Scalable vector, followed by the number of elements and the base type.
 //  E -> ext_vector, followed by the number of elements and the base type.
 //  X -> _Complex, followed by the base type.
 //  Y -> ptrdiff_t
diff --git a/clang/include/clang/Basic/BuiltinsSVE.def b/clang/include/clang/Basic/BuiltinsSVE.def
new file mode 100644
index 0000000000000..2839ca992d98c
--- /dev/null
+++ b/clang/include/clang/Basic/BuiltinsSVE.def
@@ -0,0 +1,20 @@
+//===--- BuiltinsSVE.def - SVE Builtin function database --------*- C++ -*-===//
+//
+//  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+//  See https://llvm.org/LICENSE.txt for license information.
+//  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the SVE-specific builtin function database.  Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+// The format of this database matches clang/Basic/Builtins.def.
+
+#define GET_SVE_BUILTINS
+#include "clang/Basic/arm_sve_builtins.inc"
+#undef GET_SVE_BUILTINS
+
+#undef BUILTIN
diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt
index ea011a8af177f..5eda48e8f250b 100644
--- a/clang/include/clang/Basic/CMakeLists.txt
+++ b/clang/include/clang/Basic/CMakeLists.txt
@@ -60,7 +60,15 @@ clang_tablegen(arm_mve_builtin_sema.inc -gen-arm-mve-builtin-sema
 clang_tablegen(arm_mve_builtin_aliases.inc -gen-arm-mve-builtin-aliases
   SOURCE arm_mve.td
   TARGET ClangARMMveBuiltinAliases)
-
+clang_tablegen(arm_sve_builtins.inc -gen-arm-sve-builtins
+  SOURCE arm_sve.td
+  TARGET ClangARMSveBuiltins)
+clang_tablegen(arm_sve_builtin_cg.inc -gen-arm-sve-builtin-codegen
+  SOURCE arm_sve.td
+  TARGET ClangARMSveBuiltinCG)
+clang_tablegen(arm_sve_typeflags.inc -gen-arm-sve-typeflags
+  SOURCE arm_sve.td
+  TARGET ClangARMSveTypeFlags)
 clang_tablegen(arm_cde_builtins.inc -gen-arm-cde-builtin-def
   SOURCE arm_cde.td
   TARGET ClangARMCdeBuiltinsDef)
diff --git a/clang/include/clang/Basic/DiagnosticASTKinds.td b/clang/include/clang/Basic/DiagnosticASTKinds.td
index 48bafeeff2085..544573edffdf8 100644
--- a/clang/include/clang/Basic/DiagnosticASTKinds.td
+++ b/clang/include/clang/Basic/DiagnosticASTKinds.td
@@ -186,6 +186,9 @@ def note_constexpr_access_inactive_union_member : Note<
   "construction of subobject of|destruction of}0 "
   "member %1 of union with %select{active member %3|no active member}2 "
   "is not allowed in a constant expression">;
+def note_constexpr_union_member_change_during_init : Note<
+  "assignment would change active union member during the initialization of "
+  "a different member of the same union">;
 def note_constexpr_access_static_temporary : Note<
   "%select{read of|read of|assignment to|increment of|decrement of|"
   "member call on|dynamic_cast of|typeid applied to|reconstruction of|"
diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td
index 190e82b5f7bb1..0a1d6668ec293 100644
--- a/clang/include/clang/Basic/DiagnosticParseKinds.td
+++ b/clang/include/clang/Basic/DiagnosticParseKinds.td
@@ -26,8 +26,6 @@ def err_msasm_unable_to_create_target : Error<
   "MS-style inline assembly is not available: %0">;
 def err_gnu_inline_asm_disabled : Error<
   "GNU-style inline assembly is disabled">;
-def err_asm_goto_cannot_have_output : Error<
-  "'asm goto' cannot have output constraints">;
 def err_asm_duplicate_qual : Error<"duplicate asm qualifier '%0'">;
 }
 
@@ -181,9 +179,6 @@ def err_unparenthesized_non_primary_expr_in_requires_clause : Error<
   "parentheses are required around this expression in a requires clause">;
 def note_unparenthesized_non_primary_expr_in_requires_clause : Note<
   "parentheses are required around this expression in a requires clause">;
-def err_potential_function_call_in_constraint_logical_or : Error<
-  "function call must be parenthesized to be considered part of the requires "
-  "clause">;
 
 def err_expected_fn_body : Error<
   "expected function body after function declarator">;
@@ -211,7 +206,6 @@ def err_invalid_token_after_declarator_suggest_equal : Error<
   "invalid %0 at end of declaration; did you mean '='?">;
 def err_expected_statement : Error<"expected statement">;
 def err_expected_lparen_after : Error<"expected '(' after '%0'">;
-def err_expected_lbrace_after : Error<"expected '{' after '%0'">;
 def err_expected_rparen_after : Error<"expected ')' after '%0'">;
 def err_expected_punc : Error<"expected ')' or ',' after '%0'">;
 def err_expected_less_after : Error<"expected '<' after '%0'">;
@@ -744,17 +738,10 @@ def err_friend_explicit_instantiation : Error<
 def err_explicit_instantiation_enum : Error<
   "enumerations cannot be explicitly instantiated">;
 def err_expected_template_parameter : Error<"expected template parameter">;
-def note_ill_formed_requires_expression_outside_template : Note<
-  "requires expression outside a template declaration may not contain invalid "
-  "types or expressions">;
 def err_empty_requires_expr : Error<
   "a requires expression must contain at least one requirement">;
 def err_requires_expr_parameter_list_ellipsis : Error<
   "varargs not allowed in requires expression">;
-def err_requires_expr_type_req_illegal_identifier : Error<
-  "expected identifier or template-id in type requirement">;
-def err_requires_expr_type_req_template_args_on_non_template : Error<
-  "template arguments provided for non-template '%0'">;
 def err_expected_semi_requirement : Error<
   "expected ';' at end of requirement">;
 def err_requires_expr_missing_arrow : Error<
@@ -764,9 +751,6 @@ def err_requires_expr_expected_type_constraint : Error<
 def err_requires_expr_simple_requirement_noexcept : Error<
   "'noexcept' can only be used in a compound requirement (with '{' '}' around "
   "the expression)">;
-def err_requires_expr_simple_requirement_unexpected_tok : Error<
-  "unexpected %0 after expression; did you intend to use a compound "
-  "requirement (with '{' '}' around the expression)?">;
 def warn_requires_expr_in_simple_requirement : Warning<
   "this requires expression will only be checked for syntactic validity; did "
   "you intend to place it in a nested requirement? (add another 'requires' "
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index ee28f08d27871..7c7e62e385921 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -1568,6 +1568,9 @@ def err_distant_exception_spec : Error<
 def err_incomplete_in_exception_spec : Error<
   "%select{|pointer to |reference to }0incomplete type %1 is not allowed "
   "in exception specification">;
+def err_sizeless_in_exception_spec : Error<
+  "%select{|reference to }0sizeless type %1 is not allowed "
+  "in exception specification">;
 def ext_incomplete_in_exception_spec : ExtWarn<err_incomplete_in_exception_spec.Text>,
   InGroup<MicrosoftExceptionSpec>;
 def err_rref_in_exception_spec : Error<
@@ -1976,9 +1979,6 @@ def note_destructor_nontype_here : Note<
 def ext_dtor_named_in_wrong_scope : Extension<
   "ISO C++ requires the name after '::~' to be found in the same scope as "
   "the name before '::~'">, InGroup<DtorName>;
-def ext_dtor_name_missing_template_arguments : Extension<
-  "ISO C++ requires template argument list in destructor name">,
-  InGroup<DtorName>;
 def ext_qualified_dtor_named_in_lexical_scope : ExtWarn<
   "qualified destructor name only found in lexical scope; omit the qualifier "
   "to find this type name by unqualified lookup">, InGroup<DtorName>;
@@ -2678,8 +2678,6 @@ def err_concept_extra_headers : Error<
   "extraneous template parameter list in concept definition">;
 def err_concept_no_associated_constraints : Error<
   "concept cannot have associated constraints">;
-def err_concept_not_implemented : Error<
-  "sorry, unimplemented concepts feature %0 used">;
 def err_non_constant_constraint_expression : Error<
   "substitution into constraint expression resulted in a non-constant "
   "expression">;
@@ -2688,8 +2686,6 @@ def err_non_bool_atomic_constraint : Error<
 def err_template_arg_list_constraints_not_satisfied : Error<
   "constraints not satisfied for %select{class template|function template|variable template|alias template|"
   "template template parameter|template}0 %1%2">;
-def note_constraints_not_satisfied : Note<
-  "constraints not satisfied">;
 def note_substituted_constraint_expr_is_ill_formed : Note<
   "because substituted constraint expression is ill-formed%0">;
 def note_atomic_constraint_evaluated_to_false : Note<
@@ -2706,11 +2702,6 @@ def err_trailing_requires_clause_on_deduction_guide : Error<
   "deduction guide cannot have a requires clause">;
 def err_reference_to_function_with_unsatisfied_constraints : Error<
   "invalid reference to function %0: constraints not satisfied">;
-def note_requires_expr_ill_formed_expr : Note<
-  "expression is invalid: %0">;
-def note_requires_expr_no_implicit_conversion : Note<
-  "no implicit conversion exists between expression type %0 and expected type "
-  "%1">;
 def err_requires_expr_local_parameter_default_argument : Error<
   "default arguments not allowed for parameters of a requires expression">;
 def err_requires_expr_parameter_referenced_in_evaluated_context : Error<
@@ -2733,12 +2724,6 @@ def note_type_requirement_substitution_error : Note<
   "%select{and|because}0 '%1' would be invalid: %2">;
 def note_type_requirement_unknown_substitution_error : Note<
   "%select{and|because}0 '%1' would be invalid">;
-def err_type_requirement_non_type_template : Error<
-  "'%0' refers to a %select{class template|function template|"
-  "variable template|alias template|template template parameter|template}1, "
-  "not a type template">;
-def err_type_requirement_no_such_type : Error<
-  "'%0' does not name a type">;
 def note_nested_requirement_substitution_error : Note<
   "%select{and|because}0 '%1' would be invalid: %2">;
 def note_nested_requirement_unknown_substitution_error : Note<
@@ -5389,6 +5374,17 @@ def ext_aggregate_init_not_constant : Extension<
   "initializer for aggregate is not a compile-time constant">, InGroup<C99>;
 def err_local_cant_init : Error<
   "'__local' variable cannot have an initializer">;
+def err_loader_uninitialized_cant_init
+    : Error<"variable with 'loader_uninitialized' attribute cannot have an "
+            "initializer">;
+def err_loader_uninitialized_trivial_ctor
+    : Error<"variable with 'loader_uninitialized' attribute must have a "
+            "trivial default constructor">;
+def err_loader_uninitialized_redeclaration
+    : Error<"redeclaration cannot add 'loader_uninitialized' attribute">;
+def err_loader_uninitialized_extern_decl
+    : Error<"variable %0 cannot be declared both 'extern' and with the "
+            "'loader_uninitialized' attribute">;
 def err_block_extern_cant_init : Error<
   "'extern' variable cannot have an initializer">;
 def warn_extern_init : Warning<"'extern' variable has an initializer">,
@@ -6167,8 +6163,8 @@ def err_typecheck_subscript_not_integer : Error<
   "array subscript is not an integer">;
 def err_subscript_function_type : Error<
   "subscript of pointer to function type %0">;
-def err_subscript_incomplete_type : Error<
-  "subscript of pointer to incomplete type %0">;
+def err_subscript_incomplete_or_sizeless_type : Error<
+  "subscript of pointer to %select{incomplete|sizeless}0 type %1">;
 def err_dereference_incomplete_type : Error<
   "dereference of pointer to incomplete type %0">;
 def ext_gnu_subscript_void_type : Extension<
@@ -6278,8 +6274,8 @@ def err_typecheck_illegal_increment_decrement : Error<
   "cannot %select{decrement|increment}1 value of type %0">;
 def err_typecheck_expect_int : Error<
   "used type %0 where integer is required">;
-def err_typecheck_arithmetic_incomplete_type : Error<
-  "arithmetic on a pointer to an incomplete type %0">;
+def err_typecheck_arithmetic_incomplete_or_sizeless_type : Error<
+  "arithmetic on a pointer to %select{an incomplete|sizeless}0 type %1">;
 def err_typecheck_pointer_arith_function_type : Error<
   "arithmetic on%select{ a|}0 pointer%select{|s}0 to%select{ the|}2 "
   "function type%select{|s}2 %1%select{| and %3}2">;
@@ -6935,8 +6931,8 @@ def err_array_new_needs_size : Error<
   "array size must be specified in new expression with no initializer">;
 def err_bad_new_type : Error<
   "cannot allocate %select{function|reference}1 type %0 with new">;
-def err_new_incomplete_type : Error<
-  "allocation of incomplete type %0">;
+def err_new_incomplete_or_sizeless_type : Error<
+  "allocation of %select{incomplete|sizeless}0 type %1">;
 def err_new_array_nonconst : Error<
   "only the first dimension of an allocated array may have dynamic size">;
 def err_new_array_size_unknown_from_init : Error<
@@ -7053,6 +7049,8 @@ def err_catch_incomplete_ptr : Error<
 def err_catch_incomplete_ref : Error<
   "cannot catch reference to incomplete type %0">;
 def err_catch_incomplete : Error<"cannot catch incomplete type %0">;
+def err_catch_sizeless : Error<
+  "cannot catch %select{|reference to }0sizeless type %1">;
 def err_catch_rvalue_ref : Error<"cannot catch exceptions by rvalue reference">;
 def err_catch_variably_modified : Error<
   "cannot catch variably modified type %0">;
@@ -7158,6 +7156,8 @@ def err_throw_incomplete : Error<
   "cannot throw object of incomplete type %0">;
 def err_throw_incomplete_ptr : Error<
   "cannot throw pointer to object of incomplete type %0">;
+def err_throw_sizeless : Error<
+  "cannot throw object of sizeless type %0">;
 def warn_throw_underaligned_obj : Warning<
   "underaligned exception object thrown">,
   InGroup<UnderalignedExceptionObject>;
@@ -9273,12 +9273,6 @@ def err_x86_builtin_invalid_rounding : Error<
   "invalid rounding argument">;
 def err_x86_builtin_invalid_scale : Error<
   "scale argument must be 1, 2, 4, or 8">;
-def err_hexagon_builtin_unsupported_cpu : Error<
-  "builtin is not supported on this CPU">;
-def err_hexagon_builtin_requires_hvx : Error<
-  "builtin requires HVX">;
-def err_hexagon_builtin_unsupported_hvx : Error<
-  "builtin is not supported on this version of HVX">;
 
 def err_builtin_target_unsupported : Error<
   "builtin is not supported on this target">;
@@ -10010,9 +10004,9 @@ def err_omp_wrong_ordered_loop_count : Error<
   "the parameter of the 'ordered' clause must be greater than or equal to the parameter of the 'collapse' clause">;
 def note_collapse_loop_count : Note<
   "parameter of the 'collapse' clause">;
-def err_omp_grainsize_num_tasks_mutually_exclusive : Error<
+def err_omp_clauses_mutually_exclusive : Error<
   "'%0' and '%1' clause are mutually exclusive and may not appear on the same directive">;
-def note_omp_previous_grainsize_num_tasks : Note<
+def note_omp_previous_clause : Note<
   "'%0' clause is specified here">;
 def err_omp_hint_clause_no_name : Error<
   "the name of the construct must be specified in presence of 'hint' clause">;
@@ -10184,6 +10178,8 @@ def note_omp_flush_order_clause_here : Note<
 def err_omp_non_lvalue_in_map_or_motion_clauses: Error<
   "expected addressable lvalue in '%0' clause"
   >;
+def err_omp_event_var_expected : Error<
+  "expected variable of the 'omp_event_handle_t' type%select{|, not %1}0">;
 } // end of OpenMP category
 
 let CategoryName = "Related Result Type Issue" in {
diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def
index 9ff8283702970..c3d6d0822580f 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -176,6 +176,7 @@ VALUE_LANGOPT(PackStruct  , 32, 0,
 VALUE_LANGOPT(MaxTypeAlign  , 32, 0,
               "default maximum alignment for types")
 VALUE_LANGOPT(AlignDouble            , 1, 0, "Controls if doubles should be aligned to 8 bytes (x86 only)")
+VALUE_LANGOPT(DoubleSize            , 32, 0, "width of double")
 VALUE_LANGOPT(LongDoubleSize        , 32, 0, "width of long double")
 LANGOPT(PPCIEEELongDouble            , 1, 0, "use IEEE 754 quadruple-precision for long double")
 COMPATIBLE_VALUE_LANGOPT(PICLevel    , 2, 0, "__PIC__ level")
diff --git a/clang/include/clang/Basic/OpenMPKinds.def b/clang/include/clang/Basic/OpenMPKinds.def
index 70f962427e36c..0488dad6706b5 100644
--- a/clang/include/clang/Basic/OpenMPKinds.def
+++ b/clang/include/clang/Basic/OpenMPKinds.def
@@ -212,6 +212,9 @@
 #ifndef OPENMP_DEPOBJ_CLAUSE
 #define OPENMP_DEPOBJ_CLAUSE(Name)
 #endif
+#ifndef OPENMP_DEVICE_MODIFIER
+#define OPENMP_DEVICE_MODIFIER(Name)
+#endif
 
 // OpenMP clauses.
 OPENMP_CLAUSE(allocator, OMPAllocatorClause)
@@ -277,6 +280,7 @@ OPENMP_CLAUSE(nontemporal, OMPNontemporalClause)
 OPENMP_CLAUSE(order, OMPOrderClause)
 OPENMP_CLAUSE(depobj, OMPDepobjClause)
 OPENMP_CLAUSE(destroy, OMPDestroyClause)
+OPENMP_CLAUSE(detach, OMPDetachClause)
 
 // Clauses allowed for OpenMP directive 'parallel'.
 OPENMP_PARALLEL_CLAUSE(if)
@@ -365,6 +369,10 @@ OPENMP_SCHEDULE_MODIFIER(monotonic)
 OPENMP_SCHEDULE_MODIFIER(nonmonotonic)
 OPENMP_SCHEDULE_MODIFIER(simd)
 
+// Modifiers for 'device' clause.
+OPENMP_DEVICE_MODIFIER(ancestor)
+OPENMP_DEVICE_MODIFIER(device_num)
+
 // Static attributes for 'defaultmap' clause.
 OPENMP_DEFAULTMAP_KIND(scalar)
 OPENMP_DEFAULTMAP_KIND(aggregate)
@@ -471,6 +479,7 @@ OPENMP_TASK_CLAUSE(depend)
 OPENMP_TASK_CLAUSE(priority)
 OPENMP_TASK_CLAUSE(in_reduction)
 OPENMP_TASK_CLAUSE(allocate)
+OPENMP_TASK_CLAUSE(detach)
 
 // Clauses allowed for OpenMP directive 'atomic'.
 OPENMP_ATOMIC_CLAUSE(read)
@@ -1089,6 +1098,7 @@ OPENMP_DEPOBJ_CLAUSE(depend)
 OPENMP_DEPOBJ_CLAUSE(destroy)
 OPENMP_DEPOBJ_CLAUSE(update)
 
+#undef OPENMP_DEVICE_MODIFIER
 #undef OPENMP_DEPOBJ_CLAUSE
 #undef OPENMP_FLUSH_CLAUSE
 #undef OPENMP_ORDER_KIND
diff --git a/clang/include/clang/Basic/OpenMPKinds.h b/clang/include/clang/Basic/OpenMPKinds.h
index 43196663c45f6..46eeffe999d91 100644
--- a/clang/include/clang/Basic/OpenMPKinds.h
+++ b/clang/include/clang/Basic/OpenMPKinds.h
@@ -51,6 +51,13 @@ enum OpenMPScheduleClauseModifier {
   OMPC_SCHEDULE_MODIFIER_last
 };
 
+/// OpenMP modifiers for 'device' clause.
+enum OpenMPDeviceClauseModifier {
+#define OPENMP_DEVICE_MODIFIER(Name) OMPC_DEVICE_##Name,
+#include "clang/Basic/OpenMPKinds.def"
+  OMPC_DEVICE_unknown,
+};
+
 /// OpenMP attributes for 'depend' clause.
 enum OpenMPDependClauseKind {
 #define OPENMP_DEPEND_KIND(Name) \
diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h
index 0e2f0753b0c59..fd339ef34e1e4 100644
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -41,11 +41,22 @@ namespace clang {
     };
   }
 
+  namespace SVE {
+  enum {
+    LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
+#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+#include "clang/Basic/BuiltinsSVE.def"
+    FirstTSBuiltin,
+  };
+  }
+
   /// AArch64 builtins
   namespace AArch64 {
   enum {
     LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
     LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
+    FirstSVEBuiltin = NEON::FirstTSBuiltin,
+    LastSVEBuiltin = SVE::FirstTSBuiltin - 1,
   #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
   #include "clang/Basic/BuiltinsAArch64.def"
     LastTSBuiltin
@@ -149,6 +160,44 @@ namespace clang {
     bool isQuad() const { return (Flags & QuadFlag) != 0; }
   };
 
+  /// Flags to identify the types for overloaded SVE builtins.
+  class SVETypeFlags {
+    uint64_t Flags;
+
+  public:
+#define LLVM_GET_SVE_TYPEFLAGS
+#include "clang/Basic/arm_sve_typeflags.inc"
+#undef LLVM_GET_SVE_TYPEFLAGS
+
+    enum EltType {
+#define LLVM_GET_SVE_ELTTYPES
+#include "clang/Basic/arm_sve_typeflags.inc"
+#undef LLVM_GET_SVE_ELTTYPES
+    };
+
+    enum MemEltType {
+#define LLVM_GET_SVE_MEMELTTYPES
+#include "clang/Basic/arm_sve_typeflags.inc"
+#undef LLVM_GET_SVE_MEMELTTYPES
+    };
+
+    SVETypeFlags(uint64_t F) : Flags(F) {}
+    SVETypeFlags(EltType ET, bool IsUnsigned) : Flags(ET) {}
+
+    EltType getEltType() const {
+      return (EltType)((Flags & EltTypeMask) - FirstEltType);
+    }
+
+    MemEltType getMemEltType() const {
+      return (MemEltType)((Flags & MemEltTypeMask) - FirstMemEltType);
+    }
+
+    bool isLoad() const { return Flags & IsLoad; }
+
+    uint64_t getBits() const { return Flags; }
+    bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
+  };
+
   /// Hexagon builtins
   namespace Hexagon {
     enum {
diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td
index d2203d6503010..45e45899de5f0 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -202,6 +202,67 @@ let params = T.Float in {
   defm vfms: FMA<0>;
 }
 
+let params = T.Int, pnt = PNT_NType in {
+  def vmlaq_n: Intrinsic<
+    Vector, (args Vector:$addend, Vector:$m1, unpromoted<Scalar>:$m2_s),
+    (add (mul $m1, (splat $m2_s)), $addend)>;
+  def vmlasq_n: Intrinsic<
+    Vector, (args Vector:$m1, Vector:$m2, unpromoted<Scalar>:$addend_s),
+    (add (mul $m1, $m2), (splat $addend_s))>;
+
+  def vmlaq_m_n: Intrinsic<
+    Vector, (args Vector:$addend, Vector:$m1, Scalar:$m2_s, Predicate:$pred),
+    (IRInt<"vmla_n_predicated", [Vector, Predicate]>
+        $addend, $m1, $m2_s, $pred)>;
+  def vmlasq_m_n: Intrinsic<
+    Vector, (args Vector:$m1, Vector:$m2, Scalar:$addend_s, Predicate:$pred),
+    (IRInt<"vmlas_n_predicated", [Vector, Predicate]>
+        $m1, $m2, $addend_s, $pred)>;
+}
+
+multiclass VQDMLA {
+  def hq_n: Intrinsic<
+    Vector, (args Vector:$addend, Vector:$m1, Scalar:$m2_s),
+    (IRInt<NAME # "h", [Vector]> $addend, $m1, $m2_s)>;
+  def shq_n: Intrinsic<
+    Vector, (args Vector:$m1, Vector:$m2, Scalar:$addend_s),
+    (IRInt<NAME # "sh", [Vector]> $m1, $m2, $addend_s)>;
+
+  def hq_m_n: Intrinsic<
+    Vector, (args Vector:$addend, Vector:$m1, Scalar:$m2_s, Predicate:$pred),
+    (IRInt<NAME # "h_predicated", [Vector, Predicate]>
+         $addend, $m1, $m2_s, $pred)>;
+  def shq_m_n: Intrinsic<
+    Vector, (args Vector:$m1, Vector:$m2, Scalar:$addend_s, Predicate:$pred),
+    (IRInt<NAME # "sh_predicated", [Vector, Predicate]>
+         $m1, $m2, $addend_s, $pred)>;
+}
+
+let params = T.Signed, pnt = PNT_NType in {
+  defm vqdmla: VQDMLA;
+  defm vqrdmla: VQDMLA;
+}
+
+multiclass VQDMLAD<int exchange, int round, int subtract> {
+  def "": Intrinsic<Vector, (args Vector:$a, Vector:$b, Vector:$c),
+       (IRInt<"vqdmlad", [Vector]> $a, $b, $c,
+            (u32 exchange), (u32 round), (u32 subtract))>;
+  def _m: Intrinsic<Vector, (args Vector:$a, Vector:$b, Vector:$c,
+                                  Predicate:$pred),
+       (IRInt<"vqdmlad_predicated", [Vector, Predicate]> $a, $b, $c,
+            (u32 exchange), (u32 round), (u32 subtract), $pred)>;
+}
+let params = T.Signed in {
+  defm vqdmladhq:   VQDMLAD<0, 0, 0>;
+  defm vqdmladhxq:  VQDMLAD<1, 0, 0>;
+  defm vqdmlsdhq:   VQDMLAD<0, 0, 1>;
+  defm vqdmlsdhxq:  VQDMLAD<1, 0, 1>;
+  defm vqrdmladhq:  VQDMLAD<0, 1, 0>;
+  defm vqrdmladhxq: VQDMLAD<1, 1, 0>;
+  defm vqrdmlsdhq:  VQDMLAD<0, 1, 1>;
+  defm vqrdmlsdhxq: VQDMLAD<1, 1, 1>;
+}
+
 let params = !listconcat(T.Int16, T.Int32) in {
   let pnt = PNT_None in {
     def vmvnq_n: Intrinsic<Vector, (args imm_simd_vmvn:$imm),
diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
new file mode 100644
index 0000000000000..012f639527c70
--- /dev/null
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -0,0 +1,139 @@
+//===--- arm_sve.td - ARM SVE compiler interface ------------------------===//
+//
+//  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+//  See https://llvm.org/LICENSE.txt for license information.
+//  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file defines the TableGen definitions from which the ARM SVE header
+//  file will be generated.  See:
+//
+//      https://developer.arm.com/architectures/system-architectures/software-standards/acle
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction definitions
+//===----------------------------------------------------------------------===//
+// Every intrinsic subclasses "Inst". An intrinsic has a name, a prototype and
+// a sequence of typespecs.
+//
+// The name is the base name of the intrinsic, for example "svld1". This is
+// then mangled by the tblgen backend to add type information ("svld1_s16").
+//
+// A typespec is a sequence of uppercase characters (modifiers) followed by one
+// lowercase character. A typespec encodes a particular "base type" of the
+// intrinsic.
+//
+// An example typespec is "Us" - unsigned short - svuint16_t. The available
+// typespec codes are given below.
+//
+// The string given to an Inst class is a sequence of typespecs. The intrinsic
+// is instantiated for every typespec in the sequence. For example "sdUsUd".
+//
+// The prototype is a string that defines the return type of the intrinsic
+// and the type of each argument. The return type and every argument gets a
+// "modifier" that can change in some way the "base type" of the intrinsic.
+//
+// The modifier 'd' means "default" and does not modify the base type in any
+// way. The available modifiers are given below.
+//
+// Typespecs
+// ---------
+// c: char
+// s: short
+// i: int
+// l: long
+// f: float
+// h: half-float
+// d: double
+
+// Typespec modifiers
+// ------------------
+// P: boolean
+// U: unsigned
+
+// Prototype modifiers
+// -------------------
+// prototype: return (arg, arg, ...)
+//
+// d: default
+// c: const pointer type
+// P: predicate type
+
+class MergeType<int val> {
+  int Value = val;
+}
+def MergeNone    : MergeType<0>;
+def MergeAny     : MergeType<1>;
+def MergeOp1     : MergeType<2>;
+def MergeZero    : MergeType<3>;
+def MergeAnyExp  : MergeType<4>; // Use merged builtin with explicit
+def MergeZeroExp : MergeType<5>; // generation of its inactive argument.
+
+class EltType<int val> {
+  int Value = val;
+}
+def EltTyInvalid : EltType<0>;
+def EltTyInt8    : EltType<1>;
+def EltTyInt16   : EltType<2>;
+def EltTyInt32   : EltType<3>;
+def EltTyInt64   : EltType<4>;
+def EltTyFloat16 : EltType<5>;
+def EltTyFloat32 : EltType<6>;
+def EltTyFloat64 : EltType<7>;
+def EltTyBool8   : EltType<8>;
+def EltTyBool16  : EltType<9>;
+def EltTyBool32  : EltType<10>;
+def EltTyBool64  : EltType<11>;
+
+class MemEltType<int val> {
+  int Value = val;
+}
+def MemEltTyDefault   : MemEltType<0>;
+def MemEltTyInt8      : MemEltType<1>;
+def MemEltTyInt16     : MemEltType<2>;
+def MemEltTyInt32     : MemEltType<3>;
+def MemEltTyInt64     : MemEltType<4>;
+
+class FlagType<int val> {
+  int Value = val;
+}
+
+// These must be kept in sync with the flags in utils/TableGen/SveEmitter.h
+// and include/clang/Basic/TargetBuiltins.h
+def NoFlags                   : FlagType<0x00000000>;
+def FirstEltType              : FlagType<0x00000001>;
+//      :                                     :
+//      :                                     :
+def EltTypeMask               : FlagType<0x0000000f>;
+def FirstMemEltType           : FlagType<0x00000010>;
+//      :                                     :
+//      :                                     :
+def MemEltTypeMask            : FlagType<0x00000070>;
+def IsLoad                    : FlagType<0x00000080>;
+
+// Every intrinsic subclasses Inst.
+class Inst<string n, string p, string t, MergeType mt, string i,
+           list<FlagType> ft, MemEltType met> {
+  string Name = n;
+  string Prototype = p;
+  string Types = t;
+  string ArchGuard = "";
+  int Merge = mt.Value;
+  string LLVMIntrinsic = i;
+  list<FlagType> Flags = ft;
+  int MemEltType = met.Value;
+}
+
+// MInst: Instructions which access memory
+class MInst<string n, string p, string t, list<FlagType> f,
+            MemEltType met=MemEltTyDefault, string i="">
+  : Inst<n, p, t, MergeNone, i, f, met> {}
+
+////////////////////////////////////////////////////////////////////////////////
+// Loads
+
+// Load one vector (scalar base)
+def SVLD1   : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>;
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 2131d3a47f843..563a894d5439c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2236,6 +2236,8 @@ def mbranches_within_32B_boundaries : Flag<["-"], "mbranches-within-32B-boundari
 def mfancy_math_387 : Flag<["-"], "mfancy-math-387">, Group<clang_ignored_m_Group>;
 def mlong_calls : Flag<["-"], "mlong-calls">, Group<m_Group>,
   HelpText<"Generate branches with extended addressability, usually via indirect jumps.">;
+def mdouble_EQ : Joined<["-"], "mdouble=">, Group<m_Group>, Values<"32,64">, Flags<[CC1Option]>,
+  HelpText<"Force double to be 32 bits or 64 bits">;
 def LongDouble_Group : OptionGroup<"<LongDouble group>">, Group<m_Group>,
   DocName<"Long double flags">,
   DocBrief<[{Selects the long double implementation}]>;
diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h
index 903a9dae9b289..f62f2a3fee40a 100644
--- a/clang/include/clang/Parse/Parser.h
+++ b/clang/include/clang/Parse/Parser.h
@@ -3038,11 +3038,13 @@ class Parser : public CodeCompletionHandler {
   /// Parses clause with a single expression and an additional argument
   /// of a kind \a Kind.
   ///
+  /// \param DKind Directive kind.
   /// \param Kind Kind of current clause.
   /// \param ParseOnly true to skip the clause's semantic actions and return
   /// nullptr.
   ///
-  OMPClause *ParseOpenMPSingleExprWithArgClause(OpenMPClauseKind Kind,
+  OMPClause *ParseOpenMPSingleExprWithArgClause(OpenMPDirectiveKind DKind,
+                                                OpenMPClauseKind Kind,
                                                 bool ParseOnly);
   /// Parses clause without any additional arguments.
   ///
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 8019459e03639..04ac17bccf855 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -7129,7 +7129,8 @@ class Sema final {
                           QualType ObjectType, bool EnteringContext,
                           bool &MemberOfUnknownSpecialization,
                           SourceLocation TemplateKWLoc = SourceLocation(),
-                          AssumedTemplateKind *ATK = nullptr);
+                          AssumedTemplateKind *ATK = nullptr,
+                          bool Disambiguation = false);
 
   TemplateNameKind isTemplateName(Scope *S,
                                   CXXScopeSpec &SS,
@@ -7138,7 +7139,8 @@ class Sema final {
                                   ParsedType ObjectType,
                                   bool EnteringContext,
                                   TemplateTy &Template,
-                                  bool &MemberOfUnknownSpecialization);
+                                  bool &MemberOfUnknownSpecialization,
+                                  bool Disambiguation = false);
 
   /// Try to resolve an undeclared template name as a type template.
   ///
@@ -10520,6 +10522,10 @@ class Sema final {
   OMPClause *ActOnOpenMPHintClause(Expr *Hint, SourceLocation StartLoc,
                                    SourceLocation LParenLoc,
                                    SourceLocation EndLoc);
+  /// Called on well-formed 'detach' clause.
+  OMPClause *ActOnOpenMPDetachClause(Expr *Evt, SourceLocation StartLoc,
+                                     SourceLocation LParenLoc,
+                                     SourceLocation EndLoc);
 
   OMPClause *ActOnOpenMPSimpleClause(OpenMPClauseKind Kind,
                                      unsigned Argument,
@@ -10728,8 +10734,10 @@ class Sema final {
                           SourceLocation StartLoc, SourceLocation LParenLoc,
                           SourceLocation EndLoc);
   /// Called on well-formed 'device' clause.
-  OMPClause *ActOnOpenMPDeviceClause(Expr *Device, SourceLocation StartLoc,
+  OMPClause *ActOnOpenMPDeviceClause(OpenMPDeviceClauseModifier Modifier,
+                                     Expr *Device, SourceLocation StartLoc,
                                      SourceLocation LParenLoc,
+                                     SourceLocation ModifierLoc,
                                      SourceLocation EndLoc);
   /// Called on well-formed 'map' clause.
   OMPClause *
diff --git a/clang/include/clang/Tooling/Syntax/Nodes.h b/clang/include/clang/Tooling/Syntax/Nodes.h
index 25acc1757428c..82fcac33f99bd 100644
--- a/clang/include/clang/Tooling/Syntax/Nodes.h
+++ b/clang/include/clang/Tooling/Syntax/Nodes.h
@@ -38,10 +38,10 @@ enum class NodeKind : uint16_t {
   Leaf,
   TranslationUnit,
 
-  // Expressions
+  // Expressions.
   UnknownExpression,
 
-  // Statements
+  // Statements.
   UnknownStatement,
   DeclarationStatement,
   EmptyStatement,
@@ -58,7 +58,7 @@ enum class NodeKind : uint16_t {
   ExpressionStatement,
   CompoundStatement,
 
-  // Declarations
+  // Declarations.
   UnknownDeclaration,
   EmptyDeclaration,
   StaticAssertDeclaration,
@@ -68,7 +68,16 @@ enum class NodeKind : uint16_t {
   NamespaceAliasDefinition,
   UsingNamespaceDirective,
   UsingDeclaration,
-  TypeAliasDeclaration
+  TypeAliasDeclaration,
+
+  // Declarators.
+  SimpleDeclarator,
+  ParenDeclarator,
+
+  ArraySubscript,
+  TrailingReturnType,
+  ParametersAndQualifiers,
+  MemberPointer
 };
 /// For debugging purposes.
 llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, NodeKind K);
@@ -101,11 +110,19 @@ enum class NodeRole : uint8_t {
   ExpressionStatement_expression,
   CompoundStatement_statement,
   StaticAssertDeclaration_condition,
-  StaticAssertDeclaration_message
+  StaticAssertDeclaration_message,
+  SimpleDeclaration_declarator,
+  ArraySubscript_sizeExpression,
+  TrailingReturnType_arrow,
+  TrailingReturnType_declarator,
+  ParametersAndQualifiers_parameter,
+  ParametersAndQualifiers_trailingReturn
 };
 /// For debugging purposes.
 llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, NodeRole R);
 
+class SimpleDeclarator;
+
 /// A root node for a translation unit. Parent is always null.
 class TranslationUnit final : public Tree {
 public:
@@ -375,6 +392,8 @@ class SimpleDeclaration final : public Declaration {
   static bool classof(const Node *N) {
     return N->kind() == NodeKind::SimpleDeclaration;
   }
+  /// FIXME: use custom iterator instead of 'vector'.
+  std::vector<syntax::SimpleDeclarator *> declarators();
 };
 
 /// namespace <name> { <decls> }
@@ -424,6 +443,113 @@ class TypeAliasDeclaration final : public Declaration {
   }
 };
 
+/// Covers a name, an initializer and a part of the type outside declaration
+/// specifiers. Examples are:
+///     `*a` in `int *a`
+///     `a[10]` in `int a[10]`
+///     `*a = nullptr` in `int *a = nullptr`
+/// Declarators can be unnamed too:
+///     `**` in `new int**`
+///     `* = nullptr` in `void foo(int* = nullptr)`
+/// Most declarators you encounter are instances of SimpleDeclarator. They may
+/// contain an inner declarator inside parentheses, we represent it as
+/// ParenDeclarator. E.g.
+///     `(*a)` in `int (*a) = 10`
+class Declarator : public Tree {
+public:
+  Declarator(NodeKind K) : Tree(K) {}
+  static bool classof(const Node *N) {
+    return NodeKind::SimpleDeclarator <= N->kind() &&
+           N->kind() <= NodeKind::ParenDeclarator;
+  }
+};
+
+/// A top-level declarator without parentheses. See comment of Declarator for
+/// more details.
+class SimpleDeclarator final : public Declarator {
+public:
+  SimpleDeclarator() : Declarator(NodeKind::SimpleDeclarator) {}
+  static bool classof(const Node *N) {
+    return N->kind() == NodeKind::SimpleDeclarator;
+  }
+};
+
+/// Declarator inside parentheses.
+/// E.g. `(***a)` from `int (***a) = nullptr;`
+/// See comment of Declarator for more details.
+class ParenDeclarator final : public Declarator {
+public:
+  ParenDeclarator() : Declarator(NodeKind::ParenDeclarator) {}
+  static bool classof(const Node *N) {
+    return N->kind() == NodeKind::ParenDeclarator;
+  }
+  syntax::Leaf *lparen();
+  syntax::Leaf *rparen();
+};
+
+/// Array size specified inside a declarator.
+/// E.g:
+///   `[10]` in `int a[10];`
+///   `[static 10]` in `void f(int xs[static 10]);`
+class ArraySubscript final : public Tree {
+public:
+  ArraySubscript() : Tree(NodeKind::ArraySubscript) {}
+  static bool classof(const Node *N) {
+    return N->kind() == NodeKind::ArraySubscript;
+  }
+  // TODO: add an accessor for the "static" keyword.
+  syntax::Leaf *lbracket();
+  syntax::Expression *sizeExpression();
+  syntax::Leaf *rbracket();
+};
+
+/// Trailing return type after the parameter list, including the arrow token.
+/// E.g. `-> int***`.
+class TrailingReturnType final : public Tree {
+public:
+  TrailingReturnType() : Tree(NodeKind::TrailingReturnType) {}
+  static bool classof(const Node *N) {
+    return N->kind() == NodeKind::TrailingReturnType;
+  }
+  // TODO: add accessors for specifiers.
+  syntax::Leaf *arrow();
+  syntax::SimpleDeclarator *declarator();
+};
+
+/// Parameter list for a function type and a trailing return type, if the
+/// function has one.
+/// E.g.:
+///  `(int a) volatile ` in `int foo(int a) volatile;`
+///  `(int a) &&` in `int foo(int a) &&;`
+///  `() -> int` in `auto foo() -> int;`
+///  `() const` in `int foo() const;`
+///  `() noexcept` in `int foo() noexcept;`
+///  `() throw()` in `int foo() throw();`
+///
+/// (!) override doesn't belong here.
+class ParametersAndQualifiers final : public Tree {
+public:
+  ParametersAndQualifiers() : Tree(NodeKind::ParametersAndQualifiers) {}
+  static bool classof(const Node *N) {
+    return N->kind() == NodeKind::ParametersAndQualifiers;
+  }
+  syntax::Leaf *lparen();
+  /// FIXME: use custom iterator instead of 'vector'.
+  std::vector<syntax::SimpleDeclaration *> parameters();
+  syntax::Leaf *rparen();
+  syntax::TrailingReturnType *trailingReturn();
+};
+
+/// Member pointer inside a declarator
+/// E.g. `X::*` in `int X::* a = 0;`
+class MemberPointer final : public Tree {
+public:
+  MemberPointer() : Tree(NodeKind::MemberPointer) {}
+  static bool classof(const Node *N) {
+    return N->kind() == NodeKind::MemberPointer;
+  }
+};
+
 } // namespace syntax
 } // namespace clang
 #endif
diff --git a/clang/include/clang/module.modulemap b/clang/include/clang/module.modulemap
index af1322acc289f..15f891c153401 100644
--- a/clang/include/clang/module.modulemap
+++ b/clang/include/clang/module.modulemap
@@ -45,6 +45,7 @@ module Clang_Basic {
   textual header "Basic/BuiltinsNEON.def"
   textual header "Basic/BuiltinsNVPTX.def"
   textual header "Basic/BuiltinsPPC.def"
+  textual header "Basic/BuiltinsSVE.def"
   textual header "Basic/BuiltinsSystemZ.def"
   textual header "Basic/BuiltinsWebAssembly.def"
   textual header "Basic/BuiltinsX86.def"
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index e3b830ed4e452..b4c24bbf30ec8 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -2105,16 +2105,16 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const {
     // Because the length is only known at runtime, we use a dummy value
     // of 0 for the static length.  The alignment values are those defined
     // by the Procedure Call Standard for the Arm Architecture.
-#define SVE_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, IsSigned, IsFP)\
-    case BuiltinType::Id: \
-      Width = 0; \
-      Align = 128; \
-      break;
-#define SVE_PREDICATE_TYPE(Name, Id, SingletonId, ElKind) \
-    case BuiltinType::Id: \
-      Width = 0; \
-      Align = 16; \
-      break;
+#define SVE_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP) \
+  case BuiltinType::Id:                                                        \
+    Width = 0;                                                                 \
+    Align = 128;                                                               \
+    break;
+#define SVE_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)                      \
+  case BuiltinType::Id:                                                        \
+    Width = 0;                                                                 \
+    Align = 16;                                                                \
+    break;
 #include "clang/Basic/AArch64SVEACLETypes.def"
     }
     break;
@@ -3589,6 +3589,28 @@ QualType ASTContext::getIncompleteArrayType(QualType elementType,
   return QualType(newType, 0);
 }
 
+/// getScalableVectorType - Return the unique reference to a scalable vector
+/// type of the specified element type and size. VectorType must be a built-in
+/// type.
+QualType ASTContext::getScalableVectorType(QualType EltTy,
+                                           unsigned NumElts) const {
+  if (Target->hasAArch64SVETypes()) {
+    uint64_t EltTySize = getTypeSize(EltTy);
+#define SVE_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP) \
+  if (!EltTy->isBooleanType() &&                                               \
+      ((EltTy->hasIntegerRepresentation() &&                                   \
+        EltTy->hasSignedIntegerRepresentation() == IsSigned) ||                \
+       (EltTy->hasFloatingRepresentation() && IsFP)) &&                        \
+      EltTySize == ElBits && NumElts == NumEls)                                \
+    return SingletonId;
+#define SVE_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)                      \
+  if (EltTy->isBooleanType() && NumElts == NumEls)                             \
+    return SingletonId;
+#include "clang/Basic/AArch64SVEACLETypes.def"
+  }
+  return QualType();
+}
+
 /// getVectorType - Return the unique reference to a vector type of
 /// the specified element type and size. VectorType must be a built-in type.
 QualType ASTContext::getVectorType(QualType vecType, unsigned NumElts,
@@ -9704,6 +9726,19 @@ static QualType DecodeTypeFromStr(const char *&Str, const ASTContext &Context,
     else
       Type = Context.getLValueReferenceType(Type);
     break;
+  case 'q': {
+    char *End;
+    unsigned NumElements = strtoul(Str, &End, 10);
+    assert(End != Str && "Missing vector size");
+    Str = End;
+
+    QualType ElementType = DecodeTypeFromStr(Str, Context, Error,
+                                             RequiresICE, false);
+    assert(!RequiresICE && "Can't require vector ICE");
+
+    Type = Context.getScalableVectorType(ElementType, NumElements);
+    break;
+  }
   case 'V': {
     char *End;
     unsigned NumElements = strtoul(Str, &End, 10);
diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp
index c135e95a3dd59..73622f22bcec5 100644
--- a/clang/lib/AST/ASTImporter.cpp
+++ b/clang/lib/AST/ASTImporter.cpp
@@ -6340,16 +6340,13 @@ ExpectedStmt ASTNodeImporter::VisitChooseExpr(ChooseExpr *E) {
   ExprValueKind VK = E->getValueKind();
   ExprObjectKind OK = E->getObjectKind();
 
-  bool TypeDependent = ToCond->isTypeDependent();
-  bool ValueDependent = ToCond->isValueDependent();
-
   // The value of CondIsTrue only matters if the value is not
   // condition-dependent.
   bool CondIsTrue = !E->isConditionDependent() && E->isConditionTrue();
 
   return new (Importer.getToContext())
       ChooseExpr(ToBuiltinLoc, ToCond, ToLHS, ToRHS, ToType, VK, OK,
-                 ToRParenLoc, CondIsTrue, TypeDependent, ValueDependent);
+                 ToRParenLoc, CondIsTrue);
 }
 
 ExpectedStmt ASTNodeImporter::VisitGNUNullExpr(GNUNullExpr *E) {
diff --git a/clang/lib/AST/CMakeLists.txt b/clang/lib/AST/CMakeLists.txt
index da7b808e4f519..6018d32af8f8f 100644
--- a/clang/lib/AST/CMakeLists.txt
+++ b/clang/lib/AST/CMakeLists.txt
@@ -32,6 +32,7 @@ add_clang_library(clangAST
   CommentParser.cpp
   CommentSema.cpp
   ComparisonCategories.cpp
+  ComputeDependence.cpp
   CXXInheritance.cpp
   DataCollection.cpp
   Decl.cpp
diff --git a/clang/lib/AST/ComputeDependence.cpp b/clang/lib/AST/ComputeDependence.cpp
new file mode 100644
index 0000000000000..4ca4eacde8b77
--- /dev/null
+++ b/clang/lib/AST/ComputeDependence.cpp
@@ -0,0 +1,701 @@
+//===- ComputeDependence.cpp ----------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "clang/AST/ComputeDependence.h"
+#include "clang/AST/Attr.h"
+#include "clang/AST/DeclCXX.h"
+#include "clang/AST/DeclarationName.h"
+#include "clang/AST/DependenceFlags.h"
+#include "clang/AST/Expr.h"
+#include "clang/AST/ExprCXX.h"
+#include "clang/AST/ExprConcepts.h"
+#include "clang/AST/ExprObjC.h"
+#include "clang/AST/ExprOpenMP.h"
+#include "clang/Basic/ExceptionSpecificationType.h"
+#include "llvm/ADT/ArrayRef.h"
+
+using namespace clang;
+
+ExprDependence clang::computeDependence(FullExpr *E) {
+  return E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(OpaqueValueExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence());
+  if (auto *S = E->getSourceExpr())
+    D |= S->getDependence();
+  assert(!(D & ExprDependence::UnexpandedPack));
+  return D;
+}
+
+ExprDependence clang::computeDependence(ParenExpr *E) {
+  return E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(UnaryOperator *E) {
+  return toExprDependence(E->getType()->getDependence()) |
+         E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(UnaryExprOrTypeTraitExpr *E) {
+  // Never type-dependent (C++ [temp.dep.expr]p3).
+  // Value-dependent if the argument is type-dependent.
+  if (E->isArgumentType())
+    return turnTypeToValueDependence(
+        toExprDependence(E->getArgumentType()->getDependence()));
+
+  auto ArgDeps = E->getArgumentExpr()->getDependence();
+  auto Deps = ArgDeps & ~ExprDependence::TypeValue;
+  // Value-dependent if the argument is type-dependent.
+  if (ArgDeps & ExprDependence::Type)
+    Deps |= ExprDependence::Value;
+  // Check to see if we are in the situation where alignof(decl) should be
+  // dependent because decl's alignment is dependent.
+  auto ExprKind = E->getKind();
+  if (ExprKind != UETT_AlignOf && ExprKind != UETT_PreferredAlignOf)
+    return Deps;
+  if ((Deps & ExprDependence::Value) && (Deps & ExprDependence::Instantiation))
+    return Deps;
+
+  auto *NoParens = E->getArgumentExpr()->IgnoreParens();
+  const ValueDecl *D = nullptr;
+  if (const auto *DRE = dyn_cast<DeclRefExpr>(NoParens))
+    D = DRE->getDecl();
+  else if (const auto *ME = dyn_cast<MemberExpr>(NoParens))
+    D = ME->getMemberDecl();
+  if (!D)
+    return Deps;
+  for (const auto *I : D->specific_attrs<AlignedAttr>()) {
+    if (I->isAlignmentDependent())
+      return Deps | ExprDependence::ValueInstantiation;
+  }
+  return Deps;
+}
+
+ExprDependence clang::computeDependence(ArraySubscriptExpr *E) {
+  return E->getLHS()->getDependence() | E->getRHS()->getDependence();
+}
+
+ExprDependence clang::computeDependence(CompoundLiteralExpr *E) {
+  return toExprDependence(E->getTypeSourceInfo()->getType()->getDependence()) |
+         turnTypeToValueDependence(E->getInitializer()->getDependence());
+}
+
+ExprDependence clang::computeDependence(CastExpr *E) {
+  // Cast expressions are type-dependent if the type is
+  // dependent (C++ [temp.dep.expr]p3).
+  // Cast expressions are value-dependent if the type is
+  // dependent or if the subexpression is value-dependent.
+  auto D = toExprDependence(E->getType()->getDependence());
+  if (E->getStmtClass() == Stmt::ImplicitCastExprClass) {
+    // An implicit cast expression doesn't (lexically) contain an
+    // unexpanded pack, even if its target type does.
+    D &= ~ExprDependence::UnexpandedPack;
+  }
+  if (auto *S = E->getSubExpr())
+    D |= S->getDependence() & ~ExprDependence::Type;
+  return D;
+}
+
+ExprDependence clang::computeDependence(BinaryOperator *E) {
+  return E->getLHS()->getDependence() | E->getRHS()->getDependence();
+}
+
+ExprDependence clang::computeDependence(ConditionalOperator *E) {
+  // The type of the conditional operator depends on the type of the conditional
+  // to support the GCC vector conditional extension. Additionally,
+  // [temp.dep.expr] does specify state that this should be dependent on ALL sub
+  // expressions.
+  return E->getCond()->getDependence() | E->getLHS()->getDependence() |
+         E->getRHS()->getDependence();
+}
+
+ExprDependence clang::computeDependence(BinaryConditionalOperator *E) {
+  return E->getCommon()->getDependence() | E->getFalseExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(StmtExpr *E, unsigned TemplateDepth) {
+  auto D = ExprDependence::None;
+  if (E->getType()->isDependentType())
+    D |= ExprDependence::Type;
+  // Note: we treat a statement-expression in a dependent context as always
+  // being value- and instantiation-dependent. This matches the behavior of
+  // lambda-expressions and GCC.
+  if (TemplateDepth)
+    D |= ExprDependence::ValueInstantiation;
+  return D;
+}
+
+ExprDependence clang::computeDependence(ConvertVectorExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence()) |
+           E->getSrcExpr()->getDependence();
+  if (!E->getType()->isDependentType())
+    D &= ~ExprDependence::Type;
+  return D;
+}
+
+ExprDependence clang::computeDependence(ChooseExpr *E) {
+  if (E->isConditionDependent())
+    return ExprDependence::TypeValueInstantiation |
+           E->getCond()->getDependence() | E->getLHS()->getDependence() |
+           E->getRHS()->getDependence();
+
+  auto Cond = E->getCond()->getDependence();
+  auto Active = E->getLHS()->getDependence();
+  auto Inactive = E->getRHS()->getDependence();
+  if (!E->isConditionTrue())
+    std::swap(Active, Inactive);
+  // Take type- and value- dependency from the active branch. Propagate all
+  // other flags from all branches.
+  return (Active & ExprDependence::TypeValue) |
+         ((Cond | Active | Inactive) & ~ExprDependence::TypeValue);
+}
+
+ExprDependence clang::computeDependence(ParenListExpr *P) {
+  auto D = ExprDependence::None;
+  for (auto *E : P->exprs())
+    D |= E->getDependence();
+  return D;
+}
+
+ExprDependence clang::computeDependence(VAArgExpr *E) {
+  auto D =
+      toExprDependence(E->getWrittenTypeInfo()->getType()->getDependence()) |
+      (E->getSubExpr()->getDependence() & ~ExprDependence::Type);
+  return D & ~ExprDependence::Value;
+}
+
+ExprDependence clang::computeDependence(NoInitExpr *E) {
+  return toExprDependence(E->getType()->getDependence()) &
+         ExprDependence::Instantiation;
+}
+
+ExprDependence clang::computeDependence(ArrayInitLoopExpr *E) {
+  auto D = E->getCommonExpr()->getDependence() |
+           E->getSubExpr()->getDependence() | ExprDependence::Instantiation;
+  if (!E->getType()->isInstantiationDependentType())
+    D &= ~ExprDependence::Instantiation;
+  return turnTypeToValueDependence(D);
+}
+
+ExprDependence clang::computeDependence(ImplicitValueInitExpr *E) {
+  return toExprDependence(E->getType()->getDependence()) &
+         ExprDependence::Instantiation;
+}
+
+ExprDependence clang::computeDependence(ExtVectorElementExpr *E) {
+  return E->getBase()->getDependence();
+}
+
+ExprDependence clang::computeDependence(BlockExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence());
+  if (E->getBlockDecl()->isDependentContext())
+    D |= ExprDependence::Instantiation;
+  return D & ~ExprDependence::UnexpandedPack;
+}
+
+ExprDependence clang::computeDependence(AsTypeExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence()) |
+           E->getSrcExpr()->getDependence();
+  if (!E->getType()->isDependentType())
+    D &= ~ExprDependence::Type;
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXRewrittenBinaryOperator *E) {
+  return E->getSemanticForm()->getDependence();
+}
+
+ExprDependence clang::computeDependence(CXXStdInitializerListExpr *E) {
+  auto D = turnTypeToValueDependence(E->getSubExpr()->getDependence());
+  if (E->getType()->isDependentType())
+    D |= ExprDependence::Type;
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXTypeidExpr *E) {
+  auto D = ExprDependence::None;
+  if (E->isTypeOperand())
+    D = toExprDependence(
+        E->getTypeOperandSourceInfo()->getType()->getDependence());
+  else
+    D = turnTypeToValueDependence(E->getExprOperand()->getDependence());
+  // typeid is never type-dependent (C++ [temp.dep.expr]p4)
+  return D & ~ExprDependence::Type;
+}
+
+ExprDependence clang::computeDependence(MSPropertyRefExpr *E) {
+  return E->getBaseExpr()->getDependence() & ~ExprDependence::Type;
+}
+
+ExprDependence clang::computeDependence(MSPropertySubscriptExpr *E) {
+  return E->getIdx()->getDependence();
+}
+
+ExprDependence clang::computeDependence(CXXUuidofExpr *E) {
+  if (E->isTypeOperand())
+    return turnTypeToValueDependence(toExprDependence(
+        E->getTypeOperandSourceInfo()->getType()->getDependence()));
+
+  return turnTypeToValueDependence(E->getExprOperand()->getDependence());
+}
+
+ExprDependence clang::computeDependence(CXXThisExpr *E) {
+  // 'this' is type-dependent if the class type of the enclosing
+  // member function is dependent (C++ [temp.dep.expr]p2)
+  auto D = toExprDependence(E->getType()->getDependence());
+  assert(!(D & ExprDependence::UnexpandedPack));
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXThrowExpr *E) {
+  auto *Op = E->getSubExpr();
+  if (!Op)
+    return ExprDependence::None;
+  return Op->getDependence() & ~ExprDependence::TypeValue;
+}
+
+ExprDependence clang::computeDependence(CXXBindTemporaryExpr *E) {
+  return E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(CXXScalarValueInitExpr *E) {
+  return toExprDependence(E->getType()->getDependence()) &
+         ~ExprDependence::TypeValue;
+}
+
+ExprDependence clang::computeDependence(CXXDeleteExpr *E) {
+  return turnTypeToValueDependence(E->getArgument()->getDependence());
+}
+
+ExprDependence clang::computeDependence(ArrayTypeTraitExpr *E) {
+  auto D = toExprDependence(E->getQueriedType()->getDependence());
+  if (auto *Dim = E->getDimensionExpression())
+    D |= Dim->getDependence();
+  return turnTypeToValueDependence(D);
+}
+
+ExprDependence clang::computeDependence(ExpressionTraitExpr *E) {
+  // Never type-dependent.
+  auto D = E->getQueriedExpression()->getDependence() & ~ExprDependence::Type;
+  // Value-dependent if the argument is type-dependent.
+  if (E->getQueriedExpression()->isTypeDependent())
+    D |= ExprDependence::Value;
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXNoexceptExpr *E, CanThrowResult CT) {
+  auto D = E->getOperand()->getDependence() & ~ExprDependence::TypeValue;
+  if (CT == CT_Dependent)
+    D |= ExprDependence::ValueInstantiation;
+  return D;
+}
+
+ExprDependence clang::computeDependence(SubstNonTypeTemplateParmExpr *E) {
+  return E->getReplacement()->getDependence();
+}
+
+ExprDependence clang::computeDependence(CoroutineSuspendExpr *E) {
+  if (auto *Resume = E->getResumeExpr())
+    return (Resume->getDependence() & ExprDependence::TypeValue) |
+           (E->getCommonExpr()->getDependence() & ~ExprDependence::TypeValue);
+  return E->getCommonExpr()->getDependence() |
+         ExprDependence::TypeValueInstantiation;
+}
+
+ExprDependence clang::computeDependence(DependentCoawaitExpr *E) {
+  return E->getOperand()->getDependence() |
+         ExprDependence::TypeValueInstantiation;
+}
+
+ExprDependence clang::computeDependence(ObjCBoxedExpr *E) {
+  return E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(ObjCEncodeExpr *E) {
+  return toExprDependence(E->getEncodedType()->getDependence());
+}
+
+ExprDependence clang::computeDependence(ObjCIvarRefExpr *E) {
+  return turnTypeToValueDependence(E->getBase()->getDependence());
+}
+
+ExprDependence clang::computeDependence(ObjCPropertyRefExpr *E) {
+  if (E->isObjectReceiver())
+    return E->getBase()->getDependence() & ~ExprDependence::Type;
+  if (E->isSuperReceiver())
+    return toExprDependence(E->getSuperReceiverType()->getDependence()) &
+           ~ExprDependence::TypeValue;
+  assert(E->isClassReceiver());
+  return ExprDependence::None;
+}
+
+ExprDependence clang::computeDependence(ObjCSubscriptRefExpr *E) {
+  return E->getBaseExpr()->getDependence() | E->getKeyExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(ObjCIsaExpr *E) {
+  return E->getBase()->getDependence() & ~ExprDependence::Type &
+         ~ExprDependence::UnexpandedPack;
+}
+
+ExprDependence clang::computeDependence(ObjCIndirectCopyRestoreExpr *E) {
+  return E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(OMPArraySectionExpr *E) {
+  auto D = E->getBase()->getDependence();
+  if (auto *LB = E->getLowerBound())
+    D |= LB->getDependence();
+  if (auto *Len = E->getLength())
+    D |= Len->getDependence();
+  return D;
+}
+
+/// Compute the type-, value-, and instantiation-dependence of a
+/// declaration reference
+/// based on the declaration being referenced.
+ExprDependence clang::computeDependence(DeclRefExpr *E, const ASTContext &Ctx) {
+  auto Deps = ExprDependence::None;
+
+  if (auto *NNS = E->getQualifier())
+    Deps |= toExprDependence(NNS->getDependence());
+
+  if (auto *FirstArg = E->getTemplateArgs()) {
+    unsigned NumArgs = E->getNumTemplateArgs();
+    for (auto *Arg = FirstArg, *End = FirstArg + NumArgs; Arg < End; ++Arg)
+      Deps |= toExprDependence(Arg->getArgument().getDependence());
+  }
+
+  auto *Decl = E->getDecl();
+  auto Type = E->getType();
+
+  if (Decl->isParameterPack())
+    Deps |= ExprDependence::UnexpandedPack;
+
+  // (TD) C++ [temp.dep.expr]p3:
+  //   An id-expression is type-dependent if it contains:
+  //
+  // and
+  //
+  // (VD) C++ [temp.dep.constexpr]p2:
+  //  An identifier is value-dependent if it is:
+
+  //  (TD)  - an identifier that was declared with dependent type
+  //  (VD)  - a name declared with a dependent type,
+  if (Type->isDependentType())
+    return Deps | ExprDependence::TypeValueInstantiation;
+  else if (Type->isInstantiationDependentType())
+    Deps |= ExprDependence::Instantiation;
+
+  //  (TD)  - a conversion-function-id that specifies a dependent type
+  if (Decl->getDeclName().getNameKind() ==
+      DeclarationName::CXXConversionFunctionName) {
+    QualType T = Decl->getDeclName().getCXXNameType();
+    if (T->isDependentType())
+      return Deps | ExprDependence::TypeValueInstantiation;
+
+    if (T->isInstantiationDependentType())
+      Deps |= ExprDependence::Instantiation;
+  }
+
+  //  (VD)  - the name of a non-type template parameter,
+  if (isa<NonTypeTemplateParmDecl>(Decl))
+    return Deps | ExprDependence::ValueInstantiation;
+
+  //  (VD) - a constant with integral or enumeration type and is
+  //         initialized with an expression that is value-dependent.
+  //  (VD) - a constant with literal type and is initialized with an
+  //         expression that is value-dependent [C++11].
+  //  (VD) - FIXME: Missing from the standard:
+  //       -  an entity with reference type and is initialized with an
+  //          expression that is value-dependent [C++11]
+  if (VarDecl *Var = dyn_cast<VarDecl>(Decl)) {
+    if ((Ctx.getLangOpts().CPlusPlus11
+             ? Var->getType()->isLiteralType(Ctx)
+             : Var->getType()->isIntegralOrEnumerationType()) &&
+        (Var->getType().isConstQualified() ||
+         Var->getType()->isReferenceType())) {
+      if (const Expr *Init = Var->getAnyInitializer())
+        if (Init->isValueDependent()) {
+          Deps |= ExprDependence::ValueInstantiation;
+        }
+    }
+
+    // (VD) - FIXME: Missing from the standard:
+    //      -  a member function or a static data member of the current
+    //         instantiation
+    if (Var->isStaticDataMember() &&
+        Var->getDeclContext()->isDependentContext()) {
+      Deps |= ExprDependence::ValueInstantiation;
+      TypeSourceInfo *TInfo = Var->getFirstDecl()->getTypeSourceInfo();
+      if (TInfo->getType()->isIncompleteArrayType())
+        Deps |= ExprDependence::Type;
+    }
+
+    return Deps;
+  }
+
+  // (VD) - FIXME: Missing from the standard:
+  //      -  a member function or a static data member of the current
+  //         instantiation
+  if (isa<CXXMethodDecl>(Decl) && Decl->getDeclContext()->isDependentContext())
+    Deps |= ExprDependence::ValueInstantiation;
+  return Deps;
+}
+
+ExprDependence clang::computeDependence(PredefinedExpr *E) {
+  return toExprDependence(E->getType()->getDependence()) &
+         ~ExprDependence::UnexpandedPack;
+}
+
+ExprDependence clang::computeDependence(CallExpr *E,
+                                        llvm::ArrayRef<Expr *> PreArgs) {
+  auto D = E->getCallee()->getDependence();
+  for (auto *A : llvm::makeArrayRef(E->getArgs(), E->getNumArgs())) {
+    if (A)
+      D |= A->getDependence();
+  }
+  for (auto *A : PreArgs)
+    D |= A->getDependence();
+  return D;
+}
+
+ExprDependence clang::computeDependence(OffsetOfExpr *E) {
+  auto D = turnTypeToValueDependence(
+      toExprDependence(E->getTypeSourceInfo()->getType()->getDependence()));
+  for (unsigned I = 0, N = E->getNumExpressions(); I < N; ++I)
+    D |= turnTypeToValueDependence(E->getIndexExpr(I)->getDependence());
+  return D;
+}
+
+ExprDependence clang::computeDependence(MemberExpr *E) {
+  return E->getBase()->getDependence();
+}
+
+ExprDependence clang::computeDependence(InitListExpr *E) {
+  auto D = ExprDependence::None;
+  for (auto *A : E->inits())
+    D |= A->getDependence();
+  return D;
+}
+
+ExprDependence clang::computeDependence(ShuffleVectorExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence());
+  for (auto *C : llvm::makeArrayRef(E->getSubExprs(), E->getNumSubExprs()))
+    D |= C->getDependence();
+  return D;
+}
+
+ExprDependence clang::computeDependence(GenericSelectionExpr *E,
+                                        bool ContainsUnexpandedPack) {
+  auto D = ContainsUnexpandedPack ? ExprDependence::UnexpandedPack
+                                  : ExprDependence::None;
+  if (E->isResultDependent())
+    return D | ExprDependence::TypeValueInstantiation;
+  return D | (E->getResultExpr()->getDependence() &
+              ~ExprDependence::UnexpandedPack);
+}
+
+ExprDependence clang::computeDependence(DesignatedInitExpr *E) {
+  auto Deps = E->getInit()->getDependence();
+  for (auto D : E->designators()) {
+    auto DesignatorDeps = ExprDependence::None;
+    if (D.isArrayDesignator())
+      DesignatorDeps |= E->getArrayIndex(D)->getDependence();
+    else if (D.isArrayRangeDesignator())
+      DesignatorDeps |= E->getArrayRangeStart(D)->getDependence() |
+                        E->getArrayRangeEnd(D)->getDependence();
+    Deps |= DesignatorDeps;
+    if (DesignatorDeps & ExprDependence::TypeValue)
+      Deps |= ExprDependence::TypeValueInstantiation;
+  }
+  return Deps;
+}
+
+ExprDependence clang::computeDependence(PseudoObjectExpr *O) {
+  auto D = O->getSyntacticForm()->getDependence();
+  for (auto *E : O->semantics())
+    D |= E->getDependence();
+  return D;
+}
+
+ExprDependence clang::computeDependence(AtomicExpr *A) {
+  auto D = ExprDependence::None;
+  for (auto *E : llvm::makeArrayRef(A->getSubExprs(), A->getNumSubExprs()))
+    D |= E->getDependence();
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXNewExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence());
+  auto Size = E->getArraySize();
+  if (Size.hasValue() && *Size)
+    D |= turnTypeToValueDependence((*Size)->getDependence());
+  if (auto *I = E->getInitializer())
+    D |= turnTypeToValueDependence(I->getDependence());
+  for (auto *A : E->placement_arguments())
+    D |= turnTypeToValueDependence(A->getDependence());
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXPseudoDestructorExpr *E) {
+  auto D = E->getBase()->getDependence();
+  if (!E->getDestroyedType().isNull())
+    D |= toExprDependence(E->getDestroyedType()->getDependence());
+  if (auto *ST = E->getScopeTypeInfo())
+    D |= turnTypeToValueDependence(
+        toExprDependence(ST->getType()->getDependence()));
+  if (auto *Q = E->getQualifier())
+    D |= toExprDependence(Q->getDependence());
+  return D;
+}
+
+static inline ExprDependence getDependenceInExpr(DeclarationNameInfo Name) {
+  auto D = ExprDependence::None;
+  if (Name.isInstantiationDependent())
+    D |= ExprDependence::Instantiation;
+  if (Name.containsUnexpandedParameterPack())
+    D |= ExprDependence::UnexpandedPack;
+  return D;
+}
+
+ExprDependence
+clang::computeDependence(OverloadExpr *E, bool KnownDependent,
+                         bool KnownInstantiationDependent,
+                         bool KnownContainsUnexpandedParameterPack) {
+  auto Deps = ExprDependence::None;
+  if (KnownDependent)
+    Deps |= ExprDependence::TypeValue;
+  if (KnownInstantiationDependent)
+    Deps |= ExprDependence::Instantiation;
+  if (KnownContainsUnexpandedParameterPack)
+    Deps |= ExprDependence::UnexpandedPack;
+  Deps |= getDependenceInExpr(E->getNameInfo());
+  if (auto *Q = E->getQualifier())
+    Deps |= toExprDependence(Q->getDependence());
+  for (auto *D : E->decls()) {
+    if (D->getDeclContext()->isDependentContext() ||
+        isa<UnresolvedUsingValueDecl>(D))
+      Deps |= ExprDependence::TypeValueInstantiation;
+  }
+  // If we have explicit template arguments, check for dependent
+  // template arguments and whether they contain any unexpanded pack
+  // expansions.
+  for (auto A : E->template_arguments())
+    Deps |= toExprDependence(A.getArgument().getDependence());
+  return Deps;
+}
+
+ExprDependence clang::computeDependence(DependentScopeDeclRefExpr *E) {
+  auto D = ExprDependence::TypeValue;
+  D |= getDependenceInExpr(E->getNameInfo());
+  if (auto *Q = E->getQualifier())
+    D |= toExprDependence(Q->getDependence());
+  for (auto A : E->template_arguments())
+    D |= toExprDependence(A.getArgument().getDependence());
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXConstructExpr *E) {
+  auto D = toExprDependence(E->getType()->getDependence());
+  for (auto *A : E->arguments())
+    D |= A->getDependence() & ~ExprDependence::Type;
+  return D;
+}
+
+ExprDependence clang::computeDependence(LambdaExpr *E,
+                                        bool ContainsUnexpandedParameterPack) {
+  auto D = toExprDependence(E->getType()->getDependence());
+  if (ContainsUnexpandedParameterPack)
+    D |= ExprDependence::UnexpandedPack;
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXUnresolvedConstructExpr *E) {
+  auto D = ExprDependence::ValueInstantiation;
+  D |= toExprDependence(E->getType()->getDependence());
+  if (E->getType()->getContainedDeducedType())
+    D |= ExprDependence::Type;
+  for (auto *A : E->arguments())
+    D |= A->getDependence() & ExprDependence::UnexpandedPack;
+  return D;
+}
+
+ExprDependence clang::computeDependence(CXXDependentScopeMemberExpr *E) {
+  auto D = ExprDependence::TypeValueInstantiation;
+  if (!E->isImplicitAccess())
+    D |= E->getBase()->getDependence();
+  if (auto *Q = E->getQualifier())
+    D |= toExprDependence(Q->getDependence());
+  D |= getDependenceInExpr(E->getMemberNameInfo());
+  for (auto A : E->template_arguments())
+    D |= toExprDependence(A.getArgument().getDependence());
+  return D;
+}
+
+ExprDependence clang::computeDependence(MaterializeTemporaryExpr *E) {
+  return E->getSubExpr()->getDependence();
+}
+
+ExprDependence clang::computeDependence(TypeTraitExpr *E) {
+  auto D = ExprDependence::None;
+  for (const auto *A : E->getArgs())
+    D |=
+        toExprDependence(A->getType()->getDependence()) & ~ExprDependence::Type;
+  return D;
+}
+
+ExprDependence clang::computeDependence(ConceptSpecializationExpr *E,
+                                        bool ValueDependent) {
+  auto TA = TemplateArgumentDependence::None;
+  const auto InterestingDeps = TemplateArgumentDependence::Instantiation |
+                               TemplateArgumentDependence::UnexpandedPack;
+  for (const TemplateArgumentLoc &ArgLoc :
+       E->getTemplateArgsAsWritten()->arguments()) {
+    TA |= ArgLoc.getArgument().getDependence() & InterestingDeps;
+    if (TA == InterestingDeps)
+      break;
+  }
+
+  ExprDependence D =
+      ValueDependent ? ExprDependence::Value : ExprDependence::None;
+  return D | toExprDependence(TA);
+}
+
+ExprDependence clang::computeDependence(ObjCArrayLiteral *E) {
+  auto D = ExprDependence::None;
+  Expr **Elements = E->getElements();
+  for (unsigned I = 0, N = E->getNumElements(); I != N; ++I)
+    D |= turnTypeToValueDependence(Elements[I]->getDependence());
+  return D;
+}
+
+ExprDependence clang::computeDependence(ObjCDictionaryLiteral *E) {
+  auto Deps = ExprDependence::None;
+  for (unsigned I = 0, N = E->getNumElements(); I < N; ++I) {
+    auto KV = E->getKeyValueElement(I);
+    auto KVDeps = turnTypeToValueDependence(KV.Key->getDependence() |
+                                            KV.Value->getDependence());
+    if (KV.EllipsisLoc.isValid())
+      KVDeps &= ~ExprDependence::UnexpandedPack;
+    Deps |= KVDeps;
+  }
+  return Deps;
+}
+
+ExprDependence clang::computeDependence(ObjCMessageExpr *E) {
+  auto D = ExprDependence::None;
+  if (auto *R = E->getInstanceReceiver())
+    D |= R->getDependence();
+  else
+    D |= toExprDependence(E->getType()->getDependence());
+  for (auto *A : E->arguments())
+    D |= A->getDependence();
+  return D;
+}
diff --git a/clang/lib/AST/DeclBase.cpp b/clang/lib/AST/DeclBase.cpp
index 325a306b1a750..a59873cbc9fc0 100644
--- a/clang/lib/AST/DeclBase.cpp
+++ b/clang/lib/AST/DeclBase.cpp
@@ -454,7 +454,8 @@ ExternalSourceSymbolAttr *Decl::getExternalSourceSymbolAttr() const {
 }
 
 bool Decl::hasDefiningAttr() const {
-  return hasAttr<AliasAttr>() || hasAttr<IFuncAttr>();
+  return hasAttr<AliasAttr>() || hasAttr<IFuncAttr>() ||
+         hasAttr<LoaderUninitializedAttr>();
 }
 
 const Attr *Decl::getDefiningAttr() const {
@@ -462,6 +463,8 @@ const Attr *Decl::getDefiningAttr() const {
     return AA;
   if (auto *IFA = getAttr<IFuncAttr>())
     return IFA;
+  if (auto *NZA = getAttr<LoaderUninitializedAttr>())
+    return NZA;
   return nullptr;
 }
 
diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp
index 8f05709bf1181..97eb3c5300055 100644
--- a/clang/lib/AST/Expr.cpp
+++ b/clang/lib/AST/Expr.cpp
@@ -14,10 +14,11 @@
 #include "clang/AST/APValue.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/Attr.h"
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclObjC.h"
 #include "clang/AST/DeclTemplate.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/EvaluatedExprVisitor.h"
 #include "clang/AST/ExprCXX.h"
 #include "clang/AST/Mangle.h"
@@ -369,93 +370,12 @@ APValue ConstantExpr::getAPValueResult() const {
   llvm_unreachable("invalid ResultKind");
 }
 
-/// Compute the type-, value-, and instantiation-dependence of a
-/// declaration reference
-/// based on the declaration being referenced.
-static ExprDependence computeDeclRefDependence(const ASTContext &Ctx,
-                                               NamedDecl *D, QualType T) {
-  auto R = ExprDependence::None;
-  if (D->isParameterPack())
-    R |= ExprDependence::UnexpandedPack;
-
-  // (TD) C++ [temp.dep.expr]p3:
-  //   An id-expression is type-dependent if it contains:
-  //
-  // and
-  //
-  // (VD) C++ [temp.dep.constexpr]p2:
-  //  An identifier is value-dependent if it is:
-
-  //  (TD)  - an identifier that was declared with dependent type
-  //  (VD)  - a name declared with a dependent type,
-  if (T->isDependentType())
-    return R | ExprDependence::TypeValueInstantiation;
-  else if (T->isInstantiationDependentType())
-    R |= ExprDependence::Instantiation;
-
-  //  (TD)  - a conversion-function-id that specifies a dependent type
-  if (D->getDeclName().getNameKind()
-                                == DeclarationName::CXXConversionFunctionName) {
-    QualType T = D->getDeclName().getCXXNameType();
-    if (T->isDependentType())
-      return R | ExprDependence::TypeValueInstantiation;
-
-    if (T->isInstantiationDependentType())
-      R |= ExprDependence::Instantiation;
-  }
-
-  //  (VD)  - the name of a non-type template parameter,
-  if (isa<NonTypeTemplateParmDecl>(D))
-    return R | ExprDependence::ValueInstantiation;
-
-  //  (VD) - a constant with integral or enumeration type and is
-  //         initialized with an expression that is value-dependent.
-  //  (VD) - a constant with literal type and is initialized with an
-  //         expression that is value-dependent [C++11].
-  //  (VD) - FIXME: Missing from the standard:
-  //       -  an entity with reference type and is initialized with an
-  //          expression that is value-dependent [C++11]
-  if (VarDecl *Var = dyn_cast<VarDecl>(D)) {
-    if ((Ctx.getLangOpts().CPlusPlus11 ?
-           Var->getType()->isLiteralType(Ctx) :
-           Var->getType()->isIntegralOrEnumerationType()) &&
-        (Var->getType().isConstQualified() ||
-         Var->getType()->isReferenceType())) {
-      if (const Expr *Init = Var->getAnyInitializer())
-        if (Init->isValueDependent()) {
-          R |= ExprDependence::ValueInstantiation;
-        }
-    }
-
-    // (VD) - FIXME: Missing from the standard:
-    //      -  a member function or a static data member of the current
-    //         instantiation
-    if (Var->isStaticDataMember() &&
-        Var->getDeclContext()->isDependentContext()) {
-      R |= ExprDependence::ValueInstantiation;
-      TypeSourceInfo *TInfo = Var->getFirstDecl()->getTypeSourceInfo();
-      if (TInfo->getType()->isIncompleteArrayType())
-        R |= ExprDependence::Type;
-    }
-
-    return R;
-  }
-
-  // (VD) - FIXME: Missing from the standard:
-  //      -  a member function or a static data member of the current
-  //         instantiation
-  if (isa<CXXMethodDecl>(D) && D->getDeclContext()->isDependentContext())
-    R |= ExprDependence::ValueInstantiation;
-  return R;
-}
-
 DeclRefExpr::DeclRefExpr(const ASTContext &Ctx, ValueDecl *D,
                          bool RefersToEnclosingVariableOrCapture, QualType T,
                          ExprValueKind VK, SourceLocation L,
                          const DeclarationNameLoc &LocInfo,
                          NonOdrUseReason NOUR)
-    : Expr(DeclRefExprClass, T, VK, OK_Ordinary, false, false, false, false),
-      D(D), DNLoc(LocInfo) {
+    : Expr(DeclRefExprClass, T, VK, OK_Ordinary), D(D), DNLoc(LocInfo) {
   DeclRefExprBits.HasQualifier = false;
   DeclRefExprBits.HasTemplateKWAndArgsInfo = false;
   DeclRefExprBits.HasFoundDecl = false;
@@ -464,7 +384,7 @@ DeclRefExpr::DeclRefExpr(const ASTContext &Ctx, ValueDecl *D,
       RefersToEnclosingVariableOrCapture;
   DeclRefExprBits.NonOdrUseReason = NOUR;
   DeclRefExprBits.Loc = L;
-  addDependence(computeDeclRefDependence(Ctx, getDecl(), getType()));
+  setDependence(computeDependence(this, Ctx));
 }
 
 DeclRefExpr::DeclRefExpr(const ASTContext &Ctx,
@@ -474,19 +394,13 @@ DeclRefExpr::DeclRefExpr(const ASTContext &Ctx,
                          const DeclarationNameInfo &NameInfo, NamedDecl *FoundD,
                          const TemplateArgumentListInfo *TemplateArgs,
                          QualType T, ExprValueKind VK, NonOdrUseReason NOUR)
-    : Expr(DeclRefExprClass, T, VK, OK_Ordinary, false, false, false, false),
-      D(D), DNLoc(NameInfo.getInfo()) {
+    : Expr(DeclRefExprClass, T, VK, OK_Ordinary), D(D),
+      DNLoc(NameInfo.getInfo()) {
   DeclRefExprBits.Loc = NameInfo.getLoc();
   DeclRefExprBits.HasQualifier = QualifierLoc ? 1 : 0;
-  if (QualifierLoc) {
+  if (QualifierLoc)
     new (getTrailingObjects<NestedNameSpecifierLoc>())
         NestedNameSpecifierLoc(QualifierLoc);
-    auto *NNS = QualifierLoc.getNestedNameSpecifier();
-    if (NNS->isInstantiationDependent())
-      addDependence(ExprDependence::Instantiation);
-    if (NNS->containsUnexpandedParameterPack())
-      addDependence(ExprDependence::UnexpandedPack);
-  }
   DeclRefExprBits.HasFoundDecl = FoundD ? 1 : 0;
   if (FoundD)
     *getTrailingObjects<NamedDecl *>() = FoundD;
@@ -502,13 +416,12 @@ DeclRefExpr::DeclRefExpr(const ASTContext &Ctx,
         Deps);
     assert(!(Deps & TemplateArgumentDependence::Dependent) &&
            "built a DeclRefExpr with dependent template args");
-    addDependence(toExprDependence(Deps));
   } else if (TemplateKWLoc.isValid()) {
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
   }
   DeclRefExprBits.HadMultipleCandidates = 0;
-  addDependence(computeDeclRefDependence(Ctx, getDecl(), getType()));
+  setDependence(computeDependence(this, Ctx));
 }
 
 DeclRefExpr *DeclRefExpr::Create(const ASTContext &Context,
@@ -580,10 +493,7 @@ SourceLocation DeclRefExpr::getEndLoc() const {
 
 PredefinedExpr::PredefinedExpr(SourceLocation L, QualType FNTy, IdentKind IK,
                                StringLiteral *SL)
-    : Expr(PredefinedExprClass, FNTy, VK_LValue, OK_Ordinary,
-           FNTy->isDependentType(), FNTy->isDependentType(),
-           FNTy->isInstantiationDependentType(),
-           /*ContainsUnexpandedParameterPack=*/false) {
+    : Expr(PredefinedExprClass, FNTy, VK_LValue, OK_Ordinary) {
   PredefinedExprBits.Kind = IK;
   assert((getIdentKind() == IK) &&
          "IdentKind do not fit in PredefinedExprBitfields!");
@@ -592,14 +502,12 @@ PredefinedExpr::PredefinedExpr(SourceLocation L, QualType FNTy, IdentKind IK,
   PredefinedExprBits.Loc = L;
   if (HasFunctionName)
     setFunctionName(SL);
+  setDependence(computeDependence(this));
 }
 
 PredefinedExpr::PredefinedExpr(SourceLocation L, QualType FNTy, IdentKind IK,
                                TypeSourceInfo *Info)
-    : Expr(PredefinedExprClass, FNTy, VK_LValue, OK_Ordinary,
-           FNTy->isDependentType(), FNTy->isDependentType(),
-           FNTy->isInstantiationDependentType(),
-           /*ContainsUnexpandedParameterPack=*/false) {
+    : Expr(PredefinedExprClass, FNTy, VK_LValue, OK_Ordinary) {
   PredefinedExprBits.Kind = IK;
   assert((getIdentKind() == IK) &&
          "IdentKind do not fit in PredefinedExprBitfields!");
@@ -608,14 +516,12 @@ PredefinedExpr::PredefinedExpr(SourceLocation L, QualType FNTy, IdentKind IK,
   PredefinedExprBits.HasFunctionName = false;
   PredefinedExprBits.Loc = L;
   setTypeSourceInfo(Info);
+  setDependence(computeDependence(this));
 }
 
 PredefinedExpr::PredefinedExpr(SourceLocation L, QualType FNTy, IdentKind IK,
                                Expr *Info)
-    : Expr(PredefinedExprClass, FNTy, VK_LValue, OK_Ordinary,
-           FNTy->isDependentType(), FNTy->isDependentType(),
-           FNTy->isInstantiationDependentType(),
-           /*ContainsUnexpandedParameterPack=*/false) {
+    : Expr(PredefinedExprClass, FNTy, VK_LValue, OK_Ordinary) {
   PredefinedExprBits.Kind = IK;
   assert((getIdentKind() == IK) &&
          "IdentKind do not fit in PredefinedExprBitfields!");
@@ -624,6 +530,7 @@ PredefinedExpr::PredefinedExpr(SourceLocation L, QualType FNTy, IdentKind IK,
   PredefinedExprBits.HasFunctionName = false;
   PredefinedExprBits.Loc = L;
   setExpr(Info);
+  setDependence(computeDependence(this));
 }
 
 PredefinedExpr::PredefinedExpr(EmptyShell Empty, bool HasFunctionName)
@@ -732,7 +639,7 @@ std::string PredefinedExpr::ComputeName(IdentKind IK, const Decl *CurrentDecl) {
         else if (const CXXDestructorDecl *DD = dyn_cast<CXXDestructorDecl>(ND))
           GD = GlobalDecl(DD, Dtor_Base);
         else if (ND->hasAttr<CUDAGlobalAttr>())
-          GD = GlobalDecl::getDefaultKernelReference(cast<FunctionDecl>(ND));
+          GD = GlobalDecl(cast<FunctionDecl>(ND));
         else
           GD = GlobalDecl(ND);
         MC->mangleName(GD, Out);
@@ -964,13 +871,12 @@ void APNumericStorage::setIntValue(const ASTContext &C,
 
 IntegerLiteral::IntegerLiteral(const ASTContext &C, const llvm::APInt &V,
                                QualType type, SourceLocation l)
-  : Expr(IntegerLiteralClass, type, VK_RValue, OK_Ordinary, false, false,
-         false, false),
-    Loc(l) {
+    : Expr(IntegerLiteralClass, type, VK_RValue, OK_Ordinary), Loc(l) {
   assert(type->isIntegerType() && "Illegal type in IntegerLiteral");
   assert(V.getBitWidth() == C.getIntWidth(type) &&
          "Integer type is not the correct size for constant.");
   setValue(C, V);
+  setDependence(ExprDependence::None);
 }
 
 IntegerLiteral *
@@ -987,13 +893,13 @@ IntegerLiteral::Create(const ASTContext &C, EmptyShell Empty) {
 FixedPointLiteral::FixedPointLiteral(const ASTContext &C, const llvm::APInt &V,
                                      QualType type, SourceLocation l,
                                      unsigned Scale)
-    : Expr(FixedPointLiteralClass, type, VK_RValue, OK_Ordinary, false, false,
-           false, false),
-      Loc(l), Scale(Scale) {
+    : Expr(FixedPointLiteralClass, type, VK_RValue, OK_Ordinary), Loc(l),
+      Scale(Scale) {
   assert(type->isFixedPointType() && "Illegal type in FixedPointLiteral");
   assert(V.getBitWidth() == C.getTypeInfo(type).Width &&
          "Fixed point type is not the correct size for constant.");
   setValue(C, V);
+  setDependence(ExprDependence::None);
 }
 
 FixedPointLiteral *FixedPointLiteral::CreateFromRawInt(const ASTContext &C,
@@ -1016,11 +922,11 @@ std::string FixedPointLiteral::getValueAsString(unsigned Radix) const {
 
 FloatingLiteral::FloatingLiteral(const ASTContext &C, const llvm::APFloat &V,
                                  bool isexact, QualType Type, SourceLocation L)
-  : Expr(FloatingLiteralClass, Type, VK_RValue, OK_Ordinary, false, false,
-         false, false), Loc(L) {
+    : Expr(FloatingLiteralClass, Type, VK_RValue, OK_Ordinary), Loc(L) {
   setSemantics(V.getSemantics());
   FloatingLiteralBits.IsExact = isexact;
   setValue(C, V);
+  setDependence(ExprDependence::None);
 }
 
 FloatingLiteral::FloatingLiteral(const ASTContext &C, EmptyShell Empty)
@@ -1080,8 +986,7 @@ StringLiteral::StringLiteral(const ASTContext &Ctx, StringRef Str,
                              StringKind Kind, bool Pascal, QualType Ty,
                              const SourceLocation *Loc,
                              unsigned NumConcatenated)
-    : Expr(StringLiteralClass, Ty, VK_LValue, OK_Ordinary, false, false, false,
-           false) {
+    : Expr(StringLiteralClass, Ty, VK_LValue, OK_Ordinary) {
   assert(Ctx.getAsConstantArrayType(Ty) &&
          "StringLiteral must be of constant array type!");
   unsigned CharByteWidth = mapCharByteWidth(Ctx.getTargetInfo(), Kind);
@@ -1120,6 +1025,8 @@ StringLiteral::StringLiteral(const ASTContext &Ctx, StringRef Str,
 
   // Initialize the trailing array of char holding the string data.
   std::memcpy(getTrailingObjects<char>(), Str.data(), ByteLength);
+
+  setDependence(ExprDependence::None);
 }
 
 StringLiteral::StringLiteral(EmptyShell Empty, unsigned NumConcatenated,
@@ -1388,10 +1295,7 @@ CallExpr::CallExpr(StmtClass SC, Expr *Fn, ArrayRef<Expr *> PreArgs,
                    ArrayRef<Expr *> Args, QualType Ty, ExprValueKind VK,
                    SourceLocation RParenLoc, unsigned MinNumArgs,
                    ADLCallKind UsesADL)
-    : Expr(SC, Ty, VK, OK_Ordinary, Fn->isTypeDependent(),
-           Fn->isValueDependent(), Fn->isInstantiationDependent(),
-           Fn->containsUnexpandedParameterPack()),
-      RParenLoc(RParenLoc) {
+    : Expr(SC, Ty, VK, OK_Ordinary), RParenLoc(RParenLoc) {
   NumArgs = std::max<unsigned>(Args.size(), MinNumArgs);
   unsigned NumPreArgs = PreArgs.size();
   CallExprBits.NumPreArgs = NumPreArgs;
@@ -1405,17 +1309,14 @@ CallExpr::CallExpr(StmtClass SC, Expr *Fn, ArrayRef<Expr *> PreArgs,
   CallExprBits.UsesADL = static_cast<bool>(UsesADL);
 
   setCallee(Fn);
-  for (unsigned I = 0; I != NumPreArgs; ++I) {
-    addDependence(PreArgs[I]->getDependence());
+  for (unsigned I = 0; I != NumPreArgs; ++I)
     setPreArg(I, PreArgs[I]);
-  }
-  for (unsigned I = 0; I != Args.size(); ++I) {
-    addDependence(Args[I]->getDependence());
+  for (unsigned I = 0; I != Args.size(); ++I)
     setArg(I, Args[I]);
-  }
-  for (unsigned I = Args.size(); I != NumArgs; ++I) {
+  for (unsigned I = Args.size(); I != NumArgs; ++I)
     setArg(I, nullptr);
-  }
+
+  setDependence(computeDependence(this, PreArgs));
 }
 
 CallExpr::CallExpr(StmtClass SC, unsigned NumPreArgs, unsigned NumArgs,
@@ -1599,28 +1500,17 @@ OffsetOfExpr *OffsetOfExpr::CreateEmpty(const ASTContext &C,
 
 OffsetOfExpr::OffsetOfExpr(const ASTContext &C, QualType type,
                            SourceLocation OperatorLoc, TypeSourceInfo *tsi,
-                           ArrayRef<OffsetOfNode> comps, ArrayRef<Expr*> exprs,
+                           ArrayRef<OffsetOfNode> comps, ArrayRef<Expr *> exprs,
                            SourceLocation RParenLoc)
-  : Expr(OffsetOfExprClass, type, VK_RValue, OK_Ordinary,
-         /*TypeDependent=*/false,
-         /*ValueDependent=*/tsi->getType()->isDependentType(),
-         tsi->getType()->isInstantiationDependentType(),
-         tsi->getType()->containsUnexpandedParameterPack()),
-    OperatorLoc(OperatorLoc), RParenLoc(RParenLoc), TSInfo(tsi),
-    NumComps(comps.size()), NumExprs(exprs.size())
-{
-  for (unsigned i = 0; i != comps.size(); ++i) {
+    : Expr(OffsetOfExprClass, type, VK_RValue, OK_Ordinary),
+      OperatorLoc(OperatorLoc), RParenLoc(RParenLoc), TSInfo(tsi),
+      NumComps(comps.size()), NumExprs(exprs.size()) {
+  for (unsigned i = 0; i != comps.size(); ++i)
     setComponent(i, comps[i]);
-  }
-
-  for (unsigned i = 0; i != exprs.size(); ++i) {
-    if (exprs[i]->isTypeDependent() || exprs[i]->isValueDependent())
-      addDependence(ExprDependence::Value);
-    if (exprs[i]->containsUnexpandedParameterPack())
-      addDependence(ExprDependence ::UnexpandedPack);
-
+  for (unsigned i = 0; i != exprs.size(); ++i)
     setIndexExpr(i, exprs[i]);
-  }
+
+  setDependence(computeDependence(this));
 }
 
 IdentifierInfo *OffsetOfNode::getFieldName() const {
@@ -1634,38 +1524,12 @@ IdentifierInfo *OffsetOfNode::getFieldName() const {
 UnaryExprOrTypeTraitExpr::UnaryExprOrTypeTraitExpr(
     UnaryExprOrTypeTrait ExprKind, Expr *E, QualType resultType,
     SourceLocation op, SourceLocation rp)
-    : Expr(UnaryExprOrTypeTraitExprClass, resultType, VK_RValue, OK_Ordinary,
-           false, // Never type-dependent (C++ [temp.dep.expr]p3).
-           // Value-dependent if the argument is type-dependent.
-           E->isTypeDependent(), E->isInstantiationDependent(),
-           E->containsUnexpandedParameterPack()),
+    : Expr(UnaryExprOrTypeTraitExprClass, resultType, VK_RValue, OK_Ordinary),
       OpLoc(op), RParenLoc(rp) {
   UnaryExprOrTypeTraitExprBits.Kind = ExprKind;
   UnaryExprOrTypeTraitExprBits.IsType = false;
   Argument.Ex = E;
-
-  // Check to see if we are in the situation where alignof(decl) should be
-  // dependent because decl's alignment is dependent.
-  if (ExprKind == UETT_AlignOf || ExprKind == UETT_PreferredAlignOf) {
-    if (!isValueDependent() || !isInstantiationDependent()) {
-      E = E->IgnoreParens();
-
-      const ValueDecl *D = nullptr;
-      if (const auto *DRE = dyn_cast<DeclRefExpr>(E))
-        D = DRE->getDecl();
-      else if (const auto *ME = dyn_cast<MemberExpr>(E))
-        D = ME->getMemberDecl();
-
-      if (D) {
-        for (const auto *I : D->specific_attrs<AlignedAttr>()) {
-          if (I->isAlignmentDependent()) {
-            addDependence(ExprDependence::ValueInstantiation);
-            break;
-          }
-        }
-      }
-    }
-  }
+  setDependence(computeDependence(this));
 }
 
 MemberExpr::MemberExpr(Expr *Base, bool IsArrow, SourceLocation OperatorLoc,
@@ -1673,11 +1537,8 @@ MemberExpr::MemberExpr(Expr *Base, bool IsArrow, SourceLocation OperatorLoc,
                        const DeclarationNameInfo &NameInfo, QualType T,
                        ExprValueKind VK, ExprObjectKind OK,
                        NonOdrUseReason NOUR)
-    : Expr(MemberExprClass, T, VK, OK, Base->isTypeDependent(),
-           Base->isValueDependent(), Base->isInstantiationDependent(),
-           Base->containsUnexpandedParameterPack()),
-      Base(Base), MemberDecl(MemberDecl), MemberDNLoc(NameInfo.getInfo()),
-      MemberLoc(NameInfo.getLoc()) {
+    : Expr(MemberExprClass, T, VK, OK), Base(Base), MemberDecl(MemberDecl),
+      MemberDNLoc(NameInfo.getInfo()), MemberLoc(NameInfo.getLoc()) {
   assert(!NameInfo.getName() ||
          MemberDecl->getDeclName() == NameInfo.getName());
   MemberExprBits.IsArrow = IsArrow;
@@ -1686,6 +1547,7 @@ MemberExpr::MemberExpr(Expr *Base, bool IsArrow, SourceLocation OperatorLoc,
   MemberExprBits.HadMultipleCandidates = false;
   MemberExprBits.NonOdrUseReason = NOUR;
   MemberExprBits.OperatorLoc = OperatorLoc;
+  setDependence(computeDependence(this));
 }
 
 MemberExpr *MemberExpr::Create(
@@ -2192,9 +2054,10 @@ SourceLocExpr::SourceLocExpr(const ASTContext &Ctx, IdentKind Kind,
                              SourceLocation BLoc, SourceLocation RParenLoc,
                              DeclContext *ParentContext)
     : Expr(SourceLocExprClass, getDecayedSourceLocExprType(Ctx, Kind),
-           VK_RValue, OK_Ordinary, false, false, false, false),
+           VK_RValue, OK_Ordinary),
       BuiltinLoc(BLoc), RParenLoc(RParenLoc), ParentContext(ParentContext) {
   SourceLocExprBits.Kind = Kind;
+  setDependence(ExprDependence::None);
 }
 
 StringRef SourceLocExpr::getBuiltinStr() const {
@@ -2258,17 +2121,14 @@ APValue SourceLocExpr::EvaluateInContext(const ASTContext &Ctx,
 }
 
 InitListExpr::InitListExpr(const ASTContext &C, SourceLocation lbraceloc,
-                           ArrayRef<Expr*> initExprs, SourceLocation rbraceloc)
-  : Expr(InitListExprClass, QualType(), VK_RValue, OK_Ordinary, false, false,
-         false, false),
-    InitExprs(C, initExprs.size()),
-    LBraceLoc(lbraceloc), RBraceLoc(rbraceloc), AltForm(nullptr, true)
-{
+                           ArrayRef<Expr *> initExprs, SourceLocation rbraceloc)
+    : Expr(InitListExprClass, QualType(), VK_RValue, OK_Ordinary),
+      InitExprs(C, initExprs.size()), LBraceLoc(lbraceloc),
+      RBraceLoc(rbraceloc), AltForm(nullptr, true) {
   sawArrayRangeDesignator(false);
-  for (unsigned I = 0; I != initExprs.size(); ++I)
-    addDependence(initExprs[I]->getDependence());
-
   InitExprs.insert(C, InitExprs.end(), initExprs.begin(), initExprs.end());
+
+  setDependence(computeDependence(this));
 }
 
 void InitListExpr::reserveInits(const ASTContext &C, unsigned NumInits) {
@@ -4177,20 +4037,16 @@ void ExtVectorElementExpr::getEncodedElementAccess(
   }
 }
 
-ShuffleVectorExpr::ShuffleVectorExpr(const ASTContext &C, ArrayRef<Expr*> args,
+ShuffleVectorExpr::ShuffleVectorExpr(const ASTContext &C, ArrayRef<Expr *> args,
                                      QualType Type, SourceLocation BLoc,
                                      SourceLocation RP)
-   : Expr(ShuffleVectorExprClass, Type, VK_RValue, OK_Ordinary,
-          Type->isDependentType(), Type->isDependentType(),
-          Type->isInstantiationDependentType(),
-          Type->containsUnexpandedParameterPack()),
-     BuiltinLoc(BLoc), RParenLoc(RP), NumExprs(args.size())
-{
+    : Expr(ShuffleVectorExprClass, Type, VK_RValue, OK_Ordinary),
+      BuiltinLoc(BLoc), RParenLoc(RP), NumExprs(args.size()) {
   SubExprs = new (C) Stmt*[args.size()];
-  for (unsigned i = 0; i != args.size(); i++) {
-    addDependence(args[i]->getDependence());
+  for (unsigned i = 0; i != args.size(); i++)
     SubExprs[i] = args[i];
-  }
+
+  setDependence(computeDependence(this));
 }
 
 void ShuffleVectorExpr::setExprs(const ASTContext &C, ArrayRef<Expr *> Exprs) {
@@ -4208,11 +4064,7 @@ GenericSelectionExpr::GenericSelectionExpr(
     bool ContainsUnexpandedParameterPack, unsigned ResultIndex)
     : Expr(GenericSelectionExprClass, AssocExprs[ResultIndex]->getType(),
            AssocExprs[ResultIndex]->getValueKind(),
-           AssocExprs[ResultIndex]->getObjectKind(),
-           AssocExprs[ResultIndex]->isTypeDependent(),
-           AssocExprs[ResultIndex]->isValueDependent(),
-           AssocExprs[ResultIndex]->isInstantiationDependent(),
-           ContainsUnexpandedParameterPack),
+           AssocExprs[ResultIndex]->getObjectKind()),
       NumAssocs(AssocExprs.size()), ResultIndex(ResultIndex),
       DefaultLoc(DefaultLoc), RParenLoc(RParenLoc) {
   assert(AssocTypes.size() == AssocExprs.size() &&
@@ -4226,6 +4078,8 @@ GenericSelectionExpr::GenericSelectionExpr(
             getTrailingObjects<Stmt *>() + AssocExprStartIndex);
   std::copy(AssocTypes.begin(), AssocTypes.end(),
             getTrailingObjects<TypeSourceInfo *>());
+
+  setDependence(computeDependence(this, ContainsUnexpandedParameterPack));
 }
 
 GenericSelectionExpr::GenericSelectionExpr(
@@ -4234,10 +4088,7 @@ GenericSelectionExpr::GenericSelectionExpr(
     SourceLocation DefaultLoc, SourceLocation RParenLoc,
     bool ContainsUnexpandedParameterPack)
     : Expr(GenericSelectionExprClass, Context.DependentTy, VK_RValue,
-           OK_Ordinary,
-           /*isTypeDependent=*/true,
-           /*isValueDependent=*/true,
-           /*isInstantiationDependent=*/true, ContainsUnexpandedParameterPack),
+           OK_Ordinary),
       NumAssocs(AssocExprs.size()), ResultIndex(ResultDependentIndex),
       DefaultLoc(DefaultLoc), RParenLoc(RParenLoc) {
   assert(AssocTypes.size() == AssocExprs.size() &&
@@ -4250,6 +4101,8 @@ GenericSelectionExpr::GenericSelectionExpr(
             getTrailingObjects<Stmt *>() + AssocExprStartIndex);
   std::copy(AssocTypes.begin(), AssocTypes.end(),
             getTrailingObjects<TypeSourceInfo *>());
+
+  setDependence(computeDependence(this, ContainsUnexpandedParameterPack));
 }
 
 GenericSelectionExpr::GenericSelectionExpr(EmptyShell Empty, unsigned NumAssocs)
@@ -4308,15 +4161,11 @@ DesignatedInitExpr::DesignatedInitExpr(const ASTContext &C, QualType Ty,
                                        llvm::ArrayRef<Designator> Designators,
                                        SourceLocation EqualOrColonLoc,
                                        bool GNUSyntax,
-                                       ArrayRef<Expr*> IndexExprs,
-                                       Expr *Init)
-  : Expr(DesignatedInitExprClass, Ty,
-         Init->getValueKind(), Init->getObjectKind(),
-         Init->isTypeDependent(), Init->isValueDependent(),
-         Init->isInstantiationDependent(),
-         Init->containsUnexpandedParameterPack()),
-    EqualOrColonLoc(EqualOrColonLoc), GNUSyntax(GNUSyntax),
-    NumDesignators(Designators.size()), NumSubExprs(IndexExprs.size() + 1) {
+                                       ArrayRef<Expr *> IndexExprs, Expr *Init)
+    : Expr(DesignatedInitExprClass, Ty, Init->getValueKind(),
+           Init->getObjectKind()),
+      EqualOrColonLoc(EqualOrColonLoc), GNUSyntax(GNUSyntax),
+      NumDesignators(Designators.size()), NumSubExprs(IndexExprs.size() + 1) {
   this->Designators = new (C) Designator[NumDesignators];
 
   // Record the initializer itself.
@@ -4328,29 +4177,10 @@ DesignatedInitExpr::DesignatedInitExpr(const ASTContext &C, QualType Ty,
   unsigned IndexIdx = 0;
   for (unsigned I = 0; I != NumDesignators; ++I) {
     this->Designators[I] = Designators[I];
-
     if (this->Designators[I].isArrayDesignator()) {
-      // Compute type- and value-dependence.
-      Expr *Index = IndexExprs[IndexIdx];
-
-      // Propagate dependence flags.
-      auto Deps = Index->getDependence();
-      if (Deps & (ExprDependence::Type | ExprDependence::Value))
-        Deps |= ExprDependence::Type | ExprDependence::Value;
-      addDependence(Deps);
-
       // Copy the index expressions into permanent storage.
       *Child++ = IndexExprs[IndexIdx++];
     } else if (this->Designators[I].isArrayRangeDesignator()) {
-      // Compute type- and value-dependence.
-      Expr *Start = IndexExprs[IndexIdx];
-      Expr *End = IndexExprs[IndexIdx + 1];
-
-      auto Deps = Start->getDependence() | End->getDependence();
-      if (Deps & (ExprDependence::Type | ExprDependence::Value))
-        Deps |= ExprDependence::TypeValueInstantiation;
-      addDependence(Deps);
-
       // Copy the start/end expressions into permanent storage.
       *Child++ = IndexExprs[IndexIdx++];
       *Child++ = IndexExprs[IndexIdx++];
@@ -4358,6 +4188,7 @@ DesignatedInitExpr::DesignatedInitExpr(const ASTContext &C, QualType Ty,
   }
 
   assert(IndexIdx == IndexExprs.size() && "Wrong number of index expressions");
+  setDependence(computeDependence(this));
 }
 
 DesignatedInitExpr *
@@ -4461,14 +4292,18 @@ void DesignatedInitExpr::ExpandDesignator(const ASTContext &C, unsigned Idx,
 }
 
 DesignatedInitUpdateExpr::DesignatedInitUpdateExpr(const ASTContext &C,
-    SourceLocation lBraceLoc, Expr *baseExpr, SourceLocation rBraceLoc)
-  : Expr(DesignatedInitUpdateExprClass, baseExpr->getType(), VK_RValue,
-         OK_Ordinary, false, false, false, false) {
+                                                   SourceLocation lBraceLoc,
+                                                   Expr *baseExpr,
+                                                   SourceLocation rBraceLoc)
+    : Expr(DesignatedInitUpdateExprClass, baseExpr->getType(), VK_RValue,
+           OK_Ordinary) {
   BaseAndUpdaterExprs[0] = baseExpr;
 
   InitListExpr *ILE = new (C) InitListExpr(C, lBraceLoc, None, rBraceLoc);
   ILE->setType(baseExpr->getType());
   BaseAndUpdaterExprs[1] = ILE;
+
+  setDependence(ExprDependence::None);
 }
 
 SourceLocation DesignatedInitUpdateExpr::getBeginLoc() const {
@@ -4481,15 +4316,13 @@ SourceLocation DesignatedInitUpdateExpr::getEndLoc() const {
 
 ParenListExpr::ParenListExpr(SourceLocation LParenLoc, ArrayRef<Expr *> Exprs,
                              SourceLocation RParenLoc)
-    : Expr(ParenListExprClass, QualType(), VK_RValue, OK_Ordinary, false, false,
-           false, false),
+    : Expr(ParenListExprClass, QualType(), VK_RValue, OK_Ordinary),
       LParenLoc(LParenLoc), RParenLoc(RParenLoc) {
   ParenListExprBits.NumExprs = Exprs.size();
 
-  for (unsigned I = 0, N = Exprs.size(); I != N; ++I) {
-    addDependence(Exprs[I]->getDependence());
+  for (unsigned I = 0, N = Exprs.size(); I != N; ++I)
     getTrailingObjects<Stmt *>()[I] = Exprs[I];
-  }
+  setDependence(computeDependence(this));
 }
 
 ParenListExpr::ParenListExpr(EmptyShell Empty, unsigned NumExprs)
@@ -4563,10 +4396,9 @@ PseudoObjectExpr *PseudoObjectExpr::Create(const ASTContext &C, Expr *syntax,
 }
 
 PseudoObjectExpr::PseudoObjectExpr(QualType type, ExprValueKind VK,
-                                   Expr *syntax, ArrayRef<Expr*> semantics,
+                                   Expr *syntax, ArrayRef<Expr *> semantics,
                                    unsigned resultIndex)
-  : Expr(PseudoObjectExprClass, type, VK, OK_Ordinary,
-         /*filled in at end of ctor*/ false, false, false, false) {
+    : Expr(PseudoObjectExprClass, type, VK, OK_Ordinary) {
   PseudoObjectExprBits.NumSubExprs = semantics.size() + 1;
   PseudoObjectExprBits.ResultIndex = resultIndex + 1;
 
@@ -4574,13 +4406,13 @@ PseudoObjectExpr::PseudoObjectExpr(QualType type, ExprValueKind VK,
     Expr *E = (i == 0 ? syntax : semantics[i-1]);
     getSubExprsBuffer()[i] = E;
 
-    addDependence(E->getDependence());
-
     if (isa<OpaqueValueExpr>(E))
       assert(cast<OpaqueValueExpr>(E)->getSourceExpr() != nullptr &&
              "opaque-value semantic expressions for pseudo-object "
              "operations must have sources");
   }
+
+  setDependence(computeDependence(this));
 }
 
 //===----------------------------------------------------------------------===//
@@ -4607,17 +4439,14 @@ Stmt::const_child_range UnaryExprOrTypeTraitExpr::children() const {
   return const_child_range(&Argument.Ex, &Argument.Ex + 1);
 }
 
-AtomicExpr::AtomicExpr(SourceLocation BLoc, ArrayRef<Expr*> args,
-                       QualType t, AtomicOp op, SourceLocation RP)
-  : Expr(AtomicExprClass, t, VK_RValue, OK_Ordinary,
-         false, false, false, false),
-    NumSubExprs(args.size()), BuiltinLoc(BLoc), RParenLoc(RP), Op(op)
-{
+AtomicExpr::AtomicExpr(SourceLocation BLoc, ArrayRef<Expr *> args, QualType t,
+                       AtomicOp op, SourceLocation RP)
+    : Expr(AtomicExprClass, t, VK_RValue, OK_Ordinary),
+      NumSubExprs(args.size()), BuiltinLoc(BLoc), RParenLoc(RP), Op(op) {
   assert(args.size() == getNumSubExprs(op) && "wrong number of subexpressions");
-  for (unsigned i = 0; i != args.size(); i++) {
-    addDependence(args[i]->getDependence());
+  for (unsigned i = 0; i != args.size(); i++)
     SubExprs[i] = args[i];
-  }
+  setDependence(computeDependence(this));
 }
 
 unsigned AtomicExpr::getNumSubExprs(AtomicOp Op) {
diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp
index 38cdfcf752df5..cc53b663cf4e1 100644
--- a/clang/lib/AST/ExprCXX.cpp
+++ b/clang/lib/AST/ExprCXX.cpp
@@ -13,13 +13,14 @@
 #include "clang/AST/ExprCXX.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/Attr.h"
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclAccessPair.h"
 #include "clang/AST/DeclBase.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/DeclarationName.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/LambdaCapture.h"
 #include "clang/AST/NestedNameSpecifier.h"
@@ -174,9 +175,7 @@ CXXNewExpr::CXXNewExpr(bool IsGlobalNew, FunctionDecl *OperatorNew,
                        Expr *Initializer, QualType Ty,
                        TypeSourceInfo *AllocatedTypeInfo, SourceRange Range,
                        SourceRange DirectInitRange)
-    : Expr(CXXNewExprClass, Ty, VK_RValue, OK_Ordinary, Ty->isDependentType(),
-           Ty->isDependentType(), Ty->isInstantiationDependentType(),
-           Ty->containsUnexpandedParameterPack()),
+    : Expr(CXXNewExprClass, Ty, VK_RValue, OK_Ordinary),
       OperatorNew(OperatorNew), OperatorDelete(OperatorDelete),
       AllocatedTypeInfo(AllocatedTypeInfo), Range(Range),
       DirectInitRange(DirectInitRange) {
@@ -194,26 +193,13 @@ CXXNewExpr::CXXNewExpr(bool IsGlobalNew, FunctionDecl *OperatorNew,
   CXXNewExprBits.IsParenTypeId = IsParenTypeId;
   CXXNewExprBits.NumPlacementArgs = PlacementArgs.size();
 
-  if (ArraySize) {
-    if (Expr *SizeExpr = *ArraySize)
-      addDependence(SizeExpr->getDependence() & ~ExprDependence::Type);
-
+  if (ArraySize)
     getTrailingObjects<Stmt *>()[arraySizeOffset()] = *ArraySize;
-  }
-
-  if (Initializer) {
-    addDependence(Initializer->getDependence() & ~ExprDependence::Type);
-
+  if (Initializer)
     getTrailingObjects<Stmt *>()[initExprOffset()] = Initializer;
-  }
-
-  for (unsigned I = 0; I != PlacementArgs.size(); ++I) {
-    addDependence(PlacementArgs[I]->getDependence() & ~ExprDependence::Type);
-
+  for (unsigned I = 0; I != PlacementArgs.size(); ++I)
     getTrailingObjects<Stmt *>()[placementNewArgsOffset() + I] =
         PlacementArgs[I];
-  }
-
   if (IsParenTypeId)
     getTrailingObjects<SourceRange>()[0] = TypeIdParens;
 
@@ -229,6 +215,8 @@ CXXNewExpr::CXXNewExpr(bool IsGlobalNew, FunctionDecl *OperatorNew,
       this->Range.setEnd(TypeIdParens.getEnd());
     break;
   }
+
+  setDependence(computeDependence(this));
 }
 
 CXXNewExpr::CXXNewExpr(EmptyShell Empty, bool IsArray,
@@ -316,40 +304,19 @@ PseudoDestructorTypeStorage::PseudoDestructorTypeStorage(TypeSourceInfo *Info)
   Location = Info->getTypeLoc().getLocalSourceRange().getBegin();
 }
 
-CXXPseudoDestructorExpr::CXXPseudoDestructorExpr(const ASTContext &Context,
-                Expr *Base, bool isArrow, SourceLocation OperatorLoc,
-                NestedNameSpecifierLoc QualifierLoc, TypeSourceInfo *ScopeType,
-                SourceLocation ColonColonLoc, SourceLocation TildeLoc,
-                PseudoDestructorTypeStorage DestroyedType)
-  : Expr(CXXPseudoDestructorExprClass,
-         Context.BoundMemberTy,
-         VK_RValue, OK_Ordinary,
-         /*isTypeDependent=*/(Base->isTypeDependent() ||
-           (DestroyedType.getTypeSourceInfo() &&
-            DestroyedType.getTypeSourceInfo()->getType()->isDependentType())),
-         /*isValueDependent=*/Base->isValueDependent(),
-         (Base->isInstantiationDependent() ||
-          (QualifierLoc &&
-           QualifierLoc.getNestedNameSpecifier()->isInstantiationDependent()) ||
-          (ScopeType &&
-           ScopeType->getType()->isInstantiationDependentType()) ||
-          (DestroyedType.getTypeSourceInfo() &&
-           DestroyedType.getTypeSourceInfo()->getType()
-                                             ->isInstantiationDependentType())),
-         // ContainsUnexpandedParameterPack
-         (Base->containsUnexpandedParameterPack() ||
-          (QualifierLoc &&
-           QualifierLoc.getNestedNameSpecifier()
-                                        ->containsUnexpandedParameterPack()) ||
-          (ScopeType &&
-           ScopeType->getType()->containsUnexpandedParameterPack()) ||
-          (DestroyedType.getTypeSourceInfo() &&
-           DestroyedType.getTypeSourceInfo()->getType()
-                                   ->containsUnexpandedParameterPack()))),
-    Base(static_cast<Stmt *>(Base)), IsArrow(isArrow),
-    OperatorLoc(OperatorLoc), QualifierLoc(QualifierLoc),
-    ScopeType(ScopeType), ColonColonLoc(ColonColonLoc), TildeLoc(TildeLoc),
-    DestroyedType(DestroyedType) {}
+CXXPseudoDestructorExpr::CXXPseudoDestructorExpr(
+    const ASTContext &Context, Expr *Base, bool isArrow,
+    SourceLocation OperatorLoc, NestedNameSpecifierLoc QualifierLoc,
+    TypeSourceInfo *ScopeType, SourceLocation ColonColonLoc,
+    SourceLocation TildeLoc, PseudoDestructorTypeStorage DestroyedType)
+    : Expr(CXXPseudoDestructorExprClass, Context.BoundMemberTy, VK_RValue,
+           OK_Ordinary),
+      Base(static_cast<Stmt *>(Base)), IsArrow(isArrow),
+      OperatorLoc(OperatorLoc), QualifierLoc(QualifierLoc),
+      ScopeType(ScopeType), ColonColonLoc(ColonColonLoc), TildeLoc(TildeLoc),
+      DestroyedType(DestroyedType) {
+  setDependence(computeDependence(this));
+}
 
 QualType CXXPseudoDestructorExpr::getDestroyedType() const {
   if (TypeSourceInfo *TInfo = DestroyedType.getTypeSourceInfo())
@@ -439,49 +406,31 @@ OverloadExpr::OverloadExpr(StmtClass SC, const ASTContext &Context,
                            UnresolvedSetIterator End, bool KnownDependent,
                            bool KnownInstantiationDependent,
                            bool KnownContainsUnexpandedParameterPack)
-    : Expr(
-          SC, Context.OverloadTy, VK_LValue, OK_Ordinary, KnownDependent,
-          KnownDependent,
-          (KnownInstantiationDependent || NameInfo.isInstantiationDependent() ||
-           (QualifierLoc &&
-            QualifierLoc.getNestedNameSpecifier()->isInstantiationDependent())),
-          (KnownContainsUnexpandedParameterPack ||
-           NameInfo.containsUnexpandedParameterPack() ||
-           (QualifierLoc && QualifierLoc.getNestedNameSpecifier()
-                                ->containsUnexpandedParameterPack()))),
-      NameInfo(NameInfo), QualifierLoc(QualifierLoc) {
+    : Expr(SC, Context.OverloadTy, VK_LValue, OK_Ordinary), NameInfo(NameInfo),
+      QualifierLoc(QualifierLoc) {
   unsigned NumResults = End - Begin;
   OverloadExprBits.NumResults = NumResults;
   OverloadExprBits.HasTemplateKWAndArgsInfo =
       (TemplateArgs != nullptr ) || TemplateKWLoc.isValid();
 
   if (NumResults) {
-    // Determine whether this expression is type-dependent.
-    for (UnresolvedSetImpl::const_iterator I = Begin; I != End; ++I) {
-      if ((*I)->getDeclContext()->isDependentContext() ||
-          isa<UnresolvedUsingValueDecl>(*I))
-        addDependence(ExprDependence::TypeValueInstantiation);
-    }
-
     // Copy the results to the trailing array past UnresolvedLookupExpr
     // or UnresolvedMemberExpr.
     DeclAccessPair *Results = getTrailingResults();
     memcpy(Results, Begin.I, NumResults * sizeof(DeclAccessPair));
   }
 
-  // If we have explicit template arguments, check for dependent
-  // template arguments and whether they contain any unexpanded pack
-  // expansions.
   if (TemplateArgs) {
     auto Deps = TemplateArgumentDependence::None;
     getTrailingASTTemplateKWAndArgsInfo()->initializeFrom(
         TemplateKWLoc, *TemplateArgs, getTrailingTemplateArgumentLoc(), Deps);
-    addDependence(toExprDependence(Deps));
-
   } else if (TemplateKWLoc.isValid()) {
     getTrailingASTTemplateKWAndArgsInfo()->initializeFrom(TemplateKWLoc);
   }
 
+  setDependence(computeDependence(this, KnownDependent,
+                                  KnownInstantiationDependent,
+                                  KnownContainsUnexpandedParameterPack));
   if (isTypeDependent())
     setType(Context.DependentTy);
 }
@@ -498,15 +447,7 @@ DependentScopeDeclRefExpr::DependentScopeDeclRefExpr(
     QualType Ty, NestedNameSpecifierLoc QualifierLoc,
     SourceLocation TemplateKWLoc, const DeclarationNameInfo &NameInfo,
     const TemplateArgumentListInfo *Args)
-    : Expr(
-          DependentScopeDeclRefExprClass, Ty, VK_LValue, OK_Ordinary, true,
-          true,
-          (NameInfo.isInstantiationDependent() ||
-           (QualifierLoc &&
-            QualifierLoc.getNestedNameSpecifier()->isInstantiationDependent())),
-          (NameInfo.containsUnexpandedParameterPack() ||
-           (QualifierLoc && QualifierLoc.getNestedNameSpecifier()
-                                ->containsUnexpandedParameterPack()))),
+    : Expr(DependentScopeDeclRefExprClass, Ty, VK_LValue, OK_Ordinary),
       QualifierLoc(QualifierLoc), NameInfo(NameInfo) {
   DependentScopeDeclRefExprBits.HasTemplateKWAndArgsInfo =
       (Args != nullptr) || TemplateKWLoc.isValid();
@@ -514,12 +455,11 @@ DependentScopeDeclRefExpr::DependentScopeDeclRefExpr(
     auto Deps = TemplateArgumentDependence::None;
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc, *Args, getTrailingObjects<TemplateArgumentLoc>(), Deps);
-    if (Deps & TemplateArgumentDependence::UnexpandedPack)
-      addDependence(ExprDependence::UnexpandedPack);
   } else if (TemplateKWLoc.isValid()) {
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
   }
+  setDependence(computeDependence(this));
 }
 
 DependentScopeDeclRefExpr *DependentScopeDeclRefExpr::Create(
@@ -637,7 +577,7 @@ SourceRange CXXOperatorCallExpr::getSourceRangeImpl() const {
       // Postfix operator
       return SourceRange(getArg(0)->getBeginLoc(), getOperatorLoc());
   } else if (Kind == OO_Arrow) {
-    return getArg(0)->getSourceRange();
+    return SourceRange(getArg(0)->getBeginLoc(), getOperatorLoc());
   } else if (Kind == OO_Call) {
     return SourceRange(getArg(0)->getBeginLoc(), getRParenLoc());
   } else if (Kind == OO_Subscript) {
@@ -959,17 +899,19 @@ const IdentifierInfo *UserDefinedLiteral::getUDSuffix() const {
   return cast<FunctionDecl>(getCalleeDecl())->getLiteralIdentifier();
 }
 
-CXXDefaultInitExpr::CXXDefaultInitExpr(const ASTContext &Ctx, SourceLocation Loc,
-                                       FieldDecl *Field, QualType Ty,
-                                       DeclContext *UsedContext)
+CXXDefaultInitExpr::CXXDefaultInitExpr(const ASTContext &Ctx,
+                                       SourceLocation Loc, FieldDecl *Field,
+                                       QualType Ty, DeclContext *UsedContext)
     : Expr(CXXDefaultInitExprClass, Ty.getNonLValueExprType(Ctx),
-           Ty->isLValueReferenceType() ? VK_LValue : Ty->isRValueReferenceType()
-                                                        ? VK_XValue
-                                                        : VK_RValue,
-           /*FIXME*/ OK_Ordinary, false, false, false, false),
+           Ty->isLValueReferenceType()
+               ? VK_LValue
+               : Ty->isRValueReferenceType() ? VK_XValue : VK_RValue,
+           /*FIXME*/ OK_Ordinary),
       Field(Field), UsedContext(UsedContext) {
   CXXDefaultInitExprBits.Loc = Loc;
   assert(Field->hasInClassInitializer());
+
+  setDependence(ExprDependence::None);
 }
 
 CXXTemporary *CXXTemporary::Create(const ASTContext &C,
@@ -1067,11 +1009,8 @@ CXXConstructExpr::CXXConstructExpr(
     bool ListInitialization, bool StdInitListInitialization,
     bool ZeroInitialization, ConstructionKind ConstructKind,
     SourceRange ParenOrBraceRange)
-    : Expr(SC, Ty, VK_RValue, OK_Ordinary, Ty->isDependentType(),
-           Ty->isDependentType(), Ty->isInstantiationDependentType(),
-           Ty->containsUnexpandedParameterPack()),
-      Constructor(Ctor), ParenOrBraceRange(ParenOrBraceRange),
-      NumArgs(Args.size()) {
+    : Expr(SC, Ty, VK_RValue, OK_Ordinary), Constructor(Ctor),
+      ParenOrBraceRange(ParenOrBraceRange), NumArgs(Args.size()) {
   CXXConstructExprBits.Elidable = Elidable;
   CXXConstructExprBits.HadMultipleCandidates = HadMultipleCandidates;
   CXXConstructExprBits.ListInitialization = ListInitialization;
@@ -1083,10 +1022,10 @@ CXXConstructExpr::CXXConstructExpr(
   Stmt **TrailingArgs = getTrailingArgs();
   for (unsigned I = 0, N = Args.size(); I != N; ++I) {
     assert(Args[I] && "NULL argument in CXXConstructExpr!");
-    addDependence(Args[I]->getDependence() & ~ExprDependence::Type);
-
     TrailingArgs[I] = Args[I];
   }
+
+  setDependence(computeDependence(this));
 }
 
 CXXConstructExpr::CXXConstructExpr(StmtClass SC, EmptyShell Empty,
@@ -1139,9 +1078,7 @@ LambdaExpr::LambdaExpr(QualType T, SourceRange IntroducerRange,
                        bool ExplicitResultType, ArrayRef<Expr *> CaptureInits,
                        SourceLocation ClosingBrace,
                        bool ContainsUnexpandedParameterPack)
-    : Expr(LambdaExprClass, T, VK_RValue, OK_Ordinary, T->isDependentType(),
-           T->isDependentType(), T->isDependentType(),
-           ContainsUnexpandedParameterPack),
+    : Expr(LambdaExprClass, T, VK_RValue, OK_Ordinary),
       IntroducerRange(IntroducerRange), CaptureDefaultLoc(CaptureDefaultLoc),
       NumCaptures(Captures.size()), CaptureDefault(CaptureDefault),
       ExplicitParams(ExplicitParams), ExplicitResultType(ExplicitResultType),
@@ -1173,6 +1110,8 @@ LambdaExpr::LambdaExpr(QualType T, SourceRange IntroducerRange,
 
   // Copy the body of the lambda.
   *Stored++ = getCallOperator()->getBody();
+
+  setDependence(computeDependence(this, ContainsUnexpandedParameterPack));
 }
 
 LambdaExpr *LambdaExpr::Create(
@@ -1324,19 +1263,13 @@ CXXUnresolvedConstructExpr::CXXUnresolvedConstructExpr(TypeSourceInfo *TSI,
                 ? VK_LValue
                 : TSI->getType()->isRValueReferenceType() ? VK_XValue
                                                           : VK_RValue),
-           OK_Ordinary,
-           TSI->getType()->isDependentType() ||
-               TSI->getType()->getContainedDeducedType(),
-           true, true, TSI->getType()->containsUnexpandedParameterPack()),
+           OK_Ordinary),
       TSI(TSI), LParenLoc(LParenLoc), RParenLoc(RParenLoc) {
   CXXUnresolvedConstructExprBits.NumArgs = Args.size();
   auto **StoredArgs = getTrailingObjects<Expr *>();
-  for (unsigned I = 0; I != Args.size(); ++I) {
-    if (Args[I]->containsUnexpandedParameterPack())
-      addDependence(ExprDependence::UnexpandedPack);
-
+  for (unsigned I = 0; I != Args.size(); ++I)
     StoredArgs[I] = Args[I];
-  }
+  setDependence(computeDependence(this));
 }
 
 CXXUnresolvedConstructExpr *CXXUnresolvedConstructExpr::Create(
@@ -1364,11 +1297,7 @@ CXXDependentScopeMemberExpr::CXXDependentScopeMemberExpr(
     DeclarationNameInfo MemberNameInfo,
     const TemplateArgumentListInfo *TemplateArgs)
     : Expr(CXXDependentScopeMemberExprClass, Ctx.DependentTy, VK_LValue,
-           OK_Ordinary, true, true, true,
-           ((Base && Base->containsUnexpandedParameterPack()) ||
-            (QualifierLoc && QualifierLoc.getNestedNameSpecifier()
-                                 ->containsUnexpandedParameterPack()) ||
-            MemberNameInfo.containsUnexpandedParameterPack())),
+           OK_Ordinary),
       Base(Base), BaseType(BaseType), QualifierLoc(QualifierLoc),
       MemberNameInfo(MemberNameInfo) {
   CXXDependentScopeMemberExprBits.IsArrow = IsArrow;
@@ -1383,8 +1312,6 @@ CXXDependentScopeMemberExpr::CXXDependentScopeMemberExpr(
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc, *TemplateArgs, getTrailingObjects<TemplateArgumentLoc>(),
         Deps);
-    if (Deps & TemplateArgumentDependence::UnexpandedPack)
-      addDependence(ExprDependence::UnexpandedPack);
   } else if (TemplateKWLoc.isValid()) {
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
@@ -1392,6 +1319,7 @@ CXXDependentScopeMemberExpr::CXXDependentScopeMemberExpr(
 
   if (hasFirstQualifierFoundInScope())
     *getTrailingObjects<NamedDecl *>() = FirstQualifierFoundInScope;
+  setDependence(computeDependence(this));
 }
 
 CXXDependentScopeMemberExpr::CXXDependentScopeMemberExpr(
@@ -1573,16 +1501,15 @@ SizeOfPackExpr *SizeOfPackExpr::CreateDeserialized(ASTContext &Context,
   return new (Storage) SizeOfPackExpr(EmptyShell(), NumPartialArgs);
 }
 
-SubstNonTypeTemplateParmPackExpr::
-SubstNonTypeTemplateParmPackExpr(QualType T,
-                                 ExprValueKind ValueKind,
-                                 NonTypeTemplateParmDecl *Param,
-                                 SourceLocation NameLoc,
-                                 const TemplateArgument &ArgPack)
-    : Expr(SubstNonTypeTemplateParmPackExprClass, T, ValueKind, OK_Ordinary,
-           true, true, true, true),
+SubstNonTypeTemplateParmPackExpr::SubstNonTypeTemplateParmPackExpr(
+    QualType T, ExprValueKind ValueKind, NonTypeTemplateParmDecl *Param,
+    SourceLocation NameLoc, const TemplateArgument &ArgPack)
+    : Expr(SubstNonTypeTemplateParmPackExprClass, T, ValueKind, OK_Ordinary),
       Param(Param), Arguments(ArgPack.pack_begin()),
-      NumArguments(ArgPack.pack_size()), NameLoc(NameLoc) {}
+      NumArguments(ArgPack.pack_size()), NameLoc(NameLoc) {
+  setDependence(ExprDependence::TypeValueInstantiation |
+                ExprDependence::UnexpandedPack);
+}
 
 TemplateArgument SubstNonTypeTemplateParmPackExpr::getArgumentPack() const {
   return TemplateArgument(llvm::makeArrayRef(Arguments, NumArguments));
@@ -1592,12 +1519,13 @@ FunctionParmPackExpr::FunctionParmPackExpr(QualType T, VarDecl *ParamPack,
                                            SourceLocation NameLoc,
                                            unsigned NumParams,
                                            VarDecl *const *Params)
-    : Expr(FunctionParmPackExprClass, T, VK_LValue, OK_Ordinary, true, true,
-           true, true),
+    : Expr(FunctionParmPackExprClass, T, VK_LValue, OK_Ordinary),
       ParamPack(ParamPack), NameLoc(NameLoc), NumParameters(NumParams) {
   if (Params)
     std::uninitialized_copy(Params, Params + NumParams,
                             getTrailingObjects<VarDecl *>());
+  setDependence(ExprDependence::TypeValueInstantiation |
+                ExprDependence::UnexpandedPack);
 }
 
 FunctionParmPackExpr *
@@ -1619,16 +1547,14 @@ MaterializeTemporaryExpr::MaterializeTemporaryExpr(
     QualType T, Expr *Temporary, bool BoundToLvalueReference,
     LifetimeExtendedTemporaryDecl *MTD)
     : Expr(MaterializeTemporaryExprClass, T,
-           BoundToLvalueReference ? VK_LValue : VK_XValue, OK_Ordinary,
-           Temporary->isTypeDependent(), Temporary->isValueDependent(),
-           Temporary->isInstantiationDependent(),
-           Temporary->containsUnexpandedParameterPack()) {
+           BoundToLvalueReference ? VK_LValue : VK_XValue, OK_Ordinary) {
   if (MTD) {
     State = MTD;
     MTD->ExprWithTemporary = Temporary;
     return;
   }
   State = Temporary;
+  setDependence(computeDependence(this));
 }
 
 void MaterializeTemporaryExpr::setExtendingDecl(ValueDecl *ExtendedBy,
@@ -1650,25 +1576,18 @@ void MaterializeTemporaryExpr::setExtendingDecl(ValueDecl *ExtendedBy,
 
 TypeTraitExpr::TypeTraitExpr(QualType T, SourceLocation Loc, TypeTrait Kind,
                              ArrayRef<TypeSourceInfo *> Args,
-                             SourceLocation RParenLoc,
-                             bool Value)
-    : Expr(TypeTraitExprClass, T, VK_RValue, OK_Ordinary,
-           /*TypeDependent=*/false,
-           /*ValueDependent=*/false,
-           /*InstantiationDependent=*/false,
-           /*ContainsUnexpandedParameterPack=*/false),
-      Loc(Loc), RParenLoc(RParenLoc) {
+                             SourceLocation RParenLoc, bool Value)
+    : Expr(TypeTraitExprClass, T, VK_RValue, OK_Ordinary), Loc(Loc),
+      RParenLoc(RParenLoc) {
   TypeTraitExprBits.Kind = Kind;
   TypeTraitExprBits.Value = Value;
   TypeTraitExprBits.NumArgs = Args.size();
 
   auto **ToArgs = getTrailingObjects<TypeSourceInfo *>();
-
-  for (unsigned I = 0, N = Args.size(); I != N; ++I) {
-    addDependence(toExprDependence(Args[I]->getType()->getDependence()) &
-                  ~ExprDependence::Type);
+  for (unsigned I = 0, N = Args.size(); I != N; ++I)
     ToArgs[I] = Args[I];
-  }
+
+  setDependence(computeDependence(this));
 }
 
 TypeTraitExpr *TypeTraitExpr::Create(const ASTContext &C, QualType T,
@@ -1720,4 +1639,4 @@ CUDAKernelCallExpr *CUDAKernelCallExpr::CreateEmpty(const ASTContext &Ctx,
   void *Mem = Ctx.Allocate(sizeof(CUDAKernelCallExpr) + SizeOfTrailingObjects,
                            alignof(CUDAKernelCallExpr));
   return new (Mem) CUDAKernelCallExpr(NumArgs, Empty);
-}
+}
\ No newline at end of file
diff --git a/clang/lib/AST/ExprConcepts.cpp b/clang/lib/AST/ExprConcepts.cpp
index 42cc4576562e4..b3a4bd9215d5c 100644
--- a/clang/lib/AST/ExprConcepts.cpp
+++ b/clang/lib/AST/ExprConcepts.cpp
@@ -13,10 +13,11 @@
 #include "clang/AST/ExprConcepts.h"
 #include "clang/AST/ASTConcept.h"
 #include "clang/AST/ASTContext.h"
+#include "clang/AST/ComputeDependence.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/DeclarationName.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/NestedNameSpecifier.h"
 #include "clang/AST/TemplateBase.h"
@@ -29,39 +30,28 @@
 
 using namespace clang;
 
-ConceptSpecializationExpr::ConceptSpecializationExpr(const ASTContext &C,
-    NestedNameSpecifierLoc NNS, SourceLocation TemplateKWLoc,
-    DeclarationNameInfo ConceptNameInfo, NamedDecl *FoundDecl,
-    ConceptDecl *NamedConcept, const ASTTemplateArgumentListInfo *ArgsAsWritten,
+ConceptSpecializationExpr::ConceptSpecializationExpr(
+    const ASTContext &C, NestedNameSpecifierLoc NNS,
+    SourceLocation TemplateKWLoc, DeclarationNameInfo ConceptNameInfo,
+    NamedDecl *FoundDecl, ConceptDecl *NamedConcept,
+    const ASTTemplateArgumentListInfo *ArgsAsWritten,
     ArrayRef<TemplateArgument> ConvertedArgs,
     const ConstraintSatisfaction *Satisfaction)
-    : Expr(ConceptSpecializationExprClass, C.BoolTy, VK_RValue, OK_Ordinary,
-           /*TypeDependent=*/false,
-           // All the flags below are set in setTemplateArguments.
-           /*ValueDependent=*/!Satisfaction, /*InstantiationDependent=*/false,
-           /*ContainsUnexpandedParameterPacks=*/false),
+    : Expr(ConceptSpecializationExprClass, C.BoolTy, VK_RValue, OK_Ordinary),
       ConceptReference(NNS, TemplateKWLoc, ConceptNameInfo, FoundDecl,
                        NamedConcept, ArgsAsWritten),
       NumTemplateArgs(ConvertedArgs.size()),
-      Satisfaction(Satisfaction ?
-                   ASTConstraintSatisfaction::Create(C, *Satisfaction) :
-                   nullptr) {
+      Satisfaction(Satisfaction
+                       ? ASTConstraintSatisfaction::Create(C, *Satisfaction)
+                       : nullptr) {
   setTemplateArguments(ConvertedArgs);
-  auto Deps = TemplateArgumentDependence::None;
-  const auto InterestingDeps = TemplateArgumentDependence::Instantiation |
-                               TemplateArgumentDependence::UnexpandedPack;
-  for (const TemplateArgumentLoc& ArgLoc : ArgsAsWritten->arguments()) {
-    Deps |= ArgLoc.getArgument().getDependence() & InterestingDeps;
-    if (Deps == InterestingDeps)
-      break;
-  }
+  setDependence(computeDependence(this, /*ValueDependent=*/!Satisfaction));
 
   // Currently guaranteed by the fact concepts can only be at namespace-scope.
   assert(!NestedNameSpec ||
          (!NestedNameSpec.getNestedNameSpecifier()->isInstantiationDependent() &&
           !NestedNameSpec.getNestedNameSpecifier()
               ->containsUnexpandedParameterPack()));
-  addDependence(toExprDependence(Deps));
   assert((!isValueDependent() || isInstantiationDependent()) &&
          "should not be value-dependent");
 }
@@ -101,18 +91,23 @@ ConceptSpecializationExpr::ConceptSpecializationExpr(
     ArrayRef<TemplateArgument> ConvertedArgs,
     const ConstraintSatisfaction *Satisfaction, bool Dependent,
     bool ContainsUnexpandedParameterPack)
-    : Expr(ConceptSpecializationExprClass, C.BoolTy, VK_RValue, OK_Ordinary,
-           /*TypeDependent=*/false,
-           /*ValueDependent=*/!Satisfaction, Dependent,
-           ContainsUnexpandedParameterPack),
+    : Expr(ConceptSpecializationExprClass, C.BoolTy, VK_RValue, OK_Ordinary),
       ConceptReference(NestedNameSpecifierLoc(), SourceLocation(),
-                       DeclarationNameInfo(), NamedConcept,
-                       NamedConcept, nullptr),
+                       DeclarationNameInfo(), NamedConcept, NamedConcept,
+                       nullptr),
       NumTemplateArgs(ConvertedArgs.size()),
-      Satisfaction(Satisfaction ?
-                   ASTConstraintSatisfaction::Create(C, *Satisfaction) :
-                   nullptr) {
+      Satisfaction(Satisfaction
+                       ? ASTConstraintSatisfaction::Create(C, *Satisfaction)
+                       : nullptr) {
   setTemplateArguments(ConvertedArgs);
+  ExprDependence D = ExprDependence::None;
+  if (!Satisfaction)
+    D |= ExprDependence::Value;
+  if (Dependent)
+    D |= ExprDependence::Instantiation;
+  if (ContainsUnexpandedParameterPack)
+    D |= ExprDependence::UnexpandedPack;
+  setDependence(D);
 }
 
 ConceptSpecializationExpr *
@@ -151,11 +146,9 @@ RequiresExpr::RequiresExpr(ASTContext &C, SourceLocation RequiresKWLoc,
                            ArrayRef<ParmVarDecl *> LocalParameters,
                            ArrayRef<concepts::Requirement *> Requirements,
                            SourceLocation RBraceLoc)
-  : Expr(RequiresExprClass, C.BoolTy, VK_RValue, OK_Ordinary,
-         /*TD=*/false, /*VD=*/false, /*ID=*/false,
-         /*ContainsUnexpandedParameterPack=*/false),
-    NumLocalParameters(LocalParameters.size()),
-    NumRequirements(Requirements.size()), Body(Body), RBraceLoc(RBraceLoc) {
+    : Expr(RequiresExprClass, C.BoolTy, VK_RValue, OK_Ordinary),
+      NumLocalParameters(LocalParameters.size()),
+      NumRequirements(Requirements.size()), Body(Body), RBraceLoc(RBraceLoc) {
   RequiresExprBits.IsSatisfied = false;
   RequiresExprBits.RequiresKWLoc = RequiresKWLoc;
   bool Dependent = false;
@@ -180,6 +173,7 @@ RequiresExpr::RequiresExpr(ASTContext &C, SourceLocation RequiresKWLoc,
   std::copy(Requirements.begin(), Requirements.end(),
             getTrailingObjects<concepts::Requirement *>());
   RequiresExprBits.IsSatisfied |= Dependent;
+  // FIXME: move the computing dependency logic to ComputeDependence.h
   if (ContainsUnexpandedParameterPack)
     addDependence(ExprDependence::UnexpandedPack);
   // FIXME: this is incorrect for cases where we have a non-dependent
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 5bb9fc319d485..f5c37ad44ebd1 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -674,6 +674,7 @@ namespace {
     None,
     Bases,
     AfterBases,
+    AfterFields,
     Destroying,
     DestroyingBases
   };
@@ -821,6 +822,9 @@ namespace {
       void finishedConstructingBases() {
         EI.ObjectsUnderConstruction[Object] = ConstructionPhase::AfterBases;
       }
+      void finishedConstructingFields() {
+        EI.ObjectsUnderConstruction[Object] = ConstructionPhase::AfterFields;
+      }
       ~EvaluatingConstructorRAII() {
         if (DidInsert) EI.ObjectsUnderConstruction.erase(Object);
       }
@@ -5121,6 +5125,7 @@ static Optional<DynamicType> ComputeDynamicType(EvalInfo &Info, const Expr *E,
 
     case ConstructionPhase::None:
     case ConstructionPhase::AfterBases:
+    case ConstructionPhase::AfterFields:
     case ConstructionPhase::Destroying:
       // We've finished constructing the base classes and not yet started
       // destroying them again, so this is the dynamic type.
@@ -5339,7 +5344,10 @@ static bool HandleDynamicCast(EvalInfo &Info, const ExplicitCastExpr *E,
 
 namespace {
 struct StartLifetimeOfUnionMemberHandler {
+  EvalInfo &Info;
+  const Expr *LHSExpr;
   const FieldDecl *Field;
+  bool DuringInit;
 
   static const AccessKinds AccessKind = AK_Assign;
 
@@ -5355,9 +5363,21 @@ struct StartLifetimeOfUnionMemberHandler {
     //  * No variant members' lifetimes begin
     //  * All scalar subobjects whose lifetimes begin have indeterminate values
     assert(SubobjType->isUnionType());
-    if (!declaresSameEntity(Subobj.getUnionField(), Field) ||
-        !Subobj.getUnionValue().hasValue())
-      Subobj.setUnion(Field, getDefaultInitValue(Field->getType()));
+    if (declaresSameEntity(Subobj.getUnionField(), Field)) {
+      // This union member is already active. If it's also in-lifetime, there's
+      // nothing to do.
+      if (Subobj.getUnionValue().hasValue())
+        return true;
+    } else if (DuringInit) {
+      // We're currently in the process of initializing a different union
+      // member.  If we carried on, that initialization would attempt to
+      // store to an inactive union member, resulting in undefined behavior.
+      Info.FFDiag(LHSExpr,
+                  diag::note_constexpr_union_member_change_during_init);
+      return false;
+    }
+
+    Subobj.setUnion(Field, getDefaultInitValue(Field->getType()));
     return true;
   }
   bool found(APSInt &Value, QualType SubobjType) {
@@ -5460,7 +5480,10 @@ static bool HandleUnionActiveMemberChange(EvalInfo &Info, const Expr *LHSExpr,
     SubobjectDesignator D = LHS.Designator;
     D.truncate(Info.Ctx, LHS.Base, LengthAndField.first);
 
-    StartLifetimeOfUnionMemberHandler StartLifetime{LengthAndField.second};
+    bool DuringInit = Info.isEvaluatingCtorDtor(LHS.Base, D.Entries) ==
+                      ConstructionPhase::AfterBases;
+    StartLifetimeOfUnionMemberHandler StartLifetime{
+        Info, LHSExpr, LengthAndField.second, DuringInit};
     if (!findSubobject(Info, LHSExpr, Obj, D, StartLifetime))
       return false;
   }
@@ -5778,6 +5801,8 @@ static bool HandleConstructorCall(const Expr *E, const LValue &This,
     }
   }
 
+  EvalObj.finishedConstructingFields();
+
   return Success &&
          EvaluateStmt(Ret, Info, Definition->getBody()) != ESR_Failed &&
          LifetimeExtendedScope.destroy();
@@ -9180,6 +9205,8 @@ bool RecordExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
     }
   }
 
+  EvalObj.finishedConstructingFields();
+
   return Success;
 }
 
diff --git a/clang/lib/AST/ExprObjC.cpp b/clang/lib/AST/ExprObjC.cpp
index 6d98429bc89dc..662bc325f12c8 100644
--- a/clang/lib/AST/ExprObjC.cpp
+++ b/clang/lib/AST/ExprObjC.cpp
@@ -12,7 +12,8 @@
 
 #include "clang/AST/ExprObjC.h"
 #include "clang/AST/ASTContext.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/ComputeDependence.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/SelectorLocationsKind.h"
 #include "clang/AST/Type.h"
 #include "clang/AST/TypeLoc.h"
@@ -26,14 +27,13 @@ using namespace clang;
 
 ObjCArrayLiteral::ObjCArrayLiteral(ArrayRef<Expr *> Elements, QualType T,
                                    ObjCMethodDecl *Method, SourceRange SR)
-    : Expr(ObjCArrayLiteralClass, T, VK_RValue, OK_Ordinary, false, false,
-           false, false),
+    : Expr(ObjCArrayLiteralClass, T, VK_RValue, OK_Ordinary),
       NumElements(Elements.size()), Range(SR), ArrayWithObjectsMethod(Method) {
   Expr **SaveElements = getElements();
-  for (unsigned I = 0, N = Elements.size(); I != N; ++I) {
-    addDependence(turnTypeToValueDependence(Elements[I]->getDependence()));
+  for (unsigned I = 0, N = Elements.size(); I != N; ++I)
     SaveElements[I] = Elements[I];
-  }
+
+  setDependence(computeDependence(this));
 }
 
 ObjCArrayLiteral *ObjCArrayLiteral::Create(const ASTContext &C,
@@ -54,20 +54,13 @@ ObjCDictionaryLiteral::ObjCDictionaryLiteral(ArrayRef<ObjCDictionaryElement> VK,
                                              bool HasPackExpansions, QualType T,
                                              ObjCMethodDecl *method,
                                              SourceRange SR)
-    : Expr(ObjCDictionaryLiteralClass, T, VK_RValue, OK_Ordinary, false, false,
-           false, false),
+    : Expr(ObjCDictionaryLiteralClass, T, VK_RValue, OK_Ordinary),
       NumElements(VK.size()), HasPackExpansions(HasPackExpansions), Range(SR),
       DictWithObjectsMethod(method) {
   KeyValuePair *KeyValues = getTrailingObjects<KeyValuePair>();
   ExpansionData *Expansions =
       HasPackExpansions ? getTrailingObjects<ExpansionData>() : nullptr;
   for (unsigned I = 0; I < NumElements; I++) {
-    auto Deps = turnTypeToValueDependence(VK[I].Key->getDependence() |
-                                          VK[I].Value->getDependence());
-    if (VK[I].EllipsisLoc.isValid())
-      Deps &= ~ExprDependence::UnexpandedPack;
-    addDependence(Deps);
-
     KeyValues[I].Key = VK[I].Key;
     KeyValues[I].Value = VK[I].Value;
     if (Expansions) {
@@ -78,6 +71,7 @@ ObjCDictionaryLiteral::ObjCDictionaryLiteral(ArrayRef<ObjCDictionaryElement> VK,
         Expansions[I].NumExpansionsPlusOne = 0;
     }
   }
+  setDependence(computeDependence(this));
 }
 
 ObjCDictionaryLiteral *
@@ -117,10 +111,7 @@ ObjCMessageExpr::ObjCMessageExpr(QualType T, ExprValueKind VK,
                                  SelectorLocationsKind SelLocsK,
                                  ObjCMethodDecl *Method, ArrayRef<Expr *> Args,
                                  SourceLocation RBracLoc, bool isImplicit)
-    : Expr(ObjCMessageExprClass, T, VK, OK_Ordinary,
-           /*TypeDependent=*/false, /*ValueDependent=*/false,
-           /*InstantiationDependent=*/false,
-           /*ContainsUnexpandedParameterPack=*/false),
+    : Expr(ObjCMessageExprClass, T, VK, OK_Ordinary),
       SelectorOrMethod(
           reinterpret_cast<uintptr_t>(Method ? Method : Sel.getAsOpaquePtr())),
       Kind(IsInstanceSuper ? SuperInstance : SuperClass),
@@ -129,6 +120,7 @@ ObjCMessageExpr::ObjCMessageExpr(QualType T, ExprValueKind VK,
       RBracLoc(RBracLoc) {
   initArgsAndSelLocs(Args, SelLocs, SelLocsK);
   setReceiverPointer(SuperType.getAsOpaquePtr());
+  setDependence(computeDependence(this));
 }
 
 ObjCMessageExpr::ObjCMessageExpr(QualType T, ExprValueKind VK,
@@ -138,15 +130,14 @@ ObjCMessageExpr::ObjCMessageExpr(QualType T, ExprValueKind VK,
                                  SelectorLocationsKind SelLocsK,
                                  ObjCMethodDecl *Method, ArrayRef<Expr *> Args,
                                  SourceLocation RBracLoc, bool isImplicit)
-    : Expr(ObjCMessageExprClass, T, VK, OK_Ordinary, T->isDependentType(),
-           T->isDependentType(), T->isInstantiationDependentType(),
-           T->containsUnexpandedParameterPack()),
+    : Expr(ObjCMessageExprClass, T, VK, OK_Ordinary),
       SelectorOrMethod(
           reinterpret_cast<uintptr_t>(Method ? Method : Sel.getAsOpaquePtr())),
       Kind(Class), HasMethod(Method != nullptr), IsDelegateInitCall(false),
       IsImplicit(isImplicit), LBracLoc(LBracLoc), RBracLoc(RBracLoc) {
   initArgsAndSelLocs(Args, SelLocs, SelLocsK);
   setReceiverPointer(Receiver);
+  setDependence(computeDependence(this));
 }
 
 ObjCMessageExpr::ObjCMessageExpr(QualType T, ExprValueKind VK,
@@ -155,16 +146,14 @@ ObjCMessageExpr::ObjCMessageExpr(QualType T, ExprValueKind VK,
                                  SelectorLocationsKind SelLocsK,
                                  ObjCMethodDecl *Method, ArrayRef<Expr *> Args,
                                  SourceLocation RBracLoc, bool isImplicit)
-    : Expr(ObjCMessageExprClass, T, VK, OK_Ordinary,
-           Receiver->isTypeDependent(), Receiver->isTypeDependent(),
-           Receiver->isInstantiationDependent(),
-           Receiver->containsUnexpandedParameterPack()),
+    : Expr(ObjCMessageExprClass, T, VK, OK_Ordinary),
       SelectorOrMethod(
           reinterpret_cast<uintptr_t>(Method ? Method : Sel.getAsOpaquePtr())),
       Kind(Instance), HasMethod(Method != nullptr), IsDelegateInitCall(false),
       IsImplicit(isImplicit), LBracLoc(LBracLoc), RBracLoc(RBracLoc) {
   initArgsAndSelLocs(Args, SelLocs, SelLocsK);
   setReceiverPointer(Receiver);
+  setDependence(computeDependence(this));
 }
 
 void ObjCMessageExpr::initArgsAndSelLocs(ArrayRef<Expr *> Args,
@@ -172,10 +161,8 @@ void ObjCMessageExpr::initArgsAndSelLocs(ArrayRef<Expr *> Args,
                                          SelectorLocationsKind SelLocsK) {
   setNumArgs(Args.size());
   Expr **MyArgs = getArgs();
-  for (unsigned I = 0; I != Args.size(); ++I) {
-    addDependence(Args[I]->getDependence());
+  for (unsigned I = 0; I != Args.size(); ++I)
     MyArgs[I] = Args[I];
-  }
 
   SelLocsKind = SelLocsK;
   if (!isImplicit()) {
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index db5aff3c077f5..5fb71b48a6538 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -1580,14 +1580,8 @@ static GlobalDecl getParentOfLocalEntity(const DeclContext *DC) {
     GD = GlobalDecl(CD, Ctor_Complete);
   else if (auto *DD = dyn_cast<CXXDestructorDecl>(DC))
     GD = GlobalDecl(DD, Dtor_Complete);
-  else {
-    auto *FD = cast<FunctionDecl>(DC);
-    // Local variables can only exist in real kernels.
-    if (FD->hasAttr<CUDAGlobalAttr>())
-      GD = GlobalDecl(FD, KernelReferenceKind::Kernel);
-    else
-      GD = GlobalDecl(FD);
-  }
+  else
+    GD = GlobalDecl(cast<FunctionDecl>(DC));
   return GD;
 }
 
diff --git a/clang/lib/AST/Mangle.cpp b/clang/lib/AST/Mangle.cpp
index cc46994c1003d..30078fcb243df 100644
--- a/clang/lib/AST/Mangle.cpp
+++ b/clang/lib/AST/Mangle.cpp
@@ -444,7 +444,7 @@ class ASTNameGenerator::Implementation {
       else if (const auto *DtorD = dyn_cast<CXXDestructorDecl>(D))
         GD = GlobalDecl(DtorD, Dtor_Complete);
       else if (D->hasAttr<CUDAGlobalAttr>())
-        GD = GlobalDecl::getDefaultKernelReference(cast<FunctionDecl>(D));
+        GD = GlobalDecl(cast<FunctionDecl>(D));
       else
         GD = GlobalDecl(D);
       MC->mangleName(GD, OS);
diff --git a/clang/lib/AST/NestedNameSpecifier.cpp b/clang/lib/AST/NestedNameSpecifier.cpp
index 8cd65a857beb4..af53c7fd9ba42 100644
--- a/clang/lib/AST/NestedNameSpecifier.cpp
+++ b/clang/lib/AST/NestedNameSpecifier.cpp
@@ -16,7 +16,7 @@
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/PrettyPrinter.h"
 #include "clang/AST/TemplateName.h"
 #include "clang/AST/Type.h"
diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp
index e68a5d6820a90..a957890670562 100644
--- a/clang/lib/AST/OpenMPClause.cpp
+++ b/clang/lib/AST/OpenMPClause.cpp
@@ -145,6 +145,7 @@ const OMPClauseWithPreInit *OMPClauseWithPreInit::get(const OMPClause *C) {
   case OMPC_nontemporal:
   case OMPC_order:
   case OMPC_destroy:
+  case OMPC_detach:
     break;
   }
 
@@ -231,6 +232,7 @@ const OMPClauseWithPostUpdate *OMPClauseWithPostUpdate::get(const OMPClause *C)
   case OMPC_nontemporal:
   case OMPC_order:
   case OMPC_destroy:
+  case OMPC_detach:
     break;
   }
 
@@ -1294,6 +1296,12 @@ void OMPClausePrinter::VisitOMPCollapseClause(OMPCollapseClause *Node) {
   OS << ")";
 }
 
+void OMPClausePrinter::VisitOMPDetachClause(OMPDetachClause *Node) {
+  OS << "detach(";
+  Node->getEventHandler()->printPretty(OS, nullptr, Policy, 0);
+  OS << ")";
+}
+
 void OMPClausePrinter::VisitOMPDefaultClause(OMPDefaultClause *Node) {
   OS << "default("
      << getOpenMPSimpleClauseTypeName(OMPC_default,
@@ -1425,6 +1433,11 @@ void OMPClausePrinter::VisitOMPSIMDClause(OMPSIMDClause *) { OS << "simd"; }
 
 void OMPClausePrinter::VisitOMPDeviceClause(OMPDeviceClause *Node) {
   OS << "device(";
+  OpenMPDeviceClauseModifier Modifier = Node->getModifier();
+  if (Modifier != OMPC_DEVICE_unknown) {
+    OS << getOpenMPSimpleClauseTypeName(Node->getClauseKind(), Modifier)
+       << ": ";
+  }
   Node->getDevice()->printPretty(OS, nullptr, Policy, 0);
   OS << ")";
 }
diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp
index 9f11983702359..8d43491ea8f4c 100644
--- a/clang/lib/AST/StmtProfile.cpp
+++ b/clang/lib/AST/StmtProfile.cpp
@@ -472,6 +472,11 @@ void OMPClauseProfiler::VisitOMPCollapseClause(const OMPCollapseClause *C) {
     Profiler->VisitStmt(C->getNumForLoops());
 }
 
+void OMPClauseProfiler::VisitOMPDetachClause(const OMPDetachClause *C) {
+  if (Expr *Evt = C->getEventHandler())
+    Profiler->VisitStmt(Evt);
+}
+
 void OMPClauseProfiler::VisitOMPDefaultClause(const OMPDefaultClause *C) { }
 
 void OMPClauseProfiler::VisitOMPProcBindClause(const OMPProcBindClause *C) { }
diff --git a/clang/lib/AST/TemplateBase.cpp b/clang/lib/AST/TemplateBase.cpp
index 3c550bddaff8c..c122213766915 100644
--- a/clang/lib/AST/TemplateBase.cpp
+++ b/clang/lib/AST/TemplateBase.cpp
@@ -16,7 +16,7 @@
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclBase.h"
 #include "clang/AST/DeclTemplate.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/ExprCXX.h"
 #include "clang/AST/PrettyPrinter.h"
diff --git a/clang/lib/AST/TemplateName.cpp b/clang/lib/AST/TemplateName.cpp
index 3b8ae06c63397..40a8736ae1afd 100644
--- a/clang/lib/AST/TemplateName.cpp
+++ b/clang/lib/AST/TemplateName.cpp
@@ -14,7 +14,7 @@
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclBase.h"
 #include "clang/AST/DeclTemplate.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/NestedNameSpecifier.h"
 #include "clang/AST/PrettyPrinter.h"
 #include "clang/AST/TemplateBase.h"
diff --git a/clang/lib/Basic/OpenMPKinds.cpp b/clang/lib/Basic/OpenMPKinds.cpp
index 5ecc24647e7cd..f2106531d6eb1 100644
--- a/clang/lib/Basic/OpenMPKinds.cpp
+++ b/clang/lib/Basic/OpenMPKinds.cpp
@@ -154,6 +154,11 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind,
 #define OPENMP_DEPEND_KIND(Name) .Case(#Name, OMPC_DEPEND_##Name)
 #include "clang/Basic/OpenMPKinds.def"
         .Default(OMPC_DEPEND_unknown);
+  case OMPC_device:
+    return llvm::StringSwitch<OpenMPDeviceClauseModifier>(Str)
+#define OPENMP_DEVICE_MODIFIER(Name) .Case(#Name, OMPC_DEVICE_##Name)
+#include "clang/Basic/OpenMPKinds.def"
+        .Default(OMPC_DEVICE_unknown);
   case OMPC_unknown:
   case OMPC_threadprivate:
   case OMPC_if:
@@ -187,7 +192,6 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind,
   case OMPC_acquire:
   case OMPC_release:
   case OMPC_relaxed:
-  case OMPC_device:
   case OMPC_threads:
   case OMPC_simd:
   case OMPC_num_teams:
@@ -207,6 +211,7 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind,
   case OMPC_match:
   case OMPC_nontemporal:
   case OMPC_destroy:
+  case OMPC_detach:
     break;
   }
   llvm_unreachable("Invalid OpenMP simple clause kind");
@@ -379,6 +384,16 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind,
 #include "clang/Basic/OpenMPKinds.def"
     }
     llvm_unreachable("Invalid OpenMP 'depend' clause type");
+  case OMPC_device:
+    switch (Type) {
+    case OMPC_DEVICE_unknown:
+      return "unknown";
+#define OPENMP_DEVICE_MODIFIER(Name)                                           \
+  case OMPC_DEVICE_##Name:                                                     \
+    return #Name;
+#include "clang/Basic/OpenMPKinds.def"
+    }
+    llvm_unreachable("Invalid OpenMP 'device' clause modifier");
   case OMPC_unknown:
   case OMPC_threadprivate:
   case OMPC_if:
@@ -412,7 +427,6 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind,
   case OMPC_acquire:
   case OMPC_release:
   case OMPC_relaxed:
-  case OMPC_device:
   case OMPC_threads:
   case OMPC_simd:
   case OMPC_num_teams:
@@ -432,6 +446,7 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind,
   case OMPC_match:
   case OMPC_nontemporal:
   case OMPC_destroy:
+  case OMPC_detach:
     break;
   }
   llvm_unreachable("Invalid OpenMP simple clause kind");
@@ -554,6 +569,8 @@ bool clang::isAllowedClauseForDirective(OpenMPDirectiveKind DKind,
     }
     break;
   case OMPD_task:
+    if (OpenMPVersion < 50 && CKind == OMPC_detach)
+      return false;
     switch (CKind) {
 #define OPENMP_TASK_CLAUSE(Name)                                               \
   case OMPC_##Name:                                                            \
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 58d018c5bd3e2..2330339bedfb2 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -380,6 +380,20 @@ void TargetInfo::adjust(LangOptions &Opts) {
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
   }
 
+  if (Opts.DoubleSize) {
+    if (Opts.DoubleSize == 32) {
+      DoubleWidth = 32;
+      LongDoubleWidth = 32;
+      DoubleFormat = &llvm::APFloat::IEEEsingle();
+      LongDoubleFormat = &llvm::APFloat::IEEEsingle();
+    } else if (Opts.DoubleSize == 64) {
+      DoubleWidth = 64;
+      LongDoubleWidth = 64;
+      DoubleFormat = &llvm::APFloat::IEEEdouble();
+      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+    }
+  }
+
   if (Opts.LongDoubleSize) {
     if (Opts.LongDoubleSize == DoubleWidth) {
       LongDoubleWidth = DoubleWidth;
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index bd1a8834c2fa3..74bb6900b19e3 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -26,6 +26,10 @@ const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
    {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #include "clang/Basic/BuiltinsNEON.def"
 
+#define BUILTIN(ID, TYPE, ATTRS)                                               \
+   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsSVE.def"
+
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
    {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
@@ -486,17 +490,29 @@ bool AArch64TargetInfo::validateAsmConstraint(
     Info.setAllowsRegister();
     return true;
   case 'U':
+    if (Name[1] == 'p' && (Name[2] == 'l' || Name[2] == 'a')) {
+      // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
+      Info.setAllowsRegister();
+      Name += 2;
+      return true;
+    }
     // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
     // Utf: A memory address suitable for ldp/stp in TF mode.
     // Usa: An absolute symbolic address.
     // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
-    llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
+
+    // Better to return an error saying that it's an unrecognised constraint
+    // even if this is a valid constraint in gcc.
+    return false;
   case 'z': // Zero register, wzr or xzr
     Info.setAllowsRegister();
     return true;
   case 'x': // Floating point and SIMD registers (V0-V15)
     Info.setAllowsRegister();
     return true;
+  case 'y': // SVE registers (V0-V7)
+    Info.setAllowsRegister();
+    return true;
   }
   return false;
 }
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 5e78237743c90..41970e5d716e7 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -87,6 +87,21 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
 
   ArrayRef<const char *> getGCCRegNames() const override;
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
+
+  std::string convertConstraint(const char *&Constraint) const override {
+    std::string R;
+    switch (*Constraint) {
+    case 'U': // Three-character constraint; add "@3" hint for later parsing.
+      R = std::string("@3") + std::string(Constraint, 3);
+      Constraint += 2;
+      break;
+    default:
+      R = TargetInfo::convertConstraint(Constraint);
+      break;
+    }
+    return R;
+  }
+
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
   bool
diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
index 645fcbcf1bb70..7e5db5f088dff 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -18,6 +18,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/Analysis/StackSafetyAnalysis.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeReader.h"
@@ -351,6 +352,11 @@ static void addDataFlowSanitizerPass(const PassManagerBuilder &Builder,
   PM.add(createDataFlowSanitizerPass(LangOpts.SanitizerBlacklistFiles));
 }
 
+static void addMemTagOptimizationPasses(const PassManagerBuilder &Builder,
+                                        legacy::PassManagerBase &PM) {
+  PM.add(createStackSafetyGlobalInfoWrapperPass(/*SetMetadata=*/true));
+}
+
 static TargetLibraryInfoImpl *createTLII(llvm::Triple &TargetTriple,
                                          const CodeGenOptions &CodeGenOpts) {
   TargetLibraryInfoImpl *TLII = new TargetLibraryInfoImpl(TargetTriple);
@@ -702,6 +708,11 @@ void EmitAssemblyHelper::CreatePasses(legacy::PassManager &MPM,
                            addDataFlowSanitizerPass);
   }
 
+  if (LangOpts.Sanitize.has(SanitizerKind::MemTag)) {
+    PMBuilder.addExtension(PassManagerBuilder::EP_OptimizerLast,
+                           addMemTagOptimizationPasses);
+  }
+
   // Set up the per-function pass manager.
   FPM.add(new TargetLibraryInfoWrapperPass(*TLII));
   if (CodeGenOpts.VerifyModule)
@@ -1309,6 +1320,11 @@ void EmitAssemblyHelper::EmitAssemblyWithNewPassManager(
           /*CompileKernel=*/true, /*Recover=*/true));
     }
 
+    if (CodeGenOpts.OptimizationLevel > 0 &&
+        LangOpts.Sanitize.has(SanitizerKind::MemTag)) {
+      MPM.addPass(StackSafetyGlobalAnnotatorPass());
+    }
+
     if (CodeGenOpts.OptimizationLevel == 0) {
       addCoroutinePassesAtO0(MPM, LangOpts, CodeGenOpts);
       addSanitizersAtO0(MPM, TargetTriple, LangOpts, CodeGenOpts);
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index c6a308c428435..aa40aeab98942 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -4582,7 +4582,7 @@ enum {
 };
 
 namespace {
-struct NeonIntrinsicInfo {
+struct ARMVectorIntrinsicInfo {
   const char *NameHint;
   unsigned BuiltinID;
   unsigned LLVMIntrinsic;
@@ -4592,7 +4592,7 @@ struct NeonIntrinsicInfo {
   bool operator<(unsigned RHSBuiltinID) const {
     return BuiltinID < RHSBuiltinID;
   }
-  bool operator<(const NeonIntrinsicInfo &TE) const {
+  bool operator<(const ARMVectorIntrinsicInfo &TE) const {
     return BuiltinID < TE.BuiltinID;
   }
 };
@@ -4610,7 +4610,7 @@ struct NeonIntrinsicInfo {
       Intrinsic::LLVMIntrinsic, Intrinsic::AltLLVMIntrinsic, \
       TypeModifier }
 
-static const NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
+static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
   NEONMAP2(vabd_v, arm_neon_vabdu, arm_neon_vabds, Add1ArgType | UnsignedAlts),
   NEONMAP2(vabdq_v, arm_neon_vabdu, arm_neon_vabds, Add1ArgType | UnsignedAlts),
   NEONMAP1(vabs_v, arm_neon_vabs, 0),
@@ -4891,7 +4891,7 @@ static const NeonIntrinsicInfo ARMSIMDIntrinsicMap [] = {
   NEONMAP0(vzipq_v)
 };
 
-static const NeonIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
+static const ARMVectorIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
   NEONMAP1(vabs_v, aarch64_neon_abs, 0),
   NEONMAP1(vabsq_v, aarch64_neon_abs, 0),
   NEONMAP0(vaddhn_v),
@@ -5060,7 +5060,7 @@ static const NeonIntrinsicInfo AArch64SIMDIntrinsicMap[] = {
   NEONMAP0(vtstq_v),
 };
 
-static const NeonIntrinsicInfo AArch64SISDIntrinsicMap[] = {
+static const ARMVectorIntrinsicInfo AArch64SISDIntrinsicMap[] = {
   NEONMAP1(vabdd_f64, aarch64_sisd_fabd, Add1ArgType),
   NEONMAP1(vabds_f32, aarch64_sisd_fabd, Add1ArgType),
   NEONMAP1(vabsd_s64, aarch64_neon_abs, Add1ArgType),
@@ -5290,15 +5290,32 @@ static const NeonIntrinsicInfo AArch64SISDIntrinsicMap[] = {
 #undef NEONMAP1
 #undef NEONMAP2
 
+#define SVEMAP1(NameBase, LLVMIntrinsic, TypeModifier)                         \
+  {                                                                            \
+    #NameBase, SVE::BI__builtin_sve_##NameBase, Intrinsic::LLVMIntrinsic, 0,   \
+        TypeModifier                                                           \
+  }
+
+#define SVEMAP2(NameBase, TypeModifier)                                        \
+  { #NameBase, SVE::BI__builtin_sve_##NameBase, 0, 0, TypeModifier }
+static const ARMVectorIntrinsicInfo AArch64SVEIntrinsicMap[] = {
+#define GET_SVE_LLVM_INTRINSIC_MAP
+#include "clang/Basic/arm_sve_builtin_cg.inc"
+#undef GET_SVE_LLVM_INTRINSIC_MAP
+};
+
+#undef SVEMAP1
+#undef SVEMAP2
+
 static bool NEONSIMDIntrinsicsProvenSorted = false;
 
 static bool AArch64SIMDIntrinsicsProvenSorted = false;
 static bool AArch64SISDIntrinsicsProvenSorted = false;
+static bool AArch64SVEIntrinsicsProvenSorted = false;
 
-
-static const NeonIntrinsicInfo *
-findNeonIntrinsicInMap(ArrayRef<NeonIntrinsicInfo> IntrinsicMap,
-                       unsigned BuiltinID, bool &MapProvenSorted) {
+static const ARMVectorIntrinsicInfo *
+findARMVectorIntrinsicInMap(ArrayRef<ARMVectorIntrinsicInfo> IntrinsicMap,
+                            unsigned BuiltinID, bool &MapProvenSorted) {
 
 #ifndef NDEBUG
   if (!MapProvenSorted) {
@@ -5307,7 +5324,8 @@ findNeonIntrinsicInMap(ArrayRef<NeonIntrinsicInfo> IntrinsicMap,
   }
 #endif
 
-  const NeonIntrinsicInfo *Builtin = llvm::lower_bound(IntrinsicMap, BuiltinID);
+  const ARMVectorIntrinsicInfo *Builtin =
+      llvm::lower_bound(IntrinsicMap, BuiltinID);
 
   if (Builtin != IntrinsicMap.end() && Builtin->BuiltinID == BuiltinID)
     return Builtin;
@@ -5354,10 +5372,9 @@ Function *CodeGenFunction::LookupNeonLLVMIntrinsic(unsigned IntrinsicID,
   return CGM.getIntrinsic(IntrinsicID, Tys);
 }
 
-static Value *EmitCommonNeonSISDBuiltinExpr(CodeGenFunction &CGF,
-                                            const NeonIntrinsicInfo &SISDInfo,
-                                            SmallVectorImpl<Value *> &Ops,
-                                            const CallExpr *E) {
+static Value *EmitCommonNeonSISDBuiltinExpr(
+    CodeGenFunction &CGF, const ARMVectorIntrinsicInfo &SISDInfo,
+    SmallVectorImpl<Value *> &Ops, const CallExpr *E) {
   unsigned BuiltinID = SISDInfo.BuiltinID;
   unsigned int Int = SISDInfo.LLVMIntrinsic;
   unsigned Modifier = SISDInfo.TypeModifier;
@@ -6870,7 +6887,7 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
   // Many NEON builtins have identical semantics and uses in ARM and
   // AArch64. Emit these in a single function.
   auto IntrinsicMap = makeArrayRef(ARMSIMDIntrinsicMap);
-  const NeonIntrinsicInfo *Builtin = findNeonIntrinsicInMap(
+  const ARMVectorIntrinsicInfo *Builtin = findARMVectorIntrinsicInMap(
       IntrinsicMap, BuiltinID, NEONSIMDIntrinsicsProvenSorted);
   if (Builtin)
     return EmitCommonNeonBuiltinExpr(
@@ -7390,9 +7407,92 @@ Value *CodeGenFunction::vectorWrapScalar16(Value *Op) {
   return Op;
 }
 
+// Reinterpret the input predicate so that it can be used to correctly isolate
+// the elements of the specified datatype.
+Value *CodeGenFunction::EmitSVEPredicateCast(Value *Pred,
+                                             llvm::VectorType *VTy) {
+  llvm::VectorType *RTy = llvm::VectorType::get(
+      IntegerType::get(getLLVMContext(), 1), VTy->getElementCount());
+  if (Pred->getType() == RTy)
+    return Pred;
+
+  unsigned IntID;
+  llvm::Type *IntrinsicTy;
+  switch (VTy->getNumElements()) {
+  default:
+    llvm_unreachable("unsupported element count!");
+  case 2:
+  case 4:
+  case 8:
+    IntID = Intrinsic::aarch64_sve_convert_from_svbool;
+    IntrinsicTy = RTy;
+    break;
+  case 16:
+    IntID = Intrinsic::aarch64_sve_convert_to_svbool;
+    IntrinsicTy = Pred->getType();
+    break;
+  }
+
+  Function *F = CGM.getIntrinsic(IntID, IntrinsicTy);
+  Value *C = Builder.CreateCall(F, Pred);
+  assert(C->getType() == RTy && "Unexpected return type!");
+  return C;
+}
+
+Value *CodeGenFunction::EmitSVEMaskedLoad(llvm::Type *ReturnTy,
+                                          SmallVectorImpl<Value *> &Ops) {
+  llvm::PointerType *PTy = cast<llvm::PointerType>(Ops[1]->getType());
+  llvm::Type *MemEltTy = PTy->getPointerElementType();
+
+  // The vector type that is returned may be different from the
+  // eventual type loaded from memory.
+  auto VectorTy = cast<llvm::VectorType>(ReturnTy);
+  auto MemoryTy =
+      llvm::VectorType::get(MemEltTy, VectorTy->getVectorElementCount());
+
+  Value *Offset = Builder.getInt32(0);
+  Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy);
+  Value *BasePtr = Builder.CreateBitCast(Ops[1], MemoryTy->getPointerTo());
+  BasePtr = Builder.CreateGEP(MemoryTy, BasePtr, Offset);
+
+  Value *Splat0 = Constant::getNullValue(MemoryTy);
+  return Builder.CreateMaskedLoad(BasePtr, Align(1), Predicate, Splat0);
+}
+
+Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
+                                                  const CallExpr *E) {
+  // Find out if any arguments are required to be integer constant expressions.
+  unsigned ICEArguments = 0;
+  ASTContext::GetBuiltinTypeError Error;
+  getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
+  assert(Error == ASTContext::GE_None && "Should not codegen an error");
+
+  llvm::SmallVector<Value *, 4> Ops;
+  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
+    if ((ICEArguments & (1 << i)) == 0)
+      Ops.push_back(EmitScalarExpr(E->getArg(i)));
+    else
+      llvm_unreachable("Not yet implemented");
+  }
+
+  auto *Builtin = findARMVectorIntrinsicInMap(AArch64SVEIntrinsicMap, BuiltinID,
+                                              AArch64SVEIntrinsicsProvenSorted);
+  SVETypeFlags TypeFlags(Builtin->TypeModifier);
+  llvm::Type *Ty = ConvertType(E->getType());
+  if (TypeFlags.isLoad())
+    return EmitSVEMaskedLoad(Ty, Ops);
+
+  /// Should not happen
+  return nullptr;
+}
+
 Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
                                                const CallExpr *E,
                                                llvm::Triple::ArchType Arch) {
+  if (BuiltinID >= AArch64::FirstSVEBuiltin &&
+      BuiltinID <= AArch64::LastSVEBuiltin)
+    return EmitAArch64SVEBuiltinExpr(BuiltinID, E);
+
   unsigned HintID = static_cast<unsigned>(-1);
   switch (BuiltinID) {
   default: break;
@@ -7824,7 +7924,7 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
   }
 
   auto SISDMap = makeArrayRef(AArch64SISDIntrinsicMap);
-  const NeonIntrinsicInfo *Builtin = findNeonIntrinsicInMap(
+  const ARMVectorIntrinsicInfo *Builtin = findARMVectorIntrinsicInMap(
       SISDMap, BuiltinID, AArch64SISDIntrinsicsProvenSorted);
 
   if (Builtin) {
@@ -8664,8 +8764,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
 
   // Not all intrinsics handled by the common case work for AArch64 yet, so only
   // defer to common code if it's been added to our special map.
-  Builtin = findNeonIntrinsicInMap(AArch64SIMDIntrinsicMap, BuiltinID,
-                                   AArch64SIMDIntrinsicsProvenSorted);
+  Builtin = findARMVectorIntrinsicInMap(AArch64SIMDIntrinsicMap, BuiltinID,
+                                        AArch64SIMDIntrinsicsProvenSorted);
 
   if (Builtin)
     return EmitCommonNeonBuiltinExpr(
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 64c261f1ba92f..4e7f689a213fd 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -4530,8 +4530,9 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo,
   // Update the largest vector width if any arguments have vector types.
   for (unsigned i = 0; i < IRCallArgs.size(); ++i) {
     if (auto *VT = dyn_cast<llvm::VectorType>(IRCallArgs[i]->getType()))
-      LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                   VT->getPrimitiveSizeInBits().getFixedSize());
+      LargestVectorWidth =
+          std::max((uint64_t)LargestVectorWidth,
+                   VT->getPrimitiveSizeInBits().getKnownMinSize());
   }
 
   // Compute the calling convention and attributes.
@@ -4645,8 +4646,9 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo,
 
   // Update largest vector width from the return type.
   if (auto *VT = dyn_cast<llvm::VectorType>(CI->getType()))
-    LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                  VT->getPrimitiveSizeInBits().getFixedSize());
+    LargestVectorWidth =
+        std::max((uint64_t)LargestVectorWidth,
+                 VT->getPrimitiveSizeInBits().getKnownMinSize());
 
   // Insert instrumentation or attach profile metadata at indirect call sites.
   // For more details, see the comment before the definition of
diff --git a/clang/lib/CodeGen/CGCoroutine.cpp b/clang/lib/CodeGen/CGCoroutine.cpp
index aee5a927a055b..5c57ad0685d58 100644
--- a/clang/lib/CodeGen/CGCoroutine.cpp
+++ b/clang/lib/CodeGen/CGCoroutine.cpp
@@ -275,9 +275,9 @@ RValue CodeGenFunction::EmitCoyieldExpr(const CoyieldExpr &E,
 void CodeGenFunction::EmitCoreturnStmt(CoreturnStmt const &S) {
   ++CurCoro.Data->CoreturnCount;
   const Expr *RV = S.getOperand();
-  if (RV && RV->getType()->isVoidType()) {
-    // Make sure to evaluate the expression of a co_return with a void
-    // expression for side effects.
+  if (RV && RV->getType()->isVoidType() && !isa<InitListExpr>(RV)) {
+    // Make sure to evaluate the non initlist expression of a co_return
+    // with a void expression for side effects.
     RunCleanupsScope cleanupScope(*this);
     EmitIgnoredExpr(RV);
   }
diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp
index e5d8f8eaa18a8..726e3829793dd 100644
--- a/clang/lib/CodeGen/CGDecl.cpp
+++ b/clang/lib/CodeGen/CGDecl.cpp
@@ -253,7 +253,7 @@ llvm::Constant *CodeGenModule::getOrCreateStaticVarDecl(
   // variables cannot have an initializer.
   llvm::Constant *Init = nullptr;
   if (Ty.getAddressSpace() == LangAS::opencl_local ||
-      D.hasAttr<CUDASharedAttr>())
+      D.hasAttr<CUDASharedAttr>() || D.hasAttr<LoaderUninitializedAttr>())
     Init = llvm::UndefValue::get(LTy);
   else
     Init = EmitNullConstant(Ty);
@@ -301,7 +301,7 @@ llvm::Constant *CodeGenModule::getOrCreateStaticVarDecl(
   else if (const auto *DD = dyn_cast<CXXDestructorDecl>(DC))
     GD = GlobalDecl(DD, Dtor_Base);
   else if (const auto *FD = dyn_cast<FunctionDecl>(DC))
-    GD = getGlobalDecl(FD);
+    GD = GlobalDecl(FD);
   else {
     // Don't do anything for Obj-C method decls or global closures. We should
     // never defer them.
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index f7270b41e5780..f96b5d2e57de1 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -4737,12 +4737,12 @@ CGCallee CodeGenFunction::EmitCallee(const Expr *E) {
   // Resolve direct calls.
   } else if (auto DRE = dyn_cast<DeclRefExpr>(E)) {
     if (auto FD = dyn_cast<FunctionDecl>(DRE->getDecl())) {
-      return EmitDirectCallee(*this, CGM.getGlobalDecl(FD));
+      return EmitDirectCallee(*this, FD);
     }
   } else if (auto ME = dyn_cast<MemberExpr>(E)) {
     if (auto FD = dyn_cast<FunctionDecl>(ME->getMemberDecl())) {
       EmitIgnoredExpr(ME->getBase());
-      return EmitDirectCallee(*this, CGM.getGlobalDecl(FD));
+      return EmitDirectCallee(*this, FD);
     }
 
   // Look through template substitutions.
diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
index fde42b1fe2429..fa60221e8b593 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
@@ -765,6 +765,9 @@ enum OpenMPRTLFunction {
   // Call to void __tgt_push_mapper_component(void *rt_mapper_handle, void
   // *base, void *begin, int64_t size, int64_t type);
   OMPRTL__tgt_push_mapper_component,
+  // Call to kmp_event_t *__kmpc_task_allow_completion_event(ident_t *loc_ref,
+  // int gtid, kmp_task_t *task);
+  OMPRTL__kmpc_task_allow_completion_event,
 };
 
 /// A basic class for pre|post-action for advanced codegen sequence for OpenMP
@@ -2596,6 +2599,16 @@ llvm::FunctionCallee CGOpenMPRuntime::createRuntimeFunction(unsigned Function) {
     RTLFn = CGM.CreateRuntimeFunction(FnTy, "__tgt_push_mapper_component");
     break;
   }
+  case OMPRTL__kmpc_task_allow_completion_event: {
+    // Build kmp_event_t *__kmpc_task_allow_completion_event(ident_t *loc_ref,
+    // int gtid, kmp_task_t *task);
+    auto *FnTy = llvm::FunctionType::get(
+        CGM.VoidPtrTy, {getIdentTyPointerTy(), CGM.IntTy, CGM.VoidPtrTy},
+        /*isVarArg=*/false);
+    RTLFn =
+        CGM.CreateRuntimeFunction(FnTy, "__kmpc_task_allow_completion_event");
+    break;
+  }
   }
   assert(RTLFn && "Unable to find OpenMP runtime function");
   return RTLFn;
@@ -5083,7 +5096,8 @@ CGOpenMPRuntime::emitTaskInit(CodeGenFunction &CGF, SourceLocation Loc,
     TiedFlag = 0x1,
     FinalFlag = 0x2,
     DestructorsFlag = 0x8,
-    PriorityFlag = 0x20
+    PriorityFlag = 0x20,
+    DetachableFlag = 0x40,
   };
   unsigned Flags = Data.Tied ? TiedFlag : 0;
   bool NeedsCleanup = false;
@@ -5094,6 +5108,8 @@ CGOpenMPRuntime::emitTaskInit(CodeGenFunction &CGF, SourceLocation Loc,
   }
   if (Data.Priority.getInt())
     Flags = Flags | PriorityFlag;
+  if (D.hasClausesOfKind<OMPDetachClause>())
+    Flags = Flags | DetachableFlag;
   llvm::Value *TaskFlags =
       Data.Final.getPointer()
           ? CGF.Builder.CreateSelect(Data.Final.getPointer(),
@@ -5126,6 +5142,25 @@ CGOpenMPRuntime::emitTaskInit(CodeGenFunction &CGF, SourceLocation Loc,
     NewTask = CGF.EmitRuntimeCall(
       createRuntimeFunction(OMPRTL__kmpc_omp_task_alloc), AllocArgs);
   }
+  // Emit detach clause initialization.
+  // evt = (typeof(evt))__kmpc_task_allow_completion_event(loc, tid,
+  // task_descriptor);
+  if (const auto *DC = D.getSingleClause<OMPDetachClause>()) {
+    const Expr *Evt = DC->getEventHandler()->IgnoreParenImpCasts();
+    LValue EvtLVal = CGF.EmitLValue(Evt);
+
+    // Build kmp_event_t *__kmpc_task_allow_completion_event(ident_t *loc_ref,
+    // int gtid, kmp_task_t *task);
+    llvm::Value *Loc = emitUpdateLocation(CGF, DC->getBeginLoc());
+    llvm::Value *Tid = getThreadID(CGF, DC->getBeginLoc());
+    Tid = CGF.Builder.CreateIntCast(Tid, CGF.IntTy, /*isSigned=*/false);
+    llvm::Value *EvtVal = CGF.EmitRuntimeCall(
+        createRuntimeFunction(OMPRTL__kmpc_task_allow_completion_event),
+        {Loc, Tid, NewTask});
+    EvtVal = CGF.EmitScalarConversion(EvtVal, C.VoidPtrTy, Evt->getType(),
+                                      Evt->getExprLoc());
+    CGF.EmitStoreOfScalar(EvtVal, EvtLVal);
+  }
   llvm::Value *NewTaskNewTaskTTy =
       CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
           NewTask, KmpTaskTWithPrivatesPtrTy);
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index ee30580493d55..283942441b0e1 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -2118,8 +2118,9 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
 
       // Update largest vector width for any vector types.
       if (auto *VT = dyn_cast<llvm::VectorType>(ResultRegTypes.back()))
-        LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                   VT->getPrimitiveSizeInBits().getFixedSize());
+        LargestVectorWidth =
+            std::max((uint64_t)LargestVectorWidth,
+                     VT->getPrimitiveSizeInBits().getKnownMinSize());
     } else {
       ArgTypes.push_back(Dest.getAddress(*this).getType());
       Args.push_back(Dest.getPointer(*this));
@@ -2143,8 +2144,9 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
 
       // Update largest vector width for any vector types.
       if (auto *VT = dyn_cast<llvm::VectorType>(Arg->getType()))
-        LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                   VT->getPrimitiveSizeInBits().getFixedSize());
+        LargestVectorWidth =
+            std::max((uint64_t)LargestVectorWidth,
+                     VT->getPrimitiveSizeInBits().getKnownMinSize());
       if (Info.allowsRegister())
         InOutConstraints += llvm::utostr(i);
       else
@@ -2230,8 +2232,9 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
 
     // Update largest vector width for any vector types.
     if (auto *VT = dyn_cast<llvm::VectorType>(Arg->getType()))
-      LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                   VT->getPrimitiveSizeInBits().getFixedSize());
+      LargestVectorWidth =
+          std::max((uint64_t)LargestVectorWidth,
+                   VT->getPrimitiveSizeInBits().getKnownMinSize());
 
     ArgTypes.push_back(Arg->getType());
     Args.push_back(Arg);
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index e3dd490216447..2ffe79957ee85 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -4615,6 +4615,7 @@ static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind,
   case OMPC_nontemporal:
   case OMPC_order:
   case OMPC_destroy:
+  case OMPC_detach:
     llvm_unreachable("Clause is not allowed in 'omp atomic'.");
   }
 }
@@ -4724,8 +4725,11 @@ static void emitCommonOMPTargetDirective(CodeGenFunction &CGF,
 
   // Check if we have any device clause associated with the directive.
   const Expr *Device = nullptr;
-  if (auto *C = S.getSingleClause<OMPDeviceClause>())
-    Device = C->getDevice();
+  if (auto *C = S.getSingleClause<OMPDeviceClause>()) {
+    if (C->getModifier() == OMPC_DEVICE_unknown ||
+        C->getModifier() == OMPC_DEVICE_device_num)
+      Device = C->getDevice();
+  }
 
   // Check if we have an if clause whose conditional always evaluates to false
   // or if we do not have any targets specified. If so the target region is not
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index c2925b28c8d45..1f06514a38c13 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -496,13 +496,15 @@ void CodeGenFunction::FinishFunction(SourceLocation EndLoc) {
   // Scan function arguments for vector width.
   for (llvm::Argument &A : CurFn->args())
     if (auto *VT = dyn_cast<llvm::VectorType>(A.getType()))
-      LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                   VT->getPrimitiveSizeInBits().getFixedSize());
+      LargestVectorWidth =
+          std::max((uint64_t)LargestVectorWidth,
+                   VT->getPrimitiveSizeInBits().getKnownMinSize());
 
   // Update vector width based on return type.
   if (auto *VT = dyn_cast<llvm::VectorType>(CurFn->getReturnType()))
-    LargestVectorWidth = std::max((uint64_t)LargestVectorWidth,
-                                  VT->getPrimitiveSizeInBits().getFixedSize());
+    LargestVectorWidth =
+        std::max((uint64_t)LargestVectorWidth,
+                 VT->getPrimitiveSizeInBits().getKnownMinSize());
 
   // Add the required-vector-width attribute. This contains the max width from:
   // 1. min-vector-width attribute used in the source program.
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index 2e77ad49273b7..0a4a4c3a71d42 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -3900,6 +3900,12 @@ class CodeGenFunction : public CodeGenTypeCache {
   llvm::Value *EmitNeonRShiftImm(llvm::Value *Vec, llvm::Value *Amt,
                                  llvm::Type *Ty, bool usgn, const char *name);
   llvm::Value *vectorWrapScalar16(llvm::Value *Op);
+
+  llvm::Value *EmitSVEPredicateCast(llvm::Value *Pred, llvm::VectorType *VTy);
+  llvm::Value *EmitSVEMaskedLoad(llvm::Type *ReturnTy,
+                                 SmallVectorImpl<llvm::Value *> &Ops);
+  llvm::Value *EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
+
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
                                       llvm::Triple::ArchType Arch);
   llvm::Value *EmitBPFBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index e61d27de3deaf..37b453de9b99a 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -4146,6 +4146,8 @@ void CodeGenModule::EmitGlobalVarDefinition(const VarDecl *D,
   if (getLangOpts().CUDA &&
       (IsCUDASharedVar || IsCUDAShadowVar || IsHIPPinnedShadowVar))
     Init = llvm::UndefValue::get(getTypes().ConvertType(ASTTy));
+  else if (D->hasAttr<LoaderUninitializedAttr>())
+    Init = llvm::UndefValue::get(getTypes().ConvertType(ASTTy));
   else if (!InitExpr) {
     // This is a tentative definition; tentative definitions are
     // implicitly initialized with { 0 }.
@@ -5512,7 +5514,7 @@ void CodeGenModule::EmitTopLevelDecl(Decl *D) {
   case Decl::CXXConversion:
   case Decl::CXXMethod:
   case Decl::Function:
-    EmitGlobal(getGlobalDecl(cast<FunctionDecl>(D)));
+    EmitGlobal(cast<FunctionDecl>(D));
     // Always provide some coverage mapping
     // even for the functions that aren't emitted.
     AddDeferredUnusedCoverageMapping(D);
@@ -6174,10 +6176,3 @@ CodeGenModule::createOpenCLIntToSamplerConversion(const Expr *E,
                                 "__translate_sampler_initializer"),
                                 {C});
 }
-
-GlobalDecl CodeGenModule::getGlobalDecl(const FunctionDecl *FD) {
-  if (FD->hasAttr<CUDAGlobalAttr>())
-    return GlobalDecl::getDefaultKernelReference(FD);
-  else
-    return GlobalDecl(FD);
-}
diff --git a/clang/lib/CodeGen/CodeGenModule.h b/clang/lib/CodeGen/CodeGenModule.h
index 9437b13b56956..af53d77b9358d 100644
--- a/clang/lib/CodeGen/CodeGenModule.h
+++ b/clang/lib/CodeGen/CodeGenModule.h
@@ -720,9 +720,6 @@ class CodeGenModule : public CodeGenTypeCache {
   CtorList &getGlobalCtors() { return GlobalCtors; }
   CtorList &getGlobalDtors() { return GlobalDtors; }
 
-  /// get GlobalDecl for non-ctor/dtor functions.
-  GlobalDecl getGlobalDecl(const FunctionDecl *FD);
-
   /// getTBAATypeInfo - Get metadata used to describe accesses to objects of
   /// the given type.
   llvm::MDNode *getTBAATypeInfo(QualType QTy);
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index fcc796f9a4d60..444bdcb7d0921 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -4671,6 +4671,14 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
   RenderFloatingPointOptions(TC, D, OFastEnabled, Args, CmdArgs,
                              JA.getOffloadingDeviceKind());
 
+  if (Arg *A = Args.getLastArg(options::OPT_mdouble_EQ)) {
+    if (TC.getArch() == llvm::Triple::avr)
+      A->render(Args, CmdArgs);
+    else
+      D.Diag(diag::err_drv_unsupported_opt_for_target)
+          << A->getAsString(Args) << TripleStr;
+  }
+
   if (Arg *A = Args.getLastArg(options::OPT_LongDouble_Group)) {
     if (TC.getTriple().isX86())
       A->render(Args, CmdArgs);
diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp b/clang/lib/Driver/ToolChains/MSVC.cpp
index 05f5d731f3667..198800c437e37 100644
--- a/clang/lib/Driver/ToolChains/MSVC.cpp
+++ b/clang/lib/Driver/ToolChains/MSVC.cpp
@@ -1538,7 +1538,8 @@ static void TranslateDArg(Arg *A, llvm::opt::DerivedArgList &DAL,
 
 llvm::opt::DerivedArgList *
 MSVCToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args,
-                             StringRef BoundArch, Action::OffloadKind) const {
+                             StringRef BoundArch,
+                             Action::OffloadKind OFK) const {
   DerivedArgList *DAL = new DerivedArgList(Args.getBaseArgs());
   const OptTable &Opts = getDriver().getOpts();
 
@@ -1577,7 +1578,8 @@ MSVCToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args,
     } else if (A->getOption().matches(options::OPT_D)) {
       // Translate -Dfoo#bar into -Dfoo=bar.
       TranslateDArg(A, *DAL, Opts);
-    } else {
+    } else if (OFK != Action::OFK_HIP) {
+      // HIP Toolchain translates input args by itself.
       DAL->append(A);
     }
   }
diff --git a/clang/lib/Driver/ToolChains/PS4CPU.cpp b/clang/lib/Driver/ToolChains/PS4CPU.cpp
index 93d86e6d04b18..9ecbb7241d454 100644
--- a/clang/lib/Driver/ToolChains/PS4CPU.cpp
+++ b/clang/lib/Driver/ToolChains/PS4CPU.cpp
@@ -30,13 +30,17 @@ void tools::PS4cpu::addProfileRTArgs(const ToolChain &TC, const ArgList &Args,
   if ((Args.hasFlag(options::OPT_fprofile_arcs, options::OPT_fno_profile_arcs,
                     false) ||
        Args.hasFlag(options::OPT_fprofile_generate,
-                    options::OPT_fno_profile_instr_generate, false) ||
+                    options::OPT_fno_profile_generate, false) ||
        Args.hasFlag(options::OPT_fprofile_generate_EQ,
-                    options::OPT_fno_profile_instr_generate, false) ||
+                    options::OPT_fno_profile_generate, false) ||
        Args.hasFlag(options::OPT_fprofile_instr_generate,
                     options::OPT_fno_profile_instr_generate, false) ||
        Args.hasFlag(options::OPT_fprofile_instr_generate_EQ,
                     options::OPT_fno_profile_instr_generate, false) ||
+       Args.hasFlag(options::OPT_fcs_profile_generate,
+                    options::OPT_fno_profile_generate, false) ||
+       Args.hasFlag(options::OPT_fcs_profile_generate_EQ,
+                    options::OPT_fno_profile_generate, false) ||
        Args.hasArg(options::OPT_fcreate_profile) ||
        Args.hasArg(options::OPT_coverage)))
     CmdArgs.push_back("--dependent-lib=libclang_rt.profile-x86_64.a");
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index fdfd5a0fafc24..3b5ef975bd891 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -2951,6 +2951,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   Opts.PackStruct = getLastArgIntValue(Args, OPT_fpack_struct_EQ, 0, Diags);
   Opts.MaxTypeAlign = getLastArgIntValue(Args, OPT_fmax_type_align_EQ, 0, Diags);
   Opts.AlignDouble = Args.hasArg(OPT_malign_double);
+  Opts.DoubleSize = getLastArgIntValue(Args, OPT_mdouble_EQ, 0, Diags);
   Opts.LongDoubleSize = Args.hasArg(OPT_mlong_double_128)
                             ? 128
                             : Args.hasArg(OPT_mlong_double_64) ? 64 : 0;
diff --git a/clang/lib/Frontend/FrontendOptions.cpp b/clang/lib/Frontend/FrontendOptions.cpp
index 5c1fbf889c23b..63088b95c310b 100644
--- a/clang/lib/Frontend/FrontendOptions.cpp
+++ b/clang/lib/Frontend/FrontendOptions.cpp
@@ -30,6 +30,7 @@ InputKind FrontendOptions::getInputKindForExtension(StringRef Extension) {
       .Case("iim", InputKind(Language::CXX).getPreprocessed())
       .Case("cl", Language::OpenCL)
       .Case("cu", Language::CUDA)
+      .Case("hip", Language::HIP)
       .Cases("ll", "bc", Language::LLVM_IR)
       .Default(Language::Unknown);
 }
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 923784305d05a..28d43cb7ed35a 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -184,6 +184,8 @@ endforeach( f )
 clang_generate_header(-gen-arm-neon arm_neon.td arm_neon.h)
 # Generate arm_fp16.h
 clang_generate_header(-gen-arm-fp16 arm_fp16.td arm_fp16.h)
+# Generate arm_sve.h
+clang_generate_header(-gen-arm-sve-header arm_sve.td arm_sve.h)
 # Generate arm_mve.h
 clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h)
 # Generate arm_cde.h
diff --git a/clang/lib/Headers/module.modulemap b/clang/lib/Headers/module.modulemap
index 7954a77a41258..6894672ef0529 100644
--- a/clang/lib/Headers/module.modulemap
+++ b/clang/lib/Headers/module.modulemap
@@ -27,6 +27,12 @@ module _Builtin_intrinsics [system] [extern_c] {
       header "arm_fp16.h"
       export *
     }
+
+    explicit module sve {
+      requires sve
+      header "arm_sve.h"
+      export *
+    }
   }
 
   explicit module intel {
diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp
index 9375ef0d5d2c9..bdff5273de611 100644
--- a/clang/lib/Parse/ParseDecl.cpp
+++ b/clang/lib/Parse/ParseDecl.cpp
@@ -3254,6 +3254,9 @@ void Parser::ParseDeclarationSpecifiers(DeclSpec &DS,
           goto DoneWithDeclSpec;
         if (isTypeConstraintAnnotation())
           continue;
+        if (NextToken().is(tok::annot_template_id))
+          // Might have been annotated by TryAnnotateTypeConstraint.
+          continue;
         // Eat the scope spec so the identifier is current.
         ConsumeAnnotationToken();
         ParsedAttributesWithRange Attrs(AttrFactory);
@@ -3405,7 +3408,10 @@ void Parser::ParseDeclarationSpecifiers(DeclSpec &DS,
       if (!TypeRep) {
         if (TryAnnotateTypeConstraint())
           goto DoneWithDeclSpec;
-        if (isTypeConstraintAnnotation())
+        if (Tok.isNot(tok::identifier))
+          continue;
+        if (Tok.is(tok::annot_template_id))
+          // Might have been annotated by TryAnnotateTypeConstraint.
           continue;
         ParsedAttributesWithRange Attrs(AttrFactory);
         if (ParseImplicitInt(DS, nullptr, TemplateInfo, AS, DSContext, Attrs)) {
diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp
index 1da884f657a05..84e7b7c9995c5 100644
--- a/clang/lib/Parse/ParseOpenMP.cpp
+++ b/clang/lib/Parse/ParseOpenMP.cpp
@@ -2340,7 +2340,7 @@ bool Parser::ParseOpenMPSimpleVarList(
 ///       from-clause | is_device_ptr-clause | task_reduction-clause |
 ///       in_reduction-clause | allocator-clause | allocate-clause |
 ///       acq_rel-clause | acquire-clause | release-clause | relaxed-clause |
-///       depobj-clause | destroy-clause
+///       depobj-clause | destroy-clause | detach-clause
 ///
 OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
                                      OpenMPClauseKind CKind, bool FirstClause) {
@@ -2363,7 +2363,6 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
   case OMPC_simdlen:
   case OMPC_collapse:
   case OMPC_ordered:
-  case OMPC_device:
   case OMPC_num_teams:
   case OMPC_thread_limit:
   case OMPC_priority:
@@ -2372,14 +2371,13 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
   case OMPC_hint:
   case OMPC_allocator:
   case OMPC_depobj:
+  case OMPC_detach:
     // OpenMP [2.5, Restrictions]
     //  At most one num_threads clause can appear on the directive.
     // OpenMP [2.8.1, simd construct, Restrictions]
     //  Only one safelen  clause can appear on a simd directive.
     //  Only one simdlen  clause can appear on a simd directive.
     //  Only one collapse clause can appear on a simd directive.
-    // OpenMP [2.9.1, target data construct, Restrictions]
-    //  At most one device clause can appear on the directive.
     // OpenMP [2.11.1, task Construct, Restrictions]
     //  At most one if clause can appear on the directive.
     //  At most one final clause can appear on the directive.
@@ -2394,6 +2392,8 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
     // At most one num_tasks clause can appear on the directive.
     // OpenMP [2.11.3, allocate Directive, Restrictions]
     // At most one allocator clause can appear on the directive.
+    // OpenMP 5.0, 2.10.1 task Construct, Restrictions.
+    // At most one detach clause can appear on the directive.
     if (!FirstClause) {
       Diag(Tok, diag::err_omp_more_one_clause)
           << getOpenMPDirectiveName(DKind) << getOpenMPClauseName(CKind) << 0;
@@ -2425,6 +2425,7 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
 
     Clause = ParseOpenMPSimpleClause(CKind, WrongDirective);
     break;
+  case OMPC_device:
   case OMPC_schedule:
   case OMPC_dist_schedule:
   case OMPC_defaultmap:
@@ -2432,6 +2433,8 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
     //  Only one schedule clause can appear on a loop directive.
     // OpenMP 4.5 [2.10.4, Restrictions, p. 106]
     //  At most one defaultmap clause can appear on the directive.
+    // OpenMP 5.0 [2.12.5, target construct, Restrictions]
+    //  At most one device clause can appear on the directive.
     if ((getLangOpts().OpenMP < 50 || CKind != OMPC_defaultmap) &&
         !FirstClause) {
       Diag(Tok, diag::err_omp_more_one_clause)
@@ -2440,7 +2443,7 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
     }
     LLVM_FALLTHROUGH;
   case OMPC_if:
-    Clause = ParseOpenMPSingleExprWithArgClause(CKind, WrongDirective);
+    Clause = ParseOpenMPSingleExprWithArgClause(DKind, CKind, WrongDirective);
     break;
   case OMPC_nowait:
   case OMPC_untied:
@@ -2552,7 +2555,8 @@ ExprResult Parser::ParseOpenMPParensExpr(StringRef ClauseName,
 
 /// Parsing of OpenMP clauses with single expressions like 'final',
 /// 'collapse', 'safelen', 'num_threads', 'simdlen', 'num_teams',
-/// 'thread_limit', 'simdlen', 'priority', 'grainsize', 'num_tasks' or 'hint'.
+/// 'thread_limit', 'simdlen', 'priority', 'grainsize', 'num_tasks', 'hint' or
+/// 'detach'.
 ///
 ///    final-clause:
 ///      'final' '(' expression ')'
@@ -2584,6 +2588,9 @@ ExprResult Parser::ParseOpenMPParensExpr(StringRef ClauseName,
 ///    allocator-clause:
 ///      'allocator' '(' expression ')'
 ///
+///    detach-clause:
+///      'detach' '(' event-handler-expression ')'
+///
 OMPClause *Parser::ParseOpenMPSingleExprClause(OpenMPClauseKind Kind,
                                                bool ParseOnly) {
   SourceLocation Loc = ConsumeToken();
@@ -2670,7 +2677,11 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPClauseKind Kind, bool ParseOnly) {
 ///    defaultmap:
 ///      'defaultmap' '(' modifier ':' kind ')'
 ///
-OMPClause *Parser::ParseOpenMPSingleExprWithArgClause(OpenMPClauseKind Kind,
+///    device-clause:
+///      'device' '(' [ device-modifier ':' ] expression ')'
+///
+OMPClause *Parser::ParseOpenMPSingleExprWithArgClause(OpenMPDirectiveKind DKind,
+                                                      OpenMPClauseKind Kind,
                                                       bool ParseOnly) {
   SourceLocation Loc = ConsumeToken();
   SourceLocation DelimLoc;
@@ -2764,6 +2775,21 @@ OMPClause *Parser::ParseOpenMPSingleExprWithArgClause(OpenMPClauseKind Kind,
     if (Tok.isNot(tok::r_paren) && Tok.isNot(tok::comma) &&
         Tok.isNot(tok::annot_pragma_openmp_end))
       ConsumeAnyToken();
+  } else if (Kind == OMPC_device) {
+    // Only target executable directives support extended device construct.
+    if (isOpenMPTargetExecutionDirective(DKind) && getLangOpts().OpenMP >= 50 &&
+        NextToken().is(tok::colon)) {
+      // Parse optional <device modifier> ':'
+      Arg.push_back(getOpenMPSimpleClauseType(
+          Kind, Tok.isAnnotation() ? "" : PP.getSpelling(Tok)));
+      KLoc.push_back(Tok.getLocation());
+      ConsumeAnyToken();
+      // Parse ':'
+      ConsumeAnyToken();
+    } else {
+      Arg.push_back(OMPC_DEVICE_unknown);
+      KLoc.emplace_back();
+    }
   } else {
     assert(Kind == OMPC_if);
     KLoc.push_back(Tok.getLocation());
@@ -2786,7 +2812,7 @@ OMPClause *Parser::ParseOpenMPSingleExprWithArgClause(OpenMPClauseKind Kind,
 
   bool NeedAnExpression = (Kind == OMPC_schedule && DelimLoc.isValid()) ||
                           (Kind == OMPC_dist_schedule && DelimLoc.isValid()) ||
-                          Kind == OMPC_if;
+                          Kind == OMPC_if || Kind == OMPC_device;
   if (NeedAnExpression) {
     SourceLocation ELoc = Tok.getLocation();
     ExprResult LHS(ParseCastExpression(AnyCastExpr, false, NotTypeCast));
diff --git a/clang/lib/Parse/ParseTemplate.cpp b/clang/lib/Parse/ParseTemplate.cpp
index 53c4829f43f4e..0406820f74a33 100644
--- a/clang/lib/Parse/ParseTemplate.cpp
+++ b/clang/lib/Parse/ParseTemplate.cpp
@@ -710,7 +710,8 @@ bool Parser::TryAnnotateTypeConstraint() {
                                       /*ObjectType=*/ParsedType(),
                                       /*EnteringContext=*/false,
                                       PossibleConcept,
-                                      MemberOfUnknownSpecialization);
+                                      MemberOfUnknownSpecialization,
+                                      /*Disambiguation=*/true);
     if (MemberOfUnknownSpecialization || !PossibleConcept ||
         TNK != TNK_Concept_template) {
       if (SS.isNotEmpty())
diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td
index ab3310ac89204..651ca8aefc3cc 100644
--- a/clang/lib/Sema/OpenCLBuiltins.td
+++ b/clang/lib/Sema/OpenCLBuiltins.td
@@ -290,7 +290,10 @@ def Image2dMsaaDepth      : Type<"image2d_msaa_depth_t", QualType<"OCLImage2dMSA
 def Image2dArrayMsaaDepth : Type<"image2d_array_msaa_depth_t", QualType<"OCLImage2dArrayMSAADepth", 1>>;
 
 def Sampler               : Type<"sampler_t", QualType<"OCLSamplerTy">>;
+def ClkEvent              : Type<"clk_event_t", QualType<"OCLClkEventTy">>;
 def Event                 : Type<"event_t", QualType<"OCLEventTy">>;
+def Queue                 : Type<"queue_t", QualType<"OCLQueueTy">>;
+def ReserveId             : Type<"reserve_id_t", QualType<"OCLReserveIDTy">>;
 
 // OpenCL v2.0 s6.13.11: Atomic integer and floating-point types.
 def AtomicInt             : Type<"atomic_int", QualType<"getAtomicType(Context.IntTy)">>;
@@ -1234,6 +1237,44 @@ let MinVersion = CL20 in {
 }
 
 
+//--------------------------------------------------------------------
+// OpenCL2.0 : 6.13.16 : Pipe Functions
+// --- Table 27 ---
+// Defined in Builtins.def
+
+// --- Table 28 ---
+// Builtins taking pipe arguments are defined in Builtins.def
+def : Builtin<"is_valid_reserve_id", [Bool, ReserveId]>;
+
+// --- Table 29 ---
+// Defined in Builtins.def
+
+
+//--------------------------------------------------------------------
+// OpenCL2.0 : 6.13.17 : Enqueuing Kernels
+// --- Table 30 ---
+// Defined in Builtins.def
+
+// --- Table 32 ---
+// Defined in Builtins.def
+
+// --- Table 33 ---
+def : Builtin<"enqueue_marker",
+    [Int, Queue, UInt, PointerType<ConstType<ClkEvent>, GenericAS>, PointerType<ClkEvent, GenericAS>]>;
+
+// --- Table 34 ---
+def : Builtin<"retain_event", [Void, ClkEvent]>;
+def : Builtin<"release_event", [Void, ClkEvent]>;
+def : Builtin<"create_user_event", [ClkEvent]>;
+def : Builtin<"is_valid_event", [Bool, ClkEvent]>;
+def : Builtin<"set_user_event_status", [Void, ClkEvent, Int]>;
+// TODO: capture_event_profiling_info
+
+// --- Table 35 ---
+def : Builtin<"get_default_queue", [Queue]>;
+// TODO: ndrange functions
+
+
 // OpenCL v2.0 s9.17.3: Additions to section 6.13.1: Work-Item Functions
 let MinVersion = CL20 in {
   let Extension = FuncExtKhrSubgroups in {
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 67348b39acb37..b4d3258371274 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -2712,6 +2712,18 @@ static void checkNewAttributesAfterDef(Sema &S, Decl *New, const Decl *Old) {
         --E;
         continue;
       }
+    } else if (isa<LoaderUninitializedAttr>(NewAttribute)) {
+      // If there is a C definition followed by a redeclaration with this
+      // attribute then there are two different definitions. In C++, prefer the
+      // standard diagnostics.
+      if (!S.getLangOpts().CPlusPlus) {
+        S.Diag(NewAttribute->getLocation(),
+               diag::err_loader_uninitialized_redeclaration);
+        S.Diag(Def->getLocation(), diag::note_previous_definition);
+        NewAttributes.erase(NewAttributes.begin() + I);
+        --E;
+        continue;
+      }
     } else if (isa<SelectAnyAttr>(NewAttribute) &&
                cast<VarDecl>(New)->isInline() &&
                !cast<VarDecl>(New)->isInlineSpecified()) {
@@ -11928,6 +11940,13 @@ void Sema::AddInitializerToDecl(Decl *RealDecl, Expr *Init, bool DirectInit) {
     return;
   }
 
+  // The LoaderUninitialized attribute acts as a definition (of undef).
+  if (VDecl->hasAttr<LoaderUninitializedAttr>()) {
+    Diag(VDecl->getLocation(), diag::err_loader_uninitialized_cant_init);
+    VDecl->setInvalidDecl();
+    return;
+  }
+
   // Get the decls type and save a reference for later, since
   // CheckInitializerTypes may change it.
   QualType DclT = VDecl->getType(), SavT = DclT;
@@ -12341,6 +12360,22 @@ void Sema::ActOnUninitializedDecl(Decl *RealDecl) {
       return;
     }
 
+    if (!Var->isInvalidDecl() && RealDecl->hasAttr<LoaderUninitializedAttr>()) {
+      if (CXXRecordDecl *RD = Var->getType()->getAsCXXRecordDecl()) {
+        if (!RD->hasTrivialDefaultConstructor()) {
+          Diag(Var->getLocation(), diag::err_loader_uninitialized_trivial_ctor);
+          Var->setInvalidDecl();
+          return;
+        }
+      }
+      if (Var->getStorageClass() == SC_Extern) {
+        Diag(Var->getLocation(), diag::err_loader_uninitialized_extern_decl)
+            << Var;
+        Var->setInvalidDecl();
+        return;
+      }
+    }
+
     VarDecl::DefinitionKind DefKind = Var->isThisDeclarationADefinition();
     if (!Var->isInvalidDecl() && DefKind != VarDecl::DeclarationOnly &&
         Var->getType().hasNonTrivialToPrimitiveDefaultInitializeCUnion())
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 12e7cc869fb0c..f18ebef074711 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -8107,6 +8107,10 @@ static void ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D,
     handleUninitializedAttr(S, D, AL);
     break;
 
+  case ParsedAttr::AT_LoaderUninitialized:
+    handleSimpleAttribute<LoaderUninitializedAttr>(S, D, AL);
+    break;
+
   case ParsedAttr::AT_ObjCExternallyRetained:
     handleObjCExternallyRetainedAttr(S, D, AL);
     break;
diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp
index 141eeb8682746..9f19dae5dbe93 100644
--- a/clang/lib/Sema/SemaDeclCXX.cpp
+++ b/clang/lib/Sema/SemaDeclCXX.cpp
@@ -15567,6 +15567,11 @@ VarDecl *Sema::BuildExceptionDeclaration(Scope *S,
       !BaseType->isDependentType() && RequireCompleteType(Loc, BaseType, DK))
     Invalid = true;
 
+  if (!Invalid && Mode != 1 && BaseType->isSizelessType()) {
+    Diag(Loc, diag::err_catch_sizeless) << (Mode == 2 ? 1 : 0) << BaseType;
+    Invalid = true;
+  }
+
   if (!Invalid && !ExDeclType->isDependentType() &&
       RequireNonAbstractType(Loc, ExDeclType,
                              diag::err_abstract_type_in_decl,
diff --git a/clang/lib/Sema/SemaExceptionSpec.cpp b/clang/lib/Sema/SemaExceptionSpec.cpp
index 1e892aa622df7..5c9844e1cd281 100644
--- a/clang/lib/Sema/SemaExceptionSpec.cpp
+++ b/clang/lib/Sema/SemaExceptionSpec.cpp
@@ -167,6 +167,14 @@ bool Sema::CheckSpecifiedExceptionType(QualType &T, SourceRange Range) {
       RequireCompleteType(Range.getBegin(), PointeeT, DiagID, Kind, Range))
     return ReturnValueOnError;
 
+  // The MSVC compatibility mode doesn't extend to sizeless types,
+  // so diagnose them separately.
+  if (PointeeT->isSizelessType() && Kind != 1) {
+    Diag(Range.getBegin(), diag::err_sizeless_in_exception_spec)
+        << (Kind == 2 ? 1 : 0) << PointeeT << Range;
+    return true;
+  }
+
   return false;
 }
 
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index e55bd51815639..27343daa22c85 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "TreeTransform.h"
+#include "UsedDeclVisitor.h"
 #include "clang/AST/ASTConsumer.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/ASTLambda.h"
@@ -4966,8 +4967,9 @@ Sema::CreateBuiltinArraySubscriptExpr(Expr *Base, SourceLocation LLoc,
     // See IsCForbiddenLValueType.
     if (!ResultType.hasQualifiers()) VK = VK_RValue;
   } else if (!ResultType->isDependentType() &&
-      RequireCompleteType(LLoc, ResultType,
-                          diag::err_subscript_incomplete_type, BaseExpr))
+             RequireCompleteSizedType(
+                 LLoc, ResultType,
+                 diag::err_subscript_incomplete_or_sizeless_type, BaseExpr))
     return ExprError();
 
   assert(VK == VK_RValue || LangOpts.CPlusPlus ||
@@ -9614,9 +9616,10 @@ static bool checkArithmeticIncompletePointerType(Sema &S, SourceLocation Loc,
 
   assert(ResType->isAnyPointerType() && !ResType->isDependentType());
   QualType PointeeTy = ResType->getPointeeType();
-  return S.RequireCompleteType(Loc, PointeeTy,
-                               diag::err_typecheck_arithmetic_incomplete_type,
-                               PointeeTy, Operand->getSourceRange());
+  return S.RequireCompleteSizedType(
+      Loc, PointeeTy,
+      diag::err_typecheck_arithmetic_incomplete_or_sizeless_type,
+      Operand->getSourceRange());
 }
 
 /// Check the validity of an arithmetic pointer operand.
@@ -14285,11 +14288,9 @@ ExprResult Sema::ActOnChooseExpr(SourceLocation BuiltinLoc,
   ExprValueKind VK = VK_RValue;
   ExprObjectKind OK = OK_Ordinary;
   QualType resType;
-  bool ValueDependent = false;
   bool CondIsTrue = false;
   if (CondExpr->isTypeDependent() || CondExpr->isValueDependent()) {
     resType = Context.DependentTy;
-    ValueDependent = true;
   } else {
     // The conditional expression is required to be a constant expression.
     llvm::APSInt condEval(32);
@@ -14305,14 +14306,12 @@ ExprResult Sema::ActOnChooseExpr(SourceLocation BuiltinLoc,
     Expr *ActiveExpr = CondIsTrue ? LHSExpr : RHSExpr;
 
     resType = ActiveExpr->getType();
-    ValueDependent = ActiveExpr->isValueDependent();
     VK = ActiveExpr->getValueKind();
     OK = ActiveExpr->getObjectKind();
   }
 
-  return new (Context)
-      ChooseExpr(BuiltinLoc, CondExpr, LHSExpr, RHSExpr, resType, VK, OK, RPLoc,
-                 CondIsTrue, resType->isDependentType(), ValueDependent);
+  return new (Context) ChooseExpr(BuiltinLoc, CondExpr, LHSExpr, RHSExpr,
+                                  resType, VK, OK, RPLoc, CondIsTrue);
 }
 
 //===----------------------------------------------------------------------===//
@@ -17485,71 +17484,33 @@ void Sema::MarkDeclarationsReferencedInType(SourceLocation Loc, QualType T) {
 }
 
 namespace {
-  /// Helper class that marks all of the declarations referenced by
-  /// potentially-evaluated subexpressions as "referenced".
-  class EvaluatedExprMarker : public EvaluatedExprVisitor<EvaluatedExprMarker> {
-    Sema &S;
-    bool SkipLocalVariables;
-
-  public:
-    typedef EvaluatedExprVisitor<EvaluatedExprMarker> Inherited;
-
-    EvaluatedExprMarker(Sema &S, bool SkipLocalVariables)
-      : Inherited(S.Context), S(S), SkipLocalVariables(SkipLocalVariables) { }
-
-    void VisitDeclRefExpr(DeclRefExpr *E) {
-      // If we were asked not to visit local variables, don't.
-      if (SkipLocalVariables) {
-        if (VarDecl *VD = dyn_cast<VarDecl>(E->getDecl()))
-          if (VD->hasLocalStorage())
-            return;
-      }
-
-      S.MarkDeclRefReferenced(E);
-    }
-
-    void VisitMemberExpr(MemberExpr *E) {
-      S.MarkMemberReferenced(E);
-      Inherited::VisitMemberExpr(E);
-    }
-
-    void VisitCXXBindTemporaryExpr(CXXBindTemporaryExpr *E) {
-      S.MarkFunctionReferenced(
-          E->getBeginLoc(),
-          const_cast<CXXDestructorDecl *>(E->getTemporary()->getDestructor()));
-      Visit(E->getSubExpr());
-    }
+/// Helper class that marks all of the declarations referenced by
+/// potentially-evaluated subexpressions as "referenced".
+class EvaluatedExprMarker : public UsedDeclVisitor<EvaluatedExprMarker> {
+public:
+  typedef UsedDeclVisitor<EvaluatedExprMarker> Inherited;
+  bool SkipLocalVariables;
 
-    void VisitCXXNewExpr(CXXNewExpr *E) {
-      if (E->getOperatorNew())
-        S.MarkFunctionReferenced(E->getBeginLoc(), E->getOperatorNew());
-      if (E->getOperatorDelete())
-        S.MarkFunctionReferenced(E->getBeginLoc(), E->getOperatorDelete());
-      Inherited::VisitCXXNewExpr(E);
-    }
+  EvaluatedExprMarker(Sema &S, bool SkipLocalVariables)
+      : Inherited(S), SkipLocalVariables(SkipLocalVariables) {}
 
-    void VisitCXXDeleteExpr(CXXDeleteExpr *E) {
-      if (E->getOperatorDelete())
-        S.MarkFunctionReferenced(E->getBeginLoc(), E->getOperatorDelete());
-      QualType Destroyed = S.Context.getBaseElementType(E->getDestroyedType());
-      if (const RecordType *DestroyedRec = Destroyed->getAs<RecordType>()) {
-        CXXRecordDecl *Record = cast<CXXRecordDecl>(DestroyedRec->getDecl());
-        S.MarkFunctionReferenced(E->getBeginLoc(), S.LookupDestructor(Record));
-      }
-
-      Inherited::VisitCXXDeleteExpr(E);
-    }
+  void visitUsedDecl(SourceLocation Loc, Decl *D) {
+    S.MarkFunctionReferenced(Loc, cast<FunctionDecl>(D));
+  }
 
-    void VisitCXXConstructExpr(CXXConstructExpr *E) {
-      S.MarkFunctionReferenced(E->getBeginLoc(), E->getConstructor());
-      Inherited::VisitCXXConstructExpr(E);
+  void VisitDeclRefExpr(DeclRefExpr *E) {
+    // If we were asked not to visit local variables, don't.
+    if (SkipLocalVariables) {
+      if (VarDecl *VD = dyn_cast<VarDecl>(E->getDecl()))
+        if (VD->hasLocalStorage())
+          return;
     }
+    S.MarkDeclRefReferenced(E);
+  }
 
-    void VisitCXXDefaultArgExpr(CXXDefaultArgExpr *E) {
-      Visit(E->getExpr());
-    }
-  };
-}
+  void VisitMemberExpr(MemberExpr *E) { S.MarkMemberReferenced(E); }
+};
+} // namespace
 
 /// Mark any declarations that appear within this expression or any
 /// potentially-evaluated subexpressions as "referenced".
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index e6ec7e6eeb551..afa46fb04822d 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -961,6 +961,11 @@ bool Sema::CheckCXXThrowOperand(SourceLocation ThrowLoc,
                             E->getSourceRange()))
       return true;
 
+    if (!isPointer && Ty->isSizelessType()) {
+      Diag(ThrowLoc, diag::err_throw_sizeless) << Ty << E->getSourceRange();
+      return true;
+    }
+
     if (RequireNonAbstractType(ThrowLoc, ExceptionObjectTy,
                                diag::err_throw_abstract_type, E))
       return true;
@@ -2344,7 +2349,8 @@ bool Sema::CheckAllocatedType(QualType AllocType, SourceLocation Loc,
     return Diag(Loc, diag::err_bad_new_type)
       << AllocType << 1 << R;
   else if (!AllocType->isDependentType() &&
-           RequireCompleteType(Loc, AllocType, diag::err_new_incomplete_type,R))
+           RequireCompleteSizedType(
+               Loc, AllocType, diag::err_new_incomplete_or_sizeless_type, R))
     return true;
   else if (RequireNonAbstractType(Loc, AllocType,
                                   diag::err_allocation_of_abstract_type))
@@ -3470,7 +3476,8 @@ Sema::ActOnCXXDelete(SourceLocation StartLoc, bool UseGlobal,
       // this, so we treat it as a warning unless we're in a SFINAE context.
       Diag(StartLoc, diag::ext_delete_void_ptr_operand)
         << Type << Ex.get()->getSourceRange();
-    } else if (Pointee->isFunctionType() || Pointee->isVoidType()) {
+    } else if (Pointee->isFunctionType() || Pointee->isVoidType() ||
+               Pointee->isSizelessType()) {
       return ExprError(Diag(StartLoc, diag::err_delete_operand)
         << Type << Ex.get()->getSourceRange());
     } else if (!Pointee->isDependentType()) {
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index 898f658fcf9c4..7d0821829daa5 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -270,6 +270,8 @@ class DSAStackTy {
   QualType OMPAllocatorHandleT;
   /// omp_depend_t type.
   QualType OMPDependT;
+  /// omp_event_handle_t type.
+  QualType OMPEventHandleT;
   /// Expression for the predefined allocators.
   Expr *OMPPredefinedAllocators[OMPAllocateDeclAttr::OMPUserDefinedMemAlloc] = {
       nullptr};
@@ -298,6 +300,11 @@ class DSAStackTy {
   /// Gets omp_depend_t type.
   QualType getOMPDependT() const { return OMPDependT; }
 
+  /// Sets omp_event_handle_t type.
+  void setOMPEventHandleT(QualType Ty) { OMPEventHandleT = Ty; }
+  /// Gets omp_event_handle_t type.
+  QualType getOMPEventHandleT() const { return OMPEventHandleT; }
+
   bool isClauseParsingMode() const { return ClauseKindMode != OMPC_unknown; }
   OpenMPClauseKind getClauseParsingMode() const {
     assert(isClauseParsingMode() && "Must be in clause parsing mode.");
@@ -4722,6 +4729,11 @@ StmtResult Sema::ActOnOpenMPExecutableDirective(
           if (E)
             ImplicitFirstprivates.emplace_back(E);
       }
+      // OpenMP 5.0, 2.10.1 task Construct
+      // [detach clause]... The event-handle will be considered as if it was
+      // specified on a firstprivate clause.
+      if (auto *DC = dyn_cast<OMPDetachClause>(C))
+        ImplicitFirstprivates.push_back(DC->getEventHandler());
     }
     if (!ImplicitFirstprivates.empty()) {
       if (OMPClause *Implicit = ActOnOpenMPFirstprivateClause(
@@ -5090,6 +5102,7 @@ StmtResult Sema::ActOnOpenMPExecutableDirective(
           break;
         continue;
       case OMPC_schedule:
+      case OMPC_detach:
         break;
       case OMPC_grainsize:
       case OMPC_num_tasks:
@@ -8619,12 +8632,41 @@ Sema::ActOnOpenMPParallelSectionsDirective(ArrayRef<OMPClause *> Clauses,
       Context, StartLoc, EndLoc, Clauses, AStmt, DSAStack->isCancelRegion());
 }
 
+/// detach and mergeable clauses are mutially exclusive, check for it.
+static bool checkDetachMergeableClauses(Sema &S,
+                                        ArrayRef<OMPClause *> Clauses) {
+  const OMPClause *PrevClause = nullptr;
+  bool ErrorFound = false;
+  for (const OMPClause *C : Clauses) {
+    if (C->getClauseKind() == OMPC_detach ||
+        C->getClauseKind() == OMPC_mergeable) {
+      if (!PrevClause) {
+        PrevClause = C;
+      } else if (PrevClause->getClauseKind() != C->getClauseKind()) {
+        S.Diag(C->getBeginLoc(), diag::err_omp_clauses_mutually_exclusive)
+            << getOpenMPClauseName(C->getClauseKind())
+            << getOpenMPClauseName(PrevClause->getClauseKind());
+        S.Diag(PrevClause->getBeginLoc(), diag::note_omp_previous_clause)
+            << getOpenMPClauseName(PrevClause->getClauseKind());
+        ErrorFound = true;
+      }
+    }
+  }
+  return ErrorFound;
+}
+
 StmtResult Sema::ActOnOpenMPTaskDirective(ArrayRef<OMPClause *> Clauses,
                                           Stmt *AStmt, SourceLocation StartLoc,
                                           SourceLocation EndLoc) {
   if (!AStmt)
     return StmtError();
 
+  // OpenMP 5.0, 2.10.1 task Construct
+  // If a detach clause appears on the directive, then a mergeable clause cannot
+  // appear on the same directive.
+  if (checkDetachMergeableClauses(*this, Clauses))
+    return StmtError();
+
   auto *CS = cast<CapturedStmt>(AStmt);
   // 1.2.2 OpenMP Language Terminology
   // Structured block - An executable statement with a single entry at the
@@ -9884,12 +9926,10 @@ static bool checkGrainsizeNumTasksClauses(Sema &S,
       if (!PrevClause)
         PrevClause = C;
       else if (PrevClause->getClauseKind() != C->getClauseKind()) {
-        S.Diag(C->getBeginLoc(),
-               diag::err_omp_grainsize_num_tasks_mutually_exclusive)
+        S.Diag(C->getBeginLoc(), diag::err_omp_clauses_mutually_exclusive)
             << getOpenMPClauseName(C->getClauseKind())
             << getOpenMPClauseName(PrevClause->getClauseKind());
-        S.Diag(PrevClause->getBeginLoc(),
-               diag::note_omp_previous_grainsize_num_tasks)
+        S.Diag(PrevClause->getBeginLoc(), diag::note_omp_previous_clause)
             << getOpenMPClauseName(PrevClause->getClauseKind());
         ErrorFound = true;
       }
@@ -11003,9 +11043,6 @@ OMPClause *Sema::ActOnOpenMPSingleExprClause(OpenMPClauseKind Kind, Expr *Expr,
   case OMPC_ordered:
     Res = ActOnOpenMPOrderedClause(StartLoc, EndLoc, LParenLoc, Expr);
     break;
-  case OMPC_device:
-    Res = ActOnOpenMPDeviceClause(Expr, StartLoc, LParenLoc, EndLoc);
-    break;
   case OMPC_num_teams:
     Res = ActOnOpenMPNumTeamsClause(Expr, StartLoc, LParenLoc, EndLoc);
     break;
@@ -11027,6 +11064,10 @@ OMPClause *Sema::ActOnOpenMPSingleExprClause(OpenMPClauseKind Kind, Expr *Expr,
   case OMPC_depobj:
     Res = ActOnOpenMPDepobjClause(Expr, StartLoc, LParenLoc, EndLoc);
     break;
+  case OMPC_detach:
+    Res = ActOnOpenMPDetachClause(Expr, StartLoc, LParenLoc, EndLoc);
+    break;
+  case OMPC_device:
   case OMPC_if:
   case OMPC_default:
   case OMPC_proc_bind:
@@ -11806,6 +11847,7 @@ static OpenMPDirectiveKind getOpenMPCaptureRegionForClause(
   case OMPC_nontemporal:
   case OMPC_order:
   case OMPC_destroy:
+  case OMPC_detach:
     llvm_unreachable("Unexpected OpenMP clause.");
   }
   return CaptureRegion;
@@ -12242,6 +12284,7 @@ OMPClause *Sema::ActOnOpenMPSimpleClause(
   case OMPC_match:
   case OMPC_nontemporal:
   case OMPC_destroy:
+  case OMPC_detach:
     llvm_unreachable("Clause is not allowed.");
   }
   return Res;
@@ -12395,6 +12438,12 @@ OMPClause *Sema::ActOnOpenMPSingleExprWithArgClause(
         StartLoc, LParenLoc, ArgumentLoc[Modifier], ArgumentLoc[DefaultmapKind],
         EndLoc);
     break;
+  case OMPC_device:
+    assert(Argument.size() == 1 && ArgumentLoc.size() == 1);
+    Res = ActOnOpenMPDeviceClause(
+        static_cast<OpenMPDeviceClauseModifier>(Argument.back()), Expr,
+        StartLoc, LParenLoc, ArgumentLoc.back(), EndLoc);
+    break;
   case OMPC_final:
   case OMPC_num_threads:
   case OMPC_safelen:
@@ -12432,7 +12481,6 @@ OMPClause *Sema::ActOnOpenMPSingleExprWithArgClause(
   case OMPC_release:
   case OMPC_relaxed:
   case OMPC_depend:
-  case OMPC_device:
   case OMPC_threads:
   case OMPC_simd:
   case OMPC_map:
@@ -12459,6 +12507,7 @@ OMPClause *Sema::ActOnOpenMPSingleExprWithArgClause(
   case OMPC_nontemporal:
   case OMPC_order:
   case OMPC_destroy:
+  case OMPC_detach:
     llvm_unreachable("Clause is not allowed.");
   }
   return Res;
@@ -12688,6 +12737,7 @@ OMPClause *Sema::ActOnOpenMPClause(OpenMPClauseKind Kind,
   case OMPC_match:
   case OMPC_nontemporal:
   case OMPC_order:
+  case OMPC_detach:
     llvm_unreachable("Clause is not allowed.");
   }
   return Res;
@@ -12943,6 +12993,7 @@ OMPClause *Sema::ActOnOpenMPVarListClause(
   case OMPC_match:
   case OMPC_order:
   case OMPC_destroy:
+  case OMPC_detach:
     llvm_unreachable("Clause is not allowed.");
   }
   return Res;
@@ -13389,7 +13440,8 @@ OMPClause *Sema::ActOnOpenMPFirstprivateClause(ArrayRef<Expr *> VarList,
           ExprCaptures.push_back(Ref->getDecl());
       }
     }
-    DSAStack->addDSA(D, RefExpr->IgnoreParens(), OMPC_firstprivate, Ref);
+    if (!IsImplicitClause)
+      DSAStack->addDSA(D, RefExpr->IgnoreParens(), OMPC_firstprivate, Ref);
     Vars.push_back((VD || CurContext->isDependentContext())
                        ? RefExpr->IgnoreParens()
                        : Ref);
@@ -15592,16 +15644,32 @@ Sema::ActOnOpenMPDependClause(OpenMPDependClauseKind DepKind,
   return C;
 }
 
-OMPClause *Sema::ActOnOpenMPDeviceClause(Expr *Device, SourceLocation StartLoc,
+OMPClause *Sema::ActOnOpenMPDeviceClause(OpenMPDeviceClauseModifier Modifier,
+                                         Expr *Device, SourceLocation StartLoc,
                                          SourceLocation LParenLoc,
+                                         SourceLocation ModifierLoc,
                                          SourceLocation EndLoc) {
+  assert((ModifierLoc.isInvalid() || LangOpts.OpenMP >= 50) &&
+         "Unexpected device modifier in OpenMP < 50.");
+
+  bool ErrorFound = false;
+  if (ModifierLoc.isValid() && Modifier == OMPC_DEVICE_unknown) {
+    std::string Values =
+        getListOfPossibleValues(OMPC_device, /*First=*/0, OMPC_DEVICE_unknown);
+    Diag(ModifierLoc, diag::err_omp_unexpected_clause_value)
+        << Values << getOpenMPClauseName(OMPC_device);
+    ErrorFound = true;
+  }
+
   Expr *ValExpr = Device;
   Stmt *HelperValStmt = nullptr;
 
   // OpenMP [2.9.1, Restrictions]
   // The device expression must evaluate to a non-negative integer value.
-  if (!isNonNegativeIntegerValue(ValExpr, *this, OMPC_device,
-                                 /*StrictlyPositive=*/false))
+  ErrorFound = !isNonNegativeIntegerValue(ValExpr, *this, OMPC_device,
+                                          /*StrictlyPositive=*/false) ||
+               ErrorFound;
+  if (ErrorFound)
     return nullptr;
 
   OpenMPDirectiveKind DKind = DSAStack->getCurrentDirective();
@@ -15614,8 +15682,9 @@ OMPClause *Sema::ActOnOpenMPDeviceClause(Expr *Device, SourceLocation StartLoc,
     HelperValStmt = buildPreInits(Context, Captures);
   }
 
-  return new (Context) OMPDeviceClause(ValExpr, HelperValStmt, CaptureRegion,
-                                       StartLoc, LParenLoc, EndLoc);
+  return new (Context)
+      OMPDeviceClause(Modifier, ValExpr, HelperValStmt, CaptureRegion, StartLoc,
+                      LParenLoc, ModifierLoc, EndLoc);
 }
 
 static bool checkTypeMappable(SourceLocation SL, SourceRange SR, Sema &SemaRef,
@@ -17266,6 +17335,68 @@ OMPClause *Sema::ActOnOpenMPHintClause(Expr *Hint, SourceLocation StartLoc,
       OMPHintClause(HintExpr.get(), StartLoc, LParenLoc, EndLoc);
 }
 
+/// Tries to find omp_event_handle_t type.
+static bool findOMPEventHandleT(Sema &S, SourceLocation Loc,
+                                DSAStackTy *Stack) {
+  QualType OMPEventHandleT = Stack->getOMPEventHandleT();
+  if (!OMPEventHandleT.isNull())
+    return true;
+  IdentifierInfo *II = &S.PP.getIdentifierTable().get("omp_event_handle_t");
+  ParsedType PT = S.getTypeName(*II, Loc, S.getCurScope());
+  if (!PT.getAsOpaquePtr() || PT.get().isNull()) {
+    S.Diag(Loc, diag::err_omp_implied_type_not_found) << "omp_event_handle_t";
+    return false;
+  }
+  Stack->setOMPEventHandleT(PT.get());
+  return true;
+}
+
+OMPClause *Sema::ActOnOpenMPDetachClause(Expr *Evt, SourceLocation StartLoc,
+                                         SourceLocation LParenLoc,
+                                         SourceLocation EndLoc) {
+  if (!Evt->isValueDependent() && !Evt->isTypeDependent() &&
+      !Evt->isInstantiationDependent() &&
+      !Evt->containsUnexpandedParameterPack()) {
+    if (!findOMPEventHandleT(*this, Evt->getExprLoc(), DSAStack))
+      return nullptr;
+    // OpenMP 5.0, 2.10.1 task Construct.
+    // event-handle is a variable of the omp_event_handle_t type.
+    auto *Ref = dyn_cast<DeclRefExpr>(Evt->IgnoreParenImpCasts());
+    if (!Ref) {
+      Diag(Evt->getExprLoc(), diag::err_omp_event_var_expected)
+          << 0 << Evt->getSourceRange();
+      return nullptr;
+    }
+    auto *VD = dyn_cast_or_null<VarDecl>(Ref->getDecl());
+    if (!VD) {
+      Diag(Evt->getExprLoc(), diag::err_omp_event_var_expected)
+          << 0 << Evt->getSourceRange();
+      return nullptr;
+    }
+    if (!Context.hasSameUnqualifiedType(DSAStack->getOMPEventHandleT(),
+                                        VD->getType()) ||
+        VD->getType().isConstant(Context)) {
+      Diag(Evt->getExprLoc(), diag::err_omp_event_var_expected)
+          << 1 << VD->getType() << Evt->getSourceRange();
+      return nullptr;
+    }
+    // OpenMP 5.0, 2.10.1 task Construct
+    // [detach clause]... The event-handle will be considered as if it was
+    // specified on a firstprivate clause.
+    DSAStackTy::DSAVarData DVar = DSAStack->getTopDSA(VD, /*FromParent=*/false);
+    if (DVar.CKind != OMPC_unknown && DVar.CKind != OMPC_firstprivate &&
+        DVar.RefExpr) {
+      Diag(Evt->getExprLoc(), diag::err_omp_wrong_dsa)
+          << getOpenMPClauseName(DVar.CKind)
+          << getOpenMPClauseName(OMPC_firstprivate);
+      reportOriginalDsa(*this, DSAStack, VD, DVar);
+      return nullptr;
+    }
+  }
+
+  return new (Context) OMPDetachClause(Evt, StartLoc, LParenLoc, EndLoc);
+}
+
 OMPClause *Sema::ActOnOpenMPDistScheduleClause(
     OpenMPDistScheduleClauseKind Kind, Expr *ChunkSize, SourceLocation StartLoc,
     SourceLocation LParenLoc, SourceLocation KindLoc, SourceLocation CommaLoc,
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 9ecf5867e9661..d80aac9d703ac 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -13,7 +13,7 @@
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/CXXInheritance.h"
 #include "clang/AST/DeclObjC.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/ExprCXX.h"
 #include "clang/AST/ExprObjC.h"
diff --git a/clang/lib/Sema/SemaPseudoObject.cpp b/clang/lib/Sema/SemaPseudoObject.cpp
index 5587e0d24c7f4..87c3c264b472e 100644
--- a/clang/lib/Sema/SemaPseudoObject.cpp
+++ b/clang/lib/Sema/SemaPseudoObject.cpp
@@ -167,16 +167,11 @@ namespace {
         Expr *&rebuiltExpr = ce->isConditionTrue() ? LHS : RHS;
         rebuiltExpr = rebuild(rebuiltExpr);
 
-        return new (S.Context) ChooseExpr(ce->getBuiltinLoc(),
-                                          ce->getCond(),
-                                          LHS, RHS,
-                                          rebuiltExpr->getType(),
-                                          rebuiltExpr->getValueKind(),
-                                          rebuiltExpr->getObjectKind(),
-                                          ce->getRParenLoc(),
-                                          ce->isConditionTrue(),
-                                          rebuiltExpr->isTypeDependent(),
-                                          rebuiltExpr->isValueDependent());
+        return new (S.Context)
+            ChooseExpr(ce->getBuiltinLoc(), ce->getCond(), LHS, RHS,
+                       rebuiltExpr->getType(), rebuiltExpr->getValueKind(),
+                       rebuiltExpr->getObjectKind(), ce->getRParenLoc(),
+                       ce->isConditionTrue());
       }
 
       llvm_unreachable("bad expression to rebuild!");
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 4923d0a6dad2a..f95b16c1cbaed 100755
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -174,7 +174,8 @@ TemplateNameKind Sema::isTemplateName(Scope *S,
                                       ParsedType ObjectTypePtr,
                                       bool EnteringContext,
                                       TemplateTy &TemplateResult,
-                                      bool &MemberOfUnknownSpecialization) {
+                                      bool &MemberOfUnknownSpecialization,
+                                      bool Disambiguation) {
   assert(getLangOpts().CPlusPlus && "No template names in C!");
 
   DeclarationName TName;
@@ -204,7 +205,7 @@ TemplateNameKind Sema::isTemplateName(Scope *S,
   LookupResult R(*this, TName, Name.getBeginLoc(), LookupOrdinaryName);
   if (LookupTemplateName(R, S, SS, ObjectType, EnteringContext,
                          MemberOfUnknownSpecialization, SourceLocation(),
-                         &AssumedTemplate))
+                         &AssumedTemplate, Disambiguation))
     return TNK_Non_template;
 
   if (AssumedTemplate != AssumedTemplateKind::None) {
@@ -371,7 +372,8 @@ bool Sema::LookupTemplateName(LookupResult &Found,
                               bool EnteringContext,
                               bool &MemberOfUnknownSpecialization,
                               SourceLocation TemplateKWLoc,
-                              AssumedTemplateKind *ATK) {
+                              AssumedTemplateKind *ATK,
+                              bool Disambiguation) {
   if (ATK)
     *ATK = AssumedTemplateKind::None;
 
@@ -494,8 +496,9 @@ bool Sema::LookupTemplateName(LookupResult &Found,
     }
   }
 
-  if (Found.empty() && !IsDependent) {
-    // If we did not find any names, attempt to correct any typos.
+  if (Found.empty() && !IsDependent && !Disambiguation) {
+    // If we did not find any names, and this is not a disambiguation, attempt
+    // to correct any typos.
     DeclarationName Name = Found.getLookupName();
     Found.clear();
     // Simple filter callback that, for keywords, only accepts the C++ *_cast
@@ -5925,7 +5928,9 @@ bool UnnamedLocalNoLinkageFinder::VisitDependentNameType(
 
 bool UnnamedLocalNoLinkageFinder::VisitDependentTemplateSpecializationType(
                                  const DependentTemplateSpecializationType* T) {
-  return VisitNestedNameSpecifier(T->getQualifier());
+  if (auto *Q = T->getQualifier())
+    return VisitNestedNameSpecifier(Q);
+  return false;
 }
 
 bool UnnamedLocalNoLinkageFinder::VisitPackExpansionType(
@@ -5979,6 +5984,7 @@ bool UnnamedLocalNoLinkageFinder::VisitTagDecl(const TagDecl *Tag) {
 
 bool UnnamedLocalNoLinkageFinder::VisitNestedNameSpecifier(
                                                     NestedNameSpecifier *NNS) {
+  assert(NNS);
   if (NNS->getPrefix() && VisitNestedNameSpecifier(NNS->getPrefix()))
     return true;
 
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 223462aaf3624..91d0a1cfa74b6 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -1851,11 +1851,13 @@ class TreeTransform {
   ///
   /// By default, performs semantic analysis to build the new statement.
   /// Subclasses may override this routine to provide different behavior.
-  OMPClause *RebuildOMPDeviceClause(Expr *Device, SourceLocation StartLoc,
+  OMPClause *RebuildOMPDeviceClause(OpenMPDeviceClauseModifier Modifier,
+                                    Expr *Device, SourceLocation StartLoc,
                                     SourceLocation LParenLoc,
+                                    SourceLocation ModifierLoc,
                                     SourceLocation EndLoc) {
-    return getSema().ActOnOpenMPDeviceClause(Device, StartLoc, LParenLoc,
-                                             EndLoc);
+    return getSema().ActOnOpenMPDeviceClause(Modifier, Device, StartLoc,
+                                             LParenLoc, ModifierLoc, EndLoc);
   }
 
   /// Build a new OpenMP 'map' clause.
@@ -1954,6 +1956,16 @@ class TreeTransform {
     return getSema().ActOnOpenMPHintClause(Hint, StartLoc, LParenLoc, EndLoc);
   }
 
+  /// Build a new OpenMP 'detach' clause.
+  ///
+  /// By default, performs semantic analysis to build the new statement.
+  /// Subclasses may override this routine to provide different behavior.
+  OMPClause *RebuildOMPDetachClause(Expr *Evt, SourceLocation StartLoc,
+                                    SourceLocation LParenLoc,
+                                    SourceLocation EndLoc) {
+    return getSema().ActOnOpenMPDetachClause(Evt, StartLoc, LParenLoc, EndLoc);
+  }
+
   /// Build a new OpenMP 'dist_schedule' clause.
   ///
   /// By default, performs semantic analysis to build the new OpenMP clause.
@@ -8786,6 +8798,19 @@ TreeTransform<Derived>::TransformOMPOrderedClause(OMPOrderedClause *C) {
                                               C->getLParenLoc(), E.get());
 }
 
+template <typename Derived>
+OMPClause *
+TreeTransform<Derived>::TransformOMPDetachClause(OMPDetachClause *C) {
+  ExprResult E;
+  if (Expr *Evt = C->getEventHandler()) {
+    E = getDerived().TransformExpr(Evt);
+    if (E.isInvalid())
+      return nullptr;
+  }
+  return getDerived().RebuildOMPDetachClause(E.get(), C->getBeginLoc(),
+                                             C->getLParenLoc(), C->getEndLoc());
+}
+
 template <typename Derived>
 OMPClause *
 TreeTransform<Derived>::TransformOMPNowaitClause(OMPNowaitClause *C) {
@@ -9240,8 +9265,9 @@ TreeTransform<Derived>::TransformOMPDeviceClause(OMPDeviceClause *C) {
   ExprResult E = getDerived().TransformExpr(C->getDevice());
   if (E.isInvalid())
     return nullptr;
-  return getDerived().RebuildOMPDeviceClause(E.get(), C->getBeginLoc(),
-                                             C->getLParenLoc(), C->getEndLoc());
+  return getDerived().RebuildOMPDeviceClause(
+      C->getModifier(), E.get(), C->getBeginLoc(), C->getLParenLoc(),
+      C->getModifierLoc(), C->getEndLoc());
 }
 
 template <typename Derived, class T>
diff --git a/clang/lib/Sema/UsedDeclVisitor.h b/clang/lib/Sema/UsedDeclVisitor.h
new file mode 100644
index 0000000000000..be46f0d4affcc
--- /dev/null
+++ b/clang/lib/Sema/UsedDeclVisitor.h
@@ -0,0 +1,90 @@
+//===- UsedDeclVisitor.h - ODR-used declarations visitor --------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//===----------------------------------------------------------------------===//
+//
+//  This file defines UsedDeclVisitor, a CRTP class which visits all the
+//  declarations that are ODR-used by an expression or statement.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CLANG_LIB_SEMA_USEDDECLVISITOR_H
+#define LLVM_CLANG_LIB_SEMA_USEDDECLVISITOR_H
+
+#include "clang/AST/EvaluatedExprVisitor.h"
+#include "clang/Sema/SemaInternal.h"
+
+namespace clang {
+template <class Derived>
+class UsedDeclVisitor : public EvaluatedExprVisitor<Derived> {
+protected:
+  Sema &S;
+
+public:
+  typedef EvaluatedExprVisitor<Derived> Inherited;
+
+  UsedDeclVisitor(Sema &S) : Inherited(S.Context), S(S) {}
+
+  Derived &asImpl() { return *static_cast<Derived *>(this); }
+
+  void VisitDeclRefExpr(DeclRefExpr *E) {
+    auto *D = E->getDecl();
+    if (isa<FunctionDecl>(D) || isa<VarDecl>(D)) {
+      asImpl().visitUsedDecl(E->getLocation(), D);
+    }
+  }
+
+  void VisitMemberExpr(MemberExpr *E) {
+    auto *D = E->getMemberDecl();
+    if (isa<FunctionDecl>(D) || isa<VarDecl>(D)) {
+      asImpl().visitUsedDecl(E->getMemberLoc(), D);
+    }
+    asImpl().Visit(E->getBase());
+  }
+
+  void VisitCapturedStmt(CapturedStmt *Node) {
+    asImpl().visitUsedDecl(Node->getBeginLoc(), Node->getCapturedDecl());
+    Inherited::VisitCapturedStmt(Node);
+  }
+
+  void VisitCXXBindTemporaryExpr(CXXBindTemporaryExpr *E) {
+    asImpl().visitUsedDecl(
+        E->getBeginLoc(),
+        const_cast<CXXDestructorDecl *>(E->getTemporary()->getDestructor()));
+    asImpl().Visit(E->getSubExpr());
+  }
+
+  void VisitCXXNewExpr(CXXNewExpr *E) {
+    if (E->getOperatorNew())
+      asImpl().visitUsedDecl(E->getBeginLoc(), E->getOperatorNew());
+    if (E->getOperatorDelete())
+      asImpl().visitUsedDecl(E->getBeginLoc(), E->getOperatorDelete());
+    Inherited::VisitCXXNewExpr(E);
+  }
+
+  void VisitCXXDeleteExpr(CXXDeleteExpr *E) {
+    if (E->getOperatorDelete())
+      asImpl().visitUsedDecl(E->getBeginLoc(), E->getOperatorDelete());
+    QualType Destroyed = S.Context.getBaseElementType(E->getDestroyedType());
+    if (const RecordType *DestroyedRec = Destroyed->getAs<RecordType>()) {
+      CXXRecordDecl *Record = cast<CXXRecordDecl>(DestroyedRec->getDecl());
+      asImpl().visitUsedDecl(E->getBeginLoc(), S.LookupDestructor(Record));
+    }
+
+    Inherited::VisitCXXDeleteExpr(E);
+  }
+
+  void VisitCXXConstructExpr(CXXConstructExpr *E) {
+    asImpl().visitUsedDecl(E->getBeginLoc(), E->getConstructor());
+    Inherited::VisitCXXConstructExpr(E);
+  }
+
+  void VisitCXXDefaultArgExpr(CXXDefaultArgExpr *E) {
+    asImpl().Visit(E->getExpr());
+  }
+};
+} // end namespace clang
+
+#endif // LLVM_CLANG_LIB_SEMA_USEDDECLVISITOR_H
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index 096a741e7bb98..dd0fa9f70dafd 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -11830,6 +11830,9 @@ OMPClause *OMPClauseReader::readClause() {
   case OMPC_destroy:
     C = new (Context) OMPDestroyClause();
     break;
+  case OMPC_detach:
+    C = new (Context) OMPDetachClause();
+    break;
   }
   assert(C && "Unknown OMPClause type");
 
@@ -11928,6 +11931,11 @@ void OMPClauseReader::VisitOMPOrderedClause(OMPOrderedClause *C) {
   C->setLParenLoc(Record.readSourceLocation());
 }
 
+void OMPClauseReader::VisitOMPDetachClause(OMPDetachClause *C) {
+  C->setEventHandler(Record.readSubExpr());
+  C->setLParenLoc(Record.readSourceLocation());
+}
+
 void OMPClauseReader::VisitOMPNowaitClause(OMPNowaitClause *) {}
 
 void OMPClauseReader::VisitOMPUntiedClause(OMPUntiedClause *) {}
@@ -12286,7 +12294,9 @@ void OMPClauseReader::VisitOMPDependClause(OMPDependClause *C) {
 
 void OMPClauseReader::VisitOMPDeviceClause(OMPDeviceClause *C) {
   VisitOMPClauseWithPreInit(C);
+  C->setModifier(Record.readEnum<OpenMPDeviceClauseModifier>());
   C->setDevice(Record.readSubExpr());
+  C->setModifierLoc(Record.readSourceLocation());
   C->setLParenLoc(Record.readSourceLocation());
 }
 
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index 4efd337650b29..d74b0d514eda0 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -21,7 +21,7 @@
 #include "clang/AST/DeclObjC.h"
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/DeclarationName.h"
-#include "clang/AST/DependencyFlags.h"
+#include "clang/AST/DependenceFlags.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/ExprCXX.h"
 #include "clang/AST/ExprObjC.h"
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 1278841a15a2e..c96e46543dbad 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -6096,6 +6096,11 @@ void OMPClauseWriter::VisitOMPCollapseClause(OMPCollapseClause *C) {
   Record.AddSourceLocation(C->getLParenLoc());
 }
 
+void OMPClauseWriter::VisitOMPDetachClause(OMPDetachClause *C) {
+  Record.AddStmt(C->getEventHandler());
+  Record.AddSourceLocation(C->getLParenLoc());
+}
+
 void OMPClauseWriter::VisitOMPDefaultClause(OMPDefaultClause *C) {
   Record.push_back(unsigned(C->getDefaultKind()));
   Record.AddSourceLocation(C->getLParenLoc());
@@ -6371,7 +6376,9 @@ void OMPClauseWriter::VisitOMPDependClause(OMPDependClause *C) {
 
 void OMPClauseWriter::VisitOMPDeviceClause(OMPDeviceClause *C) {
   VisitOMPClauseWithPreInit(C);
+  Record.writeEnum(C->getModifier());
   Record.AddStmt(C->getDevice());
+  Record.AddSourceLocation(C->getModifierLoc());
   Record.AddSourceLocation(C->getLParenLoc());
 }
 
diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
index d52b3f371af95..210a4ff199c63 100644
--- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
@@ -71,14 +71,6 @@ class StdLibraryFunctionsChecker : public Checker<check::PostCall, eval::Call> {
   /// to us. If he doesn't, he performs additional invalidations.
   enum InvalidationKind { NoEvalCall, EvalCallAsPure };
 
-  /// A pair of ValueRangeKind and IntRangeVector would describe a range
-  /// imposed on a particular argument or return value symbol.
-  ///
-  /// Given a range, should the argument stay inside or outside this range?
-  /// The special `ComparesToArgument' value indicates that we should
-  /// impose a constraint that involves other argument or return value symbols.
-  enum ValueRangeKind { OutOfRange, WithinRange, ComparesToArgument };
-
   // The universal integral type to use in value range descriptions.
   // Unsigned to make sure overflows are well-defined.
   typedef uint64_t RangeInt;
@@ -93,44 +85,42 @@ class StdLibraryFunctionsChecker : public Checker<check::PostCall, eval::Call> {
   /// ArgNo in CallExpr and CallEvent is defined as Unsigned, but
   /// obviously uint32_t should be enough for all practical purposes.
   typedef uint32_t ArgNo;
-  static const ArgNo Ret = std::numeric_limits<ArgNo>::max();
-
-  /// Incapsulates a single range on a single symbol within a branch.
-  class ValueRange {
-    ArgNo ArgN;          // Argument to which we apply the range.
-    ValueRangeKind Kind; // Kind of range definition.
-    IntRangeVector Args; // Polymorphic arguments.
+  static const ArgNo Ret;
 
+  /// Polymorphic base class that represents a constraint on a given argument
+  /// (or return value) of a function. Derived classes implement different kind
+  /// of constraints, e.g range constraints or correlation between two
+  /// arguments.
+  class ValueConstraint {
   public:
-    ValueRange(ArgNo ArgN, ValueRangeKind Kind, const IntRangeVector &Args)
-        : ArgN(ArgN), Kind(Kind), Args(Args) {}
-
+    ValueConstraint(ArgNo ArgN) : ArgN(ArgN) {}
+    virtual ~ValueConstraint() {}
+    /// Apply the effects of the constraint on the given program state. If null
+    /// is returned then the constraint is not feasible.
+    virtual ProgramStateRef apply(ProgramStateRef State, const CallEvent &Call,
+                                  const Summary &Summary) const = 0;
     ArgNo getArgNo() const { return ArgN; }
-    ValueRangeKind getKind() const { return Kind; }
-
-    BinaryOperator::Opcode getOpcode() const {
-      assert(Kind == ComparesToArgument);
-      assert(Args.size() == 1);
-      BinaryOperator::Opcode Op =
-          static_cast<BinaryOperator::Opcode>(Args[0].first);
-      assert(BinaryOperator::isComparisonOp(Op) &&
-             "Only comparison ops are supported for ComparesToArgument");
-      return Op;
-    }
 
-    ArgNo getOtherArgNo() const {
-      assert(Kind == ComparesToArgument);
-      assert(Args.size() == 1);
-      return static_cast<ArgNo>(Args[0].second);
-    }
+  protected:
+    ArgNo ArgN; // Argument to which we apply the constraint.
+  };
+
+  /// Given a range, should the argument stay inside or outside this range?
+  enum RangeKind { OutOfRange, WithinRange };
+
+  /// Encapsulates a single range on a single symbol within a branch.
+  class RangeConstraint : public ValueConstraint {
+    RangeKind Kind;      // Kind of range definition.
+    IntRangeVector Args; // Polymorphic arguments.
+
+  public:
+    RangeConstraint(ArgNo ArgN, RangeKind Kind, const IntRangeVector &Args)
+        : ValueConstraint(ArgN), Kind(Kind), Args(Args) {}
 
     const IntRangeVector &getRanges() const {
-      assert(Kind != ComparesToArgument);
       return Args;
     }
 
-    // We avoid creating a virtual apply() method because
-    // it makes initializer lists harder to write.
   private:
     ProgramStateRef applyAsOutOfRange(ProgramStateRef State,
                                       const CallEvent &Call,
@@ -138,30 +128,44 @@ class StdLibraryFunctionsChecker : public Checker<check::PostCall, eval::Call> {
     ProgramStateRef applyAsWithinRange(ProgramStateRef State,
                                        const CallEvent &Call,
                                        const Summary &Summary) const;
-    ProgramStateRef applyAsComparesToArgument(ProgramStateRef State,
-                                              const CallEvent &Call,
-                                              const Summary &Summary) const;
-
   public:
     ProgramStateRef apply(ProgramStateRef State, const CallEvent &Call,
-                          const Summary &Summary) const {
+                          const Summary &Summary) const override {
       switch (Kind) {
       case OutOfRange:
         return applyAsOutOfRange(State, Call, Summary);
       case WithinRange:
         return applyAsWithinRange(State, Call, Summary);
-      case ComparesToArgument:
-        return applyAsComparesToArgument(State, Call, Summary);
       }
-      llvm_unreachable("Unknown ValueRange kind!");
+      llvm_unreachable("Unknown range kind!");
     }
   };
 
-  /// The complete list of ranges that defines a single branch.
-  typedef std::vector<ValueRange> ValueRangeSet;
+  class ComparisonConstraint : public ValueConstraint {
+    BinaryOperator::Opcode Opcode;
+    ArgNo OtherArgN;
+
+  public:
+    ComparisonConstraint(ArgNo ArgN, BinaryOperator::Opcode Opcode,
+                         ArgNo OtherArgN)
+        : ValueConstraint(ArgN), Opcode(Opcode), OtherArgN(OtherArgN) {}
+    ArgNo getOtherArgNo() const { return OtherArgN; }
+    BinaryOperator::Opcode getOpcode() const { return Opcode; }
+    ProgramStateRef apply(ProgramStateRef State, const CallEvent &Call,
+                          const Summary &Summary) const override;
+  };
+
+  // Pointer to the ValueConstraint. We need a copyable, polymorphic and
+  // default initialize able type (vector needs that). A raw pointer was good,
+  // however, we cannot default initialize that. unique_ptr makes the Summary
+  // class non-copyable, therefore not an option. Releasing the copyability
+  // requirement would render the initialization of the Summary map infeasible.
+  using ValueConstraintPtr = std::shared_ptr<ValueConstraint>;
+  /// The complete list of constraints that defines a single branch.
+  typedef std::vector<ValueConstraintPtr> ConstraintSet;
 
   using ArgTypes = std::vector<QualType>;
-  using Ranges = std::vector<ValueRangeSet>;
+  using Cases = std::vector<ConstraintSet>;
 
   /// Includes information about function prototype (which is necessary to
   /// ensure we're modeling the right function and casting values properly),
@@ -171,14 +175,14 @@ class StdLibraryFunctionsChecker : public Checker<check::PostCall, eval::Call> {
     const ArgTypes ArgTys;
     const QualType RetTy;
     const InvalidationKind InvalidationKd;
-    Ranges Cases;
-    ValueRangeSet ArgConstraints;
+    Cases CaseConstraints;
+    ConstraintSet ArgConstraints;
 
     Summary(ArgTypes ArgTys, QualType RetTy, InvalidationKind InvalidationKd)
         : ArgTys(ArgTys), RetTy(RetTy), InvalidationKd(InvalidationKd) {}
 
-    Summary &Case(ValueRangeSet VRS) {
-      Cases.push_back(VRS);
+    Summary &Case(ConstraintSet&& CS) {
+      CaseConstraints.push_back(std::move(CS));
       return *this;
     }
 
@@ -244,9 +248,13 @@ class StdLibraryFunctionsChecker : public Checker<check::PostCall, eval::Call> {
 
   void initFunctionSummaries(CheckerContext &C) const;
 };
+
+const StdLibraryFunctionsChecker::ArgNo StdLibraryFunctionsChecker::Ret =
+    std::numeric_limits<ArgNo>::max();
+
 } // end of anonymous namespace
 
-ProgramStateRef StdLibraryFunctionsChecker::ValueRange::applyAsOutOfRange(
+ProgramStateRef StdLibraryFunctionsChecker::RangeConstraint::applyAsOutOfRange(
     ProgramStateRef State, const CallEvent &Call,
     const Summary &Summary) const {
 
@@ -273,7 +281,7 @@ ProgramStateRef StdLibraryFunctionsChecker::ValueRange::applyAsOutOfRange(
   return State;
 }
 
-ProgramStateRef StdLibraryFunctionsChecker::ValueRange::applyAsWithinRange(
+ProgramStateRef StdLibraryFunctionsChecker::RangeConstraint::applyAsWithinRange(
     ProgramStateRef State, const CallEvent &Call,
     const Summary &Summary) const {
 
@@ -330,8 +338,7 @@ ProgramStateRef StdLibraryFunctionsChecker::ValueRange::applyAsWithinRange(
   return State;
 }
 
-ProgramStateRef
-StdLibraryFunctionsChecker::ValueRange::applyAsComparesToArgument(
+ProgramStateRef StdLibraryFunctionsChecker::ComparisonConstraint::apply(
     ProgramStateRef State, const CallEvent &Call,
     const Summary &Summary) const {
 
@@ -367,15 +374,15 @@ void StdLibraryFunctionsChecker::checkPostCall(const CallEvent &Call,
   if (!FoundSummary)
     return;
 
-  // Now apply ranges.
+  // Now apply the constraints.
   const Summary &Summary = *FoundSummary;
   ProgramStateRef State = C.getState();
 
   // Apply case/branch specifications.
-  for (const auto &VRS : Summary.Cases) {
+  for (const auto &VRS : Summary.CaseConstraints) {
     ProgramStateRef NewState = State;
     for (const auto &VR: VRS) {
-      NewState = VR.apply(NewState, Call, Summary);
+      NewState = VR->apply(NewState, Call, Summary);
       if (!NewState)
         break;
     }
@@ -510,8 +517,14 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
   const RangeInt LongMax = BVF.getMaxValue(LongTy).getLimitedValue();
   const RangeInt LongLongMax = BVF.getMaxValue(LongLongTy).getLimitedValue();
 
-  const RangeInt UCharMax =
-      BVF.getMaxValue(ACtx.UnsignedCharTy).getLimitedValue();
+  // Set UCharRangeMax to min of int or uchar maximum value.
+  // The C standard states that the arguments of functions like isalpha must
+  // be representable as an unsigned char. Their type is 'int', so the max
+  // value of the argument should be min(UCharMax, IntMax). This just happen
+  // to be true for commonly used and well tested instruction set
+  // architectures, but not for others.
+  const RangeInt UCharRangeMax =
+      std::min(BVF.getMaxValue(ACtx.UnsignedCharTy).getLimitedValue(), IntMax);
 
   // The platform dependent value of EOF.
   // Try our best to parse this from the Preprocessor, otherwise fallback to -1.
@@ -549,44 +562,46 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
   // Please update the list of functions in the header after editing!
   //
 
-  // Below are helper functions to create the summaries.
-  auto ArgumentCondition = [](ArgNo ArgN, ValueRangeKind Kind,
-                              IntRangeVector Ranges) -> ValueRange {
-    ValueRange VR{ArgN, Kind, Ranges};
-    return VR;
-  };
-  auto ReturnValueCondition = [](ValueRangeKind Kind,
-                                 IntRangeVector Ranges) -> ValueRange {
-    ValueRange VR{Ret, Kind, Ranges};
-    return VR;
+  // Below are helpers functions to create the summaries.
+  auto ArgumentCondition = [](ArgNo ArgN, RangeKind Kind,
+                              IntRangeVector Ranges) {
+    return std::make_shared<RangeConstraint>(ArgN, Kind, Ranges);
   };
+  struct {
+    auto operator()(RangeKind Kind, IntRangeVector Ranges) {
+      return std::make_shared<RangeConstraint>(Ret, Kind, Ranges);
+    }
+    auto operator()(BinaryOperator::Opcode Op, ArgNo OtherArgN) {
+      return std::make_shared<ComparisonConstraint>(Ret, Op, OtherArgN);
+    }
+  } ReturnValueCondition;
   auto Range = [](RangeInt b, RangeInt e) {
     return IntRangeVector{std::pair<RangeInt, RangeInt>{b, e}};
   };
   auto SingleValue = [](RangeInt v) {
     return IntRangeVector{std::pair<RangeInt, RangeInt>{v, v}};
   };
-  auto IsLessThan = [](ArgNo ArgN) { return IntRangeVector{{BO_LE, ArgN}}; };
+  auto LessThanOrEq = BO_LE;
 
   using RetType = QualType;
 
   // Templates for summaries that are reused by many functions.
   auto Getc = [&]() {
     return Summary(ArgTypes{Irrelevant}, RetType{IntTy}, NoEvalCall)
-        .Case(
-            {ReturnValueCondition(WithinRange, {{EOFv, EOFv}, {0, UCharMax}})});
+        .Case({ReturnValueCondition(WithinRange,
+                                    {{EOFv, EOFv}, {0, UCharRangeMax}})});
   };
   auto Read = [&](RetType R, RangeInt Max) {
     return Summary(ArgTypes{Irrelevant, Irrelevant, SizeTy}, RetType{R},
                    NoEvalCall)
-        .Case({ReturnValueCondition(ComparesToArgument, IsLessThan(2)),
+        .Case({ReturnValueCondition(LessThanOrEq, ArgNo(2)),
                ReturnValueCondition(WithinRange, Range(-1, Max))});
   };
   auto Fread = [&]() {
     return Summary(ArgTypes{Irrelevant, Irrelevant, SizeTy, Irrelevant},
                    RetType{SizeTy}, NoEvalCall)
         .Case({
-            ReturnValueCondition(ComparesToArgument, IsLessThan(2)),
+            ReturnValueCondition(LessThanOrEq, ArgNo(2)),
         });
   };
   auto Getline = [&](RetType R, RangeInt Max) {
@@ -609,12 +624,13 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
                   // The locale-specific range.
                   // No post-condition. We are completely unaware of
                   // locale-specific return values.
-                  .Case({ArgumentCondition(0U, WithinRange, {{128, UCharMax}})})
+                  .Case({ArgumentCondition(0U, WithinRange,
+                                           {{128, UCharRangeMax}})})
                   .Case({ArgumentCondition(0U, OutOfRange,
                                            {{'0', '9'},
                                             {'A', 'Z'},
                                             {'a', 'z'},
-                                            {128, UCharMax}}),
+                                            {128, UCharRangeMax}}),
                          ReturnValueCondition(WithinRange, SingleValue(0))})},
       },
       {
@@ -625,10 +641,11 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
                                            {{'A', 'Z'}, {'a', 'z'}}),
                          ReturnValueCondition(OutOfRange, SingleValue(0))})
                   // The locale-specific range.
-                  .Case({ArgumentCondition(0U, WithinRange, {{128, UCharMax}})})
+                  .Case({ArgumentCondition(0U, WithinRange,
+                                           {{128, UCharRangeMax}})})
                   .Case({ArgumentCondition(
                              0U, OutOfRange,
-                             {{'A', 'Z'}, {'a', 'z'}, {128, UCharMax}}),
+                             {{'A', 'Z'}, {'a', 'z'}, {128, UCharRangeMax}}),
                          ReturnValueCondition(WithinRange, SingleValue(0))})},
       },
       {
@@ -692,9 +709,11 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
                          ArgumentCondition(0U, OutOfRange, Range('a', 'z')),
                          ReturnValueCondition(WithinRange, SingleValue(0))})
                   // The locale-specific range.
-                  .Case({ArgumentCondition(0U, WithinRange, {{128, UCharMax}})})
+                  .Case({ArgumentCondition(0U, WithinRange,
+                                           {{128, UCharRangeMax}})})
                   // Is not an unsigned char.
-                  .Case({ArgumentCondition(0U, OutOfRange, Range(0, UCharMax)),
+                  .Case({ArgumentCondition(0U, OutOfRange,
+                                           Range(0, UCharRangeMax)),
                          ReturnValueCondition(WithinRange, SingleValue(0))})},
       },
       {
@@ -728,10 +747,11 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
                                            {{9, 13}, {' ', ' '}}),
                          ReturnValueCondition(OutOfRange, SingleValue(0))})
                   // The locale-specific range.
-                  .Case({ArgumentCondition(0U, WithinRange, {{128, UCharMax}})})
+                  .Case({ArgumentCondition(0U, WithinRange,
+                                           {{128, UCharRangeMax}})})
                   .Case({ArgumentCondition(
                              0U, OutOfRange,
-                             {{9, 13}, {' ', ' '}, {128, UCharMax}}),
+                             {{9, 13}, {' ', ' '}, {128, UCharRangeMax}}),
                          ReturnValueCondition(WithinRange, SingleValue(0))})},
       },
       {
@@ -742,10 +762,11 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
                   .Case({ArgumentCondition(0U, WithinRange, Range('A', 'Z')),
                          ReturnValueCondition(OutOfRange, SingleValue(0))})
                   // The locale-specific range.
-                  .Case({ArgumentCondition(0U, WithinRange, {{128, UCharMax}})})
+                  .Case({ArgumentCondition(0U, WithinRange,
+                                           {{128, UCharRangeMax}})})
                   // Other.
                   .Case({ArgumentCondition(0U, OutOfRange,
-                                           {{'A', 'Z'}, {128, UCharMax}}),
+                                           {{'A', 'Z'}, {128, UCharRangeMax}}),
                          ReturnValueCondition(WithinRange, SingleValue(0))})},
       },
       {
@@ -768,7 +789,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries(
       {"getchar",
        Summaries{Summary(ArgTypes{}, RetType{IntTy}, NoEvalCall)
                      .Case({ReturnValueCondition(
-                         WithinRange, {{EOFv, EOFv}, {0, UCharMax}})})}},
+                         WithinRange, {{EOFv, EOFv}, {0, UCharRangeMax}})})}},
 
       // read()-like functions that never return more than buffer size.
       // We are not sure how ssize_t is defined on every platform, so we
diff --git a/clang/lib/Tooling/Syntax/BuildTree.cpp b/clang/lib/Tooling/Syntax/BuildTree.cpp
index 2430394134037..9ebf7d29d8eda 100644
--- a/clang/lib/Tooling/Syntax/BuildTree.cpp
+++ b/clang/lib/Tooling/Syntax/BuildTree.cpp
@@ -6,10 +6,15 @@
 //
 //===----------------------------------------------------------------------===//
 #include "clang/Tooling/Syntax/BuildTree.h"
+#include "clang/AST/ASTFwd.h"
 #include "clang/AST/Decl.h"
 #include "clang/AST/DeclBase.h"
+#include "clang/AST/DeclCXX.h"
+#include "clang/AST/DeclarationName.h"
 #include "clang/AST/RecursiveASTVisitor.h"
 #include "clang/AST/Stmt.h"
+#include "clang/AST/TypeLoc.h"
+#include "clang/AST/TypeLocVisitor.h"
 #include "clang/Basic/LLVM.h"
 #include "clang/Basic/SourceLocation.h"
 #include "clang/Basic/SourceManager.h"
@@ -20,6 +25,7 @@
 #include "clang/Tooling/Syntax/Tree.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/ScopeExit.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Allocator.h"
 #include "llvm/Support/Casting.h"
@@ -34,6 +40,110 @@ using namespace clang;
 LLVM_ATTRIBUTE_UNUSED
 static bool isImplicitExpr(clang::Expr *E) { return E->IgnoreImplicit() != E; }
 
+static SourceLocation getQualifiedNameStart(DeclaratorDecl *D) {
+  auto DN = D->getDeclName();
+  bool IsAnonymous = DN.isIdentifier() && !DN.getAsIdentifierInfo();
+  if (IsAnonymous)
+    return SourceLocation();
+  return D->getQualifierLoc() ? D->getQualifierLoc().getBeginLoc()
+                              : D->getLocation();
+}
+
+namespace {
+/// Get start location of the Declarator from the TypeLoc.
+/// E.g.:
+///   loc of `(` in `int (a)`
+///   loc of `*` in `int *(a)`
+///   loc of the first `(` in `int (*a)(int)`
+///   loc of the `*` in `int *(a)(int)`
+///   loc of the first `*` in `const int *const *volatile a;`
+///
+/// It is non-trivial to get the start location because TypeLocs are stored
+/// inside out. In the example above `*volatile` is the TypeLoc returned
+/// by `Decl.getTypeSourceInfo()`, and `*const` is what `.getPointeeLoc()`
+/// returns.
+struct GetStartLoc : TypeLocVisitor<GetStartLoc, SourceLocation> {
+  SourceLocation VisitParenTypeLoc(ParenTypeLoc T) {
+    auto L = Visit(T.getInnerLoc());
+    if (L.isValid())
+      return L;
+    return T.getLParenLoc();
+  }
+
+  // Types spelled in the prefix part of the declarator.
+  SourceLocation VisitPointerTypeLoc(PointerTypeLoc T) {
+    return HandlePointer(T);
+  }
+
+  SourceLocation VisitMemberPointerTypeLoc(MemberPointerTypeLoc T) {
+    return HandlePointer(T);
+  }
+
+  SourceLocation VisitBlockPointerTypeLoc(BlockPointerTypeLoc T) {
+    return HandlePointer(T);
+  }
+
+  SourceLocation VisitReferenceTypeLoc(ReferenceTypeLoc T) {
+    return HandlePointer(T);
+  }
+
+  SourceLocation VisitObjCObjectPointerTypeLoc(ObjCObjectPointerTypeLoc T) {
+    return HandlePointer(T);
+  }
+
+  // All other cases are not important, as they are either part of declaration
+  // specifiers (e.g. inheritors of TypeSpecTypeLoc) or introduce modifiers on
+  // existing declarators (e.g. QualifiedTypeLoc). They cannot start the
+  // declarator themselves, but their underlying type can.
+  SourceLocation VisitTypeLoc(TypeLoc T) {
+    auto N = T.getNextTypeLoc();
+    if (!N)
+      return SourceLocation();
+    return Visit(N);
+  }
+
+  SourceLocation VisitFunctionProtoTypeLoc(FunctionProtoTypeLoc T) {
+    if (T.getTypePtr()->hasTrailingReturn())
+      return SourceLocation(); // avoid recursing into the suffix of declarator.
+    return VisitTypeLoc(T);
+  }
+
+private:
+  template <class PtrLoc> SourceLocation HandlePointer(PtrLoc T) {
+    auto L = Visit(T.getPointeeLoc());
+    if (L.isValid())
+      return L;
+    return T.getLocalSourceRange().getBegin();
+  }
+};
+} // namespace
+
+/// Gets the range of declarator as defined by the C++ grammar. E.g.
+///     `int a;` -> range of `a`,
+///     `int *a;` -> range of `*a`,
+///     `int a[10];` -> range of `a[10]`,
+///     `int a[1][2][3];` -> range of `a[1][2][3]`,
+///     `int *a = nullptr` -> range of `*a = nullptr`.
+/// FIMXE: \p Name must be a source range, e.g. for `operator+`.
+static SourceRange getDeclaratorRange(const SourceManager &SM, TypeLoc T,
+                                      SourceLocation Name,
+                                      SourceRange Initializer) {
+  SourceLocation Start = GetStartLoc().Visit(T);
+  SourceLocation End = T.getSourceRange().getEnd();
+  assert(End.isValid());
+  if (Name.isValid()) {
+    if (Start.isInvalid())
+      Start = Name;
+    if (SM.isBeforeInTranslationUnit(End, Name))
+      End = Name;
+  }
+  if (Initializer.isValid()) {
+    assert(SM.isBeforeInTranslationUnit(End, Initializer.getEnd()));
+    End = Initializer.getEnd();
+  }
+  return SourceRange(Start, End);
+}
+
 /// A helper class for constructing the syntax tree while traversing a clang
 /// AST.
 ///
@@ -57,6 +167,7 @@ class syntax::TreeBuilder {
   }
 
   llvm::BumpPtrAllocator &allocator() { return Arena.allocator(); }
+  const SourceManager &sourceManager() const { return Arena.sourceManager(); }
 
   /// Populate children for \p New node, assuming it covers tokens from \p
   /// Range.
@@ -64,16 +175,16 @@ class syntax::TreeBuilder {
 
   /// Must be called with the range of each `DeclaratorDecl`. Ensures the
   /// corresponding declarator nodes are covered by `SimpleDeclaration`.
-  void noticeDeclaratorRange(llvm::ArrayRef<syntax::Token> Range);
+  void noticeDeclRange(llvm::ArrayRef<syntax::Token> Range);
 
   /// Notifies that we should not consume trailing semicolon when computing
   /// token range of \p D.
-  void noticeDeclaratorWithoutSemicolon(Decl *D);
+  void noticeDeclWithoutSemicolon(Decl *D);
 
   /// Mark the \p Child node with a corresponding \p Role. All marked children
   /// should be consumed by foldNode.
-  /// (!) when called on expressions (clang::Expr is derived from clang::Stmt),
-  ///     wraps expressions into expression statement.
+  /// When called on expressions (clang::Expr is derived from clang::Stmt),
+  /// wraps expressions into expression statement.
   void markStmtChild(Stmt *Child, NodeRole Role);
   /// Should be called for expressions in non-statement position to avoid
   /// wrapping into expression statement.
@@ -81,6 +192,13 @@ class syntax::TreeBuilder {
 
   /// Set role for a token starting at \p Loc.
   void markChildToken(SourceLocation Loc, NodeRole R);
+  /// Set role for \p T.
+  void markChildToken(const syntax::Token *T, NodeRole R);
+
+  /// Set role for the node that spans exactly \p Range.
+  void markChild(llvm::ArrayRef<syntax::Token> Range, NodeRole R);
+  /// Set role for the delayed node that spans exactly \p Range.
+  void markDelayedChild(llvm::ArrayRef<syntax::Token> Range, NodeRole R);
 
   /// Finish building the tree and consume the root node.
   syntax::TranslationUnit *finalize() && {
@@ -141,7 +259,7 @@ class syntax::TreeBuilder {
   withTrailingSemicolon(llvm::ArrayRef<syntax::Token> Tokens) const {
     assert(!Tokens.empty());
     assert(Tokens.back().kind() != tok::eof);
-    // (!) we never consume 'eof', so looking at the next token is ok.
+    // We never consume 'eof', so looking at the next token is ok.
     if (Tokens.back().kind() != tok::semi && Tokens.end()->kind() == tok::semi)
       return llvm::makeArrayRef(Tokens.begin(), Tokens.end() + 1);
     return Tokens;
@@ -172,6 +290,14 @@ class syntax::TreeBuilder {
 
     ~Forest() { assert(DelayedFolds.empty()); }
 
+    void assignRoleDelayed(llvm::ArrayRef<syntax::Token> Range,
+                           syntax::NodeRole Role) {
+      auto It = DelayedFolds.find(Range.begin());
+      assert(It != DelayedFolds.end());
+      assert(It->second.End == Range.end());
+      It->second.Role = Role;
+    }
+
     void assignRole(llvm::ArrayRef<syntax::Token> Range,
                     syntax::NodeRole Role) {
       assert(!Range.empty());
@@ -189,12 +315,19 @@ class syntax::TreeBuilder {
                       llvm::ArrayRef<syntax::Token> Tokens,
                       syntax::Tree *Node) {
       // Execute delayed folds inside `Tokens`.
-      auto BeginExecuted = DelayedFolds.lower_bound(Tokens.begin());
-      auto It = BeginExecuted;
-      for (; It != DelayedFolds.end() && It->second.End <= Tokens.end(); ++It)
+      auto BeginFolds = DelayedFolds.lower_bound(Tokens.begin());
+      auto EndFolds = BeginFolds;
+      for (; EndFolds != DelayedFolds.end() &&
+             EndFolds->second.End <= Tokens.end();
+           ++EndFolds)
+        ;
+      // We go in reverse order to ensure we fold deeper nodes first.
+      for (auto RevIt = EndFolds; RevIt != BeginFolds; --RevIt) {
+        auto It = std::prev(RevIt);
         foldChildrenEager(A, llvm::makeArrayRef(It->first, It->second.End),
                           It->second.Node);
-      DelayedFolds.erase(BeginExecuted, It);
+      }
+      DelayedFolds.erase(BeginFolds, EndFolds);
 
       // Attach children to `Node`.
       foldChildrenEager(A, Tokens, Node);
@@ -269,7 +402,7 @@ class syntax::TreeBuilder {
           (EndChildren == Trees.end() || EndChildren->first == Tokens.end()) &&
           "fold crosses boundaries of existing subtrees");
 
-      // (!) we need to go in reverse order, because we can only prepend.
+      // We need to go in reverse order, because we can only prepend.
       for (auto It = EndChildren; It != BeginChildren; --It)
         Node->prependChildLowLevel(std::prev(It)->second.Node,
                                    std::prev(It)->second.Role);
@@ -301,6 +434,7 @@ class syntax::TreeBuilder {
     struct DelayedFold {
       const syntax::Token *End = nullptr;
       syntax::Tree *Node = nullptr;
+      NodeRole Role = NodeRole::Unknown;
     };
     std::map<const syntax::Token *, DelayedFold> DelayedFolds;
   };
@@ -324,16 +458,43 @@ class BuildTreeVisitor : public RecursiveASTVisitor<BuildTreeVisitor> {
 
   bool shouldTraversePostOrder() const { return true; }
 
-  bool WalkUpFromDeclaratorDecl(DeclaratorDecl *D) {
+  bool WalkUpFromDeclaratorDecl(DeclaratorDecl *DD) {
     // Ensure declarators are covered by SimpleDeclaration.
-    Builder.noticeDeclaratorRange(Builder.getRange(D));
-    // FIXME: build nodes for the declarator too.
+    Builder.noticeDeclRange(Builder.getRange(DD));
+
+    // Build the declarator node.
+    SourceRange Initializer;
+    if (auto *V = llvm::dyn_cast<VarDecl>(DD)) {
+      auto *I = V->getInit();
+      // Initializers in range-based-for are not part of the declarator
+      if (I && !V->isCXXForRangeDecl())
+        Initializer = I->getSourceRange();
+    }
+    auto Declarator = getDeclaratorRange(
+        Builder.sourceManager(), DD->getTypeSourceInfo()->getTypeLoc(),
+        getQualifiedNameStart(DD), Initializer);
+    if (Declarator.isValid()) {
+      auto Tokens =
+          Builder.getRange(Declarator.getBegin(), Declarator.getEnd());
+      Builder.foldNode(Tokens, new (allocator()) syntax::SimpleDeclarator);
+      Builder.markChild(Tokens, syntax::NodeRole::SimpleDeclaration_declarator);
+    }
+
     return true;
   }
+
   bool WalkUpFromTypedefNameDecl(TypedefNameDecl *D) {
-    // Also a declarator.
-    Builder.noticeDeclaratorRange(Builder.getRange(D));
-    // FIXME: build nodes for the declarator too.
+    // Ensure declarators are covered by SimpleDeclaration.
+    Builder.noticeDeclRange(Builder.getRange(D));
+
+    auto R = getDeclaratorRange(
+        Builder.sourceManager(), D->getTypeSourceInfo()->getTypeLoc(),
+        /*Name=*/D->getLocation(), /*Initializer=*/SourceRange());
+    if (R.isValid()) {
+      auto Tokens = Builder.getRange(R.getBegin(), R.getEnd());
+      Builder.foldNode(Tokens, new (allocator()) syntax::SimpleDeclarator);
+      Builder.markChild(Tokens, syntax::NodeRole::SimpleDeclaration_declarator);
+    }
     return true;
   }
 
@@ -356,7 +517,7 @@ class BuildTreeVisitor : public RecursiveASTVisitor<BuildTreeVisitor> {
   }
 
   bool WalkUpFromTranslationUnitDecl(TranslationUnitDecl *TU) {
-    // (!) we do not want to call VisitDecl(), the declaration for translation
+    // We do not want to call VisitDecl(), the declaration for translation
     // unit is built by finalize().
     return true;
   }
@@ -401,10 +562,10 @@ class BuildTreeVisitor : public RecursiveASTVisitor<BuildTreeVisitor> {
     if (auto *DS = llvm::dyn_cast_or_null<DeclStmt>(S)) {
       // We want to consume the semicolon, make sure SimpleDeclaration does not.
       for (auto *D : DS->decls())
-        Builder.noticeDeclaratorWithoutSemicolon(D);
+        Builder.noticeDeclWithoutSemicolon(D);
     } else if (auto *E = llvm::dyn_cast_or_null<Expr>(S)) {
-      // (!) do not recurse into subexpressions.
-      // we do not have syntax trees for expressions yet, so we only want to see
+      // Do not recurse into subexpressions.
+      // We do not have syntax trees for expressions yet, so we only want to see
       // the first top-level expression.
       return WalkUpFromExpr(E->IgnoreImplicit());
     }
@@ -431,6 +592,62 @@ class BuildTreeVisitor : public RecursiveASTVisitor<BuildTreeVisitor> {
     return true;
   }
 
+  bool TraverseParenTypeLoc(ParenTypeLoc L) {
+    // We reverse order of traversal to get the proper syntax structure.
+    if (!WalkUpFromParenTypeLoc(L))
+      return false;
+    return TraverseTypeLoc(L.getInnerLoc());
+  }
+
+  bool WalkUpFromParenTypeLoc(ParenTypeLoc L) {
+    Builder.markChildToken(L.getLParenLoc(), syntax::NodeRole::OpenParen);
+    Builder.markChildToken(L.getRParenLoc(), syntax::NodeRole::CloseParen);
+    Builder.foldNode(Builder.getRange(L.getLParenLoc(), L.getRParenLoc()),
+                     new (allocator()) syntax::ParenDeclarator);
+    return true;
+  }
+
+  // Declarator chunks, they are produced by type locs and some clang::Decls.
+  bool WalkUpFromArrayTypeLoc(ArrayTypeLoc L) {
+    Builder.markChildToken(L.getLBracketLoc(), syntax::NodeRole::OpenParen);
+    Builder.markExprChild(L.getSizeExpr(),
+                          syntax::NodeRole::ArraySubscript_sizeExpression);
+    Builder.markChildToken(L.getRBracketLoc(), syntax::NodeRole::CloseParen);
+    Builder.foldNode(Builder.getRange(L.getLBracketLoc(), L.getRBracketLoc()),
+                     new (allocator()) syntax::ArraySubscript);
+    return true;
+  }
+
+  bool WalkUpFromFunctionTypeLoc(FunctionTypeLoc L) {
+    Builder.markChildToken(L.getLParenLoc(), syntax::NodeRole::OpenParen);
+    for (auto *P : L.getParams())
+      Builder.markDelayedChild(
+          Builder.getRange(P),
+          syntax::NodeRole::ParametersAndQualifiers_parameter);
+    Builder.markChildToken(L.getRParenLoc(), syntax::NodeRole::CloseParen);
+    Builder.foldNode(Builder.getRange(L.getLParenLoc(), L.getEndLoc()),
+                     new (allocator()) syntax::ParametersAndQualifiers);
+    return true;
+  }
+
+  bool WalkUpFromFunctionProtoTypeLoc(FunctionProtoTypeLoc L) {
+    if (!L.getTypePtr()->hasTrailingReturn())
+      return WalkUpFromFunctionTypeLoc(L);
+
+    auto TrailingReturnTokens = BuildTrailingReturn(L);
+    // Finish building the node for parameters.
+    Builder.markChild(TrailingReturnTokens,
+                      syntax::NodeRole::ParametersAndQualifiers_trailingReturn);
+    return WalkUpFromFunctionTypeLoc(L);
+  }
+
+  bool WalkUpFromMemberPointerTypeLoc(MemberPointerTypeLoc L) {
+    auto SR = L.getLocalSourceRange();
+    Builder.foldNode(Builder.getRange(SR.getBegin(), SR.getEnd()),
+                     new (allocator()) syntax::MemberPointer);
+    return true;
+  }
+
   // The code below is very regular, it could even be generated with some
   // preprocessor magic. We merely assign roles to the corresponding children
   // and fold resulting nodes.
@@ -597,6 +814,37 @@ class BuildTreeVisitor : public RecursiveASTVisitor<BuildTreeVisitor> {
   }
 
 private:
+  /// Returns the range of the built node.
+  llvm::ArrayRef<syntax::Token> BuildTrailingReturn(FunctionProtoTypeLoc L) {
+    assert(L.getTypePtr()->hasTrailingReturn());
+
+    auto ReturnedType = L.getReturnLoc();
+    // Build node for the declarator, if any.
+    auto ReturnDeclaratorRange =
+        getDeclaratorRange(this->Builder.sourceManager(), ReturnedType,
+                           /*Name=*/SourceLocation(),
+                           /*Initializer=*/SourceLocation());
+    llvm::ArrayRef<syntax::Token> ReturnDeclaratorTokens;
+    if (ReturnDeclaratorRange.isValid()) {
+      ReturnDeclaratorTokens = Builder.getRange(
+          ReturnDeclaratorRange.getBegin(), ReturnDeclaratorRange.getEnd());
+      Builder.foldNode(ReturnDeclaratorTokens,
+                       new (allocator()) syntax::SimpleDeclarator);
+    }
+
+    // Build node for trailing return type.
+    auto Return =
+        Builder.getRange(ReturnedType.getBeginLoc(), ReturnedType.getEndLoc());
+    const auto *Arrow = Return.begin() - 1;
+    assert(Arrow->kind() == tok::arrow);
+    auto Tokens = llvm::makeArrayRef(Arrow, Return.end());
+    Builder.markChildToken(Arrow, syntax::NodeRole::TrailingReturnType_arrow);
+    if (!ReturnDeclaratorTokens.empty())
+      Builder.markChild(ReturnDeclaratorTokens,
+                        syntax::NodeRole::TrailingReturnType_declarator);
+    Builder.foldNode(Tokens, new (allocator()) syntax::TrailingReturnType);
+    return Tokens;
+  }
   /// A small helper to save some typing.
   llvm::BumpPtrAllocator &allocator() { return Builder.allocator(); }
 
@@ -610,15 +858,14 @@ void syntax::TreeBuilder::foldNode(llvm::ArrayRef<syntax::Token> Range,
   Pending.foldChildren(Arena, Range, New);
 }
 
-void syntax::TreeBuilder::noticeDeclaratorRange(
-    llvm::ArrayRef<syntax::Token> Range) {
+void syntax::TreeBuilder::noticeDeclRange(llvm::ArrayRef<syntax::Token> Range) {
   if (Pending.extendDelayedFold(Range))
     return;
   Pending.foldChildrenDelayed(Range,
                               new (allocator()) syntax::SimpleDeclaration);
 }
 
-void syntax::TreeBuilder::noticeDeclaratorWithoutSemicolon(Decl *D) {
+void syntax::TreeBuilder::noticeDeclWithoutSemicolon(Decl *D) {
   DeclsWithoutSemicolons.insert(D);
 }
 
@@ -628,6 +875,22 @@ void syntax::TreeBuilder::markChildToken(SourceLocation Loc, NodeRole Role) {
   Pending.assignRole(*findToken(Loc), Role);
 }
 
+void syntax::TreeBuilder::markChildToken(const syntax::Token *T, NodeRole R) {
+  if (!T)
+    return;
+  Pending.assignRole(*T, R);
+}
+
+void syntax::TreeBuilder::markChild(llvm::ArrayRef<syntax::Token> Range,
+                                    NodeRole R) {
+  Pending.assignRole(Range, R);
+}
+
+void syntax::TreeBuilder::markDelayedChild(llvm::ArrayRef<syntax::Token> Range,
+                                           NodeRole R) {
+  Pending.assignRoleDelayed(Range, R);
+}
+
 void syntax::TreeBuilder::markStmtChild(Stmt *Child, NodeRole Role) {
   if (!Child)
     return;
@@ -638,7 +901,7 @@ void syntax::TreeBuilder::markStmtChild(Stmt *Child, NodeRole Role) {
   if (auto *E = dyn_cast<Expr>(Child)) {
     Pending.assignRole(getExprRange(E),
                        NodeRole::ExpressionStatement_expression);
-    // (!) 'getRange(Stmt)' ensures this already covers a trailing semicolon.
+    // 'getRange(Stmt)' ensures this already covers a trailing semicolon.
     Pending.foldChildren(Arena, Range,
                          new (allocator()) syntax::ExpressionStatement);
   }
diff --git a/clang/lib/Tooling/Syntax/Nodes.cpp b/clang/lib/Tooling/Syntax/Nodes.cpp
index 5b0c5107c134c..4f86007e39bb5 100644
--- a/clang/lib/Tooling/Syntax/Nodes.cpp
+++ b/clang/lib/Tooling/Syntax/Nodes.cpp
@@ -68,6 +68,18 @@ llvm::raw_ostream &syntax::operator<<(llvm::raw_ostream &OS, NodeKind K) {
     return OS << "UsingDeclaration";
   case NodeKind::TypeAliasDeclaration:
     return OS << "TypeAliasDeclaration";
+  case NodeKind::SimpleDeclarator:
+    return OS << "SimpleDeclarator";
+  case NodeKind::ParenDeclarator:
+    return OS << "ParenDeclarator";
+  case NodeKind::ArraySubscript:
+    return OS << "ArraySubscript";
+  case NodeKind::TrailingReturnType:
+    return OS << "TrailingReturnType";
+  case NodeKind::ParametersAndQualifiers:
+    return OS << "ParametersAndQualifiers";
+  case NodeKind::MemberPointer:
+    return OS << "MemberPointer";
   }
   llvm_unreachable("unknown node kind");
 }
@@ -104,6 +116,18 @@ llvm::raw_ostream &syntax::operator<<(llvm::raw_ostream &OS, NodeRole R) {
     return OS << "StaticAssertDeclaration_condition";
   case syntax::NodeRole::StaticAssertDeclaration_message:
     return OS << "StaticAssertDeclaration_message";
+  case syntax::NodeRole::SimpleDeclaration_declarator:
+    return OS << "SimpleDeclaration_declarator";
+  case syntax::NodeRole::ArraySubscript_sizeExpression:
+    return OS << "ArraySubscript_sizeExpression";
+  case syntax::NodeRole::TrailingReturnType_arrow:
+    return OS << "TrailingReturnType_arrow";
+  case syntax::NodeRole::TrailingReturnType_declarator:
+    return OS << "TrailingReturnType_declarator";
+  case syntax::NodeRole::ParametersAndQualifiers_parameter:
+    return OS << "ParametersAndQualifiers_parameter";
+  case syntax::NodeRole::ParametersAndQualifiers_trailingReturn:
+    return OS << "ParametersAndQualifiers_trailingReturn";
   }
   llvm_unreachable("invalid role");
 }
@@ -246,3 +270,73 @@ syntax::Expression *syntax::StaticAssertDeclaration::message() {
   return llvm::cast_or_null<syntax::Expression>(
       findChild(syntax::NodeRole::StaticAssertDeclaration_message));
 }
+
+std::vector<syntax::SimpleDeclarator *>
+syntax::SimpleDeclaration::declarators() {
+  std::vector<syntax::SimpleDeclarator *> Children;
+  for (auto *C = firstChild(); C; C = C->nextSibling()) {
+    if (C->role() == syntax::NodeRole::SimpleDeclaration_declarator)
+      Children.push_back(llvm::cast<syntax::SimpleDeclarator>(C));
+  }
+  return Children;
+}
+
+syntax::Leaf *syntax::ParenDeclarator::lparen() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::OpenParen));
+}
+
+syntax::Leaf *syntax::ParenDeclarator::rparen() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::CloseParen));
+}
+
+syntax::Leaf *syntax::ArraySubscript::lbracket() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::OpenParen));
+}
+
+syntax::Expression *syntax::ArraySubscript::sizeExpression() {
+  return llvm::cast_or_null<syntax::Expression>(
+      findChild(syntax::NodeRole::ArraySubscript_sizeExpression));
+}
+
+syntax::Leaf *syntax::ArraySubscript::rbracket() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::CloseParen));
+}
+
+syntax::Leaf *syntax::TrailingReturnType::arrow() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::TrailingReturnType_arrow));
+}
+
+syntax::SimpleDeclarator *syntax::TrailingReturnType::declarator() {
+  return llvm::cast_or_null<syntax::SimpleDeclarator>(
+      findChild(syntax::NodeRole::TrailingReturnType_declarator));
+}
+
+syntax::Leaf *syntax::ParametersAndQualifiers::lparen() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::OpenParen));
+}
+
+std::vector<syntax::SimpleDeclaration *>
+syntax::ParametersAndQualifiers::parameters() {
+  std::vector<syntax::SimpleDeclaration *> Children;
+  for (auto *C = firstChild(); C; C = C->nextSibling()) {
+    if (C->role() == syntax::NodeRole::ParametersAndQualifiers_parameter)
+      Children.push_back(llvm::cast<syntax::SimpleDeclaration>(C));
+  }
+  return Children;
+}
+
+syntax::Leaf *syntax::ParametersAndQualifiers::rparen() {
+  return llvm::cast_or_null<syntax::Leaf>(
+      findChild(syntax::NodeRole::CloseParen));
+}
+
+syntax::TrailingReturnType *syntax::ParametersAndQualifiers::trailingReturn() {
+  return llvm::cast_or_null<syntax::TrailingReturnType>(
+      findChild(syntax::NodeRole::ParametersAndQualifiers_trailingReturn));
+}
diff --git a/clang/test/AST/ast-dump-openmp-task.c b/clang/test/AST/ast-dump-openmp-task.c
index e275d33285842..139524c378323 100644
--- a/clang/test/AST/ast-dump-openmp-task.c
+++ b/clang/test/AST/ast-dump-openmp-task.c
@@ -1,21 +1,27 @@
-// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fopenmp -ast-dump %s | FileCheck --match-full-lines -implicit-check-not=openmp_structured_block %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fopenmp -fopenmp-version=50 -ast-dump %s | FileCheck --match-full-lines -implicit-check-not=openmp_structured_block %s
 
+typedef unsigned long omp_event_handle_t;
 void test() {
-#pragma omp task
+  omp_event_handle_t evt;
+#pragma omp task detach(evt)
   ;
 }
 
 // CHECK: TranslationUnitDecl {{.*}} <<invalid sloc>> <invalid sloc>
-// CHECK: `-FunctionDecl {{.*}} <{{.*}}ast-dump-openmp-task.c:3:1, line:6:1> line:3:6 test 'void ()'
-// CHECK-NEXT:   `-CompoundStmt {{.*}} <col:13, line:6:1>
-// CHECK-NEXT:     `-OMPTaskDirective {{.*}} <line:4:1, col:17>
-// CHECK-NEXT:       `-CapturedStmt {{.*}} <line:5:3>
+// CHECK: `-FunctionDecl {{.*}} <line:4:1, line:8:1> line:4:6 test 'void ()'
+// CHECK-NEXT:   `-CompoundStmt {{.*}} <col:13, line:8:1>
+// CHECK:          `-OMPTaskDirective {{.*}} <line:6:1, col:29>
+// CHECK-NEXT:       |-OMPDetachClause {{.+}} <col:18, col:28>
+// CHECK-NEXT:       | `-DeclRefExpr {{.+}} <col:25> 'omp_event_handle_t':'unsigned long' lvalue Var {{.+}} 'evt' 'omp_event_handle_t':'unsigned long'
+// CHECK-NEXT:       |-OMPFirstprivateClause {{.+}} <<invalid sloc>> <implicit>
+// CHECK-NEXT:       | `-DeclRefExpr {{.+}} <col:25> 'omp_event_handle_t':'unsigned long' lvalue Var {{.+}} 'evt' 'omp_event_handle_t':'unsigned long'
+// CHECK-NEXT:       `-CapturedStmt {{.*}} <line:7:3>
 // CHECK-NEXT:         `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
 // CHECK-NEXT:           |-NullStmt {{.*}} <col:3>
 // CHECK-NEXT:           |-AlwaysInlineAttr {{.*}} <<invalid sloc>> Implicit __forceinline
-// CHECK-NEXT:           |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit .global_tid. 'const int'
+// CHECK-NEXT:           |-ImplicitParamDecl {{.*}} <line:6:1> col:1 implicit .global_tid. 'const int'
 // CHECK-NEXT:           |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .part_id. 'const int *const restrict'
 // CHECK-NEXT:           |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .privates. 'void *const restrict'
 // CHECK-NEXT:           |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .copy_fn. 'void (*const restrict)(void *const restrict, ...)'
 // CHECK-NEXT:           |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .task_t. 'void *const'
-// CHECK-NEXT:           `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (anonymous at {{.*}}ast-dump-openmp-task.c:4:1) *const restrict'
+// CHECK-NEXT:           `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (anonymous at {{.*}}ast-dump-openmp-task.c:6:1) *const restrict'
diff --git a/clang/test/CodeGen/aarch64-sve-inline-asm-crash.c b/clang/test/CodeGen/aarch64-sve-inline-asm-crash.c
new file mode 100644
index 0000000000000..11ddb7f6d5800
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-inline-asm-crash.c
@@ -0,0 +1,24 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns \
+// RUN:   -target-feature +neon -S -O1 -o - %s 2>&1 | FileCheck %s
+
+// Set a vector constraint for an sve predicate register
+// As the wrong constraint is used for an SVBool,
+// the compiler will try to extend the nxv16i1 to an nxv16i8
+// TODO: We don't have patterns for this yet but once they are added this test
+// should be updated to check for an assembler error
+__SVBool_t funcB1(__SVBool_t in)
+{
+  __SVBool_t ret ;
+  asm volatile (
+    "mov %[ret].b, %[in].b \n"
+    : [ret] "=w" (ret)
+    : [in] "w" (in)
+    :);
+
+  return ret ;
+}
+
+// CHECK: funcB1
+// CHECK-ERROR: fatal error: error in backend: Cannot select
diff --git a/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c b/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
new file mode 100644
index 0000000000000..c68bb25e36fa5
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
@@ -0,0 +1,252 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns \
+// RUN:   -target-feature +neon -S -O1 -o - -emit-llvm %s | FileCheck %s
+
+// Tests to check that all sve datatypes can be passed in as input operands
+// and passed out as output operands.
+
+#define SVINT_TEST(DT, KIND)\
+DT func_int_##DT##KIND(DT in)\
+{\
+  DT out;\
+  asm volatile (\
+    "ptrue p0.b\n"\
+    "mov %[out]." #KIND ", p0/m, %[in]." #KIND "\n"\
+    : [out] "=w" (out)\
+    : [in] "w" (in)\
+    : "p0"\
+    );\
+  return out;\
+}
+
+SVINT_TEST(__SVUint8_t,b);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+SVINT_TEST(__SVUint8_t,h);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+SVINT_TEST(__SVUint8_t,s);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+SVINT_TEST(__SVUint8_t,d);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+
+SVINT_TEST(__SVUint16_t,b);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+SVINT_TEST(__SVUint16_t,h);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+SVINT_TEST(__SVUint16_t,s);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+SVINT_TEST(__SVUint16_t,d);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+
+SVINT_TEST(__SVUint32_t,b);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+SVINT_TEST(__SVUint32_t,h);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+SVINT_TEST(__SVUint32_t,s);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+SVINT_TEST(__SVUint32_t,d);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+
+SVINT_TEST(__SVUint64_t,b);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+SVINT_TEST(__SVUint64_t,h);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+SVINT_TEST(__SVUint64_t,s);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+SVINT_TEST(__SVUint64_t,d);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+
+SVINT_TEST(__SVInt8_t,b);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+SVINT_TEST(__SVInt8_t,h);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+SVINT_TEST(__SVInt8_t,s);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+SVINT_TEST(__SVInt8_t,d);
+// CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in)
+
+SVINT_TEST(__SVInt16_t,b);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+SVINT_TEST(__SVInt16_t,h);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+SVINT_TEST(__SVInt16_t,s);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+SVINT_TEST(__SVInt16_t,d);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in)
+
+SVINT_TEST(__SVInt32_t,b);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+SVINT_TEST(__SVInt32_t,h);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+SVINT_TEST(__SVInt32_t,s);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+SVINT_TEST(__SVInt32_t,d);
+// CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in)
+
+SVINT_TEST(__SVInt64_t,b);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+SVINT_TEST(__SVInt64_t,h);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+SVINT_TEST(__SVInt64_t,s);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+SVINT_TEST(__SVInt64_t,d);
+// CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in)
+
+
+//Test that floats can also be used as datatypes for integer instructions
+//and check all the variants which would not be possible with a float
+//instruction
+SVINT_TEST(__SVFloat16_t,b);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in)
+SVINT_TEST(__SVFloat16_t,h);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in)
+SVINT_TEST(__SVFloat16_t,s);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in)
+SVINT_TEST(__SVFloat16_t,d);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in)
+
+SVINT_TEST(__SVFloat32_t,b);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in)
+SVINT_TEST(__SVFloat32_t,h);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in)
+SVINT_TEST(__SVFloat32_t,s);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in)
+SVINT_TEST(__SVFloat32_t,d);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in)
+
+SVINT_TEST(__SVFloat64_t,b);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in)
+SVINT_TEST(__SVFloat64_t,h);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in)
+SVINT_TEST(__SVFloat64_t,s);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in)
+SVINT_TEST(__SVFloat64_t,d);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in)
+
+
+#define SVBOOL_TEST(KIND)\
+__SVBool_t func_bool_##KIND(__SVBool_t in1, __SVBool_t in2)\
+{\
+  __SVBool_t out;\
+  asm volatile (\
+    "zip1 %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND "\n"\
+    : [out] "=Upa" (out)\
+    :  [in1] "Upa" (in1),\
+      [in2] "Upa" (in2)\
+    :);\
+  return out;\
+}
+
+SVBOOL_TEST(b) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.b, $1.b, $2.b\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2)
+SVBOOL_TEST(h) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.h, $1.h, $2.h\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2)
+SVBOOL_TEST(s) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.s, $1.s, $2.s\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2)
+SVBOOL_TEST(d) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.d, $1.d, $2.d\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2)
+
+
+#define SVBOOL_TEST_UPL(DT, KIND)\
+__SVBool_t func_bool_upl_##KIND(__SVBool_t in1, DT in2, DT in3)\
+{\
+  __SVBool_t out;\
+  asm volatile (\
+    "fadd %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND ", %[in3]." #KIND "\n"\
+    : [out] "=w" (out)\
+    :  [in1] "Upl" (in1),\
+      [in2] "w" (in2),\
+      [in3] "w" (in3)\
+    :);\
+  return out;\
+}
+
+SVBOOL_TEST_UPL(__SVInt8_t, b) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.b, $1.b, $2.b, $3.b\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 16 x i8> %in2, <vscale x 16 x i8> %in3)
+SVBOOL_TEST_UPL(__SVInt16_t, h) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.h, $1.h, $2.h, $3.h\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 8 x i16> %in2, <vscale x 8 x i16> %in3)
+SVBOOL_TEST_UPL(__SVInt32_t, s) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.s, $1.s, $2.s, $3.s\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 4 x i32> %in2, <vscale x 4 x i32> %in3)
+SVBOOL_TEST_UPL(__SVInt64_t, d) ;
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.d, $1.d, $2.d, $3.d\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3)
+
+#define SVFLOAT_TEST(DT,KIND)\
+DT func_float_##DT##KIND(DT inout1, DT in2)\
+{\
+  asm volatile (\
+    "ptrue p0." #KIND ", #1 \n"\
+    "fsub %[inout1]." #KIND ", p0/m, %[inout1]." #KIND ", %[in2]." #KIND "\n"\
+    : [inout1] "=w" (inout1)\
+    : "[inout1]" (inout1),\
+      [in2] "w" (in2)\
+    : "p0");\
+  return inout1 ;\
+}\
+
+SVFLOAT_TEST(__SVFloat16_t,s);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.s, #1 \0Afsub $0.s, p0/m, $0.s, $2.s\0A", "=w,0,w,~{p0}"(<vscale x 8 x half> %inout1, <vscale x 8 x half> %in2)
+SVFLOAT_TEST(__SVFloat16_t,d);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.d, #1 \0Afsub $0.d, p0/m, $0.d, $2.d\0A", "=w,0,w,~{p0}"(<vscale x 8 x half> %inout1, <vscale x 8 x half> %in2)
+
+SVFLOAT_TEST(__SVFloat32_t,s);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.s, #1 \0Afsub $0.s, p0/m, $0.s, $2.s\0A", "=w,0,w,~{p0}"(<vscale x 4 x float> %inout1, <vscale x 4 x float> %in2)
+SVFLOAT_TEST(__SVFloat32_t,d);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.d, #1 \0Afsub $0.d, p0/m, $0.d, $2.d\0A", "=w,0,w,~{p0}"(<vscale x 4 x float> %inout1, <vscale x 4 x float> %in2)
+
+SVFLOAT_TEST(__SVFloat64_t,s);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.s, #1 \0Afsub $0.s, p0/m, $0.s, $2.s\0A", "=w,0,w,~{p0}"(<vscale x 2 x double> %inout1, <vscale x 2 x double> %in2)
+SVFLOAT_TEST(__SVFloat64_t,d);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.d, #1 \0Afsub $0.d, p0/m, $0.d, $2.d\0A", "=w,0,w,~{p0}"(<vscale x 2 x double> %inout1, <vscale x 2 x double> %in2)
+
+#define SVFLOAT_TEST_Y(DT, KIND)\
+__SVBool_t func_float_y_##KIND(DT in1, DT in2)\
+{\
+  __SVBool_t out;\
+  asm volatile (\
+    "fmul %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND "\n"\
+    : [out] "=w" (out)\
+    :  [in1] "w" (in1),\
+      [in2] "y" (in2)\
+    :);\
+  return out;\
+}
+
+SVFLOAT_TEST_Y(__SVFloat16_t,h);
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fmul $0.h, $1.h, $2.h\0A", "=w,w,y"(<vscale x 8 x half> %in1, <vscale x 8 x half> %in2)
+SVFLOAT_TEST_Y(__SVFloat32_t,s);
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fmul $0.s, $1.s, $2.s\0A", "=w,w,y"(<vscale x 4 x float> %in1, <vscale x 4 x float> %in2)
+SVFLOAT_TEST_Y(__SVFloat64_t,d);
+// CHECK: call <vscale x 16 x i1> asm sideeffect "fmul $0.d, $1.d, $2.d\0A", "=w,w,y"(<vscale x 2 x double> %in1, <vscale x 2 x double> %in2)
+
+
+// Another test for floats to include h suffix
+
+#define SVFLOAT_CVT_TEST(DT1,KIND1,DT2,KIND2)\
+DT1 func_float_cvt_##DT1##KIND1##DT2##KIND2(DT2 in1)\
+{\
+  DT1 out1 ;\
+  asm volatile (\
+    "ptrue p0." #KIND2 ", #1 \n"\
+    "fcvt %[out1]." #KIND1 ", p0/m, %[in1]." #KIND2 "\n"\
+    : [out1] "=w" (out1)\
+    : [in1] "w" (in1)\
+    : "p0");\
+  return out1 ;\
+}\
+
+SVFLOAT_CVT_TEST(__SVFloat64_t,d,__SVFloat32_t,s);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.s, #1 \0Afcvt $0.d, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in1)
+SVFLOAT_CVT_TEST(__SVFloat64_t,d,__SVFloat16_t,h);
+// CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.h, #1 \0Afcvt $0.d, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in1)
+SVFLOAT_CVT_TEST(__SVFloat32_t,s,__SVFloat16_t,h);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.h, #1 \0Afcvt $0.s, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in1)
+SVFLOAT_CVT_TEST(__SVFloat32_t,s,__SVFloat64_t,d);
+// CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.d, #1 \0Afcvt $0.s, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in1)
+SVFLOAT_CVT_TEST(__SVFloat16_t,h,__SVFloat64_t,d);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.d, #1 \0Afcvt $0.h, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in1)
+SVFLOAT_CVT_TEST(__SVFloat16_t,h,__SVFloat32_t,s);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.s, #1 \0Afcvt $0.h, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in1)
+
+//Test a mix of float and ints
+SVFLOAT_CVT_TEST(__SVInt16_t,h,__SVFloat32_t,s);
+// CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.s, #1 \0Afcvt $0.h, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in1)
+SVFLOAT_CVT_TEST(__SVFloat16_t,s,__SVUint32_t,d);
+// CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.d, #1 \0Afcvt $0.s, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in1)
diff --git a/clang/test/CodeGen/aarch64-sve-inline-asm-negative-test.c b/clang/test/CodeGen/aarch64-sve-inline-asm-negative-test.c
new file mode 100644
index 0000000000000..ffe7a41946941
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-inline-asm-negative-test.c
@@ -0,0 +1,21 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns \
+// RUN:   -target-feature +neon -S -O1 -o - %s | FileCheck %s
+
+// Assembler error
+// Output constraint : Set a vector constraint on an integer
+__SVFloat32_t funcB2()
+{
+  __SVFloat32_t ret ;
+  asm volatile (
+    "fmov %[ret], wzr \n"
+    : [ret] "=w" (ret)
+    :
+    :);
+
+  return ret ;
+}
+
+// CHECK: funcB2
+// CHECK-ERROR: error: invalid operand for instruction
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c
new file mode 100644
index 0000000000000..82f66432fe332
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c
@@ -0,0 +1,83 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s -D__ARM_FEATURE_SVE | FileCheck %s
+
+#include <arm_sve.h>
+//
+// ld1
+//
+
+svint8_t test_svld1_s8(svbool_t pg, const int8_t *base)
+{
+  // CHECK-LABEL: test_svld1_s8
+  // CHECK: <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %{{.*}}, i32 1, <vscale x 16 x i1> %{{.*}}, <vscale x 16 x i8> zeroinitializer)
+  return svld1_s8(pg, base);
+}
+
+svint16_t test_svld1_s16(svbool_t pg, const int16_t *base)
+{
+  // CHECK-LABEL: test_svld1_s16
+  // CHECK: <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %{{.*}}, i32 1, <vscale x 8 x i1> %{{.*}}, <vscale x 8 x i16> zeroinitializer)
+  return svld1_s16(pg, base);
+}
+
+svint32_t test_svld1_s32(svbool_t pg, const int32_t *base)
+{
+  // CHECK-LABEL: test_svld1_s32
+  // CHECK: <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %{{.*}}, i32 1, <vscale x 4 x i1> %{{.*}}, <vscale x 4 x i32> zeroinitializer)
+  return svld1_s32(pg, base);
+}
+
+svint64_t test_svld1_s64(svbool_t pg, const int64_t *base)
+{
+  // CHECK-LABEL: test_svld1_s64
+  // CHECK: <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %{{.*}}, i32 1, <vscale x 2 x i1> %{{.*}}, <vscale x 2 x i64> zeroinitializer)
+  return svld1_s64(pg, base);
+}
+
+svuint8_t test_svld1_u8(svbool_t pg, const uint8_t *base)
+{
+  // CHECK-LABEL: test_svld1_u8
+  // CHECK: <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %{{.*}}, i32 1, <vscale x 16 x i1> %{{.*}}, <vscale x 16 x i8> zeroinitializer)
+  return svld1_u8(pg, base);
+}
+
+svuint16_t test_svld1_u16(svbool_t pg, const uint16_t *base)
+{
+  // CHECK-LABEL: test_svld1_u16
+  // CHECK: <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %{{.*}}, i32 1, <vscale x 8 x i1> %{{.*}}, <vscale x 8 x i16> zeroinitializer)
+  return svld1_u16(pg, base);
+}
+
+svuint32_t test_svld1_u32(svbool_t pg, const uint32_t *base)
+{
+  // CHECK-LABEL: test_svld1_u32
+  // CHECK: <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %{{.*}}, i32 1, <vscale x 4 x i1> %{{.*}}, <vscale x 4 x i32> zeroinitializer)
+  return svld1_u32(pg, base);
+}
+
+svuint64_t test_svld1_u64(svbool_t pg, const uint64_t *base)
+{
+  // CHECK-LABEL: test_svld1_u64
+  // CHECK: <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %{{.*}}, i32 1, <vscale x 2 x i1> %{{.*}}, <vscale x 2 x i64> zeroinitializer)
+  return svld1_u64(pg, base);
+}
+
+svfloat16_t test_svld1_f16(svbool_t pg, const float16_t *base)
+{
+  // CHECK-LABEL: test_svld1_f16
+  // CHECK: <vscale x 8 x half> @llvm.masked.load.nxv8f16.p0nxv8f16(<vscale x 8 x half>* %{{.*}}, i32 1, <vscale x 8 x i1> %{{.*}}, <vscale x 8 x half> zeroinitializer)
+  return svld1_f16(pg, base);
+}
+
+svfloat32_t test_svld1_f32(svbool_t pg, const float32_t *base)
+{
+  // CHECK-LABEL: test_svld1_f32
+  // CHECK: <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %{{.*}}, i32 1, <vscale x 4 x i1> %{{.*}}, <vscale x 4 x float> zeroinitializer)
+  return svld1_f32(pg, base);
+}
+
+svfloat64_t test_svld1_f64(svbool_t pg, const float64_t *base)
+{
+  // CHECK-LABEL: test_svld1_f64
+  // CHECK: <vscale x 2 x double> @llvm.masked.load.nxv2f64.p0nxv2f64(<vscale x 2 x double>* %{{.*}}, i32 1, <vscale x 2 x i1> %{{.*}}, <vscale x 2 x double> zeroinitializer)
+  return svld1_f64(pg, base);
+}
diff --git a/clang/test/CodeGen/arm-mve-intrinsics/ternary.c b/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
index ab1cb14c3aed8..90e258715d261 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
@@ -124,6 +124,321 @@ float32x4_t test_vfmsq_f32(float32x4_t a, float32x4_t b, float32x4_t c) {
 #endif /* POLYMORPHIC */
 }
 
+// CHECK-LABEL: @test_vmlaq_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> undef, i8 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> undef, <16 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <16 x i8> [[B:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[TMP0]], [[A:%.*]]
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+int8x16_t test_vmlaq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
+#ifdef POLYMORPHIC
+  return vmlaq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlaq_n_s8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> undef, i16 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> undef, <8 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <8 x i16> [[B:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i16> [[TMP0]], [[A:%.*]]
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+int16x8_t test_vmlaq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
+#ifdef POLYMORPHIC
+  return vmlaq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlaq_n_s16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <4 x i32> [[B:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[TMP0]], [[A:%.*]]
+// CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+//
+int32x4_t test_vmlaq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
+#ifdef POLYMORPHIC
+  return vmlaq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlaq_n_s32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_n_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> undef, i8 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> undef, <16 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <16 x i8> [[B:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[TMP0]], [[A:%.*]]
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+uint8x16_t test_vmlaq_n_u8(uint8x16_t a, uint8x16_t b, uint8_t c) {
+#ifdef POLYMORPHIC
+  return vmlaq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlaq_n_u8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_n_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> undef, i16 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> undef, <8 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <8 x i16> [[B:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i16> [[TMP0]], [[A:%.*]]
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+uint16x8_t test_vmlaq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c) {
+#ifdef POLYMORPHIC
+  return vmlaq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlaq_n_u16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_n_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <4 x i32> [[B:%.*]], [[DOTSPLAT]]
+// CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[TMP0]], [[A:%.*]]
+// CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+//
+uint32x4_t test_vmlaq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) {
+#ifdef POLYMORPHIC
+  return vmlaq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlaq_n_u32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <16 x i8> [[A:%.*]], [[B:%.*]]
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> undef, i8 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> undef, <16 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[TMP0]], [[DOTSPLAT]]
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+int8x16_t test_vmlasq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
+#ifdef POLYMORPHIC
+  return vmlasq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlasq_n_s8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <8 x i16> [[A:%.*]], [[B:%.*]]
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> undef, i16 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> undef, <8 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i16> [[TMP0]], [[DOTSPLAT]]
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+int16x8_t test_vmlasq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
+#ifdef POLYMORPHIC
+  return vmlasq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlasq_n_s16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[TMP0]], [[DOTSPLAT]]
+// CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+//
+int32x4_t test_vmlasq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
+#ifdef POLYMORPHIC
+  return vmlasq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlasq_n_s32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_n_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <16 x i8> [[A:%.*]], [[B:%.*]]
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> undef, i8 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> undef, <16 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[TMP0]], [[DOTSPLAT]]
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+uint8x16_t test_vmlasq_n_u8(uint8x16_t a, uint8x16_t b, uint8_t c) {
+#ifdef POLYMORPHIC
+  return vmlasq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlasq_n_u8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_n_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <8 x i16> [[A:%.*]], [[B:%.*]]
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> undef, i16 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> undef, <8 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i16> [[TMP0]], [[DOTSPLAT]]
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+uint16x8_t test_vmlasq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c) {
+#ifdef POLYMORPHIC
+  return vmlasq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlasq_n_u16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_n_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
+// CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[C:%.*]], i32 0
+// CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
+// CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[TMP0]], [[DOTSPLAT]]
+// CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+//
+uint32x4_t test_vmlasq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) {
+#ifdef POLYMORPHIC
+  return vmlasq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vmlasq_n_u32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlahq_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+int8x16_t test_vqdmlahq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
+#ifdef POLYMORPHIC
+  return vqdmlahq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqdmlahq_n_s8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlahq_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+int16x8_t test_vqdmlahq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
+#ifdef POLYMORPHIC
+  return vqdmlahq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqdmlahq_n_s16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlahq_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqdmlahq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
+#ifdef POLYMORPHIC
+  return vqdmlahq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqdmlahq_n_s32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlahq_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+int8x16_t test_vqrdmlahq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
+#ifdef POLYMORPHIC
+  return vqrdmlahq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqrdmlahq_n_s8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlahq_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+int16x8_t test_vqrdmlahq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
+#ifdef POLYMORPHIC
+  return vqrdmlahq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqrdmlahq_n_s16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlahq_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqrdmlahq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
+#ifdef POLYMORPHIC
+  return vqrdmlahq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqrdmlahq_n_s32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlashq_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 [[TMP0]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+//
+int8x16_t test_vqrdmlashq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
+#ifdef POLYMORPHIC
+  return vqrdmlashq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqrdmlashq_n_s8(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlashq_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 [[TMP0]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+//
+int16x8_t test_vqrdmlashq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
+#ifdef POLYMORPHIC
+  return vqrdmlashq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqrdmlashq_n_s16(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlashq_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[C:%.*]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqrdmlashq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
+#ifdef POLYMORPHIC
+  return vqrdmlashq(a, b, c);
+#else  /* POLYMORPHIC */
+  return vqrdmlashq_n_s32(a, b, c);
+#endif /* POLYMORPHIC */
+}
+
 // CHECK-LABEL: @test_vfmaq_m_f16(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
@@ -259,3 +574,333 @@ float32x4_t test_vfmsq_m_f32(float32x4_t a, float32x4_t b, float32x4_t c, mve_pr
   return vfmsq_m_f32(a, b, c, p);
 #endif /* POLYMORPHIC */
 }
+
+// CHECK-LABEL: @test_vmlaq_m_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+int8x16_t test_vmlaq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlaq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlaq_m_n_s8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_m_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+int16x8_t test_vmlaq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlaq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlaq_m_n_s16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_m_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vmlaq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlaq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlaq_m_n_s32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_m_n_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+uint8x16_t test_vmlaq_m_n_u8(uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlaq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlaq_m_n_u8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_m_n_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+uint16x8_t test_vmlaq_m_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlaq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlaq_m_n_u16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlaq_m_n_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+uint32x4_t test_vmlaq_m_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlaq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlaq_m_n_u32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_m_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+int8x16_t test_vmlasq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlasq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlasq_m_n_s8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_m_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+int16x8_t test_vmlasq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlasq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlasq_m_n_s16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_m_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vmlasq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlasq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlasq_m_n_s32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_m_n_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+uint8x16_t test_vmlasq_m_n_u8(uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlasq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlasq_m_n_u8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_m_n_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+uint16x8_t test_vmlasq_m_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlasq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlasq_m_n_u16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmlasq_m_n_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+uint32x4_t test_vmlasq_m_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vmlasq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vmlasq_m_n_u32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlahq_m_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+int8x16_t test_vqdmlahq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlahq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqdmlahq_m_n_s8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlahq_m_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+int16x8_t test_vqdmlahq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlahq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqdmlahq_m_n_s16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlahq_m_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqdmlahq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlahq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqdmlahq_m_n_s32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlahq_m_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+int8x16_t test_vqrdmlahq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlahq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlahq_m_n_s8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlahq_m_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+int16x8_t test_vqrdmlahq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlahq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlahq_m_n_s16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlahq_m_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqrdmlahq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlahq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlahq_m_n_s32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlashq_m_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+//
+int8x16_t test_vqrdmlashq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlashq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlashq_m_n_s8(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlashq_m_n_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
+// CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+//
+int16x8_t test_vqrdmlashq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlashq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlashq_m_n_s16(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlashq_m_n_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqrdmlashq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlashq_m(a, b, c, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlashq_m_n_s32(a, b, c, p);
+#endif /* POLYMORPHIC */
+}
+
diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c b/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
new file mode 100644
index 0000000000000..cd59e6ccdfb75
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
@@ -0,0 +1,677 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include <arm_mve.h>
+
+// CHECK-LABEL: @test_vqdmladhq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqdmladhq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqdmladhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmladhq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 0)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqdmladhq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqdmladhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmladhq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 0)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqdmladhq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqdmladhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmladhq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhxq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqdmladhxq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqdmladhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmladhxq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhxq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqdmladhxq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqdmladhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmladhxq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhxq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqdmladhxq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqdmladhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmladhxq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqdmlsdhq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 1)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqdmlsdhq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 1)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqdmlsdhq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhxq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqdmlsdhxq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhxq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhxq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 1)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqdmlsdhxq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhxq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhxq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 1)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqdmlsdhxq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhxq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqrdmladhq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmladhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmladhq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 0)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqrdmladhq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmladhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmladhq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 0)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqrdmladhq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmladhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmladhq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhxq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 0)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqrdmladhxq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmladhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmladhxq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhxq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 0)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqrdmladhxq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmladhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmladhxq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhxq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 0)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqrdmladhxq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmladhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmladhxq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqrdmlsdhq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 1)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqrdmlsdhq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 1)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqrdmlsdhq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhxq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 1)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vqrdmlsdhxq_s8(int8x16_t inactive, int8x16_t a, int8x16_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhxq_s8(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhxq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 1)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vqrdmlsdhxq_s16(int16x8_t inactive, int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhxq_s16(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhxq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 1)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqrdmlsdhxq_s32(int32x4_t inactive, int32x4_t a, int32x4_t b) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhxq(inactive, a, b);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhxq_s32(inactive, a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 0, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqdmladhq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmladhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmladhq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 0, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqdmladhq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmladhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmladhq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 0, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqdmladhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmladhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmladhq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhxq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 0, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqdmladhxq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmladhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmladhxq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhxq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 0, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqdmladhxq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmladhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmladhxq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmladhxq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 0, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqdmladhxq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmladhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmladhxq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 1, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqdmlsdhq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 1, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqdmlsdhq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 1, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqdmlsdhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhxq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 1, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqdmlsdhxq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhxq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhxq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 1, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqdmlsdhxq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhxq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmlsdhxq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 1, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqdmlsdhxq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqdmlsdhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqdmlsdhxq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 0, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqrdmladhq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmladhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmladhq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 0, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqrdmladhq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmladhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmladhq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 0, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqrdmladhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmladhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmladhq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhxq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 0, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqrdmladhxq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmladhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmladhxq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhxq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 0, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqrdmladhxq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmladhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmladhxq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmladhxq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 0, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqrdmladhxq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmladhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmladhxq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 1, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqrdmlsdhq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 1, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqrdmlsdhq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 1, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqrdmlsdhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhxq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 1, <16 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vqrdmlsdhxq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhxq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhxq_m_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 1, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+//
+int16x8_t test_vqrdmlsdhxq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhxq_m_s16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqrdmlsdhxq_m_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 1, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+//
+int32x4_t test_vqrdmlsdhxq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vqrdmlsdhxq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vqrdmlsdhxq_m_s32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
diff --git a/clang/test/CodeGen/attr-loader-uninitialized.c b/clang/test/CodeGen/attr-loader-uninitialized.c
new file mode 100644
index 0000000000000..9ff0c23d77c34
--- /dev/null
+++ b/clang/test/CodeGen/attr-loader-uninitialized.c
@@ -0,0 +1,25 @@
+// UNSUPPORTED: system-windows
+// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: @tentative_attr_first = global i32 undef
+int tentative_attr_first __attribute__((loader_uninitialized));
+int tentative_attr_first;
+
+// CHECK: @tentative_attr_second = global i32 undef
+int tentative_attr_second;
+int tentative_attr_second __attribute__((loader_uninitialized));
+
+// CHECK: @array = global [16 x float] undef
+float array[16] __attribute__((loader_uninitialized));
+
+typedef struct
+{
+  int x;
+  float y;
+} s;
+
+// CHECK: @i = global %struct.s undef
+s i __attribute__((loader_uninitialized));
+
+// CHECK: @private_extern_ok = hidden global i32 undef
+__private_extern__ int private_extern_ok __attribute__((loader_uninitialized));
diff --git a/clang/test/CodeGen/inline-asm-p-constraint.c b/clang/test/CodeGen/inline-asm-p-constraint.c
new file mode 100644
index 0000000000000..70db78bc6492c
--- /dev/null
+++ b/clang/test/CodeGen/inline-asm-p-constraint.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -emit-llvm %s -o - -triple aarch64-linux-gnu | FileCheck %s
+void foo(void* ptr) {
+  asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
+  // CHECK:     call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "r"(i8* %0)
+  // CHECK-NOT: call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "p"(i8* %0)
+}
diff --git a/clang/test/CodeGen/mdouble.c b/clang/test/CodeGen/mdouble.c
new file mode 100644
index 0000000000000..8399919f70257
--- /dev/null
+++ b/clang/test/CodeGen/mdouble.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=avr-unknown-unknown -mdouble=64 | \
+// RUN:   FileCheck --check-prefix=AVR-FP64 %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=avr-unknown-unknown -mdouble=32 | \
+// RUN:   FileCheck --check-prefix=AVR-FP32 %s
+
+double x = 0;
+int size = sizeof(x);
+
+// FIXME: the double should have an alignment of 1 on AVR, not 4 or 8.
+// AVR-FP64: @x = global double {{.*}}, align 8
+// AVR-FP64: @size = global i16 8
+// AVR-FP32: @x = global float {{.*}}, align 4
+// AVR-FP32: @size = global i16 4
diff --git a/clang/test/CodeGenCUDA/hip-pinned-shadow.cu b/clang/test/CodeGenCUDA/hip-pinned-shadow.hip
similarity index 81%
rename from clang/test/CodeGenCUDA/hip-pinned-shadow.cu
rename to clang/test/CodeGenCUDA/hip-pinned-shadow.hip
index 1d22ed6dc94ca..7f0e7544d8284 100644
--- a/clang/test/CodeGenCUDA/hip-pinned-shadow.cu
+++ b/clang/test/CodeGenCUDA/hip-pinned-shadow.hip
@@ -1,11 +1,11 @@
 // REQUIRES: amdgpu-registered-target
 
 // RUN: %clang_cc1 -triple amdgcn -fcuda-is-device -std=c++11 -fvisibility hidden -fapply-global-visibility-to-externs \
-// RUN:     -emit-llvm -o - -x hip %s | FileCheck -check-prefixes=HIPDEV %s
+// RUN:     -emit-llvm -o - %s | FileCheck -check-prefixes=HIPDEV %s
 // RUN: %clang_cc1 -triple x86_64 -std=c++11 \
-// RUN:     -emit-llvm -o - -x hip %s | FileCheck -check-prefixes=HIPHOST %s
+// RUN:     -emit-llvm -o - %s | FileCheck -check-prefixes=HIPHOST %s
 // RUN: %clang_cc1 -triple amdgcn -fcuda-is-device -std=c++11 -fvisibility hidden -fapply-global-visibility-to-externs \
-// RUN:     -O3 -emit-llvm -o - -x hip %s | FileCheck -check-prefixes=HIPDEVUNSED %s
+// RUN:     -O3 -emit-llvm -o - %s | FileCheck -check-prefixes=HIPDEVUNSED %s
 
 struct textureReference {
   int a;
diff --git a/clang/test/CodeGenCXX/attr-loader-uninitialized.cpp b/clang/test/CodeGenCXX/attr-loader-uninitialized.cpp
new file mode 100644
index 0000000000000..e82ae47e9f16e
--- /dev/null
+++ b/clang/test/CodeGenCXX/attr-loader-uninitialized.cpp
@@ -0,0 +1,30 @@
+// UNSUPPORTED: system-windows
+// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s
+
+// CHECK: @defn = global i32 undef
+int defn  [[clang::loader_uninitialized]];
+
+// CHECK: @_ZL11defn_static = internal global i32 undef
+static int defn_static [[clang::loader_uninitialized]] __attribute__((used));
+
+// CHECK: @_ZZ4funcvE4data = internal global i32 undef
+int* func(void)
+{
+  static int data [[clang::loader_uninitialized]];
+  return &data;
+}
+
+class trivial
+{
+  float x;
+};
+
+// CHECK: @ut = global %class.trivial undef
+trivial ut [[clang::loader_uninitialized]];
+
+// CHECK: @arr = global [32 x double] undef
+double arr[32] __attribute__((loader_uninitialized));
+
+// Defining as arr2[] [[clang..]] raises the error: attribute cannot be applied to types
+// CHECK: @arr2 = global [4 x double] undef
+double arr2 [[clang::loader_uninitialized]] [4];
diff --git a/clang/test/CodeGenCoroutines/coro-return-voidtype-initlist.cpp b/clang/test/CodeGenCoroutines/coro-return-voidtype-initlist.cpp
new file mode 100644
index 0000000000000..8526b6f8a8dad
--- /dev/null
+++ b/clang/test/CodeGenCoroutines/coro-return-voidtype-initlist.cpp
@@ -0,0 +1,81 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcoroutines-ts -std=c++1z -emit-llvm %s -o - -disable-llvm-passes | FileCheck %s
+
+namespace std {
+template <typename a>
+struct b { b(int, a); };
+template <typename, typename = int>
+struct c {};
+namespace experimental {
+template <typename d>
+struct coroutine_traits : d {};
+template <typename = void>
+struct coroutine_handle;
+template <>
+struct coroutine_handle<> {};
+template <typename>
+struct coroutine_handle : coroutine_handle<> {
+  static coroutine_handle from_address(void *);
+};
+struct e {
+  int await_ready();
+  void await_suspend(coroutine_handle<>);
+  void await_resume();
+};
+} // namespace experimental
+} // namespace std
+template <typename ag>
+auto ah(ag) { return ag().ah(0); }
+template <typename>
+struct f;
+struct g {
+  struct h {
+    int await_ready();
+    template <typename al>
+    void await_suspend(std::experimental::coroutine_handle<al>);
+    void await_resume();
+  };
+  std::experimental::e initial_suspend();
+  h final_suspend();
+  template <typename ag>
+  auto await_transform(ag) { return ah(ag()); }
+};
+struct j : g {
+  f<std::b<std::c<int, int>>> get_return_object();
+  void return_value(std::b<std::c<int, int>>);
+  void unhandled_exception();
+};
+struct k {
+  k(std::experimental::coroutine_handle<>);
+  int await_ready();
+};
+template <typename am>
+struct f {
+  using promise_type = j;
+  std::experimental::coroutine_handle<> ar;
+  struct l : k {
+    using at = k;
+    l(std::experimental::coroutine_handle<> m) : at(m) {}
+    void await_suspend(std::experimental::coroutine_handle<>);
+  };
+  struct n : l {
+    n(std::experimental::coroutine_handle<> m) : l(m) {}
+    am await_resume();
+  };
+  auto ah(int) { return n(ar); }
+};
+template <typename am, typename av, typename aw>
+auto ax(std::c<am, av>, aw) -> f<std::c<int, aw>>;
+template <typename>
+struct J { static f<std::b<std::c<int, int>>> bo(); };
+// CHECK-LABEL: _ZN1JIiE2boEv(
+template <typename bc>
+f<std::b<std::c<int, int>>> J<bc>::bo() {
+  std::c<int> bu;
+  int bw(0);
+  // CHECK: void @_ZN1j12return_valueESt1bISt1cIiiEE(%struct.j* %__promise)
+  co_return{0, co_await ax(bu, bw)};
+}
+void bh() {
+  auto cn = [] { J<int>::bo; };
+  cn();
+}
diff --git a/clang/test/Driver/clang_f_opts.c b/clang/test/Driver/clang_f_opts.c
index bda026715c369..180d4713dcb4f 100644
--- a/clang/test/Driver/clang_f_opts.c
+++ b/clang/test/Driver/clang_f_opts.c
@@ -304,7 +304,6 @@
 // RUN:     -fno-inline-small-functions -finline-small-functions              \
 // RUN:     -fno-fat-lto-objects -ffat-lto-objects                            \
 // RUN:     -fno-merge-constants -fmerge-constants                            \
-// RUN:     -fno-merge-all-constants -fmerge-all-constants                    \
 // RUN:     -fno-caller-saves -fcaller-saves                                  \
 // RUN:     -fno-reorder-blocks -freorder-blocks                              \
 // RUN:     -fno-schedule-insns2 -fschedule-insns2                            \
@@ -544,13 +543,6 @@
 // CHECK-DISCARD-NAMES: "-discard-value-names"
 // CHECK-NO-DISCARD-NAMES-NOT: "-discard-value-names"
 
-// RUN: %clang -### -S -fmerge-all-constants %s 2>&1 | FileCheck -check-prefix=CHECK-MERGE-ALL-CONSTANTS %s
-// RUN: %clang -### -S -fno-merge-all-constants %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MERGE-ALL-CONSTANTS %s
-// RUN: %clang -### -S -fmerge-all-constants -fno-merge-all-constants %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MERGE-ALL-CONSTANTS %s
-// RUN: %clang -### -S -fno-merge-all-constants -fmerge-all-constants %s 2>&1 | FileCheck -check-prefix=CHECK-MERGE-ALL-CONSTANTS %s
-// CHECK-NO-MERGE-ALL-CONSTANTS-NOT: "-fmerge-all-constants"
-// CHECK-MERGE-ALL-CONSTANTS: "-fmerge-all-constants"
-
 // RUN: %clang -### -S -fdelete-null-pointer-checks %s 2>&1 | FileCheck -check-prefix=CHECK-NULL-POINTER-CHECKS %s
 // RUN: %clang -### -S -fno-delete-null-pointer-checks %s 2>&1 | FileCheck -check-prefix=CHECK-NO-NULL-POINTER-CHECKS %s
 // RUN: %clang -### -S -fdelete-null-pointer-checks -fno-delete-null-pointer-checks %s 2>&1 | FileCheck -check-prefix=CHECK-NO-NULL-POINTER-CHECKS %s
diff --git a/clang/test/Driver/fmerge-constants.c b/clang/test/Driver/fmerge-constants.c
new file mode 100644
index 0000000000000..c478a9d7b1e5f
--- /dev/null
+++ b/clang/test/Driver/fmerge-constants.c
@@ -0,0 +1,6 @@
+// RUN: %clang -### -c %s -fno-merge-all-constants -fmerge-all-constants 2>&1 | FileCheck %s
+// CHECK: "-fmerge-all-constants"
+
+// RUN: %clang -### -c %s 2>&1 | FileCheck --check-prefix=NO %s
+// RUN: %clang -### -c %s -fmerge-all-constants -fno-merge-all-constants 2>&1 | FileCheck --check-prefix=NO %s
+// NO-NOT: "-fmerge-all-constants"
diff --git a/clang/test/Driver/hip-autolink.hip b/clang/test/Driver/hip-autolink.hip
index 9c1b65f1592bf..c06f0f9d8b715 100644
--- a/clang/test/Driver/hip-autolink.hip
+++ b/clang/test/Driver/hip-autolink.hip
@@ -3,9 +3,9 @@
 // REQUIRES: amdgpu-registered-target
 //
 // RUN: %clang --target=i386-pc-windows-msvc --cuda-gpu-arch=gfx906 -nogpulib \
-// RUN:   --cuda-device-only -x hip %s -### 2>&1 | FileCheck --check-prefix=DEV %s
+// RUN:   --cuda-device-only %s -### 2>&1 | FileCheck --check-prefix=DEV %s
 // RUN: %clang --target=i386-pc-windows-msvc --cuda-gpu-arch=gfx906 -nogpulib \
-// RUN:   --cuda-host-only -x hip %s -### 2>&1 | FileCheck --check-prefix=HOST %s
+// RUN:   --cuda-host-only %s -### 2>&1 | FileCheck --check-prefix=HOST %s
 
 // DEV: "-cc1" "-triple" "amdgcn-amd-amdhsa"
 // DEV-SAME: "-fno-autolink"
diff --git a/clang/test/Driver/hip-default-gpu-arch.hip b/clang/test/Driver/hip-default-gpu-arch.hip
index 56e36882dc637..bce9a67b4b1c9 100644
--- a/clang/test/Driver/hip-default-gpu-arch.hip
+++ b/clang/test/Driver/hip-default-gpu-arch.hip
@@ -2,6 +2,6 @@
 // REQUIRES: x86-registered-target
 // REQUIRES: amdgpu-registered-target
 
-// RUN: %clang -### -x hip -c %s 2>&1 | FileCheck %s
+// RUN: %clang -### -c %s 2>&1 | FileCheck %s
 
 // CHECK: {{.*}}clang{{.*}}"-target-cpu" "gfx803"
diff --git a/clang/test/Driver/hip-device-libs.hip b/clang/test/Driver/hip-device-libs.hip
index 97e76525dde81..b79cb70cbe683 100644
--- a/clang/test/Driver/hip-device-libs.hip
+++ b/clang/test/Driver/hip-device-libs.hip
@@ -5,7 +5,7 @@
 // Test flush-denormals-to-zero enabled uses oclc_daz_opt_on
 
 // RUN: %clang -### -target x86_64-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   --hip-device-lib-path=%S/Inputs/hip_dev_lib \
 // RUN:   -fcuda-flush-denormals-to-zero \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
@@ -14,7 +14,7 @@
 // Test flush-denormals-to-zero disabled uses oclc_daz_opt_off
 
 // RUN: %clang -### -target x86_64-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   --hip-device-lib-path=%S/Inputs/hip_dev_lib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck %s --check-prefixes=COM,NOFLUSHD
@@ -23,7 +23,7 @@
 
 // RUN: env HIP_DEVICE_LIB_PATH=%S/Inputs/hip_dev_lib \
 // RUN:   %clang -### -target x86_64-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck %s --check-prefixes=COM
 
diff --git a/clang/test/Driver/hip-host-cpu-features.hip b/clang/test/Driver/hip-host-cpu-features.hip
index efadd8bed22cf..67a5004556916 100644
--- a/clang/test/Driver/hip-host-cpu-features.hip
+++ b/clang/test/Driver/hip-host-cpu-features.hip
@@ -2,9 +2,9 @@
 // REQUIRES: x86-registered-target
 // REQUIRES: amdgpu-registered-target
 
-// RUN: %clang -### -c -target x86_64-linux-gnu -march=znver2 -x hip --cuda-gpu-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s -check-prefix=HOSTCPU
-// RUN: %clang -### -c -target x86_64-linux-gnu -msse3 -x hip --cuda-gpu-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s -check-prefix=HOSTSSE3
-// RUN: %clang -### -c -target x86_64-linux-gnu --gpu-use-aux-triple-only -march=znver2 -x hip --cuda-gpu-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s -check-prefix=NOHOSTCPU
+// RUN: %clang -### -c -target x86_64-linux-gnu -march=znver2 --cuda-gpu-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s -check-prefix=HOSTCPU
+// RUN: %clang -### -c -target x86_64-linux-gnu -msse3 --cuda-gpu-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s -check-prefix=HOSTSSE3
+// RUN: %clang -### -c -target x86_64-linux-gnu --gpu-use-aux-triple-only -march=znver2 --cuda-gpu-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s -check-prefix=NOHOSTCPU
 
 // HOSTCPU: "-cc1" "-triple" "amdgcn-amd-amdhsa"
 // HOSTCPU-SAME: "-aux-triple" "x86_64-unknown-linux-gnu"
diff --git a/clang/test/Driver/hip-no-device-libs.hip b/clang/test/Driver/hip-no-device-libs.hip
index 9fc73699d515c..d19382698bb13 100644
--- a/clang/test/Driver/hip-no-device-libs.hip
+++ b/clang/test/Driver/hip-no-device-libs.hip
@@ -3,7 +3,7 @@
 // REQUIRES: amdgpu-registered-target
 
 // RUN: %clang -### -nogpulib -target x86_64-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck %s
 
diff --git a/clang/test/Driver/hip-options.hip b/clang/test/Driver/hip-options.hip
index b2ad0424b3061..59afa3fdb2d7b 100644
--- a/clang/test/Driver/hip-options.hip
+++ b/clang/test/Driver/hip-options.hip
@@ -8,3 +8,8 @@
 //
 // CHECK: clang{{.*}}" "-cc1" {{.*}} "-fcuda-is-device"
 // CHECK-SAME: "--gpu-max-threads-per-block=1024"
+
+// RUN: %clang -### -x hip -target x86_64-pc-windows-msvc -fms-extensions \
+// RUN:   -mllvm -amdgpu-early-inline-all=true  %s 2>&1 | \
+// RUN:   FileCheck -check-prefix=MLLVM %s
+// MLLVM-NOT: "-mllvm"{{.*}}"-amdgpu-early-inline-all=true"{{.*}}"-mllvm"{{.*}}"-amdgpu-early-inline-all=true"
diff --git a/clang/test/Driver/hip-output-file-name.hip b/clang/test/Driver/hip-output-file-name.hip
index cce9f76406eec..d57f7e87f89e1 100644
--- a/clang/test/Driver/hip-output-file-name.hip
+++ b/clang/test/Driver/hip-output-file-name.hip
@@ -3,7 +3,7 @@
 // REQUIRES: amdgpu-registered-target
 
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN: 2>&1 | FileCheck %s
 
 // CHECK: {{.*}}clang-offload-bundler{{.*}}"-outputs=hip-output-file-name.o"
diff --git a/clang/test/Driver/hip-printf.hip b/clang/test/Driver/hip-printf.hip
index ada6c651ddb7e..065398a214f1d 100644
--- a/clang/test/Driver/hip-printf.hip
+++ b/clang/test/Driver/hip-printf.hip
@@ -2,7 +2,7 @@
 // REQUIRES: x86-registered-target
 // REQUIRES: amdgpu-registered-target
 
-// RUN: %clang -### -target x86_64-linux-gnu -x hip --cuda-gpu-arch=gfx900 \
+// RUN: %clang -### -target x86_64-linux-gnu --cuda-gpu-arch=gfx900 \
 // RUN:   %s 2>&1 | FileCheck %s
 
 // CHECK: [[CLANG:".*clang.*"]] "-cc1"
diff --git a/clang/test/Driver/hip-save-temps.hip b/clang/test/Driver/hip-save-temps.hip
index f7f2c6ef57ff5..e9a8bd1f2099e 100644
--- a/clang/test/Driver/hip-save-temps.hip
+++ b/clang/test/Driver/hip-save-temps.hip
@@ -4,22 +4,22 @@
 
 // -fno-gpu-rdc without -o
 // RUN: %clang -### -target x86_64-linux-gnu -nogpulib -save-temps \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 %s 2>&1 | \
+// RUN:   --cuda-gpu-arch=gfx900 %s 2>&1 | \
 // RUN:   FileCheck -check-prefixes=CHECK,NORDC,NOUT %s
 
 // -fno-gpu-rdc with -o
 // RUN: %clang -### -target x86_64-linux-gnu -nogpulib -save-temps \
-// RUN:   -o executable -x hip --cuda-gpu-arch=gfx900 %s 2>&1 | \
+// RUN:   -o executable --cuda-gpu-arch=gfx900 %s 2>&1 | \
 // RUN:   FileCheck -check-prefixes=CHECK,NORDC,WOUT %s
 
 // -fgpu-rdc without -o
 // RUN: %clang -### -target x86_64-linux-gnu -nogpulib -save-temps \
-// RUN:   -fgpu-rdc -x hip --cuda-gpu-arch=gfx900 %s 2>&1 | \
+// RUN:   -fgpu-rdc --cuda-gpu-arch=gfx900 %s 2>&1 | \
 // RUN:   FileCheck -check-prefixes=CHECK,RDC,RDC-NOUT,NOUT %s
 
 // -fgpu-rdc with -o
 // RUN: %clang -### -target x86_64-linux-gnu -nogpulib -save-temps \
-// RUN:   -o executable -fgpu-rdc -x hip --cuda-gpu-arch=gfx900 %s 2>&1 | \
+// RUN:   -o executable -fgpu-rdc --cuda-gpu-arch=gfx900 %s 2>&1 | \
 // RUN:   FileCheck -check-prefixes=CHECK,RDC,RDC-WOUT,WOUT %s
 
 // CHECK: {{.*}}clang{{.*}}"-o" "hip-save-temps-hip-amdgcn-amd-amdhsa-gfx900.cui"
diff --git a/clang/test/Driver/hip-syntax-only.hip b/clang/test/Driver/hip-syntax-only.hip
index 051c3c68962e2..e52acb0344ef9 100644
--- a/clang/test/Driver/hip-syntax-only.hip
+++ b/clang/test/Driver/hip-syntax-only.hip
@@ -2,7 +2,7 @@
 // REQUIRES: x86-registered-target
 // REQUIRES: amdgpu-registered-target
 
-// RUN: %clang -### -x hip -nogpulib -target x86_64 -fsyntax-only %s 2>&1 | FileCheck %s
+// RUN: %clang -### -nogpulib -target x86_64 -fsyntax-only %s 2>&1 | FileCheck %s
 
 // Check that there are commands for both host- and device-side compilations.
 //
diff --git a/clang/test/Driver/hip-toolchain-features.hip b/clang/test/Driver/hip-toolchain-features.hip
index 0fe94015ef1ec..3b90d4101ee3d 100644
--- a/clang/test/Driver/hip-toolchain-features.hip
+++ b/clang/test/Driver/hip-toolchain-features.hip
@@ -3,10 +3,10 @@
 // REQUIRES: amdgpu-registered-target
 
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN:   -mxnack 2>&1 | FileCheck %s -check-prefix=XNACK
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN:   -mno-xnack 2>&1 | FileCheck %s -check-prefix=NOXNACK
 
 // XNACK: {{.*}}clang{{.*}}"-target-feature" "+xnack"
@@ -14,10 +14,10 @@
 
 
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN:   -msram-ecc 2>&1 | FileCheck %s -check-prefix=SRAM
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN:   -mno-sram-ecc 2>&1 | FileCheck %s -check-prefix=NOSRAM
 
 // SRAM: {{.*}}clang{{.*}}"-target-feature" "+sram-ecc"
@@ -25,11 +25,11 @@
 
 
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN:   -mxnack -msram-ecc \
 // RUN:   2>&1 | FileCheck %s -check-prefix=ALL3
 // RUN: %clang -### -c -target x86_64-linux-gnu -fgpu-rdc \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 %s \
 // RUN:   -mno-xnack -mno-sram-ecc \
 // RUN:   2>&1 | FileCheck %s -check-prefix=NOALL3
 
diff --git a/clang/test/Driver/hip-toolchain-mllvm.hip b/clang/test/Driver/hip-toolchain-mllvm.hip
index ab665055f482c..692a9a7d5c703 100644
--- a/clang/test/Driver/hip-toolchain-mllvm.hip
+++ b/clang/test/Driver/hip-toolchain-mllvm.hip
@@ -3,7 +3,7 @@
 // REQUIRES: amdgpu-registered-target
 
 // RUN: %clang -### -target x86_64-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx803 --cuda-gpu-arch=gfx900 \
 // RUN:   -mllvm -amdgpu-function-calls=0 \
 // RUN:   %s 2>&1 | FileCheck %s
 
diff --git a/clang/test/Driver/hip-toolchain-opt.hip b/clang/test/Driver/hip-toolchain-opt.hip
index ae64ae7d0d0fb..c6d6bf561cde1 100644
--- a/clang/test/Driver/hip-toolchain-opt.hip
+++ b/clang/test/Driver/hip-toolchain-opt.hip
@@ -4,56 +4,56 @@
 
 // RUN: %clang -### \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,DEFAULT %s
 
 // RUN: %clang -### -O0 \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,O0 %s
 
 // RUN: %clang -### -O1 \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,O1 %s
 
 // RUN: %clang -### -O2 \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,O2 %s
 
 // RUN: %clang -### -O3 \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,O3 %s
 
 // RUN: %clang -### -Os \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,Os %s
 
 // RUN: %clang -### -Oz \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,Oz %s
 
 // RUN: %clang -### -Og \
 // RUN:   -target x86_64-unknown-linux-gnu \
-// RUN:   -x hip --cuda-gpu-arch=gfx900 \
+// RUN:   --cuda-gpu-arch=gfx900 \
 // RUN:   -c -nogpulib \
 // RUN:   %S/Inputs/hip_multiple_inputs/b.hip \
 // RUN: 2>&1 | FileCheck --check-prefixes=ALL,Og %s
diff --git a/clang/test/Driver/mdouble.c b/clang/test/Driver/mdouble.c
new file mode 100644
index 0000000000000..408d907053163
--- /dev/null
+++ b/clang/test/Driver/mdouble.c
@@ -0,0 +1,7 @@
+// RUN: %clang -target avr -c -### %s -mdouble=64 2>&1 | FileCheck %s
+
+// CHECK: "-mdouble=64"
+
+// RUN: %clang -target aarch64 -c -### %s -mdouble=64 2>&1 | FileCheck --check-prefix=ERR %s
+
+// ERR: error: unsupported option '-mdouble=64' for target 'aarch64'
diff --git a/clang/test/Driver/memtag.c b/clang/test/Driver/memtag.c
new file mode 100644
index 0000000000000..bfe453beef562
--- /dev/null
+++ b/clang/test/Driver/memtag.c
@@ -0,0 +1,23 @@
+// REQUIRES: aarch64-registered-target
+
+// Old pass manager.
+// RUN: %clang     -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-NO-SAFETY
+// RUN: %clang -O1 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-SAFETY
+// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-SAFETY
+// RUN: %clang -O3 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-SAFETY
+
+// New pass manager.
+// RUN: %clang     -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-NO-SAFETY
+// RUN: %clang -O1 -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-SAFETY
+// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-SAFETY
+// RUN: %clang -O3 -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-SAFETY
+
+int z;
+__attribute__((noinline)) void use(int *p) { *p = z; }
+int foo() { int x; use(&x); return x; }
+
+// CHECK-NO-SAFETY: define dso_local i32 @foo()
+// CHECK-NO-SAFETY: %{{.*}} = alloca i32, align 4{{$}}
+
+// CHECK-SAFETY: define dso_local i32 @foo()
+// CHECK-SAFETY: %{{.*}} = alloca i32, align 4, !stack-safe
diff --git a/clang/test/Driver/ps4-runtime-flags.c b/clang/test/Driver/ps4-runtime-flags.c
index 315976d4e228e..3131690304dbf 100644
--- a/clang/test/Driver/ps4-runtime-flags.c
+++ b/clang/test/Driver/ps4-runtime-flags.c
@@ -10,10 +10,15 @@
 // RUN: %clang -target x86_64-scei-ps4 -fprofile-arcs -fno-profile-arcs %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-NO-PROFILE %s
 // RUN: %clang -target x86_64-scei-ps4 -fprofile-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-PROFILE %s
 // RUN: %clang -target x86_64-scei-ps4 -fno-profile-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-NO-PROFILE %s
+// RUN: %clang -target x86_64-scei-ps4 -fprofile-generate -fno-profile-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-NO-PROFILE %s
 // RUN: %clang -target x86_64-scei-ps4 -fprofile-generate=dir %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-PROFILE %s
 // RUN: %clang -target x86_64-scei-ps4 -fprofile-instr-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-PROFILE %s
 // RUN: %clang -target x86_64-scei-ps4 -fno-profile-instr-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-NO-PROFILE %s
+// RUN: %clang -target x86_64-scei-ps4 -fprofile-instr-generate -fno-profile-instr-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-NO-PROFILE %s
+// RUN: %clang -target x86_64-scei-ps4 -fprofile-generate -fno-profile-instr-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-PROFILE %s
 // RUN: %clang -target x86_64-scei-ps4 -fprofile-instr-generate=somefile.profraw %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-PROFILE %s
+// RUN: %clang -target x86_64-scei-ps4 -fcs-profile-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-PROFILE %s
+// RUN: %clang -target x86_64-scei-ps4 -fcs-profile-generate -fno-profile-generate %s -### 2>&1 | FileCheck --check-prefix=CHECK-PS4-NO-PROFILE %s
 //
 // CHECK-PS4-PROFILE: "--dependent-lib=libclang_rt.profile-x86_64.a"
 // CHECK-PS4-NO-PROFILE-NOT: "--dependent-lib=libclang_rt.profile-x86_64.a"
diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
index 2a196f48973b2..d77a06819ae75 100644
--- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test
+++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
@@ -66,6 +66,7 @@
 // CHECK-NEXT: IntelReqdSubGroupSize (SubjectMatchRule_function, SubjectMatchRule_function_is_member)
 // CHECK-NEXT: InternalLinkage (SubjectMatchRule_variable, SubjectMatchRule_function, SubjectMatchRule_record)
 // CHECK-NEXT: LTOVisibilityPublic (SubjectMatchRule_record)
+// CHECK-NEXT: LoaderUninitialized (SubjectMatchRule_variable_is_global)
 // CHECK-NEXT: Lockable (SubjectMatchRule_record)
 // CHECK-NEXT: MIGServerRoutine (SubjectMatchRule_function, SubjectMatchRule_objc_method, SubjectMatchRule_block)
 // CHECK-NEXT: MSStruct (SubjectMatchRule_record)
diff --git a/clang/test/OpenMP/target_ast_print.cpp b/clang/test/OpenMP/target_ast_print.cpp
index a36b44bd406ef..0352ae63ff81b 100644
--- a/clang/test/OpenMP/target_ast_print.cpp
+++ b/clang/test/OpenMP/target_ast_print.cpp
@@ -353,11 +353,11 @@ int a;
 template <typename T, int C>
 T tmain(T argc, T *argv) {
   T i, j, a[20], always, close;
-#pragma omp target
+#pragma omp target device(argc)
   foo();
-#pragma omp target if (target:argc > 0)
+#pragma omp target if (target:argc > 0) device(device_num: C)
   foo();
-#pragma omp target if (C)
+#pragma omp target if (C) device(ancestor: argc)
   foo();
 #pragma omp target map(i)
   foo();
@@ -458,11 +458,11 @@ T tmain(T argc, T *argv) {
 
 // OMP5: template <typename T, int C> T tmain(T argc, T *argv) {
 // OMP5-NEXT: T i, j, a[20]
-// OMP5-NEXT: #pragma omp target{{$}}
+// OMP5-NEXT: #pragma omp target device(argc){{$}}
 // OMP5-NEXT: foo();
-// OMP5-NEXT: #pragma omp target if(target: argc > 0)
+// OMP5-NEXT: #pragma omp target if(target: argc > 0) device(device_num: C)
 // OMP5-NEXT: foo()
-// OMP5-NEXT: #pragma omp target if(C)
+// OMP5-NEXT: #pragma omp target if(C) device(ancestor: argc)
 // OMP5-NEXT: foo()
 // OMP5-NEXT: #pragma omp target map(tofrom: i)
 // OMP5-NEXT: foo()
@@ -650,11 +650,11 @@ T tmain(T argc, T *argv) {
 // OMP5-NEXT: foo()
 // OMP5: template<> char tmain<char, 1>(char argc, char *argv) {
 // OMP5-NEXT: char i, j, a[20]
-// OMP5-NEXT: #pragma omp target
+// OMP5-NEXT: #pragma omp target device(argc)
 // OMP5-NEXT: foo();
-// OMP5-NEXT: #pragma omp target if(target: argc > 0)
+// OMP5-NEXT: #pragma omp target if(target: argc > 0) device(device_num: 1)
 // OMP5-NEXT: foo()
-// OMP5-NEXT: #pragma omp target if(1)
+// OMP5-NEXT: #pragma omp target if(1) device(ancestor: argc)
 // OMP5-NEXT: foo()
 // OMP5-NEXT: #pragma omp target map(tofrom: i)
 // OMP5-NEXT: foo()
diff --git a/clang/test/OpenMP/target_data_device_messages.cpp b/clang/test/OpenMP/target_data_device_messages.cpp
index 873402d372ddf..7610e8413158c 100644
--- a/clang/test/OpenMP/target_data_device_messages.cpp
+++ b/clang/test/OpenMP/target_data_device_messages.cpp
@@ -1,6 +1,6 @@
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
 void foo() {
 }
@@ -24,6 +24,7 @@ int main(int argc, char **argv) {
   #pragma omp target data map(to: a) device (S1) // expected-error {{'S1' does not refer to a value}}
   #pragma omp target data map(to: a) device (-2) // expected-error {{argument to 'device' clause must be a non-negative integer value}}
   #pragma omp target data map(to: a) device (-10u)
+  #pragma omp target data map(to: a) device (ancestor: -10u) // expected-error {{use of undeclared identifier 'ancestor'}} expected-error {{expected ')'}} expected-note {{to match this '('}}
   #pragma omp target data map(to: a) device (3.14) // expected-error {{expression must have integral or unscoped enumeration type, not 'double'}}
   foo();
 
diff --git a/clang/test/OpenMP/target_device_messages.cpp b/clang/test/OpenMP/target_device_messages.cpp
index 8a583e9f3bd74..1ca4a88ba8c53 100644
--- a/clang/test/OpenMP/target_device_messages.cpp
+++ b/clang/test/OpenMP/target_device_messages.cpp
@@ -1,6 +1,8 @@
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify=expected,omp45 -fopenmp -fopenmp-version=45 -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify=expected,omp50 -fopenmp -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify=expected,omp45 -fopenmp-simd -fopenmp-version=45 -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify=expected,omp50 -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
 void foo() {
 }
@@ -21,11 +23,13 @@ int main(int argc, char **argv) {
   foo();
   #pragma omp target device (argc // expected-error {{expected ')'}} expected-note {{to match this '('}}
   foo();
+  #pragma omp target device (argc: // expected-error {{expected ')'}} expected-note {{to match this '('}} omp50-error {{expected expression}}
+  foo();
   #pragma omp target device (z-argc)) // expected-warning {{extra tokens at the end of '#pragma omp target' are ignored}}
   foo();
-  #pragma omp target device (argc > 0 ? argv[1] : argv[2]) // expected-error {{expression must have integral or unscoped enumeration type, not 'char *'}}
+  #pragma omp target device (device_num : argc > 0 ? argv[1] : argv[2]) // omp45-error {{use of undeclared identifier 'device_num'}} omp45-error {{expected ')'}} omp45-note {{to match this '('}} omp50-error {{expression must have integral or unscoped enumeration type, not 'char *'}}
   foo();
-  #pragma omp target device (argc + argc)
+  #pragma omp target device (argc: argc + argc) // omp45-error {{expected ')'}} omp45-note {{to match this '('}} omp50-error {{expected 'ancestor' or 'device_num' in OpenMP clause 'device'}}
   foo();
   #pragma omp target device (argc), device (argc+1) // expected-error {{directive '#pragma omp target' cannot contain more than one 'device' clause}}
   foo();
@@ -37,6 +41,8 @@ int main(int argc, char **argv) {
   foo();
   #pragma omp target device (3.14) // expected-error {{expression must have integral or unscoped enumeration type, not 'double'}}
   foo();
+  #pragma omp target device (ancestor) // expected-error {{use of undeclared identifier 'ancestor'}}
+  foo();
 
   return 0;
 }
diff --git a/clang/test/OpenMP/target_enter_data_device_messages.cpp b/clang/test/OpenMP/target_enter_data_device_messages.cpp
index a233a47152dc0..7f5356b2fc5f4 100644
--- a/clang/test/OpenMP/target_enter_data_device_messages.cpp
+++ b/clang/test/OpenMP/target_enter_data_device_messages.cpp
@@ -1,6 +1,6 @@
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
 void foo() {
 }
@@ -24,6 +24,7 @@ int main(int argc, char **argv) {
   #pragma omp target enter data map(to: i) device (S1) // expected-error {{'S1' does not refer to a value}}
   #pragma omp target enter data map(to: i) device (-2) // expected-error {{argument to 'device' clause must be a non-negative integer value}}
   #pragma omp target enter data map(to: i) device (-10u)
+  #pragma omp target enter data map(to: i) device (device_num: -10u) // expected-error {{use of undeclared identifier 'device_num'}} expected-error {{expected ')'}} expected-note {{to match this '('}}
   #pragma omp target enter data map(to: i) device (3.14) // expected-error {{expression must have integral or unscoped enumeration type, not 'double'}}
   foo();
 
diff --git a/clang/test/OpenMP/target_exit_data_device_messages.cpp b/clang/test/OpenMP/target_exit_data_device_messages.cpp
index 035bf6f76a615..f896882f6f1b0 100644
--- a/clang/test/OpenMP/target_exit_data_device_messages.cpp
+++ b/clang/test/OpenMP/target_exit_data_device_messages.cpp
@@ -1,6 +1,6 @@
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
-// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -ferror-limit 100 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -triple x86_64-apple-macos10.7.0 -verify -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 -o - %s -Wuninitialized
 
 void foo() {
 }
@@ -24,6 +24,7 @@ int main(int argc, char **argv) {
   #pragma omp target exit data map(from: i) device (S1) // expected-error {{'S1' does not refer to a value}}
   #pragma omp target exit data map(from: i) device (-2) // expected-error {{argument to 'device' clause must be a non-negative integer value}}
   #pragma omp target exit data map(from: i) device (-10u + z)
+  #pragma omp target exit data map(from: i) device (ancestor: -10u + z) // expected-error {{use of undeclared identifier 'ancestor'}} expected-error {{expected ')'}} expected-note {{to match this '('}}
   #pragma omp target exit data map(from: i) device (3.14) // expected-error {{expression must have integral or unscoped enumeration type, not 'double'}}
   foo();
 
diff --git a/clang/test/OpenMP/target_update_device_messages.cpp b/clang/test/OpenMP/target_update_device_messages.cpp
index 8b4aefaf580d8..fa1c356f9c40c 100644
--- a/clang/test/OpenMP/target_update_device_messages.cpp
+++ b/clang/test/OpenMP/target_update_device_messages.cpp
@@ -1,6 +1,6 @@
-// RUN: %clang_cc1 -verify -fopenmp -ferror-limit 100 %s -Wuninitialized
+// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -ferror-limit 100 %s -Wuninitialized
 
-// RUN: %clang_cc1 -verify -fopenmp-simd -ferror-limit 100 %s -Wuninitialized
+// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -ferror-limit 100 %s -Wuninitialized
 
 void foo() {
 }
@@ -21,6 +21,7 @@ int tmain(T argc, S **argv) {
 #pragma omp target update to(i) device (argc)) // expected-warning {{extra tokens at the end of '#pragma omp target update' are ignored}}
 #pragma omp target update from(i) device (argc > 0 ? argv[1] : argv[2]) // expected-error {{expression must have integral or unscoped enumeration type, not 'char *'}}
 #pragma omp target update from(i) device (argc + z)
+#pragma omp target update from(i) device (device_num: argc + z) // expected-error {{use of undeclared identifier 'device_num'}} expected-error {{expected ')'}} expected-note {{to match this '('}}
 #pragma omp target update from(i) device (argc), device (argc+1) // expected-error {{directive '#pragma omp target update' cannot contain more than one 'device' clause}}
 #pragma omp target update from(i) device (S1) // expected-error {{'S1' does not refer to a value}}
 #pragma omp target update from(i) device (3.14) // expected-error 2 {{expression must have integral or unscoped enumeration type, not 'double'}}
diff --git a/clang/test/OpenMP/task_ast_print.cpp b/clang/test/OpenMP/task_ast_print.cpp
index f8a669523a5af..73323c6c2ae57 100644
--- a/clang/test/OpenMP/task_ast_print.cpp
+++ b/clang/test/OpenMP/task_ast_print.cpp
@@ -11,6 +11,7 @@
 #define HEADER
 
 typedef void *omp_depend_t;
+typedef unsigned long omp_event_handle_t;
 
 void foo() {}
 
@@ -31,8 +32,9 @@ class S7 : public T {
 public:
   S7(typename T::type v) : a(v) {
     omp_depend_t x;
+    omp_event_handle_t evt;
 #pragma omp taskgroup allocate(b) task_reduction(+:b)
-#pragma omp task private(a) private(this->a) private(T::a) in_reduction(+:this->b) allocate(b) depend(depobj:x)
+#pragma omp task private(a) private(this->a) private(T::a) in_reduction(+:this->b) allocate(b) depend(depobj:x) detach(evt)
     for (int k = 0; k < a.a; ++k)
       ++this->a.a;
   }
@@ -45,7 +47,7 @@ class S7 : public T {
 };
 
 // CHECK: #pragma omp taskgroup allocate(this->b) task_reduction(+: this->b)
-// CHECK: #pragma omp task private(this->a) private(this->a) private(T::a) in_reduction(+: this->b) allocate(this->b) depend(depobj : x){{$}}
+// CHECK: #pragma omp task private(this->a) private(this->a) private(T::a) in_reduction(+: this->b) allocate(this->b) depend(depobj : x) detach(evt){{$}}
 // CHECK: #pragma omp task private(this->a) private(this->a)
 // CHECK: #pragma omp task private(this->a) private(this->a) private(this->S1::a)
 
@@ -96,7 +98,8 @@ T tmain(T argc, T *argv) {
   S<T> s;
   T arr[argc];
   omp_depend_t x;
-#pragma omp task untied depend(in : argc, argv[b:argc], arr[:]) if (task : argc > 0) depend(depobj: x)
+  omp_event_handle_t evt;
+#pragma omp task untied depend(in : argc, argv[b:argc], arr[:]) if (task : argc > 0) depend(depobj: x) detach(evt)
   a = 2;
 #pragma omp task default(none), private(argc, b) firstprivate(argv) shared(d) if (argc > 0) final(S<T>::TS > 0) priority(argc)
   foo();
@@ -112,7 +115,8 @@ T tmain(T argc, T *argv) {
 // CHECK-NEXT: S<T> s;
 // CHECK-NEXT: T arr[argc];
 // CHECK-NEXT: omp_depend_t x;
-// CHECK-NEXT: #pragma omp task untied depend(in : argc,argv[b:argc],arr[:]) if(task: argc > 0) depend(depobj : x)
+// CHECK-NEXT: omp_event_handle_t evt;
+// CHECK-NEXT: #pragma omp task untied depend(in : argc,argv[b:argc],arr[:]) if(task: argc > 0) depend(depobj : x) detach(evt)
 // CHECK-NEXT: a = 2;
 // CHECK-NEXT: #pragma omp task default(none) private(argc,b) firstprivate(argv) shared(d) if(argc > 0) final(S<T>::TS > 0) priority(argc)
 // CHECK-NEXT: foo()
@@ -125,7 +129,8 @@ T tmain(T argc, T *argv) {
 // CHECK-NEXT: S<int> s;
 // CHECK-NEXT: int arr[argc];
 // CHECK-NEXT: omp_depend_t x;
-// CHECK-NEXT: #pragma omp task untied depend(in : argc,argv[b:argc],arr[:]) if(task: argc > 0) depend(depobj : x)
+// CHECK-NEXT: omp_event_handle_t evt;
+// CHECK-NEXT: #pragma omp task untied depend(in : argc,argv[b:argc],arr[:]) if(task: argc > 0) depend(depobj : x) detach(evt)
 // CHECK-NEXT: a = 2;
 // CHECK-NEXT: #pragma omp task default(none) private(argc,b) firstprivate(argv) shared(d) if(argc > 0) final(S<int>::TS > 0) priority(argc)
 // CHECK-NEXT: foo()
@@ -138,7 +143,8 @@ T tmain(T argc, T *argv) {
 // CHECK-NEXT: S<long> s;
 // CHECK-NEXT: long arr[argc];
 // CHECK-NEXT: omp_depend_t x;
-// CHECK-NEXT: #pragma omp task untied depend(in : argc,argv[b:argc],arr[:]) if(task: argc > 0) depend(depobj : x)
+// CHECK-NEXT: omp_event_handle_t evt;
+// CHECK-NEXT: #pragma omp task untied depend(in : argc,argv[b:argc],arr[:]) if(task: argc > 0) depend(depobj : x) detach(evt)
 // CHECK-NEXT: a = 2;
 // CHECK-NEXT: #pragma omp task default(none) private(argc,b) firstprivate(argv) shared(d) if(argc > 0) final(S<long>::TS > 0) priority(argc)
 // CHECK-NEXT: foo()
@@ -154,6 +160,7 @@ int main(int argc, char **argv) {
   static int a;
   int arr[10], arr1[argc];
   omp_depend_t y;
+  omp_event_handle_t evt;
 #pragma omp threadprivate(a)
   Enum ee;
 // CHECK: Enum ee;
@@ -162,9 +169,9 @@ int main(int argc, char **argv) {
   a = 2;
 // CHECK-NEXT: a = 2;
 #pragma omp taskgroup task_reduction(min: arr1)
-#pragma omp task default(none), private(argc, b) firstprivate(argv) if (argc > 0) final(a > 0) depend(inout : a, argv[:argc],arr[:a]) priority(23) in_reduction(min: arr1)
+#pragma omp task default(none), private(argc, b) firstprivate(argv, evt) if (argc > 0) final(a > 0) depend(inout : a, argv[:argc],arr[:a]) priority(23) in_reduction(min: arr1), detach(evt)
   // CHECK-NEXT: #pragma omp taskgroup task_reduction(min: arr1)
-  // CHECK-NEXT: #pragma omp task default(none) private(argc,b) firstprivate(argv) if(argc > 0) final(a > 0) depend(inout : a,argv[:argc],arr[:a]) priority(23) in_reduction(min: arr1)
+  // CHECK-NEXT: #pragma omp task default(none) private(argc,b) firstprivate(argv,evt) if(argc > 0) final(a > 0) depend(inout : a,argv[:argc],arr[:a]) priority(23) in_reduction(min: arr1) detach(evt)
   foo();
   // CHECK-NEXT: foo();
 #pragma omp taskgroup task_reduction(min: arr1)
diff --git a/clang/test/OpenMP/task_codegen.c b/clang/test/OpenMP/task_codegen.c
index c6b82193f1942..d0bbe5670d691 100644
--- a/clang/test/OpenMP/task_codegen.c
+++ b/clang/test/OpenMP/task_codegen.c
@@ -11,18 +11,24 @@
 #define HEADER
 
 typedef void *omp_depend_t;
+typedef __UINTPTR_TYPE__ omp_event_handle_t;
 
 void foo();
 
 // CHECK-LABEL: @main
 int main() {
   omp_depend_t d, x;
+  omp_event_handle_t evt;
   int a;
   // CHECK: [[D_ADDR:%.+]] = alloca i8*,
   // CHECK: [[X_ADDR:%.+]] = alloca i8*,
+  // CHECK: [[EVT_ADDR:%.+]] = alloca i64,
   // CHECK: [[A_ADDR:%.+]] = alloca i32,
   // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(
-  // CHECK: [[ALLOC:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @{{.+}}, i32 %0, i32 1, i64 40, i64 0, i32 (i32, i8*)* bitcast (i32 (i32, [[PRIVATES_TY:%.+]]*)* [[TASK_ENTRY:@.+]] to i32 (i32, i8*)*))
+  // CHECK: [[ALLOC:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @{{.+}}, i32 [[GTID]], i32 65, i64 48, i64 0, i32 (i32, i8*)* bitcast (i32 (i32, [[PRIVATES_TY:%.+]]*)* [[TASK_ENTRY:@.+]] to i32 (i32, i8*)*))
+  // CHECK: [[EVT_VAL:%.+]] = call i8* @__kmpc_task_allow_completion_event(%struct.ident_t* @{{.+}}, i32 [[GTID]], i8* [[ALLOC]])
+  // CHECK: [[CAST_EVT_VAL:%.+]] = ptrtoint i8* [[EVT_VAL]] to i64
+  // CHECK: store i64 [[CAST_EVT_VAL]], i64* [[EVT_ADDR]],
   // CHECK: [[DATA:%.+]] = bitcast i8* [[ALLOC]] to [[PRIVATES_TY]]*
   // CHECK: [[D:%.+]] = load i8*, i8** [[D_ADDR]],
   // CHECK: [[D_DEP:%.+]] = bitcast i8* [[D]] to %struct.kmp_depend_info*
@@ -55,7 +61,7 @@ int main() {
   // CHECK: [[DEST:%.+]] = bitcast %struct.kmp_depend_info* [[VLA_D]] to i8*
   // CHECK: [[SRC:%.+]] = bitcast %struct.kmp_depend_info* [[D_DEP]] to i8*
   // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[DEST]], i8* align 8 [[SRC]], i64 [[D_SIZE]], i1 false)
-  // CHECK: [[VLA_X:%.+]] = getelementptr %struct.kmp_depend_info, %struct.kmp_depend_info* %25, i64 [[SIZE1]]
+  // CHECK: [[VLA_X:%.+]] = getelementptr %struct.kmp_depend_info, %struct.kmp_depend_info* [[VLA_D]], i64 [[SIZE1]]
   // CHECK: [[X_SIZE:%.+]] = mul nuw i64 24, [[SIZE2]]
   // CHECK: [[DEST:%.+]] = bitcast %struct.kmp_depend_info* [[VLA_X]] to i8*
   // CHECK: [[SRC:%.+]] = bitcast %struct.kmp_depend_info* [[X_DEP]] to i8*
@@ -64,7 +70,7 @@ int main() {
   // CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @{{.+}}, i32 [[GTID]], i8* [[ALLOC]], i32 [[SIZE32]], i8* [[BC]], i32 0, i8* null)
   // CHECK: [[SV:%.+]] = load i8*, i8** [[SV_ADDR]],
   // CHECK: call void @llvm.stackrestore(i8* [[SV]])
-#pragma omp task depend(in: a) depend(depobj: d, x)
+#pragma omp task depend(in: a) depend(depobj: d, x) detach(evt)
   {
 #pragma omp taskgroup
     {
diff --git a/clang/test/OpenMP/task_messages.cpp b/clang/test/OpenMP/task_messages.cpp
index 062125f5f6ea6..ccead84775734 100644
--- a/clang/test/OpenMP/task_messages.cpp
+++ b/clang/test/OpenMP/task_messages.cpp
@@ -1,6 +1,8 @@
-// RUN: %clang_cc1 -verify -fopenmp -ferror-limit 100 -std=c++11 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -verify=expected,omp45 -fopenmp-version=45 -fopenmp -ferror-limit 200 -std=c++11 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -verify=expected,omp50 -fopenmp-version=50 -fopenmp -ferror-limit 200 -std=c++11 -o - %s -Wuninitialized
 
-// RUN: %clang_cc1 -verify -fopenmp-simd -ferror-limit 100 -std=c++11 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -verify=expected,omp45 -fopenmp-version=45 -fopenmp-simd -ferror-limit 200 -std=c++11 -o - %s -Wuninitialized
+// RUN: %clang_cc1 -verify=expected,omp50 -fopenmp-version=50 -fopenmp-simd -ferror-limit 200 -std=c++11 -o - %s -Wuninitialized
 
 void xxx(int argc) {
   int x; // expected-note {{initialize the variable 'x' to silence this warning}}
@@ -9,8 +11,12 @@ void xxx(int argc) {
 }
 
 void foo() {
+#pragma omp task detach(0) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'omp_event_handle_t' type not found; include <omp.h>}}
+  ;
 }
 
+typedef unsigned long omp_event_handle_t;
+
 #pragma omp task // expected-error {{unexpected OpenMP directive '#pragma omp task'}}
 
 class S {
@@ -125,6 +131,25 @@ int foo() {
 // expected-error@+1 {{directive '#pragma omp task' cannot contain more than one 'mergeable' clause}}
 #pragma omp task mergeable mergeable
   ++r;
+  volatile omp_event_handle_t evt;
+  const omp_event_handle_t cevt = 0;
+  omp_event_handle_t sevt;
+  omp_event_handle_t &revt = sevt;
+#pragma omp task detach // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{expected '(' after 'detach'}}
+#pragma omp task detach( // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}}
+#pragma omp task detach() // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{expected expression}}
+#pragma omp task detach(a) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'int'}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'S'}}
+  ;
+#pragma omp task detach(evt) detach(evt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}}
+#pragma omp task detach(cevt) detach(revt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'const omp_event_handle_t' (aka 'const unsigned long')}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'omp_event_handle_t &' (aka 'unsigned long &')}}
+#pragma omp task detach(evt) mergeable // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'mergeable' and 'detach' clause are mutually exclusive and may not appear on the same directive}} omp50-note {{'detach' clause is specified here}}
+  ;
+#pragma omp task mergeable detach(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'detach' and 'mergeable' clause are mutually exclusive and may not appear on the same directive}} omp50-note {{'mergeable' clause is specified here}}
+#pragma omp task detach(-evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{expected variable of the 'omp_event_handle_t' type}}
+  ;
+#pragma omp task detach(evt) shared(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
+#pragma omp task detach(evt) firstprivate(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
+  ;
   return a + b;
 }
 
@@ -290,6 +315,24 @@ int main(int argc, char **argv) {
 // expected-error@+1 {{directive '#pragma omp task' cannot contain more than one 'mergeable' clause}}
 #pragma omp task mergeable mergeable
   ++r;
+  volatile omp_event_handle_t evt;
+  omp_event_handle_t sevt;
+  const omp_event_handle_t cevt = evt;
+  omp_event_handle_t &revt = sevt;
+#pragma omp task detach // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{expected '(' after 'detach'}}
+#pragma omp task detach( // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}}
+#pragma omp task detach() // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{expected expression}}
+#pragma omp task detach(a) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'int'}}
+#pragma omp task detach(evt) detach(evt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}}
+#pragma omp task detach(cevt) detach(revt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'const omp_event_handle_t' (aka 'const unsigned long')}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'omp_event_handle_t &' (aka 'unsigned long &')}}
+#pragma omp task detach(evt) mergeable // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'mergeable' and 'detach' clause are mutually exclusive and may not appear on the same directive}} omp50-note {{'detach' clause is specified here}}
+  ;
+#pragma omp task mergeable detach(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'detach' and 'mergeable' clause are mutually exclusive and may not appear on the same directive}} omp50-note {{'mergeable' clause is specified here}}
+#pragma omp task detach(-evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{expected variable of the 'omp_event_handle_t' type}}
+  ;
+#pragma omp task detach(evt) shared(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
+#pragma omp task detach(evt) firstprivate(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
+  ;
   // expected-note@+2 {{in instantiation of function template specialization 'foo<int>' requested here}}
   // expected-note@+1 {{in instantiation of function template specialization 'foo<S>' requested here}}
   return foo<int>() + foo<S>();
diff --git a/clang/test/Parser/cxx-template-decl.cpp b/clang/test/Parser/cxx-template-decl.cpp
index 3d7a3dc14f4c4..0d52ad8fb50f0 100644
--- a/clang/test/Parser/cxx-template-decl.cpp
+++ b/clang/test/Parser/cxx-template-decl.cpp
@@ -273,3 +273,9 @@ namespace AnnotateAfterInvalidTemplateId {
 namespace PR45063 {
   template<class=class a::template b<>> struct X {}; // expected-error {{undeclared identifier 'a'}}
 }
+
+namespace NoCrashOnEmptyNestedNameSpecifier {
+  template <typename FnT,
+            typename T = typename ABC<FnT>::template arg_t<0>> // expected-error {{no template named 'ABC'}}
+  void foo(FnT) {}
+}
diff --git a/clang/test/Sema/attr-loader-uninitialized.c b/clang/test/Sema/attr-loader-uninitialized.c
new file mode 100644
index 0000000000000..f2e78d9815808
--- /dev/null
+++ b/clang/test/Sema/attr-loader-uninitialized.c
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+// See also attr-loader-uninitialized.cpp
+
+int good __attribute__((loader_uninitialized));
+static int local_ok __attribute__((loader_uninitialized));
+int hidden_ok __attribute__((visibility("hidden"))) __attribute__((loader_uninitialized));
+
+const int can_still_be_const __attribute__((loader_uninitialized));
+
+extern int external_rejected __attribute__((loader_uninitialized));
+// expected-error@-1 {{variable 'external_rejected' cannot be declared both 'extern' and with the 'loader_uninitialized' attribute}}
+
+int noargs __attribute__((loader_uninitialized(0)));
+// expected-error@-1 {{'loader_uninitialized' attribute takes no arguments}}
+
+int init_rejected __attribute__((loader_uninitialized)) = 42;
+// expected-error@-1 {{variable with 'loader_uninitialized' attribute cannot have an initializer}}
+
+int declaration_then_uninit_ok;
+int declaration_then_uninit_ok __attribute__((loader_uninitialized));
+
+int definition_then_uninit_rejected = 0;
+int definition_then_uninit_rejected __attribute__((loader_uninitialized));
+// expected-error@-1 {{redeclaration cannot add 'loader_uninitialized' attribute}}
+// expected-note@-3 {{previous definition is here}}
+
+int tentative_repeated_ok __attribute__((loader_uninitialized));
+int tentative_repeated_ok __attribute__((loader_uninitialized));
+
+__private_extern__ int private_extern_can_be_initialised = 10;
+__private_extern__ int therefore_uninit_private_extern_ok __attribute__((loader_uninitialized));
+
+__private_extern__ int initialized_private_extern_rejected __attribute__((loader_uninitialized)) = 5;
+// expected-error@-1 {{variable with 'loader_uninitialized' attribute cannot have an initializer}}
+
+extern __attribute__((visibility("hidden"))) int extern_hidden __attribute__((loader_uninitialized));
+// expected-error@-1 {{variable 'extern_hidden' cannot be declared both 'extern' and with the 'loader_uninitialized' attribute}}
diff --git a/clang/test/Sema/attr-loader-uninitialized.cpp b/clang/test/Sema/attr-loader-uninitialized.cpp
new file mode 100644
index 0000000000000..3a330b3d59655
--- /dev/null
+++ b/clang/test/Sema/attr-loader-uninitialized.cpp
@@ -0,0 +1,60 @@
+// RUN: %clang_cc1 %s -verify -fsyntax-only
+
+int good __attribute__((loader_uninitialized));
+static int local_ok __attribute__((loader_uninitialized));
+int hidden_ok __attribute__((visibility("hidden"))) __attribute__((loader_uninitialized));
+
+const int still_cant_be_const __attribute__((loader_uninitialized));
+// expected-error@-1 {{default initialization of an object of const type}}
+extern int external_rejected __attribute__((loader_uninitialized));
+// expected-error@-1 {{variable 'external_rejected' cannot be declared both 'extern' and with the 'loader_uninitialized' attribute}}
+
+int noargs __attribute__((loader_uninitialized(0)));
+// expected-error@-1 {{'loader_uninitialized' attribute takes no arguments}}
+
+int init_rejected __attribute__((loader_uninitialized)) = 42;
+// expected-error@-1 {{variable with 'loader_uninitialized' attribute cannot have an initializer}}
+
+void func() __attribute__((loader_uninitialized))
+// expected-warning@-1 {{'loader_uninitialized' attribute only applies to global variables}}
+{
+  int local __attribute__((loader_uninitialized));
+  // expected-warning@-1 {{'loader_uninitialized' attribute only applies to global variables}}
+
+  static int sl __attribute__((loader_uninitialized));
+}
+
+struct s {
+  __attribute__((loader_uninitialized)) int field;
+  // expected-warning@-1 {{'loader_uninitialized' attribute only applies to global variables}}
+
+  static __attribute__((loader_uninitialized)) int sfield;
+
+} __attribute__((loader_uninitialized));
+// expected-warning@-1 {{'loader_uninitialized' attribute only applies to global variables}}
+
+int redef_attr_first __attribute__((loader_uninitialized));
+int redef_attr_first;
+// expected-error@-1 {{redefinition of 'redef_attr_first'}}
+// expected-note@-3 {{previous definition is here}}
+
+int redef_attr_second;
+int redef_attr_second __attribute__((loader_uninitialized));
+// expected-warning@-1 {{attribute declaration must precede definition}}
+// expected-note@-3 {{previous definition is here}}
+// expected-error@-3 {{redefinition of 'redef_attr_second'}}
+// expected-note@-5 {{previous definition is here}}
+
+struct trivial {};
+
+trivial default_ok __attribute__((loader_uninitialized));
+trivial value_rejected  __attribute__((loader_uninitialized)) {};
+// expected-error@-1 {{variable with 'loader_uninitialized' attribute cannot have an initializer}}
+
+struct nontrivial
+{
+  nontrivial() {}
+};
+
+nontrivial needs_trivial_ctor __attribute__((loader_uninitialized));
+// expected-error@-1 {{variable with 'loader_uninitialized' attribute must have a trivial default constructor}}
diff --git a/clang/test/Sema/sizeless-1.c b/clang/test/Sema/sizeless-1.c
index 962595b7b1f86..c823823fa00c9 100644
--- a/clang/test/Sema/sizeless-1.c
+++ b/clang/test/Sema/sizeless-1.c
@@ -137,11 +137,17 @@ void func(int sel) {
   dump(&volatile_int8);
   dump(&const_volatile_int8);
 
+  dump(&local_int8 + 1); // expected-error {{arithmetic on a pointer to sizeless type}}
+
   *&local_int8 = local_int8;
   *&const_int8 = local_int8; // expected-error {{read-only variable is not assignable}}
   *&volatile_int8 = local_int8;
   *&const_volatile_int8 = local_int8; // expected-error {{read-only variable is not assignable}}
 
+  global_int8_ptr[0] = local_int8;       // expected-error {{subscript of pointer to sizeless type 'svint8_t'}}
+  global_int8_ptr[1] = local_int8;       // expected-error {{subscript of pointer to sizeless type 'svint8_t'}}
+  global_int8_ptr = &global_int8_ptr[2]; // expected-error {{subscript of pointer to sizeless type 'svint8_t'}}
+
   overf(local_int8);
   overf(local_int16);
 
@@ -154,6 +160,16 @@ void func(int sel) {
   noproto(local_int8);
   varargs(1, local_int8, local_int16);
 
+  global_int8_ptr++;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr--;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  ++global_int8_ptr;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  --global_int8_ptr;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr + 1;               // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr - 1;               // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr += 1;              // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr -= 1;              // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr - global_int8_ptr; // expected-error {{arithmetic on a pointer to sizeless type}}
+
   +init_int8;       // expected-error {{invalid argument type 'svint8_t'}}
   ++init_int8;      // expected-error {{cannot increment value of type 'svint8_t'}}
   init_int8++;      // expected-error {{cannot increment value of type 'svint8_t'}}
diff --git a/clang/test/SemaCXX/constant-expression-cxx2a.cpp b/clang/test/SemaCXX/constant-expression-cxx2a.cpp
index 01d2a7f58d481..42d7300c5fdec 100644
--- a/clang/test/SemaCXX/constant-expression-cxx2a.cpp
+++ b/clang/test/SemaCXX/constant-expression-cxx2a.cpp
@@ -1346,3 +1346,38 @@ namespace mutable_subobjects {
   auto &zti = typeid(z.y);
   static_assert(&zti == &typeid(Y));
 }
+
+namespace PR45133 {
+  struct A { long x; };
+
+  union U;
+  constexpr A foo(U *up);
+
+  union U {
+    A a = foo(this); // expected-note {{in call to 'foo(&u)'}}
+    int y;
+  };
+
+  constexpr A foo(U *up) {
+    up->y = 11; // expected-note {{assignment would change active union member during the initialization of a different member}}
+    return {42};
+  }
+
+  constinit U u = {}; // expected-error {{constant init}} expected-note {{constinit}}
+
+  template<int> struct X {};
+
+  union V {
+    int a, b;
+    constexpr V(X<0>) : a(a = 1) {} // ok
+    constexpr V(X<1>) : a(b = 1) {} // expected-note {{assignment would change active union member during the initialization of a different member}}
+    constexpr V(X<2>) : a() { b = 1; } // ok
+    // This case (changing the active member then changing it back) is debatable,
+    // but it seems appropriate to reject.
+    constexpr V(X<3>) : a((b = 1, a = 1)) {} // expected-note {{assignment would change active union member during the initialization of a different member}}
+  };
+  constinit V v0 = X<0>();
+  constinit V v1 = X<1>(); // expected-error {{constant init}} expected-note {{constinit}} expected-note {{in call}}
+  constinit V v2 = X<2>();
+  constinit V v3 = X<3>(); // expected-error {{constant init}} expected-note {{constinit}} expected-note {{in call}}
+}
diff --git a/clang/test/SemaCXX/invalid-member-expr.cpp b/clang/test/SemaCXX/invalid-member-expr.cpp
index 920d92380e69e..e0b40794a0ce7 100644
--- a/clang/test/SemaCXX/invalid-member-expr.cpp
+++ b/clang/test/SemaCXX/invalid-member-expr.cpp
@@ -1,6 +1,7 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s
 // RUN: %clang_cc1 -fsyntax-only -verify -std=c++98 %s
 // RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++20 %s
 
 class X {};
 
diff --git a/clang/test/SemaCXX/sizeless-1.cpp b/clang/test/SemaCXX/sizeless-1.cpp
index 8b6c00f6e044c..5cbf1923d7055 100644
--- a/clang/test/SemaCXX/sizeless-1.cpp
+++ b/clang/test/SemaCXX/sizeless-1.cpp
@@ -158,11 +158,17 @@ void func(int sel) {
   dump(&volatile_int8);
   dump(&const_volatile_int8);
 
+  dump(&local_int8 + 1); // expected-error {{arithmetic on a pointer to sizeless type}}
+
   *&local_int8 = local_int8;
   *&const_int8 = local_int8; // expected-error {{read-only variable is not assignable}}
   *&volatile_int8 = local_int8;
   *&const_volatile_int8 = local_int8; // expected-error {{read-only variable is not assignable}}
 
+  global_int8_ptr[0] = local_int8;       // expected-error {{subscript of pointer to sizeless type 'svint8_t'}}
+  global_int8_ptr[1] = local_int8;       // expected-error {{subscript of pointer to sizeless type 'svint8_t'}}
+  global_int8_ptr = &global_int8_ptr[2]; // expected-error {{subscript of pointer to sizeless type 'svint8_t'}}
+
   overf(local_int8);
   overf(local_int16);
 
@@ -174,6 +180,16 @@ void func(int sel) {
 
   varargs(1, local_int8, local_int16);
 
+  global_int8_ptr++;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr--;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  ++global_int8_ptr;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  --global_int8_ptr;                 // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr + 1;               // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr - 1;               // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr += 1;              // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr -= 1;              // expected-error {{arithmetic on a pointer to sizeless type}}
+  global_int8_ptr - global_int8_ptr; // expected-error {{arithmetic on a pointer to sizeless type}}
+
   +init_int8;       // expected-error {{invalid argument type 'svint8_t'}}
   ++init_int8;      // expected-error {{cannot increment value of type 'svint8_t'}}
   init_int8++;      // expected-error {{cannot increment value of type 'svint8_t'}}
@@ -329,6 +345,12 @@ void with_default(svint8_t = svint8_t());
 constexpr int ce_taking_int8(svint8_t) { return 1; } // expected-error {{constexpr function's 1st parameter type 'svint8_t' (aka '__SVInt8_t') is not a literal type}}
 #endif
 
+#if __cplusplus < 201703L
+void throwing_func() throw(svint8_t); // expected-error {{sizeless type 'svint8_t' (aka '__SVInt8_t') is not allowed in exception specification}}
+void throwing_pointer_func() throw(svint8_t *);
+void throwing_reference_func() throw(svint8_t &); // expected-error {{reference to sizeless type 'svint8_t' (aka '__SVInt8_t') is not allowed in exception specification}}
+#endif
+
 template <typename T>
 void template_fn_direct(T) {}
 template <typename T>
@@ -373,6 +395,34 @@ void cxx_only(int sel) {
   local_int16 = static_cast<svint16_t>(local_int8); // expected-error {{static_cast from 'svint8_t' (aka '__SVInt8_t') to 'svint16_t' (aka '__SVInt16_t') is not allowed}}
   sel = static_cast<int>(local_int8);               // expected-error {{static_cast from 'svint8_t' (aka '__SVInt8_t') to 'int' is not allowed}}
 
+  throw local_int8; // expected-error {{cannot throw object of sizeless type 'svint8_t'}}
+  throw global_int8_ptr;
+
+  try {
+  } catch (int) {
+  }
+  try {
+  } catch (svint8_t) { // expected-error {{cannot catch sizeless type 'svint8_t'}}
+  }
+  try {
+  } catch (svint8_t *) {
+  }
+  try {
+  } catch (svint8_t &) { // expected-error {{cannot catch reference to sizeless type 'svint8_t'}}
+  }
+
+  new svint8_t;     // expected-error {{allocation of sizeless type 'svint8_t'}}
+  new svint8_t();   // expected-error {{allocation of sizeless type 'svint8_t'}}
+  new svint8_t[10]; // expected-error {{allocation of sizeless type 'svint8_t'}}
+  new svint8_t *;
+
+  new (global_int8_ptr) svint8_t;     // expected-error {{allocation of sizeless type 'svint8_t'}}
+  new (global_int8_ptr) svint8_t();   // expected-error {{allocation of sizeless type 'svint8_t'}}
+  new (global_int8_ptr) svint8_t[10]; // expected-error {{allocation of sizeless type 'svint8_t'}}
+
+  delete global_int8_ptr;   // expected-error {{cannot delete expression of type 'svint8_t *'}}
+  delete[] global_int8_ptr; // expected-error {{cannot delete expression of type 'svint8_t *'}}
+
   local_int8.~__SVInt8_t(); // expected-error {{object expression of non-scalar type 'svint8_t' (aka '__SVInt8_t') cannot be used in a pseudo-destructor expression}}
 
   (void)svint8_t();
diff --git a/clang/test/SemaCXX/typo-correction.cpp b/clang/test/SemaCXX/typo-correction.cpp
index 33dea4d36b3e5..92a145074e728 100644
--- a/clang/test/SemaCXX/typo-correction.cpp
+++ b/clang/test/SemaCXX/typo-correction.cpp
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -fspell-checking-limit 0 -verify -Wno-c++11-extensions %s
+// RUN: %clang_cc1 -fspell-checking-limit 0 -verify -Wno-c++11-extensions -std=c++20 %s
 
 namespace PR21817{
 int a(-rsing[2]); // expected-error {{undeclared identifier 'rsing'; did you mean 'using'?}}
@@ -523,8 +524,8 @@ PR18685::BitVector Map;  // expected-error-re {{no type named 'BitVector' in nam
 namespace shadowed_template {
 template <typename T> class Fizbin {};  // expected-note {{'::shadowed_template::Fizbin' declared here}}
 class Baz {
-   int Fizbin();
-   Fizbin<int> qux;  // expected-error {{no template named 'Fizbin'; did you mean '::shadowed_template::Fizbin'?}}
+   int Fizbin;
+   Fizbin<int> qux; // expected-error {{no template named 'Fizbin'; did you mean '::shadowed_template::Fizbin'?}}
 };
 }
 
diff --git a/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp b/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp
index a41248ee1b8ef..cb497176ff0ee 100644
--- a/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp
+++ b/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -fcxx-exceptions -fexceptions -std=c++1y -fms-compatibility -fno-spell-checking -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fcxx-exceptions -fexceptions -std=c++20 -fms-compatibility -fno-spell-checking -fsyntax-only -verify %s
 
 
 template <class T>
diff --git a/clang/test/SemaTemplate/undeclared-template.cpp b/clang/test/SemaTemplate/undeclared-template.cpp
new file mode 100644
index 0000000000000..fccc29deea254
--- /dev/null
+++ b/clang/test/SemaTemplate/undeclared-template.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -std=c++2a -verify %s
+
+template<typename T> notdefined<T::any> PR45207; // expected-error {{no template named 'notdefined'}}
+
+// FIXME: We don't disambiguate this as an undeclared template-id even though there's nothing else it could be.
+template<typename T> int var_template(notdefined<T::any>); // expected-error {{undeclared identifier 'notdefined'}} expected-error {{expected expression}}
+
+// FIXME: We don't disambiguate this as a function template even though it can't be a variable template due to the ', int'.
+template<typename T> int fn_template(notdefined<T::any>, int); // expected-error {{undeclared identifier 'notdefined'}} expected-error {{expected expression}} expected-error {{expected '('}}
diff --git a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
index d8ab145941850..aefb761cd70cd 100644
--- a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
+++ b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
@@ -19,7 +19,7 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/ExecutionEngine/JITEventListener.h"
@@ -29,9 +29,9 @@
 #include "llvm/ExecutionEngine/RTDyldMemoryManager.h"
 #include "llvm/ExecutionEngine/SectionMemoryManager.h"
 #include "llvm/IR/IRPrintingPasses.h"
+#include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/IR/LegacyPassNameParser.h"
-#include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/Verifier.h"
 #include "llvm/IRReader/IRReader.h"
@@ -42,12 +42,14 @@
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Transforms/IPO/PassManagerBuilder.h"
 #include "llvm/Transforms/IPO.h"
+#include "llvm/Transforms/IPO/PassManagerBuilder.h"
 #include "llvm/Transforms/Vectorize.h"
 
 using namespace llvm;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 // Define a type for the functions that are compiled and executed
 typedef void (*LLVMFunc)(int*, int*, int*, int);
 
@@ -100,15 +102,17 @@ static std::string OptLLVM(const std::string &IR, CodeGenOpt::Level OLvl) {
     ErrorAndExit("Could not parse IR");
 
   Triple ModuleTriple(M->getTargetTriple());
-  const TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  const TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   std::string E;
-  const Target *TheTarget = TargetRegistry::lookupTarget(MArch, ModuleTriple, E);
-  TargetMachine *Machine =
-      TheTarget->createTargetMachine(M->getTargetTriple(), getCPUStr(),
-                                     getFeaturesStr(), Options, getRelocModel(),
-                                     getCodeModel(), OLvl);
+  const Target *TheTarget =
+      TargetRegistry::lookupTarget(codegen::getMArch(), ModuleTriple, E);
+  TargetMachine *Machine = TheTarget->createTargetMachine(
+      M->getTargetTriple(), codegen::getCPUStr(), codegen::getFeaturesStr(),
+      Options, codegen::getExplicitRelocModel(),
+      codegen::getExplicitCodeModel(), OLvl);
   std::unique_ptr<TargetMachine> TM(Machine);
-  setFunctionAttributes(getCPUStr(), getFeaturesStr(), *M);
+  codegen::setFunctionAttributes(codegen::getCPUStr(),
+                                 codegen::getFeaturesStr(), *M);
 
   legacy::PassManager Passes;
   
@@ -154,14 +158,14 @@ static void CreateAndRunJITFunc(const std::string &IR, CodeGenOpt::Level OLvl) {
 
   std::string ErrorMsg;
   EngineBuilder builder(std::move(M));
-  builder.setMArch(MArch);
-  builder.setMCPU(getCPUStr());
-  builder.setMAttrs(getFeatureList());
+  builder.setMArch(codegen::getMArch());
+  builder.setMCPU(codegen::getCPUStr());
+  builder.setMAttrs(codegen::getFeatureList());
   builder.setErrorStr(&ErrorMsg);
   builder.setEngineKind(EngineKind::JIT);
   builder.setMCJITMemoryManager(std::make_unique<SectionMemoryManager>());
   builder.setOptLevel(OLvl);
-  builder.setTargetOptions(InitTargetOptionsFromCodeGenFlags());
+  builder.setTargetOptions(codegen::InitTargetOptionsFromCodeGenFlags());
 
   std::unique_ptr<ExecutionEngine> EE(builder.create());
   if (!EE)
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index 62dc0e2b8f926..df5530c73c6d6 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -2220,6 +2220,10 @@ void OMPClauseEnqueue::VisitOMPOrderedClause(const OMPOrderedClause *C) {
   Visitor->AddStmt(C->getNumForLoops());
 }
 
+void OMPClauseEnqueue::VisitOMPDetachClause(const OMPDetachClause *C) {
+  Visitor->AddStmt(C->getEventHandler());
+}
+
 void OMPClauseEnqueue::VisitOMPNowaitClause(const OMPNowaitClause *) {}
 
 void OMPClauseEnqueue::VisitOMPUntiedClause(const OMPUntiedClause *) {}
diff --git a/clang/unittests/CodeGen/CodeGenExternalTest.cpp b/clang/unittests/CodeGen/CodeGenExternalTest.cpp
index 8dff45c8a0f53..255b8c3e9d8cd 100644
--- a/clang/unittests/CodeGen/CodeGenExternalTest.cpp
+++ b/clang/unittests/CodeGen/CodeGenExternalTest.cpp
@@ -199,7 +199,7 @@ static void test_codegen_fns(MyASTConsumer *my) {
           dbgs() << "\n";
         }
 
-        llvm::CompositeType* structTy = dyn_cast<CompositeType>(llvmTy);
+        auto* structTy = dyn_cast<llvm::StructType>(llvmTy);
         ASSERT_TRUE(structTy != NULL);
 
         // Check getLLVMFieldNumber
diff --git a/clang/unittests/Tooling/Syntax/TreeTest.cpp b/clang/unittests/Tooling/Syntax/TreeTest.cpp
index 1749e6635a12a..6e914b6378c86 100644
--- a/clang/unittests/Tooling/Syntax/TreeTest.cpp
+++ b/clang/unittests/Tooling/Syntax/TreeTest.cpp
@@ -174,17 +174,21 @@ void foo() {}
 *: TranslationUnit
 |-SimpleDeclaration
 | |-int
-| |-main
-| |-(
-| |-)
+| |-SimpleDeclarator
+| | |-main
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   `-)
 | `-CompoundStatement
 |   |-{
 |   `-}
 `-SimpleDeclaration
   |-void
-  |-foo
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-foo
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     `-}
@@ -201,9 +205,11 @@ int main() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-int
-  |-main
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-main
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-IfStatement
@@ -246,9 +252,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-ForStatement
@@ -268,18 +276,21 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-DeclarationStatement
     | |-SimpleDeclaration
     | | |-int
-    | | |-a
-    | | |-=
-    | | `-UnknownExpression
-    | |   `-10
+    | | `-SimpleDeclarator
+    | |   |-a
+    | |   |-=
+    | |   `-UnknownExpression
+    | |     `-10
     | `-;
     `-}
 )txt"},
@@ -287,9 +298,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-EmptyStatement
@@ -309,9 +322,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-SwitchStatement
@@ -345,9 +360,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-WhileStatement
@@ -375,9 +392,11 @@ int test() { return 1; }
 *: TranslationUnit
 `-SimpleDeclaration
   |-int
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-ReturnStatement
@@ -398,26 +417,31 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-DeclarationStatement
     | |-SimpleDeclaration
     | | |-int
-    | | |-a
-    | | |-[
-    | | |-UnknownExpression
-    | | | `-3
-    | | `-]
+    | | `-SimpleDeclarator
+    | |   |-a
+    | |   `-ArraySubscript
+    | |     |-[
+    | |     |-UnknownExpression
+    | |     | `-3
+    | |     `-]
     | `-;
     |-RangeBasedForStatement
     | |-for
     | |-(
     | |-SimpleDeclaration
     | | |-int
-    | | |-x
+    | | |-SimpleDeclarator
+    | | | `-x
     | | `-:
     | |-UnknownExpression
     | | `-a
@@ -433,9 +457,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-main
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-main
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-UnknownStatement
@@ -460,9 +486,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-ExpressionStatement
@@ -500,10 +528,12 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-int
-  |-*
-  |-a
+  |-SimpleDeclarator
+  | |-*
+  | `-a
   |-,
-  |-b
+  |-SimpleDeclarator
+  | `-b
   `-;
   )txt"},
       {R"cpp(
@@ -514,10 +544,12 @@ void test() {
 `-SimpleDeclaration
   |-typedef
   |-int
-  |-*
-  |-a
+  |-SimpleDeclarator
+  | |-*
+  | `-a
   |-,
-  |-b
+  |-SimpleDeclarator
+  | `-b
   `-;
   )txt"},
       // Multiple declarators inside a statement.
@@ -531,27 +563,33 @@ void foo() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-foo
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-foo
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-DeclarationStatement
     | |-SimpleDeclaration
     | | |-int
-    | | |-*
-    | | |-a
+    | | |-SimpleDeclarator
+    | | | |-*
+    | | | `-a
     | | |-,
-    | | `-b
+    | | `-SimpleDeclarator
+    | |   `-b
     | `-;
     |-DeclarationStatement
     | |-SimpleDeclaration
     | | |-typedef
     | | |-int
-    | | |-*
-    | | |-ta
+    | | |-SimpleDeclarator
+    | | | |-*
+    | | | `-ta
     | | |-,
-    | | `-tb
+    | | `-SimpleDeclarator
+    | |   `-tb
     | `-;
     `-}
   )txt"},
@@ -617,23 +655,26 @@ struct {} *a1;
 |-SimpleDeclaration
 | |-struct
 | |-Y
-| |-*
-| |-y1
+| |-SimpleDeclarator
+| | |-*
+| | `-y1
 | `-;
 |-SimpleDeclaration
 | |-struct
 | |-Y
 | |-{
 | |-}
-| |-*
-| |-y2
+| |-SimpleDeclarator
+| | |-*
+| | `-y2
 | `-;
 `-SimpleDeclaration
   |-struct
   |-{
   |-}
-  |-*
-  |-a1
+  |-SimpleDeclarator
+  | |-*
+  | `-a1
   `-;
 )txt"},
       {R"cpp(
@@ -666,7 +707,8 @@ using ns::a;
 | |-{
 | |-SimpleDeclaration
 | | |-int
-| | |-a
+| | |-SimpleDeclarator
+| | | `-a
 | | `-;
 | `-}
 `-UsingDeclaration
@@ -766,7 +808,8 @@ extern "C" { int b; int c; }
 | |-"C"
 | `-SimpleDeclaration
 |   |-int
-|   |-a
+|   |-SimpleDeclarator
+|   | `-a
 |   `-;
 `-LinkageSpecificationDeclaration
   |-extern
@@ -774,11 +817,13 @@ extern "C" { int b; int c; }
   |-{
   |-SimpleDeclaration
   | |-int
-  | |-b
+  | |-SimpleDeclarator
+  | | `-b
   | `-;
   |-SimpleDeclaration
   | |-int
-  | |-c
+  | |-SimpleDeclarator
+  | | `-c
   | `-;
   `-}
        )txt"},
@@ -793,9 +838,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-IfStatement
@@ -834,9 +881,11 @@ void test() {
 *: TranslationUnit
 `-SimpleDeclaration
   |-void
-  |-test
-  |-(
-  |-)
+  |-SimpleDeclarator
+  | |-test
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   `-)
   `-CompoundStatement
     |-{
     |-CompoundStatement
@@ -855,6 +904,533 @@ void test() {
     | `-}
     `-}
        )txt"},
+      // Array subscripts in declarators.
+      {R"cpp(
+int a[10];
+int b[1][2][3];
+int c[] = {1,2,3};
+void f(int xs[static 10]);
+    )cpp",
+       R"txt(
+*: TranslationUnit
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-a
+| | `-ArraySubscript
+| |   |-[
+| |   |-UnknownExpression
+| |   | `-10
+| |   `-]
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-b
+| | |-ArraySubscript
+| | | |-[
+| | | |-UnknownExpression
+| | | | `-1
+| | | `-]
+| | |-ArraySubscript
+| | | |-[
+| | | |-UnknownExpression
+| | | | `-2
+| | | `-]
+| | `-ArraySubscript
+| |   |-[
+| |   |-UnknownExpression
+| |   | `-3
+| |   `-]
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-c
+| | |-ArraySubscript
+| | | |-[
+| | | `-]
+| | |-=
+| | `-UnknownExpression
+| |   |-{
+| |   |-1
+| |   |-,
+| |   |-2
+| |   |-,
+| |   |-3
+| |   `-}
+| `-;
+`-SimpleDeclaration
+  |-void
+  |-SimpleDeclarator
+  | |-f
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-SimpleDeclaration
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   |-xs
+  |   |   `-ArraySubscript
+  |   |     |-[
+  |   |     |-static
+  |   |     |-UnknownExpression
+  |   |     | `-10
+  |   |     `-]
+  |   `-)
+  `-;
+       )txt"},
+      // Parameter lists in declarators.
+      {R"cpp(
+int a() const;
+int b() volatile;
+int c() &;
+int d() &&;
+int foo(int a, int b);
+int foo(
+  const int a,
+  volatile int b,
+  const volatile int c,
+  int* d,
+  int& e,
+  int&& f
+);
+    )cpp",
+       R"txt(
+*: TranslationUnit
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-a
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-)
+| |   `-const
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-b
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-)
+| |   `-volatile
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-c
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-)
+| |   `-&
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-d
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-)
+| |   `-&&
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-foo
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-SimpleDeclaration
+| |   | |-int
+| |   | `-SimpleDeclarator
+| |   |   `-a
+| |   |-,
+| |   |-SimpleDeclaration
+| |   | |-int
+| |   | `-SimpleDeclarator
+| |   |   `-b
+| |   `-)
+| `-;
+`-SimpleDeclaration
+  |-int
+  |-SimpleDeclarator
+  | |-foo
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-SimpleDeclaration
+  |   | |-const
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   `-a
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-volatile
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   `-b
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-const
+  |   | |-volatile
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   `-c
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   |-*
+  |   |   `-d
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   |-&
+  |   |   `-e
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-int
+  |   | `-SimpleDeclarator
+  |   |   |-&&
+  |   |   `-f
+  |   `-)
+  `-;
+       )txt"},
+      // Trailing const qualifier.
+      {R"cpp(
+struct X {
+  int foo() const;
+}
+    )cpp",
+       R"txt(
+*: TranslationUnit
+`-SimpleDeclaration
+  |-struct
+  |-X
+  |-{
+  |-SimpleDeclaration
+  | |-int
+  | |-SimpleDeclarator
+  | | |-foo
+  | | `-ParametersAndQualifiers
+  | |   |-(
+  | |   |-)
+  | |   `-const
+  | `-;
+  `-}
+    )txt"},
+      // Trailing return type in parameter lists.
+      {R"cpp(
+auto foo() -> int;
+    )cpp",
+       R"txt(
+*: TranslationUnit
+`-SimpleDeclaration
+  |-auto
+  |-SimpleDeclarator
+  | |-foo
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-)
+  |   `-TrailingReturnType
+  |     |-->
+  |     `-int
+  `-;
+       )txt"},
+      // Exception specification in parameter lists.
+      {R"cpp(
+int a() noexcept;
+int b() noexcept(true);
+int c() throw();
+    )cpp",
+       R"txt(
+*: TranslationUnit
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-a
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-)
+| |   `-noexcept
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-b
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-)
+| |   |-noexcept
+| |   |-(
+| |   |-UnknownExpression
+| |   | `-true
+| |   `-)
+| `-;
+`-SimpleDeclaration
+  |-int
+  |-SimpleDeclarator
+  | |-c
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-)
+  |   |-throw
+  |   |-(
+  |   `-)
+  `-;
+       )txt"},
+      // Declarators in parentheses.
+      {R"cpp(
+int (a);
+int *(b);
+int (*c)(int);
+int *(d)(int);
+    )cpp",
+       R"txt(
+*: TranslationUnit
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | `-ParenDeclarator
+| |   |-(
+| |   |-a
+| |   `-)
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-*
+| | `-ParenDeclarator
+| |   |-(
+| |   |-b
+| |   `-)
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-ParenDeclarator
+| | | |-(
+| | | |-*
+| | | |-c
+| | | `-)
+| | `-ParametersAndQualifiers
+| |   |-(
+| |   |-SimpleDeclaration
+| |   | `-int
+| |   `-)
+| `-;
+`-SimpleDeclaration
+  |-int
+  |-SimpleDeclarator
+  | |-*
+  | |-ParenDeclarator
+  | | |-(
+  | | |-d
+  | | `-)
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-SimpleDeclaration
+  |   | `-int
+  |   `-)
+  `-;
+       )txt"},
+      // CV qualifiers.
+      {R"cpp(
+const int west = -1;
+int const east = 1;
+const int const universal = 0;
+const int const *const *volatile b;
+    )cpp",
+       R"txt(
+*: TranslationUnit
+|-SimpleDeclaration
+| |-const
+| |-int
+| |-SimpleDeclarator
+| | |-west
+| | |-=
+| | `-UnknownExpression
+| |   |--
+| |   `-1
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-const
+| |-SimpleDeclarator
+| | |-east
+| | |-=
+| | `-UnknownExpression
+| |   `-1
+| `-;
+|-SimpleDeclaration
+| |-const
+| |-int
+| |-const
+| |-SimpleDeclarator
+| | |-universal
+| | |-=
+| | `-UnknownExpression
+| |   `-0
+| `-;
+`-SimpleDeclaration
+  |-const
+  |-int
+  |-const
+  |-SimpleDeclarator
+  | |-*
+  | |-const
+  | |-*
+  | |-volatile
+  | `-b
+  `-;
+       )txt"},
+      // Ranges of declarators with trailing return types.
+      {R"cpp(
+auto foo() -> auto(*)(int) -> double*;
+    )cpp",
+       R"txt(
+*: TranslationUnit
+`-SimpleDeclaration
+  |-auto
+  |-SimpleDeclarator
+  | |-foo
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-)
+  |   `-TrailingReturnType
+  |     |-->
+  |     |-auto
+  |     `-SimpleDeclarator
+  |       |-ParenDeclarator
+  |       | |-(
+  |       | |-*
+  |       | `-)
+  |       `-ParametersAndQualifiers
+  |         |-(
+  |         |-SimpleDeclaration
+  |         | `-int
+  |         |-)
+  |         `-TrailingReturnType
+  |           |-->
+  |           |-double
+  |           `-SimpleDeclarator
+  |             `-*
+  `-;
+       )txt"},
+      // Member pointers.
+      {R"cpp(
+struct X {};
+int X::* a;
+const int X::* b;
+    )cpp",
+       R"txt(
+*: TranslationUnit
+|-SimpleDeclaration
+| |-struct
+| |-X
+| |-{
+| |-}
+| `-;
+|-SimpleDeclaration
+| |-int
+| |-SimpleDeclarator
+| | |-MemberPointer
+| | | |-X
+| | | |-::
+| | | `-*
+| | `-a
+| `-;
+`-SimpleDeclaration
+  |-const
+  |-int
+  |-SimpleDeclarator
+  | |-MemberPointer
+  | | |-X
+  | | |-::
+  | | `-*
+  | `-b
+  `-;
+       )txt"},
+      // All-in-one tests.
+      {R"cpp(
+void x(char a, short (*b)(int));
+    )cpp",
+       R"txt(
+*: TranslationUnit
+`-SimpleDeclaration
+  |-void
+  |-SimpleDeclarator
+  | |-x
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-SimpleDeclaration
+  |   | |-char
+  |   | `-SimpleDeclarator
+  |   |   `-a
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-short
+  |   | `-SimpleDeclarator
+  |   |   |-ParenDeclarator
+  |   |   | |-(
+  |   |   | |-*
+  |   |   | |-b
+  |   |   | `-)
+  |   |   `-ParametersAndQualifiers
+  |   |     |-(
+  |   |     |-SimpleDeclaration
+  |   |     | `-int
+  |   |     `-)
+  |   `-)
+  `-;
+       )txt"},
+      {R"cpp(
+void x(char a, short (*b)(int), long (**c)(long long));
+    )cpp",
+       R"txt(
+*: TranslationUnit
+`-SimpleDeclaration
+  |-void
+  |-SimpleDeclarator
+  | |-x
+  | `-ParametersAndQualifiers
+  |   |-(
+  |   |-SimpleDeclaration
+  |   | |-char
+  |   | `-SimpleDeclarator
+  |   |   `-a
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-short
+  |   | `-SimpleDeclarator
+  |   |   |-ParenDeclarator
+  |   |   | |-(
+  |   |   | |-*
+  |   |   | |-b
+  |   |   | `-)
+  |   |   `-ParametersAndQualifiers
+  |   |     |-(
+  |   |     |-SimpleDeclaration
+  |   |     | `-int
+  |   |     `-)
+  |   |-,
+  |   |-SimpleDeclaration
+  |   | |-long
+  |   | `-SimpleDeclarator
+  |   |   |-ParenDeclarator
+  |   |   | |-(
+  |   |   | |-*
+  |   |   | |-*
+  |   |   | |-c
+  |   |   | `-)
+  |   |   `-ParametersAndQualifiers
+  |   |     |-(
+  |   |     |-SimpleDeclaration
+  |   |     | |-long
+  |   |     | `-long
+  |   |     `-)
+  |   `-)
+  `-;
+       )txt"},
   };
 
   for (const auto &T : Cases) {
diff --git a/clang/utils/TableGen/CMakeLists.txt b/clang/utils/TableGen/CMakeLists.txt
index 1d992fd04b1b2..cba08d4954e34 100644
--- a/clang/utils/TableGen/CMakeLists.txt
+++ b/clang/utils/TableGen/CMakeLists.txt
@@ -17,6 +17,7 @@ add_tablegen(clang-tblgen CLANG
   ClangTypeNodesEmitter.cpp
   MveEmitter.cpp
   NeonEmitter.cpp
+  SveEmitter.cpp
   TableGen.cpp
   )
 set_target_properties(clang-tblgen PROPERTIES FOLDER "Clang tablegenning")
diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp
index ce95d78d7db03..c516c5c487e43 100644
--- a/clang/utils/TableGen/ClangAttrEmitter.cpp
+++ b/clang/utils/TableGen/ClangAttrEmitter.cpp
@@ -2329,7 +2329,7 @@ static void emitAttributes(RecordKeeper &Records, raw_ostream &OS,
     SemanticSpellingMap SemanticToSyntacticMap;
 
     std::string SpellingEnum;
-    if (!ElideSpelling)
+    if (Spellings.size() > 1)
       SpellingEnum = CreateSemanticSpellings(Spellings, SemanticToSyntacticMap);
     if (Header)
       OS << SpellingEnum;
diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp
new file mode 100644
index 0000000000000..8b53e376cb0d7
--- /dev/null
+++ b/clang/utils/TableGen/SveEmitter.cpp
@@ -0,0 +1,743 @@
+//===- SveEmitter.cpp - Generate arm_sve.h for use with clang -*- C++ -*-===//
+//
+//  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+//  See https://llvm.org/LICENSE.txt for license information.
+//  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend is responsible for emitting arm_sve.h, which includes
+// a declaration and definition of each function specified by the ARM C/C++
+// Language Extensions (ACLE).
+//
+// For details, visit:
+//  https://developer.arm.com/architectures/system-architectures/software-standards/acle
+//
+// Each SVE instruction is implemented in terms of 1 or more functions which
+// are suffixed with the element type of the input vectors.  Functions may be
+// implemented in terms of generic vector operations such as +, *, -, etc. or
+// by calling a __builtin_-prefixed function which will be handled by clang's
+// CodeGen library.
+//
+// See also the documentation in include/clang/Basic/arm_sve.td.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/Error.h"
+#include <string>
+#include <sstream>
+#include <set>
+#include <cctype>
+
+using namespace llvm;
+
+enum ClassKind {
+  ClassNone,
+  ClassS,     // signed/unsigned, e.g., "_s8", "_u8" suffix
+  ClassG,     // Overloaded name without type suffix
+};
+
+using TypeSpec = std::string;
+
+namespace {
+
+class SVEType {
+  TypeSpec TS;
+  bool Float, Signed, Immediate, Void, Constant, Pointer;
+  bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp;
+  unsigned Bitwidth, ElementBitwidth, NumVectors;
+
+public:
+  SVEType() : SVEType(TypeSpec(), 'v') {}
+
+  SVEType(TypeSpec TS, char CharMod)
+      : TS(TS), Float(false), Signed(true), Immediate(false), Void(false),
+        Constant(false), Pointer(false), DefaultType(false), IsScalable(true),
+        Predicate(false), PredicatePattern(false), PrefetchOp(false),
+        Bitwidth(128), ElementBitwidth(~0U), NumVectors(1) {
+    if (!TS.empty())
+      applyTypespec();
+    applyModifier(CharMod);
+  }
+
+  /// Return the value in SVETypeFlags for this type.
+  unsigned getTypeFlags() const;
+
+  bool isPointer() const { return Pointer; }
+  bool isVoidPointer() const { return Pointer && Void; }
+  bool isSigned() const { return Signed; }
+  bool isImmediate() const { return Immediate; }
+  bool isScalar() const { return NumVectors == 0; }
+  bool isVector() const { return NumVectors > 0; }
+  bool isScalableVector() const { return isVector() && IsScalable; }
+  bool isChar() const { return ElementBitwidth == 8; }
+  bool isVoid() const { return Void & !Pointer; }
+  bool isDefault() const { return DefaultType; }
+  bool isFloat() const { return Float; }
+  bool isInteger() const { return !Float && !Predicate; }
+  bool isScalarPredicate() const { return !Float && ElementBitwidth == 1; }
+  bool isPredicateVector() const { return Predicate; }
+  bool isPredicatePattern() const { return PredicatePattern; }
+  bool isPrefetchOp() const { return PrefetchOp; }
+  bool isConstant() const { return Constant; }
+  unsigned getElementSizeInBits() const { return ElementBitwidth; }
+  unsigned getNumVectors() const { return NumVectors; }
+
+  unsigned getNumElements() const {
+    assert(ElementBitwidth != ~0U);
+    return Bitwidth / ElementBitwidth;
+  }
+  unsigned getSizeInBits() const {
+    return Bitwidth;
+  }
+
+  /// Return the string representation of a type, which is an encoded
+  /// string for passing to the BUILTIN() macro in Builtins.def.
+  std::string builtin_str() const;
+
+private:
+  /// Creates the type based on the typespec string in TS.
+  void applyTypespec();
+
+  /// Applies a prototype modifier to the type.
+  void applyModifier(char Mod);
+};
+
+
+class SVEEmitter;
+
+/// The main grunt class. This represents an instantiation of an intrinsic with
+/// a particular typespec and prototype.
+class Intrinsic {
+  /// The unmangled name.
+  std::string Name;
+
+  /// The name of the corresponding LLVM IR intrinsic.
+  std::string LLVMName;
+
+  /// Intrinsic prototype.
+  std::string Proto;
+
+  /// The base type spec for this intrinsic.
+  TypeSpec BaseTypeSpec;
+
+  /// The base class kind. Most intrinsics use ClassS, which has full type
+  /// info for integers (_s32/_u32), or ClassG which is used for overloaded
+  /// intrinsics.
+  ClassKind Class;
+
+  /// The architectural #ifdef guard.
+  std::string Guard;
+
+  /// The types of return value [0] and parameters [1..].
+  std::vector<SVEType> Types;
+
+  /// The "base type", which is VarType('d', BaseTypeSpec).
+  SVEType BaseType;
+
+  unsigned Flags;
+
+public:
+  /// The type of predication.
+  enum MergeType {
+    MergeNone,
+    MergeAny,
+    MergeOp1,
+    MergeZero,
+    MergeAnyExp,
+    MergeZeroExp,
+    MergeInvalid
+  } Merge;
+
+  Intrinsic(StringRef Name, StringRef Proto, int64_t MT, StringRef LLVMName,
+            unsigned Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
+            StringRef Guard)
+      : Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
+        BaseTypeSpec(BT), Class(Class), Guard(Guard.str()), BaseType(BT, 'd'),
+        Flags(Flags), Merge(MergeType(MT)) {
+    // Types[0] is the return value.
+    for (unsigned I = 0; I < Proto.size(); ++I)
+      Types.emplace_back(BaseTypeSpec, Proto[I]);
+  }
+
+  ~Intrinsic()=default;
+
+  std::string getName() const { return Name; }
+  std::string getLLVMName() const { return LLVMName; }
+  std::string getProto() const { return Proto; }
+  TypeSpec getBaseTypeSpec() const { return BaseTypeSpec; }
+  SVEType getBaseType() const { return BaseType; }
+
+  StringRef getGuard() const { return Guard; }
+  ClassKind getClassKind() const { return Class; }
+  MergeType getMergeType() const { return Merge; }
+
+  SVEType getReturnType() const { return Types[0]; }
+  ArrayRef<SVEType> getTypes() const { return Types; }
+  SVEType getParamType(unsigned I) const { return Types[I + 1]; }
+  unsigned getNumParams() const { return Proto.size() - 1; }
+
+  unsigned getFlags() const { return Flags; }
+  bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
+
+  /// Return the type string for a BUILTIN() macro in Builtins.def.
+  std::string getBuiltinTypeStr();
+
+  /// Return the name, mangled with type information. The name is mangled for
+  /// ClassS, so will add type suffixes such as _u32/_s32.
+  std::string getMangledName() const { return mangleName(ClassS); }
+
+  /// Returns true if the intrinsic is overloaded, in that it should also generate
+  /// a short form without the type-specifiers, e.g. 'svld1(..)' instead of
+  /// 'svld1_u32(..)'.
+  static bool isOverloadedIntrinsic(StringRef Name) {
+    auto BrOpen = Name.find("[");
+    auto BrClose = Name.find(']');
+    return BrOpen != std::string::npos && BrClose != std::string::npos;
+  }
+
+  /// Emits the intrinsic declaration to the ostream.
+  void emitIntrinsic(raw_ostream &OS) const;
+
+private:
+  std::string getMergeSuffix() const;
+  std::string mangleName(ClassKind LocalCK) const;
+  std::string replaceTemplatedArgs(std::string Name, TypeSpec TS,
+                                   std::string Proto) const;
+};
+
+class SVEEmitter {
+private:
+  RecordKeeper &Records;
+  llvm::StringMap<uint64_t> EltTypes;
+  llvm::StringMap<uint64_t> MemEltTypes;
+  llvm::StringMap<uint64_t> FlagTypes;
+
+  unsigned getTypeFlags(const SVEType &T);
+public:
+  SVEEmitter(RecordKeeper &R) : Records(R) {
+    for (auto *RV : Records.getAllDerivedDefinitions("EltType"))
+      EltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+    for (auto *RV : Records.getAllDerivedDefinitions("MemEltType"))
+      MemEltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+    for (auto *RV : Records.getAllDerivedDefinitions("FlagType"))
+      FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  /// Emit arm_sve.h.
+  void createHeader(raw_ostream &o);
+
+  /// Emit all the __builtin prototypes and code needed by Sema.
+  void createBuiltins(raw_ostream &o);
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createCodeGenMap(raw_ostream &o);
+
+  /// Create the SVETypeFlags used in CGBuiltins
+  void createTypeFlags(raw_ostream &o);
+
+  /// Create intrinsic and add it to \p Out
+  void createIntrinsic(Record *R, SmallVectorImpl<std::unique_ptr<Intrinsic>> &Out);
+};
+
+} // end anonymous namespace
+
+
+//===----------------------------------------------------------------------===//
+// Type implementation
+//===----------------------------------------------------------------------===//
+
+unsigned SVEEmitter::getTypeFlags(const SVEType &T) {
+  unsigned FirstEltType = EltTypes["FirstEltType"];
+  if (T.isFloat()) {
+    switch (T.getElementSizeInBits()) {
+    case 16: return FirstEltType + EltTypes["EltTyFloat16"];
+    case 32: return FirstEltType + EltTypes["EltTyFloat32"];
+    case 64: return FirstEltType + EltTypes["EltTyFloat64"];
+    default: llvm_unreachable("Unhandled float element bitwidth!");
+    }
+  }
+
+  if (T.isPredicateVector()) {
+    switch (T.getElementSizeInBits()) {
+    case 8:  return FirstEltType + EltTypes["EltTyBool8"];
+    case 16: return FirstEltType + EltTypes["EltTyBool16"];
+    case 32: return FirstEltType + EltTypes["EltTyBool32"];
+    case 64: return FirstEltType + EltTypes["EltTyBool64"];
+    default: llvm_unreachable("Unhandled predicate element bitwidth!");
+    }
+  }
+
+  switch (T.getElementSizeInBits()) {
+  case 8:  return FirstEltType + EltTypes["EltTyInt8"];
+  case 16: return FirstEltType + EltTypes["EltTyInt16"];
+  case 32: return FirstEltType + EltTypes["EltTyInt32"];
+  case 64: return FirstEltType + EltTypes["EltTyInt64"];
+  default: llvm_unreachable("Unhandled integer element bitwidth!");
+  }
+}
+
+std::string SVEType::builtin_str() const {
+  std::string S;
+  if (isVoid())
+    return "v";
+
+  if (isVoidPointer())
+    S += "v";
+  else if (!Float)
+    switch (ElementBitwidth) {
+    case 1: S += "b"; break;
+    case 8: S += "c"; break;
+    case 16: S += "s"; break;
+    case 32: S += "i"; break;
+    case 64: S += "Wi"; break;
+    case 128: S += "LLLi"; break;
+    default: llvm_unreachable("Unhandled case!");
+    }
+  else
+    switch (ElementBitwidth) {
+    case 16: S += "h"; break;
+    case 32: S += "f"; break;
+    case 64: S += "d"; break;
+    default: llvm_unreachable("Unhandled case!");
+    }
+
+  if (!isFloat()) {
+    if ((isChar() || isPointer()) && !isVoidPointer()) {
+      // Make chars and typed pointers explicitly signed.
+      if (Signed)
+        S = "S" + S;
+      else if (!Signed)
+        S = "U" + S;
+    } else if (!isVoidPointer() && !Signed) {
+      S = "U" + S;
+    }
+  }
+
+  // Constant indices are "int", but have the "constant expression" modifier.
+  if (isImmediate()) {
+    assert(!isFloat() && "fp immediates are not supported");
+    S = "I" + S;
+  }
+
+  if (isScalar()) {
+    if (Constant) S += "C";
+    if (Pointer) S += "*";
+    return S;
+  }
+
+  assert(isScalableVector() && "Unsupported type");
+  return "q" + utostr(getNumElements() * NumVectors) + S;
+}
+
+void SVEType::applyTypespec() {
+  for (char I : TS) {
+    switch (I) {
+    case 'P':
+      Predicate = true;
+      ElementBitwidth = 1;
+      break;
+    case 'U':
+      Signed = false;
+      break;
+    case 'c':
+      ElementBitwidth = 8;
+      break;
+    case 's':
+      ElementBitwidth = 16;
+      break;
+    case 'i':
+      ElementBitwidth = 32;
+      break;
+    case 'l':
+      ElementBitwidth = 64;
+      break;
+    case 'h':
+      Float = true;
+      ElementBitwidth = 16;
+      break;
+    case 'f':
+      Float = true;
+      ElementBitwidth = 32;
+      break;
+    case 'd':
+      Float = true;
+      ElementBitwidth = 64;
+      break;
+    default:
+      llvm_unreachable("Unhandled type code!");
+    }
+  }
+  assert(ElementBitwidth != ~0U && "Bad element bitwidth!");
+}
+
+void SVEType::applyModifier(char Mod) {
+  switch (Mod) {
+  case 'v':
+    Void = true;
+    break;
+  case 'd':
+    DefaultType = true;
+    break;
+  case 'c':
+    Constant = true;
+    LLVM_FALLTHROUGH;
+  case 'p':
+    Pointer = true;
+    Bitwidth = ElementBitwidth;
+    NumVectors = 0;
+    break;
+  case 'P':
+    Signed = true;
+    Float = false;
+    Predicate = true;
+    Bitwidth = 16;
+    ElementBitwidth = 1;
+    break;
+  default:
+    llvm_unreachable("Unhandled character!");
+  }
+}
+
+
+//===----------------------------------------------------------------------===//
+// Intrinsic implementation
+//===----------------------------------------------------------------------===//
+
+std::string Intrinsic::getBuiltinTypeStr() {
+  std::string S;
+
+  SVEType RetT = getReturnType();
+  // Since the return value must be one type, return a vector type of the
+  // appropriate width which we will bitcast.  An exception is made for
+  // returning structs of 2, 3, or 4 vectors which are returned in a sret-like
+  // fashion, storing them to a pointer arg.
+  if (RetT.getNumVectors() > 1) {
+    S += "vv*"; // void result with void* first argument
+  } else
+    S += RetT.builtin_str();
+
+  for (unsigned I = 0; I < getNumParams(); ++I)
+    S += getParamType(I).builtin_str();
+
+  return S;
+}
+
+std::string Intrinsic::replaceTemplatedArgs(std::string Name, TypeSpec TS,
+                                            std::string Proto) const {
+  std::string Ret = Name;
+  while (Ret.find('{') != std::string::npos) {
+    size_t Pos = Ret.find('{');
+    size_t End = Ret.find('}');
+    unsigned NumChars = End - Pos + 1;
+    assert(NumChars == 3 && "Unexpected template argument");
+
+    SVEType T;
+    char C = Ret[Pos+1];
+    switch(C) {
+    default:
+      llvm_unreachable("Unknown predication specifier");
+    case 'd':
+      T = SVEType(TS, 'd');
+      break;
+    case '0':
+    case '1':
+    case '2':
+    case '3':
+      T = SVEType(TS, Proto[C - '0']);
+      break;
+    }
+
+    // Replace templated arg with the right suffix (e.g. u32)
+    std::string TypeCode;
+    if (T.isInteger())
+      TypeCode = T.isSigned() ? 's' : 'u';
+    else if (T.isPredicateVector())
+      TypeCode = 'b';
+    else
+      TypeCode = 'f';
+    Ret.replace(Pos, NumChars, TypeCode + utostr(T.getElementSizeInBits()));
+  }
+
+  return Ret;
+}
+
+// ACLE function names have a merge style postfix.
+std::string Intrinsic::getMergeSuffix() const {
+  switch (getMergeType()) {
+    default:
+      llvm_unreachable("Unknown predication specifier");
+    case MergeNone:    return "";
+    case MergeAny:
+    case MergeAnyExp:  return "_x";
+    case MergeOp1:     return "_m";
+    case MergeZero:
+    case MergeZeroExp: return "_z";
+  }
+}
+
+std::string Intrinsic::mangleName(ClassKind LocalCK) const {
+  std::string S = getName();
+
+  if (LocalCK == ClassG) {
+    // Remove the square brackets and everything in between.
+    while (S.find("[") != std::string::npos) {
+      auto Start = S.find("[");
+      auto End = S.find(']');
+      S.erase(Start, (End-Start)+1);
+    }
+  } else {
+    // Remove the square brackets.
+    while (S.find("[") != std::string::npos) {
+      auto BrPos = S.find('[');
+      if (BrPos != std::string::npos)
+        S.erase(BrPos, 1);
+      BrPos = S.find(']');
+      if (BrPos != std::string::npos)
+        S.erase(BrPos, 1);
+    }
+  }
+
+  // Replace all {d} like expressions with e.g. 'u32'
+  return replaceTemplatedArgs(S, getBaseTypeSpec(), getProto()) +
+         getMergeSuffix();
+}
+
+void Intrinsic::emitIntrinsic(raw_ostream &OS) const {
+  // Use the preprocessor to 
+  if (getClassKind() != ClassG || getProto().size() <= 1) {
+    OS << "#define " << mangleName(getClassKind())
+       << "(...) __builtin_sve_" << mangleName(ClassS)
+       << "(__VA_ARGS__)\n";
+  } else {
+    llvm_unreachable("Not yet implemented. Overloaded intrinsics will follow "
+                     "in a future patch");
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// SVEEmitter implementation
+//===----------------------------------------------------------------------===//
+void SVEEmitter::createIntrinsic(
+    Record *R, SmallVectorImpl<std::unique_ptr<Intrinsic>> &Out) {
+  StringRef Name = R->getValueAsString("Name");
+  StringRef Proto = R->getValueAsString("Prototype");
+  StringRef Types = R->getValueAsString("Types");
+  StringRef Guard = R->getValueAsString("ArchGuard");
+  StringRef LLVMName = R->getValueAsString("LLVMIntrinsic");
+  int64_t Merge = R->getValueAsInt("Merge");
+  std::vector<Record*> FlagsList = R->getValueAsListOfDefs("Flags");
+
+  int64_t Flags = 0;
+  for (auto FlagRec : FlagsList)
+    Flags |= FlagRec->getValueAsInt("Value");
+  Flags |= R->getValueAsInt("MemEltType") + MemEltTypes["FirstMemEltType"];
+
+  // Extract type specs from string
+  SmallVector<TypeSpec, 8> TypeSpecs;
+  TypeSpec Acc;
+  for (char I : Types) {
+    Acc.push_back(I);
+    if (islower(I)) {
+      TypeSpecs.push_back(TypeSpec(Acc));
+      Acc.clear();
+    }
+  }
+
+  // Remove duplicate type specs.
+  std::sort(TypeSpecs.begin(), TypeSpecs.end());
+  TypeSpecs.erase(std::unique(TypeSpecs.begin(), TypeSpecs.end()),
+                  TypeSpecs.end());
+
+  // Create an Intrinsic for each type spec.
+  for (auto TS : TypeSpecs) {
+    Out.push_back(std::make_unique<Intrinsic>(Name, Proto, Merge,
+                                              LLVMName, Flags, TS, ClassS,
+                                              *this, Guard));
+  }
+}
+
+void SVEEmitter::createHeader(raw_ostream &OS) {
+  OS << "/*===---- arm_sve.h - ARM SVE intrinsics "
+        "-----------------------------------===\n"
+        " *\n"
+        " *\n"
+        " * Part of the LLVM Project, under the Apache License v2.0 with LLVM "
+        "Exceptions.\n"
+        " * See https://llvm.org/LICENSE.txt for license information.\n"
+        " * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception\n"
+        " *\n"
+        " *===-----------------------------------------------------------------"
+        "------===\n"
+        " */\n\n";
+
+  OS << "#ifndef __ARM_SVE_H\n";
+  OS << "#define __ARM_SVE_H\n\n";
+
+  OS << "#if !defined(__ARM_FEATURE_SVE)\n";
+  OS << "#error \"SVE support not enabled\"\n";
+  OS << "#else\n\n";
+
+  OS << "#include <stdint.h>\n\n";
+  OS << "#ifdef  __cplusplus\n";
+  OS << "extern \"C\" {\n";
+  OS << "#else\n";
+  OS << "#include <stdbool.h>\n";
+  OS << "#endif\n\n";
+
+  OS << "typedef __fp16 float16_t;\n";
+  OS << "typedef float float32_t;\n";
+  OS << "typedef double float64_t;\n";
+  OS << "typedef bool bool_t;\n\n";
+
+  OS << "typedef __SVInt8_t svint8_t;\n";
+  OS << "typedef __SVInt16_t svint16_t;\n";
+  OS << "typedef __SVInt32_t svint32_t;\n";
+  OS << "typedef __SVInt64_t svint64_t;\n";
+  OS << "typedef __SVUint8_t svuint8_t;\n";
+  OS << "typedef __SVUint16_t svuint16_t;\n";
+  OS << "typedef __SVUint32_t svuint32_t;\n";
+  OS << "typedef __SVUint64_t svuint64_t;\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n";
+  OS << "typedef __SVFloat32_t svfloat32_t;\n";
+  OS << "typedef __SVFloat64_t svfloat64_t;\n";
+  OS << "typedef __SVBool_t  svbool_t;\n\n";
+
+  SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
+  std::vector<Record *> RV = Records.getAllDerivedDefinitions("Inst");
+  for (auto *R : RV)
+    createIntrinsic(R, Defs);
+
+  // Sort intrinsics in header file by following order/priority:
+  // - Architectural guard (i.e. does it require SVE2 or SVE2_AES)
+  // - Class (is intrinsic overloaded or not)
+  // - Intrinsic name
+  std::stable_sort(
+      Defs.begin(), Defs.end(), [](const std::unique_ptr<Intrinsic> &A,
+                                   const std::unique_ptr<Intrinsic> &B) {
+        return A->getGuard() < B->getGuard() ||
+               (unsigned)A->getClassKind() < (unsigned)B->getClassKind() ||
+               A->getName() < B->getName();
+      });
+
+  StringRef InGuard = "";
+  for (auto &I : Defs) {
+    // Emit #endif/#if pair if needed.
+    if (I->getGuard() != InGuard) {
+      if (!InGuard.empty())
+        OS << "#endif  //" << InGuard << "\n";
+      InGuard = I->getGuard();
+      if (!InGuard.empty())
+        OS << "\n#if " << InGuard << "\n";
+    }
+
+    // Actually emit the intrinsic declaration.
+    I->emitIntrinsic(OS);
+  }
+
+  if (!InGuard.empty())
+    OS << "#endif  //" << InGuard << "\n";
+
+  OS << "#ifdef __cplusplus\n";
+  OS << "} // extern \"C\"\n";
+  OS << "#endif\n\n";
+  OS << "#endif /*__ARM_FEATURE_SVE */\n\n";
+  OS << "#endif /* __ARM_SVE_H */\n";
+}
+
+void SVEEmitter::createBuiltins(raw_ostream &OS) {
+  std::vector<Record *> RV = Records.getAllDerivedDefinitions("Inst");
+  SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
+  for (auto *R : RV)
+    createIntrinsic(R, Defs);
+
+  // The mappings must be sorted based on BuiltinID.
+  llvm::sort(Defs, [](const std::unique_ptr<Intrinsic> &A,
+                      const std::unique_ptr<Intrinsic> &B) {
+    return A->getMangledName() < B->getMangledName();
+  });
+
+  OS << "#ifdef GET_SVE_BUILTINS\n";
+  for (auto &Def : Defs) {
+    // Only create BUILTINs for non-overloaded intrinsics, as overloaded
+    // declarations only live in the header file.
+    if (Def->getClassKind() != ClassG)
+      OS << "BUILTIN(__builtin_sve_" << Def->getMangledName() << ", \""
+         << Def->getBuiltinTypeStr() << "\", \"n\")\n";
+  }
+  OS << "#endif\n\n";
+}
+
+void SVEEmitter::createCodeGenMap(raw_ostream &OS) {
+  std::vector<Record *> RV = Records.getAllDerivedDefinitions("Inst");
+  SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
+  for (auto *R : RV)
+    createIntrinsic(R, Defs);
+
+  // The mappings must be sorted based on BuiltinID.
+  llvm::sort(Defs, [](const std::unique_ptr<Intrinsic> &A,
+                      const std::unique_ptr<Intrinsic> &B) {
+    return A->getMangledName() < B->getMangledName();
+  });
+
+  OS << "#ifdef GET_SVE_LLVM_INTRINSIC_MAP\n";
+  for (auto &Def : Defs) {
+    // Builtins only exist for non-overloaded intrinsics, overloaded
+    // declarations only live in the header file.
+    if (Def->getClassKind() == ClassG)
+      continue;
+
+    uint64_t Flags = Def->getFlags() | getTypeFlags(Def->getBaseType());
+    auto FlagString = std::to_string(Flags);
+
+    std::string LLVMName = Def->getLLVMName();
+    std::string Builtin = Def->getMangledName();
+    if (!LLVMName.empty())
+      OS << "SVEMAP1(" << Builtin << ", " << LLVMName << ", " << FlagString
+         << "),\n";
+    else
+      OS << "SVEMAP2(" << Builtin << ", " << FlagString << "),\n";
+  }
+  OS << "#endif\n\n";
+}
+
+/// Create the SVETypeFlags used in CGBuiltins
+void SVEEmitter::createTypeFlags(raw_ostream &OS) {
+  OS << "#ifdef LLVM_GET_SVE_TYPEFLAGS\n";
+  for (auto &KV : FlagTypes)
+    OS << "const uint64_t " << KV.getKey() << " = " << KV.getValue() << ";\n";
+  OS << "#endif\n\n";
+
+  OS << "#ifdef LLVM_GET_SVE_ELTTYPES\n";
+  for (auto &KV : EltTypes)
+    OS << "  " << KV.getKey() << " = " << KV.getValue() << ",\n";
+  OS << "#endif\n\n";
+
+  OS << "#ifdef LLVM_GET_SVE_MEMELTTYPES\n";
+  for (auto &KV : MemEltTypes)
+    OS << "  " << KV.getKey() << " = " << KV.getValue() << ",\n";
+  OS << "#endif\n\n";
+}
+
+namespace clang {
+void EmitSveHeader(RecordKeeper &Records, raw_ostream &OS) {
+  SVEEmitter(Records).createHeader(OS);
+}
+
+void EmitSveBuiltins(RecordKeeper &Records, raw_ostream &OS) {
+  SVEEmitter(Records).createBuiltins(OS);
+}
+
+void EmitSveBuiltinCG(RecordKeeper &Records, raw_ostream &OS) {
+  SVEEmitter(Records).createCodeGenMap(OS);
+}
+void EmitSveTypeFlags(RecordKeeper &Records, raw_ostream &OS) {
+  SVEEmitter(Records).createTypeFlags(OS);
+}
+
+} // End namespace clang
diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp
index 237afb32e57ea..b4afcfb10dc62 100644
--- a/clang/utils/TableGen/TableGen.cpp
+++ b/clang/utils/TableGen/TableGen.cpp
@@ -71,6 +71,10 @@ enum ActionType {
   GenArmMveBuiltinSema,
   GenArmMveBuiltinCG,
   GenArmMveBuiltinAliases,
+  GenArmSveHeader,
+  GenArmSveBuiltins,
+  GenArmSveBuiltinCG,
+  GenArmSveTypeFlags,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -188,6 +192,14 @@ cl::opt<ActionType> Action(
                    "Generate ARM NEON sema support for clang"),
         clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
                    "Generate ARM NEON tests for clang"),
+        clEnumValN(GenArmSveHeader, "gen-arm-sve-header",
+                   "Generate arm_sve.h for clang"),
+        clEnumValN(GenArmSveBuiltins, "gen-arm-sve-builtins",
+                   "Generate arm_sve_builtins.inc for clang"),
+        clEnumValN(GenArmSveBuiltinCG, "gen-arm-sve-builtin-codegen",
+                   "Generate arm_sve_builtin_cg_map.inc for clang"),
+        clEnumValN(GenArmSveTypeFlags, "gen-arm-sve-typeflags",
+                   "Generate arm_sve_typeflags.inc for clang"),
         clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
                    "Generate arm_mve.h for clang"),
         clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -372,6 +384,18 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   case GenArmMveBuiltinAliases:
     EmitMveBuiltinAliases(Records, OS);
     break;
+  case GenArmSveHeader:
+    EmitSveHeader(Records, OS);
+    break;
+  case GenArmSveBuiltins:
+    EmitSveBuiltins(Records, OS);
+    break;
+  case GenArmSveBuiltinCG:
+    EmitSveBuiltinCG(Records, OS);
+    break;
+  case GenArmSveTypeFlags:
+    EmitSveTypeFlags(Records, OS);
+    break;
   case GenArmCdeHeader:
     EmitCdeHeader(Records, OS);
     break;
diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h
index 1785180689cb1..dfbc3291460a1 100644
--- a/clang/utils/TableGen/TableGenBackends.h
+++ b/clang/utils/TableGen/TableGenBackends.h
@@ -91,6 +91,11 @@ void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
+void EmitSveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitSveBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitSveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_netbsd.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_netbsd.cpp
index 722cb1feb5607..fb3b69795af16 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_netbsd.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_netbsd.cpp
@@ -161,9 +161,50 @@
 #include <net/slip.h>
 #include <netbt/hci.h>
 #include <netinet/ip_compat.h>
+#if __has_include(<netinet/ip_fil.h>)
 #include <netinet/ip_fil.h>
 #include <netinet/ip_nat.h>
 #include <netinet/ip_proxy.h>
+#else
+/* Fallback for MKIPFILTER=no */
+
+typedef struct ap_control {
+  char apc_label[16];
+  char apc_config[16];
+  unsigned char apc_p;
+  unsigned long apc_cmd;
+  unsigned long apc_arg;
+  void *apc_data;
+  size_t apc_dsize;
+} ap_ctl_t;
+
+typedef struct ipftq {
+  ipfmutex_t ifq_lock;
+  unsigned int ifq_ttl;
+  void *ifq_head;
+  void **ifq_tail;
+  void *ifq_next;
+  void **ifq_pnext;
+  int ifq_ref;
+  unsigned int ifq_flags;
+} ipftq_t;
+
+typedef struct ipfobj {
+  uint32_t ipfo_rev;
+  uint32_t ipfo_size;
+  void *ipfo_ptr;
+  int ipfo_type;
+  int ipfo_offset;
+  int ipfo_retval;
+  unsigned char ipfo_xxxpad[28];
+} ipfobj_t;
+
+#define SIOCADNAT _IOW('r', 60, struct ipfobj)
+#define SIOCRMNAT _IOW('r', 61, struct ipfobj)
+#define SIOCGNATS _IOWR('r', 62, struct ipfobj)
+#define SIOCGNATL _IOWR('r', 63, struct ipfobj)
+#define SIOCPURGENAT _IOWR('r', 100, struct ipfobj)
+#endif
 #include <netinet6/in6_var.h>
 #include <netinet6/nd6.h>
 #include <netsmb/smb_dev.h>
diff --git a/compiler-rt/lib/sanitizer_common/tests/sanitizer_pthread_wrappers.h b/compiler-rt/lib/sanitizer_common/tests/sanitizer_pthread_wrappers.h
index f806ee1ea4f56..5c8d3c27dc90c 100644
--- a/compiler-rt/lib/sanitizer_common/tests/sanitizer_pthread_wrappers.h
+++ b/compiler-rt/lib/sanitizer_common/tests/sanitizer_pthread_wrappers.h
@@ -35,9 +35,9 @@ struct PthreadHelperCreateThreadInfo {
 inline DWORD WINAPI PthreadHelperThreadProc(void *arg) {
   PthreadHelperCreateThreadInfo *start_data =
       reinterpret_cast<PthreadHelperCreateThreadInfo*>(arg);
-  void *ret = (start_data->start_routine)(start_data->arg);
+  (start_data->start_routine)(start_data->arg);
   delete start_data;
-  return (DWORD)ret;
+  return 0;
 }
 
 inline void PTHREAD_CREATE(pthread_t *thread, void *attr,
@@ -60,7 +60,7 @@ inline void PTHREAD_JOIN(pthread_t thread, void **value_ptr) {
 
 inline void pthread_exit(void *retval) {
   ASSERT_EQ(0, retval) << "Nonzero retval is not supported yet.";
-  ExitThread((DWORD)retval);
+  ExitThread(0);
 }
 #endif  // _WIN32
 
diff --git a/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp b/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp
index ae65dd3fd9951..fdda7013fe5c8 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp
@@ -41,6 +41,10 @@
 #include <errno.h>
 #include <sched.h>
 
+#if __has_feature(ptrauth_calls)
+#include <ptrauth.h>
+#endif
+
 namespace __tsan {
 
 #if !SANITIZER_GO
@@ -274,6 +278,10 @@ void InitializePlatform() {
 uptr ExtractLongJmpSp(uptr *env) {
   uptr mangled_sp = env[LONG_JMP_SP_ENV_SLOT];
   uptr sp = mangled_sp ^ longjmp_xor_key;
+#if __has_feature(ptrauth_calls)
+  sp = (uptr)ptrauth_auth_data((void *)sp, ptrauth_key_asdb,
+                               ptrauth_string_discriminator("sp"));
+#endif
   return sp;
 }
 
diff --git a/compiler-rt/test/asan/TestCases/Posix/no-fd.cpp b/compiler-rt/test/asan/TestCases/Posix/no-fd.cpp
index ee355b5dc1017..6f8b2f4e15b0a 100644
--- a/compiler-rt/test/asan/TestCases/Posix/no-fd.cpp
+++ b/compiler-rt/test/asan/TestCases/Posix/no-fd.cpp
@@ -6,8 +6,9 @@
 
 // This test closes the 0, 1, and 2 file descriptors before an exec() and relies
 // on them remaining closed across an execve(). This is not the case on newer
-// versions of Android.
-// UNSUPPORTED: android
+// versions of Android. On PPC with ASLR turned on, this fails when linked with
+// lld - see https://bugs.llvm.org/show_bug.cgi?id=45076.
+// UNSUPPORTED: android, powerpc
 
 #include <assert.h>
 #include <stdio.h>
diff --git a/debuginfo-tests/dexter/dex/dextIR/DextIR.py b/debuginfo-tests/dexter/dex/dextIR/DextIR.py
index 7638e8b4ab787..b82c2bab56dec 100644
--- a/debuginfo-tests/dexter/dex/dextIR/DextIR.py
+++ b/debuginfo-tests/dexter/dex/dextIR/DextIR.py
@@ -102,6 +102,10 @@ def _get_new_step_kind(self, context, step):
             frame_step = self._get_prev_step_in_this_frame(step)
             prev_step = frame_step if frame_step is not None else prev_step
 
+        # If we're missing line numbers to compare then the step kind has to be UNKNOWN.
+        if prev_step.current_location.lineno is None or step.current_location.lineno is None:
+            return StepKind.UNKNOWN
+
         # We're in the same func as prev step, check lineo.
         if prev_step.current_location.lineno > step.current_location.lineno:
             return StepKind.VERTICAL_BACKWARD
diff --git a/debuginfo-tests/llgdb-tests/apple-accel.cpp b/debuginfo-tests/llgdb-tests/apple-accel.cpp
index a125c57428c4e..2705c29a5fb2d 100644
--- a/debuginfo-tests/llgdb-tests/apple-accel.cpp
+++ b/debuginfo-tests/llgdb-tests/apple-accel.cpp
@@ -4,9 +4,9 @@
 // These sections are going to be retired in DWARF 5, so we hardcode
 // the DWARF version in the tests.
 // RUN: %clang %s %target_itanium_abi_host_triple -gdwarf-2 -O0 -c -g -o %t-ex
-// RUN: llvm-objdump -section-headers %t-ex | FileCheck %s
+// RUN: llvm-objdump --section-headers %t-ex | FileCheck %s
 // RUN: %clang %s %target_itanium_abi_host_triple -gdwarf-4 -O0 -c -g -o %t-ex
-// RUN: llvm-objdump -section-headers %t-ex | FileCheck %s
+// RUN: llvm-objdump --section-headers %t-ex | FileCheck %s
 
 // A function in a different section forces the compiler to create the
 // __debug_ranges section.
diff --git a/libc/AOR_v20.02/Makefile b/libc/AOR_v20.02/Makefile
new file mode 100644
index 0000000000000..53e0245f82c40
--- /dev/null
+++ b/libc/AOR_v20.02/Makefile
@@ -0,0 +1,90 @@
+# Makefile - requires GNU make
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+srcdir = .
+prefix = /usr
+bindir = $(prefix)/bin
+libdir = $(prefix)/lib
+includedir = $(prefix)/include
+
+# Configure these in config.mk, do not make changes in this file.
+SUBS = math string networking
+HOST_CC = cc
+HOST_CFLAGS = -std=c99 -O2
+HOST_LDFLAGS =
+HOST_LDLIBS =
+EMULATOR =
+CPPFLAGS =
+CFLAGS = -std=c99 -O2
+CFLAGS_SHARED = -fPIC
+CFLAGS_ALL = -Ibuild/include $(CPPFLAGS) $(CFLAGS)
+LDFLAGS =
+LDLIBS =
+AR = $(CROSS_COMPILE)ar
+RANLIB = $(CROSS_COMPILE)ranlib
+INSTALL = install
+
+all:
+
+-include config.mk
+
+$(foreach sub,$(SUBS),$(eval include $(srcdir)/$(sub)/Dir.mk))
+
+# Required targets of subproject foo:
+#   all-foo
+#   check-foo
+#   clean-foo
+#   install-foo
+# Required make variables of subproject foo:
+#   foo-files: Built files (all in build/).
+# Make variables used by subproject foo:
+#   foo-...: Variables defined in foo/Dir.mk or by config.mk.
+
+all: $(SUBS:%=all-%)
+
+ALL_FILES = $(foreach sub,$(SUBS),$($(sub)-files))
+DIRS = $(sort $(patsubst %/,%,$(dir $(ALL_FILES))))
+$(ALL_FILES): | $(DIRS)
+$(DIRS):
+	mkdir -p $@
+
+$(filter %.os,$(ALL_FILES)): CFLAGS_ALL += $(CFLAGS_SHARED)
+
+build/%.o: $(srcdir)/%.S
+	$(CC) $(CFLAGS_ALL) -c -o $@ $<
+
+build/%.o: $(srcdir)/%.c
+	$(CC) $(CFLAGS_ALL) -c -o $@ $<
+
+build/%.os: $(srcdir)/%.S
+	$(CC) $(CFLAGS_ALL) -c -o $@ $<
+
+build/%.os: $(srcdir)/%.c
+	$(CC) $(CFLAGS_ALL) -c -o $@ $<
+
+clean: $(SUBS:%=clean-%)
+	rm -rf build
+
+distclean: clean
+	rm -f config.mk
+
+$(DESTDIR)$(bindir)/%: build/bin/%
+	$(INSTALL) -D $< $@
+
+$(DESTDIR)$(libdir)/%.so: build/lib/%.so
+	$(INSTALL) -D $< $@
+
+$(DESTDIR)$(libdir)/%: build/lib/%
+	$(INSTALL) -m 644 -D $< $@
+
+$(DESTDIR)$(includedir)/%: build/include/%
+	$(INSTALL) -m 644 -D $< $@
+
+install: $(SUBS:%=install-%)
+
+check: $(SUBS:%=check-%)
+
+.PHONY: all clean distclean install check
diff --git a/libc/AOR_v20.02/README.md b/libc/AOR_v20.02/README.md
new file mode 100644
index 0000000000000..860f90ebe26dd
--- /dev/null
+++ b/libc/AOR_v20.02/README.md
@@ -0,0 +1,6 @@
+This directory contains Arm's contribution of their optimized routines as
+initially uploaded to https://reviews.llvm.org/D75355. Going forward, parts
+of the implementations from this directory will be moved over to the
+appropriate place in the LLVM-libc tree. This will be done over many patches,
+all of which will go through the normal LLVM code review practice, and follow
+the LLVM-libc implementation standards.
diff --git a/libc/AOR_v20.02/config.mk b/libc/AOR_v20.02/config.mk
new file mode 100644
index 0000000000000..6808df93519e0
--- /dev/null
+++ b/libc/AOR_v20.02/config.mk
@@ -0,0 +1,70 @@
+# Example config.mk
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+# Subprojects to build
+# For now, LLVM-libc project will focus only "math" functions.
+SUBS = math # string networking
+
+# Target architecture: aarch64, arm or x86_64
+# For now, LLVM-libc project will focus on x86_64 only.
+ARCH = x86_64
+
+# Compiler for the target
+CC = $(CROSS_COMPILE)gcc
+CFLAGS = -std=c99 -pipe -O3
+CFLAGS += -Wall -Wno-missing-braces
+CFLAGS += -Werror=implicit-function-declaration
+
+# Used for test case generator that is executed on the host
+HOST_CC = gcc
+HOST_CFLAGS = -std=c99 -O2
+HOST_CFLAGS += -Wall -Wno-unused-function
+
+# Enable debug info.
+HOST_CFLAGS += -g
+CFLAGS += -g
+
+# Optimize the shared libraries on aarch64 assuming they fit in 1M.
+#CFLAGS_SHARED = -fPIC -mcmodel=tiny
+
+# Use for cross compilation with gcc.
+#CROSS_COMPILE = aarch64-none-linux-gnu-
+
+# Use with cross testing.
+#EMULATOR = qemu-aarch64-static
+#EMULATOR = sh -c 'scp $$1 user@host:/dir && ssh user@host /dir/"$$@"' --
+
+# Additional flags for subprojects.
+math-cflags =
+math-ldlibs =
+math-ulpflags =
+math-testflags =
+string-cflags =
+networking-cflags =
+
+# Use if mpfr is available on the target for ulp error checking.
+#math-ldlibs += -lmpfr -lgmp
+#math-cflags += -DUSE_MPFR
+
+# Use with gcc.
+math-cflags += -frounding-math -fexcess-precision=standard -fno-stack-protector
+math-cflags += -ffp-contract=fast -fno-math-errno
+
+# Use with clang.
+#math-cflags += -ffp-contract=fast
+
+# Disable vector math code
+#math-cflags += -DWANT_VMATH=0
+
+# Disable fenv checks
+#math-ulpflags = -q -f
+#math-testflags = -nostatus
+
+# Enable assertion checks.
+#networking-cflags += -DWANT_ASSERT
+
+# Avoid auto-vectorization of scalar code and unroll loops
+networking-cflags += -O2 -fno-tree-vectorize -funroll-loops
diff --git a/libc/AOR_v20.02/config.mk.dist b/libc/AOR_v20.02/config.mk.dist
new file mode 100644
index 0000000000000..240d4b6f4b4c2
--- /dev/null
+++ b/libc/AOR_v20.02/config.mk.dist
@@ -0,0 +1,68 @@
+# Example config.mk
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+# Subprojects to build
+SUBS = math string networking
+
+# Target architecture: aarch64, arm or x86_64
+ARCH = aarch64
+
+# Compiler for the target
+CC = $(CROSS_COMPILE)gcc
+CFLAGS = -std=c99 -pipe -O3
+CFLAGS += -Wall -Wno-missing-braces
+CFLAGS += -Werror=implicit-function-declaration
+
+# Used for test case generator that is executed on the host
+HOST_CC = gcc
+HOST_CFLAGS = -std=c99 -O2
+HOST_CFLAGS += -Wall -Wno-unused-function
+
+# Enable debug info.
+HOST_CFLAGS += -g
+CFLAGS += -g
+
+# Optimize the shared libraries on aarch64 assuming they fit in 1M.
+#CFLAGS_SHARED = -fPIC -mcmodel=tiny
+
+# Use for cross compilation with gcc.
+#CROSS_COMPILE = aarch64-none-linux-gnu-
+
+# Use with cross testing.
+#EMULATOR = qemu-aarch64-static
+#EMULATOR = sh -c 'scp $$1 user@host:/dir && ssh user@host /dir/"$$@"' --
+
+# Additional flags for subprojects.
+math-cflags =
+math-ldlibs =
+math-ulpflags =
+math-testflags =
+string-cflags =
+networking-cflags =
+
+# Use if mpfr is available on the target for ulp error checking.
+#math-ldlibs += -lmpfr -lgmp
+#math-cflags += -DUSE_MPFR
+
+# Use with gcc.
+math-cflags += -frounding-math -fexcess-precision=standard -fno-stack-protector
+math-cflags += -ffp-contract=fast -fno-math-errno
+
+# Use with clang.
+#math-cflags += -ffp-contract=fast
+
+# Disable vector math code
+#math-cflags += -DWANT_VMATH=0
+
+# Disable fenv checks
+#math-ulpflags = -q -f
+#math-testflags = -nostatus
+
+# Enable assertion checks.
+#networking-cflags += -DWANT_ASSERT
+
+# Avoid auto-vectorization of scalar code and unroll loops
+networking-cflags += -O2 -fno-tree-vectorize -funroll-loops
diff --git a/libc/AOR_v20.02/math/Dir.mk b/libc/AOR_v20.02/math/Dir.mk
new file mode 100644
index 0000000000000..6be9115e86b08
--- /dev/null
+++ b/libc/AOR_v20.02/math/Dir.mk
@@ -0,0 +1,111 @@
+# Makefile fragment - requires GNU make
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+S := $(srcdir)/math
+B := build/math
+
+math-lib-srcs := $(wildcard $(S)/*.[cS])
+math-test-srcs := \
+	$(S)/test/mathtest.c \
+	$(S)/test/mathbench.c \
+	$(S)/test/ulp.c \
+
+math-test-host-srcs := $(wildcard $(S)/test/rtest/*.[cS])
+
+math-includes := $(patsubst $(S)/%,build/%,$(wildcard $(S)/include/*.h))
+
+math-libs := \
+	build/lib/libmathlib.so \
+	build/lib/libmathlib.a \
+
+math-tools := \
+	build/bin/mathtest \
+	build/bin/mathbench \
+	build/bin/mathbench_libc \
+	build/bin/runulp.sh \
+	build/bin/ulp \
+
+math-host-tools := \
+	build/bin/rtest \
+
+math-lib-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(math-lib-srcs)))
+math-test-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(math-test-srcs)))
+math-host-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(math-test-host-srcs)))
+math-target-objs := $(math-lib-objs) $(math-test-objs)
+math-objs := $(math-target-objs) $(math-target-objs:%.o=%.os) $(math-host-objs)
+
+math-files := \
+	$(math-objs) \
+	$(math-libs) \
+	$(math-tools) \
+	$(math-host-tools) \
+	$(math-includes) \
+
+all-math: $(math-libs) $(math-tools) $(math-includes)
+
+$(math-objs): $(math-includes)
+$(math-objs): CFLAGS_ALL += $(math-cflags)
+$(B)/test/mathtest.o: CFLAGS_ALL += -fmath-errno
+$(math-host-objs): CC = $(HOST_CC)
+$(math-host-objs): CFLAGS_ALL = $(HOST_CFLAGS)
+
+$(B)/test/ulp.o: $(S)/test/ulp.h
+
+build/lib/libmathlib.so: $(math-lib-objs:%.o=%.os)
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -shared -o $@ $^
+
+build/lib/libmathlib.a: $(math-lib-objs)
+	rm -f $@
+	$(AR) rc $@ $^
+	$(RANLIB) $@
+
+$(math-host-tools): HOST_LDLIBS += -lm -lmpfr -lmpc
+$(math-tools): LDLIBS += $(math-ldlibs) -lm
+
+build/bin/rtest: $(math-host-objs)
+	$(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(HOST_LDLIBS)
+
+build/bin/mathtest: $(B)/test/mathtest.o build/lib/libmathlib.a
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -static -o $@ $^ $(LDLIBS)
+
+build/bin/mathbench: $(B)/test/mathbench.o build/lib/libmathlib.a
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -static -o $@ $^ $(LDLIBS)
+
+# This is not ideal, but allows custom symbols in mathbench to get resolved.
+build/bin/mathbench_libc: $(B)/test/mathbench.o build/lib/libmathlib.a
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -static -o $@ $< $(LDLIBS) -lc build/lib/libmathlib.a -lm
+
+build/bin/ulp: $(B)/test/ulp.o build/lib/libmathlib.a
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -static -o $@ $^ $(LDLIBS)
+
+build/include/%.h: $(S)/include/%.h
+	cp $< $@
+
+build/bin/%.sh: $(S)/test/%.sh
+	cp $< $@
+
+math-tests := $(wildcard $(S)/test/testcases/directed/*.tst)
+math-rtests := $(wildcard $(S)/test/testcases/random/*.tst)
+
+check-math-test: $(math-tools)
+	cat $(math-tests) | $(EMULATOR) build/bin/mathtest $(math-testflags)
+
+check-math-rtest: $(math-host-tools) $(math-tools)
+	cat $(math-rtests) | build/bin/rtest | $(EMULATOR) build/bin/mathtest $(math-testflags)
+
+check-math-ulp: $(math-tools)
+	ULPFLAGS="$(math-ulpflags)" build/bin/runulp.sh $(EMULATOR)
+
+check-math: check-math-test check-math-rtest check-math-ulp
+
+install-math: \
+ $(math-libs:build/lib/%=$(DESTDIR)$(libdir)/%) \
+ $(math-includes:build/include/%=$(DESTDIR)$(includedir)/%)
+
+clean-math:
+	rm -f $(math-files)
+
+.PHONY: all-math check-math-test check-math-rtest check-math-ulp check-math install-math clean-math
diff --git a/libc/AOR_v20.02/math/cosf.c b/libc/AOR_v20.02/math/cosf.c
new file mode 100644
index 0000000000000..1ab98a1dd60fb
--- /dev/null
+++ b/libc/AOR_v20.02/math/cosf.c
@@ -0,0 +1,64 @@
+/*
+ * Single-precision cos function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <math.h>
+#include "math_config.h"
+#include "sincosf.h"
+
+/* Fast cosf implementation.  Worst-case ULP is 0.5607, maximum relative
+   error is 0.5303 * 2^-23.  A single-step range reduction is used for
+   small values.  Large inputs have their range reduced using fast integer
+   arithmetic.  */
+float
+cosf (float y)
+{
+  double x = y;
+  double s;
+  int n;
+  const sincos_t *p = &__sincosf_table[0];
+
+  if (abstop12 (y) < abstop12 (pio4))
+    {
+      double x2 = x * x;
+
+      if (unlikely (abstop12 (y) < abstop12 (0x1p-12f)))
+	return 1.0f;
+
+      return sinf_poly (x, x2, p, 1);
+    }
+  else if (likely (abstop12 (y) < abstop12 (120.0f)))
+    {
+      x = reduce_fast (x, p, &n);
+
+      /* Setup the signs for sin and cos.  */
+      s = p->sign[n & 3];
+
+      if (n & 2)
+	p = &__sincosf_table[1];
+
+      return sinf_poly (x * s, x * x, p, n ^ 1);
+    }
+  else if (abstop12 (y) < abstop12 (INFINITY))
+    {
+      uint32_t xi = asuint (y);
+      int sign = xi >> 31;
+
+      x = reduce_large (xi, &n);
+
+      /* Setup signs for sin and cos - include original sign.  */
+      s = p->sign[(n + sign) & 3];
+
+      if ((n + sign) & 2)
+	p = &__sincosf_table[1];
+
+      return sinf_poly (x * s, x * x, p, n ^ 1);
+    }
+  else
+    return __math_invalidf (y);
+}
diff --git a/libc/AOR_v20.02/math/exp.c b/libc/AOR_v20.02/math/exp.c
new file mode 100644
index 0000000000000..d0996023188ca
--- /dev/null
+++ b/libc/AOR_v20.02/math/exp.c
@@ -0,0 +1,177 @@
+/*
+ * Double-precision e^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <float.h>
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+#define N (1 << EXP_TABLE_BITS)
+#define InvLn2N __exp_data.invln2N
+#define NegLn2hiN __exp_data.negln2hiN
+#define NegLn2loN __exp_data.negln2loN
+#define Shift __exp_data.shift
+#define T __exp_data.tab
+#define C2 __exp_data.poly[5 - EXP_POLY_ORDER]
+#define C3 __exp_data.poly[6 - EXP_POLY_ORDER]
+#define C4 __exp_data.poly[7 - EXP_POLY_ORDER]
+#define C5 __exp_data.poly[8 - EXP_POLY_ORDER]
+#define C6 __exp_data.poly[9 - EXP_POLY_ORDER]
+
+/* Handle cases that may overflow or underflow when computing the result that
+   is scale*(1+TMP) without intermediate rounding.  The bit representation of
+   scale is in SBITS, however it has a computed exponent that may have
+   overflown into the sign bit so that needs to be adjusted before using it as
+   a double.  (int32_t)KI is the k used in the argument reduction and exponent
+   adjustment of scale, positive k here means the result may overflow and
+   negative k means the result may underflow.  */
+static inline double
+specialcase (double_t tmp, uint64_t sbits, uint64_t ki)
+{
+  double_t scale, y;
+
+  if ((ki & 0x80000000) == 0)
+    {
+      /* k > 0, the exponent of scale might have overflowed by <= 460.  */
+      sbits -= 1009ull << 52;
+      scale = asdouble (sbits);
+      y = 0x1p1009 * (scale + scale * tmp);
+      return check_oflow (eval_as_double (y));
+    }
+  /* k < 0, need special care in the subnormal range.  */
+  sbits += 1022ull << 52;
+  scale = asdouble (sbits);
+  y = scale + scale * tmp;
+  if (y < 1.0)
+    {
+      /* Round y to the right precision before scaling it into the subnormal
+	 range to avoid double rounding that can cause 0.5+E/2 ulp error where
+	 E is the worst-case ulp error outside the subnormal range.  So this
+	 is only useful if the goal is better than 1 ulp worst-case error.  */
+      double_t hi, lo;
+      lo = scale - y + scale * tmp;
+      hi = 1.0 + y;
+      lo = 1.0 - hi + y + lo;
+      y = eval_as_double (hi + lo) - 1.0;
+      /* Avoid -0.0 with downward rounding.  */
+      if (WANT_ROUNDING && y == 0.0)
+	y = 0.0;
+      /* The underflow exception needs to be signaled explicitly.  */
+      force_eval_double (opt_barrier_double (0x1p-1022) * 0x1p-1022);
+    }
+  y = 0x1p-1022 * y;
+  return check_uflow (eval_as_double (y));
+}
+
+/* Top 12 bits of a double (sign and exponent bits).  */
+static inline uint32_t
+top12 (double x)
+{
+  return asuint64 (x) >> 52;
+}
+
+/* Computes exp(x+xtail) where |xtail| < 2^-8/N and |xtail| <= |x|.
+   If hastail is 0 then xtail is assumed to be 0 too.  */
+static inline double
+exp_inline (double x, double xtail, int hastail)
+{
+  uint32_t abstop;
+  uint64_t ki, idx, top, sbits;
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t kd, z, r, r2, scale, tail, tmp;
+
+  abstop = top12 (x) & 0x7ff;
+  if (unlikely (abstop - top12 (0x1p-54) >= top12 (512.0) - top12 (0x1p-54)))
+    {
+      if (abstop - top12 (0x1p-54) >= 0x80000000)
+	/* Avoid spurious underflow for tiny x.  */
+	/* Note: 0 is common input.  */
+	return WANT_ROUNDING ? 1.0 + x : 1.0;
+      if (abstop >= top12 (1024.0))
+	{
+	  if (asuint64 (x) == asuint64 (-INFINITY))
+	    return 0.0;
+	  if (abstop >= top12 (INFINITY))
+	    return 1.0 + x;
+	  if (asuint64 (x) >> 63)
+	    return __math_uflow (0);
+	  else
+	    return __math_oflow (0);
+	}
+      /* Large x is special cased below.  */
+      abstop = 0;
+    }
+
+  /* exp(x) = 2^(k/N) * exp(r), with exp(r) in [2^(-1/2N),2^(1/2N)].  */
+  /* x = ln2/N*k + r, with int k and r in [-ln2/2N, ln2/2N].  */
+  z = InvLn2N * x;
+#if TOINT_INTRINSICS
+  kd = roundtoint (z);
+  ki = converttoint (z);
+#elif EXP_USE_TOINT_NARROW
+  /* z - kd is in [-0.5-2^-16, 0.5] in all rounding modes.  */
+  kd = eval_as_double (z + Shift);
+  ki = asuint64 (kd) >> 16;
+  kd = (double_t) (int32_t) ki;
+#else
+  /* z - kd is in [-1, 1] in non-nearest rounding modes.  */
+  kd = eval_as_double (z + Shift);
+  ki = asuint64 (kd);
+  kd -= Shift;
+#endif
+  r = x + kd * NegLn2hiN + kd * NegLn2loN;
+  /* The code assumes 2^-200 < |xtail| < 2^-8/N.  */
+  if (hastail)
+    r += xtail;
+  /* 2^(k/N) ~= scale * (1 + tail).  */
+  idx = 2 * (ki % N);
+  top = ki << (52 - EXP_TABLE_BITS);
+  tail = asdouble (T[idx]);
+  /* This is only a valid scale when -1023*N < k < 1024*N.  */
+  sbits = T[idx + 1] + top;
+  /* exp(x) = 2^(k/N) * exp(r) ~= scale + scale * (tail + exp(r) - 1).  */
+  /* Evaluation is optimized assuming superscalar pipelined execution.  */
+  r2 = r * r;
+  /* Without fma the worst case error is 0.25/N ulp larger.  */
+  /* Worst case error is less than 0.5+1.11/N+(abs poly error * 2^53) ulp.  */
+#if EXP_POLY_ORDER == 4
+  tmp = tail + r + r2 * C2 + r * r2 * (C3 + r * C4);
+#elif EXP_POLY_ORDER == 5
+  tmp = tail + r + r2 * (C2 + r * C3) + r2 * r2 * (C4 + r * C5);
+#elif EXP_POLY_ORDER == 6
+  tmp = tail + r + r2 * (0.5 + r * C3) + r2 * r2 * (C4 + r * C5 + r2 * C6);
+#endif
+  if (unlikely (abstop == 0))
+    return specialcase (tmp, sbits, ki);
+  scale = asdouble (sbits);
+  /* Note: tmp == 0 or |tmp| > 2^-200 and scale > 2^-739, so there
+     is no spurious underflow here even without fma.  */
+  return eval_as_double (scale + scale * tmp);
+}
+
+double
+exp (double x)
+{
+  return exp_inline (x, 0, 0);
+}
+
+/* May be useful for implementing pow where more than double
+   precision input is needed.  */
+double
+__exp_dd (double x, double xtail)
+{
+  return exp_inline (x, xtail, 1);
+}
+#if USE_GLIBC_ABI
+strong_alias (exp, __exp_finite)
+hidden_alias (exp, __ieee754_exp)
+hidden_alias (__exp_dd, __exp1)
+# if LDBL_MANT_DIG == 53
+long double expl (long double x) { return exp (x); }
+# endif
+#endif
diff --git a/libc/AOR_v20.02/math/exp2.c b/libc/AOR_v20.02/math/exp2.c
new file mode 100644
index 0000000000000..53296ab7c5815
--- /dev/null
+++ b/libc/AOR_v20.02/math/exp2.c
@@ -0,0 +1,144 @@
+/*
+ * Double-precision 2^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <float.h>
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+#define N (1 << EXP_TABLE_BITS)
+#define Shift __exp_data.exp2_shift
+#define T __exp_data.tab
+#define C1 __exp_data.exp2_poly[0]
+#define C2 __exp_data.exp2_poly[1]
+#define C3 __exp_data.exp2_poly[2]
+#define C4 __exp_data.exp2_poly[3]
+#define C5 __exp_data.exp2_poly[4]
+#define C6 __exp_data.exp2_poly[5]
+
+/* Handle cases that may overflow or underflow when computing the result that
+   is scale*(1+TMP) without intermediate rounding.  The bit representation of
+   scale is in SBITS, however it has a computed exponent that may have
+   overflown into the sign bit so that needs to be adjusted before using it as
+   a double.  (int32_t)KI is the k used in the argument reduction and exponent
+   adjustment of scale, positive k here means the result may overflow and
+   negative k means the result may underflow.  */
+static inline double
+specialcase (double_t tmp, uint64_t sbits, uint64_t ki)
+{
+  double_t scale, y;
+
+  if ((ki & 0x80000000) == 0)
+    {
+      /* k > 0, the exponent of scale might have overflowed by 1.  */
+      sbits -= 1ull << 52;
+      scale = asdouble (sbits);
+      y = 2 * (scale + scale * tmp);
+      return check_oflow (eval_as_double (y));
+    }
+  /* k < 0, need special care in the subnormal range.  */
+  sbits += 1022ull << 52;
+  scale = asdouble (sbits);
+  y = scale + scale * tmp;
+  if (y < 1.0)
+    {
+      /* Round y to the right precision before scaling it into the subnormal
+	 range to avoid double rounding that can cause 0.5+E/2 ulp error where
+	 E is the worst-case ulp error outside the subnormal range.  So this
+	 is only useful if the goal is better than 1 ulp worst-case error.  */
+      double_t hi, lo;
+      lo = scale - y + scale * tmp;
+      hi = 1.0 + y;
+      lo = 1.0 - hi + y + lo;
+      y = eval_as_double (hi + lo) - 1.0;
+      /* Avoid -0.0 with downward rounding.  */
+      if (WANT_ROUNDING && y == 0.0)
+	y = 0.0;
+      /* The underflow exception needs to be signaled explicitly.  */
+      force_eval_double (opt_barrier_double (0x1p-1022) * 0x1p-1022);
+    }
+  y = 0x1p-1022 * y;
+  return check_uflow (eval_as_double (y));
+}
+
+/* Top 12 bits of a double (sign and exponent bits).  */
+static inline uint32_t
+top12 (double x)
+{
+  return asuint64 (x) >> 52;
+}
+
+double
+exp2 (double x)
+{
+  uint32_t abstop;
+  uint64_t ki, idx, top, sbits;
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t kd, r, r2, scale, tail, tmp;
+
+  abstop = top12 (x) & 0x7ff;
+  if (unlikely (abstop - top12 (0x1p-54) >= top12 (512.0) - top12 (0x1p-54)))
+    {
+      if (abstop - top12 (0x1p-54) >= 0x80000000)
+	/* Avoid spurious underflow for tiny x.  */
+	/* Note: 0 is common input.  */
+	return WANT_ROUNDING ? 1.0 + x : 1.0;
+      if (abstop >= top12 (1024.0))
+	{
+	  if (asuint64 (x) == asuint64 (-INFINITY))
+	    return 0.0;
+	  if (abstop >= top12 (INFINITY))
+	    return 1.0 + x;
+	  if (!(asuint64 (x) >> 63))
+	    return __math_oflow (0);
+	  else if (asuint64 (x) >= asuint64 (-1075.0))
+	    return __math_uflow (0);
+	}
+      if (2 * asuint64 (x) > 2 * asuint64 (928.0))
+	/* Large x is special cased below.  */
+	abstop = 0;
+    }
+
+  /* exp2(x) = 2^(k/N) * 2^r, with 2^r in [2^(-1/2N),2^(1/2N)].  */
+  /* x = k/N + r, with int k and r in [-1/2N, 1/2N].  */
+  kd = eval_as_double (x + Shift);
+  ki = asuint64 (kd); /* k.  */
+  kd -= Shift; /* k/N for int k.  */
+  r = x - kd;
+  /* 2^(k/N) ~= scale * (1 + tail).  */
+  idx = 2 * (ki % N);
+  top = ki << (52 - EXP_TABLE_BITS);
+  tail = asdouble (T[idx]);
+  /* This is only a valid scale when -1023*N < k < 1024*N.  */
+  sbits = T[idx + 1] + top;
+  /* exp2(x) = 2^(k/N) * 2^r ~= scale + scale * (tail + 2^r - 1).  */
+  /* Evaluation is optimized assuming superscalar pipelined execution.  */
+  r2 = r * r;
+  /* Without fma the worst case error is 0.5/N ulp larger.  */
+  /* Worst case error is less than 0.5+0.86/N+(abs poly error * 2^53) ulp.  */
+#if EXP2_POLY_ORDER == 4
+  tmp = tail + r * C1 + r2 * C2 + r * r2 * (C3 + r * C4);
+#elif EXP2_POLY_ORDER == 5
+  tmp = tail + r * C1 + r2 * (C2 + r * C3) + r2 * r2 * (C4 + r * C5);
+#elif EXP2_POLY_ORDER == 6
+  tmp = tail + r * C1 + r2 * (0.5 + r * C3) + r2 * r2 * (C4 + r * C5 + r2 * C6);
+#endif
+  if (unlikely (abstop == 0))
+    return specialcase (tmp, sbits, ki);
+  scale = asdouble (sbits);
+  /* Note: tmp == 0 or |tmp| > 2^-65 and scale > 2^-928, so there
+     is no spurious underflow here even without fma.  */
+  return eval_as_double (scale + scale * tmp);
+}
+#if USE_GLIBC_ABI
+strong_alias (exp2, __exp2_finite)
+hidden_alias (exp2, __ieee754_exp2)
+# if LDBL_MANT_DIG == 53
+long double exp2l (long double x) { return exp2 (x); }
+# endif
+#endif
diff --git a/libc/AOR_v20.02/math/exp2f.c b/libc/AOR_v20.02/math/exp2f.c
new file mode 100644
index 0000000000000..4259e29777e11
--- /dev/null
+++ b/libc/AOR_v20.02/math/exp2f.c
@@ -0,0 +1,81 @@
+/*
+ * Single-precision 2^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+/*
+EXP2F_TABLE_BITS = 5
+EXP2F_POLY_ORDER = 3
+
+ULP error: 0.502 (nearest rounding.)
+Relative error: 1.69 * 2^-34 in [-1/64, 1/64] (before rounding.)
+Wrong count: 168353 (all nearest rounding wrong results with fma.)
+Non-nearest ULP error: 1 (rounded ULP error)
+*/
+
+#define N (1 << EXP2F_TABLE_BITS)
+#define T __exp2f_data.tab
+#define C __exp2f_data.poly
+#define SHIFT __exp2f_data.shift_scaled
+
+static inline uint32_t
+top12 (float x)
+{
+  return asuint (x) >> 20;
+}
+
+float
+exp2f (float x)
+{
+  uint32_t abstop;
+  uint64_t ki, t;
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t kd, xd, z, r, r2, y, s;
+
+  xd = (double_t) x;
+  abstop = top12 (x) & 0x7ff;
+  if (unlikely (abstop >= top12 (128.0f)))
+    {
+      /* |x| >= 128 or x is nan.  */
+      if (asuint (x) == asuint (-INFINITY))
+	return 0.0f;
+      if (abstop >= top12 (INFINITY))
+	return x + x;
+      if (x > 0.0f)
+	return __math_oflowf (0);
+      if (x <= -150.0f)
+	return __math_uflowf (0);
+#if WANT_ERRNO_UFLOW
+      if (x < -149.0f)
+	return __math_may_uflowf (0);
+#endif
+    }
+
+  /* x = k/N + r with r in [-1/(2N), 1/(2N)] and int k.  */
+  kd = eval_as_double (xd + SHIFT);
+  ki = asuint64 (kd);
+  kd -= SHIFT; /* k/N for int k.  */
+  r = xd - kd;
+
+  /* exp2(x) = 2^(k/N) * 2^r ~= s * (C0*r^3 + C1*r^2 + C2*r + 1) */
+  t = T[ki % N];
+  t += ki << (52 - EXP2F_TABLE_BITS);
+  s = asdouble (t);
+  z = C[0] * r + C[1];
+  r2 = r * r;
+  y = C[2] * r + 1;
+  y = z * r2 + y;
+  y = y * s;
+  return eval_as_float (y);
+}
+#if USE_GLIBC_ABI
+strong_alias (exp2f, __exp2f_finite)
+hidden_alias (exp2f, __ieee754_exp2f)
+#endif
diff --git a/libc/AOR_v20.02/math/exp2f_data.c b/libc/AOR_v20.02/math/exp2f_data.c
new file mode 100644
index 0000000000000..0630750063281
--- /dev/null
+++ b/libc/AOR_v20.02/math/exp2f_data.c
@@ -0,0 +1,79 @@
+/*
+ * Shared data between expf, exp2f and powf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#define N (1 << EXP2F_TABLE_BITS)
+
+const struct exp2f_data __exp2f_data = {
+  /* tab[i] = uint(2^(i/N)) - (i << 52-BITS)
+     used for computing 2^(k/N) for an int |k| < 150 N as
+     double(tab[k%N] + (k << 52-BITS)) */
+  .tab = {
+#if N == 8
+0x3ff0000000000000, 0x3fef72b83c7d517b, 0x3fef06fe0a31b715, 0x3feebfdad5362a27,
+0x3feea09e667f3bcd, 0x3feeace5422aa0db, 0x3feee89f995ad3ad, 0x3fef5818dcfba487,
+#elif N == 16
+0x3ff0000000000000, 0x3fefb5586cf9890f, 0x3fef72b83c7d517b, 0x3fef387a6e756238,
+0x3fef06fe0a31b715, 0x3feedea64c123422, 0x3feebfdad5362a27, 0x3feeab07dd485429,
+0x3feea09e667f3bcd, 0x3feea11473eb0187, 0x3feeace5422aa0db, 0x3feec49182a3f090,
+0x3feee89f995ad3ad, 0x3fef199bdd85529c, 0x3fef5818dcfba487, 0x3fefa4afa2a490da,
+#elif N == 32
+0x3ff0000000000000, 0x3fefd9b0d3158574, 0x3fefb5586cf9890f, 0x3fef9301d0125b51,
+0x3fef72b83c7d517b, 0x3fef54873168b9aa, 0x3fef387a6e756238, 0x3fef1e9df51fdee1,
+0x3fef06fe0a31b715, 0x3feef1a7373aa9cb, 0x3feedea64c123422, 0x3feece086061892d,
+0x3feebfdad5362a27, 0x3feeb42b569d4f82, 0x3feeab07dd485429, 0x3feea47eb03a5585,
+0x3feea09e667f3bcd, 0x3fee9f75e8ec5f74, 0x3feea11473eb0187, 0x3feea589994cce13,
+0x3feeace5422aa0db, 0x3feeb737b0cdc5e5, 0x3feec49182a3f090, 0x3feed503b23e255d,
+0x3feee89f995ad3ad, 0x3feeff76f2fb5e47, 0x3fef199bdd85529c, 0x3fef3720dcef9069,
+0x3fef5818dcfba487, 0x3fef7c97337b9b5f, 0x3fefa4afa2a490da, 0x3fefd0765b6e4540,
+#elif N == 64
+0x3ff0000000000000, 0x3fefec9a3e778061, 0x3fefd9b0d3158574, 0x3fefc74518759bc8,
+0x3fefb5586cf9890f, 0x3fefa3ec32d3d1a2, 0x3fef9301d0125b51, 0x3fef829aaea92de0,
+0x3fef72b83c7d517b, 0x3fef635beb6fcb75, 0x3fef54873168b9aa, 0x3fef463b88628cd6,
+0x3fef387a6e756238, 0x3fef2b4565e27cdd, 0x3fef1e9df51fdee1, 0x3fef1285a6e4030b,
+0x3fef06fe0a31b715, 0x3feefc08b26416ff, 0x3feef1a7373aa9cb, 0x3feee7db34e59ff7,
+0x3feedea64c123422, 0x3feed60a21f72e2a, 0x3feece086061892d, 0x3feec6a2b5c13cd0,
+0x3feebfdad5362a27, 0x3feeb9b2769d2ca7, 0x3feeb42b569d4f82, 0x3feeaf4736b527da,
+0x3feeab07dd485429, 0x3feea76f15ad2148, 0x3feea47eb03a5585, 0x3feea23882552225,
+0x3feea09e667f3bcd, 0x3fee9fb23c651a2f, 0x3fee9f75e8ec5f74, 0x3fee9feb564267c9,
+0x3feea11473eb0187, 0x3feea2f336cf4e62, 0x3feea589994cce13, 0x3feea8d99b4492ed,
+0x3feeace5422aa0db, 0x3feeb1ae99157736, 0x3feeb737b0cdc5e5, 0x3feebd829fde4e50,
+0x3feec49182a3f090, 0x3feecc667b5de565, 0x3feed503b23e255d, 0x3feede6b5579fdbf,
+0x3feee89f995ad3ad, 0x3feef3a2b84f15fb, 0x3feeff76f2fb5e47, 0x3fef0c1e904bc1d2,
+0x3fef199bdd85529c, 0x3fef27f12e57d14b, 0x3fef3720dcef9069, 0x3fef472d4a07897c,
+0x3fef5818dcfba487, 0x3fef69e603db3285, 0x3fef7c97337b9b5f, 0x3fef902ee78b3ff6,
+0x3fefa4afa2a490da, 0x3fefba1bee615a27, 0x3fefd0765b6e4540, 0x3fefe7c1819e90d8,
+#endif
+  },
+  .shift_scaled = 0x1.8p+52 / N,
+  .poly = {
+#if N == 8
+  0x1.c6a00335106e2p-5, 0x1.ec0c313449f55p-3, 0x1.62e431111f69fp-1,
+#elif N == 16
+  0x1.c6ac6aa313963p-5, 0x1.ebfff4532d9bap-3, 0x1.62e43001bc49fp-1,
+#elif N == 32
+  0x1.c6af84b912394p-5, 0x1.ebfce50fac4f3p-3, 0x1.62e42ff0c52d6p-1,
+#elif N == 64
+  0x1.c6b04b4221b2ap-5, 0x1.ebfc213e184d7p-3, 0x1.62e42fefb5b7fp-1,
+#endif
+  },
+  .shift = 0x1.8p+52,
+  .invln2_scaled = 0x1.71547652b82fep+0 * N,
+  .poly_scaled = {
+#if N == 8
+  0x1.c6a00335106e2p-5/N/N/N, 0x1.ec0c313449f55p-3/N/N, 0x1.62e431111f69fp-1/N,
+#elif N == 16
+  0x1.c6ac6aa313963p-5/N/N/N, 0x1.ebfff4532d9bap-3/N/N, 0x1.62e43001bc49fp-1/N,
+#elif N == 32
+  0x1.c6af84b912394p-5/N/N/N, 0x1.ebfce50fac4f3p-3/N/N, 0x1.62e42ff0c52d6p-1/N,
+#elif N == 64
+  0x1.c6b04b4221b2ap-5/N/N/N, 0x1.ebfc213e184d7p-3/N/N, 0x1.62e42fefb5b7fp-1/N,
+#endif
+  },
+};
diff --git a/libc/AOR_v20.02/math/exp_data.c b/libc/AOR_v20.02/math/exp_data.c
new file mode 100644
index 0000000000000..682eee860070b
--- /dev/null
+++ b/libc/AOR_v20.02/math/exp_data.c
@@ -0,0 +1,1121 @@
+/*
+ * Shared data between exp, exp2 and pow.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#define N (1 << EXP_TABLE_BITS)
+
+const struct exp_data __exp_data = {
+// N/ln2
+.invln2N = 0x1.71547652b82fep0 * N,
+// -ln2/N
+#if N == 64
+.negln2hiN = -0x1.62e42fefa0000p-7,
+.negln2loN = -0x1.cf79abc9e3b3ap-46,
+#elif N == 128
+.negln2hiN = -0x1.62e42fefa0000p-8,
+.negln2loN = -0x1.cf79abc9e3b3ap-47,
+#elif N == 256
+.negln2hiN = -0x1.62e42fefc0000p-9,
+.negln2loN = 0x1.c610ca86c3899p-45,
+#elif N == 512
+.negln2hiN = -0x1.62e42fef80000p-10,
+.negln2loN = -0x1.1cf79abc9e3b4p-45,
+#endif
+// Used for rounding when !TOINT_INTRINSICS
+#if EXP_USE_TOINT_NARROW
+.shift = 0x1800000000.8p0,
+#else
+.shift = 0x1.8p52,
+#endif
+// exp polynomial coefficients.
+.poly = {
+#if N == 64 && EXP_POLY_ORDER == 5 && !EXP_POLY_WIDE
+// abs error: 1.5543*2^-60
+// ulp error: 0.529 (0.533 without fma)
+// if |x| < ln2/128+eps
+// abs error if |x| < ln2/64: 1.7157*2^-50
+0x1.fffffffffdbcdp-2,
+0x1.555555555444cp-3,
+0x1.555573c6a9f7dp-5,
+0x1.1111266d28935p-7,
+#elif N == 64 && EXP_POLY_ORDER == 6 && EXP_POLY_WIDE
+// abs error: 1.6735*2^-64
+// ulp error: 0.518 (0.522 without fma)
+// if |x| < ln2/64
+0x1.5555555548f9ap-3,
+0x1.555555554bf5dp-5,
+0x1.11115b75f0f4dp-7,
+0x1.6c171a6b6303ep-10,
+#elif N == 128 && EXP_POLY_ORDER == 5 && !EXP_POLY_WIDE
+// abs error: 1.555*2^-66
+// ulp error: 0.509 (0.511 without fma)
+// if |x| < ln2/256+eps
+// abs error if |x| < ln2/256+0x1p-15: 1.09*2^-65
+// abs error if |x| < ln2/128: 1.7145*2^-56
+0x1.ffffffffffdbdp-2,
+0x1.555555555543cp-3,
+0x1.55555cf172b91p-5,
+0x1.1111167a4d017p-7,
+#elif N == 128 && EXP_POLY_ORDER == 5 && EXP_POLY_WIDE
+// abs error: 1.5542*2^-60
+// ulp error: 0.521 (0.523 without fma)
+// if |x| < ln2/128
+0x1.fffffffffdbcep-2,
+0x1.55555555543c2p-3,
+0x1.555573c64f2e3p-5,
+0x1.111126b4eff73p-7,
+#elif N == 128 && EXP_POLY_ORDER == 6 && EXP_POLY_WIDE
+// abs error: 1.6861*2^-71
+// ulp error: 0.509 (0.511 without fma)
+// if |x| < ln2/128
+0x1.55555555548fdp-3,
+0x1.555555555658fp-5,
+0x1.111123a859bb6p-7,
+0x1.6c16ba6920cabp-10,
+#elif N == 256 && EXP_POLY_ORDER == 4 && !EXP_POLY_WIDE
+// abs error: 1.43*2^-58
+// ulp error: 0.549 (0.550 without fma)
+// if |x| < ln2/512
+0x1p0, // unused
+0x1.fffffffffffd4p-2,
+0x1.5555571d6ef9p-3,
+0x1.5555576a5adcep-5,
+#elif N == 256 && EXP_POLY_ORDER == 5 && EXP_POLY_WIDE
+// abs error: 1.5547*2^-66
+// ulp error: 0.505 (0.506 without fma)
+// if |x| < ln2/256
+0x1.ffffffffffdbdp-2,
+0x1.555555555543cp-3,
+0x1.55555cf16e1edp-5,
+0x1.1111167a4b553p-7,
+#elif N == 512 && EXP_POLY_ORDER == 4 && !EXP_POLY_WIDE
+// abs error: 1.4300*2^-63
+// ulp error: 0.504
+// if |x| < ln2/1024
+// abs error if |x| < ln2/512: 1.0689*2^-55
+0x1p0, // unused
+0x1.ffffffffffffdp-2,
+0x1.555555c75bb6p-3,
+0x1.555555dec04a8p-5,
+#endif
+},
+.exp2_shift = 0x1.8p52 / N,
+// exp2 polynomial coefficients.
+.exp2_poly = {
+#if N == 64 && EXP2_POLY_ORDER == 6 && EXP2_POLY_WIDE
+// abs error: 1.3054*2^-63
+// ulp error: 0.515
+// if |x| < 1/64
+0x1.62e42fefa39efp-1,
+0x1.ebfbdff82c58fp-3,
+0x1.c6b08d7045cf1p-5,
+0x1.3b2ab6fb8fd0ep-7,
+0x1.5d884afec48d7p-10,
+0x1.43097dc684ae1p-13,
+#elif N == 128 && EXP2_POLY_ORDER == 5 && !EXP2_POLY_WIDE
+// abs error: 1.2195*2^-65
+// ulp error: 0.507 (0.511 without fma)
+// if |x| < 1/256
+// abs error if |x| < 1/128: 1.9941*2^-56
+0x1.62e42fefa39efp-1,
+0x1.ebfbdff82c424p-3,
+0x1.c6b08d70cf4b5p-5,
+0x1.3b2abd24650ccp-7,
+0x1.5d7e09b4e3a84p-10,
+#elif N == 256 && EXP2_POLY_ORDER == 5 && EXP2_POLY_WIDE
+// abs error: 1.2195*2^-65
+// ulp error: 0.504 (0.508 without fma)
+// if |x| < 1/256
+0x1.62e42fefa39efp-1,
+0x1.ebfbdff82c424p-3,
+0x1.c6b08d70cf4b5p-5,
+0x1.3b2abd24650ccp-7,
+0x1.5d7e09b4e3a84p-10,
+#elif N == 512 && EXP2_POLY_ORDER == 4 && !EXP2_POLY_WIDE
+// abs error: 1.4411*2^-64
+// ulp error: 0.5024 (0.5063 without fma)
+// if |x| < 1/1024
+// abs error if |x| < 1/512: 1.9430*2^-56
+0x1.62e42fefa39ecp-1,
+0x1.ebfbdff82c58bp-3,
+0x1.c6b08e46de41fp-5,
+0x1.3b2ab786ee1dap-7,
+#endif
+},
+// 2^(k/N) ~= H[k]*(1 + T[k]) for int k in [0,N)
+// tab[2*k] = asuint64(T[k])
+// tab[2*k+1] = asuint64(H[k]) - (k << 52)/N
+.tab = {
+#if N == 64
+0x0, 0x3ff0000000000000,
+0xbc7160139cd8dc5d, 0x3fefec9a3e778061,
+0x3c8cd2523567f613, 0x3fefd9b0d3158574,
+0x3c60f74e61e6c861, 0x3fefc74518759bc8,
+0x3c979aa65d837b6d, 0x3fefb5586cf9890f,
+0x3c3ebe3d702f9cd1, 0x3fefa3ec32d3d1a2,
+0xbc9556522a2fbd0e, 0x3fef9301d0125b51,
+0xbc91c923b9d5f416, 0x3fef829aaea92de0,
+0xbc801b15eaa59348, 0x3fef72b83c7d517b,
+0x3c8b898c3f1353bf, 0x3fef635beb6fcb75,
+0x3c9aecf73e3a2f60, 0x3fef54873168b9aa,
+0x3c8a6f4144a6c38d, 0x3fef463b88628cd6,
+0x3c968efde3a8a894, 0x3fef387a6e756238,
+0x3c80472b981fe7f2, 0x3fef2b4565e27cdd,
+0x3c82f7e16d09ab31, 0x3fef1e9df51fdee1,
+0x3c8b3782720c0ab4, 0x3fef1285a6e4030b,
+0x3c834d754db0abb6, 0x3fef06fe0a31b715,
+0x3c8fdd395dd3f84a, 0x3feefc08b26416ff,
+0xbc924aedcc4b5068, 0x3feef1a7373aa9cb,
+0xbc71d1e83e9436d2, 0x3feee7db34e59ff7,
+0x3c859f48a72a4c6d, 0x3feedea64c123422,
+0xbc58a78f4817895b, 0x3feed60a21f72e2a,
+0x3c4363ed60c2ac11, 0x3feece086061892d,
+0x3c6ecce1daa10379, 0x3feec6a2b5c13cd0,
+0x3c7690cebb7aafb0, 0x3feebfdad5362a27,
+0xbc8f94340071a38e, 0x3feeb9b2769d2ca7,
+0xbc78dec6bd0f385f, 0x3feeb42b569d4f82,
+0x3c93350518fdd78e, 0x3feeaf4736b527da,
+0x3c9063e1e21c5409, 0x3feeab07dd485429,
+0x3c9432e62b64c035, 0x3feea76f15ad2148,
+0xbc8c33c53bef4da8, 0x3feea47eb03a5585,
+0xbc93cedd78565858, 0x3feea23882552225,
+0xbc93b3efbf5e2228, 0x3feea09e667f3bcd,
+0xbc6367efb86da9ee, 0x3fee9fb23c651a2f,
+0xbc781f647e5a3ecf, 0x3fee9f75e8ec5f74,
+0xbc8619321e55e68a, 0x3fee9feb564267c9,
+0xbc7b32dcb94da51d, 0x3feea11473eb0187,
+0x3c65ebe1abd66c55, 0x3feea2f336cf4e62,
+0xbc9369b6f13b3734, 0x3feea589994cce13,
+0xbc94d450d872576e, 0x3feea8d99b4492ed,
+0x3c8db72fc1f0eab4, 0x3feeace5422aa0db,
+0x3c7bf68359f35f44, 0x3feeb1ae99157736,
+0xbc5da9b88b6c1e29, 0x3feeb737b0cdc5e5,
+0xbc92434322f4f9aa, 0x3feebd829fde4e50,
+0x3c71affc2b91ce27, 0x3feec49182a3f090,
+0xbc87c50422622263, 0x3feecc667b5de565,
+0xbc91bbd1d3bcbb15, 0x3feed503b23e255d,
+0x3c8469846e735ab3, 0x3feede6b5579fdbf,
+0x3c8c1a7792cb3387, 0x3feee89f995ad3ad,
+0xbc55c3d956dcaeba, 0x3feef3a2b84f15fb,
+0xbc68d6f438ad9334, 0x3feeff76f2fb5e47,
+0x3c74ffd70a5fddcd, 0x3fef0c1e904bc1d2,
+0x3c736eae30af0cb3, 0x3fef199bdd85529c,
+0x3c84e08fd10959ac, 0x3fef27f12e57d14b,
+0x3c676b2c6c921968, 0x3fef3720dcef9069,
+0xbc8fad5d3ffffa6f, 0x3fef472d4a07897c,
+0x3c74a385a63d07a7, 0x3fef5818dcfba487,
+0x3c8e5a50d5c192ac, 0x3fef69e603db3285,
+0xbc82d52107b43e1f, 0x3fef7c97337b9b5f,
+0x3c74b604603a88d3, 0x3fef902ee78b3ff6,
+0xbc8ff7128fd391f0, 0x3fefa4afa2a490da,
+0x3c8ec3bc41aa2008, 0x3fefba1bee615a27,
+0x3c8a64a931d185ee, 0x3fefd0765b6e4540,
+0x3c77893b4d91cd9d, 0x3fefe7c1819e90d8,
+#elif N == 128
+0x0, 0x3ff0000000000000,
+0x3c9b3b4f1a88bf6e, 0x3feff63da9fb3335,
+0xbc7160139cd8dc5d, 0x3fefec9a3e778061,
+0xbc905e7a108766d1, 0x3fefe315e86e7f85,
+0x3c8cd2523567f613, 0x3fefd9b0d3158574,
+0xbc8bce8023f98efa, 0x3fefd06b29ddf6de,
+0x3c60f74e61e6c861, 0x3fefc74518759bc8,
+0x3c90a3e45b33d399, 0x3fefbe3ecac6f383,
+0x3c979aa65d837b6d, 0x3fefb5586cf9890f,
+0x3c8eb51a92fdeffc, 0x3fefac922b7247f7,
+0x3c3ebe3d702f9cd1, 0x3fefa3ec32d3d1a2,
+0xbc6a033489906e0b, 0x3fef9b66affed31b,
+0xbc9556522a2fbd0e, 0x3fef9301d0125b51,
+0xbc5080ef8c4eea55, 0x3fef8abdc06c31cc,
+0xbc91c923b9d5f416, 0x3fef829aaea92de0,
+0x3c80d3e3e95c55af, 0x3fef7a98c8a58e51,
+0xbc801b15eaa59348, 0x3fef72b83c7d517b,
+0xbc8f1ff055de323d, 0x3fef6af9388c8dea,
+0x3c8b898c3f1353bf, 0x3fef635beb6fcb75,
+0xbc96d99c7611eb26, 0x3fef5be084045cd4,
+0x3c9aecf73e3a2f60, 0x3fef54873168b9aa,
+0xbc8fe782cb86389d, 0x3fef4d5022fcd91d,
+0x3c8a6f4144a6c38d, 0x3fef463b88628cd6,
+0x3c807a05b0e4047d, 0x3fef3f49917ddc96,
+0x3c968efde3a8a894, 0x3fef387a6e756238,
+0x3c875e18f274487d, 0x3fef31ce4fb2a63f,
+0x3c80472b981fe7f2, 0x3fef2b4565e27cdd,
+0xbc96b87b3f71085e, 0x3fef24dfe1f56381,
+0x3c82f7e16d09ab31, 0x3fef1e9df51fdee1,
+0xbc3d219b1a6fbffa, 0x3fef187fd0dad990,
+0x3c8b3782720c0ab4, 0x3fef1285a6e4030b,
+0x3c6e149289cecb8f, 0x3fef0cafa93e2f56,
+0x3c834d754db0abb6, 0x3fef06fe0a31b715,
+0x3c864201e2ac744c, 0x3fef0170fc4cd831,
+0x3c8fdd395dd3f84a, 0x3feefc08b26416ff,
+0xbc86a3803b8e5b04, 0x3feef6c55f929ff1,
+0xbc924aedcc4b5068, 0x3feef1a7373aa9cb,
+0xbc9907f81b512d8e, 0x3feeecae6d05d866,
+0xbc71d1e83e9436d2, 0x3feee7db34e59ff7,
+0xbc991919b3ce1b15, 0x3feee32dc313a8e5,
+0x3c859f48a72a4c6d, 0x3feedea64c123422,
+0xbc9312607a28698a, 0x3feeda4504ac801c,
+0xbc58a78f4817895b, 0x3feed60a21f72e2a,
+0xbc7c2c9b67499a1b, 0x3feed1f5d950a897,
+0x3c4363ed60c2ac11, 0x3feece086061892d,
+0x3c9666093b0664ef, 0x3feeca41ed1d0057,
+0x3c6ecce1daa10379, 0x3feec6a2b5c13cd0,
+0x3c93ff8e3f0f1230, 0x3feec32af0d7d3de,
+0x3c7690cebb7aafb0, 0x3feebfdad5362a27,
+0x3c931dbdeb54e077, 0x3feebcb299fddd0d,
+0xbc8f94340071a38e, 0x3feeb9b2769d2ca7,
+0xbc87deccdc93a349, 0x3feeb6daa2cf6642,
+0xbc78dec6bd0f385f, 0x3feeb42b569d4f82,
+0xbc861246ec7b5cf6, 0x3feeb1a4ca5d920f,
+0x3c93350518fdd78e, 0x3feeaf4736b527da,
+0x3c7b98b72f8a9b05, 0x3feead12d497c7fd,
+0x3c9063e1e21c5409, 0x3feeab07dd485429,
+0x3c34c7855019c6ea, 0x3feea9268a5946b7,
+0x3c9432e62b64c035, 0x3feea76f15ad2148,
+0xbc8ce44a6199769f, 0x3feea5e1b976dc09,
+0xbc8c33c53bef4da8, 0x3feea47eb03a5585,
+0xbc845378892be9ae, 0x3feea34634ccc320,
+0xbc93cedd78565858, 0x3feea23882552225,
+0x3c5710aa807e1964, 0x3feea155d44ca973,
+0xbc93b3efbf5e2228, 0x3feea09e667f3bcd,
+0xbc6a12ad8734b982, 0x3feea012750bdabf,
+0xbc6367efb86da9ee, 0x3fee9fb23c651a2f,
+0xbc80dc3d54e08851, 0x3fee9f7df9519484,
+0xbc781f647e5a3ecf, 0x3fee9f75e8ec5f74,
+0xbc86ee4ac08b7db0, 0x3fee9f9a48a58174,
+0xbc8619321e55e68a, 0x3fee9feb564267c9,
+0x3c909ccb5e09d4d3, 0x3feea0694fde5d3f,
+0xbc7b32dcb94da51d, 0x3feea11473eb0187,
+0x3c94ecfd5467c06b, 0x3feea1ed0130c132,
+0x3c65ebe1abd66c55, 0x3feea2f336cf4e62,
+0xbc88a1c52fb3cf42, 0x3feea427543e1a12,
+0xbc9369b6f13b3734, 0x3feea589994cce13,
+0xbc805e843a19ff1e, 0x3feea71a4623c7ad,
+0xbc94d450d872576e, 0x3feea8d99b4492ed,
+0x3c90ad675b0e8a00, 0x3feeaac7d98a6699,
+0x3c8db72fc1f0eab4, 0x3feeace5422aa0db,
+0xbc65b6609cc5e7ff, 0x3feeaf3216b5448c,
+0x3c7bf68359f35f44, 0x3feeb1ae99157736,
+0xbc93091fa71e3d83, 0x3feeb45b0b91ffc6,
+0xbc5da9b88b6c1e29, 0x3feeb737b0cdc5e5,
+0xbc6c23f97c90b959, 0x3feeba44cbc8520f,
+0xbc92434322f4f9aa, 0x3feebd829fde4e50,
+0xbc85ca6cd7668e4b, 0x3feec0f170ca07ba,
+0x3c71affc2b91ce27, 0x3feec49182a3f090,
+0x3c6dd235e10a73bb, 0x3feec86319e32323,
+0xbc87c50422622263, 0x3feecc667b5de565,
+0x3c8b1c86e3e231d5, 0x3feed09bec4a2d33,
+0xbc91bbd1d3bcbb15, 0x3feed503b23e255d,
+0x3c90cc319cee31d2, 0x3feed99e1330b358,
+0x3c8469846e735ab3, 0x3feede6b5579fdbf,
+0xbc82dfcd978e9db4, 0x3feee36bbfd3f37a,
+0x3c8c1a7792cb3387, 0x3feee89f995ad3ad,
+0xbc907b8f4ad1d9fa, 0x3feeee07298db666,
+0xbc55c3d956dcaeba, 0x3feef3a2b84f15fb,
+0xbc90a40e3da6f640, 0x3feef9728de5593a,
+0xbc68d6f438ad9334, 0x3feeff76f2fb5e47,
+0xbc91eee26b588a35, 0x3fef05b030a1064a,
+0x3c74ffd70a5fddcd, 0x3fef0c1e904bc1d2,
+0xbc91bdfbfa9298ac, 0x3fef12c25bd71e09,
+0x3c736eae30af0cb3, 0x3fef199bdd85529c,
+0x3c8ee3325c9ffd94, 0x3fef20ab5fffd07a,
+0x3c84e08fd10959ac, 0x3fef27f12e57d14b,
+0x3c63cdaf384e1a67, 0x3fef2f6d9406e7b5,
+0x3c676b2c6c921968, 0x3fef3720dcef9069,
+0xbc808a1883ccb5d2, 0x3fef3f0b555dc3fa,
+0xbc8fad5d3ffffa6f, 0x3fef472d4a07897c,
+0xbc900dae3875a949, 0x3fef4f87080d89f2,
+0x3c74a385a63d07a7, 0x3fef5818dcfba487,
+0xbc82919e2040220f, 0x3fef60e316c98398,
+0x3c8e5a50d5c192ac, 0x3fef69e603db3285,
+0x3c843a59ac016b4b, 0x3fef7321f301b460,
+0xbc82d52107b43e1f, 0x3fef7c97337b9b5f,
+0xbc892ab93b470dc9, 0x3fef864614f5a129,
+0x3c74b604603a88d3, 0x3fef902ee78b3ff6,
+0x3c83c5ec519d7271, 0x3fef9a51fbc74c83,
+0xbc8ff7128fd391f0, 0x3fefa4afa2a490da,
+0xbc8dae98e223747d, 0x3fefaf482d8e67f1,
+0x3c8ec3bc41aa2008, 0x3fefba1bee615a27,
+0x3c842b94c3a9eb32, 0x3fefc52b376bba97,
+0x3c8a64a931d185ee, 0x3fefd0765b6e4540,
+0xbc8e37bae43be3ed, 0x3fefdbfdad9cbe14,
+0x3c77893b4d91cd9d, 0x3fefe7c1819e90d8,
+0x3c5305c14160cc89, 0x3feff3c22b8f71f1,
+#elif N == 256
+0x0, 0x3ff0000000000000,
+0xbc84e82fc61851ac, 0x3feffb1afa5abcbf,
+0x3c9b3b4f1a88bf6e, 0x3feff63da9fb3335,
+0xbc82985dd8521d32, 0x3feff168143b0281,
+0xbc7160139cd8dc5d, 0x3fefec9a3e778061,
+0x3c651e617061bfbd, 0x3fefe7d42e11bbcc,
+0xbc905e7a108766d1, 0x3fefe315e86e7f85,
+0x3c845fad437fa426, 0x3fefde5f72f654b1,
+0x3c8cd2523567f613, 0x3fefd9b0d3158574,
+0xbc954529642b232f, 0x3fefd50a0e3c1f89,
+0xbc8bce8023f98efa, 0x3fefd06b29ddf6de,
+0x3c8293708ef5c32e, 0x3fefcbd42b72a836,
+0x3c60f74e61e6c861, 0x3fefc74518759bc8,
+0xbc95b9280905b2a4, 0x3fefc2bdf66607e0,
+0x3c90a3e45b33d399, 0x3fefbe3ecac6f383,
+0x3c84f31f32c4b7e7, 0x3fefb9c79b1f3919,
+0x3c979aa65d837b6d, 0x3fefb5586cf9890f,
+0x3c9407fb30d06420, 0x3fefb0f145e46c85,
+0x3c8eb51a92fdeffc, 0x3fefac922b7247f7,
+0xbc9a5d04b3b9911b, 0x3fefa83b23395dec,
+0x3c3ebe3d702f9cd1, 0x3fefa3ec32d3d1a2,
+0xbc937a01f0739546, 0x3fef9fa55fdfa9c5,
+0xbc6a033489906e0b, 0x3fef9b66affed31b,
+0x3c8b8268b04ef0a5, 0x3fef973028d7233e,
+0xbc9556522a2fbd0e, 0x3fef9301d0125b51,
+0xbc9ac46e44a2ebcc, 0x3fef8edbab5e2ab6,
+0xbc5080ef8c4eea55, 0x3fef8abdc06c31cc,
+0xbc65704e90c9f860, 0x3fef86a814f204ab,
+0xbc91c923b9d5f416, 0x3fef829aaea92de0,
+0xbc897cea57e46280, 0x3fef7e95934f312e,
+0x3c80d3e3e95c55af, 0x3fef7a98c8a58e51,
+0x3c56f01429e2b9d2, 0x3fef76a45471c3c2,
+0xbc801b15eaa59348, 0x3fef72b83c7d517b,
+0x3c6e653b2459034b, 0x3fef6ed48695bbc0,
+0xbc8f1ff055de323d, 0x3fef6af9388c8dea,
+0x3c92cc7ea345b7dc, 0x3fef672658375d2f,
+0x3c8b898c3f1353bf, 0x3fef635beb6fcb75,
+0x3c957bfb2876ea9e, 0x3fef5f99f8138a1c,
+0xbc96d99c7611eb26, 0x3fef5be084045cd4,
+0x3c8cdc1873af2155, 0x3fef582f95281c6b,
+0x3c9aecf73e3a2f60, 0x3fef54873168b9aa,
+0xbc9493684653a131, 0x3fef50e75eb44027,
+0xbc8fe782cb86389d, 0x3fef4d5022fcd91d,
+0xbc98e2899077520a, 0x3fef49c18438ce4d,
+0x3c8a6f4144a6c38d, 0x3fef463b88628cd6,
+0x3c9120fcd4f59273, 0x3fef42be3578a819,
+0x3c807a05b0e4047d, 0x3fef3f49917ddc96,
+0x3c89b788c188c9b8, 0x3fef3bdda27912d1,
+0x3c968efde3a8a894, 0x3fef387a6e756238,
+0x3c877afbca90ef84, 0x3fef351ffb82140a,
+0x3c875e18f274487d, 0x3fef31ce4fb2a63f,
+0x3c91512f082876ee, 0x3fef2e85711ece75,
+0x3c80472b981fe7f2, 0x3fef2b4565e27cdd,
+0x3c9a02f0c7d75ec6, 0x3fef280e341ddf29,
+0xbc96b87b3f71085e, 0x3fef24dfe1f56381,
+0xbc803297e78260bf, 0x3fef21ba7591bb70,
+0x3c82f7e16d09ab31, 0x3fef1e9df51fdee1,
+0xbc95b77e5ccd9fbf, 0x3fef1b8a66d10f13,
+0xbc3d219b1a6fbffa, 0x3fef187fd0dad990,
+0xbc91e75c40b4251e, 0x3fef157e39771b2f,
+0x3c8b3782720c0ab4, 0x3fef1285a6e4030b,
+0x3c98a911f1f7785a, 0x3fef0f961f641589,
+0x3c6e149289cecb8f, 0x3fef0cafa93e2f56,
+0xbc61e7c998db7dbb, 0x3fef09d24abd886b,
+0x3c834d754db0abb6, 0x3fef06fe0a31b715,
+0x3c85425c11faadf4, 0x3fef0432edeeb2fd,
+0x3c864201e2ac744c, 0x3fef0170fc4cd831,
+0xbc979517a03e2847, 0x3feefeb83ba8ea32,
+0x3c8fdd395dd3f84a, 0x3feefc08b26416ff,
+0xbc800e2a46da4bee, 0x3feef96266e3fa2d,
+0xbc86a3803b8e5b04, 0x3feef6c55f929ff1,
+0xbc87430803972b34, 0x3feef431a2de883b,
+0xbc924aedcc4b5068, 0x3feef1a7373aa9cb,
+0xbc954de30ae02d94, 0x3feeef26231e754a,
+0xbc9907f81b512d8e, 0x3feeecae6d05d866,
+0xbc94f2487e1c03ec, 0x3feeea401b7140ef,
+0xbc71d1e83e9436d2, 0x3feee7db34e59ff7,
+0x3c914a5432fcb2f4, 0x3feee57fbfec6cf4,
+0xbc991919b3ce1b15, 0x3feee32dc313a8e5,
+0x3c79c3bba5562a2f, 0x3feee0e544ede173,
+0x3c859f48a72a4c6d, 0x3feedea64c123422,
+0xbc85a71612e21658, 0x3feedc70df1c5175,
+0xbc9312607a28698a, 0x3feeda4504ac801c,
+0x3c86421f6f1d24d6, 0x3feed822c367a024,
+0xbc58a78f4817895b, 0x3feed60a21f72e2a,
+0xbc9348a6815fce65, 0x3feed3fb2709468a,
+0xbc7c2c9b67499a1b, 0x3feed1f5d950a897,
+0x3c835c43984d9871, 0x3feecffa3f84b9d4,
+0x3c4363ed60c2ac11, 0x3feece086061892d,
+0xbc632afc8d9473a0, 0x3feecc2042a7d232,
+0x3c9666093b0664ef, 0x3feeca41ed1d0057,
+0xbc95fc5e44de020e, 0x3feec86d668b3237,
+0x3c6ecce1daa10379, 0x3feec6a2b5c13cd0,
+0xbc7ea0148327c42f, 0x3feec4e1e192aed2,
+0x3c93ff8e3f0f1230, 0x3feec32af0d7d3de,
+0xbc7a843ad1a88022, 0x3feec17dea6db7d7,
+0x3c7690cebb7aafb0, 0x3feebfdad5362a27,
+0x3c892ca3bf144e63, 0x3feebe41b817c114,
+0x3c931dbdeb54e077, 0x3feebcb299fddd0d,
+0xbc902c99b04aa8b0, 0x3feebb2d81d8abff,
+0xbc8f94340071a38e, 0x3feeb9b2769d2ca7,
+0x3c73e34f67e67118, 0x3feeb8417f4531ee,
+0xbc87deccdc93a349, 0x3feeb6daa2cf6642,
+0xbc75a3b1197ba0f0, 0x3feeb57de83f4eef,
+0xbc78dec6bd0f385f, 0x3feeb42b569d4f82,
+0x3c81bd2888075068, 0x3feeb2e2f4f6ad27,
+0xbc861246ec7b5cf6, 0x3feeb1a4ca5d920f,
+0xbc896be8ae89ef8f, 0x3feeb070dde910d2,
+0x3c93350518fdd78e, 0x3feeaf4736b527da,
+0xbc88e6ac90348602, 0x3feeae27dbe2c4cf,
+0x3c7b98b72f8a9b05, 0x3feead12d497c7fd,
+0xbc91af7f1365c3ac, 0x3feeac0827ff07cc,
+0x3c9063e1e21c5409, 0x3feeab07dd485429,
+0xbc943a3540d1898a, 0x3feeaa11fba87a03,
+0x3c34c7855019c6ea, 0x3feea9268a5946b7,
+0xbc951f58ddaa8090, 0x3feea84590998b93,
+0x3c9432e62b64c035, 0x3feea76f15ad2148,
+0xbc82e1648e50a17c, 0x3feea6a320dceb71,
+0xbc8ce44a6199769f, 0x3feea5e1b976dc09,
+0x3c95f30eda98a575, 0x3feea52ae6cdf6f4,
+0xbc8c33c53bef4da8, 0x3feea47eb03a5585,
+0x3c917ecda8a72159, 0x3feea3dd1d1929fd,
+0xbc845378892be9ae, 0x3feea34634ccc320,
+0xbc9345f3cee1ae6e, 0x3feea2b9febc8fb7,
+0xbc93cedd78565858, 0x3feea23882552225,
+0xbc85c33fdf910406, 0x3feea1c1c70833f6,
+0x3c5710aa807e1964, 0x3feea155d44ca973,
+0x3c81079ab5789604, 0x3feea0f4b19e9538,
+0xbc93b3efbf5e2228, 0x3feea09e667f3bcd,
+0x3c727df161cd7778, 0x3feea052fa75173e,
+0xbc6a12ad8734b982, 0x3feea012750bdabf,
+0x3c93f9924a05b767, 0x3fee9fdcddd47645,
+0xbc6367efb86da9ee, 0x3fee9fb23c651a2f,
+0xbc87557939a8b5ef, 0x3fee9f9298593ae5,
+0xbc80dc3d54e08851, 0x3fee9f7df9519484,
+0x3c51ed2f56fa9d1a, 0x3fee9f7466f42e87,
+0xbc781f647e5a3ecf, 0x3fee9f75e8ec5f74,
+0xbc88e67a9006c909, 0x3fee9f8286ead08a,
+0xbc86ee4ac08b7db0, 0x3fee9f9a48a58174,
+0x3c86597566977ac8, 0x3fee9fbd35d7cbfd,
+0xbc8619321e55e68a, 0x3fee9feb564267c9,
+0x3c92c0b7028a5c3a, 0x3feea024b1ab6e09,
+0x3c909ccb5e09d4d3, 0x3feea0694fde5d3f,
+0x3c8a30faf49cc78c, 0x3feea0b938ac1cf6,
+0xbc7b32dcb94da51d, 0x3feea11473eb0187,
+0xbc92dad3519d7b5b, 0x3feea17b0976cfdb,
+0x3c94ecfd5467c06b, 0x3feea1ed0130c132,
+0x3c87d51410fd15c2, 0x3feea26a62ff86f0,
+0x3c65ebe1abd66c55, 0x3feea2f336cf4e62,
+0xbc760a3629969871, 0x3feea3878491c491,
+0xbc88a1c52fb3cf42, 0x3feea427543e1a12,
+0x3c8b18c6e3fdef5d, 0x3feea4d2add106d9,
+0xbc9369b6f13b3734, 0x3feea589994cce13,
+0x3c90ec1ddcb1390a, 0x3feea64c1eb941f7,
+0xbc805e843a19ff1e, 0x3feea71a4623c7ad,
+0xbc522cea4f3afa1e, 0x3feea7f4179f5b21,
+0xbc94d450d872576e, 0x3feea8d99b4492ed,
+0x3c7c88549b958471, 0x3feea9cad931a436,
+0x3c90ad675b0e8a00, 0x3feeaac7d98a6699,
+0x3c931143962f7877, 0x3feeabd0a478580f,
+0x3c8db72fc1f0eab4, 0x3feeace5422aa0db,
+0x3c93e9e96f112479, 0x3feeae05bad61778,
+0xbc65b6609cc5e7ff, 0x3feeaf3216b5448c,
+0xbc8dac42a4a38df0, 0x3feeb06a5e0866d9,
+0x3c7bf68359f35f44, 0x3feeb1ae99157736,
+0x3c8b99dd98b1ed84, 0x3feeb2fed0282c8a,
+0xbc93091fa71e3d83, 0x3feeb45b0b91ffc6,
+0xbc7885ad50cbb750, 0x3feeb5c353aa2fe2,
+0xbc5da9b88b6c1e29, 0x3feeb737b0cdc5e5,
+0xbc82d5e85f3e0301, 0x3feeb8b82b5f98e5,
+0xbc6c23f97c90b959, 0x3feeba44cbc8520f,
+0xbc51669428996971, 0x3feebbdd9a7670b3,
+0xbc92434322f4f9aa, 0x3feebd829fde4e50,
+0x3c71f2b2c1c4c014, 0x3feebf33e47a22a2,
+0xbc85ca6cd7668e4b, 0x3feec0f170ca07ba,
+0xbc9294f304f166b6, 0x3feec2bb4d53fe0d,
+0x3c71affc2b91ce27, 0x3feec49182a3f090,
+0xbc8a1e58414c07d3, 0x3feec674194bb8d5,
+0x3c6dd235e10a73bb, 0x3feec86319e32323,
+0xbc79740b58a20091, 0x3feeca5e8d07f29e,
+0xbc87c50422622263, 0x3feecc667b5de565,
+0x3c9165830a2b96c2, 0x3feece7aed8eb8bb,
+0x3c8b1c86e3e231d5, 0x3feed09bec4a2d33,
+0xbc903d5cbe27874b, 0x3feed2c980460ad8,
+0xbc91bbd1d3bcbb15, 0x3feed503b23e255d,
+0x3c5986178980fce0, 0x3feed74a8af46052,
+0x3c90cc319cee31d2, 0x3feed99e1330b358,
+0xbc89472975b1f2a5, 0x3feedbfe53c12e59,
+0x3c8469846e735ab3, 0x3feede6b5579fdbf,
+0x3c7d8157a34b7e7f, 0x3feee0e521356eba,
+0xbc82dfcd978e9db4, 0x3feee36bbfd3f37a,
+0x3c8c8a4e231ebb7d, 0x3feee5ff3a3c2774,
+0x3c8c1a7792cb3387, 0x3feee89f995ad3ad,
+0xbc888c8d11a142e5, 0x3feeeb4ce622f2ff,
+0xbc907b8f4ad1d9fa, 0x3feeee07298db666,
+0x3c889c2ea41433c7, 0x3feef0ce6c9a8952,
+0xbc55c3d956dcaeba, 0x3feef3a2b84f15fb,
+0xbc7274aedac8ff80, 0x3feef68415b749b1,
+0xbc90a40e3da6f640, 0x3feef9728de5593a,
+0x3c85c620ce76df06, 0x3feefc6e29f1c52a,
+0xbc68d6f438ad9334, 0x3feeff76f2fb5e47,
+0xbc8fda52e1b51e41, 0x3fef028cf22749e4,
+0xbc91eee26b588a35, 0x3fef05b030a1064a,
+0xbc32141a7b3e2cd8, 0x3fef08e0b79a6f1f,
+0x3c74ffd70a5fddcd, 0x3fef0c1e904bc1d2,
+0xbc302899507554e5, 0x3fef0f69c3f3a207,
+0xbc91bdfbfa9298ac, 0x3fef12c25bd71e09,
+0xbc80dda2d4c0010c, 0x3fef16286141b33d,
+0x3c736eae30af0cb3, 0x3fef199bdd85529c,
+0xbc8a007daadf8d68, 0x3fef1d1cd9fa652c,
+0x3c8ee3325c9ffd94, 0x3fef20ab5fffd07a,
+0x3c836909391181d3, 0x3fef244778fafb22,
+0x3c84e08fd10959ac, 0x3fef27f12e57d14b,
+0xbc811cd7dbdf9547, 0x3fef2ba88988c933,
+0x3c63cdaf384e1a67, 0x3fef2f6d9406e7b5,
+0xbc7ac28b7bef6621, 0x3fef33405751c4db,
+0x3c676b2c6c921968, 0x3fef3720dcef9069,
+0xbc7030587207b9e1, 0x3fef3b0f2e6d1675,
+0xbc808a1883ccb5d2, 0x3fef3f0b555dc3fa,
+0xbc8cc734592af7fc, 0x3fef43155b5bab74,
+0xbc8fad5d3ffffa6f, 0x3fef472d4a07897c,
+0x3c87752a44f587e8, 0x3fef4b532b08c968,
+0xbc900dae3875a949, 0x3fef4f87080d89f2,
+0x3c85b66fefeef52e, 0x3fef53c8eacaa1d6,
+0x3c74a385a63d07a7, 0x3fef5818dcfba487,
+0x3c5159d9d908a96e, 0x3fef5c76e862e6d3,
+0xbc82919e2040220f, 0x3fef60e316c98398,
+0x3c8c254d16117a68, 0x3fef655d71ff6075,
+0x3c8e5a50d5c192ac, 0x3fef69e603db3285,
+0xbc8d8c329fbd0e03, 0x3fef6e7cd63a8315,
+0x3c843a59ac016b4b, 0x3fef7321f301b460,
+0xbc8ea6e6fbd5f2a6, 0x3fef77d5641c0658,
+0xbc82d52107b43e1f, 0x3fef7c97337b9b5f,
+0xbc63e8e3eab2cbb4, 0x3fef81676b197d17,
+0xbc892ab93b470dc9, 0x3fef864614f5a129,
+0xbc8b7966cd0d2cd9, 0x3fef8b333b16ee12,
+0x3c74b604603a88d3, 0x3fef902ee78b3ff6,
+0xbc776caa4c2ff1cf, 0x3fef953924676d76,
+0x3c83c5ec519d7271, 0x3fef9a51fbc74c83,
+0xbc81d5fc525d9940, 0x3fef9f7977cdb740,
+0xbc8ff7128fd391f0, 0x3fefa4afa2a490da,
+0x3c855cd8aaea3d21, 0x3fefa9f4867cca6e,
+0xbc8dae98e223747d, 0x3fefaf482d8e67f1,
+0x3c8269947c2bed4a, 0x3fefb4aaa2188510,
+0x3c8ec3bc41aa2008, 0x3fefba1bee615a27,
+0xbc83b6137e9afe9e, 0x3fefbf9c1cb6412a,
+0x3c842b94c3a9eb32, 0x3fefc52b376bba97,
+0xbc69fa74878ba7c7, 0x3fefcac948dd7274,
+0x3c8a64a931d185ee, 0x3fefd0765b6e4540,
+0x3c901f3a75ee0efe, 0x3fefd632798844f8,
+0xbc8e37bae43be3ed, 0x3fefdbfdad9cbe14,
+0xbc516a9ce6ed84fa, 0x3fefe1d802243c89,
+0x3c77893b4d91cd9d, 0x3fefe7c1819e90d8,
+0xbc699c7db2effc76, 0x3fefedba3692d514,
+0x3c5305c14160cc89, 0x3feff3c22b8f71f1,
+0x3c64b458677f9840, 0x3feff9d96b2a23d9,
+#elif N == 512
+0x0, 0x3ff0000000000000,
+0xbc75d87ade1f60d5, 0x3feffd8c86da1c0a,
+0xbc84e82fc61851ac, 0x3feffb1afa5abcbf,
+0x3c9bffdaa7ac4bac, 0x3feff8ab5b2cbd11,
+0x3c9b3b4f1a88bf6e, 0x3feff63da9fb3335,
+0x3c75c18e5ae0563a, 0x3feff3d1e77170b4,
+0xbc82985dd8521d32, 0x3feff168143b0281,
+0xbc705b1125cf49a5, 0x3fefef003103b10e,
+0xbc7160139cd8dc5d, 0x3fefec9a3e778061,
+0x3c9f879abbff3f87, 0x3fefea363d42b027,
+0x3c651e617061bfbd, 0x3fefe7d42e11bbcc,
+0x3c9b14003824712a, 0x3fefe57411915a8a,
+0xbc905e7a108766d1, 0x3fefe315e86e7f85,
+0x3c61cbf0f38af658, 0x3fefe0b9b35659d8,
+0x3c845fad437fa426, 0x3fefde5f72f654b1,
+0xbc9a3316383dcbc5, 0x3fefdc0727fc1762,
+0x3c8cd2523567f613, 0x3fefd9b0d3158574,
+0x3c9901c9e0e797fd, 0x3fefd75c74f0bec2,
+0xbc954529642b232f, 0x3fefd50a0e3c1f89,
+0xbc89b3236d111646, 0x3fefd2b99fa6407c,
+0xbc8bce8023f98efa, 0x3fefd06b29ddf6de,
+0xbc8cb191be99b1b0, 0x3fefce1ead925493,
+0x3c8293708ef5c32e, 0x3fefcbd42b72a836,
+0xbc9acb71e83765b7, 0x3fefc98ba42e7d30,
+0x3c60f74e61e6c861, 0x3fefc74518759bc8,
+0x3c5cd3e58b03697e, 0x3fefc50088f8093f,
+0xbc95b9280905b2a4, 0x3fefc2bdf66607e0,
+0xbc8bfb07d4755452, 0x3fefc07d61701716,
+0x3c90a3e45b33d399, 0x3fefbe3ecac6f383,
+0x3c8aedeb3e7b14cd, 0x3fefbc02331b9715,
+0x3c84f31f32c4b7e7, 0x3fefb9c79b1f3919,
+0x3c9a8eb1f3d914b4, 0x3fefb78f03834e52,
+0x3c979aa65d837b6d, 0x3fefb5586cf9890f,
+0xbc85b9eb0402507b, 0x3fefb323d833d93f,
+0x3c9407fb30d06420, 0x3fefb0f145e46c85,
+0xbc93f0f225bbf3ee, 0x3fefaec0b6bdae53,
+0x3c8eb51a92fdeffc, 0x3fefac922b7247f7,
+0xbc9c3fe7282d1784, 0x3fefaa65a4b520ba,
+0xbc9a5d04b3b9911b, 0x3fefa83b23395dec,
+0x3c9c8be44bf4cde8, 0x3fefa612a7b26300,
+0x3c3ebe3d702f9cd1, 0x3fefa3ec32d3d1a2,
+0x3c820c5444c93c44, 0x3fefa1c7c55189c6,
+0xbc937a01f0739546, 0x3fef9fa55fdfa9c5,
+0xbc84c6baeb580d7a, 0x3fef9d8503328e6d,
+0xbc6a033489906e0b, 0x3fef9b66affed31b,
+0x3c8657aa1b0d9f83, 0x3fef994a66f951ce,
+0x3c8b8268b04ef0a5, 0x3fef973028d7233e,
+0x3c62f2c7fd6ee145, 0x3fef9517f64d9ef1,
+0xbc9556522a2fbd0e, 0x3fef9301d0125b51,
+0xbc6b0b2789925e90, 0x3fef90edb6db2dc1,
+0xbc9ac46e44a2ebcc, 0x3fef8edbab5e2ab6,
+0xbc93aad17d197fae, 0x3fef8ccbae51a5c8,
+0xbc5080ef8c4eea55, 0x3fef8abdc06c31cc,
+0xbc989c464a07ad70, 0x3fef88b1e264a0e9,
+0xbc65704e90c9f860, 0x3fef86a814f204ab,
+0xbc72c338fce197f4, 0x3fef84a058cbae1e,
+0xbc91c923b9d5f416, 0x3fef829aaea92de0,
+0xbc6dca724cea0eb6, 0x3fef809717425438,
+0xbc897cea57e46280, 0x3fef7e95934f312e,
+0x3c464770b955d34d, 0x3fef7c962388149e,
+0x3c80d3e3e95c55af, 0x3fef7a98c8a58e51,
+0xbc962811c114424f, 0x3fef789d83606e12,
+0x3c56f01429e2b9d2, 0x3fef76a45471c3c2,
+0x3c8ec58e74904dd4, 0x3fef74ad3c92df73,
+0xbc801b15eaa59348, 0x3fef72b83c7d517b,
+0x3c8d63b0ab2d5bbf, 0x3fef70c554eaea89,
+0x3c6e653b2459034b, 0x3fef6ed48695bbc0,
+0xbc9ca9effbeeac92, 0x3fef6ce5d23816c9,
+0xbc8f1ff055de323d, 0x3fef6af9388c8dea,
+0x3c8bda920de0f6e2, 0x3fef690eba4df41f,
+0x3c92cc7ea345b7dc, 0x3fef672658375d2f,
+0xbc9a597f9a5ff71c, 0x3fef654013041dc2,
+0x3c8b898c3f1353bf, 0x3fef635beb6fcb75,
+0x3c50835b125aa573, 0x3fef6179e2363cf8,
+0x3c957bfb2876ea9e, 0x3fef5f99f8138a1c,
+0x3c8aaa13d61aec1f, 0x3fef5dbc2dc40bf0,
+0xbc96d99c7611eb26, 0x3fef5be084045cd4,
+0x3c8a4f81aa7110bd, 0x3fef5a06fb91588f,
+0x3c8cdc1873af2155, 0x3fef582f95281c6b,
+0xbc6817fd6a313e3e, 0x3fef565a51860746,
+0x3c9aecf73e3a2f60, 0x3fef54873168b9aa,
+0xbc96236af85fd26a, 0x3fef52b6358e15e8,
+0xbc9493684653a131, 0x3fef50e75eb44027,
+0x3c7795eb4523abe7, 0x3fef4f1aad999e82,
+0xbc8fe782cb86389d, 0x3fef4d5022fcd91d,
+0x3c8fe58b91b40095, 0x3fef4b87bf9cda38,
+0xbc98e2899077520a, 0x3fef49c18438ce4d,
+0x3c91ecaa860c614a, 0x3fef47fd7190241e,
+0x3c8a6f4144a6c38d, 0x3fef463b88628cd6,
+0xbc3e45c83ba0bbcb, 0x3fef447bc96ffc18,
+0x3c9120fcd4f59273, 0x3fef42be3578a819,
+0xbc29fd3bea07b4ee, 0x3fef4102cd3d09b9,
+0x3c807a05b0e4047d, 0x3fef3f49917ddc96,
+0x3c87f1c7350e256d, 0x3fef3d9282fc1f27,
+0x3c89b788c188c9b8, 0x3fef3bdda27912d1,
+0x3c420dac6c124f4f, 0x3fef3a2af0b63bff,
+0x3c968efde3a8a894, 0x3fef387a6e756238,
+0xbc99501d09bc09fd, 0x3fef36cc1c78903a,
+0x3c877afbca90ef84, 0x3fef351ffb82140a,
+0x3c73baf864dc8675, 0x3fef33760c547f15,
+0x3c875e18f274487d, 0x3fef31ce4fb2a63f,
+0x3c91b0575c1eaf54, 0x3fef3028c65fa1ff,
+0x3c91512f082876ee, 0x3fef2e85711ece75,
+0xbc90364bc9ce33ab, 0x3fef2ce450b3cb82,
+0x3c80472b981fe7f2, 0x3fef2b4565e27cdd,
+0xbc7548165d85ed32, 0x3fef29a8b16f0a30,
+0x3c9a02f0c7d75ec6, 0x3fef280e341ddf29,
+0x3c7c3b977a68e32c, 0x3fef2675eeb3ab98,
+0xbc96b87b3f71085e, 0x3fef24dfe1f56381,
+0xbc93a255f697ecfe, 0x3fef234c0ea83f36,
+0xbc803297e78260bf, 0x3fef21ba7591bb70,
+0x3c8d2d19edc1e550, 0x3fef202b17779965,
+0x3c82f7e16d09ab31, 0x3fef1e9df51fdee1,
+0xbc76b2173113dd8c, 0x3fef1d130f50d65c,
+0xbc95b77e5ccd9fbf, 0x3fef1b8a66d10f13,
+0x3c811aa5f853590b, 0x3fef1a03fc675d1f,
+0xbc3d219b1a6fbffa, 0x3fef187fd0dad990,
+0x3c61d61a34c8aa02, 0x3fef16fde4f2e280,
+0xbc91e75c40b4251e, 0x3fef157e39771b2f,
+0xbc91f892bf6b286d, 0x3fef1400cf2f6c18,
+0x3c8b3782720c0ab4, 0x3fef1285a6e4030b,
+0x3c7590c65c20e680, 0x3fef110cc15d5346,
+0x3c98a911f1f7785a, 0x3fef0f961f641589,
+0x3c86fe320b5c1e9d, 0x3fef0e21c1c14833,
+0x3c6e149289cecb8f, 0x3fef0cafa93e2f56,
+0xbc903cd8b2f25790, 0x3fef0b3fd6a454d2,
+0xbc61e7c998db7dbb, 0x3fef09d24abd886b,
+0x3c7b3bf786a54a87, 0x3fef08670653dfe4,
+0x3c834d754db0abb6, 0x3fef06fe0a31b715,
+0x3c74bb6c41732885, 0x3fef05975721b004,
+0x3c85425c11faadf4, 0x3fef0432edeeb2fd,
+0xbc99d7399abb9a8b, 0x3fef02d0cf63eeac,
+0x3c864201e2ac744c, 0x3fef0170fc4cd831,
+0xbc5451d60c6ac9eb, 0x3fef001375752b40,
+0xbc979517a03e2847, 0x3feefeb83ba8ea32,
+0x3c8787a210ceafd9, 0x3feefd5f4fb45e20,
+0x3c8fdd395dd3f84a, 0x3feefc08b26416ff,
+0xbc888d1e4629943d, 0x3feefab46484ebb4,
+0xbc800e2a46da4bee, 0x3feef96266e3fa2d,
+0xbc93369c544088b6, 0x3feef812ba4ea77d,
+0xbc86a3803b8e5b04, 0x3feef6c55f929ff1,
+0x3c85373ce4eb6dfb, 0x3feef57a577dd72b,
+0xbc87430803972b34, 0x3feef431a2de883b,
+0x3c83adec8265a67f, 0x3feef2eb428335b4,
+0xbc924aedcc4b5068, 0x3feef1a7373aa9cb,
+0xbc835388bcac6bc5, 0x3feef06581d3f669,
+0xbc954de30ae02d94, 0x3feeef26231e754a,
+0x3c727cdb4e4b6640, 0x3feeede91be9c811,
+0xbc9907f81b512d8e, 0x3feeecae6d05d866,
+0x3c86c2696a26af35, 0x3feeeb761742d808,
+0xbc94f2487e1c03ec, 0x3feeea401b7140ef,
+0x3c888f6ff06b979a, 0x3feee90c7a61d55b,
+0xbc71d1e83e9436d2, 0x3feee7db34e59ff7,
+0xbc89d5efaabc2030, 0x3feee6ac4bcdf3ea,
+0x3c914a5432fcb2f4, 0x3feee57fbfec6cf4,
+0xbc76b8867f91c9d6, 0x3feee4559212ef89,
+0xbc991919b3ce1b15, 0x3feee32dc313a8e5,
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+0xbc8cc734592af7fc, 0x3fef43155b5bab74,
+0xbc8335827ffb9dce, 0x3fef451f95018d17,
+0xbc8fad5d3ffffa6f, 0x3fef472d4a07897c,
+0x3c645563980ef762, 0x3fef493e7ba2c38c,
+0x3c87752a44f587e8, 0x3fef4b532b08c968,
+0xbc8cd0205eb2aab2, 0x3fef4d6b596f948c,
+0xbc900dae3875a949, 0x3fef4f87080d89f2,
+0xbc8aab80ceab2b4a, 0x3fef51a638197a3c,
+0x3c85b66fefeef52e, 0x3fef53c8eacaa1d6,
+0xbc8f870f40a8ba1b, 0x3fef55ef2158a91f,
+0x3c74a385a63d07a7, 0x3fef5818dcfba487,
+0x3c83c119f18464c5, 0x3fef5a461eec14be,
+0x3c5159d9d908a96e, 0x3fef5c76e862e6d3,
+0xbc5a628c2be4e7c7, 0x3fef5eab3a99745b,
+0xbc82919e2040220f, 0x3fef60e316c98398,
+0xbc72550d76be719a, 0x3fef631e7e2d479d,
+0x3c8c254d16117a68, 0x3fef655d71ff6075,
+0xbc82090274667d12, 0x3fef679ff37adb4a,
+0x3c8e5a50d5c192ac, 0x3fef69e603db3285,
+0x3c75f7d28150cac4, 0x3fef6c2fa45c4dfd,
+0xbc8d8c329fbd0e03, 0x3fef6e7cd63a8315,
+0x3c890de9296f4cd1, 0x3fef70cd9ab294e4,
+0x3c843a59ac016b4b, 0x3fef7321f301b460,
+0x3c832ff9978b34bc, 0x3fef7579e065807d,
+0xbc8ea6e6fbd5f2a6, 0x3fef77d5641c0658,
+0xbc7303b63dda1980, 0x3fef7a347f63c159,
+0xbc82d52107b43e1f, 0x3fef7c97337b9b5f,
+0xbc81f2ba385f2f95, 0x3fef7efd81a2ece1,
+0xbc63e8e3eab2cbb4, 0x3fef81676b197d17,
+0x3c768d9144ae12fc, 0x3fef83d4f11f8220,
+0xbc892ab93b470dc9, 0x3fef864614f5a129,
+0x3c853687f542403b, 0x3fef88bad7dcee90,
+0xbc8b7966cd0d2cd9, 0x3fef8b333b16ee12,
+0xbc736ed2de40b407, 0x3fef8daf3fe592e8,
+0x3c74b604603a88d3, 0x3fef902ee78b3ff6,
+0xbc614ef56c770f3b, 0x3fef92b2334ac7ee,
+0xbc776caa4c2ff1cf, 0x3fef953924676d76,
+0x3c8df7d1353d8e88, 0x3fef97c3bc24e350,
+0x3c83c5ec519d7271, 0x3fef9a51fbc74c83,
+0xbc850bed64091b8a, 0x3fef9ce3e4933c7e,
+0xbc81d5fc525d9940, 0x3fef9f7977cdb740,
+0x3c89d852381c317f, 0x3fefa212b6bc3181,
+0xbc8ff7128fd391f0, 0x3fefa4afa2a490da,
+0x3c68a00e3cca04c4, 0x3fefa7503ccd2be5,
+0x3c855cd8aaea3d21, 0x3fefa9f4867cca6e,
+0xbc5a1f25ce94cae7, 0x3fefac9c80faa594,
+0xbc8dae98e223747d, 0x3fefaf482d8e67f1,
+0xbc6fb5f3ee307976, 0x3fefb1f78d802dc2,
+0x3c8269947c2bed4a, 0x3fefb4aaa2188510,
+0x3c737e8ae802b851, 0x3fefb7616ca06dd6,
+0x3c8ec3bc41aa2008, 0x3fefba1bee615a27,
+0x3c875119560e34af, 0x3fefbcda28a52e59,
+0xbc83b6137e9afe9e, 0x3fefbf9c1cb6412a,
+0xbc7431c3840929c6, 0x3fefc261cbdf5be7,
+0x3c842b94c3a9eb32, 0x3fefc52b376bba97,
+0xbc8cb472d2e86b99, 0x3fefc7f860a70c22,
+0xbc69fa74878ba7c7, 0x3fefcac948dd7274,
+0x3c83f5df2fde16a8, 0x3fefcd9df15b82ac,
+0x3c8a64a931d185ee, 0x3fefd0765b6e4540,
+0x3c8eef18336b62e3, 0x3fefd35288633625,
+0x3c901f3a75ee0efe, 0x3fefd632798844f8,
+0x3c80d23f87b50a2a, 0x3fefd916302bd526,
+0xbc8e37bae43be3ed, 0x3fefdbfdad9cbe14,
+0x3c8302dee657c8e6, 0x3fefdee8f32a4b45,
+0xbc516a9ce6ed84fa, 0x3fefe1d802243c89,
+0xbc7b0caa080df170, 0x3fefe4cadbdac61d,
+0x3c77893b4d91cd9d, 0x3fefe7c1819e90d8,
+0x3c7617a9f2fd24e5, 0x3fefeabbf4c0ba54,
+0xbc699c7db2effc76, 0x3fefedba3692d514,
+0x3c75f103b8fd5ca7, 0x3feff0bc4866e8ad,
+0x3c5305c14160cc89, 0x3feff3c22b8f71f1,
+0x3c8e70b094fa075a, 0x3feff6cbe15f6314,
+0x3c64b458677f9840, 0x3feff9d96b2a23d9,
+0xbc72ec9a3e5d680a, 0x3feffceaca4391b6,
+#endif
+},
+};
diff --git a/libc/AOR_v20.02/math/expf.c b/libc/AOR_v20.02/math/expf.c
new file mode 100644
index 0000000000000..035cb45191630
--- /dev/null
+++ b/libc/AOR_v20.02/math/expf.c
@@ -0,0 +1,92 @@
+/*
+ * Single-precision e^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+/*
+EXP2F_TABLE_BITS = 5
+EXP2F_POLY_ORDER = 3
+
+ULP error: 0.502 (nearest rounding.)
+Relative error: 1.69 * 2^-34 in [-ln2/64, ln2/64] (before rounding.)
+Wrong count: 170635 (all nearest rounding wrong results with fma.)
+Non-nearest ULP error: 1 (rounded ULP error)
+*/
+
+#define N (1 << EXP2F_TABLE_BITS)
+#define InvLn2N __exp2f_data.invln2_scaled
+#define T __exp2f_data.tab
+#define C __exp2f_data.poly_scaled
+
+static inline uint32_t
+top12 (float x)
+{
+  return asuint (x) >> 20;
+}
+
+float
+expf (float x)
+{
+  uint32_t abstop;
+  uint64_t ki, t;
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t kd, xd, z, r, r2, y, s;
+
+  xd = (double_t) x;
+  abstop = top12 (x) & 0x7ff;
+  if (unlikely (abstop >= top12 (88.0f)))
+    {
+      /* |x| >= 88 or x is nan.  */
+      if (asuint (x) == asuint (-INFINITY))
+	return 0.0f;
+      if (abstop >= top12 (INFINITY))
+	return x + x;
+      if (x > 0x1.62e42ep6f) /* x > log(0x1p128) ~= 88.72 */
+	return __math_oflowf (0);
+      if (x < -0x1.9fe368p6f) /* x < log(0x1p-150) ~= -103.97 */
+	return __math_uflowf (0);
+#if WANT_ERRNO_UFLOW
+      if (x < -0x1.9d1d9ep6f) /* x < log(0x1p-149) ~= -103.28 */
+	return __math_may_uflowf (0);
+#endif
+    }
+
+  /* x*N/Ln2 = k + r with r in [-1/2, 1/2] and int k.  */
+  z = InvLn2N * xd;
+
+  /* Round and convert z to int, the result is in [-150*N, 128*N] and
+     ideally nearest int is used, otherwise the magnitude of r can be
+     bigger which gives larger approximation error.  */
+#if TOINT_INTRINSICS
+  kd = roundtoint (z);
+  ki = converttoint (z);
+#else
+# define SHIFT __exp2f_data.shift
+  kd = eval_as_double (z + SHIFT);
+  ki = asuint64 (kd);
+  kd -= SHIFT;
+#endif
+  r = z - kd;
+
+  /* exp(x) = 2^(k/N) * 2^(r/N) ~= s * (C0*r^3 + C1*r^2 + C2*r + 1) */
+  t = T[ki % N];
+  t += ki << (52 - EXP2F_TABLE_BITS);
+  s = asdouble (t);
+  z = C[0] * r + C[1];
+  r2 = r * r;
+  y = C[2] * r + 1;
+  y = z * r2 + y;
+  y = y * s;
+  return eval_as_float (y);
+}
+#if USE_GLIBC_ABI
+strong_alias (expf, __expf_finite)
+hidden_alias (expf, __ieee754_expf)
+#endif
diff --git a/libc/AOR_v20.02/math/include/mathlib.h b/libc/AOR_v20.02/math/include/mathlib.h
new file mode 100644
index 0000000000000..4765ff4106f20
--- /dev/null
+++ b/libc/AOR_v20.02/math/include/mathlib.h
@@ -0,0 +1,101 @@
+/*
+ * Public API.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef _MATHLIB_H
+#define _MATHLIB_H
+
+float expf (float);
+float exp2f (float);
+float logf (float);
+float log2f (float);
+float powf (float, float);
+float sinf (float);
+float cosf (float);
+void sincosf (float, float*, float*);
+
+double exp (double);
+double exp2 (double);
+double log (double);
+double log2 (double);
+double pow (double, double);
+
+/* Scalar functions using the vector algorithm with identical result.  */
+float __s_sinf (float);
+float __s_cosf (float);
+float __s_expf (float);
+float __s_expf_1u (float);
+float __s_exp2f (float);
+float __s_exp2f_1u (float);
+float __s_logf (float);
+float __s_powf (float, float);
+double __s_sin (double);
+double __s_cos (double);
+double __s_exp (double);
+double __s_log (double);
+double __s_pow (double, double);
+
+#if __aarch64__
+#if __GNUC__ >= 5
+typedef __Float32x4_t __f32x4_t;
+typedef __Float64x2_t __f64x2_t;
+#elif __clang_major__*100+__clang_minor__ >= 305
+typedef __attribute__((__neon_vector_type__(4))) float __f32x4_t;
+typedef __attribute__((__neon_vector_type__(2))) double __f64x2_t;
+#else
+#error Unsupported compiler
+#endif
+
+/* Vector functions following the base PCS.  */
+__f32x4_t __v_sinf (__f32x4_t);
+__f32x4_t __v_cosf (__f32x4_t);
+__f32x4_t __v_expf (__f32x4_t);
+__f32x4_t __v_expf_1u (__f32x4_t);
+__f32x4_t __v_exp2f (__f32x4_t);
+__f32x4_t __v_exp2f_1u (__f32x4_t);
+__f32x4_t __v_logf (__f32x4_t);
+__f32x4_t __v_powf (__f32x4_t, __f32x4_t);
+__f64x2_t __v_sin (__f64x2_t);
+__f64x2_t __v_cos (__f64x2_t);
+__f64x2_t __v_exp (__f64x2_t);
+__f64x2_t __v_log (__f64x2_t);
+__f64x2_t __v_pow (__f64x2_t, __f64x2_t);
+
+#if __GNUC__ >= 9 || __clang_major__ >= 8
+#define __vpcs __attribute__((__aarch64_vector_pcs__))
+
+/* Vector functions following the vector PCS.  */
+__vpcs __f32x4_t __vn_sinf (__f32x4_t);
+__vpcs __f32x4_t __vn_cosf (__f32x4_t);
+__vpcs __f32x4_t __vn_expf (__f32x4_t);
+__vpcs __f32x4_t __vn_expf_1u (__f32x4_t);
+__vpcs __f32x4_t __vn_exp2f (__f32x4_t);
+__vpcs __f32x4_t __vn_exp2f_1u (__f32x4_t);
+__vpcs __f32x4_t __vn_logf (__f32x4_t);
+__vpcs __f32x4_t __vn_powf (__f32x4_t, __f32x4_t);
+__vpcs __f64x2_t __vn_sin (__f64x2_t);
+__vpcs __f64x2_t __vn_cos (__f64x2_t);
+__vpcs __f64x2_t __vn_exp (__f64x2_t);
+__vpcs __f64x2_t __vn_log (__f64x2_t);
+__vpcs __f64x2_t __vn_pow (__f64x2_t, __f64x2_t);
+
+/* Vector functions following the vector PCS using ABI names.  */
+__vpcs __f32x4_t _ZGVnN4v_sinf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_exp2f (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_logf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4vv_powf (__f32x4_t, __f32x4_t);
+__vpcs __f64x2_t _ZGVnN2v_sin (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_log (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2vv_pow (__f64x2_t, __f64x2_t);
+#endif
+#endif
+
+#endif
diff --git a/libc/AOR_v20.02/math/log.c b/libc/AOR_v20.02/math/log.c
new file mode 100644
index 0000000000000..c546b694099dd
--- /dev/null
+++ b/libc/AOR_v20.02/math/log.c
@@ -0,0 +1,163 @@
+/*
+ * Double-precision log(x) function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <float.h>
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+#define T __log_data.tab
+#define T2 __log_data.tab2
+#define B __log_data.poly1
+#define A __log_data.poly
+#define Ln2hi __log_data.ln2hi
+#define Ln2lo __log_data.ln2lo
+#define N (1 << LOG_TABLE_BITS)
+#define OFF 0x3fe6000000000000
+
+/* Top 16 bits of a double.  */
+static inline uint32_t
+top16 (double x)
+{
+  return asuint64 (x) >> 48;
+}
+
+double
+log (double x)
+{
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t w, z, r, r2, r3, y, invc, logc, kd, hi, lo;
+  uint64_t ix, iz, tmp;
+  uint32_t top;
+  int k, i;
+
+  ix = asuint64 (x);
+  top = top16 (x);
+
+#if LOG_POLY1_ORDER == 10 || LOG_POLY1_ORDER == 11
+# define LO asuint64 (1.0 - 0x1p-5)
+# define HI asuint64 (1.0 + 0x1.1p-5)
+#elif LOG_POLY1_ORDER == 12
+# define LO asuint64 (1.0 - 0x1p-4)
+# define HI asuint64 (1.0 + 0x1.09p-4)
+#endif
+  if (unlikely (ix - LO < HI - LO))
+    {
+      /* Handle close to 1.0 inputs separately.  */
+      /* Fix sign of zero with downward rounding when x==1.  */
+      if (WANT_ROUNDING && unlikely (ix == asuint64 (1.0)))
+	return 0;
+      r = x - 1.0;
+      r2 = r * r;
+      r3 = r * r2;
+#if LOG_POLY1_ORDER == 10
+      /* Worst-case error is around 0.516 ULP.  */
+      y = r3 * (B[1] + r * B[2] + r2 * B[3]
+		+ r3 * (B[4] + r * B[5] + r2 * B[6] + r3 * (B[7] + r * B[8])));
+      w = B[0] * r2; /* B[0] == -0.5.  */
+      hi = r + w;
+      y += r - hi + w;
+      y += hi;
+#elif LOG_POLY1_ORDER == 11
+      /* Worst-case error is around 0.516 ULP.  */
+      y = r3 * (B[1] + r * B[2]
+		+ r2 * (B[3] + r * B[4] + r2 * B[5]
+			+ r3 * (B[6] + r * B[7] + r2 * B[8] + r3 * B[9])));
+      w = B[0] * r2; /* B[0] == -0.5.  */
+      hi = r + w;
+      y += r - hi + w;
+      y += hi;
+#elif LOG_POLY1_ORDER == 12
+      y = r3 * (B[1] + r * B[2] + r2 * B[3]
+		+ r3 * (B[4] + r * B[5] + r2 * B[6]
+			+ r3 * (B[7] + r * B[8] + r2 * B[9] + r3 * B[10])));
+# if N <= 64
+      /* Worst-case error is around 0.532 ULP.  */
+      w = B[0] * r2; /* B[0] == -0.5.  */
+      hi = r + w;
+      y += r - hi + w;
+      y += hi;
+# else
+      /* Worst-case error is around 0.507 ULP.  */
+      w = r * 0x1p27;
+      double_t rhi = r + w - w;
+      double_t rlo = r - rhi;
+      w = rhi * rhi * B[0]; /* B[0] == -0.5.  */
+      hi = r + w;
+      lo = r - hi + w;
+      lo += B[0] * rlo * (rhi + r);
+      y += lo;
+      y += hi;
+# endif
+#endif
+      return eval_as_double (y);
+    }
+  if (unlikely (top - 0x0010 >= 0x7ff0 - 0x0010))
+    {
+      /* x < 0x1p-1022 or inf or nan.  */
+      if (ix * 2 == 0)
+	return __math_divzero (1);
+      if (ix == asuint64 (INFINITY)) /* log(inf) == inf.  */
+	return x;
+      if ((top & 0x8000) || (top & 0x7ff0) == 0x7ff0)
+	return __math_invalid (x);
+      /* x is subnormal, normalize it.  */
+      ix = asuint64 (x * 0x1p52);
+      ix -= 52ULL << 52;
+    }
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF) and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (52 - LOG_TABLE_BITS)) % N;
+  k = (int64_t) tmp >> 52; /* arithmetic shift */
+  iz = ix - (tmp & 0xfffULL << 52);
+  invc = T[i].invc;
+  logc = T[i].logc;
+  z = asdouble (iz);
+
+  /* log(x) = log1p(z/c-1) + log(c) + k*Ln2.  */
+  /* r ~= z/c - 1, |r| < 1/(2*N).  */
+#if HAVE_FAST_FMA
+  /* rounding error: 0x1p-55/N.  */
+  r = fma (z, invc, -1.0);
+#else
+  /* rounding error: 0x1p-55/N + 0x1p-66.  */
+  r = (z - T2[i].chi - T2[i].clo) * invc;
+#endif
+  kd = (double_t) k;
+
+  /* hi + lo = r + log(c) + k*Ln2.  */
+  w = kd * Ln2hi + logc;
+  hi = w + r;
+  lo = w - hi + r + kd * Ln2lo;
+
+  /* log(x) = lo + (log1p(r) - r) + hi.  */
+  r2 = r * r; /* rounding error: 0x1p-54/N^2.  */
+  /* Worst case error if |y| > 0x1p-5:
+     0.5 + 4.13/N + abs-poly-error*2^57 ULP (+ 0.002 ULP without fma)
+     Worst case error if |y| > 0x1p-4:
+     0.5 + 2.06/N + abs-poly-error*2^56 ULP (+ 0.001 ULP without fma).  */
+#if LOG_POLY_ORDER == 6
+  y = lo + r2 * A[0] + r * r2 * (A[1] + r * A[2] + r2 * (A[3] + r * A[4])) + hi;
+#elif LOG_POLY_ORDER == 7
+  y = lo
+      + r2 * (A[0] + r * A[1] + r2 * (A[2] + r * A[3])
+	      + r2 * r2 * (A[4] + r * A[5]))
+      + hi;
+#endif
+  return eval_as_double (y);
+}
+#if USE_GLIBC_ABI
+strong_alias (log, __log_finite)
+hidden_alias (log, __ieee754_log)
+# if LDBL_MANT_DIG == 53
+long double logl (long double x) { return log (x); }
+# endif
+#endif
diff --git a/libc/AOR_v20.02/math/log2.c b/libc/AOR_v20.02/math/log2.c
new file mode 100644
index 0000000000000..a1e20b0118a59
--- /dev/null
+++ b/libc/AOR_v20.02/math/log2.c
@@ -0,0 +1,142 @@
+/*
+ * Double-precision log2(x) function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <float.h>
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+#define T __log2_data.tab
+#define T2 __log2_data.tab2
+#define B __log2_data.poly1
+#define A __log2_data.poly
+#define InvLn2hi __log2_data.invln2hi
+#define InvLn2lo __log2_data.invln2lo
+#define N (1 << LOG2_TABLE_BITS)
+#define OFF 0x3fe6000000000000
+
+/* Top 16 bits of a double.  */
+static inline uint32_t
+top16 (double x)
+{
+  return asuint64 (x) >> 48;
+}
+
+double
+log2 (double x)
+{
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t z, r, r2, r4, y, invc, logc, kd, hi, lo, t1, t2, t3, p;
+  uint64_t ix, iz, tmp;
+  uint32_t top;
+  int k, i;
+
+  ix = asuint64 (x);
+  top = top16 (x);
+
+#if LOG2_POLY1_ORDER == 11
+# define LO asuint64 (1.0 - 0x1.5b51p-5)
+# define HI asuint64 (1.0 + 0x1.6ab2p-5)
+#endif
+  if (unlikely (ix - LO < HI - LO))
+    {
+      /* Handle close to 1.0 inputs separately.  */
+      /* Fix sign of zero with downward rounding when x==1.  */
+      if (WANT_ROUNDING && unlikely (ix == asuint64 (1.0)))
+	return 0;
+      r = x - 1.0;
+#if HAVE_FAST_FMA
+      hi = r * InvLn2hi;
+      lo = r * InvLn2lo + fma (r, InvLn2hi, -hi);
+#else
+      double_t rhi, rlo;
+      rhi = asdouble (asuint64 (r) & -1ULL << 32);
+      rlo = r - rhi;
+      hi = rhi * InvLn2hi;
+      lo = rlo * InvLn2hi + r * InvLn2lo;
+#endif
+      r2 = r * r; /* rounding error: 0x1p-62.  */
+      r4 = r2 * r2;
+#if LOG2_POLY1_ORDER == 11
+      /* Worst-case error is less than 0.54 ULP (0.55 ULP without fma).  */
+      p = r2 * (B[0] + r * B[1]);
+      y = hi + p;
+      lo += hi - y + p;
+      lo += r4 * (B[2] + r * B[3] + r2 * (B[4] + r * B[5])
+		  + r4 * (B[6] + r * B[7] + r2 * (B[8] + r * B[9])));
+      y += lo;
+#endif
+      return eval_as_double (y);
+    }
+  if (unlikely (top - 0x0010 >= 0x7ff0 - 0x0010))
+    {
+      /* x < 0x1p-1022 or inf or nan.  */
+      if (ix * 2 == 0)
+	return __math_divzero (1);
+      if (ix == asuint64 (INFINITY)) /* log(inf) == inf.  */
+	return x;
+      if ((top & 0x8000) || (top & 0x7ff0) == 0x7ff0)
+	return __math_invalid (x);
+      /* x is subnormal, normalize it.  */
+      ix = asuint64 (x * 0x1p52);
+      ix -= 52ULL << 52;
+    }
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF) and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (52 - LOG2_TABLE_BITS)) % N;
+  k = (int64_t) tmp >> 52; /* arithmetic shift */
+  iz = ix - (tmp & 0xfffULL << 52);
+  invc = T[i].invc;
+  logc = T[i].logc;
+  z = asdouble (iz);
+  kd = (double_t) k;
+
+  /* log2(x) = log2(z/c) + log2(c) + k.  */
+  /* r ~= z/c - 1, |r| < 1/(2*N).  */
+#if HAVE_FAST_FMA
+  /* rounding error: 0x1p-55/N.  */
+  r = fma (z, invc, -1.0);
+  t1 = r * InvLn2hi;
+  t2 = r * InvLn2lo + fma (r, InvLn2hi, -t1);
+#else
+  double_t rhi, rlo;
+  /* rounding error: 0x1p-55/N + 0x1p-65.  */
+  r = (z - T2[i].chi - T2[i].clo) * invc;
+  rhi = asdouble (asuint64 (r) & -1ULL << 32);
+  rlo = r - rhi;
+  t1 = rhi * InvLn2hi;
+  t2 = rlo * InvLn2hi + r * InvLn2lo;
+#endif
+
+  /* hi + lo = r/ln2 + log2(c) + k.  */
+  t3 = kd + logc;
+  hi = t3 + t1;
+  lo = t3 - hi + t1 + t2;
+
+  /* log2(r+1) = r/ln2 + r^2*poly(r).  */
+  /* Evaluation is optimized assuming superscalar pipelined execution.  */
+  r2 = r * r; /* rounding error: 0x1p-54/N^2.  */
+  r4 = r2 * r2;
+#if LOG2_POLY_ORDER == 7
+  /* Worst-case error if |y| > 0x1p-4: 0.547 ULP (0.550 ULP without fma).
+     ~ 0.5 + 2/N/ln2 + abs-poly-error*0x1p56 ULP (+ 0.003 ULP without fma).  */
+  p = A[0] + r * A[1] + r2 * (A[2] + r * A[3]) + r4 * (A[4] + r * A[5]);
+  y = lo + r2 * p + hi;
+#endif
+  return eval_as_double (y);
+}
+#if USE_GLIBC_ABI
+strong_alias (log2, __log2_finite)
+hidden_alias (log2, __ieee754_log2)
+# if LDBL_MANT_DIG == 53
+long double log2l (long double x) { return log2 (x); }
+# endif
+#endif
diff --git a/libc/AOR_v20.02/math/log2_data.c b/libc/AOR_v20.02/math/log2_data.c
new file mode 100644
index 0000000000000..a487dbfb98560
--- /dev/null
+++ b/libc/AOR_v20.02/math/log2_data.c
@@ -0,0 +1,210 @@
+/*
+ * Data for log2.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#define N (1 << LOG2_TABLE_BITS)
+
+const struct log2_data __log2_data = {
+// First coefficient: 0x1.71547652b82fe1777d0ffda0d24p0
+.invln2hi = 0x1.7154765200000p+0,
+.invln2lo = 0x1.705fc2eefa200p-33,
+.poly1 = {
+#if LOG2_POLY1_ORDER == 11
+// relative error: 0x1.2fad8188p-63
+// in -0x1.5b51p-5 0x1.6ab2p-5
+-0x1.71547652b82fep-1,
+0x1.ec709dc3a03f7p-2,
+-0x1.71547652b7c3fp-2,
+0x1.2776c50f05be4p-2,
+-0x1.ec709dd768fe5p-3,
+0x1.a61761ec4e736p-3,
+-0x1.7153fbc64a79bp-3,
+0x1.484d154f01b4ap-3,
+-0x1.289e4a72c383cp-3,
+0x1.0b32f285aee66p-3,
+#endif
+},
+.poly = {
+#if N == 64 && LOG2_POLY_ORDER == 7
+// relative error: 0x1.a72c2bf8p-58
+// abs error: 0x1.67a552c8p-66
+// in -0x1.f45p-8 0x1.f45p-8
+-0x1.71547652b8339p-1,
+0x1.ec709dc3a04bep-2,
+-0x1.7154764702ffbp-2,
+0x1.2776c50034c48p-2,
+-0x1.ec7b328ea92bcp-3,
+0x1.a6225e117f92ep-3,
+#endif
+},
+/* Algorithm:
+
+	x = 2^k z
+	log2(x) = k + log2(c) + log2(z/c)
+	log2(z/c) = poly(z/c - 1)
+
+where z is in [1.6p-1; 1.6p0] which is split into N subintervals and z falls
+into the ith one, then table entries are computed as
+
+	tab[i].invc = 1/c
+	tab[i].logc = (double)log2(c)
+	tab2[i].chi = (double)c
+	tab2[i].clo = (double)(c - (double)c)
+
+where c is near the center of the subinterval and is chosen by trying +-2^29
+floating point invc candidates around 1/center and selecting one for which
+
+	1) the rounding error in 0x1.8p10 + logc is 0,
+	2) the rounding error in z - chi - clo is < 0x1p-64 and
+	3) the rounding error in (double)log2(c) is minimized (< 0x1p-68).
+
+Note: 1) ensures that k + logc can be computed without rounding error, 2)
+ensures that z/c - 1 can be computed as (z - chi - clo)*invc with close to a
+single rounding error when there is no fast fma for z*invc - 1, 3) ensures
+that logc + poly(z/c - 1) has small error, however near x == 1 when
+|log2(x)| < 0x1p-4, this is not enough so that is special cased.  */
+.tab = {
+#if N == 64
+{0x1.724286bb1acf8p+0, -0x1.1095feecdb000p-1},
+{0x1.6e1f766d2cca1p+0, -0x1.08494bd76d000p-1},
+{0x1.6a13d0e30d48ap+0, -0x1.00143aee8f800p-1},
+{0x1.661ec32d06c85p+0, -0x1.efec5360b4000p-2},
+{0x1.623fa951198f8p+0, -0x1.dfdd91ab7e000p-2},
+{0x1.5e75ba4cf026cp+0, -0x1.cffae0cc79000p-2},
+{0x1.5ac055a214fb8p+0, -0x1.c043811fda000p-2},
+{0x1.571ed0f166e1ep+0, -0x1.b0b67323ae000p-2},
+{0x1.53909590bf835p+0, -0x1.a152f5a2db000p-2},
+{0x1.5014fed61adddp+0, -0x1.9217f5af86000p-2},
+{0x1.4cab88e487bd0p+0, -0x1.8304db0719000p-2},
+{0x1.49539b4334feep+0, -0x1.74189f9a9e000p-2},
+{0x1.460cbdfafd569p+0, -0x1.6552bb5199000p-2},
+{0x1.42d664ee4b953p+0, -0x1.56b23a29b1000p-2},
+{0x1.3fb01111dd8a6p+0, -0x1.483650f5fa000p-2},
+{0x1.3c995b70c5836p+0, -0x1.39de937f6a000p-2},
+{0x1.3991c4ab6fd4ap+0, -0x1.2baa1538d6000p-2},
+{0x1.3698e0ce099b5p+0, -0x1.1d98340ca4000p-2},
+{0x1.33ae48213e7b2p+0, -0x1.0fa853a40e000p-2},
+{0x1.30d191985bdb1p+0, -0x1.01d9c32e73000p-2},
+{0x1.2e025cab271d7p+0, -0x1.e857da2fa6000p-3},
+{0x1.2b404cf13cd82p+0, -0x1.cd3c8633d8000p-3},
+{0x1.288b02c7ccb50p+0, -0x1.b26034c14a000p-3},
+{0x1.25e2263944de5p+0, -0x1.97c1c2f4fe000p-3},
+{0x1.234563d8615b1p+0, -0x1.7d6023f800000p-3},
+{0x1.20b46e33eaf38p+0, -0x1.633a71a05e000p-3},
+{0x1.1e2eefdcda3ddp+0, -0x1.494f5e9570000p-3},
+{0x1.1bb4a580b3930p+0, -0x1.2f9e424e0a000p-3},
+{0x1.19453847f2200p+0, -0x1.162595afdc000p-3},
+{0x1.16e06c0d5d73cp+0, -0x1.f9c9a75bd8000p-4},
+{0x1.1485f47b7e4c2p+0, -0x1.c7b575bf9c000p-4},
+{0x1.12358ad0085d1p+0, -0x1.960c60ff48000p-4},
+{0x1.0fef00f532227p+0, -0x1.64ce247b60000p-4},
+{0x1.0db2077d03a8fp+0, -0x1.33f78b2014000p-4},
+{0x1.0b7e6d65980d9p+0, -0x1.0387d1a42c000p-4},
+{0x1.0953efe7b408dp+0, -0x1.a6f9208b50000p-5},
+{0x1.07325cac53b83p+0, -0x1.47a954f770000p-5},
+{0x1.05197e40d1b5cp+0, -0x1.d23a8c50c0000p-6},
+{0x1.03091c1208ea2p+0, -0x1.16a2629780000p-6},
+{0x1.0101025b37e21p+0, -0x1.720f8d8e80000p-8},
+{0x1.fc07ef9caa76bp-1, 0x1.6fe53b1500000p-7},
+{0x1.f4465d3f6f184p-1, 0x1.11ccce10f8000p-5},
+{0x1.ecc079f84107fp-1, 0x1.c4dfc8c8b8000p-5},
+{0x1.e573a99975ae8p-1, 0x1.3aa321e574000p-4},
+{0x1.de5d6f0bd3de6p-1, 0x1.918a0d08b8000p-4},
+{0x1.d77b681ff38b3p-1, 0x1.e72e9da044000p-4},
+{0x1.d0cb5724de943p-1, 0x1.1dcd2507f6000p-3},
+{0x1.ca4b2dc0e7563p-1, 0x1.476ab03dea000p-3},
+{0x1.c3f8ee8d6cb51p-1, 0x1.7074377e22000p-3},
+{0x1.bdd2b4f020c4cp-1, 0x1.98ede8ba94000p-3},
+{0x1.b7d6c006015cap-1, 0x1.c0db86ad2e000p-3},
+{0x1.b20366e2e338fp-1, 0x1.e840aafcee000p-3},
+{0x1.ac57026295039p-1, 0x1.0790ab4678000p-2},
+{0x1.a6d01bc2731ddp-1, 0x1.1ac056801c000p-2},
+{0x1.a16d3bc3ff18bp-1, 0x1.2db11d4fee000p-2},
+{0x1.9c2d14967feadp-1, 0x1.406464ec58000p-2},
+{0x1.970e4f47c9902p-1, 0x1.52dbe093af000p-2},
+{0x1.920fb3982bcf2p-1, 0x1.651902050d000p-2},
+{0x1.8d30187f759f1p-1, 0x1.771d2cdeaf000p-2},
+{0x1.886e5ebb9f66dp-1, 0x1.88e9c857d9000p-2},
+{0x1.83c97b658b994p-1, 0x1.9a80155e16000p-2},
+{0x1.7f405ffc61022p-1, 0x1.abe186ed3d000p-2},
+{0x1.7ad22181415cap-1, 0x1.bd0f2aea0e000p-2},
+{0x1.767dcf99eff8cp-1, 0x1.ce0a43dbf4000p-2},
+#endif
+},
+#if !HAVE_FAST_FMA
+.tab2 = {
+# if N == 64
+{0x1.6200012b90a8ep-1, 0x1.904ab0644b605p-55},
+{0x1.66000045734a6p-1, 0x1.1ff9bea62f7a9p-57},
+{0x1.69fffc325f2c5p-1, 0x1.27ecfcb3c90bap-55},
+{0x1.6e00038b95a04p-1, 0x1.8ff8856739326p-55},
+{0x1.71fffe09994e3p-1, 0x1.afd40275f82b1p-55},
+{0x1.7600015590e1p-1, -0x1.2fd75b4238341p-56},
+{0x1.7a00012655bd5p-1, 0x1.808e67c242b76p-56},
+{0x1.7e0003259e9a6p-1, -0x1.208e426f622b7p-57},
+{0x1.81fffedb4b2d2p-1, -0x1.402461ea5c92fp-55},
+{0x1.860002dfafcc3p-1, 0x1.df7f4a2f29a1fp-57},
+{0x1.89ffff78c6b5p-1, -0x1.e0453094995fdp-55},
+{0x1.8e00039671566p-1, -0x1.a04f3bec77b45p-55},
+{0x1.91fffe2bf1745p-1, -0x1.7fa34400e203cp-56},
+{0x1.95fffcc5c9fd1p-1, -0x1.6ff8005a0695dp-56},
+{0x1.9a0003bba4767p-1, 0x1.0f8c4c4ec7e03p-56},
+{0x1.9dfffe7b92da5p-1, 0x1.e7fd9478c4602p-55},
+{0x1.a1fffd72efdafp-1, -0x1.a0c554dcdae7ep-57},
+{0x1.a5fffde04ff95p-1, 0x1.67da98ce9b26bp-55},
+{0x1.a9fffca5e8d2bp-1, -0x1.284c9b54c13dep-55},
+{0x1.adfffddad03eap-1, 0x1.812c8ea602e3cp-58},
+{0x1.b1ffff10d3d4dp-1, -0x1.efaddad27789cp-55},
+{0x1.b5fffce21165ap-1, 0x1.3cb1719c61237p-58},
+{0x1.b9fffd950e674p-1, 0x1.3f7d94194cep-56},
+{0x1.be000139ca8afp-1, 0x1.50ac4215d9bcp-56},
+{0x1.c20005b46df99p-1, 0x1.beea653e9c1c9p-57},
+{0x1.c600040b9f7aep-1, -0x1.c079f274a70d6p-56},
+{0x1.ca0006255fd8ap-1, -0x1.a0b4076e84c1fp-56},
+{0x1.cdfffd94c095dp-1, 0x1.8f933f99ab5d7p-55},
+{0x1.d1ffff975d6cfp-1, -0x1.82c08665fe1bep-58},
+{0x1.d5fffa2561c93p-1, -0x1.b04289bd295f3p-56},
+{0x1.d9fff9d228b0cp-1, 0x1.70251340fa236p-55},
+{0x1.de00065bc7e16p-1, -0x1.5011e16a4d80cp-56},
+{0x1.e200002f64791p-1, 0x1.9802f09ef62ep-55},
+{0x1.e600057d7a6d8p-1, -0x1.e0b75580cf7fap-56},
+{0x1.ea00027edc00cp-1, -0x1.c848309459811p-55},
+{0x1.ee0006cf5cb7cp-1, -0x1.f8027951576f4p-55},
+{0x1.f2000782b7dccp-1, -0x1.f81d97274538fp-55},
+{0x1.f6000260c450ap-1, -0x1.071002727ffdcp-59},
+{0x1.f9fffe88cd533p-1, -0x1.81bdce1fda8bp-58},
+{0x1.fdfffd50f8689p-1, 0x1.7f91acb918e6ep-55},
+{0x1.0200004292367p+0, 0x1.b7ff365324681p-54},
+{0x1.05fffe3e3d668p+0, 0x1.6fa08ddae957bp-55},
+{0x1.0a0000a85a757p+0, -0x1.7e2de80d3fb91p-58},
+{0x1.0e0001a5f3fccp+0, -0x1.1823305c5f014p-54},
+{0x1.11ffff8afbaf5p+0, -0x1.bfabb6680bac2p-55},
+{0x1.15fffe54d91adp+0, -0x1.d7f121737e7efp-54},
+{0x1.1a00011ac36e1p+0, 0x1.c000a0516f5ffp-54},
+{0x1.1e00019c84248p+0, -0x1.082fbe4da5dap-54},
+{0x1.220000ffe5e6ep+0, -0x1.8fdd04c9cfb43p-55},
+{0x1.26000269fd891p+0, 0x1.cfe2a7994d182p-55},
+{0x1.2a00029a6e6dap+0, -0x1.00273715e8bc5p-56},
+{0x1.2dfffe0293e39p+0, 0x1.b7c39dab2a6f9p-54},
+{0x1.31ffff7dcf082p+0, 0x1.df1336edc5254p-56},
+{0x1.35ffff05a8b6p+0, -0x1.e03564ccd31ebp-54},
+{0x1.3a0002e0eaeccp+0, 0x1.5f0e74bd3a477p-56},
+{0x1.3e000043bb236p+0, 0x1.c7dcb149d8833p-54},
+{0x1.4200002d187ffp+0, 0x1.e08afcf2d3d28p-56},
+{0x1.460000d387cb1p+0, 0x1.20837856599a6p-55},
+{0x1.4a00004569f89p+0, -0x1.9fa5c904fbcd2p-55},
+{0x1.4e000043543f3p+0, -0x1.81125ed175329p-56},
+{0x1.51fffcc027f0fp+0, 0x1.883d8847754dcp-54},
+{0x1.55ffffd87b36fp+0, -0x1.709e731d02807p-55},
+{0x1.59ffff21df7bap+0, 0x1.7f79f68727b02p-55},
+{0x1.5dfffebfc3481p+0, -0x1.180902e30e93ep-54},
+# endif
+},
+#endif /* !HAVE_FAST_FMA */
+};
diff --git a/libc/AOR_v20.02/math/log2f.c b/libc/AOR_v20.02/math/log2f.c
new file mode 100644
index 0000000000000..a43814f9827c0
--- /dev/null
+++ b/libc/AOR_v20.02/math/log2f.c
@@ -0,0 +1,81 @@
+/*
+ * Single-precision log2 function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+/*
+LOG2F_TABLE_BITS = 4
+LOG2F_POLY_ORDER = 4
+
+ULP error: 0.752 (nearest rounding.)
+Relative error: 1.9 * 2^-26 (before rounding.)
+*/
+
+#define N (1 << LOG2F_TABLE_BITS)
+#define T __log2f_data.tab
+#define A __log2f_data.poly
+#define OFF 0x3f330000
+
+float
+log2f (float x)
+{
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t z, r, r2, p, y, y0, invc, logc;
+  uint32_t ix, iz, top, tmp;
+  int k, i;
+
+  ix = asuint (x);
+#if WANT_ROUNDING
+  /* Fix sign of zero with downward rounding when x==1.  */
+  if (unlikely (ix == 0x3f800000))
+    return 0;
+#endif
+  if (unlikely (ix - 0x00800000 >= 0x7f800000 - 0x00800000))
+    {
+      /* x < 0x1p-126 or inf or nan.  */
+      if (ix * 2 == 0)
+	return __math_divzerof (1);
+      if (ix == 0x7f800000) /* log2(inf) == inf.  */
+	return x;
+      if ((ix & 0x80000000) || ix * 2 >= 0xff000000)
+	return __math_invalidf (x);
+      /* x is subnormal, normalize it.  */
+      ix = asuint (x * 0x1p23f);
+      ix -= 23 << 23;
+    }
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF] and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (23 - LOG2F_TABLE_BITS)) % N;
+  top = tmp & 0xff800000;
+  iz = ix - top;
+  k = (int32_t) tmp >> 23; /* arithmetic shift */
+  invc = T[i].invc;
+  logc = T[i].logc;
+  z = (double_t) asfloat (iz);
+
+  /* log2(x) = log1p(z/c-1)/ln2 + log2(c) + k */
+  r = z * invc - 1;
+  y0 = logc + (double_t) k;
+
+  /* Pipelined polynomial evaluation to approximate log1p(r)/ln2.  */
+  r2 = r * r;
+  y = A[1] * r + A[2];
+  y = A[0] * r2 + y;
+  p = A[3] * r + y0;
+  y = y * r2 + p;
+  return eval_as_float (y);
+}
+#if USE_GLIBC_ABI
+strong_alias (log2f, __log2f_finite)
+hidden_alias (log2f, __ieee754_log2f)
+#endif
diff --git a/libc/AOR_v20.02/math/log2f_data.c b/libc/AOR_v20.02/math/log2f_data.c
new file mode 100644
index 0000000000000..f8f270db40156
--- /dev/null
+++ b/libc/AOR_v20.02/math/log2f_data.c
@@ -0,0 +1,34 @@
+/*
+ * Data definition for log2f.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+const struct log2f_data __log2f_data = {
+  .tab = {
+  { 0x1.661ec79f8f3bep+0, -0x1.efec65b963019p-2 },
+  { 0x1.571ed4aaf883dp+0, -0x1.b0b6832d4fca4p-2 },
+  { 0x1.49539f0f010bp+0, -0x1.7418b0a1fb77bp-2 },
+  { 0x1.3c995b0b80385p+0, -0x1.39de91a6dcf7bp-2 },
+  { 0x1.30d190c8864a5p+0, -0x1.01d9bf3f2b631p-2 },
+  { 0x1.25e227b0b8eap+0, -0x1.97c1d1b3b7afp-3 },
+  { 0x1.1bb4a4a1a343fp+0, -0x1.2f9e393af3c9fp-3 },
+  { 0x1.12358f08ae5bap+0, -0x1.960cbbf788d5cp-4 },
+  { 0x1.0953f419900a7p+0, -0x1.a6f9db6475fcep-5 },
+  { 0x1p+0, 0x0p+0 },
+  { 0x1.e608cfd9a47acp-1, 0x1.338ca9f24f53dp-4 },
+  { 0x1.ca4b31f026aap-1, 0x1.476a9543891bap-3 },
+  { 0x1.b2036576afce6p-1, 0x1.e840b4ac4e4d2p-3 },
+  { 0x1.9c2d163a1aa2dp-1, 0x1.40645f0c6651cp-2 },
+  { 0x1.886e6037841edp-1, 0x1.88e9c2c1b9ff8p-2 },
+  { 0x1.767dcf5534862p-1, 0x1.ce0a44eb17bccp-2 },
+  },
+  .poly = {
+  -0x1.712b6f70a7e4dp-2, 0x1.ecabf496832ep-2, -0x1.715479ffae3dep-1,
+  0x1.715475f35c8b8p0,
+  }
+};
diff --git a/libc/AOR_v20.02/math/log_data.c b/libc/AOR_v20.02/math/log_data.c
new file mode 100644
index 0000000000000..26fc9dfca60c2
--- /dev/null
+++ b/libc/AOR_v20.02/math/log_data.c
@@ -0,0 +1,512 @@
+/*
+ * Data for log.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#define N (1 << LOG_TABLE_BITS)
+
+const struct log_data __log_data = {
+.ln2hi = 0x1.62e42fefa3800p-1,
+.ln2lo = 0x1.ef35793c76730p-45,
+.poly1 = {
+#if LOG_POLY1_ORDER == 10
+// relative error: 0x1.32eccc6p-62
+// in -0x1p-5 0x1.1p-5 (|log(1+x)| > 0x1p-5 outside this interval)
+-0x1p-1,
+0x1.55555555554e5p-2,
+-0x1.0000000000af2p-2,
+0x1.9999999bbe436p-3,
+-0x1.55555537f9cdep-3,
+0x1.24922fc8127cfp-3,
+-0x1.0000b7d6bb612p-3,
+0x1.c806ee1ddbcafp-4,
+-0x1.972335a9c2d6ep-4,
+#elif LOG_POLY1_ORDER == 11
+// relative error: 0x1.52c8b708p-68
+// in -0x1p-5 0x1.1p-5 (|log(1+x)| > 0x1p-5 outside this interval)
+-0x1p-1,
+0x1.5555555555555p-2,
+-0x1.ffffffffffea9p-3,
+0x1.999999999c4d4p-3,
+-0x1.55555557f5541p-3,
+0x1.249248fbe33e4p-3,
+-0x1.ffffc9a3c825bp-4,
+0x1.c71e1f204435dp-4,
+-0x1.9a7f26377d06ep-4,
+0x1.71c30cf8f7364p-4,
+#elif LOG_POLY1_ORDER == 12
+// relative error: 0x1.c04d76cp-63
+// in -0x1p-4 0x1.09p-4 (|log(1+x)| > 0x1p-4 outside the interval)
+-0x1p-1,
+0x1.5555555555577p-2,
+-0x1.ffffffffffdcbp-3,
+0x1.999999995dd0cp-3,
+-0x1.55555556745a7p-3,
+0x1.24924a344de3p-3,
+-0x1.fffffa4423d65p-4,
+0x1.c7184282ad6cap-4,
+-0x1.999eb43b068ffp-4,
+0x1.78182f7afd085p-4,
+-0x1.5521375d145cdp-4,
+#endif
+},
+.poly = {
+#if N == 64 && LOG_POLY_ORDER == 7
+// relative error: 0x1.906eb8ap-58
+// abs error: 0x1.d2cad5a8p-67
+// in -0x1.fp-8 0x1.fp-8
+-0x1.0000000000027p-1,
+0x1.555555555556ap-2,
+-0x1.fffffff0440bap-3,
+0x1.99999991906c3p-3,
+-0x1.555c8d7e8201ep-3,
+0x1.24978c59151fap-3,
+#elif N == 128 && LOG_POLY_ORDER == 6
+// relative error: 0x1.926199e8p-56
+// abs error: 0x1.882ff33p-65
+// in -0x1.fp-9 0x1.fp-9
+-0x1.0000000000001p-1,
+0x1.555555551305bp-2,
+-0x1.fffffffeb459p-3,
+0x1.999b324f10111p-3,
+-0x1.55575e506c89fp-3,
+#elif N == 128 && LOG_POLY_ORDER == 7
+// relative error: 0x1.649fc4bp-64
+// abs error: 0x1.c3b5769p-74
+// in -0x1.fp-9 0x1.fp-9
+-0x1.0000000000001p-1,
+0x1.5555555555556p-2,
+-0x1.fffffffea1a8p-3,
+0x1.99999998e9139p-3,
+-0x1.555776801b968p-3,
+0x1.2493c29331a5cp-3,
+#endif
+},
+/* Algorithm:
+
+	x = 2^k z
+	log(x) = k ln2 + log(c) + log(z/c)
+	log(z/c) = poly(z/c - 1)
+
+where z is in [1.6p-1; 1.6p0] which is split into N subintervals and z falls
+into the ith one, then table entries are computed as
+
+	tab[i].invc = 1/c
+	tab[i].logc = (double)log(c)
+	tab2[i].chi = (double)c
+	tab2[i].clo = (double)(c - (double)c)
+
+where c is near the center of the subinterval and is chosen by trying +-2^29
+floating point invc candidates around 1/center and selecting one for which
+
+	1) the rounding error in 0x1.8p9 + logc is 0,
+	2) the rounding error in z - chi - clo is < 0x1p-66 and
+	3) the rounding error in (double)log(c) is minimized (< 0x1p-66).
+
+Note: 1) ensures that k*ln2hi + logc can be computed without rounding error,
+2) ensures that z/c - 1 can be computed as (z - chi - clo)*invc with close to
+a single rounding error when there is no fast fma for z*invc - 1, 3) ensures
+that logc + poly(z/c - 1) has small error, however near x == 1 when
+|log(x)| < 0x1p-4, this is not enough so that is special cased.  */
+.tab = {
+#if N == 64
+{0x1.7242886495cd8p+0, -0x1.79e267bdfe000p-2},
+{0x1.6e1f769340dc9p+0, -0x1.6e60ee0ecb000p-2},
+{0x1.6a13ccc8f195cp+0, -0x1.63002fdbf6000p-2},
+{0x1.661ec72e86f3ap+0, -0x1.57bf76c597000p-2},
+{0x1.623fa6c447b16p+0, -0x1.4c9e07f0d2000p-2},
+{0x1.5e75bbca31702p+0, -0x1.419b42f027000p-2},
+{0x1.5ac05655adb10p+0, -0x1.36b67660e6000p-2},
+{0x1.571ed3e940191p+0, -0x1.2bef0839e4800p-2},
+{0x1.539094ac0fbbfp+0, -0x1.21445727cb000p-2},
+{0x1.5015007e7fc42p+0, -0x1.16b5ca3c3d000p-2},
+{0x1.4cab877c31cf9p+0, -0x1.0c42d3805f800p-2},
+{0x1.49539e76a88d3p+0, -0x1.01eae61b60800p-2},
+{0x1.460cbc12211dap+0, -0x1.ef5adb9fb0000p-3},
+{0x1.42d6624debe3ap+0, -0x1.db13daab99000p-3},
+{0x1.3fb0144f0d462p+0, -0x1.c6ffbe896e000p-3},
+{0x1.3c995a1f9a9b4p+0, -0x1.b31d84722d000p-3},
+{0x1.3991c23952500p+0, -0x1.9f6c3cf6eb000p-3},
+{0x1.3698df35eaa14p+0, -0x1.8beafe7f13000p-3},
+{0x1.33ae463091760p+0, -0x1.7898db878d000p-3},
+{0x1.30d190aae3d72p+0, -0x1.6574efe4ec000p-3},
+{0x1.2e025c9203c89p+0, -0x1.527e620845000p-3},
+{0x1.2b404a7244988p+0, -0x1.3fb457d798000p-3},
+{0x1.288b01dc19544p+0, -0x1.2d1615a077000p-3},
+{0x1.25e2268085f69p+0, -0x1.1aa2b431e5000p-3},
+{0x1.23456812abb74p+0, -0x1.08598f1d2b000p-3},
+{0x1.20b4703174157p+0, -0x1.ec738fee40000p-4},
+{0x1.1e2ef308b4e9bp+0, -0x1.c885768862000p-4},
+{0x1.1bb4a36b70a3fp+0, -0x1.a4e75b6a46000p-4},
+{0x1.194538e960658p+0, -0x1.8197efba9a000p-4},
+{0x1.16e0692a10ac8p+0, -0x1.5e95ad734e000p-4},
+{0x1.1485f1ba1568bp+0, -0x1.3bdf67117c000p-4},
+{0x1.12358e123ed6fp+0, -0x1.1973b744f0000p-4},
+{0x1.0fef01de37c8dp+0, -0x1.eea33446bc000p-5},
+{0x1.0db20b82be414p+0, -0x1.aaef4ab304000p-5},
+{0x1.0b7e6f67f69b3p+0, -0x1.67c962fd2c000p-5},
+{0x1.0953f342fc108p+0, -0x1.252f29acf8000p-5},
+{0x1.0732604ec956bp+0, -0x1.c63d19e9c0000p-6},
+{0x1.051980117f9b0p+0, -0x1.432ab6a388000p-6},
+{0x1.03091aa6810f1p+0, -0x1.8244357f50000p-7},
+{0x1.01010152cf066p+0, -0x1.0080a711c0000p-8},
+{0x1.fc07ef6b6e30bp-1, 0x1.fe03018e80000p-8},
+{0x1.f4465aa1024afp-1, 0x1.7b91986450000p-6},
+{0x1.ecc07a8fd3f5ep-1, 0x1.39e88608c8000p-5},
+{0x1.e573ad856b537p-1, 0x1.b42dc6e624000p-5},
+{0x1.de5d6dc7b8057p-1, 0x1.165372ec20000p-4},
+{0x1.d77b6498bddf7p-1, 0x1.51b07a0170000p-4},
+{0x1.d0cb580315c0fp-1, 0x1.8c3465c7ea000p-4},
+{0x1.ca4b30d1cf449p-1, 0x1.c5e544a290000p-4},
+{0x1.c3f8ef4810d8ep-1, 0x1.fec91aa0a6000p-4},
+{0x1.bdd2b8b311f44p-1, 0x1.1b72acdc5c000p-3},
+{0x1.b7d6c2eeac054p-1, 0x1.371fc65a98000p-3},
+{0x1.b20363474c8f5p-1, 0x1.526e61c1aa000p-3},
+{0x1.ac570165eeab1p-1, 0x1.6d60ffc240000p-3},
+{0x1.a6d019f331df4p-1, 0x1.87fa08a013000p-3},
+{0x1.a16d3ebc9e3c3p-1, 0x1.a23bc630c3000p-3},
+{0x1.9c2d14567ef45p-1, 0x1.bc286a3512000p-3},
+{0x1.970e4efae9169p-1, 0x1.d5c2195697000p-3},
+{0x1.920fb3bd0b802p-1, 0x1.ef0ae132d3000p-3},
+{0x1.8d3018b58699ap-1, 0x1.040259974e000p-2},
+{0x1.886e5ff170ee6p-1, 0x1.1058bd40e2000p-2},
+{0x1.83c977ad35d27p-1, 0x1.1c898c1137800p-2},
+{0x1.7f405ed16c520p-1, 0x1.2895a3e65b000p-2},
+{0x1.7ad220d0335c4p-1, 0x1.347dd8f6bd000p-2},
+{0x1.767dce53474fdp-1, 0x1.4043083cb3800p-2},
+#elif N == 128
+{0x1.734f0c3e0de9fp+0, -0x1.7cc7f79e69000p-2},
+{0x1.713786a2ce91fp+0, -0x1.76feec20d0000p-2},
+{0x1.6f26008fab5a0p+0, -0x1.713e31351e000p-2},
+{0x1.6d1a61f138c7dp+0, -0x1.6b85b38287800p-2},
+{0x1.6b1490bc5b4d1p+0, -0x1.65d5590807800p-2},
+{0x1.69147332f0cbap+0, -0x1.602d076180000p-2},
+{0x1.6719f18224223p+0, -0x1.5a8ca86909000p-2},
+{0x1.6524f99a51ed9p+0, -0x1.54f4356035000p-2},
+{0x1.63356aa8f24c4p+0, -0x1.4f637c36b4000p-2},
+{0x1.614b36b9ddc14p+0, -0x1.49da7fda85000p-2},
+{0x1.5f66452c65c4cp+0, -0x1.445923989a800p-2},
+{0x1.5d867b5912c4fp+0, -0x1.3edf439b0b800p-2},
+{0x1.5babccb5b90dep+0, -0x1.396ce448f7000p-2},
+{0x1.59d61f2d91a78p+0, -0x1.3401e17bda000p-2},
+{0x1.5805612465687p+0, -0x1.2e9e2ef468000p-2},
+{0x1.56397cee76bd3p+0, -0x1.2941b3830e000p-2},
+{0x1.54725e2a77f93p+0, -0x1.23ec58cda8800p-2},
+{0x1.52aff42064583p+0, -0x1.1e9e129279000p-2},
+{0x1.50f22dbb2bddfp+0, -0x1.1956d2b48f800p-2},
+{0x1.4f38f4734ded7p+0, -0x1.141679ab9f800p-2},
+{0x1.4d843cfde2840p+0, -0x1.0edd094ef9800p-2},
+{0x1.4bd3ec078a3c8p+0, -0x1.09aa518db1000p-2},
+{0x1.4a27fc3e0258ap+0, -0x1.047e65263b800p-2},
+{0x1.4880524d48434p+0, -0x1.feb224586f000p-3},
+{0x1.46dce1b192d0bp+0, -0x1.f474a7517b000p-3},
+{0x1.453d9d3391854p+0, -0x1.ea4443d103000p-3},
+{0x1.43a2744b4845ap+0, -0x1.e020d44e9b000p-3},
+{0x1.420b54115f8fbp+0, -0x1.d60a22977f000p-3},
+{0x1.40782da3ef4b1p+0, -0x1.cc00104959000p-3},
+{0x1.3ee8f5d57fe8fp+0, -0x1.c202956891000p-3},
+{0x1.3d5d9a00b4ce9p+0, -0x1.b81178d811000p-3},
+{0x1.3bd60c010c12bp+0, -0x1.ae2c9ccd3d000p-3},
+{0x1.3a5242b75dab8p+0, -0x1.a45402e129000p-3},
+{0x1.38d22cd9fd002p+0, -0x1.9a877681df000p-3},
+{0x1.3755bc5847a1cp+0, -0x1.90c6d69483000p-3},
+{0x1.35dce49ad36e2p+0, -0x1.87120a645c000p-3},
+{0x1.34679984dd440p+0, -0x1.7d68fb4143000p-3},
+{0x1.32f5cceffcb24p+0, -0x1.73cb83c627000p-3},
+{0x1.3187775a10d49p+0, -0x1.6a39a9b376000p-3},
+{0x1.301c8373e3990p+0, -0x1.60b3154b7a000p-3},
+{0x1.2eb4ebb95f841p+0, -0x1.5737d76243000p-3},
+{0x1.2d50a0219a9d1p+0, -0x1.4dc7b8fc23000p-3},
+{0x1.2bef9a8b7fd2ap+0, -0x1.4462c51d20000p-3},
+{0x1.2a91c7a0c1babp+0, -0x1.3b08abc830000p-3},
+{0x1.293726014b530p+0, -0x1.31b996b490000p-3},
+{0x1.27dfa5757a1f5p+0, -0x1.2875490a44000p-3},
+{0x1.268b39b1d3bbfp+0, -0x1.1f3b9f879a000p-3},
+{0x1.2539d838ff5bdp+0, -0x1.160c8252ca000p-3},
+{0x1.23eb7aac9083bp+0, -0x1.0ce7f57f72000p-3},
+{0x1.22a012ba940b6p+0, -0x1.03cdc49fea000p-3},
+{0x1.2157996cc4132p+0, -0x1.f57bdbc4b8000p-4},
+{0x1.201201dd2fc9bp+0, -0x1.e370896404000p-4},
+{0x1.1ecf4494d480bp+0, -0x1.d17983ef94000p-4},
+{0x1.1d8f5528f6569p+0, -0x1.bf9674ed8a000p-4},
+{0x1.1c52311577e7cp+0, -0x1.adc79202f6000p-4},
+{0x1.1b17c74cb26e9p+0, -0x1.9c0c3e7288000p-4},
+{0x1.19e010c2c1ab6p+0, -0x1.8a646b372c000p-4},
+{0x1.18ab07bb670bdp+0, -0x1.78d01b3ac0000p-4},
+{0x1.1778a25efbcb6p+0, -0x1.674f145380000p-4},
+{0x1.1648d354c31dap+0, -0x1.55e0e6d878000p-4},
+{0x1.151b990275fddp+0, -0x1.4485cdea1e000p-4},
+{0x1.13f0ea432d24cp+0, -0x1.333d94d6aa000p-4},
+{0x1.12c8b7210f9dap+0, -0x1.22079f8c56000p-4},
+{0x1.11a3028ecb531p+0, -0x1.10e4698622000p-4},
+{0x1.107fbda8434afp+0, -0x1.ffa6c6ad20000p-5},
+{0x1.0f5ee0f4e6bb3p+0, -0x1.dda8d4a774000p-5},
+{0x1.0e4065d2a9fcep+0, -0x1.bbcece4850000p-5},
+{0x1.0d244632ca521p+0, -0x1.9a1894012c000p-5},
+{0x1.0c0a77ce2981ap+0, -0x1.788583302c000p-5},
+{0x1.0af2f83c636d1p+0, -0x1.5715e67d68000p-5},
+{0x1.09ddb98a01339p+0, -0x1.35c8a49658000p-5},
+{0x1.08cabaf52e7dfp+0, -0x1.149e364154000p-5},
+{0x1.07b9f2f4e28fbp+0, -0x1.e72c082eb8000p-6},
+{0x1.06ab58c358f19p+0, -0x1.a55f152528000p-6},
+{0x1.059eea5ecf92cp+0, -0x1.63d62cf818000p-6},
+{0x1.04949cdd12c90p+0, -0x1.228fb8caa0000p-6},
+{0x1.038c6c6f0ada9p+0, -0x1.c317b20f90000p-7},
+{0x1.02865137932a9p+0, -0x1.419355daa0000p-7},
+{0x1.0182427ea7348p+0, -0x1.81203c2ec0000p-8},
+{0x1.008040614b195p+0, -0x1.0040979240000p-9},
+{0x1.fe01ff726fa1ap-1, 0x1.feff384900000p-9},
+{0x1.fa11cc261ea74p-1, 0x1.7dc41353d0000p-7},
+{0x1.f6310b081992ep-1, 0x1.3cea3c4c28000p-6},
+{0x1.f25f63ceeadcdp-1, 0x1.b9fc114890000p-6},
+{0x1.ee9c8039113e7p-1, 0x1.1b0d8ce110000p-5},
+{0x1.eae8078cbb1abp-1, 0x1.58a5bd001c000p-5},
+{0x1.e741aa29d0c9bp-1, 0x1.95c8340d88000p-5},
+{0x1.e3a91830a99b5p-1, 0x1.d276aef578000p-5},
+{0x1.e01e009609a56p-1, 0x1.07598e598c000p-4},
+{0x1.dca01e577bb98p-1, 0x1.253f5e30d2000p-4},
+{0x1.d92f20b7c9103p-1, 0x1.42edd8b380000p-4},
+{0x1.d5cac66fb5ccep-1, 0x1.606598757c000p-4},
+{0x1.d272caa5ede9dp-1, 0x1.7da76356a0000p-4},
+{0x1.cf26e3e6b2ccdp-1, 0x1.9ab434e1c6000p-4},
+{0x1.cbe6da2a77902p-1, 0x1.b78c7bb0d6000p-4},
+{0x1.c8b266d37086dp-1, 0x1.d431332e72000p-4},
+{0x1.c5894bd5d5804p-1, 0x1.f0a3171de6000p-4},
+{0x1.c26b533bb9f8cp-1, 0x1.067152b914000p-3},
+{0x1.bf583eeece73fp-1, 0x1.147858292b000p-3},
+{0x1.bc4fd75db96c1p-1, 0x1.2266ecdca3000p-3},
+{0x1.b951e0c864a28p-1, 0x1.303d7a6c55000p-3},
+{0x1.b65e2c5ef3e2cp-1, 0x1.3dfc33c331000p-3},
+{0x1.b374867c9888bp-1, 0x1.4ba366b7a8000p-3},
+{0x1.b094b211d304ap-1, 0x1.5933928d1f000p-3},
+{0x1.adbe885f2ef7ep-1, 0x1.66acd2418f000p-3},
+{0x1.aaf1d31603da2p-1, 0x1.740f8ec669000p-3},
+{0x1.a82e63fd358a7p-1, 0x1.815c0f51af000p-3},
+{0x1.a5740ef09738bp-1, 0x1.8e92954f68000p-3},
+{0x1.a2c2a90ab4b27p-1, 0x1.9bb3602f84000p-3},
+{0x1.a01a01393f2d1p-1, 0x1.a8bed1c2c0000p-3},
+{0x1.9d79f24db3c1bp-1, 0x1.b5b515c01d000p-3},
+{0x1.9ae2505c7b190p-1, 0x1.c2967ccbcc000p-3},
+{0x1.9852ef297ce2fp-1, 0x1.cf635d5486000p-3},
+{0x1.95cbaeea44b75p-1, 0x1.dc1bd3446c000p-3},
+{0x1.934c69de74838p-1, 0x1.e8c01b8cfe000p-3},
+{0x1.90d4f2f6752e6p-1, 0x1.f5509c0179000p-3},
+{0x1.8e6528effd79dp-1, 0x1.00e6c121fb800p-2},
+{0x1.8bfce9fcc007cp-1, 0x1.071b80e93d000p-2},
+{0x1.899c0dabec30ep-1, 0x1.0d46b9e867000p-2},
+{0x1.87427aa2317fbp-1, 0x1.13687334bd000p-2},
+{0x1.84f00acb39a08p-1, 0x1.1980d67234800p-2},
+{0x1.82a49e8653e55p-1, 0x1.1f8ffe0cc8000p-2},
+{0x1.8060195f40260p-1, 0x1.2595fd7636800p-2},
+{0x1.7e22563e0a329p-1, 0x1.2b9300914a800p-2},
+{0x1.7beb377dcb5adp-1, 0x1.3187210436000p-2},
+{0x1.79baa679725c2p-1, 0x1.377266dec1800p-2},
+{0x1.77907f2170657p-1, 0x1.3d54ffbaf3000p-2},
+{0x1.756cadbd6130cp-1, 0x1.432eee32fe000p-2},
+#endif
+},
+#if !HAVE_FAST_FMA
+.tab2 = {
+# if N == 64
+{0x1.61ffff94c4fecp-1, -0x1.9fe4fc998f325p-56},
+{0x1.66000020377ddp-1, 0x1.e804c7a9519f2p-55},
+{0x1.6a00004c41678p-1, 0x1.902c675d9ecfep-55},
+{0x1.6dffff7384f87p-1, -0x1.2fd6b95e55043p-56},
+{0x1.720000b37216ep-1, 0x1.802bc8d437043p-55},
+{0x1.75ffffbeb3c9dp-1, 0x1.6047ad0a0d4e4p-57},
+{0x1.7a0000628daep-1, -0x1.e00434b49313dp-56},
+{0x1.7dffffd7abd1ap-1, -0x1.6015f8a083576p-56},
+{0x1.81ffffdf40c54p-1, 0x1.7f54bf76a42c9p-57},
+{0x1.860000f334e11p-1, 0x1.60054cb5344d7p-56},
+{0x1.8a0001238aca7p-1, 0x1.c03c9bd132f55p-57},
+{0x1.8dffffb81d212p-1, -0x1.001e519f2764fp-55},
+{0x1.92000086adc7cp-1, 0x1.1fe40f88f49c6p-55},
+{0x1.960000135d8eap-1, -0x1.f832268dc3095p-55},
+{0x1.99ffff9435acp-1, 0x1.7031d8b835edcp-56},
+{0x1.9e00003478565p-1, -0x1.0030b221ce3eep-58},
+{0x1.a20000b592948p-1, 0x1.8fd2f1dbd4639p-55},
+{0x1.a600000ad0bcfp-1, 0x1.901d6a974e6bep-55},
+{0x1.a9ffff55953a5p-1, 0x1.a07556192db98p-57},
+{0x1.adffff29ce03dp-1, -0x1.fff0717ec71c2p-56},
+{0x1.b1ffff34f3ac8p-1, 0x1.8005573de89d1p-57},
+{0x1.b60000894c55bp-1, -0x1.ff2fb51b044c7p-57},
+{0x1.b9fffef45ec7dp-1, -0x1.9ff7c4e8730fp-56},
+{0x1.be0000cda7b2ap-1, 0x1.57d058dbf3c1dp-55},
+{0x1.c1ffff2c57917p-1, 0x1.7e66d7e48dbc9p-58},
+{0x1.c60000ea5b82ap-1, -0x1.47f5e132ed4bep-55},
+{0x1.ca0001121ae98p-1, -0x1.40958c8d5e00ap-58},
+{0x1.ce0000f9241cbp-1, -0x1.7da063caa81c8p-59},
+{0x1.d1fffe8be95a4p-1, -0x1.82e3a411afcd9p-59},
+{0x1.d5ffff035932bp-1, -0x1.00f901b3fe87dp-58},
+{0x1.d9fffe8b54ba7p-1, 0x1.ffef55d6e3a4p-55},
+{0x1.de0000ad95d19p-1, 0x1.5feb2efd4c7c7p-55},
+{0x1.e1fffe925ce47p-1, 0x1.c8085484eaf08p-55},
+{0x1.e5fffe3ddf853p-1, -0x1.fd5ed02c5cadp-60},
+{0x1.e9fffed0a0e5fp-1, -0x1.a80aaef411586p-55},
+{0x1.ee00008f82eep-1, -0x1.b000aeaf97276p-55},
+{0x1.f20000a22d2f4p-1, -0x1.8f8906e13eba3p-56},
+{0x1.f5fffee35b57dp-1, 0x1.1fdd33b2d3714p-57},
+{0x1.fa00014eec3a6p-1, -0x1.3ee0b7a18c1a5p-58},
+{0x1.fdffff5daa89fp-1, -0x1.c1e24c8e3b503p-58},
+{0x1.0200005b93349p+0, -0x1.50197fe6bedcap-54},
+{0x1.05ffff9d597acp+0, 0x1.20160d062d0dcp-55},
+{0x1.0a00005687a63p+0, -0x1.27f3f9307696ep-54},
+{0x1.0dffff779164ep+0, 0x1.b7eb40bb9c4f4p-54},
+{0x1.12000044a0aa8p+0, 0x1.efbc914d512c4p-55},
+{0x1.16000069685bcp+0, -0x1.c0bea3eb2d82cp-57},
+{0x1.1a000093f0d78p+0, 0x1.1fecbf1e8c52p-54},
+{0x1.1dffffb2b1457p+0, -0x1.3fc91365637d6p-55},
+{0x1.2200008824a1p+0, -0x1.dff7e9feb578ap-54},
+{0x1.25ffffeef953p+0, -0x1.b00a61ec912f7p-55},
+{0x1.2a0000a1e7783p+0, 0x1.60048318b0483p-56},
+{0x1.2e0000853d4c7p+0, -0x1.77fbedf2c8cf3p-54},
+{0x1.320000324c55bp+0, 0x1.f81983997354fp-54},
+{0x1.360000594f796p+0, -0x1.cfe4beff900a9p-54},
+{0x1.3a0000a4c1c0fp+0, 0x1.07dbb2e268d0ep-54},
+{0x1.3e0000751c61bp+0, 0x1.80583ed1c566ep-56},
+{0x1.42000069e8a9fp+0, 0x1.f01f1edf82045p-54},
+{0x1.460000b5a1e34p+0, -0x1.dfdf0cf45c14ap-55},
+{0x1.4a0000187e513p+0, 0x1.401306b83a98dp-55},
+{0x1.4dffff3ba420bp+0, 0x1.9fc6539a6454ep-56},
+{0x1.51fffffe391c9p+0, -0x1.601ef3353ac83p-54},
+{0x1.560000e342455p+0, 0x1.3fb7fac8ac151p-55},
+{0x1.59ffffc39676fp+0, 0x1.4fe7dd6659cc2p-55},
+{0x1.5dfffff10ef42p+0, -0x1.48154cb592bcbp-54},
+# elif N == 128
+{0x1.61000014fb66bp-1, 0x1.e026c91425b3cp-56},
+{0x1.63000034db495p-1, 0x1.dbfea48005d41p-55},
+{0x1.650000d94d478p-1, 0x1.e7fa786d6a5b7p-55},
+{0x1.67000074e6fadp-1, 0x1.1fcea6b54254cp-57},
+{0x1.68ffffedf0faep-1, -0x1.c7e274c590efdp-56},
+{0x1.6b0000763c5bcp-1, -0x1.ac16848dcda01p-55},
+{0x1.6d0001e5cc1f6p-1, 0x1.33f1c9d499311p-55},
+{0x1.6efffeb05f63ep-1, -0x1.e80041ae22d53p-56},
+{0x1.710000e86978p-1, 0x1.bff6671097952p-56},
+{0x1.72ffffc67e912p-1, 0x1.c00e226bd8724p-55},
+{0x1.74fffdf81116ap-1, -0x1.e02916ef101d2p-57},
+{0x1.770000f679c9p-1, -0x1.7fc71cd549c74p-57},
+{0x1.78ffffa7ec835p-1, 0x1.1bec19ef50483p-55},
+{0x1.7affffe20c2e6p-1, -0x1.07e1729cc6465p-56},
+{0x1.7cfffed3fc9p-1, -0x1.08072087b8b1cp-55},
+{0x1.7efffe9261a76p-1, 0x1.dc0286d9df9aep-55},
+{0x1.81000049ca3e8p-1, 0x1.97fd251e54c33p-55},
+{0x1.8300017932c8fp-1, -0x1.afee9b630f381p-55},
+{0x1.850000633739cp-1, 0x1.9bfbf6b6535bcp-55},
+{0x1.87000204289c6p-1, -0x1.bbf65f3117b75p-55},
+{0x1.88fffebf57904p-1, -0x1.9006ea23dcb57p-55},
+{0x1.8b00022bc04dfp-1, -0x1.d00df38e04b0ap-56},
+{0x1.8cfffe50c1b8ap-1, -0x1.8007146ff9f05p-55},
+{0x1.8effffc918e43p-1, 0x1.3817bd07a7038p-55},
+{0x1.910001efa5fc7p-1, 0x1.93e9176dfb403p-55},
+{0x1.9300013467bb9p-1, 0x1.f804e4b980276p-56},
+{0x1.94fffe6ee076fp-1, -0x1.f7ef0d9ff622ep-55},
+{0x1.96fffde3c12d1p-1, -0x1.082aa962638bap-56},
+{0x1.98ffff4458a0dp-1, -0x1.7801b9164a8efp-55},
+{0x1.9afffdd982e3ep-1, -0x1.740e08a5a9337p-55},
+{0x1.9cfffed49fb66p-1, 0x1.fce08c19bep-60},
+{0x1.9f00020f19c51p-1, -0x1.a3faa27885b0ap-55},
+{0x1.a10001145b006p-1, 0x1.4ff489958da56p-56},
+{0x1.a300007bbf6fap-1, 0x1.cbeab8a2b6d18p-55},
+{0x1.a500010971d79p-1, 0x1.8fecadd78793p-55},
+{0x1.a70001df52e48p-1, -0x1.f41763dd8abdbp-55},
+{0x1.a90001c593352p-1, -0x1.ebf0284c27612p-55},
+{0x1.ab0002a4f3e4bp-1, -0x1.9fd043cff3f5fp-57},
+{0x1.acfffd7ae1ed1p-1, -0x1.23ee7129070b4p-55},
+{0x1.aefffee510478p-1, 0x1.a063ee00edea3p-57},
+{0x1.b0fffdb650d5bp-1, 0x1.a06c8381f0ab9p-58},
+{0x1.b2ffffeaaca57p-1, -0x1.9011e74233c1dp-56},
+{0x1.b4fffd995badcp-1, -0x1.9ff1068862a9fp-56},
+{0x1.b7000249e659cp-1, 0x1.aff45d0864f3ep-55},
+{0x1.b8ffff987164p-1, 0x1.cfe7796c2c3f9p-56},
+{0x1.bafffd204cb4fp-1, -0x1.3ff27eef22bc4p-57},
+{0x1.bcfffd2415c45p-1, -0x1.cffb7ee3bea21p-57},
+{0x1.beffff86309dfp-1, -0x1.14103972e0b5cp-55},
+{0x1.c0fffe1b57653p-1, 0x1.bc16494b76a19p-55},
+{0x1.c2ffff1fa57e3p-1, -0x1.4feef8d30c6edp-57},
+{0x1.c4fffdcbfe424p-1, -0x1.43f68bcec4775p-55},
+{0x1.c6fffed54b9f7p-1, 0x1.47ea3f053e0ecp-55},
+{0x1.c8fffeb998fd5p-1, 0x1.383068df992f1p-56},
+{0x1.cb0002125219ap-1, -0x1.8fd8e64180e04p-57},
+{0x1.ccfffdd94469cp-1, 0x1.e7ebe1cc7ea72p-55},
+{0x1.cefffeafdc476p-1, 0x1.ebe39ad9f88fep-55},
+{0x1.d1000169af82bp-1, 0x1.57d91a8b95a71p-56},
+{0x1.d30000d0ff71dp-1, 0x1.9c1906970c7dap-55},
+{0x1.d4fffea790fc4p-1, -0x1.80e37c558fe0cp-58},
+{0x1.d70002edc87e5p-1, -0x1.f80d64dc10f44p-56},
+{0x1.d900021dc82aap-1, -0x1.47c8f94fd5c5cp-56},
+{0x1.dafffd86b0283p-1, 0x1.c7f1dc521617ep-55},
+{0x1.dd000296c4739p-1, 0x1.8019eb2ffb153p-55},
+{0x1.defffe54490f5p-1, 0x1.e00d2c652cc89p-57},
+{0x1.e0fffcdabf694p-1, -0x1.f8340202d69d2p-56},
+{0x1.e2fffdb52c8ddp-1, 0x1.b00c1ca1b0864p-56},
+{0x1.e4ffff24216efp-1, 0x1.2ffa8b094ab51p-56},
+{0x1.e6fffe88a5e11p-1, -0x1.7f673b1efbe59p-58},
+{0x1.e9000119eff0dp-1, -0x1.4808d5e0bc801p-55},
+{0x1.eafffdfa51744p-1, 0x1.80006d54320b5p-56},
+{0x1.ed0001a127fa1p-1, -0x1.002f860565c92p-58},
+{0x1.ef00007babcc4p-1, -0x1.540445d35e611p-55},
+{0x1.f0ffff57a8d02p-1, -0x1.ffb3139ef9105p-59},
+{0x1.f30001ee58ac7p-1, 0x1.a81acf2731155p-55},
+{0x1.f4ffff5823494p-1, 0x1.a3f41d4d7c743p-55},
+{0x1.f6ffffca94c6bp-1, -0x1.202f41c987875p-57},
+{0x1.f8fffe1f9c441p-1, 0x1.77dd1f477e74bp-56},
+{0x1.fafffd2e0e37ep-1, -0x1.f01199a7ca331p-57},
+{0x1.fd0001c77e49ep-1, 0x1.181ee4bceacb1p-56},
+{0x1.feffff7e0c331p-1, -0x1.e05370170875ap-57},
+{0x1.00ffff465606ep+0, -0x1.a7ead491c0adap-55},
+{0x1.02ffff3867a58p+0, -0x1.77f69c3fcb2ep-54},
+{0x1.04ffffdfc0d17p+0, 0x1.7bffe34cb945bp-54},
+{0x1.0700003cd4d82p+0, 0x1.20083c0e456cbp-55},
+{0x1.08ffff9f2cbe8p+0, -0x1.dffdfbe37751ap-57},
+{0x1.0b000010cda65p+0, -0x1.13f7faee626ebp-54},
+{0x1.0d00001a4d338p+0, 0x1.07dfa79489ff7p-55},
+{0x1.0effffadafdfdp+0, -0x1.7040570d66bcp-56},
+{0x1.110000bbafd96p+0, 0x1.e80d4846d0b62p-55},
+{0x1.12ffffae5f45dp+0, 0x1.dbffa64fd36efp-54},
+{0x1.150000dd59ad9p+0, 0x1.a0077701250aep-54},
+{0x1.170000f21559ap+0, 0x1.dfdf9e2e3deeep-55},
+{0x1.18ffffc275426p+0, 0x1.10030dc3b7273p-54},
+{0x1.1b000123d3c59p+0, 0x1.97f7980030188p-54},
+{0x1.1cffff8299eb7p+0, -0x1.5f932ab9f8c67p-57},
+{0x1.1effff48ad4p+0, 0x1.37fbf9da75bebp-54},
+{0x1.210000c8b86a4p+0, 0x1.f806b91fd5b22p-54},
+{0x1.2300003854303p+0, 0x1.3ffc2eb9fbf33p-54},
+{0x1.24fffffbcf684p+0, 0x1.601e77e2e2e72p-56},
+{0x1.26ffff52921d9p+0, 0x1.ffcbb767f0c61p-56},
+{0x1.2900014933a3cp+0, -0x1.202ca3c02412bp-56},
+{0x1.2b00014556313p+0, -0x1.2808233f21f02p-54},
+{0x1.2cfffebfe523bp+0, -0x1.8ff7e384fdcf2p-55},
+{0x1.2f0000bb8ad96p+0, -0x1.5ff51503041c5p-55},
+{0x1.30ffffb7ae2afp+0, -0x1.10071885e289dp-55},
+{0x1.32ffffeac5f7fp+0, -0x1.1ff5d3fb7b715p-54},
+{0x1.350000ca66756p+0, 0x1.57f82228b82bdp-54},
+{0x1.3700011fbf721p+0, 0x1.000bac40dd5ccp-55},
+{0x1.38ffff9592fb9p+0, -0x1.43f9d2db2a751p-54},
+{0x1.3b00004ddd242p+0, 0x1.57f6b707638e1p-55},
+{0x1.3cffff5b2c957p+0, 0x1.a023a10bf1231p-56},
+{0x1.3efffeab0b418p+0, 0x1.87f6d66b152bp-54},
+{0x1.410001532aff4p+0, 0x1.7f8375f198524p-57},
+{0x1.4300017478b29p+0, 0x1.301e672dc5143p-55},
+{0x1.44fffe795b463p+0, 0x1.9ff69b8b2895ap-55},
+{0x1.46fffe80475ep+0, -0x1.5c0b19bc2f254p-54},
+{0x1.48fffef6fc1e7p+0, 0x1.b4009f23a2a72p-54},
+{0x1.4afffe5bea704p+0, -0x1.4ffb7bf0d7d45p-54},
+{0x1.4d000171027dep+0, -0x1.9c06471dc6a3dp-54},
+{0x1.4f0000ff03ee2p+0, 0x1.77f890b85531cp-54},
+{0x1.5100012dc4bd1p+0, 0x1.004657166a436p-57},
+{0x1.530001605277ap+0, -0x1.6bfcece233209p-54},
+{0x1.54fffecdb704cp+0, -0x1.902720505a1d7p-55},
+{0x1.56fffef5f54a9p+0, 0x1.bbfe60ec96412p-54},
+{0x1.5900017e61012p+0, 0x1.87ec581afef9p-55},
+{0x1.5b00003c93e92p+0, -0x1.f41080abf0ccp-54},
+{0x1.5d0001d4919bcp+0, -0x1.8812afb254729p-54},
+{0x1.5efffe7b87a89p+0, -0x1.47eb780ed6904p-54},
+#endif
+},
+#endif /* !HAVE_FAST_FMA */
+};
diff --git a/libc/AOR_v20.02/math/logf.c b/libc/AOR_v20.02/math/logf.c
new file mode 100644
index 0000000000000..5afe629d68e78
--- /dev/null
+++ b/libc/AOR_v20.02/math/logf.c
@@ -0,0 +1,80 @@
+/*
+ * Single-precision log function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+/*
+LOGF_TABLE_BITS = 4
+LOGF_POLY_ORDER = 4
+
+ULP error: 0.818 (nearest rounding.)
+Relative error: 1.957 * 2^-26 (before rounding.)
+*/
+
+#define T __logf_data.tab
+#define A __logf_data.poly
+#define Ln2 __logf_data.ln2
+#define N (1 << LOGF_TABLE_BITS)
+#define OFF 0x3f330000
+
+float
+logf (float x)
+{
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t z, r, r2, y, y0, invc, logc;
+  uint32_t ix, iz, tmp;
+  int k, i;
+
+  ix = asuint (x);
+#if WANT_ROUNDING
+  /* Fix sign of zero with downward rounding when x==1.  */
+  if (unlikely (ix == 0x3f800000))
+    return 0;
+#endif
+  if (unlikely (ix - 0x00800000 >= 0x7f800000 - 0x00800000))
+    {
+      /* x < 0x1p-126 or inf or nan.  */
+      if (ix * 2 == 0)
+	return __math_divzerof (1);
+      if (ix == 0x7f800000) /* log(inf) == inf.  */
+	return x;
+      if ((ix & 0x80000000) || ix * 2 >= 0xff000000)
+	return __math_invalidf (x);
+      /* x is subnormal, normalize it.  */
+      ix = asuint (x * 0x1p23f);
+      ix -= 23 << 23;
+    }
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF] and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (23 - LOGF_TABLE_BITS)) % N;
+  k = (int32_t) tmp >> 23; /* arithmetic shift */
+  iz = ix - (tmp & 0x1ff << 23);
+  invc = T[i].invc;
+  logc = T[i].logc;
+  z = (double_t) asfloat (iz);
+
+  /* log(x) = log1p(z/c-1) + log(c) + k*Ln2 */
+  r = z * invc - 1;
+  y0 = logc + (double_t) k * Ln2;
+
+  /* Pipelined polynomial evaluation to approximate log1p(r).  */
+  r2 = r * r;
+  y = A[1] * r + A[2];
+  y = A[0] * r2 + y;
+  y = y * r2 + (y0 + r);
+  return eval_as_float (y);
+}
+#if USE_GLIBC_ABI
+strong_alias (logf, __logf_finite)
+hidden_alias (logf, __ieee754_logf)
+#endif
diff --git a/libc/AOR_v20.02/math/logf_data.c b/libc/AOR_v20.02/math/logf_data.c
new file mode 100644
index 0000000000000..e4de10f58e67a
--- /dev/null
+++ b/libc/AOR_v20.02/math/logf_data.c
@@ -0,0 +1,34 @@
+/*
+ * Data definition for logf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+const struct logf_data __logf_data = {
+  .tab = {
+  { 0x1.661ec79f8f3bep+0, -0x1.57bf7808caadep-2 },
+  { 0x1.571ed4aaf883dp+0, -0x1.2bef0a7c06ddbp-2 },
+  { 0x1.49539f0f010bp+0, -0x1.01eae7f513a67p-2 },
+  { 0x1.3c995b0b80385p+0, -0x1.b31d8a68224e9p-3 },
+  { 0x1.30d190c8864a5p+0, -0x1.6574f0ac07758p-3 },
+  { 0x1.25e227b0b8eap+0, -0x1.1aa2bc79c81p-3 },
+  { 0x1.1bb4a4a1a343fp+0, -0x1.a4e76ce8c0e5ep-4 },
+  { 0x1.12358f08ae5bap+0, -0x1.1973c5a611cccp-4 },
+  { 0x1.0953f419900a7p+0, -0x1.252f438e10c1ep-5 },
+  { 0x1p+0, 0x0p+0 },
+  { 0x1.e608cfd9a47acp-1, 0x1.aa5aa5df25984p-5 },
+  { 0x1.ca4b31f026aap-1, 0x1.c5e53aa362eb4p-4 },
+  { 0x1.b2036576afce6p-1, 0x1.526e57720db08p-3 },
+  { 0x1.9c2d163a1aa2dp-1, 0x1.bc2860d22477p-3 },
+  { 0x1.886e6037841edp-1, 0x1.1058bc8a07ee1p-2 },
+  { 0x1.767dcf5534862p-1, 0x1.4043057b6ee09p-2 },
+  },
+  .ln2 = 0x1.62e42fefa39efp-1,
+  .poly = {
+  -0x1.00ea348b88334p-2, 0x1.5575b0be00b6ap-2, -0x1.ffffef20a4123p-2,
+  }
+};
diff --git a/libc/AOR_v20.02/math/math_config.h b/libc/AOR_v20.02/math/math_config.h
new file mode 100644
index 0000000000000..ea2d59e94ff0d
--- /dev/null
+++ b/libc/AOR_v20.02/math/math_config.h
@@ -0,0 +1,420 @@
+/*
+ * Configuration for math routines.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef _MATH_CONFIG_H
+#define _MATH_CONFIG_H
+
+#include <math.h>
+#include <stdint.h>
+
+#ifndef WANT_ROUNDING
+/* If defined to 1, return correct results for special cases in non-nearest
+   rounding modes (logf (1.0f) returns 0.0f with FE_DOWNWARD rather than -0.0f).
+   This may be set to 0 if there is no fenv support or if math functions only
+   get called in round to nearest mode.  */
+# define WANT_ROUNDING 1
+#endif
+#ifndef WANT_ERRNO
+/* If defined to 1, set errno in math functions according to ISO C.  Many math
+   libraries do not set errno, so this is 0 by default.  It may need to be
+   set to 1 if math.h has (math_errhandling & MATH_ERRNO) != 0.  */
+# define WANT_ERRNO 0
+#endif
+#ifndef WANT_ERRNO_UFLOW
+/* Set errno to ERANGE if result underflows to 0 (in all rounding modes).  */
+# define WANT_ERRNO_UFLOW (WANT_ROUNDING && WANT_ERRNO)
+#endif
+
+/* Compiler can inline round as a single instruction.  */
+#ifndef HAVE_FAST_ROUND
+# if __aarch64__
+#   define HAVE_FAST_ROUND 1
+# else
+#   define HAVE_FAST_ROUND 0
+# endif
+#endif
+
+/* Compiler can inline lround, but not (long)round(x).  */
+#ifndef HAVE_FAST_LROUND
+# if __aarch64__ && (100*__GNUC__ + __GNUC_MINOR__) >= 408 && __NO_MATH_ERRNO__
+#   define HAVE_FAST_LROUND 1
+# else
+#   define HAVE_FAST_LROUND 0
+# endif
+#endif
+
+/* Compiler can inline fma as a single instruction.  */
+#ifndef HAVE_FAST_FMA
+# if defined FP_FAST_FMA || __aarch64__
+#   define HAVE_FAST_FMA 1
+# else
+#   define HAVE_FAST_FMA 0
+# endif
+#endif
+
+/* Provide *_finite symbols and some of the glibc hidden symbols
+   so libmathlib can be used with binaries compiled against glibc
+   to interpose math functions with both static and dynamic linking.  */
+#ifndef USE_GLIBC_ABI
+# if __GNUC__
+#   define USE_GLIBC_ABI 1
+# else
+#   define USE_GLIBC_ABI 0
+# endif
+#endif
+
+/* Optionally used extensions.  */
+#ifdef __GNUC__
+# define HIDDEN __attribute__ ((__visibility__ ("hidden")))
+# define NOINLINE __attribute__ ((noinline))
+# define UNUSED __attribute__ ((unused))
+# define likely(x) __builtin_expect (!!(x), 1)
+# define unlikely(x) __builtin_expect (x, 0)
+# if __GNUC__ >= 9
+#   define attribute_copy(f) __attribute__ ((copy (f)))
+# else
+#   define attribute_copy(f)
+# endif
+# define strong_alias(f, a) \
+  extern __typeof (f) a __attribute__ ((alias (#f))) attribute_copy (f);
+# define hidden_alias(f, a) \
+  extern __typeof (f) a __attribute__ ((alias (#f), visibility ("hidden"))) \
+  attribute_copy (f);
+#else
+# define HIDDEN
+# define NOINLINE
+# define UNUSED
+# define likely(x) (x)
+# define unlikely(x) (x)
+#endif
+
+#if HAVE_FAST_ROUND
+/* When set, the roundtoint and converttoint functions are provided with
+   the semantics documented below.  */
+# define TOINT_INTRINSICS 1
+
+/* Round x to nearest int in all rounding modes, ties have to be rounded
+   consistently with converttoint so the results match.  If the result
+   would be outside of [-2^31, 2^31-1] then the semantics is unspecified.  */
+static inline double_t
+roundtoint (double_t x)
+{
+  return round (x);
+}
+
+/* Convert x to nearest int in all rounding modes, ties have to be rounded
+   consistently with roundtoint.  If the result is not representible in an
+   int32_t then the semantics is unspecified.  */
+static inline int32_t
+converttoint (double_t x)
+{
+# if HAVE_FAST_LROUND
+  return lround (x);
+# else
+  return (long) round (x);
+# endif
+}
+#endif
+
+static inline uint32_t
+asuint (float f)
+{
+  union
+  {
+    float f;
+    uint32_t i;
+  } u = {f};
+  return u.i;
+}
+
+static inline float
+asfloat (uint32_t i)
+{
+  union
+  {
+    uint32_t i;
+    float f;
+  } u = {i};
+  return u.f;
+}
+
+static inline uint64_t
+asuint64 (double f)
+{
+  union
+  {
+    double f;
+    uint64_t i;
+  } u = {f};
+  return u.i;
+}
+
+static inline double
+asdouble (uint64_t i)
+{
+  union
+  {
+    uint64_t i;
+    double f;
+  } u = {i};
+  return u.f;
+}
+
+#ifndef IEEE_754_2008_SNAN
+# define IEEE_754_2008_SNAN 1
+#endif
+static inline int
+issignalingf_inline (float x)
+{
+  uint32_t ix = asuint (x);
+  if (!IEEE_754_2008_SNAN)
+    return (ix & 0x7fc00000) == 0x7fc00000;
+  return 2 * (ix ^ 0x00400000) > 2u * 0x7fc00000;
+}
+
+static inline int
+issignaling_inline (double x)
+{
+  uint64_t ix = asuint64 (x);
+  if (!IEEE_754_2008_SNAN)
+    return (ix & 0x7ff8000000000000) == 0x7ff8000000000000;
+  return 2 * (ix ^ 0x0008000000000000) > 2 * 0x7ff8000000000000ULL;
+}
+
+#if __aarch64__ && __GNUC__
+/* Prevent the optimization of a floating-point expression.  */
+static inline float
+opt_barrier_float (float x)
+{
+  __asm__ __volatile__ ("" : "+w" (x));
+  return x;
+}
+static inline double
+opt_barrier_double (double x)
+{
+  __asm__ __volatile__ ("" : "+w" (x));
+  return x;
+}
+/* Force the evaluation of a floating-point expression for its side-effect.  */
+static inline void
+force_eval_float (float x)
+{
+  __asm__ __volatile__ ("" : "+w" (x));
+}
+static inline void
+force_eval_double (double x)
+{
+  __asm__ __volatile__ ("" : "+w" (x));
+}
+#else
+static inline float
+opt_barrier_float (float x)
+{
+  volatile float y = x;
+  return y;
+}
+static inline double
+opt_barrier_double (double x)
+{
+  volatile double y = x;
+  return y;
+}
+static inline void
+force_eval_float (float x)
+{
+  volatile float y UNUSED = x;
+}
+static inline void
+force_eval_double (double x)
+{
+  volatile double y UNUSED = x;
+}
+#endif
+
+/* Evaluate an expression as the specified type, normally a type
+   cast should be enough, but compilers implement non-standard
+   excess-precision handling, so when FLT_EVAL_METHOD != 0 then
+   these functions may need to be customized.  */
+static inline float
+eval_as_float (float x)
+{
+  return x;
+}
+static inline double
+eval_as_double (double x)
+{
+  return x;
+}
+
+/* Error handling tail calls for special cases, with a sign argument.
+   The sign of the return value is set if the argument is non-zero.  */
+
+/* The result overflows.  */
+HIDDEN float __math_oflowf (uint32_t);
+/* The result underflows to 0 in nearest rounding mode.  */
+HIDDEN float __math_uflowf (uint32_t);
+/* The result underflows to 0 in some directed rounding mode only.  */
+HIDDEN float __math_may_uflowf (uint32_t);
+/* Division by zero.  */
+HIDDEN float __math_divzerof (uint32_t);
+/* The result overflows.  */
+HIDDEN double __math_oflow (uint32_t);
+/* The result underflows to 0 in nearest rounding mode.  */
+HIDDEN double __math_uflow (uint32_t);
+/* The result underflows to 0 in some directed rounding mode only.  */
+HIDDEN double __math_may_uflow (uint32_t);
+/* Division by zero.  */
+HIDDEN double __math_divzero (uint32_t);
+
+/* Error handling using input checking.  */
+
+/* Invalid input unless it is a quiet NaN.  */
+HIDDEN float __math_invalidf (float);
+/* Invalid input unless it is a quiet NaN.  */
+HIDDEN double __math_invalid (double);
+
+/* Error handling using output checking, only for errno setting.  */
+
+/* Check if the result overflowed to infinity.  */
+HIDDEN double __math_check_oflow (double);
+/* Check if the result underflowed to 0.  */
+HIDDEN double __math_check_uflow (double);
+
+/* Check if the result overflowed to infinity.  */
+static inline double
+check_oflow (double x)
+{
+  return WANT_ERRNO ? __math_check_oflow (x) : x;
+}
+
+/* Check if the result underflowed to 0.  */
+static inline double
+check_uflow (double x)
+{
+  return WANT_ERRNO ? __math_check_uflow (x) : x;
+}
+
+
+/* Shared between expf, exp2f and powf.  */
+#define EXP2F_TABLE_BITS 5
+#define EXP2F_POLY_ORDER 3
+extern const struct exp2f_data
+{
+  uint64_t tab[1 << EXP2F_TABLE_BITS];
+  double shift_scaled;
+  double poly[EXP2F_POLY_ORDER];
+  double shift;
+  double invln2_scaled;
+  double poly_scaled[EXP2F_POLY_ORDER];
+} __exp2f_data HIDDEN;
+
+#define LOGF_TABLE_BITS 4
+#define LOGF_POLY_ORDER 4
+extern const struct logf_data
+{
+  struct
+  {
+    double invc, logc;
+  } tab[1 << LOGF_TABLE_BITS];
+  double ln2;
+  double poly[LOGF_POLY_ORDER - 1]; /* First order coefficient is 1.  */
+} __logf_data HIDDEN;
+
+#define LOG2F_TABLE_BITS 4
+#define LOG2F_POLY_ORDER 4
+extern const struct log2f_data
+{
+  struct
+  {
+    double invc, logc;
+  } tab[1 << LOG2F_TABLE_BITS];
+  double poly[LOG2F_POLY_ORDER];
+} __log2f_data HIDDEN;
+
+#define POWF_LOG2_TABLE_BITS 4
+#define POWF_LOG2_POLY_ORDER 5
+#if TOINT_INTRINSICS
+# define POWF_SCALE_BITS EXP2F_TABLE_BITS
+#else
+# define POWF_SCALE_BITS 0
+#endif
+#define POWF_SCALE ((double) (1 << POWF_SCALE_BITS))
+extern const struct powf_log2_data
+{
+  struct
+  {
+    double invc, logc;
+  } tab[1 << POWF_LOG2_TABLE_BITS];
+  double poly[POWF_LOG2_POLY_ORDER];
+} __powf_log2_data HIDDEN;
+
+
+#define EXP_TABLE_BITS 7
+#define EXP_POLY_ORDER 5
+/* Use polynomial that is optimized for a wider input range.  This may be
+   needed for good precision in non-nearest rounding and !TOINT_INTRINSICS.  */
+#define EXP_POLY_WIDE 0
+/* Use close to nearest rounding toint when !TOINT_INTRINSICS.  This may be
+   needed for good precision in non-nearest rouning and !EXP_POLY_WIDE.  */
+#define EXP_USE_TOINT_NARROW 0
+#define EXP2_POLY_ORDER 5
+#define EXP2_POLY_WIDE 0
+extern const struct exp_data
+{
+  double invln2N;
+  double shift;
+  double negln2hiN;
+  double negln2loN;
+  double poly[4]; /* Last four coefficients.  */
+  double exp2_shift;
+  double exp2_poly[EXP2_POLY_ORDER];
+  uint64_t tab[2*(1 << EXP_TABLE_BITS)];
+} __exp_data HIDDEN;
+
+#define LOG_TABLE_BITS 7
+#define LOG_POLY_ORDER 6
+#define LOG_POLY1_ORDER 12
+extern const struct log_data
+{
+  double ln2hi;
+  double ln2lo;
+  double poly[LOG_POLY_ORDER - 1]; /* First coefficient is 1.  */
+  double poly1[LOG_POLY1_ORDER - 1];
+  struct {double invc, logc;} tab[1 << LOG_TABLE_BITS];
+#if !HAVE_FAST_FMA
+  struct {double chi, clo;} tab2[1 << LOG_TABLE_BITS];
+#endif
+} __log_data HIDDEN;
+
+#define LOG2_TABLE_BITS 6
+#define LOG2_POLY_ORDER 7
+#define LOG2_POLY1_ORDER 11
+extern const struct log2_data
+{
+  double invln2hi;
+  double invln2lo;
+  double poly[LOG2_POLY_ORDER - 1];
+  double poly1[LOG2_POLY1_ORDER - 1];
+  struct {double invc, logc;} tab[1 << LOG2_TABLE_BITS];
+#if !HAVE_FAST_FMA
+  struct {double chi, clo;} tab2[1 << LOG2_TABLE_BITS];
+#endif
+} __log2_data HIDDEN;
+
+#define POW_LOG_TABLE_BITS 7
+#define POW_LOG_POLY_ORDER 8
+extern const struct pow_log_data
+{
+  double ln2hi;
+  double ln2lo;
+  double poly[POW_LOG_POLY_ORDER - 1]; /* First coefficient is 1.  */
+  /* Note: the pad field is unused, but allows slightly faster indexing.  */
+  struct {double invc, pad, logc, logctail;} tab[1 << POW_LOG_TABLE_BITS];
+} __pow_log_data HIDDEN;
+
+#endif
diff --git a/libc/AOR_v20.02/math/math_err.c b/libc/AOR_v20.02/math/math_err.c
new file mode 100644
index 0000000000000..77d8a940efee2
--- /dev/null
+++ b/libc/AOR_v20.02/math/math_err.c
@@ -0,0 +1,81 @@
+/*
+ * Double-precision math error handling.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#if WANT_ERRNO
+#include <errno.h>
+/* NOINLINE reduces code size and avoids making math functions non-leaf
+   when the error handling is inlined.  */
+NOINLINE static double
+with_errno (double y, int e)
+{
+  errno = e;
+  return y;
+}
+#else
+#define with_errno(x, e) (x)
+#endif
+
+/* NOINLINE reduces code size.  */
+NOINLINE static double
+xflow (uint32_t sign, double y)
+{
+  y = eval_as_double (opt_barrier_double (sign ? -y : y) * y);
+  return with_errno (y, ERANGE);
+}
+
+HIDDEN double
+__math_uflow (uint32_t sign)
+{
+  return xflow (sign, 0x1p-767);
+}
+
+#if WANT_ERRNO_UFLOW
+/* Underflows to zero in some non-nearest rounding mode, setting errno
+   is valid even if the result is non-zero, but in the subnormal range.  */
+HIDDEN double
+__math_may_uflow (uint32_t sign)
+{
+  return xflow (sign, 0x1.8p-538);
+}
+#endif
+
+HIDDEN double
+__math_oflow (uint32_t sign)
+{
+  return xflow (sign, 0x1p769);
+}
+
+HIDDEN double
+__math_divzero (uint32_t sign)
+{
+  double y = opt_barrier_double (sign ? -1.0 : 1.0) / 0.0;
+  return with_errno (y, ERANGE);
+}
+
+HIDDEN double
+__math_invalid (double x)
+{
+  double y = (x - x) / (x - x);
+  return isnan (x) ? y : with_errno (y, EDOM);
+}
+
+/* Check result and set errno if necessary.  */
+
+HIDDEN double
+__math_check_uflow (double y)
+{
+  return y == 0.0 ? with_errno (y, ERANGE) : y;
+}
+
+HIDDEN double
+__math_check_oflow (double y)
+{
+  return isinf (y) ? with_errno (y, ERANGE) : y;
+}
diff --git a/libc/AOR_v20.02/math/math_errf.c b/libc/AOR_v20.02/math/math_errf.c
new file mode 100644
index 0000000000000..0837463af4fdc
--- /dev/null
+++ b/libc/AOR_v20.02/math/math_errf.c
@@ -0,0 +1,67 @@
+/*
+ * Single-precision math error handling.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#if WANT_ERRNO
+#include <errno.h>
+/* NOINLINE reduces code size and avoids making math functions non-leaf
+   when the error handling is inlined.  */
+NOINLINE static float
+with_errnof (float y, int e)
+{
+  errno = e;
+  return y;
+}
+#else
+#define with_errnof(x, e) (x)
+#endif
+
+/* NOINLINE reduces code size.  */
+NOINLINE static float
+xflowf (uint32_t sign, float y)
+{
+  y = eval_as_float (opt_barrier_float (sign ? -y : y) * y);
+  return with_errnof (y, ERANGE);
+}
+
+HIDDEN float
+__math_uflowf (uint32_t sign)
+{
+  return xflowf (sign, 0x1p-95f);
+}
+
+#if WANT_ERRNO_UFLOW
+/* Underflows to zero in some non-nearest rounding mode, setting errno
+   is valid even if the result is non-zero, but in the subnormal range.  */
+HIDDEN float
+__math_may_uflowf (uint32_t sign)
+{
+  return xflowf (sign, 0x1.4p-75f);
+}
+#endif
+
+HIDDEN float
+__math_oflowf (uint32_t sign)
+{
+  return xflowf (sign, 0x1p97f);
+}
+
+HIDDEN float
+__math_divzerof (uint32_t sign)
+{
+  float y = opt_barrier_float (sign ? -1.0f : 1.0f) / 0.0f;
+  return with_errnof (y, ERANGE);
+}
+
+HIDDEN float
+__math_invalidf (float x)
+{
+  float y = (x - x) / (x - x);
+  return isnan (x) ? y : with_errnof (y, EDOM);
+}
diff --git a/libc/AOR_v20.02/math/pow.c b/libc/AOR_v20.02/math/pow.c
new file mode 100644
index 0000000000000..acdb23da138e7
--- /dev/null
+++ b/libc/AOR_v20.02/math/pow.c
@@ -0,0 +1,381 @@
+/*
+ * Double-precision x^y function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <float.h>
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+/*
+Worst-case error: 0.54 ULP (~= ulperr_exp + 1024*Ln2*relerr_log*2^53)
+relerr_log: 1.3 * 2^-68 (Relative error of log, 1.5 * 2^-68 without fma)
+ulperr_exp: 0.509 ULP (ULP error of exp, 0.511 ULP without fma)
+*/
+
+#define T __pow_log_data.tab
+#define A __pow_log_data.poly
+#define Ln2hi __pow_log_data.ln2hi
+#define Ln2lo __pow_log_data.ln2lo
+#define N (1 << POW_LOG_TABLE_BITS)
+#define OFF 0x3fe6955500000000
+
+/* Top 12 bits of a double (sign and exponent bits).  */
+static inline uint32_t
+top12 (double x)
+{
+  return asuint64 (x) >> 52;
+}
+
+/* Compute y+TAIL = log(x) where the rounded result is y and TAIL has about
+   additional 15 bits precision.  IX is the bit representation of x, but
+   normalized in the subnormal range using the sign bit for the exponent.  */
+static inline double_t
+log_inline (uint64_t ix, double_t *tail)
+{
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t z, r, y, invc, logc, logctail, kd, hi, t1, t2, lo, lo1, lo2, p;
+  uint64_t iz, tmp;
+  int k, i;
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF) and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (52 - POW_LOG_TABLE_BITS)) % N;
+  k = (int64_t) tmp >> 52; /* arithmetic shift */
+  iz = ix - (tmp & 0xfffULL << 52);
+  z = asdouble (iz);
+  kd = (double_t) k;
+
+  /* log(x) = k*Ln2 + log(c) + log1p(z/c-1).  */
+  invc = T[i].invc;
+  logc = T[i].logc;
+  logctail = T[i].logctail;
+
+  /* Note: 1/c is j/N or j/N/2 where j is an integer in [N,2N) and
+     |z/c - 1| < 1/N, so r = z/c - 1 is exactly representible.  */
+#if HAVE_FAST_FMA
+  r = fma (z, invc, -1.0);
+#else
+  /* Split z such that rhi, rlo and rhi*rhi are exact and |rlo| <= |r|.  */
+  double_t zhi = asdouble ((iz + (1ULL << 31)) & (-1ULL << 32));
+  double_t zlo = z - zhi;
+  double_t rhi = zhi * invc - 1.0;
+  double_t rlo = zlo * invc;
+  r = rhi + rlo;
+#endif
+
+  /* k*Ln2 + log(c) + r.  */
+  t1 = kd * Ln2hi + logc;
+  t2 = t1 + r;
+  lo1 = kd * Ln2lo + logctail;
+  lo2 = t1 - t2 + r;
+
+  /* Evaluation is optimized assuming superscalar pipelined execution.  */
+  double_t ar, ar2, ar3, lo3, lo4;
+  ar = A[0] * r; /* A[0] = -0.5.  */
+  ar2 = r * ar;
+  ar3 = r * ar2;
+  /* k*Ln2 + log(c) + r + A[0]*r*r.  */
+#if HAVE_FAST_FMA
+  hi = t2 + ar2;
+  lo3 = fma (ar, r, -ar2);
+  lo4 = t2 - hi + ar2;
+#else
+  double_t arhi = A[0] * rhi;
+  double_t arhi2 = rhi * arhi;
+  hi = t2 + arhi2;
+  lo3 = rlo * (ar + arhi);
+  lo4 = t2 - hi + arhi2;
+#endif
+  /* p = log1p(r) - r - A[0]*r*r.  */
+#if POW_LOG_POLY_ORDER == 8
+  p = (ar3
+       * (A[1] + r * A[2] + ar2 * (A[3] + r * A[4] + ar2 * (A[5] + r * A[6]))));
+#endif
+  lo = lo1 + lo2 + lo3 + lo4 + p;
+  y = hi + lo;
+  *tail = hi - y + lo;
+  return y;
+}
+
+#undef N
+#undef T
+#define N (1 << EXP_TABLE_BITS)
+#define InvLn2N __exp_data.invln2N
+#define NegLn2hiN __exp_data.negln2hiN
+#define NegLn2loN __exp_data.negln2loN
+#define Shift __exp_data.shift
+#define T __exp_data.tab
+#define C2 __exp_data.poly[5 - EXP_POLY_ORDER]
+#define C3 __exp_data.poly[6 - EXP_POLY_ORDER]
+#define C4 __exp_data.poly[7 - EXP_POLY_ORDER]
+#define C5 __exp_data.poly[8 - EXP_POLY_ORDER]
+#define C6 __exp_data.poly[9 - EXP_POLY_ORDER]
+
+/* Handle cases that may overflow or underflow when computing the result that
+   is scale*(1+TMP) without intermediate rounding.  The bit representation of
+   scale is in SBITS, however it has a computed exponent that may have
+   overflown into the sign bit so that needs to be adjusted before using it as
+   a double.  (int32_t)KI is the k used in the argument reduction and exponent
+   adjustment of scale, positive k here means the result may overflow and
+   negative k means the result may underflow.  */
+static inline double
+specialcase (double_t tmp, uint64_t sbits, uint64_t ki)
+{
+  double_t scale, y;
+
+  if ((ki & 0x80000000) == 0)
+    {
+      /* k > 0, the exponent of scale might have overflowed by <= 460.  */
+      sbits -= 1009ull << 52;
+      scale = asdouble (sbits);
+      y = 0x1p1009 * (scale + scale * tmp);
+      return check_oflow (eval_as_double (y));
+    }
+  /* k < 0, need special care in the subnormal range.  */
+  sbits += 1022ull << 52;
+  /* Note: sbits is signed scale.  */
+  scale = asdouble (sbits);
+  y = scale + scale * tmp;
+  if (fabs (y) < 1.0)
+    {
+      /* Round y to the right precision before scaling it into the subnormal
+	 range to avoid double rounding that can cause 0.5+E/2 ulp error where
+	 E is the worst-case ulp error outside the subnormal range.  So this
+	 is only useful if the goal is better than 1 ulp worst-case error.  */
+      double_t hi, lo, one = 1.0;
+      if (y < 0.0)
+	one = -1.0;
+      lo = scale - y + scale * tmp;
+      hi = one + y;
+      lo = one - hi + y + lo;
+      y = eval_as_double (hi + lo) - one;
+      /* Fix the sign of 0.  */
+      if (y == 0.0)
+	y = asdouble (sbits & 0x8000000000000000);
+      /* The underflow exception needs to be signaled explicitly.  */
+      force_eval_double (opt_barrier_double (0x1p-1022) * 0x1p-1022);
+    }
+  y = 0x1p-1022 * y;
+  return check_uflow (eval_as_double (y));
+}
+
+#define SIGN_BIAS (0x800 << EXP_TABLE_BITS)
+
+/* Computes sign*exp(x+xtail) where |xtail| < 2^-8/N and |xtail| <= |x|.
+   The sign_bias argument is SIGN_BIAS or 0 and sets the sign to -1 or 1.  */
+static inline double
+exp_inline (double_t x, double_t xtail, uint32_t sign_bias)
+{
+  uint32_t abstop;
+  uint64_t ki, idx, top, sbits;
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t kd, z, r, r2, scale, tail, tmp;
+
+  abstop = top12 (x) & 0x7ff;
+  if (unlikely (abstop - top12 (0x1p-54) >= top12 (512.0) - top12 (0x1p-54)))
+    {
+      if (abstop - top12 (0x1p-54) >= 0x80000000)
+	{
+	  /* Avoid spurious underflow for tiny x.  */
+	  /* Note: 0 is common input.  */
+	  double_t one = WANT_ROUNDING ? 1.0 + x : 1.0;
+	  return sign_bias ? -one : one;
+	}
+      if (abstop >= top12 (1024.0))
+	{
+	  /* Note: inf and nan are already handled.  */
+	  if (asuint64 (x) >> 63)
+	    return __math_uflow (sign_bias);
+	  else
+	    return __math_oflow (sign_bias);
+	}
+      /* Large x is special cased below.  */
+      abstop = 0;
+    }
+
+  /* exp(x) = 2^(k/N) * exp(r), with exp(r) in [2^(-1/2N),2^(1/2N)].  */
+  /* x = ln2/N*k + r, with int k and r in [-ln2/2N, ln2/2N].  */
+  z = InvLn2N * x;
+#if TOINT_INTRINSICS
+  kd = roundtoint (z);
+  ki = converttoint (z);
+#elif EXP_USE_TOINT_NARROW
+  /* z - kd is in [-0.5-2^-16, 0.5] in all rounding modes.  */
+  kd = eval_as_double (z + Shift);
+  ki = asuint64 (kd) >> 16;
+  kd = (double_t) (int32_t) ki;
+#else
+  /* z - kd is in [-1, 1] in non-nearest rounding modes.  */
+  kd = eval_as_double (z + Shift);
+  ki = asuint64 (kd);
+  kd -= Shift;
+#endif
+  r = x + kd * NegLn2hiN + kd * NegLn2loN;
+  /* The code assumes 2^-200 < |xtail| < 2^-8/N.  */
+  r += xtail;
+  /* 2^(k/N) ~= scale * (1 + tail).  */
+  idx = 2 * (ki % N);
+  top = (ki + sign_bias) << (52 - EXP_TABLE_BITS);
+  tail = asdouble (T[idx]);
+  /* This is only a valid scale when -1023*N < k < 1024*N.  */
+  sbits = T[idx + 1] + top;
+  /* exp(x) = 2^(k/N) * exp(r) ~= scale + scale * (tail + exp(r) - 1).  */
+  /* Evaluation is optimized assuming superscalar pipelined execution.  */
+  r2 = r * r;
+  /* Without fma the worst case error is 0.25/N ulp larger.  */
+  /* Worst case error is less than 0.5+1.11/N+(abs poly error * 2^53) ulp.  */
+#if EXP_POLY_ORDER == 4
+  tmp = tail + r + r2 * C2 + r * r2 * (C3 + r * C4);
+#elif EXP_POLY_ORDER == 5
+  tmp = tail + r + r2 * (C2 + r * C3) + r2 * r2 * (C4 + r * C5);
+#elif EXP_POLY_ORDER == 6
+  tmp = tail + r + r2 * (0.5 + r * C3) + r2 * r2 * (C4 + r * C5 + r2 * C6);
+#endif
+  if (unlikely (abstop == 0))
+    return specialcase (tmp, sbits, ki);
+  scale = asdouble (sbits);
+  /* Note: tmp == 0 or |tmp| > 2^-200 and scale > 2^-739, so there
+     is no spurious underflow here even without fma.  */
+  return eval_as_double (scale + scale * tmp);
+}
+
+/* Returns 0 if not int, 1 if odd int, 2 if even int.  The argument is
+   the bit representation of a non-zero finite floating-point value.  */
+static inline int
+checkint (uint64_t iy)
+{
+  int e = iy >> 52 & 0x7ff;
+  if (e < 0x3ff)
+    return 0;
+  if (e > 0x3ff + 52)
+    return 2;
+  if (iy & ((1ULL << (0x3ff + 52 - e)) - 1))
+    return 0;
+  if (iy & (1ULL << (0x3ff + 52 - e)))
+    return 1;
+  return 2;
+}
+
+/* Returns 1 if input is the bit representation of 0, infinity or nan.  */
+static inline int
+zeroinfnan (uint64_t i)
+{
+  return 2 * i - 1 >= 2 * asuint64 (INFINITY) - 1;
+}
+
+double
+pow (double x, double y)
+{
+  uint32_t sign_bias = 0;
+  uint64_t ix, iy;
+  uint32_t topx, topy;
+
+  ix = asuint64 (x);
+  iy = asuint64 (y);
+  topx = top12 (x);
+  topy = top12 (y);
+  if (unlikely (topx - 0x001 >= 0x7ff - 0x001
+		|| (topy & 0x7ff) - 0x3be >= 0x43e - 0x3be))
+    {
+      /* Note: if |y| > 1075 * ln2 * 2^53 ~= 0x1.749p62 then pow(x,y) = inf/0
+	 and if |y| < 2^-54 / 1075 ~= 0x1.e7b6p-65 then pow(x,y) = +-1.  */
+      /* Special cases: (x < 0x1p-126 or inf or nan) or
+	 (|y| < 0x1p-65 or |y| >= 0x1p63 or nan).  */
+      if (unlikely (zeroinfnan (iy)))
+	{
+	  if (2 * iy == 0)
+	    return issignaling_inline (x) ? x + y : 1.0;
+	  if (ix == asuint64 (1.0))
+	    return issignaling_inline (y) ? x + y : 1.0;
+	  if (2 * ix > 2 * asuint64 (INFINITY)
+	      || 2 * iy > 2 * asuint64 (INFINITY))
+	    return x + y;
+	  if (2 * ix == 2 * asuint64 (1.0))
+	    return 1.0;
+	  if ((2 * ix < 2 * asuint64 (1.0)) == !(iy >> 63))
+	    return 0.0; /* |x|<1 && y==inf or |x|>1 && y==-inf.  */
+	  return y * y;
+	}
+      if (unlikely (zeroinfnan (ix)))
+	{
+	  double_t x2 = x * x;
+	  if (ix >> 63 && checkint (iy) == 1)
+	    {
+	      x2 = -x2;
+	      sign_bias = 1;
+	    }
+	  if (WANT_ERRNO && 2 * ix == 0 && iy >> 63)
+	    return __math_divzero (sign_bias);
+	  /* Without the barrier some versions of clang hoist the 1/x2 and
+	     thus division by zero exception can be signaled spuriously.  */
+	  return iy >> 63 ? opt_barrier_double (1 / x2) : x2;
+	}
+      /* Here x and y are non-zero finite.  */
+      if (ix >> 63)
+	{
+	  /* Finite x < 0.  */
+	  int yint = checkint (iy);
+	  if (yint == 0)
+	    return __math_invalid (x);
+	  if (yint == 1)
+	    sign_bias = SIGN_BIAS;
+	  ix &= 0x7fffffffffffffff;
+	  topx &= 0x7ff;
+	}
+      if ((topy & 0x7ff) - 0x3be >= 0x43e - 0x3be)
+	{
+	  /* Note: sign_bias == 0 here because y is not odd.  */
+	  if (ix == asuint64 (1.0))
+	    return 1.0;
+	  if ((topy & 0x7ff) < 0x3be)
+	    {
+	      /* |y| < 2^-65, x^y ~= 1 + y*log(x).  */
+	      if (WANT_ROUNDING)
+		return ix > asuint64 (1.0) ? 1.0 + y : 1.0 - y;
+	      else
+		return 1.0;
+	    }
+	  return (ix > asuint64 (1.0)) == (topy < 0x800) ? __math_oflow (0)
+							 : __math_uflow (0);
+	}
+      if (topx == 0)
+	{
+	  /* Normalize subnormal x so exponent becomes negative.  */
+	  /* Without the barrier some versions of clang evalutate the mul
+	     unconditionally causing spurious overflow exceptions.  */
+	  ix = asuint64 (opt_barrier_double (x) * 0x1p52);
+	  ix &= 0x7fffffffffffffff;
+	  ix -= 52ULL << 52;
+	}
+    }
+
+  double_t lo;
+  double_t hi = log_inline (ix, &lo);
+  double_t ehi, elo;
+#if HAVE_FAST_FMA
+  ehi = y * hi;
+  elo = y * lo + fma (y, hi, -ehi);
+#else
+  double_t yhi = asdouble (iy & -1ULL << 27);
+  double_t ylo = y - yhi;
+  double_t lhi = asdouble (asuint64 (hi) & -1ULL << 27);
+  double_t llo = hi - lhi + lo;
+  ehi = yhi * lhi;
+  elo = ylo * lhi + y * llo; /* |elo| < |ehi| * 2^-25.  */
+#endif
+  return exp_inline (ehi, elo, sign_bias);
+}
+#if USE_GLIBC_ABI
+strong_alias (pow, __pow_finite)
+hidden_alias (pow, __ieee754_pow)
+# if LDBL_MANT_DIG == 53
+long double powl (long double x, long double y) { return pow (x, y); }
+# endif
+#endif
diff --git a/libc/AOR_v20.02/math/pow_log_data.c b/libc/AOR_v20.02/math/pow_log_data.c
new file mode 100644
index 0000000000000..445d605228f8e
--- /dev/null
+++ b/libc/AOR_v20.02/math/pow_log_data.c
@@ -0,0 +1,185 @@
+/*
+ * Data for the log part of pow.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+#define N (1 << POW_LOG_TABLE_BITS)
+
+const struct pow_log_data __pow_log_data = {
+.ln2hi = 0x1.62e42fefa3800p-1,
+.ln2lo = 0x1.ef35793c76730p-45,
+.poly = {
+#if N == 128 && POW_LOG_POLY_ORDER == 8
+// relative error: 0x1.11922ap-70
+// in -0x1.6bp-8 0x1.6bp-8
+// Coefficients are scaled to match the scaling during evaluation.
+-0x1p-1,
+0x1.555555555556p-2 * -2,
+-0x1.0000000000006p-2 * -2,
+0x1.999999959554ep-3 * 4,
+-0x1.555555529a47ap-3 * 4,
+0x1.2495b9b4845e9p-3 * -8,
+-0x1.0002b8b263fc3p-3 * -8,
+#endif
+},
+/* Algorithm:
+
+	x = 2^k z
+	log(x) = k ln2 + log(c) + log(z/c)
+	log(z/c) = poly(z/c - 1)
+
+where z is in [0x1.69555p-1; 0x1.69555p0] which is split into N subintervals
+and z falls into the ith one, then table entries are computed as
+
+	tab[i].invc = 1/c
+	tab[i].logc = round(0x1p43*log(c))/0x1p43
+	tab[i].logctail = (double)(log(c) - logc)
+
+where c is chosen near the center of the subinterval such that 1/c has only a
+few precision bits so z/c - 1 is exactly representible as double:
+
+	1/c = center < 1 ? round(N/center)/N : round(2*N/center)/N/2
+
+Note: |z/c - 1| < 1/N for the chosen c, |log(c) - logc - logctail| < 0x1p-97,
+the last few bits of logc are rounded away so k*ln2hi + logc has no rounding
+error and the interval for z is selected such that near x == 1, where log(x)
+is tiny, large cancellation error is avoided in logc + poly(z/c - 1).  */
+.tab = {
+#if N == 128
+#define A(a, b, c) {a, 0, b, c},
+A(0x1.6a00000000000p+0, -0x1.62c82f2b9c800p-2, 0x1.ab42428375680p-48)
+A(0x1.6800000000000p+0, -0x1.5d1bdbf580800p-2, -0x1.ca508d8e0f720p-46)
+A(0x1.6600000000000p+0, -0x1.5767717455800p-2, -0x1.362a4d5b6506dp-45)
+A(0x1.6400000000000p+0, -0x1.51aad872df800p-2, -0x1.684e49eb067d5p-49)
+A(0x1.6200000000000p+0, -0x1.4be5f95777800p-2, -0x1.41b6993293ee0p-47)
+A(0x1.6000000000000p+0, -0x1.4618bc21c6000p-2, 0x1.3d82f484c84ccp-46)
+A(0x1.5e00000000000p+0, -0x1.404308686a800p-2, 0x1.c42f3ed820b3ap-50)
+A(0x1.5c00000000000p+0, -0x1.3a64c55694800p-2, 0x1.0b1c686519460p-45)
+A(0x1.5a00000000000p+0, -0x1.347dd9a988000p-2, 0x1.5594dd4c58092p-45)
+A(0x1.5800000000000p+0, -0x1.2e8e2bae12000p-2, 0x1.67b1e99b72bd8p-45)
+A(0x1.5600000000000p+0, -0x1.2895a13de8800p-2, 0x1.5ca14b6cfb03fp-46)
+A(0x1.5600000000000p+0, -0x1.2895a13de8800p-2, 0x1.5ca14b6cfb03fp-46)
+A(0x1.5400000000000p+0, -0x1.22941fbcf7800p-2, -0x1.65a242853da76p-46)
+A(0x1.5200000000000p+0, -0x1.1c898c1699800p-2, -0x1.fafbc68e75404p-46)
+A(0x1.5000000000000p+0, -0x1.1675cababa800p-2, 0x1.f1fc63382a8f0p-46)
+A(0x1.4e00000000000p+0, -0x1.1058bf9ae4800p-2, -0x1.6a8c4fd055a66p-45)
+A(0x1.4c00000000000p+0, -0x1.0a324e2739000p-2, -0x1.c6bee7ef4030ep-47)
+A(0x1.4a00000000000p+0, -0x1.0402594b4d000p-2, -0x1.036b89ef42d7fp-48)
+A(0x1.4a00000000000p+0, -0x1.0402594b4d000p-2, -0x1.036b89ef42d7fp-48)
+A(0x1.4800000000000p+0, -0x1.fb9186d5e4000p-3, 0x1.d572aab993c87p-47)
+A(0x1.4600000000000p+0, -0x1.ef0adcbdc6000p-3, 0x1.b26b79c86af24p-45)
+A(0x1.4400000000000p+0, -0x1.e27076e2af000p-3, -0x1.72f4f543fff10p-46)
+A(0x1.4200000000000p+0, -0x1.d5c216b4fc000p-3, 0x1.1ba91bbca681bp-45)
+A(0x1.4000000000000p+0, -0x1.c8ff7c79aa000p-3, 0x1.7794f689f8434p-45)
+A(0x1.4000000000000p+0, -0x1.c8ff7c79aa000p-3, 0x1.7794f689f8434p-45)
+A(0x1.3e00000000000p+0, -0x1.bc286742d9000p-3, 0x1.94eb0318bb78fp-46)
+A(0x1.3c00000000000p+0, -0x1.af3c94e80c000p-3, 0x1.a4e633fcd9066p-52)
+A(0x1.3a00000000000p+0, -0x1.a23bc1fe2b000p-3, -0x1.58c64dc46c1eap-45)
+A(0x1.3a00000000000p+0, -0x1.a23bc1fe2b000p-3, -0x1.58c64dc46c1eap-45)
+A(0x1.3800000000000p+0, -0x1.9525a9cf45000p-3, -0x1.ad1d904c1d4e3p-45)
+A(0x1.3600000000000p+0, -0x1.87fa06520d000p-3, 0x1.bbdbf7fdbfa09p-45)
+A(0x1.3400000000000p+0, -0x1.7ab890210e000p-3, 0x1.bdb9072534a58p-45)
+A(0x1.3400000000000p+0, -0x1.7ab890210e000p-3, 0x1.bdb9072534a58p-45)
+A(0x1.3200000000000p+0, -0x1.6d60fe719d000p-3, -0x1.0e46aa3b2e266p-46)
+A(0x1.3000000000000p+0, -0x1.5ff3070a79000p-3, -0x1.e9e439f105039p-46)
+A(0x1.3000000000000p+0, -0x1.5ff3070a79000p-3, -0x1.e9e439f105039p-46)
+A(0x1.2e00000000000p+0, -0x1.526e5e3a1b000p-3, -0x1.0de8b90075b8fp-45)
+A(0x1.2c00000000000p+0, -0x1.44d2b6ccb8000p-3, 0x1.70cc16135783cp-46)
+A(0x1.2c00000000000p+0, -0x1.44d2b6ccb8000p-3, 0x1.70cc16135783cp-46)
+A(0x1.2a00000000000p+0, -0x1.371fc201e9000p-3, 0x1.178864d27543ap-48)
+A(0x1.2800000000000p+0, -0x1.29552f81ff000p-3, -0x1.48d301771c408p-45)
+A(0x1.2600000000000p+0, -0x1.1b72ad52f6000p-3, -0x1.e80a41811a396p-45)
+A(0x1.2600000000000p+0, -0x1.1b72ad52f6000p-3, -0x1.e80a41811a396p-45)
+A(0x1.2400000000000p+0, -0x1.0d77e7cd09000p-3, 0x1.a699688e85bf4p-47)
+A(0x1.2400000000000p+0, -0x1.0d77e7cd09000p-3, 0x1.a699688e85bf4p-47)
+A(0x1.2200000000000p+0, -0x1.fec9131dbe000p-4, -0x1.575545ca333f2p-45)
+A(0x1.2000000000000p+0, -0x1.e27076e2b0000p-4, 0x1.a342c2af0003cp-45)
+A(0x1.2000000000000p+0, -0x1.e27076e2b0000p-4, 0x1.a342c2af0003cp-45)
+A(0x1.1e00000000000p+0, -0x1.c5e548f5bc000p-4, -0x1.d0c57585fbe06p-46)
+A(0x1.1c00000000000p+0, -0x1.a926d3a4ae000p-4, 0x1.53935e85baac8p-45)
+A(0x1.1c00000000000p+0, -0x1.a926d3a4ae000p-4, 0x1.53935e85baac8p-45)
+A(0x1.1a00000000000p+0, -0x1.8c345d631a000p-4, 0x1.37c294d2f5668p-46)
+A(0x1.1a00000000000p+0, -0x1.8c345d631a000p-4, 0x1.37c294d2f5668p-46)
+A(0x1.1800000000000p+0, -0x1.6f0d28ae56000p-4, -0x1.69737c93373dap-45)
+A(0x1.1600000000000p+0, -0x1.51b073f062000p-4, 0x1.f025b61c65e57p-46)
+A(0x1.1600000000000p+0, -0x1.51b073f062000p-4, 0x1.f025b61c65e57p-46)
+A(0x1.1400000000000p+0, -0x1.341d7961be000p-4, 0x1.c5edaccf913dfp-45)
+A(0x1.1400000000000p+0, -0x1.341d7961be000p-4, 0x1.c5edaccf913dfp-45)
+A(0x1.1200000000000p+0, -0x1.16536eea38000p-4, 0x1.47c5e768fa309p-46)
+A(0x1.1000000000000p+0, -0x1.f0a30c0118000p-5, 0x1.d599e83368e91p-45)
+A(0x1.1000000000000p+0, -0x1.f0a30c0118000p-5, 0x1.d599e83368e91p-45)
+A(0x1.0e00000000000p+0, -0x1.b42dd71198000p-5, 0x1.c827ae5d6704cp-46)
+A(0x1.0e00000000000p+0, -0x1.b42dd71198000p-5, 0x1.c827ae5d6704cp-46)
+A(0x1.0c00000000000p+0, -0x1.77458f632c000p-5, -0x1.cfc4634f2a1eep-45)
+A(0x1.0c00000000000p+0, -0x1.77458f632c000p-5, -0x1.cfc4634f2a1eep-45)
+A(0x1.0a00000000000p+0, -0x1.39e87b9fec000p-5, 0x1.502b7f526feaap-48)
+A(0x1.0a00000000000p+0, -0x1.39e87b9fec000p-5, 0x1.502b7f526feaap-48)
+A(0x1.0800000000000p+0, -0x1.f829b0e780000p-6, -0x1.980267c7e09e4p-45)
+A(0x1.0800000000000p+0, -0x1.f829b0e780000p-6, -0x1.980267c7e09e4p-45)
+A(0x1.0600000000000p+0, -0x1.7b91b07d58000p-6, -0x1.88d5493faa639p-45)
+A(0x1.0400000000000p+0, -0x1.fc0a8b0fc0000p-7, -0x1.f1e7cf6d3a69cp-50)
+A(0x1.0400000000000p+0, -0x1.fc0a8b0fc0000p-7, -0x1.f1e7cf6d3a69cp-50)
+A(0x1.0200000000000p+0, -0x1.fe02a6b100000p-8, -0x1.9e23f0dda40e4p-46)
+A(0x1.0200000000000p+0, -0x1.fe02a6b100000p-8, -0x1.9e23f0dda40e4p-46)
+A(0x1.0000000000000p+0, 0x0.0000000000000p+0, 0x0.0000000000000p+0)
+A(0x1.0000000000000p+0, 0x0.0000000000000p+0, 0x0.0000000000000p+0)
+A(0x1.fc00000000000p-1, 0x1.0101575890000p-7, -0x1.0c76b999d2be8p-46)
+A(0x1.f800000000000p-1, 0x1.0205658938000p-6, -0x1.3dc5b06e2f7d2p-45)
+A(0x1.f400000000000p-1, 0x1.8492528c90000p-6, -0x1.aa0ba325a0c34p-45)
+A(0x1.f000000000000p-1, 0x1.0415d89e74000p-5, 0x1.111c05cf1d753p-47)
+A(0x1.ec00000000000p-1, 0x1.466aed42e0000p-5, -0x1.c167375bdfd28p-45)
+A(0x1.e800000000000p-1, 0x1.894aa149fc000p-5, -0x1.97995d05a267dp-46)
+A(0x1.e400000000000p-1, 0x1.ccb73cdddc000p-5, -0x1.a68f247d82807p-46)
+A(0x1.e200000000000p-1, 0x1.eea31c006c000p-5, -0x1.e113e4fc93b7bp-47)
+A(0x1.de00000000000p-1, 0x1.1973bd1466000p-4, -0x1.5325d560d9e9bp-45)
+A(0x1.da00000000000p-1, 0x1.3bdf5a7d1e000p-4, 0x1.cc85ea5db4ed7p-45)
+A(0x1.d600000000000p-1, 0x1.5e95a4d97a000p-4, -0x1.c69063c5d1d1ep-45)
+A(0x1.d400000000000p-1, 0x1.700d30aeac000p-4, 0x1.c1e8da99ded32p-49)
+A(0x1.d000000000000p-1, 0x1.9335e5d594000p-4, 0x1.3115c3abd47dap-45)
+A(0x1.cc00000000000p-1, 0x1.b6ac88dad6000p-4, -0x1.390802bf768e5p-46)
+A(0x1.ca00000000000p-1, 0x1.c885801bc4000p-4, 0x1.646d1c65aacd3p-45)
+A(0x1.c600000000000p-1, 0x1.ec739830a2000p-4, -0x1.dc068afe645e0p-45)
+A(0x1.c400000000000p-1, 0x1.fe89139dbe000p-4, -0x1.534d64fa10afdp-45)
+A(0x1.c000000000000p-1, 0x1.1178e8227e000p-3, 0x1.1ef78ce2d07f2p-45)
+A(0x1.be00000000000p-1, 0x1.1aa2b7e23f000p-3, 0x1.ca78e44389934p-45)
+A(0x1.ba00000000000p-1, 0x1.2d1610c868000p-3, 0x1.39d6ccb81b4a1p-47)
+A(0x1.b800000000000p-1, 0x1.365fcb0159000p-3, 0x1.62fa8234b7289p-51)
+A(0x1.b400000000000p-1, 0x1.4913d8333b000p-3, 0x1.5837954fdb678p-45)
+A(0x1.b200000000000p-1, 0x1.527e5e4a1b000p-3, 0x1.633e8e5697dc7p-45)
+A(0x1.ae00000000000p-1, 0x1.6574ebe8c1000p-3, 0x1.9cf8b2c3c2e78p-46)
+A(0x1.ac00000000000p-1, 0x1.6f0128b757000p-3, -0x1.5118de59c21e1p-45)
+A(0x1.aa00000000000p-1, 0x1.7898d85445000p-3, -0x1.c661070914305p-46)
+A(0x1.a600000000000p-1, 0x1.8beafeb390000p-3, -0x1.73d54aae92cd1p-47)
+A(0x1.a400000000000p-1, 0x1.95a5adcf70000p-3, 0x1.7f22858a0ff6fp-47)
+A(0x1.a000000000000p-1, 0x1.a93ed3c8ae000p-3, -0x1.8724350562169p-45)
+A(0x1.9e00000000000p-1, 0x1.b31d8575bd000p-3, -0x1.c358d4eace1aap-47)
+A(0x1.9c00000000000p-1, 0x1.bd087383be000p-3, -0x1.d4bc4595412b6p-45)
+A(0x1.9a00000000000p-1, 0x1.c6ffbc6f01000p-3, -0x1.1ec72c5962bd2p-48)
+A(0x1.9600000000000p-1, 0x1.db13db0d49000p-3, -0x1.aff2af715b035p-45)
+A(0x1.9400000000000p-1, 0x1.e530effe71000p-3, 0x1.212276041f430p-51)
+A(0x1.9200000000000p-1, 0x1.ef5ade4dd0000p-3, -0x1.a211565bb8e11p-51)
+A(0x1.9000000000000p-1, 0x1.f991c6cb3b000p-3, 0x1.bcbecca0cdf30p-46)
+A(0x1.8c00000000000p-1, 0x1.07138604d5800p-2, 0x1.89cdb16ed4e91p-48)
+A(0x1.8a00000000000p-1, 0x1.0c42d67616000p-2, 0x1.7188b163ceae9p-45)
+A(0x1.8800000000000p-1, 0x1.1178e8227e800p-2, -0x1.c210e63a5f01cp-45)
+A(0x1.8600000000000p-1, 0x1.16b5ccbacf800p-2, 0x1.b9acdf7a51681p-45)
+A(0x1.8400000000000p-1, 0x1.1bf99635a6800p-2, 0x1.ca6ed5147bdb7p-45)
+A(0x1.8200000000000p-1, 0x1.214456d0eb800p-2, 0x1.a87deba46baeap-47)
+A(0x1.7e00000000000p-1, 0x1.2bef07cdc9000p-2, 0x1.a9cfa4a5004f4p-45)
+A(0x1.7c00000000000p-1, 0x1.314f1e1d36000p-2, -0x1.8e27ad3213cb8p-45)
+A(0x1.7a00000000000p-1, 0x1.36b6776be1000p-2, 0x1.16ecdb0f177c8p-46)
+A(0x1.7800000000000p-1, 0x1.3c25277333000p-2, 0x1.83b54b606bd5cp-46)
+A(0x1.7600000000000p-1, 0x1.419b423d5e800p-2, 0x1.8e436ec90e09dp-47)
+A(0x1.7400000000000p-1, 0x1.4718dc271c800p-2, -0x1.f27ce0967d675p-45)
+A(0x1.7200000000000p-1, 0x1.4c9e09e173000p-2, -0x1.e20891b0ad8a4p-45)
+A(0x1.7000000000000p-1, 0x1.522ae0738a000p-2, 0x1.ebe708164c759p-45)
+A(0x1.6e00000000000p-1, 0x1.57bf753c8d000p-2, 0x1.fadedee5d40efp-46)
+A(0x1.6c00000000000p-1, 0x1.5d5bddf596000p-2, -0x1.a0b2a08a465dcp-47)
+#endif
+},
+};
diff --git a/libc/AOR_v20.02/math/powf.c b/libc/AOR_v20.02/math/powf.c
new file mode 100644
index 0000000000000..3cb70c0b62882
--- /dev/null
+++ b/libc/AOR_v20.02/math/powf.c
@@ -0,0 +1,222 @@
+/*
+ * Single-precision pow function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <math.h>
+#include <stdint.h>
+#include "math_config.h"
+
+/*
+POWF_LOG2_POLY_ORDER = 5
+EXP2F_TABLE_BITS = 5
+
+ULP error: 0.82 (~ 0.5 + relerr*2^24)
+relerr: 1.27 * 2^-26 (Relative error ~= 128*Ln2*relerr_log2 + relerr_exp2)
+relerr_log2: 1.83 * 2^-33 (Relative error of logx.)
+relerr_exp2: 1.69 * 2^-34 (Relative error of exp2(ylogx).)
+*/
+
+#define N (1 << POWF_LOG2_TABLE_BITS)
+#define T __powf_log2_data.tab
+#define A __powf_log2_data.poly
+#define OFF 0x3f330000
+
+/* Subnormal input is normalized so ix has negative biased exponent.
+   Output is multiplied by N (POWF_SCALE) if TOINT_INTRINICS is set.  */
+static inline double_t
+log2_inline (uint32_t ix)
+{
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t z, r, r2, r4, p, q, y, y0, invc, logc;
+  uint32_t iz, top, tmp;
+  int k, i;
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF] and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (23 - POWF_LOG2_TABLE_BITS)) % N;
+  top = tmp & 0xff800000;
+  iz = ix - top;
+  k = (int32_t) top >> (23 - POWF_SCALE_BITS); /* arithmetic shift */
+  invc = T[i].invc;
+  logc = T[i].logc;
+  z = (double_t) asfloat (iz);
+
+  /* log2(x) = log1p(z/c-1)/ln2 + log2(c) + k */
+  r = z * invc - 1;
+  y0 = logc + (double_t) k;
+
+  /* Pipelined polynomial evaluation to approximate log1p(r)/ln2.  */
+  r2 = r * r;
+  y = A[0] * r + A[1];
+  p = A[2] * r + A[3];
+  r4 = r2 * r2;
+  q = A[4] * r + y0;
+  q = p * r2 + q;
+  y = y * r4 + q;
+  return y;
+}
+
+#undef N
+#undef T
+#define N (1 << EXP2F_TABLE_BITS)
+#define T __exp2f_data.tab
+#define SIGN_BIAS (1 << (EXP2F_TABLE_BITS + 11))
+
+/* The output of log2 and thus the input of exp2 is either scaled by N
+   (in case of fast toint intrinsics) or not.  The unscaled xd must be
+   in [-1021,1023], sign_bias sets the sign of the result.  */
+static inline float
+exp2_inline (double_t xd, uint32_t sign_bias)
+{
+  uint64_t ki, ski, t;
+  /* double_t for better performance on targets with FLT_EVAL_METHOD==2.  */
+  double_t kd, z, r, r2, y, s;
+
+#if TOINT_INTRINSICS
+# define C __exp2f_data.poly_scaled
+  /* N*x = k + r with r in [-1/2, 1/2] */
+  kd = roundtoint (xd); /* k */
+  ki = converttoint (xd);
+#else
+# define C __exp2f_data.poly
+# define SHIFT __exp2f_data.shift_scaled
+  /* x = k/N + r with r in [-1/(2N), 1/(2N)] */
+  kd = eval_as_double (xd + SHIFT);
+  ki = asuint64 (kd);
+  kd -= SHIFT; /* k/N */
+#endif
+  r = xd - kd;
+
+  /* exp2(x) = 2^(k/N) * 2^r ~= s * (C0*r^3 + C1*r^2 + C2*r + 1) */
+  t = T[ki % N];
+  ski = ki + sign_bias;
+  t += ski << (52 - EXP2F_TABLE_BITS);
+  s = asdouble (t);
+  z = C[0] * r + C[1];
+  r2 = r * r;
+  y = C[2] * r + 1;
+  y = z * r2 + y;
+  y = y * s;
+  return eval_as_float (y);
+}
+
+/* Returns 0 if not int, 1 if odd int, 2 if even int.  The argument is
+   the bit representation of a non-zero finite floating-point value.  */
+static inline int
+checkint (uint32_t iy)
+{
+  int e = iy >> 23 & 0xff;
+  if (e < 0x7f)
+    return 0;
+  if (e > 0x7f + 23)
+    return 2;
+  if (iy & ((1 << (0x7f + 23 - e)) - 1))
+    return 0;
+  if (iy & (1 << (0x7f + 23 - e)))
+    return 1;
+  return 2;
+}
+
+static inline int
+zeroinfnan (uint32_t ix)
+{
+  return 2 * ix - 1 >= 2u * 0x7f800000 - 1;
+}
+
+float
+powf (float x, float y)
+{
+  uint32_t sign_bias = 0;
+  uint32_t ix, iy;
+
+  ix = asuint (x);
+  iy = asuint (y);
+  if (unlikely (ix - 0x00800000 >= 0x7f800000 - 0x00800000 || zeroinfnan (iy)))
+    {
+      /* Either (x < 0x1p-126 or inf or nan) or (y is 0 or inf or nan).  */
+      if (unlikely (zeroinfnan (iy)))
+	{
+	  if (2 * iy == 0)
+	    return issignalingf_inline (x) ? x + y : 1.0f;
+	  if (ix == 0x3f800000)
+	    return issignalingf_inline (y) ? x + y : 1.0f;
+	  if (2 * ix > 2u * 0x7f800000 || 2 * iy > 2u * 0x7f800000)
+	    return x + y;
+	  if (2 * ix == 2 * 0x3f800000)
+	    return 1.0f;
+	  if ((2 * ix < 2 * 0x3f800000) == !(iy & 0x80000000))
+	    return 0.0f; /* |x|<1 && y==inf or |x|>1 && y==-inf.  */
+	  return y * y;
+	}
+      if (unlikely (zeroinfnan (ix)))
+	{
+	  float_t x2 = x * x;
+	  if (ix & 0x80000000 && checkint (iy) == 1)
+	    {
+	      x2 = -x2;
+	      sign_bias = 1;
+	    }
+#if WANT_ERRNO
+	  if (2 * ix == 0 && iy & 0x80000000)
+	    return __math_divzerof (sign_bias);
+#endif
+	  /* Without the barrier some versions of clang hoist the 1/x2 and
+	     thus division by zero exception can be signaled spuriously.  */
+	  return iy & 0x80000000 ? opt_barrier_float (1 / x2) : x2;
+	}
+      /* x and y are non-zero finite.  */
+      if (ix & 0x80000000)
+	{
+	  /* Finite x < 0.  */
+	  int yint = checkint (iy);
+	  if (yint == 0)
+	    return __math_invalidf (x);
+	  if (yint == 1)
+	    sign_bias = SIGN_BIAS;
+	  ix &= 0x7fffffff;
+	}
+      if (ix < 0x00800000)
+	{
+	  /* Normalize subnormal x so exponent becomes negative.  */
+	  ix = asuint (x * 0x1p23f);
+	  ix &= 0x7fffffff;
+	  ix -= 23 << 23;
+	}
+    }
+  double_t logx = log2_inline (ix);
+  double_t ylogx = y * logx; /* Note: cannot overflow, y is single prec.  */
+  if (unlikely ((asuint64 (ylogx) >> 47 & 0xffff)
+		 >= asuint64 (126.0 * POWF_SCALE) >> 47))
+    {
+      /* |y*log(x)| >= 126.  */
+      if (ylogx > 0x1.fffffffd1d571p+6 * POWF_SCALE)
+	/* |x^y| > 0x1.ffffffp127.  */
+	return __math_oflowf (sign_bias);
+      if (WANT_ROUNDING && WANT_ERRNO
+	  && ylogx > 0x1.fffffffa3aae2p+6 * POWF_SCALE)
+	/* |x^y| > 0x1.fffffep127, check if we round away from 0.  */
+	if ((!sign_bias
+	     && eval_as_float (1.0f + opt_barrier_float (0x1p-25f)) != 1.0f)
+	    || (sign_bias
+		&& eval_as_float (-1.0f - opt_barrier_float (0x1p-25f))
+		     != -1.0f))
+	  return __math_oflowf (sign_bias);
+      if (ylogx <= -150.0 * POWF_SCALE)
+	return __math_uflowf (sign_bias);
+#if WANT_ERRNO_UFLOW
+      if (ylogx < -149.0 * POWF_SCALE)
+	return __math_may_uflowf (sign_bias);
+#endif
+    }
+  return exp2_inline (ylogx, sign_bias);
+}
+#if USE_GLIBC_ABI
+strong_alias (powf, __powf_finite)
+hidden_alias (powf, __ieee754_powf)
+#endif
diff --git a/libc/AOR_v20.02/math/powf_log2_data.c b/libc/AOR_v20.02/math/powf_log2_data.c
new file mode 100644
index 0000000000000..d7c74b3d19e8e
--- /dev/null
+++ b/libc/AOR_v20.02/math/powf_log2_data.c
@@ -0,0 +1,35 @@
+/*
+ * Data definition for powf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "math_config.h"
+
+const struct powf_log2_data __powf_log2_data = {
+  .tab = {
+  { 0x1.661ec79f8f3bep+0, -0x1.efec65b963019p-2 * POWF_SCALE },
+  { 0x1.571ed4aaf883dp+0, -0x1.b0b6832d4fca4p-2 * POWF_SCALE },
+  { 0x1.49539f0f010bp+0, -0x1.7418b0a1fb77bp-2 * POWF_SCALE },
+  { 0x1.3c995b0b80385p+0, -0x1.39de91a6dcf7bp-2 * POWF_SCALE },
+  { 0x1.30d190c8864a5p+0, -0x1.01d9bf3f2b631p-2 * POWF_SCALE },
+  { 0x1.25e227b0b8eap+0, -0x1.97c1d1b3b7afp-3 * POWF_SCALE },
+  { 0x1.1bb4a4a1a343fp+0, -0x1.2f9e393af3c9fp-3 * POWF_SCALE },
+  { 0x1.12358f08ae5bap+0, -0x1.960cbbf788d5cp-4 * POWF_SCALE },
+  { 0x1.0953f419900a7p+0, -0x1.a6f9db6475fcep-5 * POWF_SCALE },
+  { 0x1p+0, 0x0p+0 * POWF_SCALE },
+  { 0x1.e608cfd9a47acp-1, 0x1.338ca9f24f53dp-4 * POWF_SCALE },
+  { 0x1.ca4b31f026aap-1, 0x1.476a9543891bap-3 * POWF_SCALE },
+  { 0x1.b2036576afce6p-1, 0x1.e840b4ac4e4d2p-3 * POWF_SCALE },
+  { 0x1.9c2d163a1aa2dp-1, 0x1.40645f0c6651cp-2 * POWF_SCALE },
+  { 0x1.886e6037841edp-1, 0x1.88e9c2c1b9ff8p-2 * POWF_SCALE },
+  { 0x1.767dcf5534862p-1, 0x1.ce0a44eb17bccp-2 * POWF_SCALE },
+  },
+  .poly = {
+  0x1.27616c9496e0bp-2 * POWF_SCALE, -0x1.71969a075c67ap-2 * POWF_SCALE,
+  0x1.ec70a6ca7baddp-2 * POWF_SCALE, -0x1.7154748bef6c8p-1 * POWF_SCALE,
+  0x1.71547652ab82bp0 * POWF_SCALE,
+  }
+};
diff --git a/libc/AOR_v20.02/math/s_cos.c b/libc/AOR_v20.02/math/s_cos.c
new file mode 100644
index 0000000000000..c0176c70e3d30
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_cos.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_cos.c"
diff --git a/libc/AOR_v20.02/math/s_cosf.c b/libc/AOR_v20.02/math/s_cosf.c
new file mode 100644
index 0000000000000..8bea8ec96b601
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_cosf.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_cosf.c"
diff --git a/libc/AOR_v20.02/math/s_exp.c b/libc/AOR_v20.02/math/s_exp.c
new file mode 100644
index 0000000000000..2c9dbe7dde9be
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_exp.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_exp.c"
diff --git a/libc/AOR_v20.02/math/s_exp2f.c b/libc/AOR_v20.02/math/s_exp2f.c
new file mode 100644
index 0000000000000..de566753922d3
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_exp2f.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_exp2f.c"
diff --git a/libc/AOR_v20.02/math/s_exp2f_1u.c b/libc/AOR_v20.02/math/s_exp2f_1u.c
new file mode 100644
index 0000000000000..53d557fb4aea6
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_exp2f_1u.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_exp2f_1u.c"
diff --git a/libc/AOR_v20.02/math/s_expf.c b/libc/AOR_v20.02/math/s_expf.c
new file mode 100644
index 0000000000000..6340895920fe6
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_expf.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_expf.c"
diff --git a/libc/AOR_v20.02/math/s_expf_1u.c b/libc/AOR_v20.02/math/s_expf_1u.c
new file mode 100644
index 0000000000000..127ae3bdd47b4
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_expf_1u.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_expf_1u.c"
diff --git a/libc/AOR_v20.02/math/s_log.c b/libc/AOR_v20.02/math/s_log.c
new file mode 100644
index 0000000000000..22fd46c488198
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_log.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_log.c"
diff --git a/libc/AOR_v20.02/math/s_logf.c b/libc/AOR_v20.02/math/s_logf.c
new file mode 100644
index 0000000000000..3066f381482f4
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_logf.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_logf.c"
diff --git a/libc/AOR_v20.02/math/s_pow.c b/libc/AOR_v20.02/math/s_pow.c
new file mode 100644
index 0000000000000..bf0910bfef029
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_pow.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_pow.c"
diff --git a/libc/AOR_v20.02/math/s_powf.c b/libc/AOR_v20.02/math/s_powf.c
new file mode 100644
index 0000000000000..48319a22db52f
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_powf.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_powf.c"
diff --git a/libc/AOR_v20.02/math/s_sin.c b/libc/AOR_v20.02/math/s_sin.c
new file mode 100644
index 0000000000000..969714f996e3f
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_sin.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_sin.c"
diff --git a/libc/AOR_v20.02/math/s_sinf.c b/libc/AOR_v20.02/math/s_sinf.c
new file mode 100644
index 0000000000000..55d45677c642d
--- /dev/null
+++ b/libc/AOR_v20.02/math/s_sinf.c
@@ -0,0 +1,7 @@
+/*
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_sinf.c"
diff --git a/libc/AOR_v20.02/math/sincosf.c b/libc/AOR_v20.02/math/sincosf.c
new file mode 100644
index 0000000000000..819b05b210806
--- /dev/null
+++ b/libc/AOR_v20.02/math/sincosf.c
@@ -0,0 +1,80 @@
+/*
+ * Single-precision sin/cos function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <math.h>
+#include "math_config.h"
+#include "sincosf.h"
+
+/* Fast sincosf implementation.  Worst-case ULP is 0.5607, maximum relative
+   error is 0.5303 * 2^-23.  A single-step range reduction is used for
+   small values.  Large inputs have their range reduced using fast integer
+   arithmetic.  */
+void
+sincosf (float y, float *sinp, float *cosp)
+{
+  double x = y;
+  double s;
+  int n;
+  const sincos_t *p = &__sincosf_table[0];
+
+  if (abstop12 (y) < abstop12 (pio4))
+    {
+      double x2 = x * x;
+
+      if (unlikely (abstop12 (y) < abstop12 (0x1p-12f)))
+	{
+	  if (unlikely (abstop12 (y) < abstop12 (0x1p-126f)))
+	    /* Force underflow for tiny y.  */
+	    force_eval_float (x2);
+	  *sinp = y;
+	  *cosp = 1.0f;
+	  return;
+	}
+
+      sincosf_poly (x, x2, p, 0, sinp, cosp);
+    }
+  else if (abstop12 (y) < abstop12 (120.0f))
+    {
+      x = reduce_fast (x, p, &n);
+
+      /* Setup the signs for sin and cos.  */
+      s = p->sign[n & 3];
+
+      if (n & 2)
+	p = &__sincosf_table[1];
+
+      sincosf_poly (x * s, x * x, p, n, sinp, cosp);
+    }
+  else if (likely (abstop12 (y) < abstop12 (INFINITY)))
+    {
+      uint32_t xi = asuint (y);
+      int sign = xi >> 31;
+
+      x = reduce_large (xi, &n);
+
+      /* Setup signs for sin and cos - include original sign.  */
+      s = p->sign[(n + sign) & 3];
+
+      if ((n + sign) & 2)
+	p = &__sincosf_table[1];
+
+      sincosf_poly (x * s, x * x, p, n, sinp, cosp);
+    }
+  else
+    {
+      /* Return NaN if Inf or NaN for both sin and cos.  */
+      *sinp = *cosp = y - y;
+#if WANT_ERRNO
+      /* Needed to set errno for +-Inf, the add is a hack to work
+	 around a gcc register allocation issue: just passing y
+	 affects code generation in the fast path.  */
+      __math_invalidf (y + y);
+#endif
+    }
+}
diff --git a/libc/AOR_v20.02/math/sincosf.h b/libc/AOR_v20.02/math/sincosf.h
new file mode 100644
index 0000000000000..ef40d708acdee
--- /dev/null
+++ b/libc/AOR_v20.02/math/sincosf.h
@@ -0,0 +1,154 @@
+/*
+ * Header for sinf, cosf and sincosf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <math.h>
+#include "math_config.h"
+
+/* 2PI * 2^-64.  */
+static const double pi63 = 0x1.921FB54442D18p-62;
+/* PI / 4.  */
+static const double pio4 = 0x1.921FB54442D18p-1;
+
+/* The constants and polynomials for sine and cosine.  */
+typedef struct
+{
+  double sign[4];		/* Sign of sine in quadrants 0..3.  */
+  double hpi_inv;		/* 2 / PI ( * 2^24 if !TOINT_INTRINSICS).  */
+  double hpi;			/* PI / 2.  */
+  double c0, c1, c2, c3, c4;	/* Cosine polynomial.  */
+  double s1, s2, s3;		/* Sine polynomial.  */
+} sincos_t;
+
+/* Polynomial data (the cosine polynomial is negated in the 2nd entry).  */
+extern const sincos_t __sincosf_table[2] HIDDEN;
+
+/* Table with 4/PI to 192 bit precision.  */
+extern const uint32_t __inv_pio4[] HIDDEN;
+
+/* Top 12 bits of the float representation with the sign bit cleared.  */
+static inline uint32_t
+abstop12 (float x)
+{
+  return (asuint (x) >> 20) & 0x7ff;
+}
+
+/* Compute the sine and cosine of inputs X and X2 (X squared), using the
+   polynomial P and store the results in SINP and COSP.  N is the quadrant,
+   if odd the cosine and sine polynomials are swapped.  */
+static inline void
+sincosf_poly (double x, double x2, const sincos_t *p, int n, float *sinp,
+	      float *cosp)
+{
+  double x3, x4, x5, x6, s, c, c1, c2, s1;
+
+  x4 = x2 * x2;
+  x3 = x2 * x;
+  c2 = p->c3 + x2 * p->c4;
+  s1 = p->s2 + x2 * p->s3;
+
+  /* Swap sin/cos result based on quadrant.  */
+  float *tmp = (n & 1 ? cosp : sinp);
+  cosp = (n & 1 ? sinp : cosp);
+  sinp = tmp;
+
+  c1 = p->c0 + x2 * p->c1;
+  x5 = x3 * x2;
+  x6 = x4 * x2;
+
+  s = x + x3 * p->s1;
+  c = c1 + x4 * p->c2;
+
+  *sinp = s + x5 * s1;
+  *cosp = c + x6 * c2;
+}
+
+/* Return the sine of inputs X and X2 (X squared) using the polynomial P.
+   N is the quadrant, and if odd the cosine polynomial is used.  */
+static inline float
+sinf_poly (double x, double x2, const sincos_t *p, int n)
+{
+  double x3, x4, x6, x7, s, c, c1, c2, s1;
+
+  if ((n & 1) == 0)
+    {
+      x3 = x * x2;
+      s1 = p->s2 + x2 * p->s3;
+
+      x7 = x3 * x2;
+      s = x + x3 * p->s1;
+
+      return s + x7 * s1;
+    }
+  else
+    {
+      x4 = x2 * x2;
+      c2 = p->c3 + x2 * p->c4;
+      c1 = p->c0 + x2 * p->c1;
+
+      x6 = x4 * x2;
+      c = c1 + x4 * p->c2;
+
+      return c + x6 * c2;
+    }
+}
+
+/* Fast range reduction using single multiply-subtract.  Return the modulo of
+   X as a value between -PI/4 and PI/4 and store the quadrant in NP.
+   The values for PI/2 and 2/PI are accessed via P.  Since PI/2 as a double
+   is accurate to 55 bits and the worst-case cancellation happens at 6 * PI/4,
+   the result is accurate for |X| <= 120.0.  */
+static inline double
+reduce_fast (double x, const sincos_t *p, int *np)
+{
+  double r;
+#if TOINT_INTRINSICS
+  /* Use fast round and lround instructions when available.  */
+  r = x * p->hpi_inv;
+  *np = converttoint (r);
+  return x - roundtoint (r) * p->hpi;
+#else
+  /* Use scaled float to int conversion with explicit rounding.
+     hpi_inv is prescaled by 2^24 so the quadrant ends up in bits 24..31.
+     This avoids inaccuracies introduced by truncating negative values.  */
+  r = x * p->hpi_inv;
+  int n = ((int32_t)r + 0x800000) >> 24;
+  *np = n;
+  return x - n * p->hpi;
+#endif
+}
+
+/* Reduce the range of XI to a multiple of PI/2 using fast integer arithmetic.
+   XI is a reinterpreted float and must be >= 2.0f (the sign bit is ignored).
+   Return the modulo between -PI/4 and PI/4 and store the quadrant in NP.
+   Reduction uses a table of 4/PI with 192 bits of precision.  A 32x96->128 bit
+   multiply computes the exact 2.62-bit fixed-point modulo.  Since the result
+   can have at most 29 leading zeros after the binary point, the double
+   precision result is accurate to 33 bits.  */
+static inline double
+reduce_large (uint32_t xi, int *np)
+{
+  const uint32_t *arr = &__inv_pio4[(xi >> 26) & 15];
+  int shift = (xi >> 23) & 7;
+  uint64_t n, res0, res1, res2;
+
+  xi = (xi & 0xffffff) | 0x800000;
+  xi <<= shift;
+
+  res0 = xi * arr[0];
+  res1 = (uint64_t)xi * arr[4];
+  res2 = (uint64_t)xi * arr[8];
+  res0 = (res2 >> 32) | (res0 << 32);
+  res0 += res1;
+
+  n = (res0 + (1ULL << 61)) >> 62;
+  res0 -= n << 62;
+  double x = (int64_t)res0;
+  *np = n;
+  return x * pi63;
+}
diff --git a/libc/AOR_v20.02/math/sincosf_data.c b/libc/AOR_v20.02/math/sincosf_data.c
new file mode 100644
index 0000000000000..a3d5efda6f4ce
--- /dev/null
+++ b/libc/AOR_v20.02/math/sincosf_data.c
@@ -0,0 +1,64 @@
+/*
+ * Data definition for sinf, cosf and sincosf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <math.h>
+#include "math_config.h"
+#include "sincosf.h"
+
+/* The constants and polynomials for sine and cosine.  The 2nd entry
+   computes -cos (x) rather than cos (x) to get negation for free.  */
+const sincos_t __sincosf_table[2] =
+{
+  {
+    { 1.0, -1.0, -1.0, 1.0 },
+#if TOINT_INTRINSICS
+    0x1.45F306DC9C883p-1,
+#else
+    0x1.45F306DC9C883p+23,
+#endif
+    0x1.921FB54442D18p0,
+    0x1p0,
+    -0x1.ffffffd0c621cp-2,
+    0x1.55553e1068f19p-5,
+    -0x1.6c087e89a359dp-10,
+    0x1.99343027bf8c3p-16,
+    -0x1.555545995a603p-3,
+    0x1.1107605230bc4p-7,
+    -0x1.994eb3774cf24p-13
+  },
+  {
+    { 1.0, -1.0, -1.0, 1.0 },
+#if TOINT_INTRINSICS
+    0x1.45F306DC9C883p-1,
+#else
+    0x1.45F306DC9C883p+23,
+#endif
+    0x1.921FB54442D18p0,
+    -0x1p0,
+    0x1.ffffffd0c621cp-2,
+    -0x1.55553e1068f19p-5,
+    0x1.6c087e89a359dp-10,
+    -0x1.99343027bf8c3p-16,
+    -0x1.555545995a603p-3,
+    0x1.1107605230bc4p-7,
+    -0x1.994eb3774cf24p-13
+  }
+};
+
+/* Table with 4/PI to 192 bit precision.  To avoid unaligned accesses
+   only 8 new bits are added per entry, making the table 4 times larger.  */
+const uint32_t __inv_pio4[24] =
+{
+  0xa2,       0xa2f9,	  0xa2f983,   0xa2f9836e,
+  0xf9836e4e, 0x836e4e44, 0x6e4e4415, 0x4e441529,
+  0x441529fc, 0x1529fc27, 0x29fc2757, 0xfc2757d1,
+  0x2757d1f5, 0x57d1f534, 0xd1f534dd, 0xf534ddc0,
+  0x34ddc0db, 0xddc0db62, 0xc0db6295, 0xdb629599,
+  0x6295993c, 0x95993c43, 0x993c4390, 0x3c439041
+};
diff --git a/libc/AOR_v20.02/math/sinf.c b/libc/AOR_v20.02/math/sinf.c
new file mode 100644
index 0000000000000..644b82dd94da2
--- /dev/null
+++ b/libc/AOR_v20.02/math/sinf.c
@@ -0,0 +1,68 @@
+/*
+ * Single-precision sin function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <math.h>
+#include "math_config.h"
+#include "sincosf.h"
+
+/* Fast sinf implementation.  Worst-case ULP is 0.5607, maximum relative
+   error is 0.5303 * 2^-23.  A single-step range reduction is used for
+   small values.  Large inputs have their range reduced using fast integer
+   arithmetic.  */
+float
+sinf (float y)
+{
+  double x = y;
+  double s;
+  int n;
+  const sincos_t *p = &__sincosf_table[0];
+
+  if (abstop12 (y) < abstop12 (pio4))
+    {
+      s = x * x;
+
+      if (unlikely (abstop12 (y) < abstop12 (0x1p-12f)))
+	{
+	  if (unlikely (abstop12 (y) < abstop12 (0x1p-126f)))
+	    /* Force underflow for tiny y.  */
+	    force_eval_float (s);
+	  return y;
+	}
+
+      return sinf_poly (x, s, p, 0);
+    }
+  else if (likely (abstop12 (y) < abstop12 (120.0f)))
+    {
+      x = reduce_fast (x, p, &n);
+
+      /* Setup the signs for sin and cos.  */
+      s = p->sign[n & 3];
+
+      if (n & 2)
+	p = &__sincosf_table[1];
+
+      return sinf_poly (x * s, x * x, p, n);
+    }
+  else if (abstop12 (y) < abstop12 (INFINITY))
+    {
+      uint32_t xi = asuint (y);
+      int sign = xi >> 31;
+
+      x = reduce_large (xi, &n);
+
+      /* Setup signs for sin and cos - include original sign.  */
+      s = p->sign[(n + sign) & 3];
+
+      if ((n + sign) & 2)
+	p = &__sincosf_table[1];
+
+      return sinf_poly (x * s, x * x, p, n);
+    }
+  else
+    return __math_invalidf (y);
+}
diff --git a/libc/AOR_v20.02/math/test/mathbench.c b/libc/AOR_v20.02/math/test/mathbench.c
new file mode 100644
index 0000000000000..a57eddb2b4812
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/mathbench.c
@@ -0,0 +1,772 @@
+/*
+ * Microbenchmark for math functions.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#undef _GNU_SOURCE
+#define _GNU_SOURCE 1
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include <math.h>
+#include "mathlib.h"
+
+#ifndef WANT_VMATH
+/* Enable the build of vector math code.  */
+# define WANT_VMATH 1
+#endif
+
+/* Number of measurements, best result is reported.  */
+#define MEASURE 60
+/* Array size.  */
+#define N 8000
+/* Iterations over the array.  */
+#define ITER 125
+
+static double *Trace;
+static size_t trace_size;
+static double A[N];
+static float Af[N];
+static long measurecount = MEASURE;
+static long itercount = ITER;
+
+#if __aarch64__ && WANT_VMATH
+typedef __f64x2_t v_double;
+
+#define v_double_len() 2
+
+static inline v_double
+v_double_load (const double *p)
+{
+  return (v_double){p[0], p[1]};
+}
+
+static inline v_double
+v_double_dup (double x)
+{
+  return (v_double){x, x};
+}
+
+typedef __f32x4_t v_float;
+
+#define v_float_len() 4
+
+static inline v_float
+v_float_load (const float *p)
+{
+  return (v_float){p[0], p[1], p[2], p[3]};
+}
+
+static inline v_float
+v_float_dup (float x)
+{
+  return (v_float){x, x, x, x};
+}
+#else
+/* dummy definitions to make things compile.  */
+typedef double v_double;
+typedef float v_float;
+#define v_double_len(x) 1
+#define v_double_load(x) (x)[0]
+#define v_double_dup(x) (x)
+#define v_float_len(x) 1
+#define v_float_load(x) (x)[0]
+#define v_float_dup(x) (x)
+#endif
+
+static double
+dummy (double x)
+{
+  return x;
+}
+
+static float
+dummyf (float x)
+{
+  return x;
+}
+
+#if WANT_VMATH
+#if __aarch64__
+static v_double
+__v_dummy (v_double x)
+{
+  return x;
+}
+
+static v_float
+__v_dummyf (v_float x)
+{
+  return x;
+}
+
+#ifdef __vpcs
+__vpcs static v_double
+__vn_dummy (v_double x)
+{
+  return x;
+}
+
+__vpcs static v_float
+__vn_dummyf (v_float x)
+{
+  return x;
+}
+
+__vpcs static v_float
+xy__vn_powf (v_float x)
+{
+  return __vn_powf (x, x);
+}
+
+__vpcs static v_float
+xy_Z_powf (v_float x)
+{
+  return _ZGVnN4vv_powf (x, x);
+}
+
+__vpcs static v_double
+xy__vn_pow (v_double x)
+{
+  return __vn_pow (x, x);
+}
+
+__vpcs static v_double
+xy_Z_pow (v_double x)
+{
+  return _ZGVnN2vv_pow (x, x);
+}
+#endif
+
+static v_float
+xy__v_powf (v_float x)
+{
+  return __v_powf (x, x);
+}
+
+static v_double
+xy__v_pow (v_double x)
+{
+  return __v_pow (x, x);
+}
+#endif
+
+static float
+xy__s_powf (float x)
+{
+  return __s_powf (x, x);
+}
+
+static double
+xy__s_pow (double x)
+{
+  return __s_pow (x, x);
+}
+#endif
+
+static double
+xypow (double x)
+{
+  return pow (x, x);
+}
+
+static float
+xypowf (float x)
+{
+  return powf (x, x);
+}
+
+static double
+xpow (double x)
+{
+  return pow (x, 23.4);
+}
+
+static float
+xpowf (float x)
+{
+  return powf (x, 23.4f);
+}
+
+static double
+ypow (double x)
+{
+  return pow (2.34, x);
+}
+
+static float
+ypowf (float x)
+{
+  return powf (2.34f, x);
+}
+
+static float
+sincosf_wrap (float x)
+{
+  float s, c;
+  sincosf (x, &s, &c);
+  return s + c;
+}
+
+static const struct fun
+{
+  const char *name;
+  int prec;
+  int vec;
+  double lo;
+  double hi;
+  union
+  {
+    double (*d) (double);
+    float (*f) (float);
+    v_double (*vd) (v_double);
+    v_float (*vf) (v_float);
+#ifdef __vpcs
+    __vpcs v_double (*vnd) (v_double);
+    __vpcs v_float (*vnf) (v_float);
+#endif
+  } fun;
+} funtab[] = {
+#define D(func, lo, hi) {#func, 'd', 0, lo, hi, {.d = func}},
+#define F(func, lo, hi) {#func, 'f', 0, lo, hi, {.f = func}},
+#define VD(func, lo, hi) {#func, 'd', 'v', lo, hi, {.vd = func}},
+#define VF(func, lo, hi) {#func, 'f', 'v', lo, hi, {.vf = func}},
+#define VND(func, lo, hi) {#func, 'd', 'n', lo, hi, {.vnd = func}},
+#define VNF(func, lo, hi) {#func, 'f', 'n', lo, hi, {.vnf = func}},
+D (dummy, 1.0, 2.0)
+D (exp, -9.9, 9.9)
+D (exp, 0.5, 1.0)
+D (exp2, -9.9, 9.9)
+D (log, 0.01, 11.1)
+D (log, 0.999, 1.001)
+D (log2, 0.01, 11.1)
+D (log2, 0.999, 1.001)
+{"pow", 'd', 0, 0.01, 11.1, {.d = xypow}},
+D (xpow, 0.01, 11.1)
+D (ypow, -9.9, 9.9)
+
+F (dummyf, 1.0, 2.0)
+F (expf, -9.9, 9.9)
+F (exp2f, -9.9, 9.9)
+F (logf, 0.01, 11.1)
+F (log2f, 0.01, 11.1)
+{"powf", 'f', 0, 0.01, 11.1, {.f = xypowf}},
+F (xpowf, 0.01, 11.1)
+F (ypowf, -9.9, 9.9)
+{"sincosf", 'f', 0, 0.1, 0.7, {.f = sincosf_wrap}},
+{"sincosf", 'f', 0, 0.8, 3.1, {.f = sincosf_wrap}},
+{"sincosf", 'f', 0, -3.1, 3.1, {.f = sincosf_wrap}},
+{"sincosf", 'f', 0, 3.3, 33.3, {.f = sincosf_wrap}},
+{"sincosf", 'f', 0, 100, 1000, {.f = sincosf_wrap}},
+{"sincosf", 'f', 0, 1e6, 1e32, {.f = sincosf_wrap}},
+F (sinf, 0.1, 0.7)
+F (sinf, 0.8, 3.1)
+F (sinf, -3.1, 3.1)
+F (sinf, 3.3, 33.3)
+F (sinf, 100, 1000)
+F (sinf, 1e6, 1e32)
+F (cosf, 0.1, 0.7)
+F (cosf, 0.8, 3.1)
+F (cosf, -3.1, 3.1)
+F (cosf, 3.3, 33.3)
+F (cosf, 100, 1000)
+F (cosf, 1e6, 1e32)
+#if WANT_VMATH
+D (__s_sin, -3.1, 3.1)
+D (__s_cos, -3.1, 3.1)
+D (__s_exp, -9.9, 9.9)
+D (__s_log, 0.01, 11.1)
+{"__s_pow", 'd', 0, 0.01, 11.1, {.d = xy__s_pow}},
+F (__s_expf, -9.9, 9.9)
+F (__s_expf_1u, -9.9, 9.9)
+F (__s_exp2f, -9.9, 9.9)
+F (__s_exp2f_1u, -9.9, 9.9)
+F (__s_logf, 0.01, 11.1)
+{"__s_powf", 'f', 0, 0.01, 11.1, {.f = xy__s_powf}},
+F (__s_sinf, -3.1, 3.1)
+F (__s_cosf, -3.1, 3.1)
+#if __aarch64__
+VD (__v_dummy, 1.0, 2.0)
+VD (__v_sin, -3.1, 3.1)
+VD (__v_cos, -3.1, 3.1)
+VD (__v_exp, -9.9, 9.9)
+VD (__v_log, 0.01, 11.1)
+{"__v_pow", 'd', 'v', 0.01, 11.1, {.vd = xy__v_pow}},
+VF (__v_dummyf, 1.0, 2.0)
+VF (__v_expf, -9.9, 9.9)
+VF (__v_expf_1u, -9.9, 9.9)
+VF (__v_exp2f, -9.9, 9.9)
+VF (__v_exp2f_1u, -9.9, 9.9)
+VF (__v_logf, 0.01, 11.1)
+{"__v_powf", 'f', 'v', 0.01, 11.1, {.vf = xy__v_powf}},
+VF (__v_sinf, -3.1, 3.1)
+VF (__v_cosf, -3.1, 3.1)
+#ifdef __vpcs
+VND (__vn_dummy, 1.0, 2.0)
+VND (__vn_exp, -9.9, 9.9)
+VND (_ZGVnN2v_exp, -9.9, 9.9)
+VND (__vn_log, 0.01, 11.1)
+VND (_ZGVnN2v_log, 0.01, 11.1)
+{"__vn_pow", 'd', 'n', 0.01, 11.1, {.vnd = xy__vn_pow}},
+{"_ZGVnN2vv_pow", 'd', 'n', 0.01, 11.1, {.vnd = xy_Z_pow}},
+VND (__vn_sin, -3.1, 3.1)
+VND (_ZGVnN2v_sin, -3.1, 3.1)
+VND (__vn_cos, -3.1, 3.1)
+VND (_ZGVnN2v_cos, -3.1, 3.1)
+VNF (__vn_dummyf, 1.0, 2.0)
+VNF (__vn_expf, -9.9, 9.9)
+VNF (_ZGVnN4v_expf, -9.9, 9.9)
+VNF (__vn_expf_1u, -9.9, 9.9)
+VNF (__vn_exp2f, -9.9, 9.9)
+VNF (_ZGVnN4v_exp2f, -9.9, 9.9)
+VNF (__vn_exp2f_1u, -9.9, 9.9)
+VNF (__vn_logf, 0.01, 11.1)
+VNF (_ZGVnN4v_logf, 0.01, 11.1)
+{"__vn_powf", 'f', 'n', 0.01, 11.1, {.vnf = xy__vn_powf}},
+{"_ZGVnN4vv_powf", 'f', 'n', 0.01, 11.1, {.vnf = xy_Z_powf}},
+VNF (__vn_sinf, -3.1, 3.1)
+VNF (_ZGVnN4v_sinf, -3.1, 3.1)
+VNF (__vn_cosf, -3.1, 3.1)
+VNF (_ZGVnN4v_cosf, -3.1, 3.1)
+#endif
+#endif
+#endif
+{0},
+#undef F
+#undef D
+#undef VF
+#undef VD
+#undef VNF
+#undef VND
+};
+
+static void
+gen_linear (double lo, double hi)
+{
+  for (int i = 0; i < N; i++)
+    A[i] = (lo * (N - i) + hi * i) / N;
+}
+
+static void
+genf_linear (double lo, double hi)
+{
+  for (int i = 0; i < N; i++)
+    Af[i] = (float)(lo * (N - i) + hi * i) / N;
+}
+
+static inline double
+asdouble (uint64_t i)
+{
+  union
+  {
+    uint64_t i;
+    double f;
+  } u = {i};
+  return u.f;
+}
+
+static uint64_t seed = 0x0123456789abcdef;
+
+static double
+frand (double lo, double hi)
+{
+  seed = 6364136223846793005ULL * seed + 1;
+  return lo + (hi - lo) * (asdouble (seed >> 12 | 0x3ffULL << 52) - 1.0);
+}
+
+static void
+gen_rand (double lo, double hi)
+{
+  for (int i = 0; i < N; i++)
+    A[i] = frand (lo, hi);
+}
+
+static void
+genf_rand (double lo, double hi)
+{
+  for (int i = 0; i < N; i++)
+    Af[i] = (float)frand (lo, hi);
+}
+
+static void
+gen_trace (int index)
+{
+  for (int i = 0; i < N; i++)
+    A[i] = Trace[index + i];
+}
+
+static void
+genf_trace (int index)
+{
+  for (int i = 0; i < N; i++)
+    Af[i] = (float)Trace[index + i];
+}
+
+static void
+run_thruput (double f (double))
+{
+  for (int i = 0; i < N; i++)
+    f (A[i]);
+}
+
+static void
+runf_thruput (float f (float))
+{
+  for (int i = 0; i < N; i++)
+    f (Af[i]);
+}
+
+volatile double zero = 0;
+
+static void
+run_latency (double f (double))
+{
+  double z = zero;
+  double prev = z;
+  for (int i = 0; i < N; i++)
+    prev = f (A[i] + prev * z);
+}
+
+static void
+runf_latency (float f (float))
+{
+  float z = (float)zero;
+  float prev = z;
+  for (int i = 0; i < N; i++)
+    prev = f (Af[i] + prev * z);
+}
+
+static void
+run_v_thruput (v_double f (v_double))
+{
+  for (int i = 0; i < N; i += v_double_len ())
+    f (v_double_load (A+i));
+}
+
+static void
+runf_v_thruput (v_float f (v_float))
+{
+  for (int i = 0; i < N; i += v_float_len ())
+    f (v_float_load (Af+i));
+}
+
+static void
+run_v_latency (v_double f (v_double))
+{
+  v_double z = v_double_dup (zero);
+  v_double prev = z;
+  for (int i = 0; i < N; i += v_double_len ())
+    prev = f (v_double_load (A+i) + prev * z);
+}
+
+static void
+runf_v_latency (v_float f (v_float))
+{
+  v_float z = v_float_dup (zero);
+  v_float prev = z;
+  for (int i = 0; i < N; i += v_float_len ())
+    prev = f (v_float_load (Af+i) + prev * z);
+}
+
+#ifdef __vpcs
+static void
+run_vn_thruput (__vpcs v_double f (v_double))
+{
+  for (int i = 0; i < N; i += v_double_len ())
+    f (v_double_load (A+i));
+}
+
+static void
+runf_vn_thruput (__vpcs v_float f (v_float))
+{
+  for (int i = 0; i < N; i += v_float_len ())
+    f (v_float_load (Af+i));
+}
+
+static void
+run_vn_latency (__vpcs v_double f (v_double))
+{
+  v_double z = v_double_dup (zero);
+  v_double prev = z;
+  for (int i = 0; i < N; i += v_double_len ())
+    prev = f (v_double_load (A+i) + prev * z);
+}
+
+static void
+runf_vn_latency (__vpcs v_float f (v_float))
+{
+  v_float z = v_float_dup (zero);
+  v_float prev = z;
+  for (int i = 0; i < N; i += v_float_len ())
+    prev = f (v_float_load (Af+i) + prev * z);
+}
+#endif
+
+static uint64_t
+tic (void)
+{
+  struct timespec ts;
+  if (clock_gettime (CLOCK_REALTIME, &ts))
+    abort ();
+  return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
+}
+
+#define TIMEIT(run, f) do { \
+  dt = -1; \
+  run (f); /* Warm up.  */ \
+  for (int j = 0; j < measurecount; j++) \
+    { \
+      uint64_t t0 = tic (); \
+      for (int i = 0; i < itercount; i++) \
+	run (f); \
+      uint64_t t1 = tic (); \
+      if (t1 - t0 < dt) \
+	dt = t1 - t0; \
+    } \
+} while (0)
+
+static void
+bench1 (const struct fun *f, int type, double lo, double hi)
+{
+  uint64_t dt = 0;
+  uint64_t ns100;
+  const char *s = type == 't' ? "rthruput" : "latency";
+  int vlen = 1;
+
+  if (f->vec && f->prec == 'd')
+    vlen = v_double_len();
+  else if (f->vec && f->prec == 'f')
+    vlen = v_float_len();
+
+  if (f->prec == 'd' && type == 't' && f->vec == 0)
+    TIMEIT (run_thruput, f->fun.d);
+  else if (f->prec == 'd' && type == 'l' && f->vec == 0)
+    TIMEIT (run_latency, f->fun.d);
+  else if (f->prec == 'f' && type == 't' && f->vec == 0)
+    TIMEIT (runf_thruput, f->fun.f);
+  else if (f->prec == 'f' && type == 'l' && f->vec == 0)
+    TIMEIT (runf_latency, f->fun.f);
+  else if (f->prec == 'd' && type == 't' && f->vec == 'v')
+    TIMEIT (run_v_thruput, f->fun.vd);
+  else if (f->prec == 'd' && type == 'l' && f->vec == 'v')
+    TIMEIT (run_v_latency, f->fun.vd);
+  else if (f->prec == 'f' && type == 't' && f->vec == 'v')
+    TIMEIT (runf_v_thruput, f->fun.vf);
+  else if (f->prec == 'f' && type == 'l' && f->vec == 'v')
+    TIMEIT (runf_v_latency, f->fun.vf);
+#ifdef __vpcs
+  else if (f->prec == 'd' && type == 't' && f->vec == 'n')
+    TIMEIT (run_vn_thruput, f->fun.vnd);
+  else if (f->prec == 'd' && type == 'l' && f->vec == 'n')
+    TIMEIT (run_vn_latency, f->fun.vnd);
+  else if (f->prec == 'f' && type == 't' && f->vec == 'n')
+    TIMEIT (runf_vn_thruput, f->fun.vnf);
+  else if (f->prec == 'f' && type == 'l' && f->vec == 'n')
+    TIMEIT (runf_vn_latency, f->fun.vnf);
+#endif
+
+  if (type == 't')
+    {
+      ns100 = (100 * dt + itercount * N / 2) / (itercount * N);
+      printf ("%9s %8s: %4u.%02u ns/elem %10llu ns in [%g %g]\n", f->name, s,
+	      (unsigned) (ns100 / 100), (unsigned) (ns100 % 100),
+	      (unsigned long long) dt, lo, hi);
+    }
+  else if (type == 'l')
+    {
+      ns100 = (100 * dt + itercount * N / vlen / 2) / (itercount * N / vlen);
+      printf ("%9s %8s: %4u.%02u ns/call %10llu ns in [%g %g]\n", f->name, s,
+	      (unsigned) (ns100 / 100), (unsigned) (ns100 % 100),
+	      (unsigned long long) dt, lo, hi);
+    }
+  fflush (stdout);
+}
+
+static void
+bench (const struct fun *f, double lo, double hi, int type, int gen)
+{
+  if (f->prec == 'd' && gen == 'r')
+    gen_rand (lo, hi);
+  else if (f->prec == 'd' && gen == 'l')
+    gen_linear (lo, hi);
+  else if (f->prec == 'd' && gen == 't')
+    gen_trace (0);
+  else if (f->prec == 'f' && gen == 'r')
+    genf_rand (lo, hi);
+  else if (f->prec == 'f' && gen == 'l')
+    genf_linear (lo, hi);
+  else if (f->prec == 'f' && gen == 't')
+    genf_trace (0);
+
+  if (gen == 't')
+    hi = trace_size / N;
+
+  if (type == 'b' || type == 't')
+    bench1 (f, 't', lo, hi);
+
+  if (type == 'b' || type == 'l')
+    bench1 (f, 'l', lo, hi);
+
+  for (int i = N; i < trace_size; i += N)
+    {
+      if (f->prec == 'd')
+	gen_trace (i);
+      else
+	genf_trace (i);
+
+      lo = i / N;
+      if (type == 'b' || type == 't')
+	bench1 (f, 't', lo, hi);
+
+      if (type == 'b' || type == 'l')
+	bench1 (f, 'l', lo, hi);
+    }
+}
+
+static void
+readtrace (const char *name)
+{
+	int n = 0;
+	FILE *f = strcmp (name, "-") == 0 ? stdin : fopen (name, "r");
+	if (!f)
+	  {
+	    printf ("openning \"%s\" failed: %m\n", name);
+	    exit (1);
+	  }
+	for (;;)
+	  {
+	    if (n >= trace_size)
+	      {
+		trace_size += N;
+		Trace = realloc (Trace, trace_size * sizeof (Trace[0]));
+		if (Trace == NULL)
+		  {
+		    printf ("out of memory\n");
+		    exit (1);
+		  }
+	      }
+	    if (fscanf (f, "%lf", Trace + n) != 1)
+	      break;
+	    n++;
+	  }
+	if (ferror (f) || n == 0)
+	  {
+	    printf ("reading \"%s\" failed: %m\n", name);
+	    exit (1);
+	  }
+	fclose (f);
+	if (n % N == 0)
+	  trace_size = n;
+	for (int i = 0; n < trace_size; n++, i++)
+	  Trace[n] = Trace[i];
+}
+
+static void
+usage (void)
+{
+  printf ("usage: ./mathbench [-g rand|linear|trace] [-t latency|thruput|both] "
+	  "[-i low high] [-f tracefile] [-m measurements] [-c iterations] func "
+	  "[func2 ..]\n");
+  printf ("func:\n");
+  printf ("%7s [run all benchmarks]\n", "all");
+  for (const struct fun *f = funtab; f->name; f++)
+    printf ("%7s [low: %g high: %g]\n", f->name, f->lo, f->hi);
+  exit (1);
+}
+
+int
+main (int argc, char *argv[])
+{
+  int usergen = 0, gen = 'r', type = 'b', all = 0;
+  double lo = 0, hi = 0;
+  const char *tracefile = "-";
+
+  argv++;
+  argc--;
+  for (;;)
+    {
+      if (argc <= 0)
+	usage ();
+      if (argv[0][0] != '-')
+	break;
+      else if (argc >= 3 && strcmp (argv[0], "-i") == 0)
+	{
+	  usergen = 1;
+	  lo = strtod (argv[1], 0);
+	  hi = strtod (argv[2], 0);
+	  argv += 3;
+	  argc -= 3;
+	}
+      else if (argc >= 2 && strcmp (argv[0], "-m") == 0)
+	{
+	  measurecount = strtol (argv[1], 0, 0);
+	  argv += 2;
+	  argc -= 2;
+	}
+      else if (argc >= 2 && strcmp (argv[0], "-c") == 0)
+	{
+	  itercount = strtol (argv[1], 0, 0);
+	  argv += 2;
+	  argc -= 2;
+	}
+      else if (argc >= 2 && strcmp (argv[0], "-g") == 0)
+	{
+	  gen = argv[1][0];
+	  if (strchr ("rlt", gen) == 0)
+	    usage ();
+	  argv += 2;
+	  argc -= 2;
+	}
+      else if (argc >= 2 && strcmp (argv[0], "-f") == 0)
+	{
+	  gen = 't';  /* -f implies -g trace.  */
+	  tracefile = argv[1];
+	  argv += 2;
+	  argc -= 2;
+	}
+      else if (argc >= 2 && strcmp (argv[0], "-t") == 0)
+	{
+	  type = argv[1][0];
+	  if (strchr ("ltb", type) == 0)
+	    usage ();
+	  argv += 2;
+	  argc -= 2;
+	}
+      else
+	usage ();
+    }
+  if (gen == 't')
+    {
+      readtrace (tracefile);
+      lo = hi = 0;
+      usergen = 1;
+    }
+  while (argc > 0)
+    {
+      int found = 0;
+      all = strcmp (argv[0], "all") == 0;
+      for (const struct fun *f = funtab; f->name; f++)
+	if (all || strcmp (argv[0], f->name) == 0)
+	  {
+	    found = 1;
+	    if (!usergen)
+	      {
+		lo = f->lo;
+		hi = f->hi;
+	      }
+	    bench (f, lo, hi, type, gen);
+	    if (usergen && !all)
+	      break;
+	  }
+      if (!found)
+	printf ("unknown function: %s\n", argv[0]);
+      argv++;
+      argc--;
+    }
+  return 0;
+}
diff --git a/libc/AOR_v20.02/math/test/mathtest.c b/libc/AOR_v20.02/math/test/mathtest.c
new file mode 100644
index 0000000000000..efe0a8a744bc5
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/mathtest.c
@@ -0,0 +1,1702 @@
+/*
+ * mathtest.c - test rig for mathlib
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <setjmp.h>
+#include <ctype.h>
+#include <math.h>
+#include <errno.h>
+#include <limits.h>
+#include <fenv.h>
+#include "mathlib.h"
+
+#ifndef math_errhandling
+# define math_errhandling 0
+#endif
+
+#ifdef __cplusplus
+ #define EXTERN_C extern "C"
+#else
+ #define EXTERN_C extern
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifdef IMPORT_SYMBOL
+#define STR2(x) #x
+#define STR(x) STR2(x)
+_Pragma(STR(import IMPORT_SYMBOL))
+#endif
+
+int dmsd, dlsd;
+int quiet = 0;
+int doround = 0;
+unsigned statusmask = FE_ALL_EXCEPT;
+
+#define EXTRABITS (12)
+#define ULPUNIT (1<<EXTRABITS)
+
+typedef int (*test) (void);
+
+/*
+  struct to hold info about a function (which could actually be a macro)
+*/
+typedef struct {
+    enum {
+        t_func, t_macro
+    } type;
+    enum {
+        at_d, at_s,      /* double or single precision float */
+        at_d2, at_s2,    /* same, but taking two args */
+        at_di, at_si,    /* double/single and an int */
+        at_dip, at_sip,  /* double/single and an int ptr */
+        at_ddp, at_ssp,  /* d/s and a d/s ptr */
+        at_dc, at_sc,    /* double or single precision complex */
+        at_dc2, at_sc2   /* same, but taking two args */
+    } argtype;
+    enum {
+        rt_d, rt_s, rt_i, /* double, single, int */
+        rt_dc, rt_sc,     /* double, single precision complex */
+        rt_d2, rt_s2      /* also use res2 */
+    } rettype;
+    union {
+        void* ptr;
+        double (*d_d_ptr)(double);
+        float (*s_s_ptr)(float);
+        int (*d_i_ptr)(double);
+        int (*s_i_ptr)(float);
+        double (*d2_d_ptr)(double, double);
+        float (*s2_s_ptr)(float, float);
+        double (*di_d_ptr)(double,int);
+        float (*si_s_ptr)(float,int);
+        double (*dip_d_ptr)(double,int*);
+        float (*sip_s_ptr)(float,int*);
+        double (*ddp_d_ptr)(double,double*);
+        float (*ssp_s_ptr)(float,float*);
+    } func;
+    enum {
+        m_none,
+        m_isfinite, m_isfinitef,
+        m_isgreater, m_isgreaterequal,
+        m_isgreaterequalf, m_isgreaterf,
+        m_isinf, m_isinff,
+        m_isless, m_islessequal,
+        m_islessequalf, m_islessf,
+        m_islessgreater, m_islessgreaterf,
+        m_isnan, m_isnanf,
+        m_isnormal, m_isnormalf,
+        m_isunordered, m_isunorderedf,
+        m_fpclassify, m_fpclassifyf,
+        m_signbit, m_signbitf,
+        /* not actually a macro, but makes things easier */
+        m_rred, m_rredf,
+        m_cadd, m_csub, m_cmul, m_cdiv,
+        m_caddf, m_csubf, m_cmulf, m_cdivf
+    } macro_name; /* only used if a macro/something that can't be done using func */
+    long long tolerance;
+    const char* name;
+} test_func;
+
+/* used in qsort */
+int compare_tfuncs(const void* a, const void* b) {
+    return strcmp(((test_func*)a)->name, ((test_func*)b)->name);
+}
+
+int is_double_argtype(int argtype) {
+    switch(argtype) {
+    case at_d:
+    case at_d2:
+    case at_dc:
+    case at_dc2:
+        return 1;
+    default:
+        return 0;
+    }
+}
+
+int is_single_argtype(int argtype) {
+    switch(argtype) {
+    case at_s:
+    case at_s2:
+    case at_sc:
+    case at_sc2:
+        return 1;
+    default:
+        return 0;
+    }
+}
+
+int is_double_rettype(int rettype) {
+    switch(rettype) {
+    case rt_d:
+    case rt_dc:
+    case rt_d2:
+        return 1;
+    default:
+        return 0;
+    }
+}
+
+int is_single_rettype(int rettype) {
+    switch(rettype) {
+    case rt_s:
+    case rt_sc:
+    case rt_s2:
+        return 1;
+    default:
+        return 0;
+    }
+}
+
+int is_complex_argtype(int argtype) {
+    switch(argtype) {
+    case at_dc:
+    case at_sc:
+    case at_dc2:
+    case at_sc2:
+        return 1;
+    default:
+        return 0;
+    }
+}
+
+int is_complex_rettype(int rettype) {
+    switch(rettype) {
+    case rt_dc:
+    case rt_sc:
+        return 1;
+    default:
+        return 0;
+    }
+}
+
+/*
+ * Special-case flags indicating that some functions' error
+ * tolerance handling is more complicated than a fixed relative
+ * error bound.
+ */
+#define ABSLOWERBOUND 0x4000000000000000LL
+#define PLUSMINUSPIO2 0x1000000000000000LL
+
+#define ARM_PREFIX(x) x
+
+#define TFUNC(arg,ret,name,tolerance) { t_func, arg, ret, (void*)&name, m_none, tolerance, #name }
+#define TFUNCARM(arg,ret,name,tolerance) { t_func, arg, ret, (void*)& ARM_PREFIX(name), m_none, tolerance, #name }
+#define MFUNC(arg,ret,name,tolerance) { t_macro, arg, ret, NULL, m_##name, tolerance, #name }
+
+/* sincosf wrappers for easier testing.  */
+static float sincosf_sinf(float x) { float s,c; sincosf(x, &s, &c); return s; }
+static float sincosf_cosf(float x) { float s,c; sincosf(x, &s, &c); return c; }
+
+test_func tfuncs[] = {
+    /* trigonometric */
+    TFUNC(at_d,rt_d, acos, 4*ULPUNIT),
+    TFUNC(at_d,rt_d, asin, 4*ULPUNIT),
+    TFUNC(at_d,rt_d, atan, 4*ULPUNIT),
+    TFUNC(at_d2,rt_d, atan2, 4*ULPUNIT),
+
+    TFUNC(at_d,rt_d, tan, 2*ULPUNIT),
+    TFUNC(at_d,rt_d, sin, 2*ULPUNIT),
+    TFUNC(at_d,rt_d, cos, 2*ULPUNIT),
+
+    TFUNC(at_s,rt_s, acosf, 4*ULPUNIT),
+    TFUNC(at_s,rt_s, asinf, 4*ULPUNIT),
+    TFUNC(at_s,rt_s, atanf, 4*ULPUNIT),
+    TFUNC(at_s2,rt_s, atan2f, 4*ULPUNIT),
+    TFUNCARM(at_s,rt_s, tanf, 4*ULPUNIT),
+    TFUNCARM(at_s,rt_s, sinf, 3*ULPUNIT/4),
+    TFUNCARM(at_s,rt_s, cosf, 3*ULPUNIT/4),
+    TFUNCARM(at_s,rt_s, sincosf_sinf, 3*ULPUNIT/4),
+    TFUNCARM(at_s,rt_s, sincosf_cosf, 3*ULPUNIT/4),
+
+    /* hyperbolic */
+    TFUNC(at_d, rt_d, atanh, 4*ULPUNIT),
+    TFUNC(at_d, rt_d, asinh, 4*ULPUNIT),
+    TFUNC(at_d, rt_d, acosh, 4*ULPUNIT),
+    TFUNC(at_d,rt_d, tanh, 4*ULPUNIT),
+    TFUNC(at_d,rt_d, sinh, 4*ULPUNIT),
+    TFUNC(at_d,rt_d, cosh, 4*ULPUNIT),
+
+    TFUNC(at_s, rt_s, atanhf, 4*ULPUNIT),
+    TFUNC(at_s, rt_s, asinhf, 4*ULPUNIT),
+    TFUNC(at_s, rt_s, acoshf, 4*ULPUNIT),
+    TFUNC(at_s,rt_s, tanhf, 4*ULPUNIT),
+    TFUNC(at_s,rt_s, sinhf, 4*ULPUNIT),
+    TFUNC(at_s,rt_s, coshf, 4*ULPUNIT),
+
+    /* exponential and logarithmic */
+    TFUNC(at_d,rt_d, log, 3*ULPUNIT/4),
+    TFUNC(at_d,rt_d, log10, 3*ULPUNIT),
+    TFUNC(at_d,rt_d, log2, 3*ULPUNIT/4),
+    TFUNC(at_d,rt_d, log1p, 2*ULPUNIT),
+    TFUNC(at_d,rt_d, exp, 3*ULPUNIT/4),
+    TFUNC(at_d,rt_d, exp2, 3*ULPUNIT/4),
+    TFUNC(at_d,rt_d, expm1, ULPUNIT),
+    TFUNCARM(at_s,rt_s, logf, ULPUNIT),
+    TFUNC(at_s,rt_s, log10f, 3*ULPUNIT),
+    TFUNCARM(at_s,rt_s, log2f, ULPUNIT),
+    TFUNC(at_s,rt_s, log1pf, 2*ULPUNIT),
+    TFUNCARM(at_s,rt_s, expf, 3*ULPUNIT/4),
+    TFUNCARM(at_s,rt_s, exp2f, 3*ULPUNIT/4),
+    TFUNC(at_s,rt_s, expm1f, ULPUNIT),
+
+    /* power */
+    TFUNC(at_d2,rt_d, pow, 3*ULPUNIT/4),
+    TFUNC(at_d,rt_d, sqrt, ULPUNIT/2),
+    TFUNC(at_d,rt_d, cbrt, 2*ULPUNIT),
+    TFUNC(at_d2, rt_d, hypot, 4*ULPUNIT),
+
+    TFUNCARM(at_s2,rt_s, powf, ULPUNIT),
+    TFUNC(at_s,rt_s, sqrtf, ULPUNIT/2),
+    TFUNC(at_s,rt_s, cbrtf, 2*ULPUNIT),
+    TFUNC(at_s2, rt_s, hypotf, 4*ULPUNIT),
+
+    /* error function */
+    TFUNC(at_d,rt_d, erf, 16*ULPUNIT),
+    TFUNC(at_s,rt_s, erff, 16*ULPUNIT),
+    TFUNC(at_d,rt_d, erfc, 16*ULPUNIT),
+    TFUNC(at_s,rt_s, erfcf, 16*ULPUNIT),
+
+    /* gamma functions */
+    TFUNC(at_d,rt_d, tgamma, 16*ULPUNIT),
+    TFUNC(at_s,rt_s, tgammaf, 16*ULPUNIT),
+    TFUNC(at_d,rt_d, lgamma, 16*ULPUNIT | ABSLOWERBOUND),
+    TFUNC(at_s,rt_s, lgammaf, 16*ULPUNIT | ABSLOWERBOUND),
+
+    TFUNC(at_d,rt_d, ceil, 0),
+    TFUNC(at_s,rt_s, ceilf, 0),
+    TFUNC(at_d2,rt_d, copysign, 0),
+    TFUNC(at_s2,rt_s, copysignf, 0),
+    TFUNC(at_d,rt_d, floor, 0),
+    TFUNC(at_s,rt_s, floorf, 0),
+    TFUNC(at_d2,rt_d, fmax, 0),
+    TFUNC(at_s2,rt_s, fmaxf, 0),
+    TFUNC(at_d2,rt_d, fmin, 0),
+    TFUNC(at_s2,rt_s, fminf, 0),
+    TFUNC(at_d2,rt_d, fmod, 0),
+    TFUNC(at_s2,rt_s, fmodf, 0),
+    MFUNC(at_d, rt_i, fpclassify, 0),
+    MFUNC(at_s, rt_i, fpclassifyf, 0),
+    TFUNC(at_dip,rt_d, frexp, 0),
+    TFUNC(at_sip,rt_s, frexpf, 0),
+    MFUNC(at_d, rt_i, isfinite, 0),
+    MFUNC(at_s, rt_i, isfinitef, 0),
+    MFUNC(at_d, rt_i, isgreater, 0),
+    MFUNC(at_d, rt_i, isgreaterequal, 0),
+    MFUNC(at_s, rt_i, isgreaterequalf, 0),
+    MFUNC(at_s, rt_i, isgreaterf, 0),
+    MFUNC(at_d, rt_i, isinf, 0),
+    MFUNC(at_s, rt_i, isinff, 0),
+    MFUNC(at_d, rt_i, isless, 0),
+    MFUNC(at_d, rt_i, islessequal, 0),
+    MFUNC(at_s, rt_i, islessequalf, 0),
+    MFUNC(at_s, rt_i, islessf, 0),
+    MFUNC(at_d, rt_i, islessgreater, 0),
+    MFUNC(at_s, rt_i, islessgreaterf, 0),
+    MFUNC(at_d, rt_i, isnan, 0),
+    MFUNC(at_s, rt_i, isnanf, 0),
+    MFUNC(at_d, rt_i, isnormal, 0),
+    MFUNC(at_s, rt_i, isnormalf, 0),
+    MFUNC(at_d, rt_i, isunordered, 0),
+    MFUNC(at_s, rt_i, isunorderedf, 0),
+    TFUNC(at_di,rt_d, ldexp, 0),
+    TFUNC(at_si,rt_s, ldexpf, 0),
+    TFUNC(at_ddp,rt_d2, modf, 0),
+    TFUNC(at_ssp,rt_s2, modff, 0),
+#ifndef BIGRANGERED
+    MFUNC(at_d, rt_d, rred, 2*ULPUNIT),
+#else
+    MFUNC(at_d, rt_d, m_rred, ULPUNIT),
+#endif
+    MFUNC(at_d, rt_i, signbit, 0),
+    MFUNC(at_s, rt_i, signbitf, 0),
+};
+
+/*
+ * keywords are: func size op1 op2 result res2 errno op1r op1i op2r op2i resultr resulti
+ * also we ignore: wrongresult wrongres2 wrongerrno
+ * op1 equivalent to op1r, same with op2 and result
+ */
+
+typedef struct {
+    test_func *func;
+    unsigned op1r[2]; /* real part, also used for non-complex numbers */
+    unsigned op1i[2]; /* imaginary part */
+    unsigned op2r[2];
+    unsigned op2i[2];
+    unsigned resultr[3];
+    unsigned resulti[3];
+    enum {
+        rc_none, rc_zero, rc_infinity, rc_nan, rc_finite
+    } resultc; /* special complex results, rc_none means use resultr and resulti as normal */
+    unsigned res2[2];
+    unsigned status;                   /* IEEE status return, if any */
+    unsigned maybestatus;             /* for optional status, or allowance for spurious */
+    int nresult;                       /* number of result words */
+    int in_err, in_err_limit;
+    int err;
+    int maybeerr;
+    int valid;
+    int comment;
+    int random;
+} testdetail;
+
+enum {                                 /* keywords */
+    k_errno, k_errno_in, k_error, k_func, k_maybeerror, k_maybestatus, k_op1, k_op1i, k_op1r, k_op2, k_op2i, k_op2r,
+    k_random, k_res2, k_result, k_resultc, k_resulti, k_resultr, k_status,
+    k_wrongres2, k_wrongresult, k_wrongstatus, k_wrongerrno
+};
+char *keywords[] = {
+    "errno", "errno_in", "error", "func", "maybeerror", "maybestatus", "op1", "op1i", "op1r", "op2", "op2i", "op2r",
+    "random", "res2", "result", "resultc", "resulti", "resultr", "status",
+    "wrongres2", "wrongresult", "wrongstatus", "wrongerrno"
+};
+
+enum {
+    e_0, e_EDOM, e_ERANGE,
+
+    /*
+     * This enum makes sure that we have the right number of errnos in the
+     * errno[] array
+     */
+    e_number_of_errnos
+};
+char *errnos[] = {
+    "0", "EDOM", "ERANGE"
+};
+
+enum {
+    e_none, e_divbyzero, e_domain, e_overflow, e_underflow
+};
+char *errors[] = {
+    "0", "divbyzero", "domain", "overflow", "underflow"
+};
+
+static int verbose, fo, strict;
+
+/* state toggled by random=on / random=off */
+static int randomstate;
+
+/* Canonify a double NaN: SNaNs all become 7FF00000.00000001 and QNaNs
+ * all become 7FF80000.00000001 */
+void canon_dNaN(unsigned a[2]) {
+    if ((a[0] & 0x7FF00000) != 0x7FF00000)
+        return;                        /* not Inf or NaN */
+    if (!(a[0] & 0xFFFFF) && !a[1])
+        return;                        /* Inf */
+    a[0] &= 0x7FF80000;                /* canonify top word */
+    a[1] = 0x00000001;                 /* canonify bottom word */
+}
+
+/* Canonify a single NaN: SNaNs all become 7F800001 and QNaNs
+ * all become 7FC00001. Returns classification of the NaN. */
+void canon_sNaN(unsigned a[1]) {
+    if ((a[0] & 0x7F800000) != 0x7F800000)
+        return;                        /* not Inf or NaN */
+    if (!(a[0] & 0x7FFFFF))
+        return;                        /* Inf */
+    a[0] &= 0x7FC00000;                /* canonify most bits */
+    a[0] |= 0x00000001;                /* canonify bottom bit */
+}
+
+/*
+ * Detect difficult operands for FO mode.
+ */
+int is_dhard(unsigned a[2])
+{
+    if ((a[0] & 0x7FF00000) == 0x7FF00000)
+        return TRUE;                   /* inf or NaN */
+    if ((a[0] & 0x7FF00000) == 0 &&
+        ((a[0] & 0x7FFFFFFF) | a[1]) != 0)
+        return TRUE;                   /* denormal */
+    return FALSE;
+}
+int is_shard(unsigned a[1])
+{
+    if ((a[0] & 0x7F800000) == 0x7F800000)
+        return TRUE;                   /* inf or NaN */
+    if ((a[0] & 0x7F800000) == 0 &&
+        (a[0] & 0x7FFFFFFF) != 0)
+        return TRUE;                   /* denormal */
+    return FALSE;
+}
+
+/*
+ * Normalise all zeroes into +0, for FO mode.
+ */
+void dnormzero(unsigned a[2])
+{
+    if (a[0] == 0x80000000 && a[1] == 0)
+        a[0] = 0;
+}
+void snormzero(unsigned a[1])
+{
+    if (a[0] == 0x80000000)
+        a[0] = 0;
+}
+
+static int find(char *word, char **array, int asize) {
+    int i, j;
+
+    asize /= sizeof(char *);
+
+    i = -1; j = asize;                 /* strictly between i and j */
+    while (j-i > 1) {
+        int k = (i+j) / 2;
+        int c = strcmp(word, array[k]);
+        if (c > 0)
+            i = k;
+        else if (c < 0)
+            j = k;
+        else                           /* found it! */
+            return k;
+    }
+    return -1;                         /* not found */
+}
+
+static test_func* find_testfunc(char *word) {
+    int i, j, asize;
+
+    asize = sizeof(tfuncs)/sizeof(test_func);
+
+    i = -1; j = asize;                 /* strictly between i and j */
+    while (j-i > 1) {
+        int k = (i+j) / 2;
+        int c = strcmp(word, tfuncs[k].name);
+        if (c > 0)
+            i = k;
+        else if (c < 0)
+            j = k;
+        else                           /* found it! */
+            return tfuncs + k;
+    }
+    return NULL;                         /* not found */
+}
+
+static long long calc_error(unsigned a[2], unsigned b[3], int shift, int rettype) {
+    unsigned r0, r1, r2;
+    int sign, carry;
+    long long result;
+
+    /*
+     * If either number is infinite, require exact equality. If
+     * either number is NaN, require that both are NaN. If either
+     * of these requirements is broken, return INT_MAX.
+     */
+    if (is_double_rettype(rettype)) {
+        if ((a[0] & 0x7FF00000) == 0x7FF00000 ||
+            (b[0] & 0x7FF00000) == 0x7FF00000) {
+            if (((a[0] & 0x800FFFFF) || a[1]) &&
+                ((b[0] & 0x800FFFFF) || b[1]) &&
+                (a[0] & 0x7FF00000) == 0x7FF00000 &&
+                (b[0] & 0x7FF00000) == 0x7FF00000)
+                return 0;              /* both NaN - OK */
+            if (!((a[0] & 0xFFFFF) || a[1]) &&
+                !((b[0] & 0xFFFFF) || b[1]) &&
+                a[0] == b[0])
+                return 0;              /* both same sign of Inf - OK */
+            return LLONG_MAX;
+        }
+    } else {
+        if ((a[0] & 0x7F800000) == 0x7F800000 ||
+            (b[0] & 0x7F800000) == 0x7F800000) {
+            if ((a[0] & 0x807FFFFF) &&
+                (b[0] & 0x807FFFFF) &&
+                (a[0] & 0x7F800000) == 0x7F800000 &&
+                (b[0] & 0x7F800000) == 0x7F800000)
+                return 0;              /* both NaN - OK */
+            if (!(a[0] & 0x7FFFFF) &&
+                !(b[0] & 0x7FFFFF) &&
+                a[0] == b[0])
+                return 0;              /* both same sign of Inf - OK */
+            return LLONG_MAX;
+        }
+    }
+
+    /*
+     * Both finite. Return INT_MAX if the signs differ.
+     */
+    if ((a[0] ^ b[0]) & 0x80000000)
+        return LLONG_MAX;
+
+    /*
+     * Now it's just straight multiple-word subtraction.
+     */
+    if (is_double_rettype(rettype)) {
+        r2 = -b[2]; carry = (r2 == 0);
+        r1 = a[1] + ~b[1] + carry; carry = (r1 < a[1] || (carry && r1 == a[1]));
+        r0 = a[0] + ~b[0] + carry;
+    } else {
+        r2 = -b[1]; carry = (r2 == 0);
+        r1 = a[0] + ~b[0] + carry; carry = (r1 < a[0] || (carry && r1 == a[0]));
+        r0 = ~0 + carry;
+    }
+
+    /*
+     * Forgive larger errors in specialised cases.
+     */
+    if (shift > 0) {
+        if (shift > 32*3)
+            return 0;                  /* all errors are forgiven! */
+        while (shift >= 32) {
+            r2 = r1;
+            r1 = r0;
+            r0 = -(r0 >> 31);
+            shift -= 32;
+        }
+
+        if (shift > 0) {
+            r2 = (r2 >> shift) | (r1 << (32-shift));
+            r1 = (r1 >> shift) | (r0 << (32-shift));
+            r0 = (r0 >> shift) | ((-(r0 >> 31)) << (32-shift));
+        }
+    }
+
+    if (r0 & 0x80000000) {
+        sign = 1;
+        r2 = ~r2; carry = (r2 == 0);
+        r1 = 0 + ~r1 + carry; carry = (carry && (r2 == 0));
+        r0 = 0 + ~r0 + carry;
+    } else {
+        sign = 0;
+    }
+
+    if (r0 >= (1LL<<(31-EXTRABITS)))
+        return LLONG_MAX;                /* many ulps out */
+
+    result = (r2 >> (32-EXTRABITS)) & (ULPUNIT-1);
+    result |= r1 << EXTRABITS;
+    result |= (long long)r0 << (32+EXTRABITS);
+    if (sign)
+        result = -result;
+    return result;
+}
+
+/* special named operands */
+
+typedef struct {
+    unsigned op1, op2;
+    char* name;
+} special_op;
+
+static special_op special_ops_double[] = {
+    {0x00000000,0x00000000,"0"},
+    {0x3FF00000,0x00000000,"1"},
+    {0x7FF00000,0x00000000,"inf"},
+    {0x7FF80000,0x00000001,"qnan"},
+    {0x7FF00000,0x00000001,"snan"},
+    {0x3ff921fb,0x54442d18,"pi2"},
+    {0x400921fb,0x54442d18,"pi"},
+    {0x3fe921fb,0x54442d18,"pi4"},
+    {0x4002d97c,0x7f3321d2,"3pi4"},
+};
+
+static special_op special_ops_float[] = {
+    {0x00000000,0,"0"},
+    {0x3f800000,0,"1"},
+    {0x7f800000,0,"inf"},
+    {0x7fc00000,0,"qnan"},
+    {0x7f800001,0,"snan"},
+    {0x3fc90fdb,0,"pi2"},
+    {0x40490fdb,0,"pi"},
+    {0x3f490fdb,0,"pi4"},
+    {0x4016cbe4,0,"3pi4"},
+};
+
+/*
+   This is what is returned by the below functions.
+   We need it to handle the sign of the number
+*/
+static special_op tmp_op = {0,0,0};
+
+special_op* find_special_op_from_op(unsigned op1, unsigned op2, int is_double) {
+    int i;
+    special_op* sop;
+    if(is_double) {
+        sop = special_ops_double;
+    } else {
+        sop = special_ops_float;
+    }
+    for(i = 0; i < sizeof(special_ops_double)/sizeof(special_op); i++) {
+        if(sop->op1 == (op1&0x7fffffff) && sop->op2 == op2) {
+            if(tmp_op.name) free(tmp_op.name);
+            tmp_op.name = malloc(strlen(sop->name)+2);
+            if(op1>>31) {
+                sprintf(tmp_op.name,"-%s",sop->name);
+            } else {
+                strcpy(tmp_op.name,sop->name);
+            }
+            return &tmp_op;
+        }
+        sop++;
+    }
+    return NULL;
+}
+
+special_op* find_special_op_from_name(const char* name, int is_double) {
+    int i, neg=0;
+    special_op* sop;
+    if(is_double) {
+        sop = special_ops_double;
+    } else {
+        sop = special_ops_float;
+    }
+    if(*name=='-') {
+        neg=1;
+        name++;
+    } else if(*name=='+') {
+        name++;
+    }
+    for(i = 0; i < sizeof(special_ops_double)/sizeof(special_op); i++) {
+        if(0 == strcmp(name,sop->name)) {
+            tmp_op.op1 = sop->op1;
+            if(neg) {
+                tmp_op.op1 |= 0x80000000;
+            }
+            tmp_op.op2 = sop->op2;
+            return &tmp_op;
+        }
+        sop++;
+    }
+    return NULL;
+}
+
+/*
+   helper function for the below
+   type=0 for single, 1 for double, 2 for no sop
+*/
+int do_op(char* q, unsigned* op, const char* name, int num, int sop_type) {
+    int i;
+    int n=num;
+    special_op* sop = NULL;
+    for(i = 0; i < num; i++) {
+        op[i] = 0;
+    }
+    if(sop_type<2) {
+        sop = find_special_op_from_name(q,sop_type);
+    }
+    if(sop != NULL) {
+        op[0] = sop->op1;
+        op[1] = sop->op2;
+    } else {
+        switch(num) {
+        case 1: n = sscanf(q, "%x", &op[0]); break;
+        case 2: n = sscanf(q, "%x.%x", &op[0], &op[1]); break;
+        case 3: n = sscanf(q, "%x.%x.%x", &op[0], &op[1], &op[2]); break;
+        default: return -1;
+        }
+    }
+    if (verbose) {
+        printf("%s=",name);
+        for (i = 0; (i < n); ++i) printf("%x.", op[i]);
+        printf(" (n=%d)\n", n);
+    }
+    return n;
+}
+
+testdetail parsetest(char *testbuf, testdetail oldtest) {
+    char *p; /* Current part of line: Option name */
+    char *q; /* Current part of line: Option value */
+    testdetail ret; /* What we return */
+    int k; /* Function enum from k_* */
+    int n; /* Used as returns for scanfs */
+    int argtype=2, rettype=2; /* for do_op */
+
+    /* clear ret */
+    memset(&ret, 0, sizeof(ret));
+
+    if (verbose) printf("Parsing line: %s\n", testbuf);
+    while (*testbuf && isspace(*testbuf)) testbuf++;
+    if (testbuf[0] == ';' || testbuf[0] == '#' || testbuf[0] == '!' ||
+        testbuf[0] == '>' || testbuf[0] == '\0') {
+        ret.comment = 1;
+        if (verbose) printf("Line is a comment\n");
+        return ret;
+    }
+    ret.comment = 0;
+
+    if (*testbuf == '+') {
+        if (oldtest.valid) {
+            ret = oldtest;             /* structure copy */
+        } else {
+            fprintf(stderr, "copy from invalid: ignored\n");
+        }
+        testbuf++;
+    }
+
+    ret.random = randomstate;
+
+    ret.in_err = 0;
+    ret.in_err_limit = e_number_of_errnos;
+
+    p = strtok(testbuf, " \t");
+    while (p != NULL) {
+        q = strchr(p, '=');
+        if (!q)
+            goto balderdash;
+        *q++ = '\0';
+        k = find(p, keywords, sizeof(keywords));
+        switch (k) {
+        case k_random:
+            randomstate = (!strcmp(q, "on"));
+            ret.comment = 1;
+            return ret;                /* otherwise ignore this line */
+        case k_func:
+            if (verbose) printf("func=%s ", q);
+            //ret.func = find(q, funcs, sizeof(funcs));
+            ret.func = find_testfunc(q);
+            if (ret.func == NULL)
+                {
+                    if (verbose) printf("(id=unknown)\n");
+                    goto balderdash;
+                }
+            if(is_single_argtype(ret.func->argtype))
+                argtype = 0;
+            else if(is_double_argtype(ret.func->argtype))
+                argtype = 1;
+            if(is_single_rettype(ret.func->rettype))
+                rettype = 0;
+            else if(is_double_rettype(ret.func->rettype))
+                rettype = 1;
+            //ret.size = sizes[ret.func];
+            if (verbose) printf("(name=%s) (size=%d)\n", ret.func->name, ret.func->argtype);
+            break;
+        case k_op1:
+        case k_op1r:
+            n = do_op(q,ret.op1r,"op1r",2,argtype);
+            if (n < 1)
+                goto balderdash;
+            break;
+        case k_op1i:
+            n = do_op(q,ret.op1i,"op1i",2,argtype);
+            if (n < 1)
+                goto balderdash;
+            break;
+        case k_op2:
+        case k_op2r:
+            n = do_op(q,ret.op2r,"op2r",2,argtype);
+            if (n < 1)
+                goto balderdash;
+            break;
+        case k_op2i:
+            n = do_op(q,ret.op2i,"op2i",2,argtype);
+            if (n < 1)
+                goto balderdash;
+            break;
+        case k_resultc:
+            puts(q);
+            if(strncmp(q,"inf",3)==0) {
+                ret.resultc = rc_infinity;
+            } else if(strcmp(q,"zero")==0) {
+                ret.resultc = rc_zero;
+            } else if(strcmp(q,"nan")==0) {
+                ret.resultc = rc_nan;
+            } else if(strcmp(q,"finite")==0) {
+                ret.resultc = rc_finite;
+            } else {
+                goto balderdash;
+            }
+            break;
+        case k_result:
+        case k_resultr:
+            n = (do_op)(q,ret.resultr,"resultr",3,rettype);
+            if (n < 1)
+                goto balderdash;
+            ret.nresult = n; /* assume real and imaginary have same no. words */
+            break;
+        case k_resulti:
+            n = do_op(q,ret.resulti,"resulti",3,rettype);
+            if (n < 1)
+                goto balderdash;
+            break;
+        case k_res2:
+            n = do_op(q,ret.res2,"res2",2,rettype);
+            if (n < 1)
+                goto balderdash;
+            break;
+        case k_status:
+            while (*q) {
+                if (*q == 'i') ret.status |= FE_INVALID;
+                if (*q == 'z') ret.status |= FE_DIVBYZERO;
+                if (*q == 'o') ret.status |= FE_OVERFLOW;
+                if (*q == 'u') ret.status |= FE_UNDERFLOW;
+                q++;
+            }
+            break;
+        case k_maybeerror:
+            n = find(q, errors, sizeof(errors));
+            if (n < 0)
+                goto balderdash;
+            if(math_errhandling&MATH_ERREXCEPT) {
+                switch(n) {
+                case e_domain: ret.maybestatus |= FE_INVALID; break;
+                case e_divbyzero: ret.maybestatus |= FE_DIVBYZERO; break;
+                case e_overflow: ret.maybestatus |= FE_OVERFLOW; break;
+                case e_underflow: ret.maybestatus |= FE_UNDERFLOW; break;
+                }
+            }
+            {
+                switch(n) {
+                case e_domain:
+                    ret.maybeerr = e_EDOM; break;
+                case e_divbyzero:
+                case e_overflow:
+                case e_underflow:
+                    ret.maybeerr = e_ERANGE; break;
+                }
+            }
+        case k_maybestatus:
+            while (*q) {
+                if (*q == 'i') ret.maybestatus |= FE_INVALID;
+                if (*q == 'z') ret.maybestatus |= FE_DIVBYZERO;
+                if (*q == 'o') ret.maybestatus |= FE_OVERFLOW;
+                if (*q == 'u') ret.maybestatus |= FE_UNDERFLOW;
+                q++;
+            }
+            break;
+        case k_error:
+            n = find(q, errors, sizeof(errors));
+            if (n < 0)
+                goto balderdash;
+            if(math_errhandling&MATH_ERREXCEPT) {
+                switch(n) {
+                case e_domain: ret.status |= FE_INVALID; break;
+                case e_divbyzero: ret.status |= FE_DIVBYZERO; break;
+                case e_overflow: ret.status |= FE_OVERFLOW; break;
+                case e_underflow: ret.status |= FE_UNDERFLOW; break;
+                }
+            }
+            if(math_errhandling&MATH_ERRNO) {
+                switch(n) {
+                case e_domain:
+                    ret.err = e_EDOM; break;
+                case e_divbyzero:
+                case e_overflow:
+                case e_underflow:
+                    ret.err = e_ERANGE; break;
+                }
+            }
+            if(!(math_errhandling&MATH_ERRNO)) {
+                switch(n) {
+                case e_domain:
+                    ret.maybeerr = e_EDOM; break;
+                case e_divbyzero:
+                case e_overflow:
+                case e_underflow:
+                    ret.maybeerr = e_ERANGE; break;
+                }
+            }
+            break;
+        case k_errno:
+            ret.err = find(q, errnos, sizeof(errnos));
+            if (ret.err < 0)
+                goto balderdash;
+            break;
+        case k_errno_in:
+            ret.in_err = find(q, errnos, sizeof(errnos));
+            if (ret.err < 0)
+                goto balderdash;
+            ret.in_err_limit = ret.in_err + 1;
+            break;
+        case k_wrongresult:
+        case k_wrongstatus:
+        case k_wrongres2:
+        case k_wrongerrno:
+            /* quietly ignore these keys */
+            break;
+        default:
+            goto balderdash;
+        }
+        p = strtok(NULL, " \t");
+    }
+    ret.valid = 1;
+    return ret;
+
+    /* come here from almost any error */
+ balderdash:
+    ret.valid = 0;
+    return ret;
+}
+
+typedef enum {
+    test_comment,                      /* deliberately not a test */
+    test_invalid,                      /* accidentally not a test */
+    test_decline,                      /* was a test, and wasn't run */
+    test_fail,                         /* was a test, and failed */
+    test_pass                          /* was a test, and passed */
+} testresult;
+
+char failtext[512];
+
+typedef union {
+    unsigned i[2];
+    double f;
+    double da[2];
+} dbl;
+
+typedef union {
+    unsigned i;
+    float f;
+    float da[2];
+} sgl;
+
+/* helper function for runtest */
+void print_error(int rettype, unsigned *result, char* text, char** failp) {
+    special_op *sop;
+    char *str;
+
+    if(result) {
+        *failp += sprintf(*failp," %s=",text);
+        sop = find_special_op_from_op(result[0],result[1],is_double_rettype(rettype));
+        if(sop) {
+            *failp += sprintf(*failp,"%s",sop->name);
+        } else {
+            if(is_double_rettype(rettype)) {
+                str="%08x.%08x";
+            } else {
+                str="%08x";
+            }
+            *failp += sprintf(*failp,str,result[0],result[1]);
+        }
+    }
+}
+
+
+void print_ulps_helper(const char *name, long long ulps, char** failp) {
+    if(ulps == LLONG_MAX) {
+        *failp += sprintf(*failp, " %s=HUGE", name);
+    } else {
+        *failp += sprintf(*failp, " %s=%.3f", name, (double)ulps / ULPUNIT);
+    }
+}
+
+/* for complex args make ulpsr or ulpsri = 0 to not print */
+void print_ulps(int rettype, long long ulpsr, long long ulpsi, char** failp) {
+    if(is_complex_rettype(rettype)) {
+        if (ulpsr) print_ulps_helper("ulpsr",ulpsr,failp);
+        if (ulpsi) print_ulps_helper("ulpsi",ulpsi,failp);
+    } else {
+        if (ulpsr) print_ulps_helper("ulps",ulpsr,failp);
+    }
+}
+
+int runtest(testdetail t) {
+    int err, status;
+
+    dbl d_arg1, d_arg2, d_res, d_res2;
+    sgl s_arg1, s_arg2, s_res, s_res2;
+
+    int deferred_decline = FALSE;
+    char *failp = failtext;
+
+    unsigned int intres=0;
+
+    int res2_adjust = 0;
+
+    if (t.comment)
+        return test_comment;
+    if (!t.valid)
+        return test_invalid;
+
+    /* Set IEEE status to mathlib-normal */
+    feclearexcept(FE_ALL_EXCEPT);
+
+    /* Deal with operands */
+#define DO_DOP(arg,op) arg.i[dmsd] = t.op[0]; arg.i[dlsd] = t.op[1]
+    DO_DOP(d_arg1,op1r);
+    DO_DOP(d_arg2,op2r);
+    s_arg1.i = t.op1r[0]; s_arg2.i = t.op2r[0];
+
+    /*
+     * Detect NaNs, infinities and denormals on input, and set a
+     * deferred decline flag if we're in FO mode.
+     *
+     * (We defer the decline rather than doing it immediately
+     * because even in FO mode the operation is not permitted to
+     * crash or tight-loop; so we _run_ the test, and then ignore
+     * all the results.)
+     */
+    if (fo) {
+        if (is_double_argtype(t.func->argtype) && is_dhard(t.op1r))
+            deferred_decline = TRUE;
+        if (t.func->argtype==at_d2 && is_dhard(t.op2r))
+            deferred_decline = TRUE;
+        if (is_single_argtype(t.func->argtype) && is_shard(t.op1r))
+            deferred_decline = TRUE;
+        if (t.func->argtype==at_s2 && is_shard(t.op2r))
+            deferred_decline = TRUE;
+        if (is_double_rettype(t.func->rettype) && is_dhard(t.resultr))
+            deferred_decline = TRUE;
+        if (t.func->rettype==rt_d2 && is_dhard(t.res2))
+            deferred_decline = TRUE;
+        if (is_single_argtype(t.func->rettype) && is_shard(t.resultr))
+            deferred_decline = TRUE;
+        if (t.func->rettype==rt_s2 && is_shard(t.res2))
+            deferred_decline = TRUE;
+        if (t.err == e_ERANGE)
+            deferred_decline = TRUE;
+    }
+
+    /*
+     * Perform the operation
+     */
+
+    errno = t.in_err == e_EDOM ? EDOM : t.in_err == e_ERANGE ? ERANGE : 0;
+    if (t.err == e_0)
+        t.err = t.in_err;
+    if (t.maybeerr == e_0)
+        t.maybeerr = t.in_err;
+
+    if(t.func->type == t_func) {
+        switch(t.func->argtype) {
+        case at_d: d_res.f = t.func->func.d_d_ptr(d_arg1.f); break;
+        case at_s: s_res.f = t.func->func.s_s_ptr(s_arg1.f); break;
+        case at_d2: d_res.f = t.func->func.d2_d_ptr(d_arg1.f, d_arg2.f); break;
+        case at_s2: s_res.f = t.func->func.s2_s_ptr(s_arg1.f, s_arg2.f); break;
+        case at_di: d_res.f = t.func->func.di_d_ptr(d_arg1.f, d_arg2.i[dmsd]); break;
+        case at_si: s_res.f = t.func->func.si_s_ptr(s_arg1.f, s_arg2.i); break;
+        case at_dip: d_res.f = t.func->func.dip_d_ptr(d_arg1.f, (int*)&intres); break;
+        case at_sip: s_res.f = t.func->func.sip_s_ptr(s_arg1.f, (int*)&intres); break;
+        case at_ddp: d_res.f = t.func->func.ddp_d_ptr(d_arg1.f, &d_res2.f); break;
+        case at_ssp: s_res.f = t.func->func.ssp_s_ptr(s_arg1.f, &s_res2.f); break;
+        default:
+            printf("unhandled function: %s\n",t.func->name);
+            return test_fail;
+        }
+    } else {
+        /* printf("macro: name=%s, num=%i, s1.i=0x%08x s1.f=%f\n",t.func->name, t.func->macro_name, s_arg1.i, (double)s_arg1.f); */
+        switch(t.func->macro_name) {
+        case m_isfinite: intres = isfinite(d_arg1.f); break;
+        case m_isinf: intres = isinf(d_arg1.f); break;
+        case m_isnan: intres = isnan(d_arg1.f); break;
+        case m_isnormal: intres = isnormal(d_arg1.f); break;
+        case m_signbit: intres = signbit(d_arg1.f); break;
+        case m_fpclassify: intres = fpclassify(d_arg1.f); break;
+        case m_isgreater: intres = isgreater(d_arg1.f, d_arg2.f); break;
+        case m_isgreaterequal: intres = isgreaterequal(d_arg1.f, d_arg2.f); break;
+        case m_isless: intres = isless(d_arg1.f, d_arg2.f); break;
+        case m_islessequal: intres = islessequal(d_arg1.f, d_arg2.f); break;
+        case m_islessgreater: intres = islessgreater(d_arg1.f, d_arg2.f); break;
+        case m_isunordered: intres = isunordered(d_arg1.f, d_arg2.f); break;
+
+        case m_isfinitef: intres = isfinite(s_arg1.f); break;
+        case m_isinff: intres = isinf(s_arg1.f); break;
+        case m_isnanf: intres = isnan(s_arg1.f); break;
+        case m_isnormalf: intres = isnormal(s_arg1.f); break;
+        case m_signbitf: intres = signbit(s_arg1.f); break;
+        case m_fpclassifyf: intres = fpclassify(s_arg1.f); break;
+        case m_isgreaterf: intres = isgreater(s_arg1.f, s_arg2.f); break;
+        case m_isgreaterequalf: intres = isgreaterequal(s_arg1.f, s_arg2.f); break;
+        case m_islessf: intres = isless(s_arg1.f, s_arg2.f); break;
+        case m_islessequalf: intres = islessequal(s_arg1.f, s_arg2.f); break;
+        case m_islessgreaterf: intres = islessgreater(s_arg1.f, s_arg2.f); break;
+        case m_isunorderedf: intres = isunordered(s_arg1.f, s_arg2.f); break;
+
+        default:
+            printf("unhandled macro: %s\n",t.func->name);
+            return test_fail;
+        }
+    }
+
+    /*
+     * Decline the test if the deferred decline flag was set above.
+     */
+    if (deferred_decline)
+        return test_decline;
+
+    /* printf("intres=%i\n",intres); */
+
+    /* Clear the fail text (indicating a pass unless we change it) */
+    failp[0] = '\0';
+
+    /* Check the IEEE status bits (except INX, which we disregard).
+     * We don't bother with this for complex numbers, because the
+     * complex functions are hard to get exactly right and we don't
+     * have to anyway (C99 annex G is only informative). */
+    if (!(is_complex_argtype(t.func->argtype) || is_complex_rettype(t.func->rettype))) {
+        status = fetestexcept(FE_INVALID|FE_DIVBYZERO|FE_OVERFLOW|FE_UNDERFLOW);
+        if ((status|t.maybestatus|~statusmask) != (t.status|t.maybestatus|~statusmask)) {
+            if (quiet) failtext[0]='x';
+            else {
+                failp += sprintf(failp,
+                                 " wrongstatus=%s%s%s%s%s",
+                                 (status & FE_INVALID ? "i" : ""),
+                                 (status & FE_DIVBYZERO ? "z" : ""),
+                                 (status & FE_OVERFLOW ? "o" : ""),
+                                 (status & FE_UNDERFLOW ? "u" : ""),
+                                 (status ? "" : "OK"));
+            }
+        }
+    }
+
+    /* Check the result */
+    {
+        unsigned resultr[2], resulti[2];
+        unsigned tresultr[3], tresulti[3], wres;
+
+        switch(t.func->rettype) {
+        case rt_d:
+        case rt_d2:
+            tresultr[0] = t.resultr[0];
+            tresultr[1] = t.resultr[1];
+            resultr[0] = d_res.i[dmsd]; resultr[1] = d_res.i[dlsd];
+            wres = 2;
+            break;
+        case rt_i:
+            tresultr[0] = t.resultr[0];
+            resultr[0] = intres;
+            wres = 1;
+            break;
+        case rt_s:
+        case rt_s2:
+            tresultr[0] = t.resultr[0];
+            resultr[0] = s_res.i;
+            wres = 1;
+            break;
+        default:
+            puts("unhandled rettype in runtest");
+            wres = 0;
+        }
+        if(t.resultc != rc_none) {
+            int err = 0;
+            switch(t.resultc) {
+            case rc_zero:
+                if(resultr[0] != 0 || resulti[0] != 0 ||
+                   (wres==2 && (resultr[1] != 0 || resulti[1] != 0))) {
+                    err = 1;
+                }
+                break;
+            case rc_infinity:
+                if(wres==1) {
+                    if(!((resultr[0]&0x7fffffff)==0x7f800000 ||
+                         (resulti[0]&0x7fffffff)==0x7f800000)) {
+                        err = 1;
+                    }
+                } else {
+                  if(!(((resultr[0]&0x7fffffff)==0x7ff00000 && resultr[1]==0) ||
+                       ((resulti[0]&0x7fffffff)==0x7ff00000 && resulti[1]==0))) {
+                        err = 1;
+                    }
+                }
+                break;
+            case rc_nan:
+                if(wres==1) {
+                    if(!((resultr[0]&0x7fffffff)>0x7f800000 ||
+                         (resulti[0]&0x7fffffff)>0x7f800000)) {
+                        err = 1;
+                    }
+                } else {
+                    canon_dNaN(resultr);
+                    canon_dNaN(resulti);
+                    if(!(((resultr[0]&0x7fffffff)>0x7ff00000 && resultr[1]==1) ||
+                         ((resulti[0]&0x7fffffff)>0x7ff00000 && resulti[1]==1))) {
+                        err = 1;
+                    }
+                }
+                break;
+            case rc_finite:
+                if(wres==1) {
+                    if(!((resultr[0]&0x7fffffff)<0x7f800000 ||
+                         (resulti[0]&0x7fffffff)<0x7f800000)) {
+                        err = 1;
+                    }
+                } else {
+                    if(!((resultr[0]&0x7fffffff)<0x7ff00000 ||
+                         (resulti[0]&0x7fffffff)<0x7ff00000)) {
+                        err = 1;
+                    }
+                }
+                break;
+            default:
+                break;
+            }
+            if(err) {
+                print_error(t.func->rettype,resultr,"wrongresultr",&failp);
+                print_error(t.func->rettype,resulti,"wrongresulti",&failp);
+            }
+        } else if (t.nresult > wres) {
+            /*
+             * The test case data has provided the result to more
+             * than double precision. Instead of testing exact
+             * equality, we test against our maximum error
+             * tolerance.
+             */
+            int rshift, ishift;
+            long long ulpsr, ulpsi, ulptolerance;
+
+            tresultr[wres] = t.resultr[wres] << (32-EXTRABITS);
+            tresulti[wres] = t.resulti[wres] << (32-EXTRABITS);
+            if(strict) {
+                ulptolerance = 4096; /* one ulp */
+            } else {
+                ulptolerance = t.func->tolerance;
+            }
+            rshift = ishift = 0;
+            if (ulptolerance & ABSLOWERBOUND) {
+                /*
+                 * Hack for the lgamma functions, which have an
+                 * error behaviour that can't conveniently be
+                 * characterised in pure ULPs. Really, we want to
+                 * say that the error in lgamma is "at most N ULPs,
+                 * or at most an absolute error of X, whichever is
+                 * larger", for appropriately chosen N,X. But since
+                 * these two functions are the only cases where it
+                 * arises, I haven't bothered to do it in a nice way
+                 * in the function table above.
+                 *
+                 * (The difficult cases arise with negative input
+                 * values such that |gamma(x)| is very near to 1; in
+                 * this situation implementations tend to separately
+                 * compute lgamma(|x|) and the log of the correction
+                 * term from the Euler reflection formula, and
+                 * subtract - which catastrophically loses
+                 * significance.)
+                 *
+                 * As far as I can tell, nobody cares about this:
+                 * GNU libm doesn't get those cases right either,
+                 * and OpenCL explicitly doesn't state a ULP error
+                 * limit for lgamma. So my guess is that this is
+                 * simply considered acceptable error behaviour for
+                 * this particular function, and hence I feel free
+                 * to allow for it here.
+                 */
+                ulptolerance &= ~ABSLOWERBOUND;
+                if (t.op1r[0] & 0x80000000) {
+                    if (t.func->rettype == rt_d)
+                        rshift = 0x400 - ((tresultr[0] >> 20) & 0x7ff);
+                    else if (t.func->rettype == rt_s)
+                        rshift = 0x80 - ((tresultr[0] >> 23) & 0xff);
+                    if (rshift < 0)
+                        rshift = 0;
+                }
+            }
+            if (ulptolerance & PLUSMINUSPIO2) {
+                ulptolerance &= ~PLUSMINUSPIO2;
+                /*
+                 * Hack for range reduction, which can reduce
+                 * borderline cases in the wrong direction, i.e.
+                 * return a value just outside one end of the interval
+                 * [-pi/4,+pi/4] when it could have returned a value
+                 * just inside the other end by subtracting an
+                 * adjacent multiple of pi/2.
+                 *
+                 * We tolerate this, up to a point, because the
+                 * trigonometric functions making use of the output of
+                 * rred can cope and because making the range reducer
+                 * do the exactly right thing in every case would be
+                 * more expensive.
+                 */
+                if (wres == 1) {
+                    /* Upper bound of overshoot derived in rredf.h */
+                    if ((resultr[0]&0x7FFFFFFF) <= 0x3f494b02 &&
+                        (resultr[0]&0x7FFFFFFF) > 0x3f490fda &&
+                        (resultr[0]&0x80000000) != (tresultr[0]&0x80000000)) {
+                        unsigned long long val;
+                        val = tresultr[0];
+                        val = (val << 32) | tresultr[1];
+                        /*
+                         * Compute the alternative permitted result by
+                         * subtracting from the sum of the extended
+                         * single-precision bit patterns of +pi/4 and
+                         * -pi/4. This is a horrible hack which only
+                         * works because we can be confident that
+                         * numbers in this range all have the same
+                         * exponent!
+                         */
+                        val = 0xfe921fb54442d184ULL - val;
+                        tresultr[0] = val >> 32;
+                        tresultr[1] = (val >> (32-EXTRABITS)) << (32-EXTRABITS);
+                        /*
+                         * Also, expect a correspondingly different
+                         * value of res2 as a result of this change.
+                         * The adjustment depends on whether we just
+                         * flipped the result from + to - or vice
+                         * versa.
+                         */
+                        if (resultr[0] & 0x80000000) {
+                            res2_adjust = +1;
+                        } else {
+                            res2_adjust = -1;
+                        }
+                    }
+                }
+            }
+            ulpsr = calc_error(resultr, tresultr, rshift, t.func->rettype);
+            if(is_complex_rettype(t.func->rettype)) {
+                ulpsi = calc_error(resulti, tresulti, ishift, t.func->rettype);
+            } else {
+                ulpsi = 0;
+            }
+            unsigned *rr = (ulpsr > ulptolerance || ulpsr < -ulptolerance) ? resultr : NULL;
+            unsigned *ri = (ulpsi > ulptolerance || ulpsi < -ulptolerance) ? resulti : NULL;
+/*             printf("tolerance=%i, ulpsr=%i, ulpsi=%i, rr=%p, ri=%p\n",ulptolerance,ulpsr,ulpsi,rr,ri); */
+            if (rr || ri) {
+                if (quiet) failtext[0]='x';
+                else {
+                    print_error(t.func->rettype,rr,"wrongresultr",&failp);
+                    print_error(t.func->rettype,ri,"wrongresulti",&failp);
+                    print_ulps(t.func->rettype,rr ? ulpsr : 0, ri ? ulpsi : 0,&failp);
+                }
+            }
+        } else {
+            if(is_complex_rettype(t.func->rettype))
+                /*
+                 * Complex functions are not fully supported,
+                 * this is unreachable, but prevents warnings.
+                 */
+                abort();
+            /*
+             * The test case data has provided the result in
+             * exactly the output precision. Therefore we must
+             * complain about _any_ violation.
+             */
+            switch(t.func->rettype) {
+            case rt_dc:
+                canon_dNaN(tresulti);
+                canon_dNaN(resulti);
+                if (fo) {
+                    dnormzero(tresulti);
+                    dnormzero(resulti);
+                }
+                /* deliberate fall-through */
+            case rt_d:
+                canon_dNaN(tresultr);
+                canon_dNaN(resultr);
+                if (fo) {
+                    dnormzero(tresultr);
+                    dnormzero(resultr);
+                }
+                break;
+            case rt_sc:
+                canon_sNaN(tresulti);
+                canon_sNaN(resulti);
+                if (fo) {
+                    snormzero(tresulti);
+                    snormzero(resulti);
+                }
+                /* deliberate fall-through */
+            case rt_s:
+                canon_sNaN(tresultr);
+                canon_sNaN(resultr);
+                if (fo) {
+                    snormzero(tresultr);
+                    snormzero(resultr);
+                }
+                break;
+            default:
+                break;
+            }
+            if(is_complex_rettype(t.func->rettype)) {
+                unsigned *rr, *ri;
+                if(resultr[0] != tresultr[0] ||
+                   (wres > 1 && resultr[1] != tresultr[1])) {
+                    rr = resultr;
+                } else {
+                    rr = NULL;
+                }
+                if(resulti[0] != tresulti[0] ||
+                   (wres > 1 && resulti[1] != tresulti[1])) {
+                    ri = resulti;
+                } else {
+                    ri = NULL;
+                }
+                if(rr || ri) {
+                    if (quiet) failtext[0]='x';
+                    print_error(t.func->rettype,rr,"wrongresultr",&failp);
+                    print_error(t.func->rettype,ri,"wrongresulti",&failp);
+                }
+            } else if (resultr[0] != tresultr[0] ||
+                       (wres > 1 && resultr[1] != tresultr[1])) {
+                if (quiet) failtext[0]='x';
+                print_error(t.func->rettype,resultr,"wrongresult",&failp);
+            }
+        }
+        /*
+         * Now test res2, for those functions (frexp, modf, rred)
+         * which use it.
+         */
+        if (t.func->func.ptr == &frexp || t.func->func.ptr == &frexpf ||
+            t.func->macro_name == m_rred || t.func->macro_name == m_rredf) {
+            unsigned tres2 = t.res2[0];
+            if (res2_adjust) {
+                /* Fix for range reduction, propagated from further up */
+                tres2 = (tres2 + res2_adjust) & 3;
+            }
+            if (tres2 != intres) {
+                if (quiet) failtext[0]='x';
+                else {
+                    failp += sprintf(failp,
+                                     " wrongres2=%08x", intres);
+                }
+            }
+        } else if (t.func->func.ptr == &modf || t.func->func.ptr == &modff) {
+            tresultr[0] = t.res2[0];
+            tresultr[1] = t.res2[1];
+            if (is_double_rettype(t.func->rettype)) {
+                canon_dNaN(tresultr);
+                resultr[0] = d_res2.i[dmsd];
+                resultr[1] = d_res2.i[dlsd];
+                canon_dNaN(resultr);
+                if (fo) {
+                    dnormzero(tresultr);
+                    dnormzero(resultr);
+                }
+            } else {
+                canon_sNaN(tresultr);
+                resultr[0] = s_res2.i;
+                resultr[1] = s_res2.i;
+                canon_sNaN(resultr);
+                if (fo) {
+                    snormzero(tresultr);
+                    snormzero(resultr);
+                }
+            }
+            if (resultr[0] != tresultr[0] ||
+                (wres > 1 && resultr[1] != tresultr[1])) {
+                if (quiet) failtext[0]='x';
+                else {
+                    if (is_double_rettype(t.func->rettype))
+                        failp += sprintf(failp, " wrongres2=%08x.%08x",
+                                         resultr[0], resultr[1]);
+                    else
+                        failp += sprintf(failp, " wrongres2=%08x",
+                                         resultr[0]);
+                }
+            }
+        }
+    }
+
+    /* Check errno */
+    err = (errno == EDOM ? e_EDOM : errno == ERANGE ? e_ERANGE : e_0);
+    if (err != t.err && err != t.maybeerr) {
+        if (quiet) failtext[0]='x';
+        else {
+            failp += sprintf(failp, " wrongerrno=%s expecterrno=%s ", errnos[err], errnos[t.err]);
+        }
+    }
+
+    return *failtext ? test_fail : test_pass;
+}
+
+int passed, failed, declined;
+
+void runtests(char *name, FILE *fp) {
+    char testbuf[512], linebuf[512];
+    int lineno = 1;
+    testdetail test;
+
+    test.valid = 0;
+
+    if (verbose) printf("runtests: %s\n", name);
+    while (fgets(testbuf, sizeof(testbuf), fp)) {
+        int res, print_errno;
+        testbuf[strcspn(testbuf, "\r\n")] = '\0';
+        strcpy(linebuf, testbuf);
+        test = parsetest(testbuf, test);
+        print_errno = 0;
+        while (test.in_err < test.in_err_limit) {
+            res = runtest(test);
+            if (res == test_pass) {
+                if (verbose)
+                    printf("%s:%d: pass\n", name, lineno);
+                ++passed;
+            } else if (res == test_decline) {
+                if (verbose)
+                    printf("%s:%d: declined\n", name, lineno);
+                ++declined;
+            } else if (res == test_fail) {
+                if (!quiet)
+                    printf("%s:%d: FAIL%s: %s%s%s%s\n", name, lineno,
+                           test.random ? " (random)" : "",
+                           linebuf,
+                           print_errno ? " errno_in=" : "",
+                           print_errno ? errnos[test.in_err] : "",
+                           failtext);
+                ++failed;
+            } else if (res == test_invalid) {
+                printf("%s:%d: malformed: %s\n", name, lineno, linebuf);
+                ++failed;
+            }
+            test.in_err++;
+            print_errno = 1;
+        }
+        lineno++;
+    }
+}
+
+int main(int ac, char **av) {
+    char **files;
+    int i, nfiles = 0;
+    dbl d;
+
+#ifdef MICROLIB
+    /*
+     * Invent argc and argv ourselves.
+     */
+    char *argv[256];
+    char args[256];
+    {
+        int sargs[2];
+        char *p;
+
+        ac = 0;
+
+        sargs[0]=(int)args;
+        sargs[1]=(int)sizeof(args);
+        if (!__semihost(0x15, sargs)) {
+            args[sizeof(args)-1] = '\0';   /* just in case */
+            p = args;
+            while (1) {
+                while (*p == ' ' || *p == '\t') p++;
+                if (!*p) break;
+                argv[ac++] = p;
+                while (*p && *p != ' ' && *p != '\t') p++;
+                if (*p) *p++ = '\0';
+            }
+        }
+
+        av = argv;
+    }
+#endif
+
+    /* Sort tfuncs */
+    qsort(tfuncs, sizeof(tfuncs)/sizeof(test_func), sizeof(test_func), &compare_tfuncs);
+
+    /*
+     * Autodetect the `double' endianness.
+     */
+    dmsd = 0;
+    d.f = 1.0;                       /* 0x3ff00000 / 0x00000000 */
+    if (d.i[dmsd] == 0) {
+        dmsd = 1;
+    }
+    /*
+     * Now dmsd denotes what the compiler thinks we're at. Let's
+     * check that it agrees with what the runtime thinks.
+     */
+    d.i[0] = d.i[1] = 0x11111111;/* a random +ve number */
+    d.f /= d.f;                    /* must now be one */
+    if (d.i[dmsd] == 0) {
+        fprintf(stderr, "YIKES! Compiler and runtime disagree on endianness"
+                " of `double'. Bailing out\n");
+        return 1;
+    }
+    dlsd = !dmsd;
+
+    /* default is terse */
+    verbose = 0;
+    fo = 0;
+    strict = 0;
+
+    files = (char **)malloc((ac+1) * sizeof(char *));
+    if (!files) {
+        fprintf(stderr, "initial malloc failed!\n");
+        return 1;
+    }
+#ifdef NOCMDLINE
+    files[nfiles++] = "testfile";
+#endif
+
+    while (--ac) {
+        char *p = *++av;
+        if (*p == '-') {
+            static char *options[] = {
+                "-fo",
+#if 0
+                "-noinexact",
+                "-noround",
+#endif
+                "-nostatus",
+                "-quiet",
+                "-strict",
+                "-v",
+                "-verbose",
+            };
+            enum {
+                op_fo,
+#if 0
+                op_noinexact,
+                op_noround,
+#endif
+                op_nostatus,
+                op_quiet,
+                op_strict,
+                op_v,
+                op_verbose,
+            };
+            switch (find(p, options, sizeof(options))) {
+            case op_quiet:
+                quiet = 1;
+                break;
+#if 0
+            case op_noinexact:
+                statusmask &= 0x0F;    /* remove bit 4 */
+                break;
+            case op_noround:
+                doround = 0;
+                break;
+#endif
+            case op_nostatus:        /* no status word => noinx,noround */
+                statusmask = 0;
+                doround = 0;
+                break;
+            case op_v:
+            case op_verbose:
+                verbose = 1;
+                break;
+            case op_fo:
+                fo = 1;
+                break;
+            case op_strict: /* tolerance is 1 ulp */
+                strict = 1;
+                break;
+            default:
+                fprintf(stderr, "unrecognised option: %s\n", p);
+                break;
+            }
+        } else {
+            files[nfiles++] = p;
+        }
+    }
+
+    passed = failed = declined = 0;
+
+    if (nfiles) {
+        for (i = 0; i < nfiles; i++) {
+            FILE *fp = fopen(files[i], "r");
+            if (!fp) {
+                fprintf(stderr, "Couldn't open %s\n", files[i]);
+            } else
+                runtests(files[i], fp);
+        }
+    } else
+        runtests("(stdin)", stdin);
+
+    printf("Completed. Passed %d, failed %d (total %d",
+           passed, failed, passed+failed);
+    if (declined)
+        printf(" plus %d declined", declined);
+    printf(")\n");
+    if (failed || passed == 0)
+        return 1;
+    printf("** TEST PASSED OK **\n");
+    return 0;
+}
+
+void undef_func() {
+    failed++;
+    puts("ERROR: undefined function called");
+}
diff --git a/libc/AOR_v20.02/math/test/rtest/dotest.c b/libc/AOR_v20.02/math/test/rtest/dotest.c
new file mode 100644
index 0000000000000..43278626e75e8
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/dotest.c
@@ -0,0 +1,2168 @@
+/*
+ * dotest.c - actually generate mathlib test cases
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <assert.h>
+#include <limits.h>
+
+#include "semi.h"
+#include "intern.h"
+#include "random.h"
+
+#define MPFR_PREC 96 /* good enough for float or double + a few extra bits */
+
+extern int lib_fo, lib_no_arith, ntests;
+
+/*
+ * Prototypes.
+ */
+static void cases_biased(uint32 *, uint32, uint32);
+static void cases_biased_positive(uint32 *, uint32, uint32);
+static void cases_biased_float(uint32 *, uint32, uint32);
+static void cases_uniform(uint32 *, uint32, uint32);
+static void cases_uniform_positive(uint32 *, uint32, uint32);
+static void cases_uniform_float(uint32 *, uint32, uint32);
+static void cases_uniform_float_positive(uint32 *, uint32, uint32);
+static void log_cases(uint32 *, uint32, uint32);
+static void log_cases_float(uint32 *, uint32, uint32);
+static void log1p_cases(uint32 *, uint32, uint32);
+static void log1p_cases_float(uint32 *, uint32, uint32);
+static void minmax_cases(uint32 *, uint32, uint32);
+static void minmax_cases_float(uint32 *, uint32, uint32);
+static void atan2_cases(uint32 *, uint32, uint32);
+static void atan2_cases_float(uint32 *, uint32, uint32);
+static void pow_cases(uint32 *, uint32, uint32);
+static void pow_cases_float(uint32 *, uint32, uint32);
+static void rred_cases(uint32 *, uint32, uint32);
+static void rred_cases_float(uint32 *, uint32, uint32);
+static void cases_semi1(uint32 *, uint32, uint32);
+static void cases_semi1_float(uint32 *, uint32, uint32);
+static void cases_semi2(uint32 *, uint32, uint32);
+static void cases_semi2_float(uint32 *, uint32, uint32);
+static void cases_ldexp(uint32 *, uint32, uint32);
+static void cases_ldexp_float(uint32 *, uint32, uint32);
+
+static void complex_cases_uniform(uint32 *, uint32, uint32);
+static void complex_cases_uniform_float(uint32 *, uint32, uint32);
+static void complex_cases_biased(uint32 *, uint32, uint32);
+static void complex_cases_biased_float(uint32 *, uint32, uint32);
+static void complex_log_cases(uint32 *, uint32, uint32);
+static void complex_log_cases_float(uint32 *, uint32, uint32);
+static void complex_pow_cases(uint32 *, uint32, uint32);
+static void complex_pow_cases_float(uint32 *, uint32, uint32);
+static void complex_arithmetic_cases(uint32 *, uint32, uint32);
+static void complex_arithmetic_cases_float(uint32 *, uint32, uint32);
+
+static uint32 doubletop(int x, int scale);
+static uint32 floatval(int x, int scale);
+
+/*
+ * Convert back and forth between IEEE bit patterns and the
+ * mpfr_t/mpc_t types.
+ */
+static void set_mpfr_d(mpfr_t x, uint32 h, uint32 l)
+{
+    uint64_t hl = ((uint64_t)h << 32) | l;
+    uint32 exp = (hl >> 52) & 0x7ff;
+    int64_t mantissa = hl & (((uint64_t)1 << 52) - 1);
+    int sign = (hl >> 63) ? -1 : +1;
+    if (exp == 0x7ff) {
+        if (mantissa == 0)
+            mpfr_set_inf(x, sign);
+        else
+            mpfr_set_nan(x);
+    } else if (exp == 0 && mantissa == 0) {
+        mpfr_set_ui(x, 0, GMP_RNDN);
+        mpfr_setsign(x, x, sign < 0, GMP_RNDN);
+    } else {
+        if (exp != 0)
+            mantissa |= ((uint64_t)1 << 52);
+        else
+            exp++;
+        mpfr_set_sj_2exp(x, mantissa * sign, (int)exp - 0x3ff - 52, GMP_RNDN);
+    }
+}
+static void set_mpfr_f(mpfr_t x, uint32 f)
+{
+    uint32 exp = (f >> 23) & 0xff;
+    int32 mantissa = f & ((1 << 23) - 1);
+    int sign = (f >> 31) ? -1 : +1;
+    if (exp == 0xff) {
+        if (mantissa == 0)
+            mpfr_set_inf(x, sign);
+        else
+            mpfr_set_nan(x);
+    } else if (exp == 0 && mantissa == 0) {
+        mpfr_set_ui(x, 0, GMP_RNDN);
+        mpfr_setsign(x, x, sign < 0, GMP_RNDN);
+    } else {
+        if (exp != 0)
+            mantissa |= (1 << 23);
+        else
+            exp++;
+        mpfr_set_sj_2exp(x, mantissa * sign, (int)exp - 0x7f - 23, GMP_RNDN);
+    }
+}
+static void set_mpc_d(mpc_t z, uint32 rh, uint32 rl, uint32 ih, uint32 il)
+{
+    mpfr_t x, y;
+    mpfr_init2(x, MPFR_PREC);
+    mpfr_init2(y, MPFR_PREC);
+    set_mpfr_d(x, rh, rl);
+    set_mpfr_d(y, ih, il);
+    mpc_set_fr_fr(z, x, y, MPC_RNDNN);
+    mpfr_clear(x);
+    mpfr_clear(y);
+}
+static void set_mpc_f(mpc_t z, uint32 r, uint32 i)
+{
+    mpfr_t x, y;
+    mpfr_init2(x, MPFR_PREC);
+    mpfr_init2(y, MPFR_PREC);
+    set_mpfr_f(x, r);
+    set_mpfr_f(y, i);
+    mpc_set_fr_fr(z, x, y, MPC_RNDNN);
+    mpfr_clear(x);
+    mpfr_clear(y);
+}
+static void get_mpfr_d(const mpfr_t x, uint32 *h, uint32 *l, uint32 *extra)
+{
+    uint32_t sign, expfield, mantfield;
+    mpfr_t significand;
+    int exp;
+
+    if (mpfr_nan_p(x)) {
+        *h = 0x7ff80000;
+        *l = 0;
+        *extra = 0;
+        return;
+    }
+
+    sign = mpfr_signbit(x) ? 0x80000000U : 0;
+
+    if (mpfr_inf_p(x)) {
+        *h = 0x7ff00000 | sign;
+        *l = 0;
+        *extra = 0;
+        return;
+    }
+
+    if (mpfr_zero_p(x)) {
+        *h = 0x00000000 | sign;
+        *l = 0;
+        *extra = 0;
+        return;
+    }
+
+    mpfr_init2(significand, MPFR_PREC);
+    mpfr_set(significand, x, GMP_RNDN);
+    exp = mpfr_get_exp(significand);
+    mpfr_set_exp(significand, 0);
+
+    /* Now significand is in [1/2,1), and significand * 2^exp == x.
+     * So the IEEE exponent corresponding to exp==0 is 0x3fe. */
+    if (exp > 0x400) {
+        /* overflow to infinity anyway */
+        *h = 0x7ff00000 | sign;
+        *l = 0;
+        *extra = 0;
+        mpfr_clear(significand);
+        return;
+    }
+
+    if (exp <= -0x3fe || mpfr_zero_p(x))
+        exp = -0x3fd;       /* denormalise */
+    expfield = exp + 0x3fd; /* offset to cancel leading mantissa bit */
+
+    mpfr_div_2si(significand, x, exp - 21, GMP_RNDN);
+    mpfr_abs(significand, significand, GMP_RNDN);
+    mantfield = mpfr_get_ui(significand, GMP_RNDZ);
+    *h = sign + ((uint64_t)expfield << 20) + mantfield;
+    mpfr_sub_ui(significand, significand, mantfield, GMP_RNDN);
+    mpfr_mul_2ui(significand, significand, 32, GMP_RNDN);
+    mantfield = mpfr_get_ui(significand, GMP_RNDZ);
+    *l = mantfield;
+    mpfr_sub_ui(significand, significand, mantfield, GMP_RNDN);
+    mpfr_mul_2ui(significand, significand, 32, GMP_RNDN);
+    mantfield = mpfr_get_ui(significand, GMP_RNDZ);
+    *extra = mantfield;
+
+    mpfr_clear(significand);
+}
+static void get_mpfr_f(const mpfr_t x, uint32 *f, uint32 *extra)
+{
+    uint32_t sign, expfield, mantfield;
+    mpfr_t significand;
+    int exp;
+
+    if (mpfr_nan_p(x)) {
+        *f = 0x7fc00000;
+        *extra = 0;
+        return;
+    }
+
+    sign = mpfr_signbit(x) ? 0x80000000U : 0;
+
+    if (mpfr_inf_p(x)) {
+        *f = 0x7f800000 | sign;
+        *extra = 0;
+        return;
+    }
+
+    if (mpfr_zero_p(x)) {
+        *f = 0x00000000 | sign;
+        *extra = 0;
+        return;
+    }
+
+    mpfr_init2(significand, MPFR_PREC);
+    mpfr_set(significand, x, GMP_RNDN);
+    exp = mpfr_get_exp(significand);
+    mpfr_set_exp(significand, 0);
+
+    /* Now significand is in [1/2,1), and significand * 2^exp == x.
+     * So the IEEE exponent corresponding to exp==0 is 0x7e. */
+    if (exp > 0x80) {
+        /* overflow to infinity anyway */
+        *f = 0x7f800000 | sign;
+        *extra = 0;
+        mpfr_clear(significand);
+        return;
+    }
+
+    if (exp <= -0x7e || mpfr_zero_p(x))
+        exp = -0x7d;                   /* denormalise */
+    expfield = exp + 0x7d; /* offset to cancel leading mantissa bit */
+
+    mpfr_div_2si(significand, x, exp - 24, GMP_RNDN);
+    mpfr_abs(significand, significand, GMP_RNDN);
+    mantfield = mpfr_get_ui(significand, GMP_RNDZ);
+    *f = sign + ((uint64_t)expfield << 23) + mantfield;
+    mpfr_sub_ui(significand, significand, mantfield, GMP_RNDN);
+    mpfr_mul_2ui(significand, significand, 32, GMP_RNDN);
+    mantfield = mpfr_get_ui(significand, GMP_RNDZ);
+    *extra = mantfield;
+
+    mpfr_clear(significand);
+}
+static void get_mpc_d(const mpc_t z,
+                      uint32 *rh, uint32 *rl, uint32 *rextra,
+                      uint32 *ih, uint32 *il, uint32 *iextra)
+{
+    mpfr_t x, y;
+    mpfr_init2(x, MPFR_PREC);
+    mpfr_init2(y, MPFR_PREC);
+    mpc_real(x, z, GMP_RNDN);
+    mpc_imag(y, z, GMP_RNDN);
+    get_mpfr_d(x, rh, rl, rextra);
+    get_mpfr_d(y, ih, il, iextra);
+    mpfr_clear(x);
+    mpfr_clear(y);
+}
+static void get_mpc_f(const mpc_t z,
+                      uint32 *r, uint32 *rextra,
+                      uint32 *i, uint32 *iextra)
+{
+    mpfr_t x, y;
+    mpfr_init2(x, MPFR_PREC);
+    mpfr_init2(y, MPFR_PREC);
+    mpc_real(x, z, GMP_RNDN);
+    mpc_imag(y, z, GMP_RNDN);
+    get_mpfr_f(x, r, rextra);
+    get_mpfr_f(y, i, iextra);
+    mpfr_clear(x);
+    mpfr_clear(y);
+}
+
+/*
+ * Implementation of mathlib functions that aren't trivially
+ * implementable using an existing mpfr or mpc function.
+ */
+int test_rred(mpfr_t ret, const mpfr_t x, int *quadrant)
+{
+    mpfr_t halfpi;
+    long quo;
+    int status;
+
+    /*
+     * In the worst case of range reduction, we get an input of size
+     * around 2^1024, and must find its remainder mod pi, which means
+     * we need 1024 bits of pi at least. Plus, the remainder might
+     * happen to come out very very small if we're unlucky. How
+     * unlucky can we be? Well, conveniently, I once went through and
+     * actually worked that out using Paxson's modular minimisation
+     * algorithm, and it turns out that the smallest exponent you can
+     * get out of a nontrivial[1] double precision range reduction is
+     * 0x3c2, i.e. of the order of 2^-61. So we need 1024 bits of pi
+     * to get us down to the units digit, another 61 or so bits (say
+     * 64) to get down to the highest set bit of the output, and then
+     * some bits to make the actual mantissa big enough.
+     *
+     *   [1] of course the output of range reduction can have an
+     *   arbitrarily small exponent in the trivial case, where the
+     *   input is so small that it's the identity function. That
+     *   doesn't count.
+     */
+    mpfr_init2(halfpi, MPFR_PREC + 1024 + 64);
+    mpfr_const_pi(halfpi, GMP_RNDN);
+    mpfr_div_ui(halfpi, halfpi, 2, GMP_RNDN);
+
+    status = mpfr_remquo(ret, &quo, x, halfpi, GMP_RNDN);
+    *quadrant = quo & 3;
+
+    mpfr_clear(halfpi);
+
+    return status;
+}
+int test_lgamma(mpfr_t ret, const mpfr_t x, mpfr_rnd_t rnd)
+{
+    /*
+     * mpfr_lgamma takes an extra int * parameter to hold the output
+     * sign. We don't bother testing that, so this wrapper throws away
+     * the sign and hence fits into the same function prototype as all
+     * the other real->real mpfr functions.
+     *
+     * There is also mpfr_lngamma which has no sign output and hence
+     * has the right prototype already, but unfortunately it returns
+     * NaN in cases where gamma(x) < 0, so it's no use to us.
+     */
+    int sign;
+    return mpfr_lgamma(ret, &sign, x, rnd);
+}
+int test_cpow(mpc_t ret, const mpc_t x, const mpc_t y, mpc_rnd_t rnd)
+{
+    /*
+     * For complex pow, we must bump up the precision by a huge amount
+     * if we want it to get the really difficult cases right. (Not
+     * that we expect the library under test to be getting those cases
+     * right itself, but we'd at least like the test suite to report
+     * them as wrong for the _right reason_.)
+     *
+     * This works around a bug in mpc_pow(), fixed by r1455 in the MPC
+     * svn repository (2014-10-14) and expected to be in any MPC
+     * release after 1.0.2 (which was the latest release already made
+     * at the time of the fix). So as and when we update to an MPC
+     * with the fix in it, we could remove this workaround.
+     *
+     * For the reasons for choosing this amount of extra precision,
+     * see analysis in complex/cpownotes.txt for the rationale for the
+     * amount.
+     */
+    mpc_t xbig, ybig, retbig;
+    int status;
+
+    mpc_init2(xbig, 1034 + 53 + 60 + MPFR_PREC);
+    mpc_init2(ybig, 1034 + 53 + 60 + MPFR_PREC);
+    mpc_init2(retbig, 1034 + 53 + 60 + MPFR_PREC);
+
+    mpc_set(xbig, x, MPC_RNDNN);
+    mpc_set(ybig, y, MPC_RNDNN);
+    status = mpc_pow(retbig, xbig, ybig, rnd);
+    mpc_set(ret, retbig, rnd);
+
+    mpc_clear(xbig);
+    mpc_clear(ybig);
+    mpc_clear(retbig);
+
+    return status;
+}
+
+/*
+ * Identify 'hard' values (NaN, Inf, nonzero denormal) for deciding
+ * whether microlib will decline to run a test.
+ */
+#define is_shard(in) ( \
+    (((in)[0] & 0x7F800000) == 0x7F800000 || \
+     (((in)[0] & 0x7F800000) == 0 && ((in)[0]&0x7FFFFFFF) != 0)))
+
+#define is_dhard(in) ( \
+    (((in)[0] & 0x7FF00000) == 0x7FF00000 || \
+     (((in)[0] & 0x7FF00000) == 0 && (((in)[0] & 0xFFFFF) | (in)[1]) != 0)))
+
+/*
+ * Identify integers.
+ */
+int is_dinteger(uint32 *in)
+{
+    uint32 out[3];
+    if ((0x7FF00000 & ~in[0]) == 0)
+        return 0;                      /* not finite, hence not integer */
+    test_ceil(in, out);
+    return in[0] == out[0] && in[1] == out[1];
+}
+int is_sinteger(uint32 *in)
+{
+    uint32 out[3];
+    if ((0x7F800000 & ~in[0]) == 0)
+        return 0;                      /* not finite, hence not integer */
+    test_ceilf(in, out);
+    return in[0] == out[0];
+}
+
+/*
+ * Identify signalling NaNs.
+ */
+int is_dsnan(const uint32 *in)
+{
+    if ((in[0] & 0x7FF00000) != 0x7FF00000)
+        return 0;                      /* not the inf/nan exponent */
+    if ((in[0] << 12) == 0 && in[1] == 0)
+        return 0;                      /* inf */
+    if (in[0] & 0x00080000)
+        return 0;                      /* qnan */
+    return 1;
+}
+int is_ssnan(const uint32 *in)
+{
+    if ((in[0] & 0x7F800000) != 0x7F800000)
+        return 0;                      /* not the inf/nan exponent */
+    if ((in[0] << 9) == 0)
+        return 0;                      /* inf */
+    if (in[0] & 0x00400000)
+        return 0;                      /* qnan */
+    return 1;
+}
+int is_snan(const uint32 *in, int size)
+{
+    return size == 2 ? is_dsnan(in) : is_ssnan(in);
+}
+
+/*
+ * Wrapper functions called to fix up unusual results after the main
+ * test function has run.
+ */
+void universal_wrapper(wrapperctx *ctx)
+{
+    /*
+     * Any SNaN input gives rise to a QNaN output.
+     */
+    int op;
+    for (op = 0; op < wrapper_get_nops(ctx); op++) {
+        int size = wrapper_get_size(ctx, op);
+
+        if (!wrapper_is_complex(ctx, op) &&
+            is_snan(wrapper_get_ieee(ctx, op), size)) {
+            wrapper_set_nan(ctx);
+        }
+    }
+}
+
+Testable functions[] = {
+    /*
+     * Trig functions: sin, cos, tan. We test the core function
+     * between -16 and +16: we assume that range reduction exists
+     * and will be used for larger arguments, and we'll test that
+     * separately. Also we only go down to 2^-27 in magnitude,
+     * because below that sin(x)=tan(x)=x and cos(x)=1 as far as
+     * double precision can tell, which is boring.
+     */
+    {"sin", (funcptr)mpfr_sin, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x40300000},
+    {"sinf", (funcptr)mpfr_sin, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x41800000},
+    {"cos", (funcptr)mpfr_cos, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x40300000},
+    {"cosf", (funcptr)mpfr_cos, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x41800000},
+    {"tan", (funcptr)mpfr_tan, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x40300000},
+    {"tanf", (funcptr)mpfr_tan, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x41800000},
+    {"sincosf_sinf", (funcptr)mpfr_sin, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x41800000},
+    {"sincosf_cosf", (funcptr)mpfr_cos, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x41800000},
+    /*
+     * Inverse trig: asin, acos. Between 1 and -1, of course. acos
+     * goes down to 2^-54, asin to 2^-27.
+     */
+    {"asin", (funcptr)mpfr_asin, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x3fefffff},
+    {"asinf", (funcptr)mpfr_asin, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x3f7fffff},
+    {"acos", (funcptr)mpfr_acos, args1, {NULL},
+        cases_uniform, 0x3c900000, 0x3fefffff},
+    {"acosf", (funcptr)mpfr_acos, args1f, {NULL},
+        cases_uniform_float, 0x33800000, 0x3f7fffff},
+    /*
+     * Inverse trig: atan. atan is stable (in double prec) with
+     * argument magnitude past 2^53, so we'll test up to there.
+     * atan(x) is boringly just x below 2^-27.
+     */
+    {"atan", (funcptr)mpfr_atan, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x43400000},
+    {"atanf", (funcptr)mpfr_atan, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x4b800000},
+    /*
+     * atan2. Interesting cases arise when the exponents of the
+     * arguments differ by at most about 50.
+     */
+    {"atan2", (funcptr)mpfr_atan2, args2, {NULL},
+        atan2_cases, 0},
+    {"atan2f", (funcptr)mpfr_atan2, args2f, {NULL},
+        atan2_cases_float, 0},
+    /*
+     * The exponentials: exp, sinh, cosh. They overflow at around
+     * 710. exp and sinh are boring below 2^-54, cosh below 2^-27.
+     */
+    {"exp", (funcptr)mpfr_exp, args1, {NULL},
+        cases_uniform, 0x3c900000, 0x40878000},
+    {"expf", (funcptr)mpfr_exp, args1f, {NULL},
+        cases_uniform_float, 0x33800000, 0x42dc0000},
+    {"sinh", (funcptr)mpfr_sinh, args1, {NULL},
+        cases_uniform, 0x3c900000, 0x40878000},
+    {"sinhf", (funcptr)mpfr_sinh, args1f, {NULL},
+        cases_uniform_float, 0x33800000, 0x42dc0000},
+    {"cosh", (funcptr)mpfr_cosh, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x40878000},
+    {"coshf", (funcptr)mpfr_cosh, args1f, {NULL},
+        cases_uniform_float, 0x39800000, 0x42dc0000},
+    /*
+     * tanh is stable past around 20. It's boring below 2^-27.
+     */
+    {"tanh", (funcptr)mpfr_tanh, args1, {NULL},
+        cases_uniform, 0x3e400000, 0x40340000},
+    {"tanhf", (funcptr)mpfr_tanh, args1f, {NULL},
+        cases_uniform, 0x39800000, 0x41100000},
+    /*
+     * log must be tested only on positive numbers, but can cover
+     * the whole range of positive nonzero finite numbers. It never
+     * gets boring.
+     */
+    {"log", (funcptr)mpfr_log, args1, {NULL}, log_cases, 0},
+    {"logf", (funcptr)mpfr_log, args1f, {NULL}, log_cases_float, 0},
+    {"log10", (funcptr)mpfr_log10, args1, {NULL}, log_cases, 0},
+    {"log10f", (funcptr)mpfr_log10, args1f, {NULL}, log_cases_float, 0},
+    /*
+     * pow.
+     */
+    {"pow", (funcptr)mpfr_pow, args2, {NULL}, pow_cases, 0},
+    {"powf", (funcptr)mpfr_pow, args2f, {NULL}, pow_cases_float, 0},
+    /*
+     * Trig range reduction. We are able to test this for all
+     * finite values, but will only bother for things between 2^-3
+     * and 2^+52.
+     */
+    {"rred", (funcptr)test_rred, rred, {NULL}, rred_cases, 0},
+    {"rredf", (funcptr)test_rred, rredf, {NULL}, rred_cases_float, 0},
+    /*
+     * Square and cube root.
+     */
+    {"sqrt", (funcptr)mpfr_sqrt, args1, {NULL}, log_cases, 0},
+    {"sqrtf", (funcptr)mpfr_sqrt, args1f, {NULL}, log_cases_float, 0},
+    {"cbrt", (funcptr)mpfr_cbrt, args1, {NULL}, log_cases, 0},
+    {"cbrtf", (funcptr)mpfr_cbrt, args1f, {NULL}, log_cases_float, 0},
+    {"hypot", (funcptr)mpfr_hypot, args2, {NULL}, atan2_cases, 0},
+    {"hypotf", (funcptr)mpfr_hypot, args2f, {NULL}, atan2_cases_float, 0},
+    /*
+     * Seminumerical functions.
+     */
+    {"ceil", (funcptr)test_ceil, semi1, {NULL}, cases_semi1},
+    {"ceilf", (funcptr)test_ceilf, semi1f, {NULL}, cases_semi1_float},
+    {"floor", (funcptr)test_floor, semi1, {NULL}, cases_semi1},
+    {"floorf", (funcptr)test_floorf, semi1f, {NULL}, cases_semi1_float},
+    {"fmod", (funcptr)test_fmod, semi2, {NULL}, cases_semi2},
+    {"fmodf", (funcptr)test_fmodf, semi2f, {NULL}, cases_semi2_float},
+    {"ldexp", (funcptr)test_ldexp, t_ldexp, {NULL}, cases_ldexp},
+    {"ldexpf", (funcptr)test_ldexpf, t_ldexpf, {NULL}, cases_ldexp_float},
+    {"frexp", (funcptr)test_frexp, t_frexp, {NULL}, cases_semi1},
+    {"frexpf", (funcptr)test_frexpf, t_frexpf, {NULL}, cases_semi1_float},
+    {"modf", (funcptr)test_modf, t_modf, {NULL}, cases_semi1},
+    {"modff", (funcptr)test_modff, t_modff, {NULL}, cases_semi1_float},
+
+    /*
+     * Classification and more semi-numericals
+     */
+    {"copysign", (funcptr)test_copysign, semi2, {NULL}, cases_semi2},
+    {"copysignf", (funcptr)test_copysignf, semi2f, {NULL}, cases_semi2_float},
+    {"isfinite", (funcptr)test_isfinite, classify, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isfinitef", (funcptr)test_isfinitef, classifyf, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"isinf", (funcptr)test_isinf, classify, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isinff", (funcptr)test_isinff, classifyf, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"isnan", (funcptr)test_isnan, classify, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isnanf", (funcptr)test_isnanf, classifyf, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"isnormal", (funcptr)test_isnormal, classify, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isnormalf", (funcptr)test_isnormalf, classifyf, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"signbit", (funcptr)test_signbit, classify, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"signbitf", (funcptr)test_signbitf, classifyf, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"fpclassify", (funcptr)test_fpclassify, classify, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"fpclassifyf", (funcptr)test_fpclassifyf, classifyf, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    /*
+     * Comparisons
+     */
+    {"isgreater", (funcptr)test_isgreater, compare, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isgreaterequal", (funcptr)test_isgreaterequal, compare, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isless", (funcptr)test_isless, compare, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"islessequal", (funcptr)test_islessequal, compare, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"islessgreater", (funcptr)test_islessgreater, compare, {NULL}, cases_uniform, 0, 0x7fffffff},
+    {"isunordered", (funcptr)test_isunordered, compare, {NULL}, cases_uniform, 0, 0x7fffffff},
+
+    {"isgreaterf", (funcptr)test_isgreaterf, comparef, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"isgreaterequalf", (funcptr)test_isgreaterequalf, comparef, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"islessf", (funcptr)test_islessf, comparef, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"islessequalf", (funcptr)test_islessequalf, comparef, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"islessgreaterf", (funcptr)test_islessgreaterf, comparef, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+    {"isunorderedf", (funcptr)test_isunorderedf, comparef, {NULL}, cases_uniform_float, 0, 0x7fffffff},
+
+    /*
+     * Inverse Hyperbolic functions
+     */
+    {"atanh", (funcptr)mpfr_atanh, args1, {NULL}, cases_uniform, 0x3e400000, 0x3fefffff},
+    {"asinh", (funcptr)mpfr_asinh, args1, {NULL}, cases_uniform, 0x3e400000, 0x3fefffff},
+    {"acosh", (funcptr)mpfr_acosh, args1, {NULL}, cases_uniform_positive, 0x3ff00000, 0x7fefffff},
+
+    {"atanhf", (funcptr)mpfr_atanh, args1f, {NULL}, cases_uniform_float, 0x32000000, 0x3f7fffff},
+    {"asinhf", (funcptr)mpfr_asinh, args1f, {NULL}, cases_uniform_float, 0x32000000, 0x3f7fffff},
+    {"acoshf", (funcptr)mpfr_acosh, args1f, {NULL}, cases_uniform_float_positive, 0x3f800000, 0x7f800000},
+
+    /*
+     * Everything else (sitting in a section down here at the bottom
+     * because historically they were not tested because we didn't
+     * have reference implementations for them)
+     */
+    {"csin", (funcptr)mpc_sin, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"csinf", (funcptr)mpc_sin, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"ccos", (funcptr)mpc_cos, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"ccosf", (funcptr)mpc_cos, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"ctan", (funcptr)mpc_tan, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"ctanf", (funcptr)mpc_tan, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+
+    {"casin", (funcptr)mpc_asin, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"casinf", (funcptr)mpc_asin, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"cacos", (funcptr)mpc_acos, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"cacosf", (funcptr)mpc_acos, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"catan", (funcptr)mpc_atan, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"catanf", (funcptr)mpc_atan, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+
+    {"csinh", (funcptr)mpc_sinh, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"csinhf", (funcptr)mpc_sinh, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"ccosh", (funcptr)mpc_cosh, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"ccoshf", (funcptr)mpc_cosh, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"ctanh", (funcptr)mpc_tanh, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"ctanhf", (funcptr)mpc_tanh, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+
+    {"casinh", (funcptr)mpc_asinh, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"casinhf", (funcptr)mpc_asinh, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"cacosh", (funcptr)mpc_acosh, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"cacoshf", (funcptr)mpc_acosh, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+    {"catanh", (funcptr)mpc_atanh, args1c, {NULL}, complex_cases_uniform, 0x3f000000, 0x40300000},
+    {"catanhf", (funcptr)mpc_atanh, args1fc, {NULL}, complex_cases_uniform_float, 0x38000000, 0x41800000},
+
+    {"cexp", (funcptr)mpc_exp, args1c, {NULL}, complex_cases_uniform, 0x3c900000, 0x40862000},
+    {"cpow", (funcptr)test_cpow, args2c, {NULL}, complex_pow_cases, 0x3fc00000, 0x40000000},
+    {"clog", (funcptr)mpc_log, args1c, {NULL}, complex_log_cases, 0, 0},
+    {"csqrt", (funcptr)mpc_sqrt, args1c, {NULL}, complex_log_cases, 0, 0},
+
+    {"cexpf", (funcptr)mpc_exp, args1fc, {NULL}, complex_cases_uniform_float, 0x24800000, 0x42b00000},
+    {"cpowf", (funcptr)test_cpow, args2fc, {NULL}, complex_pow_cases_float, 0x3e000000, 0x41000000},
+    {"clogf", (funcptr)mpc_log, args1fc, {NULL}, complex_log_cases_float, 0, 0},
+    {"csqrtf", (funcptr)mpc_sqrt, args1fc, {NULL}, complex_log_cases_float, 0, 0},
+
+    {"cdiv", (funcptr)mpc_div, args2c, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"cmul", (funcptr)mpc_mul, args2c, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"cadd", (funcptr)mpc_add, args2c, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"csub", (funcptr)mpc_sub, args2c, {NULL}, complex_arithmetic_cases, 0, 0},
+
+    {"cdivf", (funcptr)mpc_div, args2fc, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"cmulf", (funcptr)mpc_mul, args2fc, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"caddf", (funcptr)mpc_add, args2fc, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"csubf", (funcptr)mpc_sub, args2fc, {NULL}, complex_arithmetic_cases_float, 0, 0},
+
+    {"cabsf", (funcptr)mpc_abs, args1fcr, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"cabs", (funcptr)mpc_abs, args1cr, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"cargf", (funcptr)mpc_arg, args1fcr, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"carg", (funcptr)mpc_arg, args1cr, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"cimagf", (funcptr)mpc_imag, args1fcr, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"cimag", (funcptr)mpc_imag, args1cr, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"conjf", (funcptr)mpc_conj, args1fc, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"conj", (funcptr)mpc_conj, args1c, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"cprojf", (funcptr)mpc_proj, args1fc, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"cproj", (funcptr)mpc_proj, args1c, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"crealf", (funcptr)mpc_real, args1fcr, {NULL}, complex_arithmetic_cases_float, 0, 0},
+    {"creal", (funcptr)mpc_real, args1cr, {NULL}, complex_arithmetic_cases, 0, 0},
+    {"erfcf", (funcptr)mpfr_erfc, args1f, {NULL}, cases_biased_float, 0x1e800000, 0x41000000},
+    {"erfc", (funcptr)mpfr_erfc, args1, {NULL}, cases_biased, 0x3bd00000, 0x403c0000},
+    {"erff", (funcptr)mpfr_erf, args1f, {NULL}, cases_biased_float, 0x03800000, 0x40700000},
+    {"erf", (funcptr)mpfr_erf, args1, {NULL}, cases_biased, 0x00800000, 0x40200000},
+    {"exp2f", (funcptr)mpfr_exp2, args1f, {NULL}, cases_uniform_float, 0x33800000, 0x43c00000},
+    {"exp2", (funcptr)mpfr_exp2, args1, {NULL}, cases_uniform, 0x3ca00000, 0x40a00000},
+    {"expm1f", (funcptr)mpfr_expm1, args1f, {NULL}, cases_uniform_float, 0x33000000, 0x43800000},
+    {"expm1", (funcptr)mpfr_expm1, args1, {NULL}, cases_uniform, 0x3c900000, 0x409c0000},
+    {"fmaxf", (funcptr)mpfr_max, args2f, {NULL}, minmax_cases_float, 0, 0x7f7fffff},
+    {"fmax", (funcptr)mpfr_max, args2, {NULL}, minmax_cases, 0, 0x7fefffff},
+    {"fminf", (funcptr)mpfr_min, args2f, {NULL}, minmax_cases_float, 0, 0x7f7fffff},
+    {"fmin", (funcptr)mpfr_min, args2, {NULL}, minmax_cases, 0, 0x7fefffff},
+    {"lgammaf", (funcptr)test_lgamma, args1f, {NULL}, cases_uniform_float, 0x01800000, 0x7f800000},
+    {"lgamma", (funcptr)test_lgamma, args1, {NULL}, cases_uniform, 0x00100000, 0x7ff00000},
+    {"log1pf", (funcptr)mpfr_log1p, args1f, {NULL}, log1p_cases_float, 0, 0},
+    {"log1p", (funcptr)mpfr_log1p, args1, {NULL}, log1p_cases, 0, 0},
+    {"log2f", (funcptr)mpfr_log2, args1f, {NULL}, log_cases_float, 0, 0},
+    {"log2", (funcptr)mpfr_log2, args1, {NULL}, log_cases, 0, 0},
+    {"tgammaf", (funcptr)mpfr_gamma, args1f, {NULL}, cases_uniform_float, 0x2f800000, 0x43000000},
+    {"tgamma", (funcptr)mpfr_gamma, args1, {NULL}, cases_uniform, 0x3c000000, 0x40800000},
+};
+
+const int nfunctions = ( sizeof(functions)/sizeof(*functions) );
+
+#define random_sign ( random_upto(1) ? 0x80000000 : 0 )
+
+static int iszero(uint32 *x) {
+    return !((x[0] & 0x7FFFFFFF) || x[1]);
+}
+
+
+static void complex_log_cases(uint32 *out, uint32 param1,
+                              uint32 param2) {
+    cases_uniform(out,0x00100000,0x7fefffff);
+    cases_uniform(out+2,0x00100000,0x7fefffff);
+}
+
+
+static void complex_log_cases_float(uint32 *out, uint32 param1,
+                                    uint32 param2) {
+    cases_uniform_float(out,0x00800000,0x7f7fffff);
+    cases_uniform_float(out+2,0x00800000,0x7f7fffff);
+}
+
+static void complex_cases_biased(uint32 *out, uint32 lowbound,
+                                 uint32 highbound) {
+    cases_biased(out,lowbound,highbound);
+    cases_biased(out+2,lowbound,highbound);
+}
+
+static void complex_cases_biased_float(uint32 *out, uint32 lowbound,
+                                       uint32 highbound) {
+    cases_biased_float(out,lowbound,highbound);
+    cases_biased_float(out+2,lowbound,highbound);
+}
+
+static void complex_cases_uniform(uint32 *out, uint32 lowbound,
+                                 uint32 highbound) {
+    cases_uniform(out,lowbound,highbound);
+    cases_uniform(out+2,lowbound,highbound);
+}
+
+static void complex_cases_uniform_float(uint32 *out, uint32 lowbound,
+                                       uint32 highbound) {
+    cases_uniform_float(out,lowbound,highbound);
+    cases_uniform(out+2,lowbound,highbound);
+}
+
+static void complex_pow_cases(uint32 *out, uint32 lowbound,
+                              uint32 highbound) {
+    /*
+     * Generating non-overflowing cases for complex pow:
+     *
+     * Our base has both parts within the range [1/2,2], and hence
+     * its magnitude is within [1/2,2*sqrt(2)]. The magnitude of its
+     * logarithm in base 2 is therefore at most the magnitude of
+     * (log2(2*sqrt(2)) + i*pi/log(2)), or in other words
+     * hypot(3/2,pi/log(2)) = 4.77. So the magnitude of the exponent
+     * input must be at most our output magnitude limit (as a power
+     * of two) divided by that.
+     *
+     * I also set the output magnitude limit a bit low, because we
+     * don't guarantee (and neither does glibc) to prevent internal
+     * overflow in cases where the output _magnitude_ overflows but
+     * scaling it back down by cos and sin of the argument brings it
+     * back in range.
+     */
+    cases_uniform(out,0x3fe00000, 0x40000000);
+    cases_uniform(out+2,0x3fe00000, 0x40000000);
+    cases_uniform(out+4,0x3f800000, 0x40600000);
+    cases_uniform(out+6,0x3f800000, 0x40600000);
+}
+
+static void complex_pow_cases_float(uint32 *out, uint32 lowbound,
+                                    uint32 highbound) {
+    /*
+     * Reasoning as above, though of course the detailed numbers are
+     * all different.
+     */
+    cases_uniform_float(out,0x3f000000, 0x40000000);
+    cases_uniform_float(out+2,0x3f000000, 0x40000000);
+    cases_uniform_float(out+4,0x3d600000, 0x41900000);
+    cases_uniform_float(out+6,0x3d600000, 0x41900000);
+}
+
+static void complex_arithmetic_cases(uint32 *out, uint32 lowbound,
+                                     uint32 highbound) {
+    cases_uniform(out,0,0x7fefffff);
+    cases_uniform(out+2,0,0x7fefffff);
+    cases_uniform(out+4,0,0x7fefffff);
+    cases_uniform(out+6,0,0x7fefffff);
+}
+
+static void complex_arithmetic_cases_float(uint32 *out, uint32 lowbound,
+                                           uint32 highbound) {
+    cases_uniform_float(out,0,0x7f7fffff);
+    cases_uniform_float(out+2,0,0x7f7fffff);
+    cases_uniform_float(out+4,0,0x7f7fffff);
+    cases_uniform_float(out+6,0,0x7f7fffff);
+}
+
+/*
+ * Included from fplib test suite, in a compact self-contained
+ * form.
+ */
+
+void float32_case(uint32 *ret) {
+    int n, bits;
+    uint32 f;
+    static int premax, preptr;
+    static uint32 *specifics = NULL;
+
+    if (!ret) {
+        if (specifics)
+            free(specifics);
+        specifics = NULL;
+        premax = preptr = 0;
+        return;
+    }
+
+    if (!specifics) {
+        int exps[] = {
+            -127, -126, -125, -24, -4, -3, -2, -1, 0, 1, 2, 3, 4,
+                24, 29, 30, 31, 32, 61, 62, 63, 64, 126, 127, 128
+        };
+        int sign, eptr;
+        uint32 se, j;
+        /*
+         * We want a cross product of:
+         *  - each of two sign bits (2)
+         *  - each of the above (unbiased) exponents (25)
+         *  - the following list of fraction parts:
+         *    * zero (1)
+         *    * all bits (1)
+         *    * one-bit-set (23)
+         *    * one-bit-clear (23)
+         *    * one-bit-and-above (20: 3 are duplicates)
+         *    * one-bit-and-below (20: 3 are duplicates)
+         *    (total 88)
+         *  (total 4400)
+         */
+        specifics = malloc(4400 * sizeof(*specifics));
+        preptr = 0;
+        for (sign = 0; sign <= 1; sign++) {
+            for (eptr = 0; eptr < sizeof(exps)/sizeof(*exps); eptr++) {
+                se = (sign ? 0x80000000 : 0) | ((exps[eptr]+127) << 23);
+                /*
+                 * Zero.
+                 */
+                specifics[preptr++] = se | 0;
+                /*
+                 * All bits.
+                 */
+                specifics[preptr++] = se | 0x7FFFFF;
+                /*
+                 * One-bit-set.
+                 */
+                for (j = 1; j && j <= 0x400000; j <<= 1)
+                    specifics[preptr++] = se | j;
+                /*
+                 * One-bit-clear.
+                 */
+                for (j = 1; j && j <= 0x400000; j <<= 1)
+                    specifics[preptr++] = se | (0x7FFFFF ^ j);
+                /*
+                 * One-bit-and-everything-below.
+                 */
+                for (j = 2; j && j <= 0x100000; j <<= 1)
+                    specifics[preptr++] = se | (2*j-1);
+                /*
+                 * One-bit-and-everything-above.
+                 */
+                for (j = 4; j && j <= 0x200000; j <<= 1)
+                    specifics[preptr++] = se | (0x7FFFFF ^ (j-1));
+                /*
+                 * Done.
+                 */
+            }
+        }
+        assert(preptr == 4400);
+        premax = preptr;
+    }
+
+    /*
+     * Decide whether to return a pre or a random case.
+     */
+    n = random32() % (premax+1);
+    if (n < preptr) {
+        /*
+         * Return pre[n].
+         */
+        uint32 t;
+        t = specifics[n];
+        specifics[n] = specifics[preptr-1];
+        specifics[preptr-1] = t;        /* (not really needed) */
+        preptr--;
+        *ret = t;
+    } else {
+        /*
+         * Random case.
+         * Sign and exponent:
+         *  - FIXME
+         * Significand:
+         *  - with prob 1/5, a totally random bit pattern
+         *  - with prob 1/5, all 1s down to some point and then random
+         *  - with prob 1/5, all 1s up to some point and then random
+         *  - with prob 1/5, all 0s down to some point and then random
+         *  - with prob 1/5, all 0s up to some point and then random
+         */
+        n = random32() % 5;
+        f = random32();                /* some random bits */
+        bits = random32() % 22 + 1;    /* 1-22 */
+        switch (n) {
+          case 0:
+            break;                     /* leave f alone */
+          case 1:
+            f |= (1<<bits)-1;
+            break;
+          case 2:
+            f &= ~((1<<bits)-1);
+            break;
+          case 3:
+            f |= ~((1<<bits)-1);
+            break;
+          case 4:
+            f &= (1<<bits)-1;
+            break;
+        }
+        f &= 0x7FFFFF;
+        f |= (random32() & 0xFF800000);/* FIXME - do better */
+        *ret = f;
+    }
+}
+static void float64_case(uint32 *ret) {
+    int n, bits;
+    uint32 f, g;
+    static int premax, preptr;
+    static uint32 (*specifics)[2] = NULL;
+
+    if (!ret) {
+        if (specifics)
+            free(specifics);
+        specifics = NULL;
+        premax = preptr = 0;
+        return;
+    }
+
+    if (!specifics) {
+        int exps[] = {
+            -1023, -1022, -1021, -129, -128, -127, -126, -53, -4, -3, -2,
+            -1, 0, 1, 2, 3, 4, 29, 30, 31, 32, 53, 61, 62, 63, 64, 127,
+            128, 129, 1022, 1023, 1024
+        };
+        int sign, eptr;
+        uint32 se, j;
+        /*
+         * We want a cross product of:
+         *  - each of two sign bits (2)
+         *  - each of the above (unbiased) exponents (32)
+         *  - the following list of fraction parts:
+         *    * zero (1)
+         *    * all bits (1)
+         *    * one-bit-set (52)
+         *    * one-bit-clear (52)
+         *    * one-bit-and-above (49: 3 are duplicates)
+         *    * one-bit-and-below (49: 3 are duplicates)
+         *    (total 204)
+         *  (total 13056)
+         */
+        specifics = malloc(13056 * sizeof(*specifics));
+        preptr = 0;
+        for (sign = 0; sign <= 1; sign++) {
+            for (eptr = 0; eptr < sizeof(exps)/sizeof(*exps); eptr++) {
+                se = (sign ? 0x80000000 : 0) | ((exps[eptr]+1023) << 20);
+                /*
+                 * Zero.
+                 */
+                specifics[preptr][0] = 0;
+                specifics[preptr][1] = 0;
+                specifics[preptr++][0] |= se;
+                /*
+                 * All bits.
+                 */
+                specifics[preptr][0] = 0xFFFFF;
+                specifics[preptr][1] = ~0;
+                specifics[preptr++][0] |= se;
+                /*
+                 * One-bit-set.
+                 */
+                for (j = 1; j && j <= 0x80000000; j <<= 1) {
+                    specifics[preptr][0] = 0;
+                    specifics[preptr][1] = j;
+                    specifics[preptr++][0] |= se;
+                    if (j & 0xFFFFF) {
+                        specifics[preptr][0] = j;
+                        specifics[preptr][1] = 0;
+                        specifics[preptr++][0] |= se;
+                    }
+                }
+                /*
+                 * One-bit-clear.
+                 */
+                for (j = 1; j && j <= 0x80000000; j <<= 1) {
+                    specifics[preptr][0] = 0xFFFFF;
+                    specifics[preptr][1] = ~j;
+                    specifics[preptr++][0] |= se;
+                    if (j & 0xFFFFF) {
+                        specifics[preptr][0] = 0xFFFFF ^ j;
+                        specifics[preptr][1] = ~0;
+                        specifics[preptr++][0] |= se;
+                    }
+                }
+                /*
+                 * One-bit-and-everything-below.
+                 */
+                for (j = 2; j && j <= 0x80000000; j <<= 1) {
+                    specifics[preptr][0] = 0;
+                    specifics[preptr][1] = 2*j-1;
+                    specifics[preptr++][0] |= se;
+                }
+                for (j = 1; j && j <= 0x20000; j <<= 1) {
+                    specifics[preptr][0] = 2*j-1;
+                    specifics[preptr][1] = ~0;
+                    specifics[preptr++][0] |= se;
+                }
+                /*
+                 * One-bit-and-everything-above.
+                 */
+                for (j = 4; j && j <= 0x80000000; j <<= 1) {
+                    specifics[preptr][0] = 0xFFFFF;
+                    specifics[preptr][1] = ~(j-1);
+                    specifics[preptr++][0] |= se;
+                }
+                for (j = 1; j && j <= 0x40000; j <<= 1) {
+                    specifics[preptr][0] = 0xFFFFF ^ (j-1);
+                    specifics[preptr][1] = 0;
+                    specifics[preptr++][0] |= se;
+                }
+                /*
+                 * Done.
+                 */
+            }
+        }
+        assert(preptr == 13056);
+        premax = preptr;
+    }
+
+    /*
+     * Decide whether to return a pre or a random case.
+     */
+    n = (uint32) random32() % (uint32) (premax+1);
+    if (n < preptr) {
+        /*
+         * Return pre[n].
+         */
+        uint32 t;
+        t = specifics[n][0];
+        specifics[n][0] = specifics[preptr-1][0];
+        specifics[preptr-1][0] = t;     /* (not really needed) */
+        ret[0] = t;
+        t = specifics[n][1];
+        specifics[n][1] = specifics[preptr-1][1];
+        specifics[preptr-1][1] = t;     /* (not really needed) */
+        ret[1] = t;
+        preptr--;
+    } else {
+        /*
+         * Random case.
+         * Sign and exponent:
+         *  - FIXME
+         * Significand:
+         *  - with prob 1/5, a totally random bit pattern
+         *  - with prob 1/5, all 1s down to some point and then random
+         *  - with prob 1/5, all 1s up to some point and then random
+         *  - with prob 1/5, all 0s down to some point and then random
+         *  - with prob 1/5, all 0s up to some point and then random
+         */
+        n = random32() % 5;
+        f = random32();                /* some random bits */
+        g = random32();                /* some random bits */
+        bits = random32() % 51 + 1;    /* 1-51 */
+        switch (n) {
+          case 0:
+            break;                     /* leave f alone */
+          case 1:
+            if (bits <= 32)
+                f |= (1<<bits)-1;
+            else {
+                bits -= 32;
+                g |= (1<<bits)-1;
+                f = ~0;
+            }
+            break;
+          case 2:
+            if (bits <= 32)
+                f &= ~((1<<bits)-1);
+            else {
+                bits -= 32;
+                g &= ~((1<<bits)-1);
+                f = 0;
+            }
+            break;
+          case 3:
+            if (bits <= 32)
+                g &= (1<<bits)-1;
+            else {
+                bits -= 32;
+                f &= (1<<bits)-1;
+                g = 0;
+            }
+            break;
+          case 4:
+            if (bits <= 32)
+                g |= ~((1<<bits)-1);
+            else {
+                bits -= 32;
+                f |= ~((1<<bits)-1);
+                g = ~0;
+            }
+            break;
+        }
+        g &= 0xFFFFF;
+        g |= (random32() & 0xFFF00000);/* FIXME - do better */
+        ret[0] = g;
+        ret[1] = f;
+    }
+}
+
+static void cases_biased(uint32 *out, uint32 lowbound,
+                          uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto_biased(highbound-lowbound, 8);
+        out[1] = random_upto(0xFFFFFFFF);
+        out[0] |= random_sign;
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void cases_biased_positive(uint32 *out, uint32 lowbound,
+                                  uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto_biased(highbound-lowbound, 8);
+        out[1] = random_upto(0xFFFFFFFF);
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void cases_biased_float(uint32 *out, uint32 lowbound,
+                               uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto_biased(highbound-lowbound, 8);
+        out[1] = 0;
+        out[0] |= random_sign;
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void cases_semi1(uint32 *out, uint32 param1,
+                        uint32 param2) {
+    float64_case(out);
+}
+
+static void cases_semi1_float(uint32 *out, uint32 param1,
+                              uint32 param2) {
+    float32_case(out);
+}
+
+static void cases_semi2(uint32 *out, uint32 param1,
+                        uint32 param2) {
+    float64_case(out);
+    float64_case(out+2);
+}
+
+static void cases_semi2_float(uint32 *out, uint32 param1,
+                        uint32 param2) {
+    float32_case(out);
+    float32_case(out+2);
+}
+
+static void cases_ldexp(uint32 *out, uint32 param1,
+                        uint32 param2) {
+    float64_case(out);
+    out[2] = random_upto(2048)-1024;
+}
+
+static void cases_ldexp_float(uint32 *out, uint32 param1,
+                              uint32 param2) {
+    float32_case(out);
+    out[2] = random_upto(256)-128;
+}
+
+static void cases_uniform(uint32 *out, uint32 lowbound,
+                          uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto(highbound-lowbound);
+        out[1] = random_upto(0xFFFFFFFF);
+        out[0] |= random_sign;
+    } while (iszero(out));             /* rule out zero */
+}
+static void cases_uniform_float(uint32 *out, uint32 lowbound,
+                                uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto(highbound-lowbound);
+        out[1] = 0;
+        out[0] |= random_sign;
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void cases_uniform_positive(uint32 *out, uint32 lowbound,
+                                   uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto(highbound-lowbound);
+        out[1] = random_upto(0xFFFFFFFF);
+    } while (iszero(out));             /* rule out zero */
+}
+static void cases_uniform_float_positive(uint32 *out, uint32 lowbound,
+                                         uint32 highbound) {
+    do {
+        out[0] = highbound - random_upto(highbound-lowbound);
+        out[1] = 0;
+    } while (iszero(out));             /* rule out zero */
+}
+
+
+static void log_cases(uint32 *out, uint32 param1,
+                      uint32 param2) {
+    do {
+        out[0] = random_upto(0x7FEFFFFF);
+        out[1] = random_upto(0xFFFFFFFF);
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void log_cases_float(uint32 *out, uint32 param1,
+                            uint32 param2) {
+    do {
+        out[0] = random_upto(0x7F7FFFFF);
+        out[1] = 0;
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void log1p_cases(uint32 *out, uint32 param1, uint32 param2)
+{
+    uint32 sign = random_sign;
+    if (sign == 0) {
+        cases_uniform_positive(out, 0x3c700000, 0x43400000);
+    } else {
+        cases_uniform_positive(out, 0x3c000000, 0x3ff00000);
+    }
+    out[0] |= sign;
+}
+
+static void log1p_cases_float(uint32 *out, uint32 param1, uint32 param2)
+{
+    uint32 sign = random_sign;
+    if (sign == 0) {
+        cases_uniform_float_positive(out, 0x32000000, 0x4c000000);
+    } else {
+        cases_uniform_float_positive(out, 0x30000000, 0x3f800000);
+    }
+    out[0] |= sign;
+}
+
+static void minmax_cases(uint32 *out, uint32 param1, uint32 param2)
+{
+    do {
+        out[0] = random_upto(0x7FEFFFFF);
+        out[1] = random_upto(0xFFFFFFFF);
+        out[0] |= random_sign;
+        out[2] = random_upto(0x7FEFFFFF);
+        out[3] = random_upto(0xFFFFFFFF);
+        out[2] |= random_sign;
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void minmax_cases_float(uint32 *out, uint32 param1, uint32 param2)
+{
+    do {
+        out[0] = random_upto(0x7F7FFFFF);
+        out[1] = 0;
+        out[0] |= random_sign;
+        out[2] = random_upto(0x7F7FFFFF);
+        out[3] = 0;
+        out[2] |= random_sign;
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void rred_cases(uint32 *out, uint32 param1,
+                       uint32 param2) {
+    do {
+        out[0] = ((0x3fc00000 + random_upto(0x036fffff)) |
+                  (random_upto(1) << 31));
+        out[1] = random_upto(0xFFFFFFFF);
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void rred_cases_float(uint32 *out, uint32 param1,
+                             uint32 param2) {
+    do {
+        out[0] = ((0x3e000000 + random_upto(0x0cffffff)) |
+                  (random_upto(1) << 31));
+        out[1] = 0;                    /* for iszero */
+    } while (iszero(out));             /* rule out zero */
+}
+
+static void atan2_cases(uint32 *out, uint32 param1,
+                        uint32 param2) {
+    do {
+        int expdiff = random_upto(101)-51;
+        int swap;
+        if (expdiff < 0) {
+            expdiff = -expdiff;
+            swap = 2;
+        } else
+            swap = 0;
+        out[swap ^ 0] = random_upto(0x7FEFFFFF-((expdiff+1)<<20));
+        out[swap ^ 2] = random_upto(((expdiff+1)<<20)-1) + out[swap ^ 0];
+        out[1] = random_upto(0xFFFFFFFF);
+        out[3] = random_upto(0xFFFFFFFF);
+        out[0] |= random_sign;
+        out[2] |= random_sign;
+    } while (iszero(out) || iszero(out+2));/* rule out zero */
+}
+
+static void atan2_cases_float(uint32 *out, uint32 param1,
+                              uint32 param2) {
+    do {
+        int expdiff = random_upto(44)-22;
+        int swap;
+        if (expdiff < 0) {
+            expdiff = -expdiff;
+            swap = 2;
+        } else
+            swap = 0;
+        out[swap ^ 0] = random_upto(0x7F7FFFFF-((expdiff+1)<<23));
+        out[swap ^ 2] = random_upto(((expdiff+1)<<23)-1) + out[swap ^ 0];
+        out[0] |= random_sign;
+        out[2] |= random_sign;
+        out[1] = out[3] = 0;           /* for iszero */
+    } while (iszero(out) || iszero(out+2));/* rule out zero */
+}
+
+static void pow_cases(uint32 *out, uint32 param1,
+                      uint32 param2) {
+    /*
+     * Pick an exponent e (-0x33 to +0x7FE) for x, and here's the
+     * range of numbers we can use as y:
+     *
+     * For e < 0x3FE, the range is [-0x400/(0x3FE-e),+0x432/(0x3FE-e)]
+     * For e > 0x3FF, the range is [-0x432/(e-0x3FF),+0x400/(e-0x3FF)]
+     *
+     * For e == 0x3FE or e == 0x3FF, the range gets infinite at one
+     * end or the other, so we have to be cleverer: pick a number n
+     * of useful bits in the mantissa (1 thru 52, so 1 must imply
+     * 0x3ff00000.00000001 whereas 52 is anything at least as big
+     * as 0x3ff80000.00000000; for e == 0x3fe, 1 necessarily means
+     * 0x3fefffff.ffffffff and 52 is anything at most as big as
+     * 0x3fe80000.00000000). Then, as it happens, a sensible
+     * maximum power is 2^(63-n) for e == 0x3fe, and 2^(62-n) for
+     * e == 0x3ff.
+     *
+     * We inevitably get some overflows in approximating the log
+     * curves by these nasty step functions, but that's all right -
+     * we do want _some_ overflows to be tested.
+     *
+     * Having got that, then, it's just a matter of inventing a
+     * probability distribution for all of this.
+     */
+    int e, n;
+    uint32 dmin, dmax;
+    const uint32 pmin = 0x3e100000;
+
+    /*
+     * Generate exponents in a slightly biased fashion.
+     */
+    e = (random_upto(1) ?              /* is exponent small or big? */
+         0x3FE - random_upto_biased(0x431,2) :   /* small */
+         0x3FF + random_upto_biased(0x3FF,2));   /* big */
+
+    /*
+     * Now split into cases.
+     */
+    if (e < 0x3FE || e > 0x3FF) {
+        uint32 imin, imax;
+        if (e < 0x3FE)
+            imin = 0x40000 / (0x3FE - e), imax = 0x43200 / (0x3FE - e);
+        else
+            imin = 0x43200 / (e - 0x3FF), imax = 0x40000 / (e - 0x3FF);
+        /* Power range runs from -imin to imax. Now convert to doubles */
+        dmin = doubletop(imin, -8);
+        dmax = doubletop(imax, -8);
+        /* Compute the number of mantissa bits. */
+        n = (e > 0 ? 53 : 52+e);
+    } else {
+        /* Critical exponents. Generate a top bit index. */
+        n = 52 - random_upto_biased(51, 4);
+        if (e == 0x3FE)
+            dmax = 63 - n;
+        else
+            dmax = 62 - n;
+        dmax = (dmax << 20) + 0x3FF00000;
+        dmin = dmax;
+    }
+    /* Generate a mantissa. */
+    if (n <= 32) {
+        out[0] = 0;
+        out[1] = random_upto((1 << (n-1)) - 1) + (1 << (n-1));
+    } else if (n == 33) {
+        out[0] = 1;
+        out[1] = random_upto(0xFFFFFFFF);
+    } else if (n > 33) {
+        out[0] = random_upto((1 << (n-33)) - 1) + (1 << (n-33));
+        out[1] = random_upto(0xFFFFFFFF);
+    }
+    /* Negate the mantissa if e == 0x3FE. */
+    if (e == 0x3FE) {
+        out[1] = -out[1];
+        out[0] = -out[0];
+        if (out[1]) out[0]--;
+    }
+    /* Put the exponent on. */
+    out[0] &= 0xFFFFF;
+    out[0] |= ((e > 0 ? e : 0) << 20);
+    /* Generate a power. Powers don't go below 2^-30. */
+    if (random_upto(1)) {
+        /* Positive power */
+        out[2] = dmax - random_upto_biased(dmax-pmin, 10);
+    } else {
+        /* Negative power */
+        out[2] = (dmin - random_upto_biased(dmin-pmin, 10)) | 0x80000000;
+    }
+    out[3] = random_upto(0xFFFFFFFF);
+}
+static void pow_cases_float(uint32 *out, uint32 param1,
+                            uint32 param2) {
+    /*
+     * Pick an exponent e (-0x16 to +0xFE) for x, and here's the
+     * range of numbers we can use as y:
+     *
+     * For e < 0x7E, the range is [-0x80/(0x7E-e),+0x95/(0x7E-e)]
+     * For e > 0x7F, the range is [-0x95/(e-0x7F),+0x80/(e-0x7F)]
+     *
+     * For e == 0x7E or e == 0x7F, the range gets infinite at one
+     * end or the other, so we have to be cleverer: pick a number n
+     * of useful bits in the mantissa (1 thru 23, so 1 must imply
+     * 0x3f800001 whereas 23 is anything at least as big as
+     * 0x3fc00000; for e == 0x7e, 1 necessarily means 0x3f7fffff
+     * and 23 is anything at most as big as 0x3f400000). Then, as
+     * it happens, a sensible maximum power is 2^(31-n) for e ==
+     * 0x7e, and 2^(30-n) for e == 0x7f.
+     *
+     * We inevitably get some overflows in approximating the log
+     * curves by these nasty step functions, but that's all right -
+     * we do want _some_ overflows to be tested.
+     *
+     * Having got that, then, it's just a matter of inventing a
+     * probability distribution for all of this.
+     */
+    int e, n;
+    uint32 dmin, dmax;
+    const uint32 pmin = 0x38000000;
+
+    /*
+     * Generate exponents in a slightly biased fashion.
+     */
+    e = (random_upto(1) ?              /* is exponent small or big? */
+         0x7E - random_upto_biased(0x94,2) :   /* small */
+         0x7F + random_upto_biased(0x7f,2));   /* big */
+
+    /*
+     * Now split into cases.
+     */
+    if (e < 0x7E || e > 0x7F) {
+        uint32 imin, imax;
+        if (e < 0x7E)
+            imin = 0x8000 / (0x7e - e), imax = 0x9500 / (0x7e - e);
+        else
+            imin = 0x9500 / (e - 0x7f), imax = 0x8000 / (e - 0x7f);
+        /* Power range runs from -imin to imax. Now convert to doubles */
+        dmin = floatval(imin, -8);
+        dmax = floatval(imax, -8);
+        /* Compute the number of mantissa bits. */
+        n = (e > 0 ? 24 : 23+e);
+    } else {
+        /* Critical exponents. Generate a top bit index. */
+        n = 23 - random_upto_biased(22, 4);
+        if (e == 0x7E)
+            dmax = 31 - n;
+        else
+            dmax = 30 - n;
+        dmax = (dmax << 23) + 0x3F800000;
+        dmin = dmax;
+    }
+    /* Generate a mantissa. */
+    out[0] = random_upto((1 << (n-1)) - 1) + (1 << (n-1));
+    out[1] = 0;
+    /* Negate the mantissa if e == 0x7E. */
+    if (e == 0x7E) {
+        out[0] = -out[0];
+    }
+    /* Put the exponent on. */
+    out[0] &= 0x7FFFFF;
+    out[0] |= ((e > 0 ? e : 0) << 23);
+    /* Generate a power. Powers don't go below 2^-15. */
+    if (random_upto(1)) {
+        /* Positive power */
+        out[2] = dmax - random_upto_biased(dmax-pmin, 10);
+    } else {
+        /* Negative power */
+        out[2] = (dmin - random_upto_biased(dmin-pmin, 10)) | 0x80000000;
+    }
+    out[3] = 0;
+}
+
+void vet_for_decline(Testable *fn, uint32 *args, uint32 *result, int got_errno_in) {
+    int declined = 0;
+
+    switch (fn->type) {
+      case args1:
+      case rred:
+      case semi1:
+      case t_frexp:
+      case t_modf:
+      case classify:
+      case t_ldexp:
+        declined |= lib_fo && is_dhard(args+0);
+        break;
+      case args1f:
+      case rredf:
+      case semi1f:
+      case t_frexpf:
+      case t_modff:
+      case classifyf:
+        declined |= lib_fo && is_shard(args+0);
+        break;
+      case args2:
+      case semi2:
+      case args1c:
+      case args1cr:
+      case compare:
+        declined |= lib_fo && is_dhard(args+0);
+        declined |= lib_fo && is_dhard(args+2);
+        break;
+      case args2f:
+      case semi2f:
+      case t_ldexpf:
+      case comparef:
+      case args1fc:
+      case args1fcr:
+        declined |= lib_fo && is_shard(args+0);
+        declined |= lib_fo && is_shard(args+2);
+        break;
+      case args2c:
+        declined |= lib_fo && is_dhard(args+0);
+        declined |= lib_fo && is_dhard(args+2);
+        declined |= lib_fo && is_dhard(args+4);
+        declined |= lib_fo && is_dhard(args+6);
+        break;
+      case args2fc:
+        declined |= lib_fo && is_shard(args+0);
+        declined |= lib_fo && is_shard(args+2);
+        declined |= lib_fo && is_shard(args+4);
+        declined |= lib_fo && is_shard(args+6);
+        break;
+    }
+
+    switch (fn->type) {
+      case args1:              /* return an extra-precise result */
+      case args2:
+      case rred:
+      case semi1:              /* return a double result */
+      case semi2:
+      case t_ldexp:
+      case t_frexp:            /* return double * int */
+      case args1cr:
+        declined |= lib_fo && is_dhard(result);
+        break;
+      case args1f:
+      case args2f:
+      case rredf:
+      case semi1f:
+      case semi2f:
+      case t_ldexpf:
+      case args1fcr:
+        declined |= lib_fo && is_shard(result);
+        break;
+      case t_modf:             /* return double * double */
+        declined |= lib_fo && is_dhard(result+0);
+        declined |= lib_fo && is_dhard(result+2);
+        break;
+      case t_modff:                    /* return float * float */
+        declined |= lib_fo && is_shard(result+2);
+        /* fall through */
+      case t_frexpf:                   /* return float * int */
+        declined |= lib_fo && is_shard(result+0);
+        break;
+      case args1c:
+      case args2c:
+        declined |= lib_fo && is_dhard(result+0);
+        declined |= lib_fo && is_dhard(result+4);
+        break;
+      case args1fc:
+      case args2fc:
+        declined |= lib_fo && is_shard(result+0);
+        declined |= lib_fo && is_shard(result+4);
+        break;
+    }
+
+    /* Expect basic arithmetic tests to be declined if the command
+     * line said that would happen */
+    declined |= (lib_no_arith && (fn->func == (funcptr)mpc_add ||
+                                  fn->func == (funcptr)mpc_sub ||
+                                  fn->func == (funcptr)mpc_mul ||
+                                  fn->func == (funcptr)mpc_div));
+
+    if (!declined) {
+        if (got_errno_in)
+            ntests++;
+        else
+            ntests += 3;
+    }
+}
+
+void docase(Testable *fn, uint32 *args) {
+    uint32 result[8];  /* real part in first 4, imaginary part in last 4 */
+    char *errstr = NULL;
+    mpfr_t a, b, r;
+    mpc_t ac, bc, rc;
+    int rejected, printextra;
+    wrapperctx ctx;
+
+    mpfr_init2(a, MPFR_PREC);
+    mpfr_init2(b, MPFR_PREC);
+    mpfr_init2(r, MPFR_PREC);
+    mpc_init2(ac, MPFR_PREC);
+    mpc_init2(bc, MPFR_PREC);
+    mpc_init2(rc, MPFR_PREC);
+
+    printf("func=%s", fn->name);
+
+    rejected = 0; /* FIXME */
+
+    switch (fn->type) {
+      case args1:
+      case rred:
+      case semi1:
+      case t_frexp:
+      case t_modf:
+      case classify:
+        printf(" op1=%08x.%08x", args[0], args[1]);
+        break;
+      case args1f:
+      case rredf:
+      case semi1f:
+      case t_frexpf:
+      case t_modff:
+      case classifyf:
+        printf(" op1=%08x", args[0]);
+        break;
+      case args2:
+      case semi2:
+      case compare:
+        printf(" op1=%08x.%08x", args[0], args[1]);
+        printf(" op2=%08x.%08x", args[2], args[3]);
+        break;
+      case args2f:
+      case semi2f:
+      case t_ldexpf:
+      case comparef:
+        printf(" op1=%08x", args[0]);
+        printf(" op2=%08x", args[2]);
+        break;
+      case t_ldexp:
+        printf(" op1=%08x.%08x", args[0], args[1]);
+        printf(" op2=%08x", args[2]);
+        break;
+      case args1c:
+      case args1cr:
+        printf(" op1r=%08x.%08x", args[0], args[1]);
+        printf(" op1i=%08x.%08x", args[2], args[3]);
+        break;
+      case args2c:
+        printf(" op1r=%08x.%08x", args[0], args[1]);
+        printf(" op1i=%08x.%08x", args[2], args[3]);
+        printf(" op2r=%08x.%08x", args[4], args[5]);
+        printf(" op2i=%08x.%08x", args[6], args[7]);
+        break;
+      case args1fc:
+      case args1fcr:
+        printf(" op1r=%08x", args[0]);
+        printf(" op1i=%08x", args[2]);
+        break;
+      case args2fc:
+        printf(" op1r=%08x", args[0]);
+        printf(" op1i=%08x", args[2]);
+        printf(" op2r=%08x", args[4]);
+        printf(" op2i=%08x", args[6]);
+        break;
+      default:
+        fprintf(stderr, "internal inconsistency?!\n");
+        abort();
+    }
+
+    if (rejected == 2) {
+        printf(" - test case rejected\n");
+        goto cleanup;
+    }
+
+    wrapper_init(&ctx);
+
+    if (rejected == 0) {
+        switch (fn->type) {
+          case args1:
+            set_mpfr_d(a, args[0], args[1]);
+            wrapper_op_real(&ctx, a, 2, args);
+            ((testfunc1)(fn->func))(r, a, GMP_RNDN);
+            get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            wrapper_result_real(&ctx, r, 2, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            break;
+          case args1cr:
+            set_mpc_d(ac, args[0], args[1], args[2], args[3]);
+            wrapper_op_complex(&ctx, ac, 2, args);
+            ((testfunc1cr)(fn->func))(r, ac, GMP_RNDN);
+            get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            wrapper_result_real(&ctx, r, 2, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            break;
+          case args1f:
+            set_mpfr_f(a, args[0]);
+            wrapper_op_real(&ctx, a, 1, args);
+            ((testfunc1)(fn->func))(r, a, GMP_RNDN);
+            get_mpfr_f(r, &result[0], &result[1]);
+            wrapper_result_real(&ctx, r, 1, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_f(r, &result[0], &result[1]);
+            break;
+          case args1fcr:
+            set_mpc_f(ac, args[0], args[2]);
+            wrapper_op_complex(&ctx, ac, 1, args);
+            ((testfunc1cr)(fn->func))(r, ac, GMP_RNDN);
+            get_mpfr_f(r, &result[0], &result[1]);
+            wrapper_result_real(&ctx, r, 1, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_f(r, &result[0], &result[1]);
+            break;
+          case args2:
+            set_mpfr_d(a, args[0], args[1]);
+            wrapper_op_real(&ctx, a, 2, args);
+            set_mpfr_d(b, args[2], args[3]);
+            wrapper_op_real(&ctx, b, 2, args+2);
+            ((testfunc2)(fn->func))(r, a, b, GMP_RNDN);
+            get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            wrapper_result_real(&ctx, r, 2, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            break;
+          case args2f:
+            set_mpfr_f(a, args[0]);
+            wrapper_op_real(&ctx, a, 1, args);
+            set_mpfr_f(b, args[2]);
+            wrapper_op_real(&ctx, b, 1, args+2);
+            ((testfunc2)(fn->func))(r, a, b, GMP_RNDN);
+            get_mpfr_f(r, &result[0], &result[1]);
+            wrapper_result_real(&ctx, r, 1, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_f(r, &result[0], &result[1]);
+            break;
+          case rred:
+            set_mpfr_d(a, args[0], args[1]);
+            wrapper_op_real(&ctx, a, 2, args);
+            ((testrred)(fn->func))(r, a, (int *)&result[3]);
+            get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            wrapper_result_real(&ctx, r, 2, result);
+            /* We never need to mess about with the integer auxiliary
+             * output. */
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_d(r, &result[0], &result[1], &result[2]);
+            break;
+          case rredf:
+            set_mpfr_f(a, args[0]);
+            wrapper_op_real(&ctx, a, 1, args);
+            ((testrred)(fn->func))(r, a, (int *)&result[3]);
+            get_mpfr_f(r, &result[0], &result[1]);
+            wrapper_result_real(&ctx, r, 1, result);
+            /* We never need to mess about with the integer auxiliary
+             * output. */
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpfr_f(r, &result[0], &result[1]);
+            break;
+          case semi1:
+          case semi1f:
+            errstr = ((testsemi1)(fn->func))(args, result);
+            break;
+          case semi2:
+          case compare:
+            errstr = ((testsemi2)(fn->func))(args, args+2, result);
+            break;
+          case semi2f:
+          case comparef:
+          case t_ldexpf:
+            errstr = ((testsemi2f)(fn->func))(args, args+2, result);
+            break;
+          case t_ldexp:
+            errstr = ((testldexp)(fn->func))(args, args+2, result);
+            break;
+          case t_frexp:
+            errstr = ((testfrexp)(fn->func))(args, result, result+2);
+            break;
+          case t_frexpf:
+            errstr = ((testfrexp)(fn->func))(args, result, result+2);
+            break;
+          case t_modf:
+            errstr = ((testmodf)(fn->func))(args, result, result+2);
+            break;
+          case t_modff:
+            errstr = ((testmodf)(fn->func))(args, result, result+2);
+            break;
+          case classify:
+            errstr = ((testclassify)(fn->func))(args, &result[0]);
+            break;
+          case classifyf:
+            errstr = ((testclassifyf)(fn->func))(args, &result[0]);
+            break;
+          case args1c:
+            set_mpc_d(ac, args[0], args[1], args[2], args[3]);
+            wrapper_op_complex(&ctx, ac, 2, args);
+            ((testfunc1c)(fn->func))(rc, ac, MPC_RNDNN);
+            get_mpc_d(rc, &result[0], &result[1], &result[2], &result[4], &result[5], &result[6]);
+            wrapper_result_complex(&ctx, rc, 2, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpc_d(rc, &result[0], &result[1], &result[2], &result[4], &result[5], &result[6]);
+            break;
+          case args2c:
+            set_mpc_d(ac, args[0], args[1], args[2], args[3]);
+            wrapper_op_complex(&ctx, ac, 2, args);
+            set_mpc_d(bc, args[4], args[5], args[6], args[7]);
+            wrapper_op_complex(&ctx, bc, 2, args+4);
+            ((testfunc2c)(fn->func))(rc, ac, bc, MPC_RNDNN);
+            get_mpc_d(rc, &result[0], &result[1], &result[2], &result[4], &result[5], &result[6]);
+            wrapper_result_complex(&ctx, rc, 2, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpc_d(rc, &result[0], &result[1], &result[2], &result[4], &result[5], &result[6]);
+            break;
+          case args1fc:
+            set_mpc_f(ac, args[0], args[2]);
+            wrapper_op_complex(&ctx, ac, 1, args);
+            ((testfunc1c)(fn->func))(rc, ac, MPC_RNDNN);
+            get_mpc_f(rc, &result[0], &result[1], &result[4], &result[5]);
+            wrapper_result_complex(&ctx, rc, 1, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpc_f(rc, &result[0], &result[1], &result[4], &result[5]);
+            break;
+          case args2fc:
+            set_mpc_f(ac, args[0], args[2]);
+            wrapper_op_complex(&ctx, ac, 1, args);
+            set_mpc_f(bc, args[4], args[6]);
+            wrapper_op_complex(&ctx, bc, 1, args+4);
+            ((testfunc2c)(fn->func))(rc, ac, bc, MPC_RNDNN);
+            get_mpc_f(rc, &result[0], &result[1], &result[4], &result[5]);
+            wrapper_result_complex(&ctx, rc, 1, result);
+            if (wrapper_run(&ctx, fn->wrappers))
+                get_mpc_f(rc, &result[0], &result[1], &result[4], &result[5]);
+            break;
+          default:
+            fprintf(stderr, "internal inconsistency?!\n");
+            abort();
+        }
+    }
+
+    switch (fn->type) {
+      case args1:              /* return an extra-precise result */
+      case args2:
+      case args1cr:
+      case rred:
+        printextra = 1;
+        if (rejected == 0) {
+            errstr = NULL;
+            if (!mpfr_zero_p(a)) {
+                if ((result[0] & 0x7FFFFFFF) == 0 && result[1] == 0) {
+                    /*
+                     * If the output is +0 or -0 apart from the extra
+                     * precision in result[2], then there's a tricky
+                     * judgment call about what we require in the
+                     * output. If we output the extra bits and set
+                     * errstr="?underflow" then mathtest will tolerate
+                     * the function under test rounding down to zero
+                     * _or_ up to the minimum denormal; whereas if we
+                     * suppress the extra bits and set
+                     * errstr="underflow", then mathtest will enforce
+                     * that the function really does underflow to zero.
+                     *
+                     * But where to draw the line? It seems clear to
+                     * me that numbers along the lines of
+                     * 00000000.00000000.7ff should be treated
+                     * similarly to 00000000.00000000.801, but on the
+                     * other hand, we must surely be prepared to
+                     * enforce a genuine underflow-to-zero in _some_
+                     * case where the true mathematical output is
+                     * nonzero but absurdly tiny.
+                     *
+                     * I think a reasonable place to draw the
+                     * distinction is at 00000000.00000000.400, i.e.
+                     * one quarter of the minimum positive denormal.
+                     * If a value less than that rounds up to the
+                     * minimum denormal, that must mean the function
+                     * under test has managed to make an error of an
+                     * entire factor of two, and that's something we
+                     * should fix. Above that, you can misround within
+                     * the limits of your accuracy bound if you have
+                     * to.
+                     */
+                    if (result[2] < 0x40000000) {
+                        /* Total underflow (ERANGE + UFL) is required,
+                         * and we suppress the extra bits to make
+                         * mathtest enforce that the output is really
+                         * zero. */
+                        errstr = "underflow";
+                        printextra = 0;
+                    } else {
+                        /* Total underflow is not required, but if the
+                         * function rounds down to zero anyway, then
+                         * we should be prepared to tolerate it. */
+                        errstr = "?underflow";
+                    }
+                } else if (!(result[0] & 0x7ff00000)) {
+                    /*
+                     * If the output is denormal, we usually expect a
+                     * UFL exception, warning the user of partial
+                     * underflow. The exception is if the denormal
+                     * being returned is just one of the input values,
+                     * unchanged even in principle. I bodgily handle
+                     * this by just special-casing the functions in
+                     * question below.
+                     */
+                    if (!strcmp(fn->name, "fmax") ||
+                        !strcmp(fn->name, "fmin") ||
+                        !strcmp(fn->name, "creal") ||
+                        !strcmp(fn->name, "cimag")) {
+                        /* no error expected */
+                    } else {
+                        errstr = "u";
+                    }
+                } else if ((result[0] & 0x7FFFFFFF) > 0x7FEFFFFF) {
+                    /*
+                     * Infinite results are usually due to overflow,
+                     * but one exception is lgamma of a negative
+                     * integer.
+                     */
+                    if (!strcmp(fn->name, "lgamma") &&
+                        (args[0] & 0x80000000) != 0 && /* negative */
+                        is_dinteger(args)) {
+                        errstr = "ERANGE status=z";
+                    } else {
+                        errstr = "overflow";
+                    }
+                    printextra = 0;
+                }
+            } else {
+                /* lgamma(0) is also a pole. */
+                if (!strcmp(fn->name, "lgamma")) {
+                    errstr = "ERANGE status=z";
+                    printextra = 0;
+                }
+            }
+        }
+
+        if (!printextra || (rejected && !(rejected==1 && result[2]!=0))) {
+            printf(" result=%08x.%08x",
+                   result[0], result[1]);
+        } else {
+            printf(" result=%08x.%08x.%03x",
+                   result[0], result[1], (result[2] >> 20) & 0xFFF);
+        }
+        if (fn->type == rred) {
+            printf(" res2=%08x", result[3]);
+        }
+        break;
+      case args1f:
+      case args2f:
+      case args1fcr:
+      case rredf:
+        printextra = 1;
+        if (rejected == 0) {
+            errstr = NULL;
+            if (!mpfr_zero_p(a)) {
+                if ((result[0] & 0x7FFFFFFF) == 0) {
+                    /*
+                     * Decide whether to print the extra bits based on
+                     * just how close to zero the number is. See the
+                     * big comment in the double-precision case for
+                     * discussion.
+                     */
+                    if (result[1] < 0x40000000) {
+                        errstr = "underflow";
+                        printextra = 0;
+                    } else {
+                        errstr = "?underflow";
+                    }
+                } else if (!(result[0] & 0x7f800000)) {
+                    /*
+                     * Functions which do not report partial overflow
+                     * are listed here as special cases. (See the
+                     * corresponding double case above for a fuller
+                     * comment.)
+                     */
+                    if (!strcmp(fn->name, "fmaxf") ||
+                        !strcmp(fn->name, "fminf") ||
+                        !strcmp(fn->name, "crealf") ||
+                        !strcmp(fn->name, "cimagf")) {
+                        /* no error expected */
+                    } else {
+                        errstr = "u";
+                    }
+                } else if ((result[0] & 0x7FFFFFFF) > 0x7F7FFFFF) {
+                    /*
+                     * Infinite results are usually due to overflow,
+                     * but one exception is lgamma of a negative
+                     * integer.
+                     */
+                    if (!strcmp(fn->name, "lgammaf") &&
+                        (args[0] & 0x80000000) != 0 && /* negative */
+                        is_sinteger(args)) {
+                        errstr = "ERANGE status=z";
+                    } else {
+                        errstr = "overflow";
+                    }
+                    printextra = 0;
+                }
+            } else {
+                /* lgamma(0) is also a pole. */
+                if (!strcmp(fn->name, "lgammaf")) {
+                    errstr = "ERANGE status=z";
+                    printextra = 0;
+                }
+            }
+        }
+
+        if (!printextra || (rejected && !(rejected==1 && result[1]!=0))) {
+            printf(" result=%08x",
+                   result[0]);
+        } else {
+            printf(" result=%08x.%03x",
+                   result[0], (result[1] >> 20) & 0xFFF);
+        }
+        if (fn->type == rredf) {
+            printf(" res2=%08x", result[3]);
+        }
+        break;
+      case semi1:              /* return a double result */
+      case semi2:
+      case t_ldexp:
+        printf(" result=%08x.%08x", result[0], result[1]);
+        break;
+      case semi1f:
+      case semi2f:
+      case t_ldexpf:
+        printf(" result=%08x", result[0]);
+        break;
+      case t_frexp:            /* return double * int */
+        printf(" result=%08x.%08x res2=%08x", result[0], result[1],
+               result[2]);
+        break;
+      case t_modf:             /* return double * double */
+        printf(" result=%08x.%08x res2=%08x.%08x",
+               result[0], result[1], result[2], result[3]);
+        break;
+      case t_modff:                    /* return float * float */
+        /* fall through */
+      case t_frexpf:                   /* return float * int */
+        printf(" result=%08x res2=%08x", result[0], result[2]);
+        break;
+      case classify:
+      case classifyf:
+      case compare:
+      case comparef:
+        printf(" result=%x", result[0]);
+        break;
+      case args1c:
+      case args2c:
+        if (0/* errstr */) {
+            printf(" resultr=%08x.%08x", result[0], result[1]);
+            printf(" resulti=%08x.%08x", result[4], result[5]);
+        } else {
+            printf(" resultr=%08x.%08x.%03x",
+                   result[0], result[1], (result[2] >> 20) & 0xFFF);
+            printf(" resulti=%08x.%08x.%03x",
+                   result[4], result[5], (result[6] >> 20) & 0xFFF);
+        }
+        /* Underflow behaviour doesn't seem to be specified for complex arithmetic */
+        errstr = "?underflow";
+        break;
+      case args1fc:
+      case args2fc:
+        if (0/* errstr */) {
+            printf(" resultr=%08x", result[0]);
+            printf(" resulti=%08x", result[4]);
+        } else {
+            printf(" resultr=%08x.%03x",
+                   result[0], (result[1] >> 20) & 0xFFF);
+            printf(" resulti=%08x.%03x",
+                   result[4], (result[5] >> 20) & 0xFFF);
+        }
+        /* Underflow behaviour doesn't seem to be specified for complex arithmetic */
+        errstr = "?underflow";
+        break;
+    }
+
+    if (errstr && *(errstr+1) == '\0') {
+        printf(" errno=0 status=%c",*errstr);
+    } else if (errstr && *errstr == '?') {
+        printf(" maybeerror=%s", errstr+1);
+    } else if (errstr && errstr[0] == 'E') {
+        printf(" errno=%s", errstr);
+    } else {
+        printf(" error=%s", errstr && *errstr ? errstr : "0");
+    }
+
+    printf("\n");
+
+    vet_for_decline(fn, args, result, 0);
+
+  cleanup:
+    mpfr_clear(a);
+    mpfr_clear(b);
+    mpfr_clear(r);
+    mpc_clear(ac);
+    mpc_clear(bc);
+    mpc_clear(rc);
+}
+
+void gencases(Testable *fn, int number) {
+    int i;
+    uint32 args[8];
+
+    float32_case(NULL);
+    float64_case(NULL);
+
+    printf("random=on\n"); /* signal to runtests.pl that the following tests are randomly generated */
+    for (i = 0; i < number; i++) {
+        /* generate test point */
+        fn->cases(args, fn->caseparam1, fn->caseparam2);
+        docase(fn, args);
+    }
+    printf("random=off\n");
+}
+
+static uint32 doubletop(int x, int scale) {
+    int e = 0x412 + scale;
+    while (!(x & 0x100000))
+        x <<= 1, e--;
+    return (e << 20) + x;
+}
+
+static uint32 floatval(int x, int scale) {
+    int e = 0x95 + scale;
+    while (!(x & 0x800000))
+        x <<= 1, e--;
+    return (e << 23) + x;
+}
diff --git a/libc/AOR_v20.02/math/test/rtest/intern.h b/libc/AOR_v20.02/math/test/rtest/intern.h
new file mode 100644
index 0000000000000..8b1cc4f3176cb
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/intern.h
@@ -0,0 +1,92 @@
+/*
+ * intern.h
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef mathtest_intern_h
+#define mathtest_intern_h
+
+#include <mpfr.h>
+#include <mpc.h>
+
+#include "types.h"
+#include "wrappers.h"
+
+/* Generic function pointer. */
+typedef void (*funcptr)(void);
+
+/* Pointers to test function types. */
+typedef int    (*testfunc1)(mpfr_t, mpfr_t, mpfr_rnd_t);
+typedef int    (*testfunc2)(mpfr_t, mpfr_t, mpfr_t, mpfr_rnd_t);
+typedef int    (*testrred)(mpfr_t, mpfr_t, int *);
+typedef char * (*testsemi1)(uint32 *, uint32 *);
+typedef char * (*testsemi2)(uint32 *, uint32 *, uint32 *);
+typedef char * (*testsemi2f)(uint32 *, uint32 *, uint32 *);
+typedef char * (*testldexp)(uint32 *, uint32 *, uint32 *);
+typedef char * (*testfrexp)(uint32 *, uint32 *, uint32 *);
+typedef char * (*testmodf)(uint32 *, uint32 *, uint32 *);
+typedef char * (*testclassify)(uint32 *, uint32 *);
+typedef char * (*testclassifyf)(uint32 *, uint32 *);
+
+typedef int    (*testfunc1c)(mpc_t, mpc_t, mpc_rnd_t);
+typedef int    (*testfunc2c)(mpc_t, mpc_t, mpc_t, mpc_rnd_t);
+
+typedef int    (*testfunc1cr)(mpfr_t, mpc_t, mpfr_rnd_t);
+
+/* Pointer to a function that generates random test cases. */
+typedef void (*casegen)(uint32 *, uint32, uint32);
+
+/*
+ * List of testable functions, their types, and their testable range.
+ */
+enum {
+    args1,                             /* afloat-based, one argument */
+    args1f,                            /* same as args1 but in single prec */
+    args2,                             /* afloat-based, two arguments */
+    args2f,                            /* same as args2 but in single prec */
+    rred,                              /* afloat-based, one arg, aux return */
+    rredf,                             /* same as rred but in single prec */
+    semi1,                             /* seminumerical, one argument */
+    semi1f,                            /* seminumerical, 1 arg, float */
+    semi2,                             /* seminumerical, two arguments */
+    semi2f,                            /* seminumerical, 2 args, floats */
+    t_ldexp,                           /* dbl * int -> dbl */
+    t_ldexpf,                          /* sgl * int -> sgl */
+    t_frexp,                           /* dbl -> dbl * int */
+    t_frexpf,                          /* sgl -> sgl * int */
+    t_modf,                            /* dbl -> dbl * dbl */
+    t_modff,                           /* sgl -> sgl * sgl */
+    classify,                          /* classify double: dbl -> int */
+    classifyf,                         /* classify float: flt -> int */
+    compare,                           /* compare doubles, returns int */
+    comparef,                          /* compare floats, returns int */
+
+    args1c,                            /* acomplex-base, one argument */
+    args2c,
+    args1fc,
+    args2fc,
+    args1cr,                           /* dbl-complex -> complex */
+    args1fcr                           /* sgl-complex -> complex */
+};
+
+typedef struct __testable Testable;
+struct __testable {
+    char *name;
+    funcptr func;
+    int type;
+    wrapperfunc wrappers[MAXWRAPPERS];
+    casegen cases; /* complex functions use the same casegen for both real and complex args */
+    uint32 caseparam1, caseparam2;
+};
+
+extern Testable functions[];
+extern const int nfunctions;
+
+extern void init_pi(void);
+
+int nargs_(Testable* f);
+
+#endif
diff --git a/libc/AOR_v20.02/math/test/rtest/main.c b/libc/AOR_v20.02/math/test/rtest/main.c
new file mode 100644
index 0000000000000..c4ddd0f86fcbc
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/main.c
@@ -0,0 +1,335 @@
+/*
+ * main.c
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+#include <stdlib.h>
+#include <time.h>
+
+#include "intern.h"
+
+void gencases(Testable *fn, int number);
+void docase(Testable *fn, uint32 *args);
+void vet_for_decline(Testable *fn, uint32 *args, uint32 *result, int got_errno_in);
+void seed_random(uint32 seed);
+
+int check_declines = 0;
+int lib_fo = 0;
+int lib_no_arith = 0;
+int ntests = 0;
+
+int nargs_(Testable* f) {
+    switch((f)->type) {
+    case args2:
+    case args2f:
+    case semi2:
+    case semi2f:
+    case t_ldexp:
+    case t_ldexpf:
+    case args1c:
+    case args1fc:
+    case args1cr:
+    case args1fcr:
+    case compare:
+    case comparef:
+        return 2;
+    case args2c:
+    case args2fc:
+        return 4;
+    default:
+        return 1;
+    }
+}
+
+static int isdouble(Testable *f)
+{
+    switch (f->type) {
+      case args1:
+      case rred:
+      case semi1:
+      case t_frexp:
+      case t_modf:
+      case classify:
+      case t_ldexp:
+      case args2:
+      case semi2:
+      case args1c:
+      case args1cr:
+      case compare:
+      case args2c:
+        return 1;
+      case args1f:
+      case rredf:
+      case semi1f:
+      case t_frexpf:
+      case t_modff:
+      case classifyf:
+      case args2f:
+      case semi2f:
+      case t_ldexpf:
+      case comparef:
+      case args1fc:
+      case args1fcr:
+      case args2fc:
+        return 0;
+      default:
+        assert(0 && "Bad function type");
+    }
+}
+
+Testable *find_function(const char *func)
+{
+    int i;
+    for (i = 0; i < nfunctions; i++) {
+        if (func && !strcmp(func, functions[i].name)) {
+            return &functions[i];
+        }
+    }
+    return NULL;
+}
+
+void get_operand(const char *str, Testable *f, uint32 *word0, uint32 *word1)
+{
+    struct special {
+        unsigned dblword0, dblword1, sglword;
+        const char *name;
+    } specials[] = {
+        {0x00000000,0x00000000,0x00000000,"0"},
+        {0x3FF00000,0x00000000,0x3f800000,"1"},
+        {0x7FF00000,0x00000000,0x7f800000,"inf"},
+        {0x7FF80000,0x00000001,0x7fc00000,"qnan"},
+        {0x7FF00000,0x00000001,0x7f800001,"snan"},
+        {0x3ff921fb,0x54442d18,0x3fc90fdb,"pi2"},
+        {0x400921fb,0x54442d18,0x40490fdb,"pi"},
+        {0x3fe921fb,0x54442d18,0x3f490fdb,"pi4"},
+        {0x4002d97c,0x7f3321d2,0x4016cbe4,"3pi4"},
+    };
+    int i;
+
+    for (i = 0; i < (int)(sizeof(specials)/sizeof(*specials)); i++) {
+        if (!strcmp(str, specials[i].name) ||
+            ((str[0] == '-' || str[0] == '+') &&
+             !strcmp(str+1, specials[i].name))) {
+            assert(f);
+            if (isdouble(f)) {
+                *word0 = specials[i].dblword0;
+                *word1 = specials[i].dblword1;
+            } else {
+                *word0 = specials[i].sglword;
+                *word1 = 0;
+            }
+            if (str[0] == '-')
+                *word0 |= 0x80000000U;
+            return;
+        }
+    }
+
+    sscanf(str, "%"I32"x.%"I32"x", word0, word1);
+}
+
+void dofile(FILE *fp, int translating) {
+    char buf[1024], sparebuf[1024], *p;
+
+    /*
+     * Command syntax is:
+     *
+     *  - "seed <integer>" sets a random seed
+     *
+     *  - "test <function> <ntests>" generates random test lines
+     *
+     *  - "<function> op1=foo [op2=bar]" generates a specific test
+     *  - "func=<function> op1=foo [op2=bar]" does the same
+     *  - "func=<function> op1=foo result=bar" will just output the line as-is
+     *
+     *  - a semicolon or a blank line is ignored
+     */
+    while (fgets(buf, sizeof(buf), fp)) {
+        buf[strcspn(buf, "\r\n")] = '\0';
+        strcpy(sparebuf, buf);
+        p = buf;
+        while (*p && isspace(*p)) p++;
+        if (!*p || *p == ';') {
+            /* Comment or blank line. Only print if `translating' is set. */
+            if (translating)
+                printf("%s\n", buf);
+            continue;
+        }
+        if (!strncmp(buf, "seed ", 5)) {
+            seed_random(atoi(buf+5));
+        } else if (!strncmp(buf, "random=", 7)) {
+            /*
+             * Copy 'random=on' / 'random=off' lines unconditionally
+             * to the output, so that random test failures can be
+             * accumulated into a recent-failures-list file and
+             * still identified as random-in-origin when re-run the
+             * next day.
+             */
+            printf("%s\n", buf);
+        } else if (!strncmp(buf, "test ", 5)) {
+            char *p = buf+5;
+            char *q;
+            int ntests, i;
+            q = p;
+            while (*p && !isspace(*p)) p++;
+            if (*p) *p++ = '\0';
+            while (*p && isspace(*p)) p++;
+            if (*p)
+                ntests = atoi(p);
+            else
+                ntests = 100;          /* *shrug* */
+            for (i = 0; i < nfunctions; i++) {
+                if (!strcmp(q, functions[i].name)) {
+                    gencases(&functions[i], ntests);
+                    break;
+                }
+            }
+            if (i == nfunctions) {
+                fprintf(stderr, "unknown test `%s'\n", q);
+            }
+        } else {
+            /*
+             * Parse a specific test line.
+             */
+            uint32 ops[8], result[8];
+            int got_op = 0; /* &1 for got_op1, &4 for got_op3 etc. */
+            Testable *f = 0;
+            char *q, *r;
+            int got_result = 0, got_errno_in = 0;
+
+            for (q = strtok(p, " \t"); q; q = strtok(NULL, " \t")) {
+                r = strchr(q, '=');
+                if (!r) {
+                    f = find_function(q);
+                } else {
+                    *r++ = '\0';
+
+                    if (!strcmp(q, "func"))
+                        f = find_function(r);
+                    else if (!strcmp(q, "op1") || !strcmp(q, "op1r")) {
+                        get_operand(r, f, &ops[0], &ops[1]);
+                        got_op |= 1;
+                    } else if (!strcmp(q, "op2") || !strcmp(q, "op1i")) {
+                        get_operand(r, f, &ops[2], &ops[3]);
+                        got_op |= 2;
+                    } else if (!strcmp(q, "op2r")) {
+                        get_operand(r, f, &ops[4], &ops[5]);
+                        got_op |= 4;
+                    } else if (!strcmp(q, "op2i")) {
+                        get_operand(r, f, &ops[6], &ops[7]);
+                        got_op |= 8;
+                    } else if (!strcmp(q, "result") || !strcmp(q, "resultr")) {
+                        get_operand(r, f, &result[0], &result[1]);
+                        got_result |= 1;
+                    } else if (!strcmp(q, "resulti")) {
+                        get_operand(r, f, &result[4], &result[5]);
+                        got_result |= 2;
+                    } else if (!strcmp(q, "res2")) {
+                        get_operand(r, f, &result[2], &result[3]);
+                        got_result |= 4;
+                    } else if (!strcmp(q, "errno_in")) {
+                        got_errno_in = 1;
+                    }
+                }
+            }
+
+            /*
+             * Test cases already set up by the input are not
+             * reprocessed by default, unlike the fplib tests. (This
+             * is mostly for historical reasons, because we used to
+             * use a very slow and incomplete internal reference
+             * implementation; now our ref impl is MPFR/MPC it
+             * probably wouldn't be such a bad idea, though we'd still
+             * have to make sure all the special cases came out
+             * right.) If translating==2 (corresponding to the -T
+             * command-line option) then we regenerate everything
+             * regardless.
+             */
+            if (got_result && translating < 2) {
+                if (f)
+                    vet_for_decline(f, ops, result, got_errno_in);
+                puts(sparebuf);
+                continue;
+            }
+
+            if (f && got_op==(1<<nargs_(f))-1) {
+                /*
+                 * And do it!
+                 */
+                docase(f, ops);
+            }
+        }
+    }
+}
+
+int main(int argc, char **argv) {
+    int errs = 0, opts = 1, files = 0, translating = 0;
+    unsigned int seed = 1; /* in case no explicit seed provided */
+
+    seed_random(seed);
+
+    setvbuf(stdout, NULL, _IOLBF, BUFSIZ); /* stops incomplete lines being printed when out of time */
+
+    while (--argc) {
+        FILE *fp;
+        char *p = *++argv;
+
+        if (opts && *p == '-') {
+            if(*(p+1) == 0) { /* single -, read from stdin */
+                break;
+            } else if (!strcmp(p, "-t")) {
+                translating = 1;
+            } else if (!strcmp(p, "-T")) {
+                translating = 2;
+            } else if (!strcmp(p, "-c")) {
+                check_declines = 1;
+            } else if (!strcmp(p, "--")) {
+                opts = 0;
+            } else if (!strcmp(p,"--seed") && argc > 1 && 1==sscanf(*(argv+1),"%u",&seed)) {
+                seed_random(seed);
+                argv++; /* next in argv is seed value, so skip */
+                --argc;
+            } else if (!strcmp(p, "-fo")) {
+                lib_fo = 1;
+            } else if (!strcmp(p, "-noarith")) {
+                lib_no_arith = 1;
+            } else {
+                fprintf(stderr,
+                        "rtest: ignoring unrecognised option '%s'\n", p);
+                errs = 1;
+            }
+        } else {
+            files = 1;
+            if (!errs) {
+                fp = fopen(p, "r");
+                if (fp) {
+                    dofile(fp, translating);
+                    fclose(fp);
+                } else {
+                    perror(p);
+                    errs = 1;
+                }
+            }
+        }
+    }
+
+    /*
+     * If no filename arguments, use stdin.
+     */
+    if (!files && !errs) {
+        dofile(stdin, translating);
+    }
+
+    if (check_declines) {
+        fprintf(stderr, "Tests expected to run: %d\n", ntests);
+        fflush(stderr);
+    }
+
+    return errs;
+}
diff --git a/libc/AOR_v20.02/math/test/rtest/random.c b/libc/AOR_v20.02/math/test/rtest/random.c
new file mode 100644
index 0000000000000..b6ad6a79a7223
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/random.c
@@ -0,0 +1,100 @@
+/*
+ * random.c - random number generator for producing mathlib test cases
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "types.h"
+#include "random.h"
+
+static uint32 seedbuf[55];
+static int seedptr;
+
+void seed_random(uint32 seed) {
+    int i;
+
+    seedptr = 0;
+    for (i = 0; i < 55; i++) {
+        seed = seed % 44488 * 48271 - seed / 44488 * 3399;
+        seedbuf[i] = seed - 1;
+    }
+}
+
+uint32 base_random(void) {
+    seedptr %= 55;
+    seedbuf[seedptr] += seedbuf[(seedptr+31)%55];
+    return seedbuf[seedptr++];
+}
+
+uint32 random32(void) {
+    uint32 a, b, b1, b2;
+    a = base_random();
+    b = base_random();
+    for (b1 = 0x80000000, b2 = 1; b1 > b2; b1 >>= 1, b2 <<= 1) {
+        uint32 b3 = b1 | b2;
+        if ((b & b3) != 0 && (b & b3) != b3)
+            b ^= b3;
+    }
+    return a ^ b;
+}
+
+/*
+ * random_upto: generate a uniformly randomised number in the range
+ * 0,...,limit-1. (Precondition: limit > 0.)
+ *
+ * random_upto_biased: generate a number in the same range, but with
+ * the probability skewed towards the high end by means of taking the
+ * maximum of 8*bias+1 samples from the uniform distribution on the
+ * same range. (I don't know why bias is given in that curious way -
+ * historical reasons, I expect.)
+ *
+ * For speed, I separate the implementation of random_upto into the
+ * two stages of (a) generate a bitmask which reduces a 32-bit random
+ * number to within a factor of two of the right range, (b) repeatedly
+ * generate numbers in that range until one is small enough. Splitting
+ * it up like that means that random_upto_biased can do (a) only once
+ * even when it does (b) lots of times.
+ */
+
+static uint32 random_upto_makemask(uint32 limit) {
+    uint32 mask = 0xFFFFFFFF;
+    int i;
+    for (i = 16; i > 0; i >>= 1)
+        if ((limit & (mask >> i)) == limit)
+            mask >>= i;
+    return mask;
+}
+
+static uint32 random_upto_internal(uint32 limit, uint32 mask) {
+    uint32 ret;
+    do {
+        ret = random32() & mask;
+    } while (ret > limit);
+    return ret;
+}
+
+uint32 random_upto(uint32 limit) {
+    uint32 mask = random_upto_makemask(limit);
+    return random_upto_internal(limit, mask);
+}
+
+uint32 random_upto_biased(uint32 limit, int bias) {
+    uint32 mask = random_upto_makemask(limit);
+
+    uint32 ret = random_upto_internal(limit, mask);
+    while (bias--) {
+        uint32 tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+        tmp = random_upto_internal(limit, mask); if (tmp < ret) ret = tmp;
+    }
+
+    return ret;
+}
diff --git a/libc/AOR_v20.02/math/test/rtest/random.h b/libc/AOR_v20.02/math/test/rtest/random.h
new file mode 100644
index 0000000000000..5ab0c0f0dfcbd
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/random.h
@@ -0,0 +1,13 @@
+/*
+ * random.h - header for random.c
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "types.h"
+
+uint32 random32(void);
+uint32 random_upto(uint32 limit);
+uint32 random_upto_biased(uint32 limit, int bias);
diff --git a/libc/AOR_v20.02/math/test/rtest/semi.c b/libc/AOR_v20.02/math/test/rtest/semi.c
new file mode 100644
index 0000000000000..aefb2b81d4a58
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/semi.c
@@ -0,0 +1,906 @@
+/*
+ * semi.c: test implementations of mathlib seminumerical functions
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdio.h>
+#include "semi.h"
+
+static void test_rint(uint32 *in, uint32 *out,
+                       int isfloor, int isceil) {
+    int sign = in[0] & 0x80000000;
+    int roundup = (isfloor && sign) || (isceil && !sign);
+    uint32 xh, xl, roundword;
+    int ex = (in[0] >> 20) & 0x7FF;    /* exponent */
+    int i;
+
+    if ((ex > 0x3ff + 52 - 1) ||     /* things this big can't be fractional */
+        ((in[0] & 0x7FFFFFFF) == 0 && in[1] == 0)) {   /* zero */
+        /* NaN, Inf, a large integer, or zero: just return the input */
+        out[0] = in[0];
+        out[1] = in[1];
+        return;
+    }
+
+    /*
+     * Special case: ex < 0x3ff, ie our number is in (0,1). Return
+     * 1 or 0 according to roundup.
+     */
+    if (ex < 0x3ff) {
+        out[0] = sign | (roundup ? 0x3FF00000 : 0);
+        out[1] = 0;
+        return;
+    }
+
+    /*
+     * We're not short of time here, so we'll do this the hideously
+     * inefficient way. Shift bit by bit so that the units place is
+     * somewhere predictable, round, and shift back again.
+     */
+    xh = in[0];
+    xl = in[1];
+    roundword = 0;
+    for (i = ex; i < 0x3ff + 52; i++) {
+        if (roundword & 1)
+            roundword |= 2;            /* preserve sticky bit */
+        roundword = (roundword >> 1) | ((xl & 1) << 31);
+        xl = (xl >> 1) | ((xh & 1) << 31);
+        xh = xh >> 1;
+    }
+    if (roundword && roundup) {
+        xl++;
+        xh += (xl==0);
+    }
+    for (i = ex; i < 0x3ff + 52; i++) {
+        xh = (xh << 1) | ((xl >> 31) & 1);
+        xl = (xl & 0x7FFFFFFF) << 1;
+    }
+    out[0] = xh;
+    out[1] = xl;
+}
+
+char *test_ceil(uint32 *in, uint32 *out) {
+    test_rint(in, out, 0, 1);
+    return NULL;
+}
+
+char *test_floor(uint32 *in, uint32 *out) {
+    test_rint(in, out, 1, 0);
+    return NULL;
+}
+
+static void test_rintf(uint32 *in, uint32 *out,
+                       int isfloor, int isceil) {
+    int sign = *in & 0x80000000;
+    int roundup = (isfloor && sign) || (isceil && !sign);
+    uint32 x, roundword;
+    int ex = (*in >> 23) & 0xFF;       /* exponent */
+    int i;
+
+    if ((ex > 0x7f + 23 - 1) ||      /* things this big can't be fractional */
+        (*in & 0x7FFFFFFF) == 0) {     /* zero */
+        /* NaN, Inf, a large integer, or zero: just return the input */
+        *out = *in;
+        return;
+    }
+
+    /*
+     * Special case: ex < 0x7f, ie our number is in (0,1). Return
+     * 1 or 0 according to roundup.
+     */
+    if (ex < 0x7f) {
+        *out = sign | (roundup ? 0x3F800000 : 0);
+        return;
+    }
+
+    /*
+     * We're not short of time here, so we'll do this the hideously
+     * inefficient way. Shift bit by bit so that the units place is
+     * somewhere predictable, round, and shift back again.
+     */
+    x = *in;
+    roundword = 0;
+    for (i = ex; i < 0x7F + 23; i++) {
+        if (roundword & 1)
+            roundword |= 2;            /* preserve sticky bit */
+        roundword = (roundword >> 1) | ((x & 1) << 31);
+        x = x >> 1;
+    }
+    if (roundword && roundup) {
+        x++;
+    }
+    for (i = ex; i < 0x7F + 23; i++) {
+        x = x << 1;
+    }
+    *out = x;
+}
+
+char *test_ceilf(uint32 *in, uint32 *out) {
+    test_rintf(in, out, 0, 1);
+    return NULL;
+}
+
+char *test_floorf(uint32 *in, uint32 *out) {
+    test_rintf(in, out, 1, 0);
+    return NULL;
+}
+
+char *test_fmod(uint32 *a, uint32 *b, uint32 *out) {
+    int sign;
+    int32 aex, bex;
+    uint32 am[2], bm[2];
+
+    if (((a[0] & 0x7FFFFFFF) << 1) + !!a[1] > 0xFFE00000 ||
+        ((b[0] & 0x7FFFFFFF) << 1) + !!b[1] > 0xFFE00000) {
+        /* a or b is NaN: return QNaN, optionally with IVO */
+        uint32 an, bn;
+        out[0] = 0x7ff80000;
+        out[1] = 1;
+        an = ((a[0] & 0x7FFFFFFF) << 1) + !!a[1];
+        bn = ((b[0] & 0x7FFFFFFF) << 1) + !!b[1];
+        if ((an > 0xFFE00000 && an < 0xFFF00000) ||
+            (bn > 0xFFE00000 && bn < 0xFFF00000))
+            return "i";                /* at least one SNaN: IVO */
+        else
+            return NULL;               /* no SNaNs, but at least 1 QNaN */
+    }
+    if ((b[0] & 0x7FFFFFFF) == 0 && b[1] == 0) {   /* b==0: EDOM */
+        out[0] = 0x7ff80000;
+        out[1] = 1;
+        return "EDOM status=i";
+    }
+    if ((a[0] & 0x7FF00000) == 0x7FF00000) {   /* a==Inf: EDOM */
+        out[0] = 0x7ff80000;
+        out[1] = 1;
+        return "EDOM status=i";
+    }
+    if ((b[0] & 0x7FF00000) == 0x7FF00000) {   /* b==Inf: return a */
+        out[0] = a[0];
+        out[1] = a[1];
+        return NULL;
+    }
+    if ((a[0] & 0x7FFFFFFF) == 0 && a[1] == 0) {   /* a==0: return a */
+        out[0] = a[0];
+        out[1] = a[1];
+        return NULL;
+    }
+
+    /*
+     * OK. That's the special cases cleared out of the way. Now we
+     * have finite (though not necessarily normal) a and b.
+     */
+    sign = a[0] & 0x80000000;          /* we discard sign of b */
+    test_frexp(a, am, (uint32 *)&aex);
+    test_frexp(b, bm, (uint32 *)&bex);
+    am[0] &= 0xFFFFF, am[0] |= 0x100000;
+    bm[0] &= 0xFFFFF, bm[0] |= 0x100000;
+
+    while (aex >= bex) {
+        if (am[0] > bm[0] || (am[0] == bm[0] && am[1] >= bm[1])) {
+            am[1] -= bm[1];
+            am[0] = am[0] - bm[0] - (am[1] > ~bm[1]);
+        }
+        if (aex > bex) {
+            am[0] = (am[0] << 1) | ((am[1] & 0x80000000) >> 31);
+            am[1] <<= 1;
+            aex--;
+        } else
+            break;
+    }
+
+    /*
+     * Renormalise final result; this can be cunningly done by
+     * passing a denormal to ldexp.
+     */
+    aex += 0x3fd;
+    am[0] |= sign;
+    test_ldexp(am, (uint32 *)&aex, out);
+
+    return NULL;                       /* FIXME */
+}
+
+char *test_fmodf(uint32 *a, uint32 *b, uint32 *out) {
+    int sign;
+    int32 aex, bex;
+    uint32 am, bm;
+
+    if ((*a & 0x7FFFFFFF) > 0x7F800000 ||
+        (*b & 0x7FFFFFFF) > 0x7F800000) {
+        /* a or b is NaN: return QNaN, optionally with IVO */
+        uint32 an, bn;
+        *out = 0x7fc00001;
+        an = *a & 0x7FFFFFFF;
+        bn = *b & 0x7FFFFFFF;
+        if ((an > 0x7f800000 && an < 0x7fc00000) ||
+            (bn > 0x7f800000 && bn < 0x7fc00000))
+            return "i";                /* at least one SNaN: IVO */
+        else
+            return NULL;               /* no SNaNs, but at least 1 QNaN */
+    }
+    if ((*b & 0x7FFFFFFF) == 0) {      /* b==0: EDOM */
+        *out = 0x7fc00001;
+        return "EDOM status=i";
+    }
+    if ((*a & 0x7F800000) == 0x7F800000) {   /* a==Inf: EDOM */
+        *out = 0x7fc00001;
+        return "EDOM status=i";
+    }
+    if ((*b & 0x7F800000) == 0x7F800000) {   /* b==Inf: return a */
+        *out = *a;
+        return NULL;
+    }
+    if ((*a & 0x7FFFFFFF) == 0) {      /* a==0: return a */
+        *out = *a;
+        return NULL;
+    }
+
+    /*
+     * OK. That's the special cases cleared out of the way. Now we
+     * have finite (though not necessarily normal) a and b.
+     */
+    sign = a[0] & 0x80000000;          /* we discard sign of b */
+    test_frexpf(a, &am, (uint32 *)&aex);
+    test_frexpf(b, &bm, (uint32 *)&bex);
+    am &= 0x7FFFFF, am |= 0x800000;
+    bm &= 0x7FFFFF, bm |= 0x800000;
+
+    while (aex >= bex) {
+        if (am >= bm) {
+            am -= bm;
+        }
+        if (aex > bex) {
+            am <<= 1;
+            aex--;
+        } else
+            break;
+    }
+
+    /*
+     * Renormalise final result; this can be cunningly done by
+     * passing a denormal to ldexp.
+     */
+    aex += 0x7d;
+    am |= sign;
+    test_ldexpf(&am, (uint32 *)&aex, out);
+
+    return NULL;                       /* FIXME */
+}
+
+char *test_ldexp(uint32 *x, uint32 *np, uint32 *out) {
+    int n = *np;
+    int32 n2;
+    uint32 y[2];
+    int ex = (x[0] >> 20) & 0x7FF;     /* exponent */
+    int sign = x[0] & 0x80000000;
+
+    if (ex == 0x7FF) {                 /* inf/NaN; just return x */
+        out[0] = x[0];
+        out[1] = x[1];
+        return NULL;
+    }
+    if ((x[0] & 0x7FFFFFFF) == 0 && x[1] == 0) {   /* zero: return x */
+        out[0] = x[0];
+        out[1] = x[1];
+        return NULL;
+    }
+
+    test_frexp(x, y, (uint32 *)&n2);
+    ex = n + n2;
+    if (ex > 0x400) {                  /* overflow */
+        out[0] = sign | 0x7FF00000;
+        out[1] = 0;
+        return "overflow";
+    }
+    /*
+     * Underflow. 2^-1074 is 00000000.00000001; so if ex == -1074
+     * then we have something [2^-1075,2^-1074). Under round-to-
+     * nearest-even, this whole interval rounds up to 2^-1074,
+     * except for the bottom endpoint which rounds to even and is
+     * an underflow condition.
+     *
+     * So, ex < -1074 is definite underflow, and ex == -1074 is
+     * underflow iff all mantissa bits are zero.
+     */
+    if (ex < -1074 || (ex == -1074 && (y[0] & 0xFFFFF) == 0 && y[1] == 0)) {
+        out[0] = sign;                 /* underflow: correctly signed zero */
+        out[1] = 0;
+        return "underflow";
+    }
+
+    /*
+     * No overflow or underflow; should be nice and simple, unless
+     * we have to denormalise and round the result.
+     */
+    if (ex < -1021) {                  /* denormalise and round */
+        uint32 roundword;
+        y[0] &= 0x000FFFFF;
+        y[0] |= 0x00100000;            /* set leading bit */
+        roundword = 0;
+        while (ex < -1021) {
+            if (roundword & 1)
+                roundword |= 2;        /* preserve sticky bit */
+            roundword = (roundword >> 1) | ((y[1] & 1) << 31);
+            y[1] = (y[1] >> 1) | ((y[0] & 1) << 31);
+            y[0] = y[0] >> 1;
+            ex++;
+        }
+        if (roundword > 0x80000000 ||  /* round up */
+            (roundword == 0x80000000 && (y[1] & 1))) {  /* round up to even */
+            y[1]++;
+            y[0] += (y[1] == 0);
+        }
+        out[0] = sign | y[0];
+        out[1] = y[1];
+        /* Proper ERANGE underflow was handled earlier, but we still
+         * expect an IEEE Underflow exception if this partially
+         * underflowed result is not exact. */
+        if (roundword)
+            return "u";
+        return NULL;                   /* underflow was handled earlier */
+    } else {
+        out[0] = y[0] + (ex << 20);
+        out[1] = y[1];
+        return NULL;
+    }
+}
+
+char *test_ldexpf(uint32 *x, uint32 *np, uint32 *out) {
+    int n = *np;
+    int32 n2;
+    uint32 y;
+    int ex = (*x >> 23) & 0xFF;     /* exponent */
+    int sign = *x & 0x80000000;
+
+    if (ex == 0xFF) {                 /* inf/NaN; just return x */
+        *out = *x;
+        return NULL;
+    }
+    if ((*x & 0x7FFFFFFF) == 0) {      /* zero: return x */
+        *out = *x;
+        return NULL;
+    }
+
+    test_frexpf(x, &y, (uint32 *)&n2);
+    ex = n + n2;
+    if (ex > 0x80) {                  /* overflow */
+        *out = sign | 0x7F800000;
+        return "overflow";
+    }
+    /*
+     * Underflow. 2^-149 is 00000001; so if ex == -149 then we have
+     * something [2^-150,2^-149). Under round-to- nearest-even,
+     * this whole interval rounds up to 2^-149, except for the
+     * bottom endpoint which rounds to even and is an underflow
+     * condition.
+     *
+     * So, ex < -149 is definite underflow, and ex == -149 is
+     * underflow iff all mantissa bits are zero.
+     */
+    if (ex < -149 || (ex == -149 && (y & 0x7FFFFF) == 0)) {
+        *out = sign;                 /* underflow: correctly signed zero */
+        return "underflow";
+    }
+
+    /*
+     * No overflow or underflow; should be nice and simple, unless
+     * we have to denormalise and round the result.
+     */
+    if (ex < -125) {                  /* denormalise and round */
+        uint32 roundword;
+        y &= 0x007FFFFF;
+        y |= 0x00800000;               /* set leading bit */
+        roundword = 0;
+        while (ex < -125) {
+            if (roundword & 1)
+                roundword |= 2;        /* preserve sticky bit */
+            roundword = (roundword >> 1) | ((y & 1) << 31);
+            y = y >> 1;
+            ex++;
+        }
+        if (roundword > 0x80000000 ||  /* round up */
+            (roundword == 0x80000000 && (y & 1))) {  /* round up to even */
+            y++;
+        }
+        *out = sign | y;
+        /* Proper ERANGE underflow was handled earlier, but we still
+         * expect an IEEE Underflow exception if this partially
+         * underflowed result is not exact. */
+        if (roundword)
+            return "u";
+        return NULL;                   /* underflow was handled earlier */
+    } else {
+        *out = y + (ex << 23);
+        return NULL;
+    }
+}
+
+char *test_frexp(uint32 *x, uint32 *out, uint32 *nout) {
+    int ex = (x[0] >> 20) & 0x7FF;     /* exponent */
+    if (ex == 0x7FF) {                 /* inf/NaN; return x/0 */
+        out[0] = x[0];
+        out[1] = x[1];
+        nout[0] = 0;
+        return NULL;
+    }
+    if (ex == 0) {                     /* denormals/zeros */
+        int sign;
+        uint32 xh, xl;
+        if ((x[0] & 0x7FFFFFFF) == 0 && x[1] == 0) {
+            /* zero: return x/0 */
+            out[0] = x[0];
+            out[1] = x[1];
+            nout[0] = 0;
+            return NULL;
+        }
+        sign = x[0] & 0x80000000;
+        xh = x[0] & 0x7FFFFFFF;
+        xl = x[1];
+        ex = 1;
+        while (!(xh & 0x100000)) {
+            ex--;
+            xh = (xh << 1) | ((xl >> 31) & 1);
+            xl = (xl & 0x7FFFFFFF) << 1;
+        }
+        out[0] = sign | 0x3FE00000 | (xh & 0xFFFFF);
+        out[1] = xl;
+        nout[0] = ex - 0x3FE;
+        return NULL;
+    }
+    out[0] = 0x3FE00000 | (x[0] & 0x800FFFFF);
+    out[1] = x[1];
+    nout[0] = ex - 0x3FE;
+    return NULL;                       /* ordinary number; no error */
+}
+
+char *test_frexpf(uint32 *x, uint32 *out, uint32 *nout) {
+    int ex = (*x >> 23) & 0xFF;        /* exponent */
+    if (ex == 0xFF) {                  /* inf/NaN; return x/0 */
+        *out = *x;
+        nout[0] = 0;
+        return NULL;
+    }
+    if (ex == 0) {                     /* denormals/zeros */
+        int sign;
+        uint32 xv;
+        if ((*x & 0x7FFFFFFF) == 0) {
+            /* zero: return x/0 */
+            *out = *x;
+            nout[0] = 0;
+            return NULL;
+        }
+        sign = *x & 0x80000000;
+        xv = *x & 0x7FFFFFFF;
+        ex = 1;
+        while (!(xv & 0x800000)) {
+            ex--;
+            xv = xv << 1;
+        }
+        *out = sign | 0x3F000000 | (xv & 0x7FFFFF);
+        nout[0] = ex - 0x7E;
+        return NULL;
+    }
+    *out = 0x3F000000 | (*x & 0x807FFFFF);
+    nout[0] = ex - 0x7E;
+    return NULL;                       /* ordinary number; no error */
+}
+
+char *test_modf(uint32 *x, uint32 *fout, uint32 *iout) {
+    int ex = (x[0] >> 20) & 0x7FF;     /* exponent */
+    int sign = x[0] & 0x80000000;
+    uint32 fh, fl;
+
+    if (((x[0] & 0x7FFFFFFF) | (!!x[1])) > 0x7FF00000) {
+        /*
+         * NaN input: return the same in _both_ outputs.
+         */
+        fout[0] = iout[0] = x[0];
+        fout[1] = iout[1] = x[1];
+        return NULL;
+    }
+
+    test_rint(x, iout, 0, 0);
+    fh = x[0] - iout[0];
+    fl = x[1] - iout[1];
+    if (!fh && !fl) {                  /* no fraction part */
+        fout[0] = sign;
+        fout[1] = 0;
+        return NULL;
+    }
+    if (!(iout[0] & 0x7FFFFFFF) && !iout[1]) {   /* no integer part */
+        fout[0] = x[0];
+        fout[1] = x[1];
+        return NULL;
+    }
+    while (!(fh & 0x100000)) {
+        ex--;
+        fh = (fh << 1) | ((fl >> 31) & 1);
+        fl = (fl & 0x7FFFFFFF) << 1;
+    }
+    fout[0] = sign | (ex << 20) | (fh & 0xFFFFF);
+    fout[1] = fl;
+    return NULL;
+}
+
+char *test_modff(uint32 *x, uint32 *fout, uint32 *iout) {
+    int ex = (*x >> 23) & 0xFF;        /* exponent */
+    int sign = *x & 0x80000000;
+    uint32 f;
+
+    if ((*x & 0x7FFFFFFF) > 0x7F800000) {
+        /*
+         * NaN input: return the same in _both_ outputs.
+         */
+        *fout = *iout = *x;
+        return NULL;
+    }
+
+    test_rintf(x, iout, 0, 0);
+    f = *x - *iout;
+    if (!f) {                          /* no fraction part */
+        *fout = sign;
+        return NULL;
+    }
+    if (!(*iout & 0x7FFFFFFF)) {       /* no integer part */
+        *fout = *x;
+        return NULL;
+    }
+    while (!(f & 0x800000)) {
+        ex--;
+        f = f << 1;
+    }
+    *fout = sign | (ex << 23) | (f & 0x7FFFFF);
+    return NULL;
+}
+
+char *test_copysign(uint32 *x, uint32 *y, uint32 *out)
+{
+    int ysign = y[0] & 0x80000000;
+    int xhigh = x[0] & 0x7fffffff;
+
+    out[0] = ysign | xhigh;
+    out[1] = x[1];
+
+    /* There can be no error */
+    return NULL;
+}
+
+char *test_copysignf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int ysign = y[0] & 0x80000000;
+    int xhigh = x[0] & 0x7fffffff;
+
+    out[0] = ysign | xhigh;
+
+    /* There can be no error */
+    return NULL;
+}
+
+char *test_isfinite(uint32 *x, uint32 *out)
+{
+    int xhigh = x[0];
+    /* Being finite means that the exponent is not 0x7ff */
+    if ((xhigh & 0x7ff00000) == 0x7ff00000) out[0] = 0;
+    else out[0] = 1;
+    return NULL;
+}
+
+char *test_isfinitef(uint32 *x, uint32 *out)
+{
+    /* Being finite means that the exponent is not 0xff */
+    if ((x[0] & 0x7f800000) == 0x7f800000) out[0] = 0;
+    else out[0] = 1;
+    return NULL;
+}
+
+char *test_isinff(uint32 *x, uint32 *out)
+{
+    /* Being infinite means that our bottom 30 bits equate to 0x7f800000 */
+    if ((x[0] & 0x7fffffff) == 0x7f800000) out[0] = 1;
+    else out[0] = 0;
+    return NULL;
+}
+
+char *test_isinf(uint32 *x, uint32 *out)
+{
+    int xhigh = x[0];
+    int xlow = x[1];
+    /* Being infinite means that our fraction is zero and exponent is 0x7ff */
+    if (((xhigh & 0x7fffffff) == 0x7ff00000) && (xlow == 0)) out[0] = 1;
+    else out[0] = 0;
+    return NULL;
+}
+
+char *test_isnanf(uint32 *x, uint32 *out)
+{
+    /* Being NaN means that our exponent is 0xff and non-0 fraction */
+    int exponent = x[0] & 0x7f800000;
+    int fraction = x[0] & 0x007fffff;
+    if ((exponent == 0x7f800000) && (fraction != 0)) out[0] = 1;
+    else out[0] = 0;
+    return NULL;
+}
+
+char *test_isnan(uint32 *x, uint32 *out)
+{
+    /* Being NaN means that our exponent is 0x7ff and non-0 fraction */
+    int exponent = x[0] & 0x7ff00000;
+    int fractionhigh = x[0] & 0x000fffff;
+    if ((exponent == 0x7ff00000) && ((fractionhigh != 0) || x[1] != 0))
+        out[0] = 1;
+    else out[0] = 0;
+    return NULL;
+}
+
+char *test_isnormalf(uint32 *x, uint32 *out)
+{
+    /* Being normal means exponent is not 0 and is not 0xff */
+    int exponent = x[0] & 0x7f800000;
+    if (exponent == 0x7f800000) out[0] = 0;
+    else if (exponent == 0) out[0] = 0;
+    else out[0] = 1;
+    return NULL;
+}
+
+char *test_isnormal(uint32 *x, uint32 *out)
+{
+    /* Being normal means exponent is not 0 and is not 0x7ff */
+    int exponent = x[0] & 0x7ff00000;
+    if (exponent == 0x7ff00000) out[0] = 0;
+    else if (exponent == 0) out[0] = 0;
+    else out[0] = 1;
+    return NULL;
+}
+
+char *test_signbitf(uint32 *x, uint32 *out)
+{
+    /* Sign bit is bit 31 */
+    out[0] = (x[0] >> 31) & 1;
+    return NULL;
+}
+
+char *test_signbit(uint32 *x, uint32 *out)
+{
+    /* Sign bit is bit 31 */
+    out[0] = (x[0] >> 31) & 1;
+    return NULL;
+}
+
+char *test_fpclassify(uint32 *x, uint32 *out)
+{
+    int exponent = (x[0] & 0x7ff00000) >> 20;
+    int fraction = (x[0] & 0x000fffff) | x[1];
+
+    if ((exponent == 0x00) && (fraction == 0)) out[0] = 0;
+    else if ((exponent == 0x00) && (fraction != 0)) out[0] = 4;
+    else if ((exponent == 0x7ff) && (fraction == 0)) out[0] = 3;
+    else if ((exponent == 0x7ff) && (fraction != 0)) out[0] = 7;
+    else out[0] = 5;
+    return NULL;
+}
+
+char *test_fpclassifyf(uint32 *x, uint32 *out)
+{
+    int exponent = (x[0] & 0x7f800000) >> 23;
+    int fraction = x[0] & 0x007fffff;
+
+    if ((exponent == 0x000) && (fraction == 0)) out[0] = 0;
+    else if ((exponent == 0x000) && (fraction != 0)) out[0] = 4;
+    else if ((exponent == 0xff) && (fraction == 0)) out[0] = 3;
+    else if ((exponent == 0xff) && (fraction != 0)) out[0] = 7;
+    else out[0] = 5;
+    return NULL;
+}
+
+/*
+ * Internal function that compares doubles in x & y and returns -3, -2, -1, 0,
+ * 1 if they compare to be signaling, unordered, less than, equal or greater
+ * than.
+ */
+static int fpcmp4(uint32 *x, uint32 *y)
+{
+    int result = 0;
+
+    /*
+     * Sort out whether results are ordered or not to begin with
+     * NaNs have exponent 0x7ff, and non-zero fraction. Signaling NaNs take
+     * higher priority than quiet ones.
+     */
+    if ((x[0] & 0x7fffffff) >= 0x7ff80000) result = -2;
+    else if ((x[0] & 0x7fffffff) > 0x7ff00000) result = -3;
+    else if (((x[0] & 0x7fffffff) == 0x7ff00000) && (x[1] != 0)) result = -3;
+    if ((y[0] & 0x7fffffff) >= 0x7ff80000 && result != -3) result = -2;
+    else if ((y[0] & 0x7fffffff) > 0x7ff00000) result = -3;
+    else if (((y[0] & 0x7fffffff) == 0x7ff00000) && (y[1] != 0)) result = -3;
+    if (result != 0) return result;
+
+    /*
+     * The two forms of zero are equal
+     */
+    if (((x[0] & 0x7fffffff) == 0) && x[1] == 0 &&
+        ((y[0] & 0x7fffffff) == 0) && y[1] == 0)
+        return 0;
+
+    /*
+     * If x and y have different signs we can tell that they're not equal
+     * If x is +ve we have x > y return 1 - otherwise y is +ve return -1
+     */
+    if ((x[0] >> 31) != (y[0] >> 31))
+        return ((x[0] >> 31) == 0) - ((y[0] >> 31) == 0);
+
+    /*
+     * Now we have both signs the same, let's do an initial compare of the
+     * values.
+     *
+     * Whoever designed IEEE754's floating point formats is very clever and
+     * earns my undying admiration.  Once you remove the sign-bit, the
+     * floating point numbers can be ordered using the standard <, ==, >
+     * operators will treating the fp-numbers as integers with that bit-
+     * pattern.
+     */
+    if ((x[0] & 0x7fffffff) < (y[0] & 0x7fffffff)) result = -1;
+    else if ((x[0] & 0x7fffffff) > (y[0] & 0x7fffffff)) result = 1;
+    else if (x[1] < y[1]) result = -1;
+    else if (x[1] > y[1]) result = 1;
+    else result = 0;
+
+    /*
+     * Now we return the result - is x is positive (and therefore so is y) we
+     * return the plain result - otherwise we negate it and return.
+     */
+    if ((x[0] >> 31) == 0) return result;
+    else return -result;
+}
+
+/*
+ * Internal function that compares floats in x & y and returns -3, -2, -1, 0,
+ * 1 if they compare to be signaling, unordered, less than, equal or greater
+ * than.
+ */
+static int fpcmp4f(uint32 *x, uint32 *y)
+{
+    int result = 0;
+
+    /*
+     * Sort out whether results are ordered or not to begin with
+     * NaNs have exponent 0xff, and non-zero fraction - we have to handle all
+     * signaling cases over the quiet ones
+     */
+    if ((x[0] & 0x7fffffff) >= 0x7fc00000) result = -2;
+    else if ((x[0] & 0x7fffffff) > 0x7f800000) result = -3;
+    if ((y[0] & 0x7fffffff) >= 0x7fc00000 && result != -3) result = -2;
+    else if ((y[0] & 0x7fffffff) > 0x7f800000) result = -3;
+    if (result != 0) return result;
+
+    /*
+     * The two forms of zero are equal
+     */
+    if (((x[0] & 0x7fffffff) == 0) && ((y[0] & 0x7fffffff) == 0))
+        return 0;
+
+    /*
+     * If x and y have different signs we can tell that they're not equal
+     * If x is +ve we have x > y return 1 - otherwise y is +ve return -1
+     */
+    if ((x[0] >> 31) != (y[0] >> 31))
+        return ((x[0] >> 31) == 0) - ((y[0] >> 31) == 0);
+
+    /*
+     * Now we have both signs the same, let's do an initial compare of the
+     * values.
+     *
+     * Whoever designed IEEE754's floating point formats is very clever and
+     * earns my undying admiration.  Once you remove the sign-bit, the
+     * floating point numbers can be ordered using the standard <, ==, >
+     * operators will treating the fp-numbers as integers with that bit-
+     * pattern.
+     */
+    if ((x[0] & 0x7fffffff) < (y[0] & 0x7fffffff)) result = -1;
+    else if ((x[0] & 0x7fffffff) > (y[0] & 0x7fffffff)) result = 1;
+    else result = 0;
+
+    /*
+     * Now we return the result - is x is positive (and therefore so is y) we
+     * return the plain result - otherwise we negate it and return.
+     */
+    if ((x[0] >> 31) == 0) return result;
+    else return -result;
+}
+
+char *test_isgreater(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4(x, y);
+    *out = (result == 1);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_isgreaterequal(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4(x, y);
+    *out = (result >= 0);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_isless(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4(x, y);
+    *out = (result == -1);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_islessequal(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4(x, y);
+    *out = (result == -1) || (result == 0);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_islessgreater(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4(x, y);
+    *out = (result == -1) || (result == 1);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_isunordered(uint32 *x, uint32 *y, uint32 *out)
+{
+    int normal = 0;
+    int result = fpcmp4(x, y);
+
+    test_isnormal(x, out);
+    normal |= *out;
+    test_isnormal(y, out);
+    normal |= *out;
+    *out = (result == -2) || (result == -3);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_isgreaterf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4f(x, y);
+    *out = (result == 1);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_isgreaterequalf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4f(x, y);
+    *out = (result >= 0);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_islessf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4f(x, y);
+    *out = (result == -1);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_islessequalf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4f(x, y);
+    *out = (result == -1) || (result == 0);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_islessgreaterf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int result = fpcmp4f(x, y);
+    *out = (result == -1) || (result == 1);
+    return result == -3 ? "i" : NULL;
+}
+
+char *test_isunorderedf(uint32 *x, uint32 *y, uint32 *out)
+{
+    int normal = 0;
+    int result = fpcmp4f(x, y);
+
+    test_isnormalf(x, out);
+    normal |= *out;
+    test_isnormalf(y, out);
+    normal |= *out;
+    *out = (result == -2) || (result == -3);
+    return result == -3 ? "i" : NULL;
+}
diff --git a/libc/AOR_v20.02/math/test/rtest/semi.h b/libc/AOR_v20.02/math/test/rtest/semi.h
new file mode 100644
index 0000000000000..0aaeee7a0acbe
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/semi.h
@@ -0,0 +1,54 @@
+/*
+ * semi.h: header for semi.c
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef test_semi_h
+#define test_semi_h
+
+#include "types.h"
+
+char *test_ceil(uint32 *in, uint32 *out);
+char *test_floor(uint32 *in, uint32 *out);
+char *test_fmod(uint32 *a, uint32 *b, uint32 *out);
+char *test_ldexp(uint32 *x, uint32 *n, uint32 *out);
+char *test_frexp(uint32 *x, uint32 *out, uint32 *nout);
+char *test_modf(uint32 *x, uint32 *iout, uint32 *fout);
+char *test_ceilf(uint32 *in, uint32 *out);
+char *test_floorf(uint32 *in, uint32 *out);
+char *test_fmodf(uint32 *a, uint32 *b, uint32 *out);
+char *test_ldexpf(uint32 *x, uint32 *n, uint32 *out);
+char *test_frexpf(uint32 *x, uint32 *out, uint32 *nout);
+char *test_modff(uint32 *x, uint32 *iout, uint32 *fout);
+
+char *test_copysign(uint32 *x, uint32 *y, uint32 *out);
+char *test_copysignf(uint32 *x, uint32 *y, uint32 *out);
+char *test_isfinite(uint32 *x, uint32 *out);
+char *test_isfinitef(uint32 *x, uint32 *out);
+char *test_isinf(uint32 *x, uint32 *out);
+char *test_isinff(uint32 *x, uint32 *out);
+char *test_isnan(uint32 *x, uint32 *out);
+char *test_isnanf(uint32 *x, uint32 *out);
+char *test_isnormal(uint32 *x, uint32 *out);
+char *test_isnormalf(uint32 *x, uint32 *out);
+char *test_signbit(uint32 *x, uint32 *out);
+char *test_signbitf(uint32 *x, uint32 *out);
+char *test_fpclassify(uint32 *x, uint32 *out);
+char *test_fpclassifyf(uint32 *x, uint32 *out);
+
+char *test_isgreater(uint32 *x, uint32 *y, uint32 *out);
+char *test_isgreaterequal(uint32 *x, uint32 *y, uint32 *out);
+char *test_isless(uint32 *x, uint32 *y, uint32 *out);
+char *test_islessequal(uint32 *x, uint32 *y, uint32 *out);
+char *test_islessgreater(uint32 *x, uint32 *y, uint32 *out);
+char *test_isunordered(uint32 *x, uint32 *y, uint32 *out);
+char *test_isgreaterf(uint32 *x, uint32 *y, uint32 *out);
+char *test_isgreaterequalf(uint32 *x, uint32 *y, uint32 *out);
+char *test_islessf(uint32 *x, uint32 *y, uint32 *out);
+char *test_islessequalf(uint32 *x, uint32 *y, uint32 *out);
+char *test_islessgreaterf(uint32 *x, uint32 *y, uint32 *out);
+char *test_isunorderedf(uint32 *x, uint32 *y, uint32 *out);
+#endif
diff --git a/libc/AOR_v20.02/math/test/rtest/types.h b/libc/AOR_v20.02/math/test/rtest/types.h
new file mode 100644
index 0000000000000..36806a68dcab5
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/types.h
@@ -0,0 +1,26 @@
+/*
+ * types.h
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef mathtest_types_h
+#define mathtest_types_h
+
+#include <limits.h>
+
+#if UINT_MAX == 4294967295
+typedef unsigned int uint32;
+typedef int int32;
+#define I32 ""
+#elif ULONG_MAX == 4294967295
+typedef unsigned long uint32;
+typedef long int32;
+#define I32 "l"
+#else
+#error Could not find an unsigned 32-bit integer type
+#endif
+
+#endif
diff --git a/libc/AOR_v20.02/math/test/rtest/wrappers.c b/libc/AOR_v20.02/math/test/rtest/wrappers.c
new file mode 100644
index 0000000000000..71b90ea47fad9
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/wrappers.c
@@ -0,0 +1,262 @@
+/*
+ * wrappers.c - wrappers to modify output of MPFR/MPC test functions
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include "intern.h"
+
+void wrapper_init(wrapperctx *ctx)
+{
+    int i;
+    ctx->nops = ctx->nresults = 0;
+    for (i = 0; i < 2; i++) {
+        ctx->mpfr_ops[i] = NULL;
+        ctx->mpc_ops[i] = NULL;
+        ctx->ieee_ops[i] = NULL;
+    }
+    ctx->mpfr_result = NULL;
+    ctx->mpc_result = NULL;
+    ctx->ieee_result = NULL;
+    ctx->need_regen = 0;
+}
+
+void wrapper_op_real(wrapperctx *ctx, const mpfr_t r,
+                     int size, const uint32 *ieee)
+{
+    assert(ctx->nops < 2);
+    ctx->mpfr_ops[ctx->nops] = r;
+    ctx->ieee_ops[ctx->nops] = ieee;
+    ctx->size_ops[ctx->nops] = size;
+    ctx->nops++;
+}
+
+void wrapper_op_complex(wrapperctx *ctx, const mpc_t c,
+                        int size, const uint32 *ieee)
+{
+    assert(ctx->nops < 2);
+    ctx->mpc_ops[ctx->nops] = c;
+    ctx->ieee_ops[ctx->nops] = ieee;
+    ctx->size_ops[ctx->nops] = size;
+    ctx->nops++;
+}
+
+void wrapper_result_real(wrapperctx *ctx, mpfr_t r,
+                         int size, uint32 *ieee)
+{
+    assert(ctx->nresults < 1);
+    ctx->mpfr_result = r;
+    ctx->ieee_result = ieee;
+    ctx->size_result = size;
+    ctx->nresults++;
+}
+
+void wrapper_result_complex(wrapperctx *ctx, mpc_t c,
+                            int size, uint32 *ieee)
+{
+    assert(ctx->nresults < 1);
+    ctx->mpc_result = c;
+    ctx->ieee_result = ieee;
+    ctx->size_result = size;
+    ctx->nresults++;
+}
+
+int wrapper_run(wrapperctx *ctx, wrapperfunc wrappers[MAXWRAPPERS])
+{
+    int i;
+    for (i = 0; i < MAXWRAPPERS && wrappers[i]; i++)
+        wrappers[i](ctx);
+    universal_wrapper(ctx);
+    return ctx->need_regen;
+}
+
+mpfr_srcptr wrapper_get_mpfr(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpfr_result);
+        return ctx->mpfr_result;
+    } else {
+        assert(ctx->mpfr_ops[op]);
+        return ctx->mpfr_ops[op];
+    }
+}
+
+const uint32 *wrapper_get_ieee(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpfr_result);
+        return ctx->ieee_result;
+    } else {
+        assert(ctx->mpfr_ops[op]);
+        return ctx->ieee_ops[op];
+    }
+}
+
+int wrapper_get_nops(wrapperctx *ctx)
+{
+    return ctx->nops;
+}
+
+int wrapper_get_size(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpfr_result || ctx->mpc_result);
+        return ctx->size_result;
+    } else {
+        assert(ctx->mpfr_ops[op] || ctx->mpc_ops[op]);
+        return ctx->size_ops[op];
+    }
+}
+
+int wrapper_is_complex(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpfr_result || ctx->mpc_result);
+        return ctx->mpc_result != NULL;
+    } else {
+        assert(ctx->mpfr_ops[op] || ctx->mpc_ops[op]);
+        return ctx->mpc_ops[op] != NULL;
+    }
+}
+
+mpc_srcptr wrapper_get_mpc(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpc_result);
+        return ctx->mpc_result;
+    } else {
+        assert(ctx->mpc_ops[op]);
+        return ctx->mpc_ops[op];
+    }
+}
+
+mpfr_srcptr wrapper_get_mpfr_r(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpc_result);
+        return mpc_realref(ctx->mpc_result);
+    } else {
+        assert(ctx->mpc_ops[op]);
+        return mpc_realref(ctx->mpc_ops[op]);
+    }
+}
+
+mpfr_srcptr wrapper_get_mpfr_i(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpc_result);
+        return mpc_imagref(ctx->mpc_result);
+    } else {
+        assert(ctx->mpc_ops[op]);
+        return mpc_imagref(ctx->mpc_ops[op]);
+    }
+}
+
+const uint32 *wrapper_get_ieee_r(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpc_result);
+        return ctx->ieee_result;
+    } else {
+        assert(ctx->mpc_ops[op]);
+        return ctx->ieee_ops[op];
+    }
+}
+
+const uint32 *wrapper_get_ieee_i(wrapperctx *ctx, int op)
+{
+    if (op < 0) {
+        assert(ctx->mpc_result);
+        return ctx->ieee_result + 4;
+    } else {
+        assert(ctx->mpc_ops[op]);
+        return ctx->ieee_ops[op] + 2;
+    }
+}
+
+void wrapper_set_sign(wrapperctx *ctx, uint32 sign)
+{
+    assert(ctx->mpfr_result);
+    ctx->ieee_result[0] |= (sign & 0x80000000U);
+}
+
+void wrapper_set_sign_r(wrapperctx *ctx, uint32 sign)
+{
+    assert(ctx->mpc_result);
+    ctx->ieee_result[0] |= (sign & 0x80000000U);
+}
+
+void wrapper_set_sign_i(wrapperctx *ctx, uint32 sign)
+{
+    assert(ctx->mpc_result);
+    ctx->ieee_result[4] |= (sign & 0x80000000U);
+}
+
+void wrapper_set_nan(wrapperctx *ctx)
+{
+    assert(ctx->mpfr_result);
+    mpfr_set_nan(ctx->mpfr_result);
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_nan_r(wrapperctx *ctx)
+{
+    assert(ctx->mpc_result);
+    mpfr_set_nan(mpc_realref(ctx->mpc_result)); /* FIXME: better way? */
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_nan_i(wrapperctx *ctx)
+{
+    assert(ctx->mpc_result);
+    mpfr_set_nan(mpc_imagref(ctx->mpc_result)); /* FIXME: better way? */
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_int(wrapperctx *ctx, int val)
+{
+    assert(ctx->mpfr_result);
+    mpfr_set_si(ctx->mpfr_result, val, GMP_RNDN);
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_int_r(wrapperctx *ctx, int val)
+{
+    assert(ctx->mpc_result);
+    mpfr_set_si(mpc_realref(ctx->mpc_result), val, GMP_RNDN);
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_int_i(wrapperctx *ctx, int val)
+{
+    assert(ctx->mpc_result);
+    mpfr_set_si(mpc_realref(ctx->mpc_result), val, GMP_RNDN);
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_mpfr(wrapperctx *ctx, const mpfr_t val)
+{
+    assert(ctx->mpfr_result);
+    mpfr_set(ctx->mpfr_result, val, GMP_RNDN);
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_mpfr_r(wrapperctx *ctx, const mpfr_t val)
+{
+    assert(ctx->mpc_result);
+    mpfr_set(mpc_realref(ctx->mpc_result), val, GMP_RNDN);
+    ctx->need_regen = 1;
+}
+
+void wrapper_set_mpfr_i(wrapperctx *ctx, const mpfr_t val)
+{
+    assert(ctx->mpc_result);
+    mpfr_set(mpc_realref(ctx->mpc_result), val, GMP_RNDN);
+    ctx->need_regen = 1;
+}
diff --git a/libc/AOR_v20.02/math/test/rtest/wrappers.h b/libc/AOR_v20.02/math/test/rtest/wrappers.h
new file mode 100644
index 0000000000000..e2e653a0f01e1
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/rtest/wrappers.h
@@ -0,0 +1,115 @@
+/*
+ * wrappers.h - wrappers to modify output of MPFR/MPC test functions
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+typedef struct {
+    /* Structure type should be considered opaque outside wrappers.c,
+     * though we have to define it here so its size is known. */
+    int nops;
+    int nresults;
+    mpfr_srcptr mpfr_ops[2];
+    mpfr_ptr mpfr_result;
+    mpc_srcptr mpc_ops[2];
+    mpc_ptr mpc_result;
+    const uint32 *ieee_ops[2];
+    uint32 *ieee_result;
+    int size_ops[2];
+    int size_result;
+    int need_regen;
+} wrapperctx;
+
+typedef void (*wrapperfunc)(wrapperctx *ctx);
+#define MAXWRAPPERS 3
+
+/*
+ * Functions for the test harness to call.
+ *
+ * When the test harness executes a test function, it should
+ * initialise a wrapperctx with wrapper_init, then provide all the
+ * operands and results in both mpfr/mpc and IEEE (+ extrabits)
+ * formats via wrapper_op_* and wrapper_result_*. Then it should run
+ * the function's wrappers using wrapper_run(), and if that returns
+ * true then the primary result has been rewritten in mpfr/mpc format
+ * and it should therefore retranslate into IEEE.
+ *
+ * 'size' in all prototypes below represents an FP type by giving the
+ * number of 32-bit words it requires, so 1=float and 2=double. Input
+ * operands will be that many words (or that many for both their real
+ * and imag parts); outputs will have one extra word for 'extrabits'.
+ *
+ * This system only applies at all to reference functions using
+ * mpfr/mpc. The seminumerical functions we implement in pure IEEE
+ * form are expected to handle all their own special cases correctly.
+ */
+
+void wrapper_init(wrapperctx *ctx);
+
+/* Real operand. */
+void wrapper_op_real(wrapperctx *ctx, const mpfr_t r,
+                     int size, const uint32 *ieee);
+
+/* Complex operand. Real part starts at ieee[0], the imag part at ieee[2]. */
+void wrapper_op_complex(wrapperctx *ctx, const mpc_t c,
+                        int size, const uint32 *ieee);
+
+/* Real result. ieee contains size+1 words, as discussed above. */
+void wrapper_result_real(wrapperctx *ctx, mpfr_t r,
+                         int size, uint32 *ieee);
+
+/* Complex result. ieee contains size+1 words of real part starting at
+ * ieee[0], and another size+1 of imag part starting at ieee[4]. */
+void wrapper_result_complex(wrapperctx *ctx, mpc_t c,
+                            int size, uint32 *ieee);
+
+int wrapper_run(wrapperctx *ctx, wrapperfunc wrappers[MAXWRAPPERS]);
+
+/*
+ * Functions for wrappers to call. 'op' indicates which operand is
+ * being requested: 0,1 means first and second, and -1 means the
+ * result.
+ */
+
+mpfr_srcptr wrapper_get_mpfr(wrapperctx *ctx, int op);
+const uint32 *wrapper_get_ieee(wrapperctx *ctx, int op);
+
+mpc_srcptr wrapper_get_mpc(wrapperctx *ctx, int op);
+mpfr_srcptr wrapper_get_mpfr_r(wrapperctx *ctx, int op);
+mpfr_srcptr wrapper_get_mpfr_i(wrapperctx *ctx, int op);
+const uint32 *wrapper_get_ieee_r(wrapperctx *ctx, int op);
+const uint32 *wrapper_get_ieee_i(wrapperctx *ctx, int op);
+
+/* Query operand count + types */
+int wrapper_get_nops(wrapperctx *ctx);
+int wrapper_get_size(wrapperctx *ctx, int op);
+int wrapper_is_complex(wrapperctx *ctx, int op);
+
+/* Change just the sign of the result. Only the top bit of 'sign' is used. */
+void wrapper_set_sign(wrapperctx *ctx, uint32 sign);
+void wrapper_set_sign_r(wrapperctx *ctx, uint32 sign);
+void wrapper_set_sign_i(wrapperctx *ctx, uint32 sign);
+
+/* Set a result to NaN. */
+void wrapper_set_nan(wrapperctx *ctx);
+void wrapper_set_nan_r(wrapperctx *ctx);
+void wrapper_set_nan_i(wrapperctx *ctx);
+
+/* Set a result to an integer value (converted to the appropriate
+ * float format). */
+void wrapper_set_int(wrapperctx *ctx, int val);
+void wrapper_set_int_r(wrapperctx *ctx, int val);
+void wrapper_set_int_i(wrapperctx *ctx, int val);
+
+/* Set a result to a new MPFR float. */
+void wrapper_set_mpfr(wrapperctx *ctx, const mpfr_t val);
+void wrapper_set_mpfr_r(wrapperctx *ctx, const mpfr_t val);
+void wrapper_set_mpfr_i(wrapperctx *ctx, const mpfr_t val);
+
+/*
+ * A universal wrapper called for _all_ functions, that doesn't have
+ * to be specified individually everywhere.
+ */
+void universal_wrapper(wrapperctx *ctx);
diff --git a/libc/AOR_v20.02/math/test/runulp.sh b/libc/AOR_v20.02/math/test/runulp.sh
new file mode 100755
index 0000000000000..431829bfc52ff
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/runulp.sh
@@ -0,0 +1,295 @@
+#!/bin/bash
+
+# ULP error check script.
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+#set -x
+set -eu
+
+# cd to bin directory.
+cd "${0%/*}"
+
+rmodes='n u d z'
+#rmodes=n
+flags="${ULPFLAGS:--q}"
+emu="$@"
+
+FAIL=0
+PASS=0
+
+t() {
+	[ $r = "n" ] && Lt=$L || Lt=$Ldir
+	$emu ./ulp -r $r -e $Lt $flags "$@" && PASS=$((PASS+1)) || FAIL=$((FAIL+1))
+}
+
+check() {
+	$emu ./ulp -f -q "$@" >/dev/null
+}
+
+Ldir=0.5
+for r in $rmodes
+do
+L=0.01
+t exp  0 0xffff000000000000 10000
+t exp  0x1p-6     0x1p6     40000
+t exp -0x1p-6    -0x1p6     40000
+t exp  633.3      733.3     10000
+t exp -633.3     -777.3     10000
+
+L=0.01
+t exp2  0 0xffff000000000000 10000
+t exp2  0x1p-6     0x1p6     40000
+t exp2 -0x1p-6    -0x1p6     40000
+t exp2  633.3      733.3     10000
+t exp2 -633.3     -777.3     10000
+
+L=0.02
+t log  0 0xffff000000000000 10000
+t log  0x1p-4    0x1p4      40000
+t log  0         inf        40000
+
+L=0.05
+t log2  0 0xffff000000000000 10000
+t log2  0x1p-4    0x1p4      40000
+t log2  0         inf        40000
+
+L=0.05
+t pow  0.5  2.0  x  0  inf 20000
+t pow -0.5 -2.0  x  0  inf 20000
+t pow  0.5  2.0  x -0 -inf 20000
+t pow -0.5 -2.0  x -0 -inf 20000
+t pow  0.5  2.0  x  0x1p-10  0x1p10  40000
+t pow  0.5  2.0  x -0x1p-10 -0x1p10  40000
+t pow  0    inf  x    0.5      2.0   80000
+t pow  0    inf  x   -0.5     -2.0   80000
+t pow  0x1.fp-1   0x1.08p0  x  0x1p8 0x1p17  80000
+t pow  0x1.fp-1   0x1.08p0  x -0x1p8 -0x1p17 80000
+t pow  0         0x1p-1000  x  0 1.0 50000
+t pow  0x1p1000        inf  x  0 1.0 50000
+t pow  0x1.ffffffffffff0p-1  0x1.0000000000008p0 x 0x1p60 0x1p68 50000
+t pow  0x1.ffffffffff000p-1  0x1p0 x 0x1p50 0x1p52 50000
+t pow -0x1.ffffffffff000p-1 -0x1p0 x 0x1p50 0x1p52 50000
+
+L=0.01
+t expf  0    0xffff0000    10000
+t expf  0x1p-14   0x1p8    50000
+t expf -0x1p-14  -0x1p8    50000
+
+L=0.01
+t exp2f  0    0xffff0000   10000
+t exp2f  0x1p-14   0x1p8   50000
+t exp2f -0x1p-14  -0x1p8   50000
+
+L=0.32
+t logf  0    0xffff0000    10000
+t logf  0x1p-4    0x1p4    50000
+t logf  0         inf      50000
+
+L=0.26
+t log2f  0    0xffff0000   10000
+t log2f  0x1p-4    0x1p4   50000
+t log2f  0         inf     50000
+
+L=0.06
+t sinf  0    0xffff0000    10000
+t sinf  0x1p-14  0x1p54    50000
+t sinf -0x1p-14 -0x1p54    50000
+
+L=0.06
+t cosf  0    0xffff0000    10000
+t cosf  0x1p-14  0x1p54    50000
+t cosf -0x1p-14 -0x1p54    50000
+
+L=0.06
+t sincosf_sinf  0    0xffff0000    10000
+t sincosf_sinf  0x1p-14  0x1p54    50000
+t sincosf_sinf -0x1p-14 -0x1p54    50000
+
+L=0.06
+t sincosf_cosf  0    0xffff0000    10000
+t sincosf_cosf  0x1p-14  0x1p54    50000
+t sincosf_cosf -0x1p-14 -0x1p54    50000
+
+L=0.4
+t powf  0x1p-1   0x1p1  x  0x1p-7 0x1p7   50000
+t powf  0x1p-1   0x1p1  x -0x1p-7 -0x1p7  50000
+t powf  0x1p-70 0x1p70  x  0x1p-1 0x1p1   50000
+t powf  0x1p-70 0x1p70  x  -0x1p-1 -0x1p1 50000
+t powf  0x1.ep-1 0x1.1p0 x  0x1p8 0x1p14  50000
+t powf  0x1.ep-1 0x1.1p0 x -0x1p8 -0x1p14 50000
+done
+
+# vector functions
+Ldir=0.5
+r='n'
+flags="${ULPFLAGS:--q} -f"
+runs=
+check __s_exp 1 && runs=1
+runv=
+check __v_exp 1 && runv=1
+runvn=
+check __vn_exp 1 && runvn=1
+
+range_exp='
+  0 0xffff000000000000 10000
+  0x1p-6     0x1p6     400000
+ -0x1p-6    -0x1p6     400000
+  633.3      733.3     10000
+ -633.3     -777.3     10000
+'
+
+range_log='
+  0 0xffff000000000000 10000
+  0x1p-4     0x1p4     400000
+  0          inf       400000
+'
+
+range_pow='
+ 0x1p-1   0x1p1  x  0x1p-10 0x1p10   50000
+ 0x1p-1   0x1p1  x -0x1p-10 -0x1p10  50000
+ 0x1p-500 0x1p500  x  0x1p-1 0x1p1   50000
+ 0x1p-500 0x1p500  x  -0x1p-1 -0x1p1 50000
+ 0x1.ep-1 0x1.1p0 x  0x1p8 0x1p16    50000
+ 0x1.ep-1 0x1.1p0 x -0x1p8 -0x1p16   50000
+'
+
+range_sin='
+  0 0xffff000000000000 10000
+  0x1p-4     0x1p4     400000
+ -0x1p-23    0x1p23    400000
+'
+range_cos="$range_sin"
+
+range_expf='
+  0    0xffff0000    10000
+  0x1p-14   0x1p8    500000
+ -0x1p-14  -0x1p8    500000
+'
+
+range_expf_1u="$range_expf"
+range_exp2f="$range_expf"
+range_exp2f_1u="$range_expf"
+
+range_logf='
+ 0    0xffff0000    10000
+ 0x1p-4    0x1p4    500000
+'
+
+range_sinf='
+ 0    0xffff0000    10000
+ 0x1p-4    0x1p4    300000
+-0x1p-9   -0x1p9    300000
+'
+range_cosf="$range_sinf"
+
+range_powf='
+ 0x1p-1   0x1p1  x  0x1p-7 0x1p7   50000
+ 0x1p-1   0x1p1  x -0x1p-7 -0x1p7  50000
+ 0x1p-70 0x1p70  x  0x1p-1 0x1p1   50000
+ 0x1p-70 0x1p70  x  -0x1p-1 -0x1p1 50000
+ 0x1.ep-1 0x1.1p0 x  0x1p8 0x1p14  50000
+ 0x1.ep-1 0x1.1p0 x -0x1p8 -0x1p14 50000
+'
+
+# error limits
+L_exp=1.9
+L_log=1.2
+L_pow=0.05
+L_sin=3.0
+L_cos=3.0
+L_expf=1.49
+L_expf_1u=0.4
+L_exp2f=1.49
+L_exp2f_1u=0.4
+L_logf=2.9
+L_sinf=1.4
+L_cosf=1.4
+L_powf=2.1
+
+while read G F R
+do
+	[ "$R" = 1 ] || continue
+	case "$G" in \#*) continue ;; esac
+	eval range="\${range_$G}"
+	eval L="\${L_$G}"
+	while read X
+	do
+		[ -n "$X" ] || continue
+		case "$X" in \#*) continue ;; esac
+		t $F $X
+	done << EOF
+$range
+EOF
+done << EOF
+# group symbol run
+exp  __s_exp       $runs
+exp  __v_exp       $runv
+exp  __vn_exp      $runvn
+exp  _ZGVnN2v_exp  $runvn
+
+log  __s_log       $runs
+log  __v_log       $runv
+log  __vn_log      $runvn
+log  _ZGVnN2v_log  $runvn
+
+pow __s_pow       $runs
+pow __v_pow       $runv
+pow __vn_pow      $runvn
+pow _ZGVnN2vv_pow $runvn
+
+sin __s_sin       $runs
+sin __v_sin       $runv
+sin __vn_sin      $runvn
+sin _ZGVnN2v_sin  $runvn
+
+cos __s_cos       $runs
+cos __v_cos       $runv
+cos __vn_cos      $runvn
+cos _ZGVnN2v_cos  $runvn
+
+expf __s_expf      $runs
+expf __v_expf      $runv
+expf __vn_expf     $runvn
+expf _ZGVnN4v_expf $runvn
+
+expf_1u __s_expf_1u   $runs
+expf_1u __v_expf_1u   $runv
+expf_1u __vn_expf_1u  $runvn
+
+exp2f __s_exp2f      $runs
+exp2f __v_exp2f      $runv
+exp2f __vn_exp2f     $runvn
+exp2f _ZGVnN4v_exp2f $runvn
+
+exp2f_1u __s_exp2f_1u  $runs
+exp2f_1u __v_exp2f_1u  $runv
+exp2f_1u __vn_exp2f_1u $runvn
+
+logf __s_logf      $runs
+logf __v_logf      $runv
+logf __vn_logf     $runvn
+logf _ZGVnN4v_logf $runvn
+
+sinf __s_sinf      $runs
+sinf __v_sinf      $runv
+sinf __vn_sinf     $runvn
+sinf _ZGVnN4v_sinf $runvn
+
+cosf __s_cosf      $runs
+cosf __v_cosf      $runv
+cosf __vn_cosf     $runvn
+cosf _ZGVnN4v_cosf $runvn
+
+powf __s_powf       $runs
+powf __v_powf       $runv
+powf __vn_powf      $runvn
+powf _ZGVnN4vv_powf $runvn
+EOF
+
+[ 0 -eq $FAIL ] || {
+	echo "FAILED $FAIL PASSED $PASS"
+	exit 1
+}
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/cosf.tst b/libc/AOR_v20.02/math/test/testcases/directed/cosf.tst
new file mode 100644
index 0000000000000..8c7621a4550c6
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/cosf.tst
@@ -0,0 +1,26 @@
+; cosf.tst - Directed test cases for SP cosine
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=cosf op1=7fc00001 result=7fc00001 errno=0
+func=cosf op1=ffc00001 result=7fc00001 errno=0
+func=cosf op1=7f800001 result=7fc00001 errno=0 status=i
+func=cosf op1=ff800001 result=7fc00001 errno=0 status=i
+func=cosf op1=7f800000 result=7fc00001 errno=EDOM status=i
+func=cosf op1=ff800000 result=7fc00001 errno=EDOM status=i
+func=cosf op1=00000000 result=3f800000 errno=0
+func=cosf op1=80000000 result=3f800000 errno=0
+; SDCOMP-26094: check cosf in the cases for which the range reducer
+; returns values furthest beyond its nominal upper bound of pi/4.
+func=cosf op1=46427f1b result=3f34dc5c.565 error=0
+func=cosf op1=4647e568 result=3f34dc33.c1f error=0
+func=cosf op1=46428bac result=bf34dbf2.8e3 error=0
+func=cosf op1=4647f1f9 result=bf34dbc9.f9b error=0
+func=cosf op1=4647fe8a result=3f34db60.313 error=0
+func=cosf op1=45d8d7f1 result=bf35006a.7fd error=0
+func=cosf op1=45d371a4 result=3f350056.39b error=0
+func=cosf op1=45ce0b57 result=bf350041.f38 error=0
+func=cosf op1=45d35882 result=bf34ffec.868 error=0
+func=cosf op1=45cdf235 result=3f34ffd8.404 error=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/exp.tst b/libc/AOR_v20.02/math/test/testcases/directed/exp.tst
new file mode 100644
index 0000000000000..7c466d6b6ca9b
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/exp.tst
@@ -0,0 +1,32 @@
+; Directed test cases for exp
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=exp op1=7ff80000.00000001 result=7ff80000.00000001 errno=0
+func=exp op1=fff80000.00000001 result=7ff80000.00000001 errno=0
+func=exp op1=7ff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=exp op1=fff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=exp op1=7ff00000.00000000 result=7ff00000.00000000 errno=0
+func=exp op1=fff00000.00000000 result=00000000.00000000 errno=0
+func=exp op1=7fefffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=ox
+func=exp op1=ffefffff.ffffffff result=00000000.00000000 errno=ERANGE status=ux
+func=exp op1=00000000.00000000 result=3ff00000.00000000 errno=0
+func=exp op1=80000000.00000000 result=3ff00000.00000000 errno=0
+func=exp op1=00000000.00000001 result=3ff00000.00000000 errno=0
+func=exp op1=80000000.00000001 result=3ff00000.00000000 errno=0
+func=exp op1=3c900000.00000000 result=3ff00000.00000000.400 errno=0
+func=exp op1=bc900000.00000000 result=3fefffff.ffffffff.800 errno=0
+func=exp op1=3fe00000.00000000 result=3ffa6129.8e1e069b.c97 errno=0
+func=exp op1=bfe00000.00000000 result=3fe368b2.fc6f9609.fe8 errno=0
+func=exp op1=3ff00000.00000000 result=4005bf0a.8b145769.535 errno=0
+func=exp op1=bff00000.00000000 result=3fd78b56.362cef37.c6b errno=0
+func=exp op1=40000000.00000000 result=401d8e64.b8d4ddad.cc3 errno=0
+func=exp op1=c0000000.00000000 result=3fc152aa.a3bf81cb.9fe errno=0
+func=exp op1=3ff12345.6789abcd result=40075955.c34718ed.6e3 errno=0
+func=exp op1=40862e42.fefa39ef result=7fefffff.ffffff2a.1b1 errno=0
+func=exp op1=40862e42.fefa39f0 result=7ff00000.00000000 errno=ERANGE status=ox
+func=exp op1=c0874910.d52d3051 result=00000000.00000001 status=ux
+func=exp op1=c0874910.d52d3052 result=00000000.00000000 errno=ERANGE status=ux
+func=exp op1=c085d589.f2fe5107 result=00f00000.000000f1.46b errno=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/exp2.tst b/libc/AOR_v20.02/math/test/testcases/directed/exp2.tst
new file mode 100644
index 0000000000000..b8bcef0e7fcad
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/exp2.tst
@@ -0,0 +1,31 @@
+; Directed test cases for exp2
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=exp2 op1=7ff80000.00000001 result=7ff80000.00000001 errno=0
+func=exp2 op1=fff80000.00000001 result=7ff80000.00000001 errno=0
+func=exp2 op1=7ff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=exp2 op1=fff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=exp2 op1=7ff00000.00000000 result=7ff00000.00000000 errno=0
+func=exp2 op1=fff00000.00000000 result=00000000.00000000 errno=0
+func=exp2 op1=7fefffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=ox
+func=exp2 op1=ffefffff.ffffffff result=00000000.00000000 errno=ERANGE status=ux
+func=exp2 op1=00000000.00000000 result=3ff00000.00000000 errno=0
+func=exp2 op1=80000000.00000000 result=3ff00000.00000000 errno=0
+func=exp2 op1=00000000.00000001 result=3ff00000.00000000 errno=0
+func=exp2 op1=80000000.00000001 result=3ff00000.00000000 errno=0
+func=exp2 op1=3ca00000.00000000 result=3ff00000.00000000.58c errno=0
+func=exp2 op1=bc900000.00000000 result=3fefffff.ffffffff.a74 errno=0
+func=exp2 op1=3fe00000.00000000 result=3ff6a09e.667f3bcc.909 errno=0
+func=exp2 op1=bfe00000.00000000 result=3fe6a09e.667f3bcc.909 errno=0
+func=exp2 op1=3ff00000.00000000 result=40000000.00000000 errno=0
+func=exp2 op1=bff00000.00000000 result=3fe00000.00000000 errno=0
+func=exp2 op1=40000000.00000000 result=40100000.00000000 errno=0
+func=exp2 op1=c0000000.00000000 result=3fd00000.00000000 errno=0
+func=exp2 op1=3ff12345.6789abcd result=4000cef3.c5d12321.663 errno=0
+func=exp2 op1=408fffff.ffffffff result=7fefffff.fffffd3a.37a errno=0
+func=exp2 op1=40900000.00000000 result=7ff00000.00000000 errno=ERANGE status=ox
+func=exp2 op1=c090ca00.00000000 result=00000000.00000000.b50 status=ux
+func=exp2 op1=c090cc00.00000000 result=00000000.00000000 errno=ERANGE status=ux
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/exp2f.tst b/libc/AOR_v20.02/math/test/testcases/directed/exp2f.tst
new file mode 100644
index 0000000000000..2a7cc2b256b51
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/exp2f.tst
@@ -0,0 +1,26 @@
+; exp2f.tst - Directed test cases for exp2f
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=exp2f op1=7fc00001 result=7fc00001 errno=0
+func=exp2f op1=ffc00001 result=7fc00001 errno=0
+func=exp2f op1=7f800001 result=7fc00001 errno=0 status=i
+func=exp2f op1=ff800001 result=7fc00001 errno=0 status=i
+func=exp2f op1=7f800000 result=7f800000 errno=0
+func=exp2f op1=7f7fffff result=7f800000 errno=ERANGE status=ox
+func=exp2f op1=ff800000 result=00000000 errno=0
+func=exp2f op1=ff7fffff result=00000000 errno=ERANGE status=ux
+func=exp2f op1=00000000 result=3f800000 errno=0
+func=exp2f op1=80000000 result=3f800000 errno=0
+func=exp2f op1=42fa0001 result=7e00002c.5c8 errno=0
+func=exp2f op1=42ffffff result=7f7fffa7.470 errno=0
+func=exp2f op1=43000000 result=7f800000 errno=ERANGE status=ox
+func=exp2f op1=43000001 result=7f800000 errno=ERANGE status=ox
+func=exp2f op1=c2fa0001 result=00ffffa7.470 errno=0
+func=exp2f op1=c2fc0000 result=00800000 errno=0
+func=exp2f op1=c2fc0001 result=007fffd3.a38 errno=0 status=ux
+func=exp2f op1=c3150000 result=00000001 errno=0
+func=exp2f op1=c3158000 result=00000000.800 errno=ERANGE status=ux
+func=exp2f op1=c3165432 result=00000000.4bd errno=ERANGE status=ux
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/expf.tst b/libc/AOR_v20.02/math/test/testcases/directed/expf.tst
new file mode 100644
index 0000000000000..13ce50418f668
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/expf.tst
@@ -0,0 +1,24 @@
+; expf.tst - Directed test cases for expf
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=expf op1=7fc00001 result=7fc00001 errno=0
+func=expf op1=ffc00001 result=7fc00001 errno=0
+func=expf op1=7f800001 result=7fc00001 errno=0 status=i
+func=expf op1=ff800001 result=7fc00001 errno=0 status=i
+func=expf op1=7f800000 result=7f800000 errno=0
+func=expf op1=7f7fffff result=7f800000 errno=ERANGE status=ox
+func=expf op1=ff800000 result=00000000 errno=0
+func=expf op1=ff7fffff result=00000000 errno=ERANGE status=ux
+func=expf op1=00000000 result=3f800000 errno=0
+func=expf op1=80000000 result=3f800000 errno=0
+func=expf op1=42affff8 result=7ef87ed4.e0c errno=0
+func=expf op1=42b00008 result=7ef88698.f67 errno=0
+func=expf op1=42cffff8 result=7f800000 errno=ERANGE status=ox
+func=expf op1=42d00008 result=7f800000 errno=ERANGE status=ox
+func=expf op1=c2affff8 result=0041eecc.041 errno=0 status=ux
+func=expf op1=c2b00008 result=0041ecbc.95e errno=0 status=ux
+func=expf op1=c2cffff8 result=00000000 errno=ERANGE status=ux
+func=expf op1=c2d00008 result=00000000 errno=ERANGE status=ux
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/log.tst b/libc/AOR_v20.02/math/test/testcases/directed/log.tst
new file mode 100644
index 0000000000000..f0cb8008a121a
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/log.tst
@@ -0,0 +1,22 @@
+; Directed test cases for log
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=log op1=7ff80000.00000001 result=7ff80000.00000001 errno=0
+func=log op1=fff80000.00000001 result=7ff80000.00000001 errno=0
+func=log op1=7ff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=log op1=fff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=log op1=7ff00000.00000000 result=7ff00000.00000000 errno=0
+func=log op1=fff00000.00000000 result=7ff80000.00000001 errno=EDOM status=i
+func=log op1=7fefffff.ffffffff result=40862e42.fefa39ef.354 errno=0
+func=log op1=ffefffff.ffffffff result=7ff80000.00000001 errno=EDOM status=i
+func=log op1=3ff00000.00000000 result=00000000.00000000 errno=0
+func=log op1=bff00000.00000000 result=7ff80000.00000001 errno=EDOM status=i
+func=log op1=00000000.00000000 result=fff00000.00000000 errno=ERANGE status=z
+func=log op1=80000000.00000000 result=fff00000.00000000 errno=ERANGE status=z
+func=log op1=00000000.00000001 result=c0874385.446d71c3.639 errno=0
+func=log op1=80000000.00000001 result=7ff80000.00000001 errno=EDOM status=i
+func=log op1=40000000.00000000 result=3fe62e42.fefa39ef.358 errno=0
+func=log op1=3fe00000.00000000 result=bfe62e42.fefa39ef.358 errno=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/log2.tst b/libc/AOR_v20.02/math/test/testcases/directed/log2.tst
new file mode 100644
index 0000000000000..702f2779b400c
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/log2.tst
@@ -0,0 +1,22 @@
+; Directed test cases for log2
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=log2 op1=7ff80000.00000001 result=7ff80000.00000001 errno=0
+func=log2 op1=fff80000.00000001 result=7ff80000.00000001 errno=0
+func=log2 op1=7ff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=log2 op1=fff00000.00000001 result=7ff80000.00000001 errno=0 status=i
+func=log2 op1=7ff00000.00000000 result=7ff00000.00000000 errno=0
+func=log2 op1=fff00000.00000000 result=7ff80000.00000001 errno=EDOM status=i
+func=log2 op1=7fefffff.ffffffff result=408fffff.ffffffff.ffa errno=0
+func=log2 op1=ffefffff.ffffffff result=7ff80000.00000001 errno=EDOM status=i
+func=log2 op1=3ff00000.00000000 result=00000000.00000000 errno=0
+func=log2 op1=bff00000.00000000 result=7ff80000.00000001 errno=EDOM status=i
+func=log2 op1=00000000.00000000 result=fff00000.00000000 errno=ERANGE status=z
+func=log2 op1=80000000.00000000 result=fff00000.00000000 errno=ERANGE status=z
+func=log2 op1=00000000.00000001 result=c090c800.00000000 errno=0
+func=log2 op1=80000000.00000001 result=7ff80000.00000001 errno=EDOM status=i
+func=log2 op1=40000000.00000000 result=3ff00000.00000000 errno=0
+func=log2 op1=3fe00000.00000000 result=bff00000.00000000 errno=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/log2f.tst b/libc/AOR_v20.02/math/test/testcases/directed/log2f.tst
new file mode 100644
index 0000000000000..2f1a01e93ee99
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/log2f.tst
@@ -0,0 +1,28 @@
+; log2f.tst - Directed test cases for log2f
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=log2f op1=7fc00001 result=7fc00001 errno=0
+func=log2f op1=ffc00001 result=7fc00001 errno=0
+func=log2f op1=7f800001 result=7fc00001 errno=0 status=i
+func=log2f op1=ff800001 result=7fc00001 errno=0 status=i
+func=log2f op1=ff810000 result=7fc00001 errno=0 status=i
+func=log2f op1=7f800000 result=7f800000 errno=0
+func=log2f op1=ff800000 result=7fc00001 errno=EDOM status=i
+func=log2f op1=3f800000 result=00000000 errno=0
+func=log2f op1=00000000 result=ff800000 errno=ERANGE status=z
+func=log2f op1=80000000 result=ff800000 errno=ERANGE status=z
+func=log2f op1=80000001 result=7fc00001 errno=EDOM status=i
+
+func=log2f op1=3f7d70a4 result=bc6d8f8b.7d4 error=0
+func=log2f op1=3f604189 result=be4394c8.395 error=0
+func=log2f op1=3f278034 result=bf1caa73.88e error=0
+func=log2f op1=3edd3c36 result=bf9af3b9.619 error=0
+func=log2f op1=3e61259a result=c00bdb95.650 error=0
+func=log2f op1=3f8147ae result=3c6b3267.d6a error=0
+func=log2f op1=3f8fbe77 result=3e2b5fe2.a1c error=0
+func=log2f op1=3fac3eea result=3edb4d5e.1fc error=0
+func=log2f op1=3fd6e632 result=3f3f5d3a.827 error=0
+func=log2f op1=40070838 result=3f89e055.a0a error=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/logf.tst b/libc/AOR_v20.02/math/test/testcases/directed/logf.tst
new file mode 100644
index 0000000000000..d19cc154f363a
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/logf.tst
@@ -0,0 +1,70 @@
+; logf.tst - Directed test cases for logf
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=logf op1=7fc00001 result=7fc00001 errno=0
+func=logf op1=ffc00001 result=7fc00001 errno=0
+func=logf op1=7f800001 result=7fc00001 errno=0 status=i
+func=logf op1=ff800001 result=7fc00001 errno=0 status=i
+func=logf op1=ff810000 result=7fc00001 errno=0 status=i
+func=logf op1=7f800000 result=7f800000 errno=0
+func=logf op1=ff800000 result=7fc00001 errno=EDOM status=i
+func=logf op1=3f800000 result=00000000 errno=0
+func=logf op1=00000000 result=ff800000 errno=ERANGE status=z
+func=logf op1=80000000 result=ff800000 errno=ERANGE status=z
+func=logf op1=80000001 result=7fc00001 errno=EDOM status=i
+
+; Directed tests for the special-case handling of log of things
+; very near 1
+func=logf op1=3f781e49 result=bd0016d9.4ae error=0
+func=logf op1=3f78e602 result=bce675e5.f31 error=0
+func=logf op1=3f844a18 result=3d07030e.ae1 error=0
+func=logf op1=3f79b55b result=bccbd88a.6cb error=0
+func=logf op1=3f7e2f5f result=bbe92452.74a error=0
+func=logf op1=3f7f1c03 result=bb6462c1.c2c error=0
+func=logf op1=3f78b213 result=bced23e2.f56 error=0
+func=logf op1=3f87d5c0 result=3d735847.b7a error=0
+func=logf op1=3f7fa6ad result=bab2c532.12d error=0
+func=logf op1=3f87c06a result=3d70d4b6.b5e error=0
+func=logf op1=3f79cf30 result=bcc88942.6e9 error=0
+func=logf op1=3f794c77 result=bcd94c6f.b1e error=0
+func=logf op1=3f835655 result=3cd2d8a0.0bf error=0
+func=logf op1=3f81b5c0 result=3c596d08.520 error=0
+func=logf op1=3f805e2f result=3b3c18d4.d2b error=0
+func=logf op1=3f7aa609 result=bcad0f90.fdb error=0
+func=logf op1=3f7a9091 result=bcafcd59.f83 error=0
+func=logf op1=3f7a7475 result=bcb36490.a0f error=0
+func=logf op1=3f823417 result=3c8bd287.fa6 error=0
+func=logf op1=3f7fbcc3 result=ba868bac.14c error=0
+func=logf op1=3f805fc9 result=3b3f4a76.169 error=0
+func=logf op1=3f833d43 result=3cccbc4f.cb7 error=0
+func=logf op1=3f7cb1de result=bc54e91e.6b5 error=0
+func=logf op1=3f7f2793 result=bb58c8af.bfc error=0
+func=logf op1=3f7bb8c3 result=bc8a0fc9.93c error=0
+func=logf op1=3f81d349 result=3c67fe09.42e error=0
+func=logf op1=3f7c254d result=bc788cf4.610 error=0
+func=logf op1=3f7f789d result=bb0786d9.6c6 error=0
+func=logf op1=3f7ed1f2 result=bb97605f.963 error=0
+func=logf op1=3f826067 result=3c96b4af.5e1 error=0
+func=logf op1=3f821a68 result=3c8581f9.dac error=0
+func=logf op1=3f864e1a result=3d44f368.e66 error=0
+func=logf op1=3f7fea3d result=b9ae1f66.b58 error=0
+func=logf op1=3f7cf4f5 result=bc43ed76.1c5 error=0
+func=logf op1=3f84c223 result=3d15814e.36d error=0
+func=logf op1=3f7dae6d result=bc1511d5.0aa error=0
+func=logf op1=3f7c0a3c result=bc7f6c0d.758 error=0
+func=logf op1=3f858b22 result=3d2da861.f36 error=0
+func=logf op1=3f85d7c7 result=3d36d490.ee9 error=0
+func=logf op1=3f7f2109 result=bb5f5851.2ed error=0
+func=logf op1=3f83809c result=3cdd23f7.6b1 error=0
+func=logf op1=3f83d96e result=3cf2b9c8.0b1 error=0
+func=logf op1=3f86ca84 result=3d53bee8.53f error=0
+func=logf op1=3f83548e result=3cd269c3.39d error=0
+func=logf op1=3f7c199c result=bc7b84b6.0da error=0
+func=logf op1=3f83133f result=3cc27c0a.9dd error=0
+func=logf op1=3f7c97b4 result=bc5b89dd.399 error=0
+func=logf op1=3f810bc1 result=3c05553c.011 error=0
+func=logf op1=3f7dadb8 result=bc153f7e.fbb error=0
+func=logf op1=3f87be56 result=3d709602.538 error=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/pow.tst b/libc/AOR_v20.02/math/test/testcases/directed/pow.tst
new file mode 100644
index 0000000000000..474cc377e5f05
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/pow.tst
@@ -0,0 +1,1419 @@
+; Directed test cases for pow
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=pow op1=00000000.00000000 op2=00000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=00000000.00000001 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=00100000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=1fffffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=3bdfffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=3be00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=3fe00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=3ff00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=40000000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=40080000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=40120000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=40180000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=407ff800.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=408ff800.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=43dfffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=43e00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=7fefffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=7ff00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=7ff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=00000000.00000000 op2=7ff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=80000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=80000000.00000001 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=80100000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=9fffffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=bbdfffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=bbe00000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=bfe00000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=bff00000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c0000000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c0080000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c0120000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c0180000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c07f3000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c090ce00.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c3dfffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=c3e00000.00000000 result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=ffefffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=z
+func=pow op1=00000000.00000000 op2=fff00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=00000000.00000000 op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=00000000.00000000 op2=fff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=00000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=00000000.00000001 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=00100000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=1fffffff.ffffffff result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=3bdfffff.ffffffff result=3fefffff.ffffffff.d17 errno=0
+func=pow op1=00000000.00000001 op2=3be00000.00000000 result=3fefffff.ffffffff.d17 errno=0
+func=pow op1=00000000.00000001 op2=3fe00000.00000000 result=1e600000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=3ff00000.00000000 result=00000000.00000001 errno=0 status=u
+func=pow op1=00000000.00000001 op2=40000000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=40080000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=40120000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=40180000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=407ff800.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=408ff800.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=43dfffff.ffffffff result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=43e00000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=7fefffff.ffffffff result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=00000000.00000001 op2=7ff00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=7ff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=00000000.00000001 op2=7ff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=80000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=80000000.00000001 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=80100000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=9fffffff.ffffffff result=3ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=bbdfffff.ffffffff result=3ff00000.00000000.174 errno=0
+func=pow op1=00000000.00000001 op2=bbe00000.00000000 result=3ff00000.00000000.174 errno=0
+func=pow op1=00000000.00000001 op2=bfe00000.00000000 result=61800000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=bff00000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c0000000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c0080000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c0120000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c0180000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c07f3000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c090ce00.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c3dfffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=c3e00000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=ffefffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=00000000.00000001 op2=fff00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=00000000.00000001 op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
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+func=pow op1=c0180000.00000000 op2=c3e00000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=c0180000.00000000 op2=ffefffff.ffffffff result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=c0180000.00000000 op2=fff00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=c0180000.00000000 op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=c0180000.00000000 op2=fff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=ffefffff.ffffffff op2=00000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=ffefffff.ffffffff op2=00000000.00000001 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=00100000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=1fffffff.ffffffff result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=3bdfffff.ffffffff result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=3be00000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=3fe00000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=3ff00000.00000000 result=ffefffff.ffffffff errno=0
+func=pow op1=ffefffff.ffffffff op2=40000000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=40080000.00000000 result=fff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=40120000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=40180000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=407ff800.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=408ff800.00000000 result=fff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=43dfffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=43e00000.00000000 result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=7fefffff.ffffffff result=7ff00000.00000000 errno=ERANGE status=o
+func=pow op1=ffefffff.ffffffff op2=7ff00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=ffefffff.ffffffff op2=7ff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=ffefffff.ffffffff op2=7ff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=ffefffff.ffffffff op2=80000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=ffefffff.ffffffff op2=80000000.00000001 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=80100000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=9fffffff.ffffffff result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=bbdfffff.ffffffff result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=bbe00000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=bfe00000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=bff00000.00000000 result=80040000.00000000.200 errno=0 status=u
+func=pow op1=ffefffff.ffffffff op2=c0000000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=c0080000.00000000 result=80000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=c0120000.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=c0180000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=c07f3000.00000000 result=80000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=c090ce00.00000000 result=7ff80000.00000000 errno=EDOM status=i
+func=pow op1=ffefffff.ffffffff op2=c3dfffff.ffffffff result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=c3e00000.00000000 result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=ffefffff.ffffffff result=00000000.00000000 errno=ERANGE status=u
+func=pow op1=ffefffff.ffffffff op2=fff00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=ffefffff.ffffffff op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=ffefffff.ffffffff op2=fff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=00000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=00000000.00000001 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=00100000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=1fffffff.ffffffff result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=3bdfffff.ffffffff result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=3be00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=3fe00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=3ff00000.00000000 result=fff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=40000000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=40080000.00000000 result=fff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=40120000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=40180000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=407ff800.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=408ff800.00000000 result=fff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=43dfffff.ffffffff result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=43e00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=7fefffff.ffffffff result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=7ff00000.00000000 result=7ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=7ff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000000 op2=7ff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=80000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=80000000.00000001 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=80100000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=9fffffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=bbdfffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=bbe00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=bfe00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=bff00000.00000000 result=80000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c0000000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c0080000.00000000 result=80000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c0120000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c0180000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c07f3000.00000000 result=80000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c090ce00.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c3dfffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=c3e00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=ffefffff.ffffffff result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=fff00000.00000000 result=00000000.00000000 errno=0
+func=pow op1=fff00000.00000000 op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000000 op2=fff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=fff00000.00000001 op2=00000000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=00000000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=00100000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=1fffffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=3bdfffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=3be00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=3fe00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=3ff00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=40000000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=40080000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=40120000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=40180000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=407ff800.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=408ff800.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=43dfffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=43e00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=7fefffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=7ff00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=7ff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=7ff80000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=80000000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=80000000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=80100000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=9fffffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=bbdfffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=bbe00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=bfe00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=bff00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c0000000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c0080000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c0120000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c0180000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c07f3000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c090ce00.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c3dfffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=c3e00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=ffefffff.ffffffff result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=fff00000.00000000 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff00000.00000001 op2=fff80000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff80000.00000001 op2=00000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=00000000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=00100000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=1fffffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=3bdfffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=3be00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=3fe00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=3ff00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=40000000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=40080000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=40120000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=40180000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=407ff800.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=408ff800.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=43dfffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=43e00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=7fefffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=7ff00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=7ff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff80000.00000001 op2=7ff80000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=80000000.00000000 result=3ff00000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=80000000.00000001 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=80100000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=9fffffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=bbdfffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=bbe00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=bfe00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=bff00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c0000000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c0080000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c0120000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c0180000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c07f3000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c090ce00.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c3dfffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=c3e00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=ffefffff.ffffffff result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=fff00000.00000000 result=7ff80000.00000000 errno=0
+func=pow op1=fff80000.00000001 op2=fff00000.00000001 result=7ff80000.00000000 errno=0 status=i
+func=pow op1=fff80000.00000001 op2=fff80000.00000001 result=7ff80000.00000000 errno=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/powf.tst b/libc/AOR_v20.02/math/test/testcases/directed/powf.tst
new file mode 100644
index 0000000000000..9719b1f991ed9
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/powf.tst
@@ -0,0 +1,247 @@
+; powf.tst - Directed test cases for powf
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+func=powf op1=7f800001 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=7fc00001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=ffc00001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=7f800000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=40800000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=40400000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=3f000000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=00000000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=80000000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=bf000000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=c0400000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=c0800000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=ff800000 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800001 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=7fc00001 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=ffc00001 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=7f800000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=40800000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=40400000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=3f000000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=00000000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=80000000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=bf000000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=c0400000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=c0800000 result=7fc00001 errno=0 status=i
+func=powf op1=ff800001 op2=ff800000 result=7fc00001 errno=0 status=i
+func=powf op1=7fc00001 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=7fc00001 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=7fc00001 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=7f800000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=40800000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=40400000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=3f000000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=00000000 result=3f800000 errno=0
+func=powf op1=7fc00001 op2=80000000 result=3f800000 errno=0
+func=powf op1=7fc00001 op2=bf000000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=c0400000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=c0800000 result=7fc00001 errno=0
+func=powf op1=7fc00001 op2=ff800000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=ffc00001 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=ffc00001 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=7f800000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=40800000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=40400000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=3f000000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=00000000 result=3f800000 errno=0
+func=powf op1=ffc00001 op2=80000000 result=3f800000 errno=0
+func=powf op1=ffc00001 op2=bf000000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=c0400000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=c0800000 result=7fc00001 errno=0
+func=powf op1=ffc00001 op2=ff800000 result=7fc00001 errno=0
+func=powf op1=7f800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=7f800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=7f800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=7f800000 op2=7f800000 result=7f800000 errno=0
+func=powf op1=7f800000 op2=40800000 result=7f800000 errno=0
+func=powf op1=7f800000 op2=40400000 result=7f800000 errno=0
+func=powf op1=7f800000 op2=3f000000 result=7f800000 errno=0
+func=powf op1=7f800000 op2=00000001 result=7f800000 errno=0
+func=powf op1=7f800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=7f800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=7f800000 op2=bf000000 result=00000000 errno=0
+func=powf op1=7f800000 op2=c0400000 result=00000000 errno=0
+func=powf op1=7f800000 op2=c0800000 result=00000000 errno=0
+func=powf op1=7f800000 op2=ff800000 result=00000000 errno=0
+func=powf op1=40800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=40800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=40800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=40800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=40800000 op2=7f800000 result=7f800000 errno=0
+func=powf op1=40800000 op2=40800000 result=43800000 errno=0
+func=powf op1=40800000 op2=40400000 result=42800000 errno=0
+func=powf op1=40800000 op2=3f000000 result=40000000 errno=0
+func=powf op1=40800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=40800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=40800000 op2=bf000000 result=3f000000 errno=0
+func=powf op1=40800000 op2=c0400000 result=3c800000 errno=0
+func=powf op1=40800000 op2=c0800000 result=3b800000 errno=0
+func=powf op1=40800000 op2=ff800000 result=00000000 errno=0
+func=powf op1=3f800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=3f800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=3f800000 op2=7fc00001 result=3f800000 errno=0
+func=powf op1=3f800000 op2=ffc00001 result=3f800000 errno=0
+func=powf op1=3f800000 op2=7f800000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=40800000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=40400000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=3f000000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=bf000000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=c0400000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=c0800000 result=3f800000 errno=0
+func=powf op1=3f800000 op2=ff800000 result=3f800000 errno=0
+func=powf op1=3e800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=3e800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=3e800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=3e800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=3e800000 op2=7f800000 result=00000000 errno=0
+func=powf op1=3e800000 op2=40800000 result=3b800000 errno=0
+func=powf op1=3e800000 op2=40400000 result=3c800000 errno=0
+func=powf op1=3e800000 op2=3f000000 result=3f000000 errno=0
+func=powf op1=3e800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=3e800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=3e800000 op2=bf000000 result=40000000 errno=0
+func=powf op1=3e800000 op2=c0400000 result=42800000 errno=0
+func=powf op1=3e800000 op2=c0800000 result=43800000 errno=0
+func=powf op1=3e800000 op2=ff800000 result=7f800000 errno=0
+func=powf op1=00000001 op2=bf800000 result=7f800000 errno=ERANGE status=ox
+func=powf op1=00000000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=00000000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=00000000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=00000000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=00000000 op2=7f800000 result=00000000 errno=0
+func=powf op1=00000000 op2=40800000 result=00000000 errno=0
+func=powf op1=00000000 op2=40400000 result=00000000 errno=0
+func=powf op1=00000000 op2=3f000000 result=00000000 errno=0
+func=powf op1=00000000 op2=00000000 result=3f800000 errno=0
+func=powf op1=00000000 op2=80000000 result=3f800000 errno=0
+func=powf op1=00000000 op2=bf000000 result=7f800000 errno=ERANGE status=z
+func=powf op1=00000000 op2=c0400000 result=7f800000 errno=ERANGE status=z
+func=powf op1=00000000 op2=c0800000 result=7f800000 errno=ERANGE status=z
+func=powf op1=00000000 op2=ff800000 result=7f800000 errno=ERANGE
+func=powf op1=80000000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=80000000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=80000000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=80000000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=80000000 op2=7f800000 result=00000000 errno=0
+func=powf op1=80000000 op2=40800000 result=00000000 errno=0
+func=powf op1=80000000 op2=40400000 result=80000000 errno=0
+func=powf op1=80000000 op2=3f000000 result=00000000 errno=0
+func=powf op1=80000000 op2=00000000 result=3f800000 errno=0
+func=powf op1=80000000 op2=80000000 result=3f800000 errno=0
+func=powf op1=80000000 op2=bf000000 result=7f800000 errno=ERANGE status=z
+func=powf op1=80000000 op2=c0400000 result=ff800000 errno=ERANGE status=z
+func=powf op1=80000000 op2=c0800000 result=7f800000 errno=ERANGE status=z
+func=powf op1=80000000 op2=ff800000 result=7f800000 errno=ERANGE
+func=powf op1=be800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=be800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=be800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=be800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=be800000 op2=7f800000 result=00000000 errno=0
+func=powf op1=be800000 op2=40800000 result=3b800000 errno=0
+func=powf op1=be800000 op2=40400000 result=bc800000 errno=0
+func=powf op1=be800000 op2=3f000000 result=7fc00001 errno=EDOM status=i
+func=powf op1=be800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=be800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=be800000 op2=bf000000 result=7fc00001 errno=EDOM status=i
+func=powf op1=be800000 op2=c0400000 result=c2800000 errno=0
+func=powf op1=be800000 op2=c0800000 result=43800000 errno=0
+func=powf op1=be800000 op2=ff800000 result=7f800000 errno=0
+func=powf op1=bf800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=bf800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=bf800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=bf800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=bf800000 op2=7f800000 result=3f800000 errno=0
+func=powf op1=bf800000 op2=40800000 result=3f800000 errno=0
+func=powf op1=bf800000 op2=40400000 result=bf800000 errno=0
+func=powf op1=bf800000 op2=3f000000 result=7fc00001 errno=EDOM status=i
+func=powf op1=bf800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=bf800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=bf800000 op2=bf000000 result=7fc00001 errno=EDOM status=i
+func=powf op1=bf800000 op2=c0400000 result=bf800000 errno=0
+func=powf op1=bf800000 op2=c0800000 result=3f800000 errno=0
+func=powf op1=bf800000 op2=ff800000 result=3f800000 errno=0
+func=powf op1=c0800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=c0800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=c0800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=c0800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=c0800000 op2=7f800000 result=7f800000 errno=0
+func=powf op1=c0800000 op2=40800000 result=43800000 errno=0
+func=powf op1=c0800000 op2=40400000 result=c2800000 errno=0
+func=powf op1=c0800000 op2=3f000000 result=7fc00001 errno=EDOM status=i
+func=powf op1=c0800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=c0800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=c0800000 op2=bf000000 result=7fc00001 errno=EDOM status=i
+func=powf op1=c0800000 op2=c0400000 result=bc800000 errno=0
+func=powf op1=c0800000 op2=c0800000 result=3b800000 errno=0
+func=powf op1=c0800000 op2=ff800000 result=00000000 errno=0
+func=powf op1=ff800000 op2=7f800001 result=7fc00001 errno=0 status=i
+func=powf op1=ff800000 op2=ff800001 result=7fc00001 errno=0 status=i
+func=powf op1=ff800000 op2=7fc00001 result=7fc00001 errno=0
+func=powf op1=ff800000 op2=ffc00001 result=7fc00001 errno=0
+func=powf op1=ff800000 op2=7f800000 result=7f800000 errno=0
+func=powf op1=ff800000 op2=40800000 result=7f800000 errno=0
+func=powf op1=ff800000 op2=40400000 result=ff800000 errno=0
+func=powf op1=ff800000 op2=3f000000 result=7f800000 errno=0
+func=powf op1=ff800000 op2=00000000 result=3f800000 errno=0
+func=powf op1=ff800000 op2=80000000 result=3f800000 errno=0
+func=powf op1=ff800000 op2=bf000000 result=00000000 errno=0
+func=powf op1=ff800000 op2=c0400000 result=80000000 errno=0
+func=powf op1=ff800000 op2=c0800000 result=00000000 errno=0
+func=powf op1=ff800000 op2=ff800000 result=00000000 errno=0
+
+
+func=powf op1=36c27f9d op2=4109fa51 result=00000000 errno=ERANGE status=ux
+func=powf op1=351738cd op2=c0c55691 result=7f800000 errno=ERANGE status=ox
+func=powf op1=42836035 op2=41a99f40 result=7f800000 errno=ERANGE status=ox
+func=powf op1=32bd53f3 op2=40bcba58 result=00000000 errno=ERANGE status=ux
+func=powf op1=32dc5bff op2=40be62ea result=00000000 errno=ERANGE status=ux
+func=powf op1=3a8a3f66 op2=4172bd43 result=00000000 errno=ERANGE status=ux
+func=powf op1=28f0e770 op2=c035b4ca result=7f800000 errno=ERANGE status=ox
+func=powf op1=40886699 op2=c28f703a result=00000000 errno=ERANGE status=ux
+func=powf op1=414bd593 op2=c22370cf result=00000000 errno=ERANGE status=ux
+func=powf op1=3a2f1163 op2=c1422d45 result=7f800000 errno=ERANGE status=ox
+func=powf op1=434f5cf3 op2=41851272 result=7f800000 errno=ERANGE status=ox
+func=powf op1=2e0e27a4 op2=c06b13f5 result=7f800000 errno=ERANGE status=ox
+func=powf op1=39aef7a6 op2=414fd60a result=00000000 errno=ERANGE status=ux
+func=powf op1=21c80729 op2=c00a04ab result=7f800000 errno=ERANGE status=ox
+func=powf op1=42455a4b op2=c1d55905 result=00000000 errno=ERANGE status=ux
+func=powf op1=2d173e0b op2=c05ee797 result=7f800000 errno=ERANGE status=ox
+func=powf op1=452edf9a op2=4132dd7f result=7f800000 errno=ERANGE status=ox
+func=powf op1=406bf67b op2=c29f5f12 result=00000000 errno=ERANGE status=ux
+func=powf op1=2d82a6fc op2=4085779e result=00000000 errno=ERANGE status=ux
+func=powf op1=4551f827 op2=41304516 result=7f800000 errno=ERANGE status=ox
+func=powf op1=3a917c51 op2=41726c0a result=00000001.37f errno=0 status=ux
+; iso c allows both errno=ERANGE and errno=0
+;func=powf op1=3b19bbaa op2=4188e6fb result=00000000.b5f errno=0 status=ux
+;func=powf op1=4088bd18 op2=c28ef056 result=00000000.986 errno=0 status=ux
+func=powf op1=3f7ffd76 op2=4a09221e result=00aa9d24.3ad error=0
+
+func=powf op1=007fffff op2=bf000001 result=5f00002c.2b2 error=0
+func=powf op1=000007ff op2=bf000001 result=62000830.96f error=0
+func=powf op1=007fffff op2=80800001 result=3f800000.000 error=0
+func=powf op1=00000000 op2=800007ff result=7f800000 errno=ERANGE status=z
+func=powf op1=00000000 op2=000007ff result=00000000 error=0
+func=powf op1=bf800000 op2=ff7fffff result=3f800000 error=0
+func=powf op1=2e4e4f30 op2=406b0dc2 result=007e9c59.eb4 errno=0 status=u
+
+; SDCOMP-25549: ensure the biggest overflow case possible is not
+; mishandled. Also check the analogous underflow, and also ensure that
+; our massive-overflow checks do not affect numbers _just within_ the
+; range.
+func=powf op1=7f7fffff op2=7f7fffff result=7f800000 error=overflow
+func=powf op1=7f7fffff op2=ff7fffff result=00000000 error=underflow
+func=powf op1=54cb3000 op2=403fffff result=7f7fffb2.a95 error=0
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/sincosf.tst b/libc/AOR_v20.02/math/test/testcases/directed/sincosf.tst
new file mode 100644
index 0000000000000..d22fd98026940
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/sincosf.tst
@@ -0,0 +1,52 @@
+; Directed test cases for SP sincos
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+
+func=sincosf_sinf op1=7fc00001 result=7fc00001 errno=0
+func=sincosf_sinf op1=ffc00001 result=7fc00001 errno=0
+func=sincosf_sinf op1=7f800001 result=7fc00001 errno=0 status=i
+func=sincosf_sinf op1=ff800001 result=7fc00001 errno=0 status=i
+func=sincosf_sinf op1=7f800000 result=7fc00001 errno=EDOM status=i
+func=sincosf_sinf op1=ff800000 result=7fc00001 errno=EDOM status=i
+func=sincosf_sinf op1=00000000 result=00000000 errno=0
+func=sincosf_sinf op1=80000000 result=80000000 errno=0
+func=sincosf_sinf op1=c70d39a1 result=be37fad5.7ed errno=0
+func=sincosf_sinf op1=46427f1b result=3f352d80.f9b error=0
+func=sincosf_sinf op1=4647e568 result=3f352da9.7be error=0
+func=sincosf_sinf op1=46428bac result=bf352dea.924 error=0
+func=sincosf_sinf op1=4647f1f9 result=bf352e13.146 error=0
+func=sincosf_sinf op1=4647fe8a result=3f352e7c.ac9 error=0
+func=sincosf_sinf op1=45d8d7f1 result=3f35097b.cb0 error=0
+func=sincosf_sinf op1=45d371a4 result=bf350990.102 error=0
+func=sincosf_sinf op1=45ce0b57 result=3f3509a4.554 error=0
+func=sincosf_sinf op1=45d35882 result=3f3509f9.bdb error=0
+func=sincosf_sinf op1=45cdf235 result=bf350a0e.02c error=0
+
+func=sincosf_cosf op1=7fc00001 result=7fc00001 errno=0
+func=sincosf_cosf op1=ffc00001 result=7fc00001 errno=0
+func=sincosf_cosf op1=7f800001 result=7fc00001 errno=0 status=i
+func=sincosf_cosf op1=ff800001 result=7fc00001 errno=0 status=i
+func=sincosf_cosf op1=7f800000 result=7fc00001 errno=EDOM status=i
+func=sincosf_cosf op1=ff800000 result=7fc00001 errno=EDOM status=i
+func=sincosf_cosf op1=00000000 result=3f800000 errno=0
+func=sincosf_cosf op1=80000000 result=3f800000 errno=0
+func=sincosf_cosf op1=46427f1b result=3f34dc5c.565 error=0
+func=sincosf_cosf op1=4647e568 result=3f34dc33.c1f error=0
+func=sincosf_cosf op1=46428bac result=bf34dbf2.8e3 error=0
+func=sincosf_cosf op1=4647f1f9 result=bf34dbc9.f9b error=0
+func=sincosf_cosf op1=4647fe8a result=3f34db60.313 error=0
+func=sincosf_cosf op1=45d8d7f1 result=bf35006a.7fd error=0
+func=sincosf_cosf op1=45d371a4 result=3f350056.39b error=0
+func=sincosf_cosf op1=45ce0b57 result=bf350041.f38 error=0
+func=sincosf_cosf op1=45d35882 result=bf34ffec.868 error=0
+func=sincosf_cosf op1=45cdf235 result=3f34ffd8.404 error=0
+
+; no underflow
+func=sincosf_sinf op1=17800000 result=17800000.000
+func=sincosf_cosf op1=17800000 result=3f800000.000
+; underflow
+func=sincosf_sinf op1=00400000 result=00400000.000 status=ux
+func=sincosf_cosf op1=00400000 result=3f800000.000 status=ux
diff --git a/libc/AOR_v20.02/math/test/testcases/directed/sinf.tst b/libc/AOR_v20.02/math/test/testcases/directed/sinf.tst
new file mode 100644
index 0000000000000..022bf14248790
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/directed/sinf.tst
@@ -0,0 +1,29 @@
+; sinf.tst - Directed test cases for SP sine
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+
+func=sinf op1=7fc00001 result=7fc00001 errno=0
+func=sinf op1=ffc00001 result=7fc00001 errno=0
+func=sinf op1=7f800001 result=7fc00001 errno=0 status=i
+func=sinf op1=ff800001 result=7fc00001 errno=0 status=i
+func=sinf op1=7f800000 result=7fc00001 errno=EDOM status=i
+func=sinf op1=ff800000 result=7fc00001 errno=EDOM status=i
+func=sinf op1=00000000 result=00000000 errno=0
+func=sinf op1=80000000 result=80000000 errno=0
+; Directed test for a failure I found while developing mathbench
+func=sinf op1=c70d39a1 result=be37fad5.7ed errno=0
+; SDCOMP-26094: check sinf in the cases for which the range reducer
+; returns values furthest beyond its nominal upper bound of pi/4.
+func=sinf op1=46427f1b result=3f352d80.f9b error=0
+func=sinf op1=4647e568 result=3f352da9.7be error=0
+func=sinf op1=46428bac result=bf352dea.924 error=0
+func=sinf op1=4647f1f9 result=bf352e13.146 error=0
+func=sinf op1=4647fe8a result=3f352e7c.ac9 error=0
+func=sinf op1=45d8d7f1 result=3f35097b.cb0 error=0
+func=sinf op1=45d371a4 result=bf350990.102 error=0
+func=sinf op1=45ce0b57 result=3f3509a4.554 error=0
+func=sinf op1=45d35882 result=3f3509f9.bdb error=0
+func=sinf op1=45cdf235 result=bf350a0e.02c error=0
diff --git a/libc/AOR_v20.02/math/test/testcases/random/double.tst b/libc/AOR_v20.02/math/test/testcases/random/double.tst
new file mode 100644
index 0000000000000..3c9ab6b16a711
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/random/double.tst
@@ -0,0 +1,11 @@
+!! double.tst - Random test case specification for DP functions
+!!
+!! Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+!! See https://llvm.org/LICENSE.txt for license information.
+!! SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+test exp 10000
+test exp2 10000
+test log 10000
+test log2 10000
+test pow 40000
diff --git a/libc/AOR_v20.02/math/test/testcases/random/float.tst b/libc/AOR_v20.02/math/test/testcases/random/float.tst
new file mode 100644
index 0000000000000..c142d63cd5949
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/testcases/random/float.tst
@@ -0,0 +1,16 @@
+!! single.tst - Random test case specification for SP functions
+!!
+!! Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+!! See https://llvm.org/LICENSE.txt for license information.
+!! SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+test sinf 10000
+test cosf 10000
+test sincosf_sinf 5000
+test sincosf_cosf 5000
+test tanf 10000
+test expf 10000
+test exp2f 10000
+test logf 10000
+test log2f 10000
+test powf 10000
diff --git a/libc/AOR_v20.02/math/test/traces/exp.txt b/libc/AOR_v20.02/math/test/traces/exp.txt
new file mode 100644
index 0000000000000..cb067d5174b98
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/traces/exp.txt
@@ -0,0 +1,16000 @@
+0x1.0bc8e7ca4ae1bp+0
+0x1.f9a012f44a109p-1
+-0x1.87a0e64ca4704p-15
+0x1.d2d48a18a7775p-1
+0x1.bb1c1c3d91533p-1
+-0x1.f99f18cd2896bp-16
+0x1.58bb57317e405p-1
+0x1.4a09091f7ebeep-1
+-0x1.44718c44e91cfp-16
+0x1.45fa2a0b71c2bp-1
+0x1.38762d53b5588p-1
+-0x1.2a455304fad52p-16
+0x1.b7bf404f6d792p-1
+0x1.89b7f02cc3616p-1
+-0x1.4725ae5fe330ep-15
+0x1.7f67cd7b4808bp-1
+0x1.55ed18823552ep-1
+-0x1.a739b0e2abe9dp-16
+0x1.1b3e775bae9c8p-1
+0x1.f6023db8868e1p-2
+-0x1.104f2fa39a12bp-16
+0x1.0bd9b65f01703p-1
+0x1.da4b53554e44dp-2
+-0x1.f526b52905e9p-17
+0x1.1fc5ef99d9612p+0
+0x1.47b931f513835p+0
+-0x1.02b1bcc2094d9p-15
+0x1.f8c730332548cp-1
+0x1.19482cc4dc1fbp+0
+-0x1.4e16557b341d3p-16
+0x1.786dce71f0b35p-1
+0x1.950d7d5198b4fp-1
+-0x1.accc5b8b72601p-17
+0x1.6472662268d79p-1
+0x1.7d9d06ca67edep-1
+-0x1.8a3bc4d1f5a5ep-17
+0x1.330645d7c99bp+0
+0x1.25004ff9555e8p+0
+-0x1.85274bbfa239fp-16
+0x1.0e7034f78e1c8p+0
+0x1.0206cf3f5e944p+0
+-0x1.f6fe344c539b3p-17
+0x1.96178955052a6p-1
+0x1.8350a15e7b7f3p-1
+-0x1.43010b67688cep-17
+0x1.80e714f138abdp-1
+0x1.6f163e464ed4fp-1
+-0x1.290da68f570f6p-17
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diff --git a/libc/AOR_v20.02/math/test/traces/sincosf.txt b/libc/AOR_v20.02/math/test/traces/sincosf.txt
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index 0000000000000..33de0c7ab9e32
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/traces/sincosf.txt
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diff --git a/libc/AOR_v20.02/math/test/ulp.c b/libc/AOR_v20.02/math/test/ulp.c
new file mode 100644
index 0000000000000..3821986f7cb48
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/ulp.c
@@ -0,0 +1,852 @@
+/*
+ * ULP error checking tool for math functions.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <ctype.h>
+#include <fenv.h>
+#include <float.h>
+#include <math.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "mathlib.h"
+
+/* Don't depend on mpfr by default.  */
+#ifndef USE_MPFR
+# define USE_MPFR 0
+#endif
+#if USE_MPFR
+# include <mpfr.h>
+#endif
+
+#ifndef WANT_VMATH
+/* Enable the build of vector math code.  */
+# define WANT_VMATH 1
+#endif
+
+static inline uint64_t
+asuint64 (double f)
+{
+  union
+  {
+    double f;
+    uint64_t i;
+  } u = {f};
+  return u.i;
+}
+
+static inline double
+asdouble (uint64_t i)
+{
+  union
+  {
+    uint64_t i;
+    double f;
+  } u = {i};
+  return u.f;
+}
+
+static inline uint32_t
+asuint (float f)
+{
+  union
+  {
+    float f;
+    uint32_t i;
+  } u = {f};
+  return u.i;
+}
+
+static inline float
+asfloat (uint32_t i)
+{
+  union
+  {
+    uint32_t i;
+    float f;
+  } u = {i};
+  return u.f;
+}
+
+static uint64_t seed = 0x0123456789abcdef;
+static uint64_t
+rand64 (void)
+{
+  seed = 6364136223846793005ull * seed + 1;
+  return seed ^ (seed >> 32);
+}
+
+/* Uniform random in [0,n].  */
+static uint64_t
+randn (uint64_t n)
+{
+  uint64_t r, m;
+
+  if (n == 0)
+    return 0;
+  n++;
+  if (n == 0)
+    return rand64 ();
+  for (;;)
+    {
+      r = rand64 ();
+      m = r % n;
+      if (r - m <= -n)
+	return m;
+    }
+}
+
+struct gen
+{
+  uint64_t start;
+  uint64_t len;
+  uint64_t start2;
+  uint64_t len2;
+  uint64_t off;
+  uint64_t step;
+  uint64_t cnt;
+};
+
+struct args_f1
+{
+  float x;
+};
+
+struct args_f2
+{
+  float x;
+  float x2;
+};
+
+struct args_d1
+{
+  double x;
+};
+
+struct args_d2
+{
+  double x;
+  double x2;
+};
+
+/* result = y + tail*2^ulpexp.  */
+struct ret_f
+{
+  float y;
+  double tail;
+  int ulpexp;
+  int ex;
+  int ex_may;
+};
+
+struct ret_d
+{
+  double y;
+  double tail;
+  int ulpexp;
+  int ex;
+  int ex_may;
+};
+
+static inline uint64_t
+next1 (struct gen *g)
+{
+  /* For single argument use randomized incremental steps,
+     that produce dense sampling without collisions and allow
+     testing all inputs in a range.  */
+  uint64_t r = g->start + g->off;
+  g->off += g->step + randn (g->step / 2);
+  if (g->off > g->len)
+    g->off -= g->len; /* hack.  */
+  return r;
+}
+
+static inline uint64_t
+next2 (uint64_t *x2, struct gen *g)
+{
+  /* For two arguments use uniform random sampling.  */
+  uint64_t r = g->start + randn (g->len);
+  *x2 = g->start2 + randn (g->len2);
+  return r;
+}
+
+static struct args_f1
+next_f1 (void *g)
+{
+  return (struct args_f1){asfloat (next1 (g))};
+}
+
+static struct args_f2
+next_f2 (void *g)
+{
+  uint64_t x2;
+  uint64_t x = next2 (&x2, g);
+  return (struct args_f2){asfloat (x), asfloat (x2)};
+}
+
+static struct args_d1
+next_d1 (void *g)
+{
+  return (struct args_d1){asdouble (next1 (g))};
+}
+
+static struct args_d2
+next_d2 (void *g)
+{
+  uint64_t x2;
+  uint64_t x = next2 (&x2, g);
+  return (struct args_d2){asdouble (x), asdouble (x2)};
+}
+
+struct conf
+{
+  int r;
+  int rc;
+  int quiet;
+  int mpfr;
+  int fenv;
+  unsigned long long n;
+  double softlim;
+  double errlim;
+};
+
+/* Wrappers for sincos.  */
+static float sincosf_sinf(float x) {(void)cosf(x); return sinf(x);}
+static float sincosf_cosf(float x) {(void)sinf(x); return cosf(x);}
+static double sincos_sin(double x) {(void)cos(x); return sin(x);}
+static double sincos_cos(double x) {(void)sin(x); return cos(x);}
+#if USE_MPFR
+static int sincos_mpfr_sin(mpfr_t y, const mpfr_t x, mpfr_rnd_t r) { mpfr_cos(y,x,r); return mpfr_sin(y,x,r); }
+static int sincos_mpfr_cos(mpfr_t y, const mpfr_t x, mpfr_rnd_t r) { mpfr_sin(y,x,r); return mpfr_cos(y,x,r); }
+#endif
+
+/* A bit of a hack: call vector functions twice with the same
+   input in lane 0 but a different value in other lanes: once
+   with an in-range value and then with a special case value.  */
+static int secondcall;
+
+/* Wrappers for vector functions.  */
+#if __aarch64__ && WANT_VMATH
+typedef __f32x4_t v_float;
+typedef __f64x2_t v_double;
+static const float fv[2] = {1.0f, -INFINITY};
+static const double dv[2] = {1.0, -INFINITY};
+static inline v_float argf(float x) { return (v_float){x,x,x,fv[secondcall]}; }
+static inline v_double argd(double x) { return (v_double){x,dv[secondcall]}; }
+
+static float v_sinf(float x) { return __v_sinf(argf(x))[0]; }
+static float v_cosf(float x) { return __v_cosf(argf(x))[0]; }
+static float v_expf_1u(float x) { return __v_expf_1u(argf(x))[0]; }
+static float v_expf(float x) { return __v_expf(argf(x))[0]; }
+static float v_exp2f_1u(float x) { return __v_exp2f_1u(argf(x))[0]; }
+static float v_exp2f(float x) { return __v_exp2f(argf(x))[0]; }
+static float v_logf(float x) { return __v_logf(argf(x))[0]; }
+static float v_powf(float x, float y) { return __v_powf(argf(x),argf(y))[0]; }
+static double v_sin(double x) { return __v_sin(argd(x))[0]; }
+static double v_cos(double x) { return __v_cos(argd(x))[0]; }
+static double v_exp(double x) { return __v_exp(argd(x))[0]; }
+static double v_log(double x) { return __v_log(argd(x))[0]; }
+static double v_pow(double x, double y) { return __v_pow(argd(x),argd(y))[0]; }
+#ifdef __vpcs
+static float vn_sinf(float x) { return __vn_sinf(argf(x))[0]; }
+static float vn_cosf(float x) { return __vn_cosf(argf(x))[0]; }
+static float vn_expf_1u(float x) { return __vn_expf_1u(argf(x))[0]; }
+static float vn_expf(float x) { return __vn_expf(argf(x))[0]; }
+static float vn_exp2f_1u(float x) { return __vn_exp2f_1u(argf(x))[0]; }
+static float vn_exp2f(float x) { return __vn_exp2f(argf(x))[0]; }
+static float vn_logf(float x) { return __vn_logf(argf(x))[0]; }
+static float vn_powf(float x, float y) { return __vn_powf(argf(x),argf(y))[0]; }
+static double vn_sin(double x) { return __vn_sin(argd(x))[0]; }
+static double vn_cos(double x) { return __vn_cos(argd(x))[0]; }
+static double vn_exp(double x) { return __vn_exp(argd(x))[0]; }
+static double vn_log(double x) { return __vn_log(argd(x))[0]; }
+static double vn_pow(double x, double y) { return __vn_pow(argd(x),argd(y))[0]; }
+static float Z_sinf(float x) { return _ZGVnN4v_sinf(argf(x))[0]; }
+static float Z_cosf(float x) { return _ZGVnN4v_cosf(argf(x))[0]; }
+static float Z_expf(float x) { return _ZGVnN4v_expf(argf(x))[0]; }
+static float Z_exp2f(float x) { return _ZGVnN4v_exp2f(argf(x))[0]; }
+static float Z_logf(float x) { return _ZGVnN4v_logf(argf(x))[0]; }
+static float Z_powf(float x, float y) { return _ZGVnN4vv_powf(argf(x),argf(y))[0]; }
+static double Z_sin(double x) { return _ZGVnN2v_sin(argd(x))[0]; }
+static double Z_cos(double x) { return _ZGVnN2v_cos(argd(x))[0]; }
+static double Z_exp(double x) { return _ZGVnN2v_exp(argd(x))[0]; }
+static double Z_log(double x) { return _ZGVnN2v_log(argd(x))[0]; }
+static double Z_pow(double x, double y) { return _ZGVnN2vv_pow(argd(x),argd(y))[0]; }
+#endif
+#endif
+
+struct fun
+{
+  const char *name;
+  int arity;
+  int singleprec;
+  int twice;
+  union
+  {
+    float (*f1) (float);
+    float (*f2) (float, float);
+    double (*d1) (double);
+    double (*d2) (double, double);
+  } fun;
+  union
+  {
+    double (*f1) (double);
+    double (*f2) (double, double);
+    long double (*d1) (long double);
+    long double (*d2) (long double, long double);
+  } fun_long;
+#if USE_MPFR
+  union
+  {
+    int (*f1) (mpfr_t, const mpfr_t, mpfr_rnd_t);
+    int (*f2) (mpfr_t, const mpfr_t, const mpfr_t, mpfr_rnd_t);
+    int (*d1) (mpfr_t, const mpfr_t, mpfr_rnd_t);
+    int (*d2) (mpfr_t, const mpfr_t, const mpfr_t, mpfr_rnd_t);
+  } fun_mpfr;
+#endif
+};
+
+static const struct fun fun[] = {
+#if USE_MPFR
+# define F(x, x_wrap, x_long, x_mpfr, a, s, t, twice) \
+  {#x, a, s, twice, {.t = x_wrap}, {.t = x_long}, {.t = x_mpfr}},
+#else
+# define F(x, x_wrap, x_long, x_mpfr, a, s, t, twice) \
+  {#x, a, s, twice, {.t = x_wrap}, {.t = x_long}},
+#endif
+#define F1(x) F (x##f, x##f, x, mpfr_##x, 1, 1, f1, 0)
+#define F2(x) F (x##f, x##f, x, mpfr_##x, 2, 1, f2, 0)
+#define D1(x) F (x, x, x##l, mpfr_##x, 1, 0, d1, 0)
+#define D2(x) F (x, x, x##l, mpfr_##x, 2, 0, d2, 0)
+ F1 (sin)
+ F1 (cos)
+ F (sincosf_sinf, sincosf_sinf, sincos_sin, sincos_mpfr_sin, 1, 1, f1, 0)
+ F (sincosf_cosf, sincosf_cosf, sincos_cos, sincos_mpfr_cos, 1, 1, f1, 0)
+ F1 (exp)
+ F1 (exp2)
+ F1 (log)
+ F1 (log2)
+ F2 (pow)
+ D1 (exp)
+ D1 (exp2)
+ D1 (log)
+ D1 (log2)
+ D2 (pow)
+#if WANT_VMATH
+ F (__s_sinf, __s_sinf, sin, mpfr_sin, 1, 1, f1, 0)
+ F (__s_cosf, __s_cosf, cos, mpfr_cos, 1, 1, f1, 0)
+ F (__s_expf_1u, __s_expf_1u, exp, mpfr_exp, 1, 1, f1, 0)
+ F (__s_expf, __s_expf, exp, mpfr_exp, 1, 1, f1, 0)
+ F (__s_exp2f_1u, __s_exp2f_1u, exp2, mpfr_exp2, 1, 1, f1, 0)
+ F (__s_exp2f, __s_exp2f, exp2, mpfr_exp2, 1, 1, f1, 0)
+ F (__s_powf, __s_powf, pow, mpfr_pow, 2, 1, f2, 0)
+ F (__s_logf, __s_logf, log, mpfr_log, 1, 1, f1, 0)
+ F (__s_sin, __s_sin, sinl, mpfr_sin, 1, 0, d1, 0)
+ F (__s_cos, __s_cos, cosl, mpfr_cos, 1, 0, d1, 0)
+ F (__s_exp, __s_exp, expl, mpfr_exp, 1, 0, d1, 0)
+ F (__s_log, __s_log, logl, mpfr_log, 1, 0, d1, 0)
+ F (__s_pow, __s_pow, powl, mpfr_pow, 2, 0, d2, 0)
+#if __aarch64__
+ F (__v_sinf, v_sinf, sin, mpfr_sin, 1, 1, f1, 1)
+ F (__v_cosf, v_cosf, cos, mpfr_cos, 1, 1, f1, 1)
+ F (__v_expf_1u, v_expf_1u, exp, mpfr_exp, 1, 1, f1, 1)
+ F (__v_expf, v_expf, exp, mpfr_exp, 1, 1, f1, 1)
+ F (__v_exp2f_1u, v_exp2f_1u, exp2, mpfr_exp2, 1, 1, f1, 1)
+ F (__v_exp2f, v_exp2f, exp2, mpfr_exp2, 1, 1, f1, 1)
+ F (__v_logf, v_logf, log, mpfr_log, 1, 1, f1, 1)
+ F (__v_powf, v_powf, pow, mpfr_pow, 2, 1, f2, 1)
+ F (__v_sin, v_sin, sinl, mpfr_sin, 1, 0, d1, 1)
+ F (__v_cos, v_cos, cosl, mpfr_cos, 1, 0, d1, 1)
+ F (__v_exp, v_exp, expl, mpfr_exp, 1, 0, d1, 1)
+ F (__v_log, v_log, logl, mpfr_log, 1, 0, d1, 1)
+ F (__v_pow, v_pow, powl, mpfr_pow, 2, 0, d2, 1)
+#ifdef __vpcs
+ F (__vn_sinf, vn_sinf, sin, mpfr_sin, 1, 1, f1, 1)
+ F (__vn_cosf, vn_cosf, cos, mpfr_cos, 1, 1, f1, 1)
+ F (__vn_expf_1u, vn_expf_1u, exp, mpfr_exp, 1, 1, f1, 1)
+ F (__vn_expf, vn_expf, exp, mpfr_exp, 1, 1, f1, 1)
+ F (__vn_exp2f_1u, vn_exp2f_1u, exp2, mpfr_exp2, 1, 1, f1, 1)
+ F (__vn_exp2f, vn_exp2f, exp2, mpfr_exp2, 1, 1, f1, 1)
+ F (__vn_logf, vn_logf, log, mpfr_log, 1, 1, f1, 1)
+ F (__vn_powf, vn_powf, pow, mpfr_pow, 2, 1, f2, 1)
+ F (__vn_sin, vn_sin, sinl, mpfr_sin, 1, 0, d1, 1)
+ F (__vn_cos, vn_cos, cosl, mpfr_cos, 1, 0, d1, 1)
+ F (__vn_exp, vn_exp, expl, mpfr_exp, 1, 0, d1, 1)
+ F (__vn_log, vn_log, logl, mpfr_log, 1, 0, d1, 1)
+ F (__vn_pow, vn_pow, powl, mpfr_pow, 2, 0, d2, 1)
+ F (_ZGVnN4v_sinf, Z_sinf, sin, mpfr_sin, 1, 1, f1, 1)
+ F (_ZGVnN4v_cosf, Z_cosf, cos, mpfr_cos, 1, 1, f1, 1)
+ F (_ZGVnN4v_expf, Z_expf, exp, mpfr_exp, 1, 1, f1, 1)
+ F (_ZGVnN4v_exp2f, Z_exp2f, exp2, mpfr_exp2, 1, 1, f1, 1)
+ F (_ZGVnN4v_logf, Z_logf, log, mpfr_log, 1, 1, f1, 1)
+ F (_ZGVnN4vv_powf, Z_powf, pow, mpfr_pow, 2, 1, f2, 1)
+ F (_ZGVnN2v_sin, Z_sin, sinl, mpfr_sin, 1, 0, d1, 1)
+ F (_ZGVnN2v_cos, Z_cos, cosl, mpfr_cos, 1, 0, d1, 1)
+ F (_ZGVnN2v_exp, Z_exp, expl, mpfr_exp, 1, 0, d1, 1)
+ F (_ZGVnN2v_log, Z_log, logl, mpfr_log, 1, 0, d1, 1)
+ F (_ZGVnN2vv_pow, Z_pow, powl, mpfr_pow, 2, 0, d2, 1)
+#endif
+#endif
+#endif
+#undef F
+#undef F1
+#undef F2
+#undef D1
+#undef D2
+ {0}};
+
+/* Boilerplate for generic calls.  */
+
+static inline int
+ulpscale_f (float x)
+{
+  int e = asuint (x) >> 23 & 0xff;
+  if (!e)
+    e++;
+  return e - 0x7f - 23;
+}
+static inline int
+ulpscale_d (double x)
+{
+  int e = asuint64 (x) >> 52 & 0x7ff;
+  if (!e)
+    e++;
+  return e - 0x3ff - 52;
+}
+static inline float
+call_f1 (const struct fun *f, struct args_f1 a)
+{
+  return f->fun.f1 (a.x);
+}
+static inline float
+call_f2 (const struct fun *f, struct args_f2 a)
+{
+  return f->fun.f2 (a.x, a.x2);
+}
+
+static inline double
+call_d1 (const struct fun *f, struct args_d1 a)
+{
+  return f->fun.d1 (a.x);
+}
+static inline double
+call_d2 (const struct fun *f, struct args_d2 a)
+{
+  return f->fun.d2 (a.x, a.x2);
+}
+static inline double
+call_long_f1 (const struct fun *f, struct args_f1 a)
+{
+  return f->fun_long.f1 (a.x);
+}
+static inline double
+call_long_f2 (const struct fun *f, struct args_f2 a)
+{
+  return f->fun_long.f2 (a.x, a.x2);
+}
+static inline long double
+call_long_d1 (const struct fun *f, struct args_d1 a)
+{
+  return f->fun_long.d1 (a.x);
+}
+static inline long double
+call_long_d2 (const struct fun *f, struct args_d2 a)
+{
+  return f->fun_long.d2 (a.x, a.x2);
+}
+static inline void
+printcall_f1 (const struct fun *f, struct args_f1 a)
+{
+  printf ("%s(%a)", f->name, a.x);
+}
+static inline void
+printcall_f2 (const struct fun *f, struct args_f2 a)
+{
+  printf ("%s(%a, %a)", f->name, a.x, a.x2);
+}
+static inline void
+printcall_d1 (const struct fun *f, struct args_d1 a)
+{
+  printf ("%s(%a)", f->name, a.x);
+}
+static inline void
+printcall_d2 (const struct fun *f, struct args_d2 a)
+{
+  printf ("%s(%a, %a)", f->name, a.x, a.x2);
+}
+static inline void
+printgen_f1 (const struct fun *f, struct gen *gen)
+{
+  printf ("%s in [%a;%a]", f->name, asfloat (gen->start),
+	  asfloat (gen->start + gen->len));
+}
+static inline void
+printgen_f2 (const struct fun *f, struct gen *gen)
+{
+  printf ("%s in [%a;%a] x [%a;%a]", f->name, asfloat (gen->start),
+	  asfloat (gen->start + gen->len), asfloat (gen->start2),
+	  asfloat (gen->start2 + gen->len2));
+}
+static inline void
+printgen_d1 (const struct fun *f, struct gen *gen)
+{
+  printf ("%s in [%a;%a]", f->name, asdouble (gen->start),
+	  asdouble (gen->start + gen->len));
+}
+static inline void
+printgen_d2 (const struct fun *f, struct gen *gen)
+{
+  printf ("%s in [%a;%a] x [%a;%a]", f->name, asdouble (gen->start),
+	  asdouble (gen->start + gen->len), asdouble (gen->start2),
+	  asdouble (gen->start2 + gen->len2));
+}
+
+#define reduce_f1(a, f, op) (f (a.x))
+#define reduce_f2(a, f, op) (f (a.x) op f (a.x2))
+#define reduce_d1(a, f, op) (f (a.x))
+#define reduce_d2(a, f, op) (f (a.x) op f (a.x2))
+
+#ifndef IEEE_754_2008_SNAN
+# define IEEE_754_2008_SNAN 1
+#endif
+static inline int
+issignaling_f (float x)
+{
+  uint32_t ix = asuint (x);
+  if (!IEEE_754_2008_SNAN)
+    return (ix & 0x7fc00000) == 0x7fc00000;
+  return 2 * (ix ^ 0x00400000) > 2u * 0x7fc00000;
+}
+static inline int
+issignaling_d (double x)
+{
+  uint64_t ix = asuint64 (x);
+  if (!IEEE_754_2008_SNAN)
+    return (ix & 0x7ff8000000000000) == 0x7ff8000000000000;
+  return 2 * (ix ^ 0x0008000000000000) > 2 * 0x7ff8000000000000ULL;
+}
+
+#if USE_MPFR
+static mpfr_rnd_t
+rmap (int r)
+{
+  switch (r)
+    {
+    case FE_TONEAREST:
+      return MPFR_RNDN;
+    case FE_TOWARDZERO:
+      return MPFR_RNDZ;
+    case FE_UPWARD:
+      return MPFR_RNDU;
+    case FE_DOWNWARD:
+      return MPFR_RNDD;
+    }
+  return -1;
+}
+
+#define prec_mpfr_f 50
+#define prec_mpfr_d 80
+#define prec_f 24
+#define prec_d 53
+#define emin_f -148
+#define emin_d -1073
+#define emax_f 128
+#define emax_d 1024
+static inline int
+call_mpfr_f1 (mpfr_t y, const struct fun *f, struct args_f1 a, mpfr_rnd_t r)
+{
+  MPFR_DECL_INIT (x, prec_f);
+  mpfr_set_flt (x, a.x, MPFR_RNDN);
+  return f->fun_mpfr.f1 (y, x, r);
+}
+static inline int
+call_mpfr_f2 (mpfr_t y, const struct fun *f, struct args_f2 a, mpfr_rnd_t r)
+{
+  MPFR_DECL_INIT (x, prec_f);
+  MPFR_DECL_INIT (x2, prec_f);
+  mpfr_set_flt (x, a.x, MPFR_RNDN);
+  mpfr_set_flt (x2, a.x2, MPFR_RNDN);
+  return f->fun_mpfr.f2 (y, x, x2, r);
+}
+static inline int
+call_mpfr_d1 (mpfr_t y, const struct fun *f, struct args_d1 a, mpfr_rnd_t r)
+{
+  MPFR_DECL_INIT (x, prec_d);
+  mpfr_set_d (x, a.x, MPFR_RNDN);
+  return f->fun_mpfr.d1 (y, x, r);
+}
+static inline int
+call_mpfr_d2 (mpfr_t y, const struct fun *f, struct args_d2 a, mpfr_rnd_t r)
+{
+  MPFR_DECL_INIT (x, prec_d);
+  MPFR_DECL_INIT (x2, prec_d);
+  mpfr_set_d (x, a.x, MPFR_RNDN);
+  mpfr_set_d (x2, a.x2, MPFR_RNDN);
+  return f->fun_mpfr.d2 (y, x, x2, r);
+}
+#endif
+
+#define float_f float
+#define double_f double
+#define copysign_f copysignf
+#define nextafter_f nextafterf
+#define fabs_f fabsf
+#define asuint_f asuint
+#define asfloat_f asfloat
+#define scalbn_f scalbnf
+#define lscalbn_f scalbn
+#define halfinf_f 0x1p127f
+#define min_normal_f 0x1p-126f
+
+#define float_d double
+#define double_d long double
+#define copysign_d copysign
+#define nextafter_d nextafter
+#define fabs_d fabs
+#define asuint_d asuint64
+#define asfloat_d asdouble
+#define scalbn_d scalbn
+#define lscalbn_d scalbnl
+#define halfinf_d 0x1p1023
+#define min_normal_d 0x1p-1022
+
+#define NEW_RT
+#define RT(x) x##_f
+#define T(x) x##_f1
+#include "ulp.h"
+#undef T
+#define T(x) x##_f2
+#include "ulp.h"
+#undef T
+#undef RT
+
+#define NEW_RT
+#define RT(x) x##_d
+#define T(x) x##_d1
+#include "ulp.h"
+#undef T
+#define T(x) x##_d2
+#include "ulp.h"
+#undef T
+#undef RT
+
+static void
+usage (void)
+{
+  puts ("./ulp [-q] [-m] [-f] [-r nudz] [-l soft-ulplimit] [-e ulplimit] func "
+	"lo [hi [x lo2 hi2] [count]]");
+  puts ("Compares func against a higher precision implementation in [lo; hi].");
+  puts ("-q: quiet.");
+  puts ("-m: use mpfr even if faster method is available.");
+  puts ("-f: disable fenv testing (rounding modes and exceptions).");
+  puts ("Supported func:");
+  for (const struct fun *f = fun; f->name; f++)
+    printf ("\t%s\n", f->name);
+  exit (1);
+}
+
+static int
+cmp (const struct fun *f, struct gen *gen, const struct conf *conf)
+{
+  int r = 1;
+  if (f->arity == 1 && f->singleprec)
+    r = cmp_f1 (f, gen, conf);
+  else if (f->arity == 2 && f->singleprec)
+    r = cmp_f2 (f, gen, conf);
+  else if (f->arity == 1 && !f->singleprec)
+    r = cmp_d1 (f, gen, conf);
+  else if (f->arity == 2 && !f->singleprec)
+    r = cmp_d2 (f, gen, conf);
+  else
+    usage ();
+  return r;
+}
+
+static uint64_t
+getnum (const char *s, int singleprec)
+{
+  //	int i;
+  uint64_t sign = 0;
+  //	char buf[12];
+
+  if (s[0] == '+')
+    s++;
+  else if (s[0] == '-')
+    {
+      sign = singleprec ? 1ULL << 31 : 1ULL << 63;
+      s++;
+    }
+  /* 0xXXXX is treated as bit representation, '-' flips the sign bit.  */
+  if (s[0] == '0' && tolower (s[1]) == 'x' && strchr (s, 'p') == 0)
+    return sign ^ strtoull (s, 0, 0);
+  //	/* SNaN, QNaN, NaN, Inf.  */
+  //	for (i=0; s[i] && i < sizeof buf; i++)
+  //		buf[i] = tolower(s[i]);
+  //	buf[i] = 0;
+  //	if (strcmp(buf, "snan") == 0)
+  //		return sign | (singleprec ? 0x7fa00000 : 0x7ff4000000000000);
+  //	if (strcmp(buf, "qnan") == 0 || strcmp(buf, "nan") == 0)
+  //		return sign | (singleprec ? 0x7fc00000 : 0x7ff8000000000000);
+  //	if (strcmp(buf, "inf") == 0 || strcmp(buf, "infinity") == 0)
+  //		return sign | (singleprec ? 0x7f800000 : 0x7ff0000000000000);
+  /* Otherwise assume it's a floating-point literal.  */
+  return sign
+	 | (singleprec ? asuint (strtof (s, 0)) : asuint64 (strtod (s, 0)));
+}
+
+static void
+parsegen (struct gen *g, int argc, char *argv[], const struct fun *f)
+{
+  int singleprec = f->singleprec;
+  int arity = f->arity;
+  uint64_t a, b, a2, b2, n;
+  if (argc < 1)
+    usage ();
+  b = a = getnum (argv[0], singleprec);
+  n = 0;
+  if (argc > 1 && strcmp (argv[1], "x") == 0)
+    {
+      argc -= 2;
+      argv += 2;
+    }
+  else if (argc > 1)
+    {
+      b = getnum (argv[1], singleprec);
+      if (argc > 2 && strcmp (argv[2], "x") == 0)
+	{
+	  argc -= 3;
+	  argv += 3;
+	}
+    }
+  b2 = a2 = getnum (argv[0], singleprec);
+  if (argc > 1)
+    b2 = getnum (argv[1], singleprec);
+  if (argc > 2)
+    n = strtoull (argv[2], 0, 0);
+  if (argc > 3)
+    usage ();
+  //printf("ab %lx %lx ab2 %lx %lx n %lu\n", a, b, a2, b2, n);
+  if (arity == 1)
+    {
+      g->start = a;
+      g->len = b - a;
+      if (n - 1 > b - a)
+	n = b - a + 1;
+      g->off = 0;
+      g->step = n ? (g->len + 1) / n : 1;
+      g->start2 = g->len2 = 0;
+      g->cnt = n;
+    }
+  else if (arity == 2)
+    {
+      g->start = a;
+      g->len = b - a;
+      g->off = g->step = 0;
+      g->start2 = a2;
+      g->len2 = b2 - a2;
+      g->cnt = n;
+    }
+  else
+    usage ();
+}
+
+int
+main (int argc, char *argv[])
+{
+  const struct fun *f;
+  struct gen gen;
+  struct conf conf;
+  conf.rc = 'n';
+  conf.quiet = 0;
+  conf.mpfr = 0;
+  conf.fenv = 1;
+  conf.softlim = 0;
+  conf.errlim = INFINITY;
+  for (;;)
+    {
+      argc--;
+      argv++;
+      if (argc < 1)
+	usage ();
+      if (argv[0][0] != '-')
+	break;
+      switch (argv[0][1])
+	{
+	case 'e':
+	  argc--;
+	  argv++;
+	  if (argc < 1)
+	    usage ();
+	  conf.errlim = strtod (argv[0], 0);
+	  break;
+	case 'f':
+	  conf.fenv = 0;
+	  break;
+	case 'l':
+	  argc--;
+	  argv++;
+	  if (argc < 1)
+	    usage ();
+	  conf.softlim = strtod (argv[0], 0);
+	  break;
+	case 'm':
+	  conf.mpfr = 1;
+	  break;
+	case 'q':
+	  conf.quiet = 1;
+	  break;
+	case 'r':
+	  conf.rc = argv[0][2];
+	  if (!conf.rc)
+	    {
+	      argc--;
+	      argv++;
+	      if (argc < 1)
+		usage ();
+	      conf.rc = argv[0][0];
+	    }
+	  break;
+	default:
+	  usage ();
+	}
+    }
+  switch (conf.rc)
+    {
+    case 'n':
+      conf.r = FE_TONEAREST;
+      break;
+    case 'u':
+      conf.r = FE_UPWARD;
+      break;
+    case 'd':
+      conf.r = FE_DOWNWARD;
+      break;
+    case 'z':
+      conf.r = FE_TOWARDZERO;
+      break;
+    default:
+      usage ();
+    }
+  for (f = fun; f->name; f++)
+    if (strcmp (argv[0], f->name) == 0)
+      break;
+  if (!f->name)
+    usage ();
+  if (!f->singleprec && LDBL_MANT_DIG == DBL_MANT_DIG)
+    conf.mpfr = 1; /* Use mpfr if long double has no extra precision.  */
+  if (!USE_MPFR && conf.mpfr)
+    {
+      puts ("mpfr is not available.");
+      return 0;
+    }
+  argc--;
+  argv++;
+  parsegen (&gen, argc, argv, f);
+  conf.n = gen.cnt;
+  return cmp (f, &gen, &conf);
+}
diff --git a/libc/AOR_v20.02/math/test/ulp.h b/libc/AOR_v20.02/math/test/ulp.h
new file mode 100644
index 0000000000000..2743dc59b5a4b
--- /dev/null
+++ b/libc/AOR_v20.02/math/test/ulp.h
@@ -0,0 +1,363 @@
+/*
+ * Generic functions for ULP error estimation.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* For each different math function type,
+   T(x) should add a different suffix to x.
+   RT(x) should add a return type specific suffix to x. */
+
+#ifdef NEW_RT
+#undef NEW_RT
+
+# if USE_MPFR
+static int RT(ulpscale_mpfr) (mpfr_t x, int t)
+{
+  /* TODO: pow of 2 cases.  */
+  if (mpfr_regular_p (x))
+    {
+      mpfr_exp_t e = mpfr_get_exp (x) - RT(prec);
+      if (e < RT(emin))
+	e = RT(emin) - 1;
+      if (e > RT(emax) - RT(prec))
+	e = RT(emax) - RT(prec);
+      return e;
+    }
+  if (mpfr_zero_p (x))
+    return RT(emin) - 1;
+  if (mpfr_inf_p (x))
+    return RT(emax) - RT(prec);
+  /* NaN.  */
+  return 0;
+}
+# endif
+
+/* Difference between exact result and closest real number that
+   gets rounded to got, i.e. error before rounding, for a correctly
+   rounded result the difference is 0.  */
+static double RT(ulperr) (RT(float) got, const struct RT(ret) * p, int r)
+{
+  RT(float) want = p->y;
+  RT(float) d;
+  double e;
+
+  if (RT(asuint) (got) == RT(asuint) (want))
+    return 0.0;
+  if (signbit (got) != signbit (want))
+    /* May have false positives with NaN.  */
+    //return isnan(got) && isnan(want) ? 0 : INFINITY;
+    return INFINITY;
+  if (!isfinite (want) || !isfinite (got))
+    {
+      if (isnan (got) != isnan (want))
+	return INFINITY;
+      if (isnan (want))
+	return 0;
+      if (isinf (got))
+	{
+	  got = RT(copysign) (RT(halfinf), got);
+	  want *= 0.5f;
+	}
+      if (isinf (want))
+	{
+	  want = RT(copysign) (RT(halfinf), want);
+	  got *= 0.5f;
+	}
+    }
+  if (r == FE_TONEAREST)
+    {
+      // TODO: incorrect when got vs want cross a powof2 boundary
+      /* error = got > want
+	      ? got - want - tail ulp - 0.5 ulp
+	      : got - want - tail ulp + 0.5 ulp;  */
+      d = got - want;
+      e = d > 0 ? -p->tail - 0.5 : -p->tail + 0.5;
+    }
+  else
+    {
+      if ((r == FE_DOWNWARD && got < want) || (r == FE_UPWARD && got > want)
+	  || (r == FE_TOWARDZERO && fabs (got) < fabs (want)))
+	got = RT(nextafter) (got, want);
+      d = got - want;
+      e = -p->tail;
+    }
+  return RT(scalbn) (d, -p->ulpexp) + e;
+}
+
+static int RT(isok) (RT(float) ygot, int exgot, RT(float) ywant, int exwant,
+		      int exmay)
+{
+  return RT(asuint) (ygot) == RT(asuint) (ywant)
+	 && ((exgot ^ exwant) & ~exmay) == 0;
+}
+
+static int RT(isok_nofenv) (RT(float) ygot, RT(float) ywant)
+{
+  return RT(asuint) (ygot) == RT(asuint) (ywant);
+}
+#endif
+
+static inline void T(call_fenv) (const struct fun *f, struct T(args) a, int r,
+				  RT(float) * y, int *ex)
+{
+  if (r != FE_TONEAREST)
+    fesetround (r);
+  feclearexcept (FE_ALL_EXCEPT);
+  *y = T(call) (f, a);
+  *ex = fetestexcept (FE_ALL_EXCEPT);
+  if (r != FE_TONEAREST)
+    fesetround (FE_TONEAREST);
+}
+
+static inline void T(call_nofenv) (const struct fun *f, struct T(args) a,
+				    int r, RT(float) * y, int *ex)
+{
+  *y = T(call) (f, a);
+  *ex = 0;
+}
+
+static inline int T(call_long_fenv) (const struct fun *f, struct T(args) a,
+				      int r, struct RT(ret) * p,
+				      RT(float) ygot, int exgot)
+{
+  if (r != FE_TONEAREST)
+    fesetround (r);
+  feclearexcept (FE_ALL_EXCEPT);
+  volatile struct T(args) va = a; // TODO: barrier
+  a = va;
+  RT(double) yl = T(call_long) (f, a);
+  p->y = (RT(float)) yl;
+  volatile RT(float) vy = p->y; // TODO: barrier
+  (void) vy;
+  p->ex = fetestexcept (FE_ALL_EXCEPT);
+  if (r != FE_TONEAREST)
+    fesetround (FE_TONEAREST);
+  p->ex_may = FE_INEXACT;
+  if (RT(isok) (ygot, exgot, p->y, p->ex, p->ex_may))
+    return 1;
+  p->ulpexp = RT(ulpscale) (p->y);
+  if (isinf (p->y))
+    p->tail = RT(lscalbn) (yl - (RT(double)) 2 * RT(halfinf), -p->ulpexp);
+  else
+    p->tail = RT(lscalbn) (yl - p->y, -p->ulpexp);
+  if (RT(fabs) (p->y) < RT(min_normal))
+    {
+      /* TODO: subnormal result is treated as undeflow even if it's
+	 exact since call_long may not raise inexact correctly.  */
+      if (p->y != 0 || (p->ex & FE_INEXACT))
+	p->ex |= FE_UNDERFLOW | FE_INEXACT;
+    }
+  return 0;
+}
+static inline int T(call_long_nofenv) (const struct fun *f, struct T(args) a,
+					int r, struct RT(ret) * p,
+					RT(float) ygot, int exgot)
+{
+  RT(double) yl = T(call_long) (f, a);
+  p->y = (RT(float)) yl;
+  if (RT(isok_nofenv) (ygot, p->y))
+    return 1;
+  p->ulpexp = RT(ulpscale) (p->y);
+  if (isinf (p->y))
+    p->tail = RT(lscalbn) (yl - (RT(double)) 2 * RT(halfinf), -p->ulpexp);
+  else
+    p->tail = RT(lscalbn) (yl - p->y, -p->ulpexp);
+  return 0;
+}
+
+/* There are nan input args and all quiet.  */
+static inline int T(qnanpropagation) (struct T(args) a)
+{
+  return T(reduce) (a, isnan, ||) && !T(reduce) (a, RT(issignaling), ||);
+}
+static inline RT(float) T(sum) (struct T(args) a)
+{
+  return T(reduce) (a, , +);
+}
+
+/* returns 1 if the got result is ok.  */
+static inline int T(call_mpfr_fix) (const struct fun *f, struct T(args) a,
+				     int r_fenv, struct RT(ret) * p,
+				     RT(float) ygot, int exgot)
+{
+#if USE_MPFR
+  int t, t2;
+  mpfr_rnd_t r = rmap (r_fenv);
+  MPFR_DECL_INIT(my, RT(prec_mpfr));
+  MPFR_DECL_INIT(mr, RT(prec));
+  MPFR_DECL_INIT(me, RT(prec_mpfr));
+  mpfr_clear_flags ();
+  t = T(call_mpfr) (my, f, a, r);
+  /* Double rounding.  */
+  t2 = mpfr_set (mr, my, r);
+  if (t2)
+    t = t2;
+  mpfr_set_emin (RT(emin));
+  mpfr_set_emax (RT(emax));
+  t = mpfr_check_range (mr, t, r);
+  t = mpfr_subnormalize (mr, t, r);
+  mpfr_set_emax (MPFR_EMAX_DEFAULT);
+  mpfr_set_emin (MPFR_EMIN_DEFAULT);
+  p->y = mpfr_get_d (mr, r);
+  p->ex = t ? FE_INEXACT : 0;
+  p->ex_may = FE_INEXACT;
+  if (mpfr_underflow_p () && (p->ex & FE_INEXACT))
+    /* TODO: handle before and after rounding uflow cases.  */
+    p->ex |= FE_UNDERFLOW;
+  if (mpfr_overflow_p ())
+    p->ex |= FE_OVERFLOW | FE_INEXACT;
+  if (mpfr_divby0_p ())
+    p->ex |= FE_DIVBYZERO;
+  //if (mpfr_erangeflag_p ())
+  //  p->ex |= FE_INVALID;
+  if (!mpfr_nanflag_p () && RT(isok) (ygot, exgot, p->y, p->ex, p->ex_may))
+    return 1;
+  if (mpfr_nanflag_p () && !T(qnanpropagation) (a))
+    p->ex |= FE_INVALID;
+  p->ulpexp = RT(ulpscale_mpfr) (my, t);
+  if (!isfinite (p->y))
+    {
+      p->tail = 0;
+      if (isnan (p->y))
+	{
+	  /* If an input was nan keep its sign.  */
+	  p->y = T(sum) (a);
+	  if (!isnan (p->y))
+	    p->y = (p->y - p->y) / (p->y - p->y);
+	  return RT(isok) (ygot, exgot, p->y, p->ex, p->ex_may);
+	}
+      mpfr_set_si_2exp (mr, signbit (p->y) ? -1 : 1, 1024, MPFR_RNDN);
+      if (mpfr_cmpabs (my, mr) >= 0)
+	return RT(isok) (ygot, exgot, p->y, p->ex, p->ex_may);
+    }
+  mpfr_sub (me, my, mr, MPFR_RNDN);
+  mpfr_mul_2si (me, me, -p->ulpexp, MPFR_RNDN);
+  p->tail = mpfr_get_d (me, MPFR_RNDN);
+  return 0;
+#else
+  abort ();
+#endif
+}
+
+static int T(cmp) (const struct fun *f, struct gen *gen,
+		     const struct conf *conf)
+{
+  double maxerr = 0;
+  uint64_t cnt = 0;
+  uint64_t cnt1 = 0;
+  uint64_t cnt2 = 0;
+  uint64_t cntfail = 0;
+  int r = conf->r;
+  int use_mpfr = conf->mpfr;
+  int fenv = conf->fenv;
+  for (;;)
+    {
+      struct RT(ret) want;
+      struct T(args) a = T(next) (gen);
+      int exgot;
+      int exgot2;
+      RT(float) ygot;
+      RT(float) ygot2;
+      int fail = 0;
+      if (fenv)
+	T(call_fenv) (f, a, r, &ygot, &exgot);
+      else
+	T(call_nofenv) (f, a, r, &ygot, &exgot);
+      if (f->twice) {
+	secondcall = 1;
+	if (fenv)
+	  T(call_fenv) (f, a, r, &ygot2, &exgot2);
+	else
+	  T(call_nofenv) (f, a, r, &ygot2, &exgot2);
+	secondcall = 0;
+	if (RT(asuint) (ygot) != RT(asuint) (ygot2))
+	  {
+	    fail = 1;
+	    cntfail++;
+	    T(printcall) (f, a);
+	    printf (" got %a then %a for same input\n", ygot, ygot2);
+	  }
+      }
+      cnt++;
+      int ok = use_mpfr
+		 ? T(call_mpfr_fix) (f, a, r, &want, ygot, exgot)
+		 : (fenv ? T(call_long_fenv) (f, a, r, &want, ygot, exgot)
+			 : T(call_long_nofenv) (f, a, r, &want, ygot, exgot));
+      if (!ok)
+	{
+	  int print = 0;
+	  double err = RT(ulperr) (ygot, &want, r);
+	  double abserr = fabs (err);
+	  // TODO: count errors below accuracy limit.
+	  if (abserr > 0)
+	    cnt1++;
+	  if (abserr > 1)
+	    cnt2++;
+	  if (abserr > conf->errlim)
+	    {
+	      print = 1;
+	      if (!fail)
+		{
+		  fail = 1;
+		  cntfail++;
+		}
+	    }
+	  if (abserr > maxerr)
+	    {
+	      maxerr = abserr;
+	      if (!conf->quiet && abserr > conf->softlim)
+		print = 1;
+	    }
+	  if (print)
+	    {
+	      T(printcall) (f, a);
+	      // TODO: inf ulp handling
+	      printf (" got %a want %a %+g ulp err %g\n", ygot, want.y,
+		      want.tail, err);
+	    }
+	  int diff = fenv ? exgot ^ want.ex : 0;
+	  if (fenv && (diff & ~want.ex_may))
+	    {
+	      if (!fail)
+		{
+		  fail = 1;
+		  cntfail++;
+		}
+	      T(printcall) (f, a);
+	      printf (" is %a %+g ulp, got except 0x%0x", want.y, want.tail,
+		      exgot);
+	      if (diff & exgot)
+		printf (" wrongly set: 0x%x", diff & exgot);
+	      if (diff & ~exgot)
+		printf (" wrongly clear: 0x%x", diff & ~exgot);
+	      putchar ('\n');
+	    }
+	}
+      if (cnt >= conf->n)
+	break;
+      if (!conf->quiet && cnt % 0x100000 == 0)
+	printf ("progress: %6.3f%% cnt %llu cnt1 %llu cnt2 %llu cntfail %llu "
+		"maxerr %g\n",
+		100.0 * cnt / conf->n, (unsigned long long) cnt,
+		(unsigned long long) cnt1, (unsigned long long) cnt2,
+		(unsigned long long) cntfail, maxerr);
+    }
+  double cc = cnt;
+  if (cntfail)
+    printf ("FAIL ");
+  else
+    printf ("PASS ");
+  T(printgen) (f, gen);
+  printf (" round %c errlim %g maxerr %g %s cnt %llu cnt1 %llu %g%% cnt2 %llu "
+	  "%g%% cntfail %llu %g%%\n",
+	  conf->rc, conf->errlim,
+	  maxerr, conf->r == FE_TONEAREST ? "+0.5" : "+1.0",
+	  (unsigned long long) cnt,
+	  (unsigned long long) cnt1, 100.0 * cnt1 / cc,
+	  (unsigned long long) cnt2, 100.0 * cnt2 / cc,
+	  (unsigned long long) cntfail, 100.0 * cntfail / cc);
+  return !!cntfail;
+}
diff --git a/libc/AOR_v20.02/math/tools/cos.sollya b/libc/AOR_v20.02/math/tools/cos.sollya
new file mode 100644
index 0000000000000..71d45965decb9
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/cos.sollya
@@ -0,0 +1,32 @@
+// polynomial for approximating cos(x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 8;   // polynomial degree
+a = -pi/4; // interval
+b = pi/4;
+
+// find even polynomial with minimal abs error compared to cos(x)
+
+f = cos(x);
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(f(x)-poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = 1;
+for i from 1 to deg/2 do {
+  p = roundcoefficients(approx(poly,2*i), [|D ...|]);
+  poly = poly + x^(2*i)*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/f(x), [a;b], 30));
+print("abs error:", accurateinfnorm(f(x)-poly(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/exp.sollya b/libc/AOR_v20.02/math/tools/exp.sollya
new file mode 100644
index 0000000000000..1877b0761197b
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/exp.sollya
@@ -0,0 +1,36 @@
+// polynomial for approximating e^x
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 5; // poly degree
+N = 128; // table entries
+b = log(2)/(2*N);  // interval
+b = b + b*0x1p-16; // increase interval for non-nearest rounding (TOINT_NARROW)
+a = -b;
+
+// find polynomial with minimal abs error
+
+// return p that minimizes |exp(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(exp(x)-poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first 2 coeffs are fixed, iteratively find optimal double prec coeffs
+poly = 1 + x;
+for i from 2 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/exp(x), [a;b], 30));
+print("abs error:", accurateinfnorm(exp(x)-poly(x), [a;b], 30));
+print("in [",a,b,"]");
+// double interval error for non-nearest rounding
+print("rel2 error:", accurateinfnorm(1-poly(x)/exp(x), [2*a;2*b], 30));
+print("abs2 error:", accurateinfnorm(exp(x)-poly(x), [2*a;2*b], 30));
+print("in [",2*a,2*b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/exp2.sollya b/libc/AOR_v20.02/math/tools/exp2.sollya
new file mode 100644
index 0000000000000..7980eefbff5ff
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/exp2.sollya
@@ -0,0 +1,49 @@
+// polynomial for approximating 2^x
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+// exp2f parameters
+deg = 3; // poly degree
+N = 32;  // table entries
+b = 1/(2*N); // interval
+a = -b;
+
+//// exp2 parameters
+//deg = 5; // poly degree
+//N = 128; // table entries
+//b = 1/(2*N); // interval
+//a = -b;
+
+// find polynomial with minimal relative error
+
+f = 2^x;
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|/|f(x)|
+approx = proc(poly,d) {
+  return remez(1 - poly(x)/f(x), deg-d, [a;b], x^d/f(x), 1e-10);
+};
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|
+approx_abs = proc(poly,d) {
+  return remez(f(x) - poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = 1;
+for i from 1 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+//  p = roundcoefficients(approx_abs(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/2^x, [a;b], 30));
+print("abs error:", accurateinfnorm(2^x-poly(x), [a;b], 30));
+print("in [",a,b,"]");
+// double interval error for non-nearest rounding:
+print("rel2 error:", accurateinfnorm(1-poly(x)/2^x, [2*a;2*b], 30));
+print("abs2 error:", accurateinfnorm(2^x-poly(x), [2*a;2*b], 30));
+print("in [",2*a,2*b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/log.sollya b/libc/AOR_v20.02/math/tools/log.sollya
new file mode 100644
index 0000000000000..41072395eb92a
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/log.sollya
@@ -0,0 +1,36 @@
+// polynomial for approximating log(1+x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 12; // poly degree
+// |log(1+x)| > 0x1p-4 outside the interval
+a = -0x1p-4;
+b =  0x1.09p-4;
+
+// find log(1+x)/x polynomial with minimal relative error
+// (minimal relative error polynomial for log(1+x) is the same * x)
+deg = deg-1; // because of /x
+
+// f = log(1+x)/x; using taylor series
+f = 0;
+for i from 0 to 60 do { f = f + (-x)^i/(i+1); };
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|/|f(x)|
+approx = proc(poly,d) {
+  return remez(1 - poly(x)/f(x), deg-d, [a;b], x^d/f(x), 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = 1;
+for i from 1 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/f(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/log2.sollya b/libc/AOR_v20.02/math/tools/log2.sollya
new file mode 100644
index 0000000000000..6b3e867b77a95
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/log2.sollya
@@ -0,0 +1,43 @@
+// polynomial for approximating log2(1+x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 11; // poly degree
+// |log2(1+x)| > 0x1p-4 outside the interval
+a = -0x1.5b51p-5;
+b =  0x1.6ab2p-5;
+
+ln2 = evaluate(log(2),0);
+invln2hi = double(1/ln2 + 0x1p21) - 0x1p21; // round away last 21 bits
+invln2lo = double(1/ln2 - invln2hi);
+
+// find log2(1+x)/x polynomial with minimal relative error
+// (minimal relative error polynomial for log2(1+x) is the same * x)
+deg = deg-1; // because of /x
+
+// f = log(1+x)/x; using taylor series
+f = 0;
+for i from 0 to 60 do { f = f + (-x)^i/(i+1); };
+f = f/ln2;
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|/|f(x)|
+approx = proc(poly,d) {
+  return remez(1 - poly(x)/f(x), deg-d, [a;b], x^d/f(x), 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = invln2hi + invln2lo;
+for i from 1 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("invln2hi:", invln2hi);
+print("invln2lo:", invln2lo);
+print("rel error:", accurateinfnorm(1-poly(x)/f(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/log2_abs.sollya b/libc/AOR_v20.02/math/tools/log2_abs.sollya
new file mode 100644
index 0000000000000..ecbc7e075003f
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/log2_abs.sollya
@@ -0,0 +1,42 @@
+// polynomial for approximating log2(1+x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 7; // poly degree
+// interval ~= 1/(2*N), where N is the table entries
+a= -0x1.f45p-8;
+b=  0x1.f45p-8;
+
+ln2 = evaluate(log(2),0);
+invln2hi = double(1/ln2 + 0x1p21) - 0x1p21; // round away last 21 bits
+invln2lo = double(1/ln2 - invln2hi);
+
+// find log2(1+x) polynomial with minimal absolute error
+f = log(1+x)/ln2;
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(f(x) - poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = x*(invln2lo + invln2hi);
+for i from 2 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("invln2hi:", invln2hi);
+print("invln2lo:", invln2lo);
+print("abs error:", accurateinfnorm(f(x)-poly(x), [a;b], 30));
+//// relative error computation fails if f(0)==0
+//// g = f(x)/x = log2(1+x)/x; using taylor series
+//g = 0;
+//for i from 0 to 60 do { g = g + (-x)^i/(i+1)/ln2; };
+//print("rel error:", accurateinfnorm(1-(poly(x)/x)/g(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/log_abs.sollya b/libc/AOR_v20.02/math/tools/log_abs.sollya
new file mode 100644
index 0000000000000..c12242364869e
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/log_abs.sollya
@@ -0,0 +1,36 @@
+// polynomial for approximating log(1+x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 6; // poly degree
+// interval ~= 1/(2*N), where N is the table entries
+a = -0x1.fp-9;
+b =  0x1.fp-9;
+
+// find log(1+x) polynomial with minimal absolute error
+f = log(1+x);
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(f(x) - poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = x;
+for i from 2 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("abs error:", accurateinfnorm(f(x)-poly(x), [a;b], 30));
+// relative error computation fails if f(0)==0
+// g = f(x)/x = log(1+x)/x; using taylor series
+g = 0;
+for i from 0 to 60 do { g = g + (-x)^i/(i+1); };
+print("rel error:", accurateinfnorm(1-poly(x)/x/g(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/plot.py b/libc/AOR_v20.02/math/tools/plot.py
new file mode 100755
index 0000000000000..611c99a9e69f2
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/plot.py
@@ -0,0 +1,62 @@
+#!/usr/bin/python
+
+# ULP error plot tool.
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+import numpy as np
+import matplotlib.pyplot as plt
+import sys
+import re
+
+# example usage:
+# build/bin/ulp -e .0001 log 0.5 2.0 2345678 | math/tools/plot.py
+
+def fhex(s):
+	return float.fromhex(s)
+
+def parse(f):
+	xs = []
+	gs = []
+	ys = []
+	es = []
+	# Has to match the format used in ulp.c
+	r = re.compile(r'[^ (]+\(([^ )]*)\) got ([^ ]+) want ([^ ]+) [^ ]+ ulp err ([^ ]+)')
+	for line in f:
+		m = r.match(line)
+		if m:
+			x = fhex(m.group(1))
+			g = fhex(m.group(2))
+			y = fhex(m.group(3))
+			e = float(m.group(4))
+			xs.append(x)
+			gs.append(g)
+			ys.append(y)
+			es.append(e)
+		elif line.startswith('PASS') or line.startswith('FAIL'):
+			# Print the summary line
+			print(line)
+	return xs, gs, ys, es
+
+def plot(xs, gs, ys, es):
+	if len(xs) < 2:
+		print('not enough samples')
+		return
+	a = min(xs)
+	b = max(xs)
+	fig, (ax0,ax1) = plt.subplots(nrows=2)
+	es = np.abs(es) # ignore the sign
+	emax = max(es)
+	ax0.text(a+(b-a)*0.7, emax*0.8, '%s\n%g'%(emax.hex(),emax))
+	ax0.plot(xs,es,'r.')
+	ax0.grid()
+	ax1.plot(xs,ys,'r.',label='want')
+	ax1.plot(xs,gs,'b.',label='got')
+	ax1.grid()
+	ax1.legend()
+	plt.show()
+
+xs, gs, ys, es = parse(sys.stdin)
+plot(xs, gs, ys, es)
diff --git a/libc/AOR_v20.02/math/tools/remez.jl b/libc/AOR_v20.02/math/tools/remez.jl
new file mode 100755
index 0000000000000..bf934f4a7c115
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/remez.jl
@@ -0,0 +1,1335 @@
+#!/usr/bin/env julia
+# -*- julia -*-
+
+# remez.jl - implementation of the Remez algorithm for polynomial approximation
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+import Base.\
+
+# ----------------------------------------------------------------------
+# Helper functions to cope with different Julia versions.
+if VERSION >= v"0.7.0"
+    array1d(T, d) = Array{T, 1}(undef, d)
+    array2d(T, d1, d2) = Array{T, 2}(undef, d1, d2)
+else
+    array1d(T, d) = Array(T, d)
+    array2d(T, d1, d2) = Array(T, d1, d2)
+end
+if VERSION < v"0.5.0"
+    String = ASCIIString
+end
+if VERSION >= v"0.6.0"
+    # Use Base.invokelatest to run functions made using eval(), to
+    # avoid "world age" error
+    run(f, x...) = Base.invokelatest(f, x...)
+else
+    # Prior to 0.6.0, invokelatest doesn't exist (but fortunately the
+    # world age problem also doesn't seem to exist)
+    run(f, x...) = f(x...)
+end
+
+# ----------------------------------------------------------------------
+# Global variables configured by command-line options.
+floatsuffix = "" # adjusted by --floatsuffix
+xvarname = "x" # adjusted by --variable
+epsbits = 256 # adjusted by --bits
+debug_facilities = Set() # adjusted by --debug
+full_output = false # adjusted by --full
+array_format = false # adjusted by --array
+preliminary_commands = array1d(String, 0) # adjusted by --pre
+
+# ----------------------------------------------------------------------
+# Diagnostic and utility functions.
+
+# Enable debugging printouts from a particular subpart of this
+# program.
+#
+# Arguments:
+#    facility   Name of the facility to debug. For a list of facility names,
+#               look through the code for calls to debug().
+#
+# Return value is a BigFloat.
+function enable_debug(facility)
+    push!(debug_facilities, facility)
+end
+
+# Print a diagnostic.
+#
+# Arguments:
+#    facility   Name of the facility for which this is a debug message.
+#    printargs  Arguments to println() if debugging of that facility is
+#               enabled.
+macro debug(facility, printargs...)
+    printit = quote
+        print("[", $facility, "] ")
+    end
+    for arg in printargs
+        printit = quote
+            $printit
+            print($(esc(arg)))
+        end
+    end
+    return quote
+        if $facility in debug_facilities
+            $printit
+            println()
+        end
+    end
+end
+
+# Evaluate a polynomial.
+
+# Arguments:
+#    coeffs   Array of BigFloats giving the coefficients of the polynomial.
+#             Starts with the constant term, i.e. coeffs[i] is the
+#             coefficient of x^(i-1) (because Julia arrays are 1-based).
+#    x        Point at which to evaluate the polynomial.
+#
+# Return value is a BigFloat.
+function poly_eval(coeffs::Array{BigFloat}, x::BigFloat)
+    n = length(coeffs)
+    if n == 0
+        return BigFloat(0)
+    elseif n == 1
+        return coeffs[1]
+    else
+        return coeffs[1] + x * poly_eval(coeffs[2:n], x)
+    end
+end
+
+# Evaluate a rational function.
+
+# Arguments:
+#    ncoeffs  Array of BigFloats giving the coefficients of the numerator.
+#             Starts with the constant term, and 1-based, as above.
+#    dcoeffs  Array of BigFloats giving the coefficients of the denominator.
+#             Starts with the constant term, and 1-based, as above.
+#    x        Point at which to evaluate the function.
+#
+# Return value is a BigFloat.
+function ratfn_eval(ncoeffs::Array{BigFloat}, dcoeffs::Array{BigFloat},
+                    x::BigFloat)
+    return poly_eval(ncoeffs, x) / poly_eval(dcoeffs, x)
+end
+
+# Format a BigFloat into an appropriate output format.
+# Arguments:
+#    x        BigFloat to format.
+#
+# Return value is a string.
+function float_to_str(x)
+    return string(x) * floatsuffix
+end
+
+# Format a polynomial into an arithmetic expression, for pasting into
+# other tools such as gnuplot.
+
+# Arguments:
+#    coeffs   Array of BigFloats giving the coefficients of the polynomial.
+#             Starts with the constant term, and 1-based, as above.
+#
+# Return value is a string.
+function poly_to_string(coeffs::Array{BigFloat})
+    n = length(coeffs)
+    if n == 0
+        return "0"
+    elseif n == 1
+        return float_to_str(coeffs[1])
+    else
+        return string(float_to_str(coeffs[1]), "+", xvarname, "*(",
+                      poly_to_string(coeffs[2:n]), ")")
+    end
+end
+
+# Format a rational function into a string.
+
+# Arguments:
+#    ncoeffs  Array of BigFloats giving the coefficients of the numerator.
+#             Starts with the constant term, and 1-based, as above.
+#    dcoeffs  Array of BigFloats giving the coefficients of the denominator.
+#             Starts with the constant term, and 1-based, as above.
+#
+# Return value is a string.
+function ratfn_to_string(ncoeffs::Array{BigFloat}, dcoeffs::Array{BigFloat})
+    if length(dcoeffs) == 1 && dcoeffs[1] == 1
+        # Special case: if the denominator is just 1, leave it out.
+        return poly_to_string(ncoeffs)
+    else
+        return string("(", poly_to_string(ncoeffs), ")/(",
+                      poly_to_string(dcoeffs), ")")
+    end
+end
+
+# Format a list of x,y pairs into a string.
+
+# Arguments:
+#    xys      Array of (x,y) pairs of BigFloats.
+#
+# Return value is a string.
+function format_xylist(xys::Array{Tuple{BigFloat,BigFloat}})
+    return ("[\n" *
+            join(["  "*string(x)*" -> "*string(y) for (x,y) in xys], "\n") *
+            "\n]")
+end
+
+# ----------------------------------------------------------------------
+# Matrix-equation solver for matrices of BigFloat.
+#
+# I had hoped that Julia's type-genericity would allow me to solve the
+# matrix equation Mx=V by just writing 'M \ V'. Unfortunately, that
+# works by translating the inputs into double precision and handing
+# off to an optimised library, which misses the point when I have a
+# matrix and vector of BigFloat and want my result in _better_ than
+# double precision. So I have to implement my own specialisation of
+# the \ operator for that case.
+#
+# Fortunately, the point of using BigFloats is that we have precision
+# to burn, so I can do completely naïve Gaussian elimination without
+# worrying about instability.
+
+# Arguments:
+#    matrix_in    2-dimensional array of BigFloats, representing a matrix M
+#                 in row-first order, i.e. matrix_in[r,c] represents the
+#                 entry in row r col c.
+#    vector_in    1-dimensional array of BigFloats, representing a vector V.
+#
+# Return value: a 1-dimensional array X of BigFloats, satisfying M X = V.
+#
+# Expects the input to be an invertible square matrix and a vector of
+# the corresponding size, on pain of failing an assertion.
+function \(matrix_in :: Array{BigFloat,2},
+           vector_in :: Array{BigFloat,1})
+    # Copy the inputs, because we'll be mutating them as we go.
+    M = copy(matrix_in)
+    V = copy(vector_in)
+
+    # Input consistency criteria: matrix is square, and vector has
+    # length to match.
+    n = length(V)
+    @assert(n > 0)
+    @assert(size(M) == (n,n))
+
+    @debug("gausselim", "starting, n=", n)
+
+    for i = 1:1:n
+        # Straightforward Gaussian elimination: find the largest
+        # non-zero entry in column i (and in a row we haven't sorted
+        # out already), swap it into row i, scale that row to
+        # normalise it to 1, then zero out the rest of the column by
+        # subtracting a multiple of that row from each other row.
+
+        @debug("gausselim", "matrix=", repr(M))
+        @debug("gausselim", "vector=", repr(V))
+
+        # Find the best pivot.
+        bestrow = 0
+        bestval = 0
+        for j = i:1:n
+            if abs(M[j,i]) > bestval
+                bestrow = j
+                bestval = M[j,i]
+            end
+        end
+        @assert(bestrow > 0) # make sure we did actually find one
+
+        @debug("gausselim", "bestrow=", bestrow)
+
+        # Swap it into row i.
+        if bestrow != i
+            for k = 1:1:n
+                M[bestrow,k],M[i,k] = M[i,k],M[bestrow,k]
+            end
+            V[bestrow],V[i] = V[i],V[bestrow]
+        end
+
+        # Scale that row so that M[i,i] becomes 1.
+        divisor = M[i,i]
+        for k = 1:1:n
+            M[i,k] = M[i,k] / divisor
+        end
+        V[i] = V[i] / divisor
+        @assert(M[i,i] == 1)
+
+        # Zero out all other entries in column i, by subtracting
+        # multiples of this row.
+        for j = 1:1:n
+            if j != i
+                factor = M[j,i]
+                for k = 1:1:n
+                    M[j,k] = M[j,k] - M[i,k] * factor
+                end
+                V[j] = V[j] - V[i] * factor
+                @assert(M[j,i] == 0)
+            end
+        end
+    end
+
+    @debug("gausselim", "matrix=", repr(M))
+    @debug("gausselim", "vector=", repr(V))
+    @debug("gausselim", "done!")
+
+    # Now we're done: M is the identity matrix, so the equation Mx=V
+    # becomes just x=V, i.e. V is already exactly the vector we want
+    # to return.
+    return V
+end
+
+# ----------------------------------------------------------------------
+# Least-squares fitting of a rational function to a set of (x,y)
+# points.
+#
+# We use this to get an initial starting point for the Remez
+# iteration. Therefore, it doesn't really need to be particularly
+# accurate; it only needs to be good enough to wiggle back and forth
+# across the target function the right number of times (so as to give
+# enough error extrema to start optimising from) and not have any
+# poles in the target interval.
+#
+# Least-squares fitting of a _polynomial_ is actually a sensible thing
+# to do, and minimises the rms error. Doing the following trick with a
+# rational function P/Q is less sensible, because it cannot be made to
+# minimise the error function (P/Q-f)^2 that you actually wanted;
+# instead it minimises (P-fQ)^2. But that should be good enough to
+# have the properties described above.
+#
+# Some theory: suppose you're trying to choose a set of parameters a_i
+# so as to minimise the sum of squares of some error function E_i.
+# Basic calculus says, if you do this in one variable, just
+# differentiate and solve for zero. In this case, that works fine even
+# with multiple variables, because you _partially_ differentiate with
+# respect to each a_i, giving a system of equations, and that system
+# turns out to be linear so we just solve it as a matrix.
+#
+# In this case, our parameters are the coefficients of P and Q; to
+# avoid underdetermining the system we'll fix Q's constant term at 1,
+# so that our error function (as described above) is
+#
+# E = \sum (p_0 + p_1 x + ... + p_n x^n - y - y q_1 x - ... - y q_d x^d)^2
+#
+# where the sum is over all (x,y) coordinate pairs. Setting dE/dp_j=0
+# (for each j) gives an equation of the form
+#
+# 0 = \sum 2(p_0 + p_1 x + ... + p_n x^n - y - y q_1 x - ... - y q_d x^d) x^j
+#
+# and setting dE/dq_j=0 gives one of the form
+#
+# 0 = \sum 2(p_0 + p_1 x + ... + p_n x^n - y - y q_1 x - ... - y q_d x^d) y x^j
+#
+# And both of those row types, treated as multivariate linear
+# equations in the p,q values, have each coefficient being a value of
+# the form \sum x^i, \sum y x^i or \sum y^2 x^i, for various i. (Times
+# a factor of 2, but we can throw that away.) So we can go through the
+# list of input coordinates summing all of those things, and then we
+# have enough information to construct our matrix and solve it
+# straight off for the rational function coefficients.
+
+# Arguments:
+#    f        The function to be approximated. Maps BigFloat -> BigFloat.
+#    xvals    Array of BigFloats, giving the list of x-coordinates at which
+#             to evaluate f.
+#    n        Degree of the numerator polynomial of the desired rational
+#             function.
+#    d        Degree of the denominator polynomial of the desired rational
+#             function.
+#    w        Error-weighting function. Takes two BigFloat arguments x,y
+#             and returns a scaling factor for the error at that location.
+#             A larger value indicates that the error should be given
+#             greater weight in the square sum we try to minimise.
+#             If unspecified, defaults to giving everything the same weight.
+#
+# Return values: a pair of arrays of BigFloats (N,D) giving the
+# coefficients of the returned rational function. N has size n+1; D
+# has size d+1. Both start with the constant term, i.e. N[i] is the
+# coefficient of x^(i-1) (because Julia arrays are 1-based). D[1] will
+# be 1.
+function ratfn_leastsquares(f::Function, xvals::Array{BigFloat}, n, d,
+                            w = (x,y)->BigFloat(1))
+    # Accumulate sums of x^i y^j, for j={0,1,2} and a range of x.
+    # Again because Julia arrays are 1-based, we'll have sums[i,j]
+    # being the sum of x^(i-1) y^(j-1).
+    maxpow = max(n,d) * 2 + 1
+    sums = zeros(BigFloat, maxpow, 3)
+    for x = xvals
+        y = f(x)
+        weight = w(x,y)
+        for i = 1:1:maxpow
+            for j = 1:1:3
+                sums[i,j] += x^(i-1) * y^(j-1) * weight
+            end
+        end
+    end
+
+    @debug("leastsquares", "sums=", repr(sums))
+
+    # Build the matrix. We're solving n+d+1 equations in n+d+1
+    # unknowns. (We actually have to return n+d+2 coefficients, but
+    # one of them is hardwired to 1.)
+    matrix = array2d(BigFloat, n+d+1, n+d+1)
+    vector = array1d(BigFloat, n+d+1)
+    for i = 0:1:n
+        # Equation obtained by differentiating with respect to p_i,
+        # i.e. the numerator coefficient of x^i.
+        row = 1+i
+        for j = 0:1:n
+            matrix[row, 1+j] = sums[1+i+j, 1]
+        end
+        for j = 1:1:d
+            matrix[row, 1+n+j] = -sums[1+i+j, 2]
+        end
+        vector[row] = sums[1+i, 2]
+    end
+    for i = 1:1:d
+        # Equation obtained by differentiating with respect to q_i,
+        # i.e. the denominator coefficient of x^i.
+        row = 1+n+i
+        for j = 0:1:n
+            matrix[row, 1+j] = sums[1+i+j, 2]
+        end
+        for j = 1:1:d
+            matrix[row, 1+n+j] = -sums[1+i+j, 3]
+        end
+        vector[row] = sums[1+i, 3]
+    end
+
+    @debug("leastsquares", "matrix=", repr(matrix))
+    @debug("leastsquares", "vector=", repr(vector))
+
+    # Solve the matrix equation.
+    all_coeffs = matrix \ vector
+
+    @debug("leastsquares", "all_coeffs=", repr(all_coeffs))
+
+    # And marshal the results into two separate polynomial vectors to
+    # return.
+    ncoeffs = all_coeffs[1:n+1]
+    dcoeffs = vcat([1], all_coeffs[n+2:n+d+1])
+    return (ncoeffs, dcoeffs)
+end
+
+# ----------------------------------------------------------------------
+# Golden-section search to find a maximum of a function.
+
+# Arguments:
+#    f        Function to be maximised/minimised. Maps BigFloat -> BigFloat.
+#    a,b,c    BigFloats bracketing a maximum of the function.
+#
+# Expects:
+#    a,b,c are in order (either a<=b<=c or c<=b<=a)
+#    a != c             (but b can equal one or the other if it wants to)
+#    f(a) <= f(b) >= f(c)
+#
+# Return value is an (x,y) pair of BigFloats giving the extremal input
+# and output. (That is, y=f(x).)
+function goldensection(f::Function, a::BigFloat, b::BigFloat, c::BigFloat)
+    # Decide on a 'good enough' threshold.
+    threshold = abs(c-a) * 2^(-epsbits/2)
+
+    # We'll need the golden ratio phi, of course. Or rather, in this
+    # case, we need 1/phi = 0.618...
+    one_over_phi = 2 / (1 + sqrt(BigFloat(5)))
+
+    # Flip round the interval endpoints so that the interval [a,b] is
+    # at least as large as [b,c]. (Then we can always pick our new
+    # point in [a,b] without having to handle lots of special cases.)
+    if abs(b-a) < abs(c-a)
+        a,  c  = c,  a
+    end
+
+    # Evaluate the function at the initial points.
+    fa = f(a)
+    fb = f(b)
+    fc = f(c)
+
+    @debug("goldensection", "starting")
+
+    while abs(c-a) > threshold
+        @debug("goldensection", "a: ", a, " -> ", fa)
+        @debug("goldensection", "b: ", b, " -> ", fb)
+        @debug("goldensection", "c: ", c, " -> ", fc)
+
+        # Check invariants.
+        @assert(a <= b <= c || c <= b <= a)
+        @assert(fa <= fb >= fc)
+
+        # Subdivide the larger of the intervals [a,b] and [b,c]. We've
+        # arranged that this is always [a,b], for simplicity.
+        d = a + (b-a) * one_over_phi
+
+        # Now we have an interval looking like this (possibly
+        # reversed):
+        #
+        #    a            d       b            c
+        #
+        # and we know f(b) is bigger than either f(a) or f(c). We have
+        # two cases: either f(d) > f(b), or vice versa. In either
+        # case, we can narrow to an interval of 1/phi the size, and
+        # still satisfy all our invariants (three ordered points,
+        # [a,b] at least the width of [b,c], f(a)<=f(b)>=f(c)).
+        fd = f(d)
+        @debug("goldensection", "d: ", d, " -> ", fd)
+        if fd > fb
+            a,  b,  c  = a,  d,  b
+            fa, fb, fc = fa, fd, fb
+            @debug("goldensection", "adb case")
+        else
+            a,  b,  c  = c,  b,  d
+            fa, fb, fc = fc, fb, fd
+            @debug("goldensection", "cbd case")
+        end
+    end
+
+    @debug("goldensection", "done: ", b, " -> ", fb)
+    return (b, fb)
+end
+
+# ----------------------------------------------------------------------
+# Find the extrema of a function within a given interval.
+
+# Arguments:
+#    f         The function to be approximated. Maps BigFloat -> BigFloat.
+#    grid      A set of points at which to evaluate f. Must be high enough
+#              resolution to make extrema obvious.
+#
+# Returns an array of (x,y) pairs of BigFloats, with each x,y giving
+# the extremum location and its value (i.e. y=f(x)).
+function find_extrema(f::Function, grid::Array{BigFloat})
+    len = length(grid)
+    extrema = array1d(Tuple{BigFloat, BigFloat}, 0)
+    for i = 1:1:len
+        # We have to provide goldensection() with three points
+        # bracketing the extremum. If the extremum is at one end of
+        # the interval, then the only way we can do that is to set two
+        # of the points equal (which goldensection() will cope with).
+        prev = max(1, i-1)
+        next = min(i+1, len)
+
+        # Find our three pairs of (x,y) coordinates.
+        xp, xi, xn = grid[prev], grid[i], grid[next]
+        yp, yi, yn = f(xp), f(xi), f(xn)
+
+        # See if they look like an extremum, and if so, ask
+        # goldensection() to give a more exact location for it.
+        if yp <= yi >= yn
+            push!(extrema, goldensection(f, xp, xi, xn))
+        elseif yp >= yi <= yn
+            x, y = goldensection(x->-f(x), xp, xi, xn)
+            push!(extrema, (x, -y))
+        end
+    end
+    return extrema
+end
+
+# ----------------------------------------------------------------------
+# Winnow a list of a function's extrema to give a subsequence of a
+# specified length, with the extrema in the subsequence alternating
+# signs, and with the smallest absolute value of an extremum in the
+# subsequence as large as possible.
+#
+# We do this using a dynamic-programming approach. We work along the
+# provided array of extrema, and at all times, we track the best set
+# of extrema we have so far seen for each possible (length, sign of
+# last extremum) pair. Each new extremum is evaluated to see whether
+# it can be added to any previously seen best subsequence to make a
+# new subsequence that beats the previous record holder in its slot.
+
+# Arguments:
+#    extrema   An array of (x,y) pairs of BigFloats giving the input extrema.
+#    n         Number of extrema required as output.
+#
+# Returns a new array of (x,y) pairs which is a subsequence of the
+# original sequence. (So, in particular, if the input was sorted by x
+# then so will the output be.)
+function winnow_extrema(extrema::Array{Tuple{BigFloat,BigFloat}}, n)
+    # best[i,j] gives the best sequence so far of length i and with
+    # sign j (where signs are coded as 1=positive, 2=negative), in the
+    # form of a tuple (cost, actual array of x,y pairs).
+    best = fill((BigFloat(0), array1d(Tuple{BigFloat,BigFloat}, 0)), n, 2)
+
+    for (x,y) = extrema
+        if y > 0
+            sign = 1
+        elseif y < 0
+            sign = 2
+        else
+            # A zero-valued extremum cannot possibly contribute to any
+            # optimal sequence, so we simply ignore it!
+            continue
+        end
+
+        for i = 1:1:n
+            # See if we can create a new entry for best[i,sign] by
+            # appending our current (x,y) to some previous thing.
+            if i == 1
+                # Special case: we don't store a best zero-length
+                # sequence :-)
+                candidate = (abs(y), [(x,y)])
+            else
+                othersign = 3-sign # map 1->2 and 2->1
+                oldscore, oldlist = best[i-1, othersign]
+                newscore = min(abs(y), oldscore)
+                newlist = vcat(oldlist, [(x,y)])
+                candidate = (newscore, newlist)
+            end
+            # If our new candidate improves on the previous value of
+            # best[i,sign], then replace it.
+            if candidate[1] > best[i,sign][1]
+                best[i,sign] = candidate
+            end
+        end
+    end
+
+    # Our ultimate return value has to be either best[n,1] or
+    # best[n,2], but it could be either. See which one has the higher
+    # score.
+    if best[n,1][1] > best[n,2][1]
+        ret = best[n,1][2]
+    else
+        ret = best[n,2][2]
+    end
+    # Make sure we did actually _find_ a good answer.
+    @assert(length(ret) == n)
+    return ret
+end
+
+# ----------------------------------------------------------------------
+# Construct a rational-function approximation with equal and
+# alternating weighted deviation at a specific set of x-coordinates.
+
+# Arguments:
+#    f         The function to be approximated. Maps BigFloat -> BigFloat.
+#    coords    An array of BigFloats giving the x-coordinates. There should
+#              be n+d+2 of them.
+#    n, d      The degrees of the numerator and denominator of the desired
+#              approximation.
+#    prev_err  A plausible value for the alternating weighted deviation.
+#              (Required to kickstart a binary search in the nonlinear case;
+#              see comments below.)
+#    w         Error-weighting function. Takes two BigFloat arguments x,y
+#              and returns a scaling factor for the error at that location.
+#              The returned approximation R should have the minimum possible
+#              maximum value of abs((f(x)-R(x)) * w(x,f(x))). Optional
+#              parameter, defaulting to the always-return-1 function.
+#
+# Return values: a pair of arrays of BigFloats (N,D) giving the
+# coefficients of the returned rational function. N has size n+1; D
+# has size d+1. Both start with the constant term, i.e. N[i] is the
+# coefficient of x^(i-1) (because Julia arrays are 1-based). D[1] will
+# be 1.
+function ratfn_equal_deviation(f::Function, coords::Array{BigFloat},
+                               n, d, prev_err::BigFloat,
+                               w = (x,y)->BigFloat(1))
+    @debug("equaldev", "n=", n, " d=", d, " coords=", repr(coords))
+    @assert(length(coords) == n+d+2)
+
+    if d == 0
+        # Special case: we're after a polynomial. In this case, we
+        # have the particularly easy job of just constructing and
+        # solving a system of n+2 linear equations, to find the n+1
+        # coefficients of the polynomial and also the amount of
+        # deviation at the specified coordinates. Each equation is of
+        # the form
+        #
+        #   p_0 x^0 + p_1 x^1 + ... + p_n x^n ± e/w(x) = f(x)
+        #
+        # in which the p_i and e are the variables, and the powers of
+        # x and calls to w and f are the coefficients.
+
+        matrix = array2d(BigFloat, n+2, n+2)
+        vector = array1d(BigFloat, n+2)
+        currsign = +1
+        for i = 1:1:n+2
+            x = coords[i]
+            for j = 0:1:n
+                matrix[i,1+j] = x^j
+            end
+            y = f(x)
+            vector[i] = y
+            matrix[i, n+2] = currsign / w(x,y)
+            currsign = -currsign
+        end
+
+        @debug("equaldev", "matrix=", repr(matrix))
+        @debug("equaldev", "vector=", repr(vector))
+
+        outvector = matrix \ vector
+
+        @debug("equaldev", "outvector=", repr(outvector))
+
+        ncoeffs = outvector[1:n+1]
+        dcoeffs = [BigFloat(1)]
+        return ncoeffs, dcoeffs
+    else
+        # For a nontrivial rational function, the system of equations
+        # we need to solve becomes nonlinear, because each equation
+        # now takes the form
+        #
+        #   p_0 x^0 + p_1 x^1 + ... + p_n x^n
+        #   --------------------------------- ± e/w(x) = f(x)
+        #     x^0 + q_1 x^1 + ... + q_d x^d
+        #
+        # and multiplying up by the denominator gives you a lot of
+        # terms containing e × q_i. So we can't do this the really
+        # easy way using a matrix equation as above.
+        #
+        # Fortunately, this is a fairly easy kind of nonlinear system.
+        # The equations all become linear if you switch to treating e
+        # as a constant, so a reasonably sensible approach is to pick
+        # a candidate value of e, solve all but one of the equations
+        # for the remaining unknowns, and then see what the error
+        # turns out to be in the final equation. The Chebyshev
+        # alternation theorem guarantees that that error in the last
+        # equation will be anti-monotonic in the input e, so we can
+        # just binary-search until we get the two as close to equal as
+        # we need them.
+
+        function try_e(e)
+            # Try a given value of e, derive the coefficients of the
+            # resulting rational function by setting up equations
+            # based on the first n+d+1 of the n+d+2 coordinates, and
+            # see what the error turns out to be at the final
+            # coordinate.
+            matrix = array2d(BigFloat, n+d+1, n+d+1)
+            vector = array1d(BigFloat, n+d+1)
+            currsign = +1
+            for i = 1:1:n+d+1
+                x = coords[i]
+                y = f(x)
+                y_adj = y - currsign * e / w(x,y)
+                for j = 0:1:n
+                    matrix[i,1+j] = x^j
+                end
+                for j = 1:1:d
+                    matrix[i,1+n+j] = -x^j * y_adj
+                end
+                vector[i] = y_adj
+                currsign = -currsign
+            end
+
+            @debug("equaldev", "trying e=", e)
+            @debug("equaldev", "matrix=", repr(matrix))
+            @debug("equaldev", "vector=", repr(vector))
+
+            outvector = matrix \ vector
+
+            @debug("equaldev", "outvector=", repr(outvector))
+
+            ncoeffs = outvector[1:n+1]
+            dcoeffs = vcat([BigFloat(1)], outvector[n+2:n+d+1])
+
+            x = coords[n+d+2]
+            y = f(x)
+            last_e = (ratfn_eval(ncoeffs, dcoeffs, x) - y) * w(x,y) * -currsign
+
+            @debug("equaldev", "last e=", last_e)
+
+            return ncoeffs, dcoeffs, last_e
+        end
+
+        threshold = 2^(-epsbits/2) # convergence threshold
+
+        # Start by trying our previous iteration's error value. This
+        # value (e0) will be one end of our binary-search interval,
+        # and whatever it caused the last point's error to be, that
+        # (e1) will be the other end.
+        e0 = prev_err
+        @debug("equaldev", "e0 = ", e0)
+        nc, dc, e1 = try_e(e0)
+        @debug("equaldev", "e1 = ", e1)
+        if abs(e1-e0) <= threshold
+            # If we're _really_ lucky, we hit the error right on the
+            # nose just by doing that!
+            return nc, dc
+        end
+        s = sign(e1-e0)
+        @debug("equaldev", "s = ", s)
+
+        # Verify by assertion that trying our other interval endpoint
+        # e1 gives a value that's wrong in the other direction.
+        # (Otherwise our binary search won't get a sensible answer at
+        # all.)
+        nc, dc, e2 = try_e(e1)
+        @debug("equaldev", "e2 = ", e2)
+        @assert(sign(e2-e1) == -s)
+
+        # Now binary-search until our two endpoints narrow enough.
+        local emid
+        while abs(e1-e0) > threshold
+            emid = (e1+e0)/2
+            nc, dc, enew = try_e(emid)
+            if sign(enew-emid) == s
+                e0 = emid
+            else
+                e1 = emid
+            end
+        end
+
+        @debug("equaldev", "final e=", emid)
+        return nc, dc
+    end
+end
+
+# ----------------------------------------------------------------------
+# Top-level function to find a minimax rational-function approximation.
+
+# Arguments:
+#    f         The function to be approximated. Maps BigFloat -> BigFloat.
+#    interval  A pair of BigFloats giving the endpoints of the interval
+#              (in either order) on which to approximate f.
+#    n, d      The degrees of the numerator and denominator of the desired
+#              approximation.
+#    w         Error-weighting function. Takes two BigFloat arguments x,y
+#              and returns a scaling factor for the error at that location.
+#              The returned approximation R should have the minimum possible
+#              maximum value of abs((f(x)-R(x)) * w(x,f(x))). Optional
+#              parameter, defaulting to the always-return-1 function.
+#
+# Return values: a tuple (N,D,E,X), where
+
+#    N,D       A pair of arrays of BigFloats giving the coefficients
+#              of the returned rational function. N has size n+1; D
+#              has size d+1. Both start with the constant term, i.e.
+#              N[i] is the coefficient of x^(i-1) (because Julia
+#              arrays are 1-based). D[1] will be 1.
+#    E         The maximum weighted error (BigFloat).
+#    X         An array of pairs of BigFloats giving the locations of n+2
+#              points and the weighted error at each of those points. The
+#              weighted error values will have alternating signs, which
+#              means that the Chebyshev alternation theorem guarantees
+#              that any other function of the same degree must exceed
+#              the error of this one at at least one of those points.
+function ratfn_minimax(f::Function, interval::Tuple{BigFloat,BigFloat}, n, d,
+                       w = (x,y)->BigFloat(1))
+    # We start off by finding a least-squares approximation. This
+    # doesn't need to be perfect, but if we can get it reasonably good
+    # then it'll save iterations in the refining stage.
+    #
+    # Least-squares approximations tend to look nicer in a minimax
+    # sense if you evaluate the function at a big pile of Chebyshev
+    # nodes rather than uniformly spaced points. These values will
+    # also make a good grid to use for the initial search for error
+    # extrema, so we'll keep them around for that reason too.
+
+    # Construct the grid.
+    lo, hi = minimum(interval), maximum(interval)
+    local grid
+    let
+        mid = (hi+lo)/2
+        halfwid = (hi-lo)/2
+        nnodes = 16 * (n+d+1)
+        pi = 2*asin(BigFloat(1))
+        grid = [ mid - halfwid * cos(pi*i/nnodes) for i=0:1:nnodes ]
+    end
+
+    # Find the initial least-squares approximation.
+    (nc, dc) = ratfn_leastsquares(f, grid, n, d, w)
+    @debug("minimax", "initial leastsquares approx = ",
+           ratfn_to_string(nc, dc))
+
+    # Threshold of convergence. We stop when the relative difference
+    # between the min and max (winnowed) error extrema is less than
+    # this.
+    #
+    # This is set to the cube root of machine epsilon on a more or
+    # less empirical basis, because the rational-function case will
+    # not converge reliably if you set it to only the square root.
+    # (Repeatable by using the --test mode.) On the assumption that
+    # input and output error in each iteration can be expected to be
+    # related by a simple power law (because it'll just be down to how
+    # many leading terms of a Taylor series are zero), the cube root
+    # was the next thing to try.
+    threshold = 2^(-epsbits/3)
+
+    # Main loop.
+    while true
+        # Find all the error extrema we can.
+        function compute_error(x)
+            real_y = f(x)
+            approx_y = ratfn_eval(nc, dc, x)
+            return (approx_y - real_y) * w(x, real_y)
+        end
+        extrema = find_extrema(compute_error, grid)
+        @debug("minimax", "all extrema = ", format_xylist(extrema))
+
+        # Winnow the extrema down to the right number, and ensure they
+        # have alternating sign.
+        extrema = winnow_extrema(extrema, n+d+2)
+        @debug("minimax", "winnowed extrema = ", format_xylist(extrema))
+
+        # See if we've finished.
+        min_err = minimum([abs(y) for (x,y) = extrema])
+        max_err = maximum([abs(y) for (x,y) = extrema])
+        variation = (max_err - min_err) / max_err
+        @debug("minimax", "extremum variation = ", variation)
+        if variation < threshold
+            @debug("minimax", "done!")
+            return nc, dc, max_err, extrema
+        end
+
+        # If not, refine our function by equalising the error at the
+        # extrema points, and go round again.
+        (nc, dc) = ratfn_equal_deviation(f, map(x->x[1], extrema),
+                                         n, d, max_err, w)
+        @debug("minimax", "refined approx = ", ratfn_to_string(nc, dc))
+    end
+end
+
+# ----------------------------------------------------------------------
+# Check if a polynomial is well-conditioned for accurate evaluation in
+# a given interval by Horner's rule.
+#
+# This is true if at every step where Horner's rule computes
+# (coefficient + x*value_so_far), the constant coefficient you're
+# adding on is of larger magnitude than the x*value_so_far operand.
+# And this has to be true for every x in the interval.
+#
+# Arguments:
+#    coeffs    The coefficients of the polynomial under test. Starts with
+#              the constant term, i.e. coeffs[i] is the coefficient of
+#              x^(i-1) (because Julia arrays are 1-based).
+#    lo, hi    The bounds of the interval.
+#
+# Return value: the largest ratio (x*value_so_far / coefficient), at
+# any step of evaluation, for any x in the interval. If this is less
+# than 1, the polynomial is at least somewhat well-conditioned;
+# ideally you want it to be more like 1/8 or 1/16 or so, so that the
+# relative rounding error accumulated at each step are reduced by
+# several factors of 2 when the next coefficient is added on.
+
+function wellcond(coeffs, lo, hi)
+    x = max(abs(lo), abs(hi))
+    worst = 0
+    so_far = 0
+    for i = length(coeffs):-1:1
+        coeff = abs(coeffs[i])
+        so_far *= x
+        if coeff != 0
+            thisval = so_far / coeff
+            worst = max(worst, thisval)
+            so_far += coeff
+        end
+    end
+    return worst
+end
+
+# ----------------------------------------------------------------------
+# Small set of unit tests.
+
+function test()
+    passes = 0
+    fails = 0
+
+    function approx_eq(x, y, limit=1e-6)
+        return abs(x - y) < limit
+    end
+
+    function test(condition)
+        if condition
+            passes += 1
+        else
+            println("fail")
+            fails += 1
+        end
+    end
+
+    # Test Gaussian elimination.
+    println("Gaussian test 1:")
+    m = BigFloat[1 1 2; 3 5 8; 13 34 21]
+    v = BigFloat[1, -1, 2]
+    ret = m \ v
+    println("  ",repr(ret))
+    test(approx_eq(ret[1], 109/26))
+    test(approx_eq(ret[2], -105/130))
+    test(approx_eq(ret[3], -31/26))
+
+    # Test leastsquares rational functions.
+    println("Leastsquares test 1:")
+    n = 10000
+    a = array1d(BigFloat, n+1)
+    for i = 0:1:n
+        a[1+i] = i/BigFloat(n)
+    end
+    (nc, dc) = ratfn_leastsquares(x->exp(x), a, 2, 2)
+    println("  ",ratfn_to_string(nc, dc))
+    for x = a
+        test(approx_eq(exp(x), ratfn_eval(nc, dc, x), 1e-4))
+    end
+
+    # Test golden section search.
+    println("Golden section test 1:")
+    x, y = goldensection(x->sin(x),
+                              BigFloat(0), BigFloat(1)/10, BigFloat(4))
+    println("  ", x, " -> ", y)
+    test(approx_eq(x, asin(BigFloat(1))))
+    test(approx_eq(y, 1))
+
+    # Test extrema-winnowing algorithm.
+    println("Winnow test 1:")
+    extrema = [(x, sin(20*x)*sin(197*x))
+               for x in BigFloat(0):BigFloat(1)/1000:BigFloat(1)]
+    winnowed = winnow_extrema(extrema, 12)
+    println("  ret = ", format_xylist(winnowed))
+    prevx, prevy = -1, 0
+    for (x,y) = winnowed
+        test(x > prevx)
+        test(y != 0)
+        test(prevy * y <= 0) # tolerates initial prevx having no sign
+        test(abs(y) > 0.9)
+        prevx, prevy = x, y
+    end
+
+    # Test actual minimax approximation.
+    println("Minimax test 1 (polynomial):")
+    (nc, dc, e, x) = ratfn_minimax(x->exp(x), (BigFloat(0), BigFloat(1)), 4, 0)
+    println("  ",e)
+    println("  ",ratfn_to_string(nc, dc))
+    test(0 < e < 1e-3)
+    for x = 0:BigFloat(1)/1000:1
+        test(abs(ratfn_eval(nc, dc, x) - exp(x)) <= e * 1.0000001)
+    end
+
+    println("Minimax test 2 (rational):")
+    (nc, dc, e, x) = ratfn_minimax(x->exp(x), (BigFloat(0), BigFloat(1)), 2, 2)
+    println("  ",e)
+    println("  ",ratfn_to_string(nc, dc))
+    test(0 < e < 1e-3)
+    for x = 0:BigFloat(1)/1000:1
+        test(abs(ratfn_eval(nc, dc, x) - exp(x)) <= e * 1.0000001)
+    end
+
+    println("Minimax test 3 (polynomial, weighted):")
+    (nc, dc, e, x) = ratfn_minimax(x->exp(x), (BigFloat(0), BigFloat(1)), 4, 0,
+                                   (x,y)->1/y)
+    println("  ",e)
+    println("  ",ratfn_to_string(nc, dc))
+    test(0 < e < 1e-3)
+    for x = 0:BigFloat(1)/1000:1
+        test(abs(ratfn_eval(nc, dc, x) - exp(x))/exp(x) <= e * 1.0000001)
+    end
+
+    println("Minimax test 4 (rational, weighted):")
+    (nc, dc, e, x) = ratfn_minimax(x->exp(x), (BigFloat(0), BigFloat(1)), 2, 2,
+                                   (x,y)->1/y)
+    println("  ",e)
+    println("  ",ratfn_to_string(nc, dc))
+    test(0 < e < 1e-3)
+    for x = 0:BigFloat(1)/1000:1
+        test(abs(ratfn_eval(nc, dc, x) - exp(x))/exp(x) <= e * 1.0000001)
+    end
+
+    println("Minimax test 5 (rational, weighted, odd degree):")
+    (nc, dc, e, x) = ratfn_minimax(x->exp(x), (BigFloat(0), BigFloat(1)), 2, 1,
+                                   (x,y)->1/y)
+    println("  ",e)
+    println("  ",ratfn_to_string(nc, dc))
+    test(0 < e < 1e-3)
+    for x = 0:BigFloat(1)/1000:1
+        test(abs(ratfn_eval(nc, dc, x) - exp(x))/exp(x) <= e * 1.0000001)
+    end
+
+    total = passes + fails
+    println(passes, " passes ", fails, " fails ", total, " total")
+end
+
+# ----------------------------------------------------------------------
+# Online help.
+function help()
+    print("""
+Usage:
+
+    remez.jl [options] <lo> <hi> <n> <d> <expr> [<weight>]
+
+Arguments:
+
+    <lo>, <hi>
+
+        Bounds of the interval on which to approximate the target
+        function. These are parsed and evaluated as Julia expressions,
+        so you can write things like '1/BigFloat(6)' to get an
+        accurate representation of 1/6, or '4*atan(BigFloat(1))' to
+        get pi. (Unfortunately, the obvious 'BigFloat(pi)' doesn't
+        work in Julia.)
+
+    <n>, <d>
+
+        The desired degree of polynomial(s) you want for your
+        approximation. These should be non-negative integers. If you
+        want a rational function as output, set <n> to the degree of
+        the numerator, and <d> the denominator. If you just want an
+        ordinary polynomial, set <d> to 0, and <n> to the degree of
+        the polynomial you want.
+
+    <expr>
+
+        A Julia expression giving the function to be approximated on
+        the interval. The input value is predefined as 'x' when this
+        expression is evaluated, so you should write something along
+        the lines of 'sin(x)' or 'sqrt(1+tan(x)^2)' etc.
+
+    <weight>
+
+        If provided, a Julia expression giving the weighting factor
+        for the approximation error. The output polynomial will
+        minimise the largest absolute value of (P-f) * w at any point
+        in the interval, where P is the value of the polynomial, f is
+        the value of the target function given by <expr>, and w is the
+        weight given by this function.
+
+        When this expression is evaluated, the input value to P and f
+        is predefined as 'x', and also the true output value f(x) is
+        predefined as 'y'. So you can minimise the relative error by
+        simply writing '1/y'.
+
+        If the <weight> argument is not provided, the default
+        weighting function always returns 1, so that the polynomial
+        will minimise the maximum absolute error |P-f|.
+
+Computation options:
+
+    --pre=<predef_expr>
+
+        Evaluate the Julia expression <predef_expr> before starting
+        the computation. This permits you to pre-define variables or
+        functions which the Julia expressions in your main arguments
+        can refer to. All of <lo>, <hi>, <expr> and <weight> can make
+        use of things defined by <predef_expr>.
+
+        One internal remez.jl function that you might sometimes find
+        useful in this expression is 'goldensection', which finds the
+        location and value of a maximum of a function. For example,
+        one implementation strategy for the gamma function involves
+        translating it to put its unique local minimum at the origin,
+        in which case you can write something like this
+
+            --pre='(m,my) = goldensection(x -> -gamma(x),
+                  BigFloat(1), BigFloat(1.5), BigFloat(2))'
+
+        to predefine 'm' as the location of gamma's minimum, and 'my'
+        as the (negated) value that gamma actually takes at that
+        point, i.e. -gamma(m).
+
+        (Since 'goldensection' always finds a maximum, we had to
+        negate gamma in the input function to make it find a minimum
+        instead. Consult the comments in the source for more details
+        on the use of this function.)
+
+        If you use this option more than once, all the expressions you
+        provide will be run in sequence.
+
+    --bits=<bits>
+
+        Specify the accuracy to which you want the output polynomial,
+        in bits. Default 256, which should be more than enough.
+
+    --bigfloatbits=<bits>
+
+        Turn up the precision used by Julia for its BigFloat
+        evaluation. Default is Julia's default (also 256). You might
+        want to try setting this higher than the --bits value if the
+        algorithm is failing to converge for some reason.
+
+Output options:
+
+    --full
+
+        Instead of just printing the approximation function itself,
+        also print auxiliary information:
+         - the locations of the error extrema, and the actual
+           (weighted) error at each of those locations
+         - the overall maximum error of the function
+         - a 'well-conditioning quotient', giving the worst-case ratio
+           between any polynomial coefficient and the largest possible
+           value of the higher-order terms it will be added to.
+
+        The well-conditioning quotient should be less than 1, ideally
+        by several factors of two, for accurate evaluation in the
+        target precision. If you request a rational function, a
+        separate well-conditioning quotient will be printed for the
+        numerator and denominator.
+
+        Use this option when deciding how wide an interval to
+        approximate your function on, and what degree of polynomial
+        you need.
+
+    --variable=<identifier>
+
+        When writing the output polynomial or rational function in its
+        usual form as an arithmetic expression, use <identifier> as
+        the name of the input variable. Default is 'x'.
+
+    --suffix=<suffix>
+
+        When writing the output polynomial or rational function in its
+        usual form as an arithmetic expression, write <suffix> after
+        every floating-point literal. For example, '--suffix=F' will
+        generate a C expression in which the coefficients are literals
+        of type 'float' rather than 'double'.
+
+    --array
+
+        Instead of writing the output polynomial as an arithmetic
+        expression in Horner's rule form, write out just its
+        coefficients, one per line, each with a trailing comma.
+        Suitable for pasting into a C array declaration.
+
+        This option is not currently supported if the output is a
+        rational function, because you'd need two separate arrays for
+        the numerator and denominator coefficients and there's no
+        obviously right way to provide both of those together.
+
+Debug and test options:
+
+    --debug=<facility>
+
+        Enable debugging output from various parts of the Remez
+        calculation. <facility> should be the name of one of the
+        classes of diagnostic output implemented in the program.
+        Useful values include 'gausselim', 'leastsquares',
+        'goldensection', 'equaldev', 'minimax'. This is probably
+        mostly useful to people debugging problems with the script, so
+        consult the source code for more information about what the
+        diagnostic output for each of those facilities will be.
+
+        If you want diagnostics from more than one facility, specify
+        this option multiple times with different arguments.
+
+    --test
+
+        Run remez.jl's internal test suite. No arguments needed.
+
+Miscellaneous options:
+
+    --help
+
+        Display this text and exit. No arguments needed.
+
+""")
+end
+
+# ----------------------------------------------------------------------
+# Main program.
+
+function main()
+    nargs = length(argwords)
+    if nargs != 5 && nargs != 6
+        error("usage: remez.jl <lo> <hi> <n> <d> <expr> [<weight>]\n" *
+              "       run 'remez.jl --help' for more help")
+    end
+
+    for preliminary_command in preliminary_commands
+        eval(Meta.parse(preliminary_command))
+    end
+
+    lo = BigFloat(eval(Meta.parse(argwords[1])))
+    hi = BigFloat(eval(Meta.parse(argwords[2])))
+    n = parse(Int,argwords[3])
+    d = parse(Int,argwords[4])
+    f = eval(Meta.parse("x -> " * argwords[5]))
+
+    # Wrap the user-provided function with a function of our own. This
+    # arranges to detect silly FP values (inf,nan) early and diagnose
+    # them sensibly, and also lets us log all evaluations of the
+    # function in case you suspect it's doing the wrong thing at some
+    # special-case point.
+    function func(x)
+        y = run(f,x)
+        @debug("f", x, " -> ", y)
+        if !isfinite(y)
+            error("f(" * string(x) * ") returned non-finite value " * string(y))
+        end
+        return y
+    end
+
+    if nargs == 6
+        # Wrap the user-provided weight function similarly.
+        w = eval(Meta.parse("(x,y) -> " * argwords[6]))
+        function wrapped_weight(x,y)
+            ww = run(w,x,y)
+            if !isfinite(ww)
+                error("w(" * string(x) * "," * string(y) *
+                      ") returned non-finite value " * string(ww))
+            end
+            return ww
+        end
+        weight = wrapped_weight
+    else
+        weight = (x,y)->BigFloat(1)
+    end
+
+    (nc, dc, e, extrema) = ratfn_minimax(func, (lo, hi), n, d, weight)
+    if array_format
+        if d == 0
+            functext = join([string(x)*",\n" for x=nc],"")
+        else
+            # It's unclear how you should best format an array of
+            # coefficients for a rational function, so I'll leave
+            # implementing this option until I have a use case.
+            error("--array unsupported for rational functions")
+        end
+    else
+        functext = ratfn_to_string(nc, dc) * "\n"
+    end
+    if full_output
+        # Print everything you might want to know about the function
+        println("extrema = ", format_xylist(extrema))
+        println("maxerror = ", string(e))
+        if length(dc) > 1
+            println("wellconditioning_numerator = ",
+                    string(wellcond(nc, lo, hi)))
+            println("wellconditioning_denominator = ",
+                    string(wellcond(dc, lo, hi)))
+        else
+            println("wellconditioning = ", string(wellcond(nc, lo, hi)))
+        end
+        print("function = ", functext)
+    else
+        # Just print the text people will want to paste into their code
+        print(functext)
+    end
+end
+
+# ----------------------------------------------------------------------
+# Top-level code: parse the argument list and decide what to do.
+
+what_to_do = main
+
+doing_opts = true
+argwords = array1d(String, 0)
+for arg = ARGS
+    global doing_opts, what_to_do, argwords
+    global full_output, array_format, xvarname, floatsuffix, epsbits
+    if doing_opts && startswith(arg, "-")
+        if arg == "--"
+            doing_opts = false
+        elseif arg == "--help"
+            what_to_do = help
+        elseif arg == "--test"
+            what_to_do = test
+        elseif arg == "--full"
+            full_output = true
+        elseif arg == "--array"
+            array_format = true
+        elseif startswith(arg, "--debug=")
+            enable_debug(arg[length("--debug=")+1:end])
+        elseif startswith(arg, "--variable=")
+            xvarname = arg[length("--variable=")+1:end]
+        elseif startswith(arg, "--suffix=")
+            floatsuffix = arg[length("--suffix=")+1:end]
+        elseif startswith(arg, "--bits=")
+            epsbits = parse(Int,arg[length("--bits=")+1:end])
+        elseif startswith(arg, "--bigfloatbits=")
+            set_bigfloat_precision(
+                parse(Int,arg[length("--bigfloatbits=")+1:end]))
+        elseif startswith(arg, "--pre=")
+            push!(preliminary_commands, arg[length("--pre=")+1:end])
+        else
+            error("unrecognised option: ", arg)
+        end
+    else
+        push!(argwords, arg)
+    end
+end
+
+what_to_do()
diff --git a/libc/AOR_v20.02/math/tools/sin.sollya b/libc/AOR_v20.02/math/tools/sin.sollya
new file mode 100644
index 0000000000000..f5c11ec2f191b
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/sin.sollya
@@ -0,0 +1,38 @@
+// polynomial for approximating sin(x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 7;   // polynomial degree
+a = -pi/4; // interval
+b = pi/4;
+
+// find even polynomial with minimal abs error compared to sin(x)/x
+
+// account for /x
+deg = deg-1;
+
+// f = sin(x)/x;
+f = 1;
+c = 1;
+for i from 1 to 60 do { c = 2*i*(2*i + 1)*c; f = f + (-1)^i*x^(2*i)/c; };
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(f(x)-poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = 1;
+for i from 1 to deg/2 do {
+  p = roundcoefficients(approx(poly,2*i), [|D ...|]);
+  poly = poly + x^(2*i)*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/f(x), [a;b], 30));
+print("abs error:", accurateinfnorm(sin(x)-x*poly(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/v_exp.sollya b/libc/AOR_v20.02/math/tools/v_exp.sollya
new file mode 100644
index 0000000000000..4ef477f900200
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/v_exp.sollya
@@ -0,0 +1,31 @@
+// polynomial for approximating e^x
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 4; // poly degree
+N = 128; // table entries
+b = log(2)/(2*N);  // interval
+a = -b;
+
+// find polynomial with minimal abs error
+
+// return p that minimizes |exp(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(exp(x)-poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first 2 coeffs are fixed, iteratively find optimal double prec coeffs
+poly = 1 + x;
+for i from 2 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/exp(x), [a;b], 30));
+print("abs error:", accurateinfnorm(exp(x)-poly(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/v_log.sollya b/libc/AOR_v20.02/math/tools/v_log.sollya
new file mode 100644
index 0000000000000..d23b9da48460e
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/v_log.sollya
@@ -0,0 +1,35 @@
+// polynomial used for __v_log(x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 6; // poly degree
+a = -0x1.fc1p-9;
+b = 0x1.009p-8;
+
+// find log(1+x)/x polynomial with minimal relative error
+// (minimal relative error polynomial for log(1+x) is the same * x)
+deg = deg-1; // because of /x
+
+// f = log(1+x)/x; using taylor series
+f = 0;
+for i from 0 to 60 do { f = f + (-x)^i/(i+1); };
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|/|f(x)|
+approx = proc(poly,d) {
+  return remez(1 - poly(x)/f(x), deg-d, [a;b], x^d/f(x), 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = 1;
+for i from 1 to deg do {
+  p = roundcoefficients(approx(poly,i), [|D ...|]);
+  poly = poly + x^i*coeff(p,0);
+};
+
+display = hexadecimal;
+print("rel error:", accurateinfnorm(1-poly(x)/f(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/tools/v_sin.sollya b/libc/AOR_v20.02/math/tools/v_sin.sollya
new file mode 100644
index 0000000000000..5c596427daab2
--- /dev/null
+++ b/libc/AOR_v20.02/math/tools/v_sin.sollya
@@ -0,0 +1,37 @@
+// polynomial for approximating sin(x)
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+deg = 15;  // polynomial degree
+a = -pi/2; // interval
+b = pi/2;
+
+// find even polynomial with minimal abs error compared to sin(x)/x
+
+// account for /x
+deg = deg-1;
+
+// f = sin(x)/x;
+f = 1;
+c = 1;
+for i from 1 to 60 do { c = 2*i*(2*i + 1)*c; f = f + (-1)^i*x^(2*i)/c; };
+
+// return p that minimizes |f(x) - poly(x) - x^d*p(x)|
+approx = proc(poly,d) {
+  return remez(f(x)-poly(x), deg-d, [a;b], x^d, 1e-10);
+};
+
+// first coeff is fixed, iteratively find optimal double prec coeffs
+poly = 1;
+for i from 1 to deg/2 do {
+  p = roundcoefficients(approx(poly,2*i), [|D ...|]);
+  poly = poly + x^(2*i)*coeff(p,0);
+};
+
+display = hexadecimal;
+print("abs error:", accurateinfnorm(sin(x)-x*poly(x), [a;b], 30));
+print("in [",a,b,"]");
+print("coeffs:");
+for i from 0 to deg do coeff(poly,i);
diff --git a/libc/AOR_v20.02/math/v_cos.c b/libc/AOR_v20.02/math/v_cos.c
new file mode 100644
index 0000000000000..1eebdbceeda04
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_cos.c
@@ -0,0 +1,88 @@
+/*
+ * Double-precision vector cos function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const double Poly[] = {
+/* worst-case error is 3.5 ulp.
+   abs error: 0x1.be222a58p-53 in [-pi/2, pi/2].  */
+-0x1.9f4a9c8b21dc9p-41,
+ 0x1.60e88a10163f2p-33,
+-0x1.ae6361b7254e7p-26,
+ 0x1.71de382e8d62bp-19,
+-0x1.a01a019aeb4ffp-13,
+ 0x1.111111110b25ep-7,
+-0x1.55555555554c3p-3,
+};
+
+#define C7 v_f64 (Poly[0])
+#define C6 v_f64 (Poly[1])
+#define C5 v_f64 (Poly[2])
+#define C4 v_f64 (Poly[3])
+#define C3 v_f64 (Poly[4])
+#define C2 v_f64 (Poly[5])
+#define C1 v_f64 (Poly[6])
+
+#define InvPi v_f64 (0x1.45f306dc9c883p-2)
+#define HalfPi v_f64 (0x1.921fb54442d18p+0)
+#define Pi1 v_f64 (0x1.921fb54442d18p+1)
+#define Pi2 v_f64 (0x1.1a62633145c06p-53)
+#define Pi3 v_f64 (0x1.c1cd129024e09p-106)
+#define Shift v_f64 (0x1.8p52)
+#define RangeVal v_f64 (0x1p23)
+#define AbsMask v_u64 (0x7fffffffffffffff)
+
+VPCS_ATTR
+__attribute__ ((noinline)) static v_f64_t
+specialcase (v_f64_t x, v_f64_t y, v_u64_t cmp)
+{
+  return v_call_f64 (cos, x, y, cmp);
+}
+
+VPCS_ATTR
+v_f64_t
+V_NAME(cos) (v_f64_t x)
+{
+  v_f64_t n, r, r2, y;
+  v_u64_t odd, cmp;
+
+  r = v_as_f64_u64 (v_as_u64_f64 (x) & AbsMask);
+  cmp = v_cond_u64 (v_as_u64_f64 (r) >= v_as_u64_f64 (RangeVal));
+
+  /* n = rint((|x|+pi/2)/pi) - 0.5.  */
+  n = v_fma_f64 (InvPi, r + HalfPi, Shift);
+  odd = v_as_u64_f64 (n) << 63;
+  n -= Shift;
+  n -= v_f64 (0.5);
+
+  /* r = |x| - n*pi  (range reduction into -pi/2 .. pi/2).  */
+  r = v_fma_f64 (-Pi1, n, r);
+  r = v_fma_f64 (-Pi2, n, r);
+  r = v_fma_f64 (-Pi3, n, r);
+
+  /* sin(r) poly approx.  */
+  r2 = r * r;
+  y = v_fma_f64 (C7, r2, C6);
+  y = v_fma_f64 (y, r2, C5);
+  y = v_fma_f64 (y, r2, C4);
+  y = v_fma_f64 (y, r2, C3);
+  y = v_fma_f64 (y, r2, C2);
+  y = v_fma_f64 (y, r2, C1);
+  y = v_fma_f64 (y * r2, r, r);
+
+  /* sign.  */
+  y = v_as_f64_u64 (v_as_u64_f64 (y) ^ odd);
+
+  if (unlikely (v_any_u64 (cmp)))
+    return specialcase (x, y, cmp);
+  return y;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_cosf.c b/libc/AOR_v20.02/math/v_cosf.c
new file mode 100644
index 0000000000000..b9dcd486f4b2b
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_cosf.c
@@ -0,0 +1,77 @@
+/*
+ * Single-precision vector cos function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /* 1.886 ulp error */
+  0x1.5b2e76p-19f,
+  -0x1.9f42eap-13f,
+  0x1.110df4p-7f,
+  -0x1.555548p-3f,
+};
+#define Pi1 v_f32 (0x1.921fb6p+1f)
+#define Pi2 v_f32 (-0x1.777a5cp-24f)
+#define Pi3 v_f32 (-0x1.ee59dap-49f)
+#define A3 v_f32 (Poly[3])
+#define A5 v_f32 (Poly[2])
+#define A7 v_f32 (Poly[1])
+#define A9 v_f32 (Poly[0])
+#define RangeVal v_f32 (0x1p20f)
+#define InvPi v_f32 (0x1.45f306p-2f)
+#define Shift v_f32 (0x1.8p+23f)
+#define AbsMask v_u32 (0x7fffffff)
+#define HalfPi v_f32 (0x1.921fb6p0f)
+
+VPCS_ATTR
+static v_f32_t
+specialcase (v_f32_t x, v_f32_t y, v_u32_t cmp)
+{
+  /* Fall back to scalar code.  */
+  return v_call_f32 (cosf, x, y, cmp);
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(cosf) (v_f32_t x)
+{
+  v_f32_t n, r, r2, y;
+  v_u32_t odd, cmp;
+
+  r = v_as_f32_u32 (v_as_u32_f32 (x) & AbsMask);
+  cmp = v_cond_u32 (v_as_u32_f32 (r) >= v_as_u32_f32 (RangeVal));
+
+  /* n = rint((|x|+pi/2)/pi) - 0.5 */
+  n = v_fma_f32 (InvPi, r + HalfPi, Shift);
+  odd = v_as_u32_f32 (n) << 31;
+  n -= Shift;
+  n -= v_f32 (0.5f);
+
+  /* r = |x| - n*pi  (range reduction into -pi/2 .. pi/2) */
+  r = v_fma_f32 (-Pi1, n, r);
+  r = v_fma_f32 (-Pi2, n, r);
+  r = v_fma_f32 (-Pi3, n, r);
+
+  /* y = sin(r) */
+  r2 = r * r;
+  y = v_fma_f32 (A9, r2, A7);
+  y = v_fma_f32 (y, r2, A5);
+  y = v_fma_f32 (y, r2, A3);
+  y = v_fma_f32 (y * r2, r, r);
+
+  /* sign fix */
+  y = v_as_f32_u32 (v_as_u32_f32 (y) ^ odd);
+
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (x, y, cmp);
+  return y;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_exp.c b/libc/AOR_v20.02/math/v_exp.c
new file mode 100644
index 0000000000000..9074cecdd1543
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_exp.c
@@ -0,0 +1,95 @@
+/*
+ * Double-precision vector e^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+#include "v_exp.h"
+
+#if V_EXP_TABLE_BITS == 7
+/* maxerr: 1.88 +0.5 ulp
+   rel error: 1.4337*2^-53
+   abs error: 1.4299*2^-53 in [ -ln2/256, ln2/256 ].  */
+#define C1 v_f64 (0x1.ffffffffffd43p-2)
+#define C2 v_f64 (0x1.55555c75adbb2p-3)
+#define C3 v_f64 (0x1.55555da646206p-5)
+#define InvLn2 v_f64 (0x1.71547652b82fep7) /* N/ln2.  */
+#define Ln2hi v_f64 (0x1.62e42fefa39efp-8) /* ln2/N.  */
+#define Ln2lo v_f64 (0x1.abc9e3b39803f3p-63)
+#elif V_EXP_TABLE_BITS == 8
+/* maxerr: 0.54 +0.5 ulp
+   rel error: 1.4318*2^-58
+   abs error: 1.4299*2^-58 in [ -ln2/512, ln2/512 ].  */
+#define C1 v_f64 (0x1.fffffffffffd4p-2)
+#define C2 v_f64 (0x1.5555571d6b68cp-3)
+#define C3 v_f64 (0x1.5555576a59599p-5)
+#define InvLn2 v_f64 (0x1.71547652b82fep8)
+#define Ln2hi v_f64 (0x1.62e42fefa39efp-9)
+#define Ln2lo v_f64 (0x1.abc9e3b39803f3p-64)
+#endif
+
+#define N (1 << V_EXP_TABLE_BITS)
+#define Tab __v_exp_data
+#define IndexMask v_u64 (N - 1)
+#define Shift v_f64 (0x1.8p+52)
+#define Thres v_f64 (704.0)
+
+VPCS_ATTR
+static v_f64_t
+specialcase (v_f64_t s, v_f64_t y, v_f64_t n)
+{
+  v_f64_t absn = v_abs_f64 (n);
+
+  /* 2^(n/N) may overflow, break it up into s1*s2.  */
+  v_u64_t b = v_cond_u64 (n <= v_f64 (0.0)) & v_u64 (0x6000000000000000);
+  v_f64_t s1 = v_as_f64_u64 (v_u64 (0x7000000000000000) - b);
+  v_f64_t s2 = v_as_f64_u64 (v_as_u64_f64 (s) - v_u64 (0x3010000000000000) + b);
+  v_u64_t cmp = v_cond_u64 (absn > v_f64 (1280.0 * N));
+  v_f64_t r1 = s1 * s1;
+  v_f64_t r0 = v_fma_f64 (y, s2, s2) * s1;
+  return v_as_f64_u64 ((cmp & v_as_u64_f64 (r1)) | (~cmp & v_as_u64_f64 (r0)));
+}
+
+VPCS_ATTR
+v_f64_t
+V_NAME(exp) (v_f64_t x)
+{
+  v_f64_t n, r, r2, s, y, z;
+  v_u64_t cmp, u, e, i;
+
+  cmp = v_cond_u64 (v_abs_f64 (x) > Thres);
+
+  /* n = round(x/(ln2/N)).  */
+  z = v_fma_f64 (x, InvLn2, Shift);
+  u = v_as_u64_f64 (z);
+  n = z - Shift;
+
+  /* r = x - n*ln2/N.  */
+  r = x;
+  r = v_fma_f64 (-Ln2hi, n, r);
+  r = v_fma_f64 (-Ln2lo, n, r);
+
+  e = u << (52 - V_EXP_TABLE_BITS);
+  i = u & IndexMask;
+
+  /* y = exp(r) - 1 ~= r + C1 r^2 + C2 r^3 + C3 r^4.  */
+  r2 = r * r;
+  y = v_fma_f64 (C2, r, C1);
+  y = v_fma_f64 (C3, r2, y);
+  y = v_fma_f64 (y, r2, r);
+
+  /* s = 2^(n/N).  */
+  u = v_lookup_u64 (Tab, i);
+  s = v_as_f64_u64 (u + e);
+
+  if (unlikely (v_any_u64 (cmp)))
+    return specialcase (s, y, n);
+  return v_fma_f64 (y, s, s);
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_exp.h b/libc/AOR_v20.02/math/v_exp.h
new file mode 100644
index 0000000000000..251c85dc5255c
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_exp.h
@@ -0,0 +1,15 @@
+/*
+ * Declarations for double-precision e^x vector function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "v_math.h"
+#if WANT_VMATH
+
+#define V_EXP_TABLE_BITS 7
+
+extern const u64_t __v_exp_data[1 << V_EXP_TABLE_BITS] HIDDEN;
+#endif
diff --git a/libc/AOR_v20.02/math/v_exp2f.c b/libc/AOR_v20.02/math/v_exp2f.c
new file mode 100644
index 0000000000000..876298fea5316
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_exp2f.c
@@ -0,0 +1,79 @@
+/*
+ * Single-precision vector 2^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /* maxerr: 1.962 ulp.  */
+  0x1.59977ap-10f,
+  0x1.3ce9e4p-7f,
+  0x1.c6bd32p-5f,
+  0x1.ebf9bcp-3f,
+  0x1.62e422p-1f,
+};
+#define C0 v_f32 (Poly[0])
+#define C1 v_f32 (Poly[1])
+#define C2 v_f32 (Poly[2])
+#define C3 v_f32 (Poly[3])
+#define C4 v_f32 (Poly[4])
+
+#define Shift v_f32 (0x1.8p23f)
+
+VPCS_ATTR
+static v_f32_t
+specialcase (v_f32_t poly, v_f32_t n, v_u32_t e, v_f32_t absn, v_u32_t cmp1, v_f32_t scale)
+{
+  /* 2^n may overflow, break it up into s1*s2.  */
+  v_u32_t b = v_cond_u32 (n <= v_f32 (0.0f)) & v_u32 (0x82000000);
+  v_f32_t s1 = v_as_f32_u32 (v_u32 (0x7f000000) + b);
+  v_f32_t s2 = v_as_f32_u32 (e - b);
+  v_u32_t cmp2 = v_cond_u32 (absn > v_f32 (192.0f));
+  v_u32_t r2 = v_as_u32_f32 (s1 * s1);
+  v_u32_t r1 = v_as_u32_f32 (v_fma_f32 (poly, s2, s2) * s1);
+  /* Similar to r1 but avoids double rounding in the subnormal range.  */
+  v_u32_t r0 = v_as_u32_f32 (v_fma_f32 (poly, scale, scale));
+  return v_as_f32_u32 ((cmp2 & r2) | (~cmp2 & cmp1 & r1) | (~cmp1 & r0));
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(exp2f) (v_f32_t x)
+{
+  v_f32_t n, r, r2, scale, p, q, poly, absn;
+  v_u32_t cmp, e;
+
+  /* exp2(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)]
+     x = n + r, with r in [-1/2, 1/2].  */
+#if 0
+  v_f32_t z;
+  z = x + Shift;
+  n = z - Shift;
+  r = x - n;
+  e = v_as_u32_f32 (z) << 23;
+#else
+  n = v_round_f32 (x);
+  r = x - n;
+  e = v_as_u32_s32 (v_round_s32 (x)) << 23;
+#endif
+  scale = v_as_f32_u32 (e + v_u32 (0x3f800000));
+  absn = v_abs_f32 (n);
+  cmp = v_cond_u32 (absn > v_f32 (126.0f));
+  r2 = r * r;
+  p = v_fma_f32 (C0, r, C1);
+  q = v_fma_f32 (C2, r, C3);
+  q = v_fma_f32 (p, r2, q);
+  p = C4 * r;
+  poly = v_fma_f32 (q, r2, p);
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (poly, n, e, absn, cmp, scale);
+  return v_fma_f32 (poly, scale, scale);
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_exp2f_1u.c b/libc/AOR_v20.02/math/v_exp2f_1u.c
new file mode 100644
index 0000000000000..d8b660e15f239
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_exp2f_1u.c
@@ -0,0 +1,76 @@
+/*
+ * Single-precision vector 2^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /*  maxerr: 0.878 ulp.  */
+  0x1.416b5ep-13f, 0x1.5f082ep-10f, 0x1.3b2dep-7f, 0x1.c6af7cp-5f, 0x1.ebfbdcp-3f, 0x1.62e43p-1f
+};
+#define C0 v_f32 (Poly[0])
+#define C1 v_f32 (Poly[1])
+#define C2 v_f32 (Poly[2])
+#define C3 v_f32 (Poly[3])
+#define C4 v_f32 (Poly[4])
+#define C5 v_f32 (Poly[5])
+
+#define Shift v_f32 (0x1.8p23f)
+#define InvLn2 v_f32 (0x1.715476p+0f)
+#define Ln2hi v_f32 (0x1.62e4p-1f)
+#define Ln2lo v_f32 (0x1.7f7d1cp-20f)
+
+VPCS_ATTR
+static v_f32_t
+specialcase (v_f32_t poly, v_f32_t n, v_u32_t e, v_f32_t absn)
+{
+  /* 2^n may overflow, break it up into s1*s2.  */
+  v_u32_t b = v_cond_u32 (n <= v_f32 (0.0f)) & v_u32 (0x83000000);
+  v_f32_t s1 = v_as_f32_u32 (v_u32 (0x7f000000) + b);
+  v_f32_t s2 = v_as_f32_u32 (e - b);
+  v_u32_t cmp = v_cond_u32 (absn > v_f32 (192.0f));
+  v_f32_t r1 = s1 * s1;
+  v_f32_t r0 = poly * s1 * s2;
+  return v_as_f32_u32 ((cmp & v_as_u32_f32 (r1)) | (~cmp & v_as_u32_f32 (r0)));
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(exp2f_1u) (v_f32_t x)
+{
+  v_f32_t n, r, scale, poly, absn;
+  v_u32_t cmp, e;
+
+  /* exp2(x) = 2^n * poly(r), with poly(r) in [1/sqrt(2),sqrt(2)]
+     x = n + r, with r in [-1/2, 1/2].  */
+#if 0
+  v_f32_t z;
+  z = x + Shift;
+  n = z - Shift;
+  r = x - n;
+  e = v_as_u32_f32 (z) << 23;
+#else
+  n = v_round_f32 (x);
+  r = x - n;
+  e = v_as_u32_s32 (v_round_s32 (x)) << 23;
+#endif
+  scale = v_as_f32_u32 (e + v_u32 (0x3f800000));
+  absn = v_abs_f32 (n);
+  cmp = v_cond_u32 (absn > v_f32 (126.0f));
+  poly = v_fma_f32 (C0, r, C1);
+  poly = v_fma_f32 (poly, r, C2);
+  poly = v_fma_f32 (poly, r, C3);
+  poly = v_fma_f32 (poly, r, C4);
+  poly = v_fma_f32 (poly, r, C5);
+  poly = v_fma_f32 (poly, r, v_f32 (1.0f));
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (poly, n, e, absn);
+  return scale * poly;
+}
+#endif
diff --git a/libc/AOR_v20.02/math/v_exp_data.c b/libc/AOR_v20.02/math/v_exp_data.c
new file mode 100644
index 0000000000000..fc248e3ce479c
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_exp_data.c
@@ -0,0 +1,404 @@
+/*
+ * Lookup table for double-precision e^x vector function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "v_exp.h"
+#if WANT_VMATH
+
+#define N (1 << V_EXP_TABLE_BITS)
+
+/* 2^(j/N), j=0..N.  */
+const u64_t __v_exp_data[] = {
+#if N == 128
+0x3ff0000000000000,
+0x3feff63da9fb3335,
+0x3fefec9a3e778061,
+0x3fefe315e86e7f85,
+0x3fefd9b0d3158574,
+0x3fefd06b29ddf6de,
+0x3fefc74518759bc8,
+0x3fefbe3ecac6f383,
+0x3fefb5586cf9890f,
+0x3fefac922b7247f7,
+0x3fefa3ec32d3d1a2,
+0x3fef9b66affed31b,
+0x3fef9301d0125b51,
+0x3fef8abdc06c31cc,
+0x3fef829aaea92de0,
+0x3fef7a98c8a58e51,
+0x3fef72b83c7d517b,
+0x3fef6af9388c8dea,
+0x3fef635beb6fcb75,
+0x3fef5be084045cd4,
+0x3fef54873168b9aa,
+0x3fef4d5022fcd91d,
+0x3fef463b88628cd6,
+0x3fef3f49917ddc96,
+0x3fef387a6e756238,
+0x3fef31ce4fb2a63f,
+0x3fef2b4565e27cdd,
+0x3fef24dfe1f56381,
+0x3fef1e9df51fdee1,
+0x3fef187fd0dad990,
+0x3fef1285a6e4030b,
+0x3fef0cafa93e2f56,
+0x3fef06fe0a31b715,
+0x3fef0170fc4cd831,
+0x3feefc08b26416ff,
+0x3feef6c55f929ff1,
+0x3feef1a7373aa9cb,
+0x3feeecae6d05d866,
+0x3feee7db34e59ff7,
+0x3feee32dc313a8e5,
+0x3feedea64c123422,
+0x3feeda4504ac801c,
+0x3feed60a21f72e2a,
+0x3feed1f5d950a897,
+0x3feece086061892d,
+0x3feeca41ed1d0057,
+0x3feec6a2b5c13cd0,
+0x3feec32af0d7d3de,
+0x3feebfdad5362a27,
+0x3feebcb299fddd0d,
+0x3feeb9b2769d2ca7,
+0x3feeb6daa2cf6642,
+0x3feeb42b569d4f82,
+0x3feeb1a4ca5d920f,
+0x3feeaf4736b527da,
+0x3feead12d497c7fd,
+0x3feeab07dd485429,
+0x3feea9268a5946b7,
+0x3feea76f15ad2148,
+0x3feea5e1b976dc09,
+0x3feea47eb03a5585,
+0x3feea34634ccc320,
+0x3feea23882552225,
+0x3feea155d44ca973,
+0x3feea09e667f3bcd,
+0x3feea012750bdabf,
+0x3fee9fb23c651a2f,
+0x3fee9f7df9519484,
+0x3fee9f75e8ec5f74,
+0x3fee9f9a48a58174,
+0x3fee9feb564267c9,
+0x3feea0694fde5d3f,
+0x3feea11473eb0187,
+0x3feea1ed0130c132,
+0x3feea2f336cf4e62,
+0x3feea427543e1a12,
+0x3feea589994cce13,
+0x3feea71a4623c7ad,
+0x3feea8d99b4492ed,
+0x3feeaac7d98a6699,
+0x3feeace5422aa0db,
+0x3feeaf3216b5448c,
+0x3feeb1ae99157736,
+0x3feeb45b0b91ffc6,
+0x3feeb737b0cdc5e5,
+0x3feeba44cbc8520f,
+0x3feebd829fde4e50,
+0x3feec0f170ca07ba,
+0x3feec49182a3f090,
+0x3feec86319e32323,
+0x3feecc667b5de565,
+0x3feed09bec4a2d33,
+0x3feed503b23e255d,
+0x3feed99e1330b358,
+0x3feede6b5579fdbf,
+0x3feee36bbfd3f37a,
+0x3feee89f995ad3ad,
+0x3feeee07298db666,
+0x3feef3a2b84f15fb,
+0x3feef9728de5593a,
+0x3feeff76f2fb5e47,
+0x3fef05b030a1064a,
+0x3fef0c1e904bc1d2,
+0x3fef12c25bd71e09,
+0x3fef199bdd85529c,
+0x3fef20ab5fffd07a,
+0x3fef27f12e57d14b,
+0x3fef2f6d9406e7b5,
+0x3fef3720dcef9069,
+0x3fef3f0b555dc3fa,
+0x3fef472d4a07897c,
+0x3fef4f87080d89f2,
+0x3fef5818dcfba487,
+0x3fef60e316c98398,
+0x3fef69e603db3285,
+0x3fef7321f301b460,
+0x3fef7c97337b9b5f,
+0x3fef864614f5a129,
+0x3fef902ee78b3ff6,
+0x3fef9a51fbc74c83,
+0x3fefa4afa2a490da,
+0x3fefaf482d8e67f1,
+0x3fefba1bee615a27,
+0x3fefc52b376bba97,
+0x3fefd0765b6e4540,
+0x3fefdbfdad9cbe14,
+0x3fefe7c1819e90d8,
+0x3feff3c22b8f71f1,
+#elif N == 256
+0x3ff0000000000000,
+0x3feffb1afa5abcbf,
+0x3feff63da9fb3335,
+0x3feff168143b0281,
+0x3fefec9a3e778061,
+0x3fefe7d42e11bbcc,
+0x3fefe315e86e7f85,
+0x3fefde5f72f654b1,
+0x3fefd9b0d3158574,
+0x3fefd50a0e3c1f89,
+0x3fefd06b29ddf6de,
+0x3fefcbd42b72a836,
+0x3fefc74518759bc8,
+0x3fefc2bdf66607e0,
+0x3fefbe3ecac6f383,
+0x3fefb9c79b1f3919,
+0x3fefb5586cf9890f,
+0x3fefb0f145e46c85,
+0x3fefac922b7247f7,
+0x3fefa83b23395dec,
+0x3fefa3ec32d3d1a2,
+0x3fef9fa55fdfa9c5,
+0x3fef9b66affed31b,
+0x3fef973028d7233e,
+0x3fef9301d0125b51,
+0x3fef8edbab5e2ab6,
+0x3fef8abdc06c31cc,
+0x3fef86a814f204ab,
+0x3fef829aaea92de0,
+0x3fef7e95934f312e,
+0x3fef7a98c8a58e51,
+0x3fef76a45471c3c2,
+0x3fef72b83c7d517b,
+0x3fef6ed48695bbc0,
+0x3fef6af9388c8dea,
+0x3fef672658375d2f,
+0x3fef635beb6fcb75,
+0x3fef5f99f8138a1c,
+0x3fef5be084045cd4,
+0x3fef582f95281c6b,
+0x3fef54873168b9aa,
+0x3fef50e75eb44027,
+0x3fef4d5022fcd91d,
+0x3fef49c18438ce4d,
+0x3fef463b88628cd6,
+0x3fef42be3578a819,
+0x3fef3f49917ddc96,
+0x3fef3bdda27912d1,
+0x3fef387a6e756238,
+0x3fef351ffb82140a,
+0x3fef31ce4fb2a63f,
+0x3fef2e85711ece75,
+0x3fef2b4565e27cdd,
+0x3fef280e341ddf29,
+0x3fef24dfe1f56381,
+0x3fef21ba7591bb70,
+0x3fef1e9df51fdee1,
+0x3fef1b8a66d10f13,
+0x3fef187fd0dad990,
+0x3fef157e39771b2f,
+0x3fef1285a6e4030b,
+0x3fef0f961f641589,
+0x3fef0cafa93e2f56,
+0x3fef09d24abd886b,
+0x3fef06fe0a31b715,
+0x3fef0432edeeb2fd,
+0x3fef0170fc4cd831,
+0x3feefeb83ba8ea32,
+0x3feefc08b26416ff,
+0x3feef96266e3fa2d,
+0x3feef6c55f929ff1,
+0x3feef431a2de883b,
+0x3feef1a7373aa9cb,
+0x3feeef26231e754a,
+0x3feeecae6d05d866,
+0x3feeea401b7140ef,
+0x3feee7db34e59ff7,
+0x3feee57fbfec6cf4,
+0x3feee32dc313a8e5,
+0x3feee0e544ede173,
+0x3feedea64c123422,
+0x3feedc70df1c5175,
+0x3feeda4504ac801c,
+0x3feed822c367a024,
+0x3feed60a21f72e2a,
+0x3feed3fb2709468a,
+0x3feed1f5d950a897,
+0x3feecffa3f84b9d4,
+0x3feece086061892d,
+0x3feecc2042a7d232,
+0x3feeca41ed1d0057,
+0x3feec86d668b3237,
+0x3feec6a2b5c13cd0,
+0x3feec4e1e192aed2,
+0x3feec32af0d7d3de,
+0x3feec17dea6db7d7,
+0x3feebfdad5362a27,
+0x3feebe41b817c114,
+0x3feebcb299fddd0d,
+0x3feebb2d81d8abff,
+0x3feeb9b2769d2ca7,
+0x3feeb8417f4531ee,
+0x3feeb6daa2cf6642,
+0x3feeb57de83f4eef,
+0x3feeb42b569d4f82,
+0x3feeb2e2f4f6ad27,
+0x3feeb1a4ca5d920f,
+0x3feeb070dde910d2,
+0x3feeaf4736b527da,
+0x3feeae27dbe2c4cf,
+0x3feead12d497c7fd,
+0x3feeac0827ff07cc,
+0x3feeab07dd485429,
+0x3feeaa11fba87a03,
+0x3feea9268a5946b7,
+0x3feea84590998b93,
+0x3feea76f15ad2148,
+0x3feea6a320dceb71,
+0x3feea5e1b976dc09,
+0x3feea52ae6cdf6f4,
+0x3feea47eb03a5585,
+0x3feea3dd1d1929fd,
+0x3feea34634ccc320,
+0x3feea2b9febc8fb7,
+0x3feea23882552225,
+0x3feea1c1c70833f6,
+0x3feea155d44ca973,
+0x3feea0f4b19e9538,
+0x3feea09e667f3bcd,
+0x3feea052fa75173e,
+0x3feea012750bdabf,
+0x3fee9fdcddd47645,
+0x3fee9fb23c651a2f,
+0x3fee9f9298593ae5,
+0x3fee9f7df9519484,
+0x3fee9f7466f42e87,
+0x3fee9f75e8ec5f74,
+0x3fee9f8286ead08a,
+0x3fee9f9a48a58174,
+0x3fee9fbd35d7cbfd,
+0x3fee9feb564267c9,
+0x3feea024b1ab6e09,
+0x3feea0694fde5d3f,
+0x3feea0b938ac1cf6,
+0x3feea11473eb0187,
+0x3feea17b0976cfdb,
+0x3feea1ed0130c132,
+0x3feea26a62ff86f0,
+0x3feea2f336cf4e62,
+0x3feea3878491c491,
+0x3feea427543e1a12,
+0x3feea4d2add106d9,
+0x3feea589994cce13,
+0x3feea64c1eb941f7,
+0x3feea71a4623c7ad,
+0x3feea7f4179f5b21,
+0x3feea8d99b4492ed,
+0x3feea9cad931a436,
+0x3feeaac7d98a6699,
+0x3feeabd0a478580f,
+0x3feeace5422aa0db,
+0x3feeae05bad61778,
+0x3feeaf3216b5448c,
+0x3feeb06a5e0866d9,
+0x3feeb1ae99157736,
+0x3feeb2fed0282c8a,
+0x3feeb45b0b91ffc6,
+0x3feeb5c353aa2fe2,
+0x3feeb737b0cdc5e5,
+0x3feeb8b82b5f98e5,
+0x3feeba44cbc8520f,
+0x3feebbdd9a7670b3,
+0x3feebd829fde4e50,
+0x3feebf33e47a22a2,
+0x3feec0f170ca07ba,
+0x3feec2bb4d53fe0d,
+0x3feec49182a3f090,
+0x3feec674194bb8d5,
+0x3feec86319e32323,
+0x3feeca5e8d07f29e,
+0x3feecc667b5de565,
+0x3feece7aed8eb8bb,
+0x3feed09bec4a2d33,
+0x3feed2c980460ad8,
+0x3feed503b23e255d,
+0x3feed74a8af46052,
+0x3feed99e1330b358,
+0x3feedbfe53c12e59,
+0x3feede6b5579fdbf,
+0x3feee0e521356eba,
+0x3feee36bbfd3f37a,
+0x3feee5ff3a3c2774,
+0x3feee89f995ad3ad,
+0x3feeeb4ce622f2ff,
+0x3feeee07298db666,
+0x3feef0ce6c9a8952,
+0x3feef3a2b84f15fb,
+0x3feef68415b749b1,
+0x3feef9728de5593a,
+0x3feefc6e29f1c52a,
+0x3feeff76f2fb5e47,
+0x3fef028cf22749e4,
+0x3fef05b030a1064a,
+0x3fef08e0b79a6f1f,
+0x3fef0c1e904bc1d2,
+0x3fef0f69c3f3a207,
+0x3fef12c25bd71e09,
+0x3fef16286141b33d,
+0x3fef199bdd85529c,
+0x3fef1d1cd9fa652c,
+0x3fef20ab5fffd07a,
+0x3fef244778fafb22,
+0x3fef27f12e57d14b,
+0x3fef2ba88988c933,
+0x3fef2f6d9406e7b5,
+0x3fef33405751c4db,
+0x3fef3720dcef9069,
+0x3fef3b0f2e6d1675,
+0x3fef3f0b555dc3fa,
+0x3fef43155b5bab74,
+0x3fef472d4a07897c,
+0x3fef4b532b08c968,
+0x3fef4f87080d89f2,
+0x3fef53c8eacaa1d6,
+0x3fef5818dcfba487,
+0x3fef5c76e862e6d3,
+0x3fef60e316c98398,
+0x3fef655d71ff6075,
+0x3fef69e603db3285,
+0x3fef6e7cd63a8315,
+0x3fef7321f301b460,
+0x3fef77d5641c0658,
+0x3fef7c97337b9b5f,
+0x3fef81676b197d17,
+0x3fef864614f5a129,
+0x3fef8b333b16ee12,
+0x3fef902ee78b3ff6,
+0x3fef953924676d76,
+0x3fef9a51fbc74c83,
+0x3fef9f7977cdb740,
+0x3fefa4afa2a490da,
+0x3fefa9f4867cca6e,
+0x3fefaf482d8e67f1,
+0x3fefb4aaa2188510,
+0x3fefba1bee615a27,
+0x3fefbf9c1cb6412a,
+0x3fefc52b376bba97,
+0x3fefcac948dd7274,
+0x3fefd0765b6e4540,
+0x3fefd632798844f8,
+0x3fefdbfdad9cbe14,
+0x3fefe1d802243c89,
+0x3fefe7c1819e90d8,
+0x3fefedba3692d514,
+0x3feff3c22b8f71f1,
+0x3feff9d96b2a23d9,
+#endif
+};
+#endif
diff --git a/libc/AOR_v20.02/math/v_expf.c b/libc/AOR_v20.02/math/v_expf.c
new file mode 100644
index 0000000000000..b9223b2519b10
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_expf.c
@@ -0,0 +1,84 @@
+/*
+ * Single-precision vector e^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /* maxerr: 1.45358 +0.5 ulp.  */
+  0x1.0e4020p-7f,
+  0x1.573e2ep-5f,
+  0x1.555e66p-3f,
+  0x1.fffdb6p-2f,
+  0x1.ffffecp-1f,
+};
+#define C0 v_f32 (Poly[0])
+#define C1 v_f32 (Poly[1])
+#define C2 v_f32 (Poly[2])
+#define C3 v_f32 (Poly[3])
+#define C4 v_f32 (Poly[4])
+
+#define Shift v_f32 (0x1.8p23f)
+#define InvLn2 v_f32 (0x1.715476p+0f)
+#define Ln2hi v_f32 (0x1.62e4p-1f)
+#define Ln2lo v_f32 (0x1.7f7d1cp-20f)
+
+VPCS_ATTR
+static v_f32_t
+specialcase (v_f32_t poly, v_f32_t n, v_u32_t e, v_f32_t absn, v_u32_t cmp1, v_f32_t scale)
+{
+  /* 2^n may overflow, break it up into s1*s2.  */
+  v_u32_t b = v_cond_u32 (n <= v_f32 (0.0f)) & v_u32 (0x82000000);
+  v_f32_t s1 = v_as_f32_u32 (v_u32 (0x7f000000) + b);
+  v_f32_t s2 = v_as_f32_u32 (e - b);
+  v_u32_t cmp2 = v_cond_u32 (absn > v_f32 (192.0f));
+  v_u32_t r2 = v_as_u32_f32 (s1 * s1);
+  v_u32_t r1 = v_as_u32_f32 (v_fma_f32 (poly, s2, s2) * s1);
+  /* Similar to r1 but avoids double rounding in the subnormal range.  */
+  v_u32_t r0 = v_as_u32_f32 (v_fma_f32 (poly, scale, scale));
+  return v_as_f32_u32 ((cmp2 & r2) | (~cmp2 & cmp1 & r1) | (~cmp1 & r0));
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(expf) (v_f32_t x)
+{
+  v_f32_t n, r, r2, scale, p, q, poly, absn, z;
+  v_u32_t cmp, e;
+
+  /* exp(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)]
+     x = ln2*n + r, with r in [-ln2/2, ln2/2].  */
+#if 1
+  z = v_fma_f32 (x, InvLn2, Shift);
+  n = z - Shift;
+  r = v_fma_f32 (n, -Ln2hi, x);
+  r = v_fma_f32 (n, -Ln2lo, r);
+  e = v_as_u32_f32 (z) << 23;
+#else
+  z = x * InvLn2;
+  n = v_round_f32 (z);
+  r = v_fma_f32 (n, -Ln2hi, x);
+  r = v_fma_f32 (n, -Ln2lo, r);
+  e = v_as_u32_s32 (v_round_s32 (z)) << 23;
+#endif
+  scale = v_as_f32_u32 (e + v_u32 (0x3f800000));
+  absn = v_abs_f32 (n);
+  cmp = v_cond_u32 (absn > v_f32 (126.0f));
+  r2 = r * r;
+  p = v_fma_f32 (C0, r, C1);
+  q = v_fma_f32 (C2, r, C3);
+  q = v_fma_f32 (p, r2, q);
+  p = C4 * r;
+  poly = v_fma_f32 (q, r2, p);
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (poly, n, e, absn, cmp, scale);
+  return v_fma_f32 (poly, scale, scale);
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_expf_1u.c b/libc/AOR_v20.02/math/v_expf_1u.c
new file mode 100644
index 0000000000000..640ca1f5cad64
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_expf_1u.c
@@ -0,0 +1,81 @@
+/*
+ * Single-precision vector e^x function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /*  maxerr: 0.36565 +0.5 ulp.  */
+  0x1.6a6000p-10f,
+  0x1.12718ep-7f,
+  0x1.555af0p-5f,
+  0x1.555430p-3f,
+  0x1.fffff4p-2f,
+};
+#define C0 v_f32 (Poly[0])
+#define C1 v_f32 (Poly[1])
+#define C2 v_f32 (Poly[2])
+#define C3 v_f32 (Poly[3])
+#define C4 v_f32 (Poly[4])
+
+#define Shift v_f32 (0x1.8p23f)
+#define InvLn2 v_f32 (0x1.715476p+0f)
+#define Ln2hi v_f32 (0x1.62e4p-1f)
+#define Ln2lo v_f32 (0x1.7f7d1cp-20f)
+
+VPCS_ATTR
+static v_f32_t
+specialcase (v_f32_t poly, v_f32_t n, v_u32_t e, v_f32_t absn)
+{
+  /* 2^n may overflow, break it up into s1*s2.  */
+  v_u32_t b = v_cond_u32 (n <= v_f32 (0.0f)) & v_u32 (0x83000000);
+  v_f32_t s1 = v_as_f32_u32 (v_u32 (0x7f000000) + b);
+  v_f32_t s2 = v_as_f32_u32 (e - b);
+  v_u32_t cmp = v_cond_u32 (absn > v_f32 (192.0f));
+  v_f32_t r1 = s1 * s1;
+  v_f32_t r0 = poly * s1 * s2;
+  return v_as_f32_u32 ((cmp & v_as_u32_f32 (r1)) | (~cmp & v_as_u32_f32 (r0)));
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(expf_1u) (v_f32_t x)
+{
+  v_f32_t n, r, scale, poly, absn, z;
+  v_u32_t cmp, e;
+
+  /* exp(x) = 2^n * poly(r), with poly(r) in [1/sqrt(2),sqrt(2)]
+     x = ln2*n + r, with r in [-ln2/2, ln2/2].  */
+#if 1
+  z = v_fma_f32 (x, InvLn2, Shift);
+  n = z - Shift;
+  r = v_fma_f32 (n, -Ln2hi, x);
+  r = v_fma_f32 (n, -Ln2lo, r);
+  e = v_as_u32_f32 (z) << 23;
+#else
+  z = x * InvLn2;
+  n = v_round_f32 (z);
+  r = v_fma_f32 (n, -Ln2hi, x);
+  r = v_fma_f32 (n, -Ln2lo, r);
+  e = v_as_u32_s32 (v_round_s32 (z)) << 23;
+#endif
+  scale = v_as_f32_u32 (e + v_u32 (0x3f800000));
+  absn = v_abs_f32 (n);
+  cmp = v_cond_u32 (absn > v_f32 (126.0f));
+  poly = v_fma_f32 (C0, r, C1);
+  poly = v_fma_f32 (poly, r, C2);
+  poly = v_fma_f32 (poly, r, C3);
+  poly = v_fma_f32 (poly, r, C4);
+  poly = v_fma_f32 (poly, r, v_f32 (1.0f));
+  poly = v_fma_f32 (poly, r, v_f32 (1.0f));
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (poly, n, e, absn);
+  return scale * poly;
+}
+#endif
diff --git a/libc/AOR_v20.02/math/v_log.c b/libc/AOR_v20.02/math/v_log.c
new file mode 100644
index 0000000000000..06340fe62584b
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_log.c
@@ -0,0 +1,105 @@
+/*
+ * Double-precision vector log(x) function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#include "v_log.h"
+#if V_SUPPORTED
+
+/* Worst-case error: 1.17 + 0.5 ulp.  */
+
+static const f64_t Poly[] = {
+  /* rel error: 0x1.6272e588p-56 in [ -0x1.fc1p-9 0x1.009p-8 ].  */
+  -0x1.ffffffffffff7p-2,
+   0x1.55555555170d4p-2,
+  -0x1.0000000399c27p-2,
+   0x1.999b2e90e94cap-3,
+  -0x1.554e550bd501ep-3,
+};
+
+#define A0 v_f64 (Poly[0])
+#define A1 v_f64 (Poly[1])
+#define A2 v_f64 (Poly[2])
+#define A3 v_f64 (Poly[3])
+#define A4 v_f64 (Poly[4])
+#define Ln2 v_f64 (0x1.62e42fefa39efp-1)
+#define N (1 << V_LOG_TABLE_BITS)
+#define OFF v_u64 (0x3fe6900900000000)
+
+struct entry
+{
+  v_f64_t invc;
+  v_f64_t logc;
+};
+
+static inline struct entry
+lookup (v_u64_t i)
+{
+  struct entry e;
+#ifdef SCALAR
+  e.invc = __v_log_data[i].invc;
+  e.logc = __v_log_data[i].logc;
+#else
+  e.invc[0] = __v_log_data[i[0]].invc;
+  e.logc[0] = __v_log_data[i[0]].logc;
+  e.invc[1] = __v_log_data[i[1]].invc;
+  e.logc[1] = __v_log_data[i[1]].logc;
+#endif
+  return e;
+}
+
+VPCS_ATTR
+__attribute__ ((noinline)) static v_f64_t
+specialcase (v_f64_t x, v_f64_t y, v_u64_t cmp)
+{
+  return v_call_f64 (log, x, y, cmp);
+}
+
+VPCS_ATTR
+v_f64_t
+V_NAME(log) (v_f64_t x)
+{
+  v_f64_t z, r, r2, p, y, kd, hi;
+  v_u64_t ix, iz, tmp, top, i, cmp;
+  v_s64_t k;
+  struct entry e;
+
+  ix = v_as_u64_f64 (x);
+  top = ix >> 48;
+  cmp = v_cond_u64 (top - v_u64 (0x0010) >= v_u64 (0x7ff0 - 0x0010));
+
+  /* x = 2^k z; where z is in range [OFF,2*OFF) and exact.
+     The range is split into N subintervals.
+     The ith subinterval contains z and c is near its center.  */
+  tmp = ix - OFF;
+  i = (tmp >> (52 - V_LOG_TABLE_BITS)) % N;
+  k = v_as_s64_u64 (tmp) >> 52; /* arithmetic shift */
+  iz = ix - (tmp & v_u64 (0xfffULL << 52));
+  z = v_as_f64_u64 (iz);
+  e = lookup (i);
+
+  /* log(x) = log1p(z/c-1) + log(c) + k*Ln2.  */
+  r = v_fma_f64 (z, e.invc, v_f64 (-1.0));
+  kd = v_to_f64_s64 (k);
+
+  /* hi = r + log(c) + k*Ln2.  */
+  hi = v_fma_f64 (kd, Ln2, e.logc + r);
+  /* y = r2*(A0 + r*A1 + r2*(A2 + r*A3 + r2*A4)) + hi.  */
+  r2 = r * r;
+  y = v_fma_f64 (A3, r, A2);
+  p = v_fma_f64 (A1, r, A0);
+  y = v_fma_f64 (A4, r2, y);
+  y = v_fma_f64 (y, r2, p);
+  y = v_fma_f64 (y, r2, hi);
+
+  if (unlikely (v_any_u64 (cmp)))
+    return specialcase (x, y, cmp);
+  return y;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_log.h b/libc/AOR_v20.02/math/v_log.h
new file mode 100644
index 0000000000000..a50fe9e4671b5
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_log.h
@@ -0,0 +1,19 @@
+/*
+ * Declarations for double-precision log(x) vector function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "v_math.h"
+#if WANT_VMATH
+
+#define V_LOG_TABLE_BITS 7
+
+extern const struct v_log_data
+{
+  f64_t invc;
+  f64_t logc;
+} __v_log_data[1 << V_LOG_TABLE_BITS] HIDDEN;
+#endif
diff --git a/libc/AOR_v20.02/math/v_log_data.c b/libc/AOR_v20.02/math/v_log_data.c
new file mode 100644
index 0000000000000..a7da633648a8c
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_log_data.c
@@ -0,0 +1,159 @@
+/*
+ * Lookup table for double-precision log(x) vector function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "v_log.h"
+#if WANT_VMATH
+
+#define N (1 << V_LOG_TABLE_BITS)
+
+/* Algorithm:
+
+	x = 2^k z
+	log(x) = k ln2 + log(c) + poly(z/c - 1)
+
+where z is in [a;2a) which is split into N subintervals (a=0x1.69009p-1,N=128)
+and log(c) and 1/c for the ith subinterval comes from a lookup table:
+
+	tab[i].invc = 1/c
+	tab[i].logc = (double)log(c)
+
+where c is near the center of the subinterval and is chosen by trying several
+floating point invc candidates around 1/center and selecting one for which
+the error in (double)log(c) is minimized (< 0x1p-74), except the subinterval
+that contains 1 and the previous one got tweaked to avoid cancellation.  */
+const struct v_log_data __v_log_data[N] = {
+{0x1.6a133d0dec120p+0, -0x1.62fe995eb963ap-2},
+{0x1.6815f2f3e42edp+0, -0x1.5d5a48dad6b67p-2},
+{0x1.661e39be1ac9ep+0, -0x1.57bde257d2769p-2},
+{0x1.642bfa30ac371p+0, -0x1.52294fbf2af55p-2},
+{0x1.623f1d916f323p+0, -0x1.4c9c7b598aa38p-2},
+{0x1.60578da220f65p+0, -0x1.47174fc5ff560p-2},
+{0x1.5e75349dea571p+0, -0x1.4199b7fa7b5cap-2},
+{0x1.5c97fd387a75ap+0, -0x1.3c239f48cfb99p-2},
+{0x1.5abfd2981f200p+0, -0x1.36b4f154d2aebp-2},
+{0x1.58eca051dc99cp+0, -0x1.314d9a0ff32fbp-2},
+{0x1.571e526d9df12p+0, -0x1.2bed85cca3cffp-2},
+{0x1.5554d555b3fcbp+0, -0x1.2694a11421af9p-2},
+{0x1.539015e2a20cdp+0, -0x1.2142d8d014fb2p-2},
+{0x1.51d0014ee0164p+0, -0x1.1bf81a2c77776p-2},
+{0x1.50148538cd9eep+0, -0x1.16b452a39c6a4p-2},
+{0x1.4e5d8f9f698a1p+0, -0x1.11776ffa6c67ep-2},
+{0x1.4cab0edca66bep+0, -0x1.0c416035020e0p-2},
+{0x1.4afcf1a9db874p+0, -0x1.071211aa10fdap-2},
+{0x1.495327136e16fp+0, -0x1.01e972e293b1bp-2},
+{0x1.47ad9e84af28fp+0, -0x1.f98ee587fd434p-3},
+{0x1.460c47b39ae15p+0, -0x1.ef5800ad716fbp-3},
+{0x1.446f12b278001p+0, -0x1.e52e160484698p-3},
+{0x1.42d5efdd720ecp+0, -0x1.db1104b19352ep-3},
+{0x1.4140cfe001a0fp+0, -0x1.d100ac59e0bd6p-3},
+{0x1.3fafa3b421f69p+0, -0x1.c6fced287c3bdp-3},
+{0x1.3e225c9c8ece5p+0, -0x1.bd05a7b317c29p-3},
+{0x1.3c98ec29a211ap+0, -0x1.b31abd229164fp-3},
+{0x1.3b13442a413fep+0, -0x1.a93c0edadb0a3p-3},
+{0x1.399156baa3c54p+0, -0x1.9f697ee30d7ddp-3},
+{0x1.38131639b4cdbp+0, -0x1.95a2efa9aa40ap-3},
+{0x1.36987540fbf53p+0, -0x1.8be843d796044p-3},
+{0x1.352166b648f61p+0, -0x1.82395ecc477edp-3},
+{0x1.33adddb3eb575p+0, -0x1.7896240966422p-3},
+{0x1.323dcd99fc1d3p+0, -0x1.6efe77aca8c55p-3},
+{0x1.30d129fefc7d2p+0, -0x1.65723e117ec5cp-3},
+{0x1.2f67e6b72fe7dp+0, -0x1.5bf15c0955706p-3},
+{0x1.2e01f7cf8b187p+0, -0x1.527bb6c111da1p-3},
+{0x1.2c9f518ddc86ep+0, -0x1.491133c939f8fp-3},
+{0x1.2b3fe86e5f413p+0, -0x1.3fb1b90c7fc58p-3},
+{0x1.29e3b1211b25cp+0, -0x1.365d2cc485f8dp-3},
+{0x1.288aa08b373cfp+0, -0x1.2d13758970de7p-3},
+{0x1.2734abcaa8467p+0, -0x1.23d47a721fd47p-3},
+{0x1.25e1c82459b81p+0, -0x1.1aa0229f25ec2p-3},
+{0x1.2491eb1ad59c5p+0, -0x1.117655ddebc3bp-3},
+{0x1.23450a54048b5p+0, -0x1.0856fbf83ab6bp-3},
+{0x1.21fb1bb09e578p+0, -0x1.fe83fabbaa106p-4},
+{0x1.20b415346d8f7p+0, -0x1.ec6e8507a56cdp-4},
+{0x1.1f6fed179a1acp+0, -0x1.da6d68c7cc2eap-4},
+{0x1.1e2e99b93c7b3p+0, -0x1.c88078462be0cp-4},
+{0x1.1cf011a7a882ap+0, -0x1.b6a786a423565p-4},
+{0x1.1bb44b97dba5ap+0, -0x1.a4e2676ac7f85p-4},
+{0x1.1a7b3e66cdd4fp+0, -0x1.9330eea777e76p-4},
+{0x1.1944e11dc56cdp+0, -0x1.8192f134d5ad9p-4},
+{0x1.18112aebb1a6ep+0, -0x1.70084464f0538p-4},
+{0x1.16e013231b7e9p+0, -0x1.5e90bdec5cb1fp-4},
+{0x1.15b1913f156cfp+0, -0x1.4d2c3433c5536p-4},
+{0x1.14859cdedde13p+0, -0x1.3bda7e219879ap-4},
+{0x1.135c2dc68cfa4p+0, -0x1.2a9b732d27194p-4},
+{0x1.12353bdb01684p+0, -0x1.196eeb2b10807p-4},
+{0x1.1110bf25b85b4p+0, -0x1.0854be8ef8a7ep-4},
+{0x1.0feeafd2f8577p+0, -0x1.ee998cb277432p-5},
+{0x1.0ecf062c51c3bp+0, -0x1.ccadb79919fb9p-5},
+{0x1.0db1baa076c8bp+0, -0x1.aae5b1d8618b0p-5},
+{0x1.0c96c5bb3048ep+0, -0x1.89413015d7442p-5},
+{0x1.0b7e20263e070p+0, -0x1.67bfe7bf158dep-5},
+{0x1.0a67c2acd0ce3p+0, -0x1.46618f83941bep-5},
+{0x1.0953a6391e982p+0, -0x1.2525df1b0618ap-5},
+{0x1.0841c3caea380p+0, -0x1.040c8e2f77c6ap-5},
+{0x1.07321489b13eap+0, -0x1.c62aad39f738ap-6},
+{0x1.062491aee9904p+0, -0x1.847fe3bdead9cp-6},
+{0x1.05193497a7cc5p+0, -0x1.43183683400acp-6},
+{0x1.040ff6b5f5e9fp+0, -0x1.01f31c4e1d544p-6},
+{0x1.0308d19aa6127p+0, -0x1.82201d1e6b69ap-7},
+{0x1.0203beedb0c67p+0, -0x1.00dd0f3e1bfd6p-7},
+{0x1.010037d38bcc2p+0, -0x1.ff6fe1feb4e53p-9},
+{1.0, 0.0},
+{0x1.fc06d493cca10p-1, 0x1.fe91885ec8e20p-8},
+{0x1.f81e6ac3b918fp-1, 0x1.fc516f716296dp-7},
+{0x1.f44546ef18996p-1, 0x1.7bb4dd70a015bp-6},
+{0x1.f07b10382c84bp-1, 0x1.f84c99b34b674p-6},
+{0x1.ecbf7070e59d4p-1, 0x1.39f9ce4fb2d71p-5},
+{0x1.e91213f715939p-1, 0x1.7756c0fd22e78p-5},
+{0x1.e572a9a75f7b7p-1, 0x1.b43ee82db8f3ap-5},
+{0x1.e1e0e2c530207p-1, 0x1.f0b3fced60034p-5},
+{0x1.de5c72d8a8be3p-1, 0x1.165bd78d4878ep-4},
+{0x1.dae50fa5658ccp-1, 0x1.3425d2715ebe6p-4},
+{0x1.d77a71145a2dap-1, 0x1.51b8bd91b7915p-4},
+{0x1.d41c51166623ep-1, 0x1.6f15632c76a47p-4},
+{0x1.d0ca6ba0bb29fp-1, 0x1.8c3c88ecbe503p-4},
+{0x1.cd847e8e59681p-1, 0x1.a92ef077625dap-4},
+{0x1.ca4a499693e00p-1, 0x1.c5ed5745fa006p-4},
+{0x1.c71b8e399e821p-1, 0x1.e27876de1c993p-4},
+{0x1.c3f80faf19077p-1, 0x1.fed104fce4cdcp-4},
+{0x1.c0df92dc2b0ecp-1, 0x1.0d7bd9c17d78bp-3},
+{0x1.bdd1de3cbb542p-1, 0x1.1b76986cef97bp-3},
+{0x1.baceb9e1007a3p-1, 0x1.295913d24f750p-3},
+{0x1.b7d5ef543e55ep-1, 0x1.37239fa295d17p-3},
+{0x1.b4e749977d953p-1, 0x1.44d68dd78714bp-3},
+{0x1.b20295155478ep-1, 0x1.52722ebe5d780p-3},
+{0x1.af279f8e82be2p-1, 0x1.5ff6d12671f98p-3},
+{0x1.ac5638197fdf3p-1, 0x1.6d64c2389484bp-3},
+{0x1.a98e2f102e087p-1, 0x1.7abc4da40fddap-3},
+{0x1.a6cf5606d05c1p-1, 0x1.87fdbda1e8452p-3},
+{0x1.a4197fc04d746p-1, 0x1.95295b06a5f37p-3},
+{0x1.a16c80293dc01p-1, 0x1.a23f6d34abbc5p-3},
+{0x1.9ec82c4dc5bc9p-1, 0x1.af403a28e04f2p-3},
+{0x1.9c2c5a491f534p-1, 0x1.bc2c06a85721ap-3},
+{0x1.9998e1480b618p-1, 0x1.c903161240163p-3},
+{0x1.970d9977c6c2dp-1, 0x1.d5c5aa93287ebp-3},
+{0x1.948a5c023d212p-1, 0x1.e274051823fa9p-3},
+{0x1.920f0303d6809p-1, 0x1.ef0e656300c16p-3},
+{0x1.8f9b698a98b45p-1, 0x1.fb9509f05aa2ap-3},
+{0x1.8d2f6b81726f6p-1, 0x1.04041821f37afp-2},
+{0x1.8acae5bb55badp-1, 0x1.0a340a49b3029p-2},
+{0x1.886db5d9275b8p-1, 0x1.105a7918a126dp-2},
+{0x1.8617ba567c13cp-1, 0x1.1677819812b84p-2},
+{0x1.83c8d27487800p-1, 0x1.1c8b405b40c0ep-2},
+{0x1.8180de3c5dbe7p-1, 0x1.2295d16cfa6b1p-2},
+{0x1.7f3fbe71cdb71p-1, 0x1.28975066318a2p-2},
+{0x1.7d055498071c1p-1, 0x1.2e8fd855d86fcp-2},
+{0x1.7ad182e54f65ap-1, 0x1.347f83d605e59p-2},
+{0x1.78a42c3c90125p-1, 0x1.3a666d1244588p-2},
+{0x1.767d342f76944p-1, 0x1.4044adb6f8ec4p-2},
+{0x1.745c7ef26b00ap-1, 0x1.461a5f077558cp-2},
+{0x1.7241f15769d0fp-1, 0x1.4be799e20b9c8p-2},
+{0x1.702d70d396e41p-1, 0x1.51ac76a6b79dfp-2},
+{0x1.6e1ee3700cd11p-1, 0x1.57690d5744a45p-2},
+{0x1.6c162fc9cbe02p-1, 0x1.5d1d758e45217p-2},
+};
+#endif
diff --git a/libc/AOR_v20.02/math/v_logf.c b/libc/AOR_v20.02/math/v_logf.c
new file mode 100644
index 0000000000000..dbe2acef8c049
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_logf.c
@@ -0,0 +1,74 @@
+/*
+ * Single-precision vector log function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /* 3.34 ulp error */
+  -0x1.3e737cp-3f, 0x1.5a9aa2p-3f, -0x1.4f9934p-3f, 0x1.961348p-3f,
+  -0x1.00187cp-2f, 0x1.555d7cp-2f, -0x1.ffffc8p-2f,
+};
+#define P7 v_f32 (Poly[0])
+#define P6 v_f32 (Poly[1])
+#define P5 v_f32 (Poly[2])
+#define P4 v_f32 (Poly[3])
+#define P3 v_f32 (Poly[4])
+#define P2 v_f32 (Poly[5])
+#define P1 v_f32 (Poly[6])
+
+#define Ln2 v_f32 (0x1.62e43p-1f) /* 0x3f317218 */
+#define Min v_u32 (0x00800000)
+#define Max v_u32 (0x7f800000)
+#define Mask v_u32 (0x007fffff)
+#define Off v_u32 (0x3f2aaaab) /* 0.666667 */
+
+VPCS_ATTR
+__attribute__ ((noinline)) static v_f32_t
+specialcase (v_f32_t x, v_f32_t y, v_u32_t cmp)
+{
+  /* Fall back to scalar code.  */
+  return v_call_f32 (logf, x, y, cmp);
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(logf) (v_f32_t x)
+{
+  v_f32_t n, p, q, r, r2, y;
+  v_u32_t u, cmp;
+
+  u = v_as_u32_f32 (x);
+  cmp = v_cond_u32 (u - Min >= Max - Min);
+
+  /* x = 2^n * (1+r), where 2/3 < 1+r < 4/3 */
+  u -= Off;
+  n = v_to_f32_s32 (v_as_s32_u32 (u) >> 23); /* signextend */
+  u &= Mask;
+  u += Off;
+  r = v_as_f32_u32 (u) - v_f32 (1.0f);
+
+  /* y = log(1+r) + n*ln2.  */
+  r2 = r * r;
+  /* n*ln2 + r + r2*(P1 + r*P2 + r2*(P3 + r*P4 + r2*(P5 + r*P6 + r2*P7))).  */
+  p = v_fma_f32 (P6, r, P5);
+  q = v_fma_f32 (P4, r, P3);
+  y = v_fma_f32 (P2, r, P1);
+  p = v_fma_f32 (P7, r2, p);
+  q = v_fma_f32 (p, r2, q);
+  y = v_fma_f32 (q, r2, y);
+  p = v_fma_f32 (Ln2, n, r);
+  y = v_fma_f32 (y, r2, p);
+
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (x, y, cmp);
+  return y;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_math.h b/libc/AOR_v20.02/math/v_math.h
new file mode 100644
index 0000000000000..4b2a6d19faaf5
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_math.h
@@ -0,0 +1,642 @@
+/*
+ * Vector math abstractions.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef _V_MATH_H
+#define _V_MATH_H
+
+#ifndef WANT_VMATH
+/* Enable the build of vector math code.  */
+# define WANT_VMATH 1
+#endif
+#if WANT_VMATH
+
+/* The goal of this header is to allow vector and scalar
+   build of the same algorithm, the provided intrinsic
+   wrappers are also vector length agnostic so they can
+   be implemented for SVE too (or other simd architectures)
+   and then the code should work on those targets too.  */
+
+#if SCALAR
+#define V_NAME(x) __s_##x
+#elif VPCS && __aarch64__
+#define V_NAME(x) __vn_##x
+#define VPCS_ATTR __attribute__ ((aarch64_vector_pcs))
+#else
+#define V_NAME(x) __v_##x
+#endif
+
+#ifndef VPCS_ATTR
+#define VPCS_ATTR
+#endif
+#ifndef VPCS_ALIAS
+#define VPCS_ALIAS
+#endif
+
+#include <stdint.h>
+#include "math_config.h"
+
+typedef float f32_t;
+typedef uint32_t u32_t;
+typedef int32_t s32_t;
+typedef double f64_t;
+typedef uint64_t u64_t;
+typedef int64_t s64_t;
+
+/* reinterpret as type1 from type2.  */
+static inline u32_t
+as_u32_f32 (f32_t x)
+{
+  union { f32_t f; u32_t u; } r = {x};
+  return r.u;
+}
+static inline f32_t
+as_f32_u32 (u32_t x)
+{
+  union { u32_t u; f32_t f; } r = {x};
+  return r.f;
+}
+static inline s32_t
+as_s32_u32 (u32_t x)
+{
+  union { u32_t u; s32_t i; } r = {x};
+  return r.i;
+}
+static inline u32_t
+as_u32_s32 (s32_t x)
+{
+  union { s32_t i; u32_t u; } r = {x};
+  return r.u;
+}
+static inline u64_t
+as_u64_f64 (f64_t x)
+{
+  union { f64_t f; u64_t u; } r = {x};
+  return r.u;
+}
+static inline f64_t
+as_f64_u64 (u64_t x)
+{
+  union { u64_t u; f64_t f; } r = {x};
+  return r.f;
+}
+static inline s64_t
+as_s64_u64 (u64_t x)
+{
+  union { u64_t u; s64_t i; } r = {x};
+  return r.i;
+}
+static inline u64_t
+as_u64_s64 (s64_t x)
+{
+  union { s64_t i; u64_t u; } r = {x};
+  return r.u;
+}
+
+#if SCALAR
+#define V_SUPPORTED 1
+typedef f32_t v_f32_t;
+typedef u32_t v_u32_t;
+typedef s32_t v_s32_t;
+typedef f64_t v_f64_t;
+typedef u64_t v_u64_t;
+typedef s64_t v_s64_t;
+
+static inline int
+v_lanes32 (void)
+{
+  return 1;
+}
+
+static inline v_f32_t
+v_f32 (f32_t x)
+{
+  return x;
+}
+static inline v_u32_t
+v_u32 (u32_t x)
+{
+  return x;
+}
+static inline v_s32_t
+v_s32 (s32_t x)
+{
+  return x;
+}
+
+static inline f32_t
+v_get_f32 (v_f32_t x, int i)
+{
+  return x;
+}
+static inline u32_t
+v_get_u32 (v_u32_t x, int i)
+{
+  return x;
+}
+static inline s32_t
+v_get_s32 (v_s32_t x, int i)
+{
+  return x;
+}
+
+static inline void
+v_set_f32 (v_f32_t *x, int i, f32_t v)
+{
+  *x = v;
+}
+static inline void
+v_set_u32 (v_u32_t *x, int i, u32_t v)
+{
+  *x = v;
+}
+static inline void
+v_set_s32 (v_s32_t *x, int i, s32_t v)
+{
+  *x = v;
+}
+
+/* true if any elements of a v_cond result is non-zero.  */
+static inline int
+v_any_u32 (v_u32_t x)
+{
+  return x != 0;
+}
+/* to wrap the result of relational operators.  */
+static inline v_u32_t
+v_cond_u32 (v_u32_t x)
+{
+  return x ? -1 : 0;
+}
+static inline v_f32_t
+v_abs_f32 (v_f32_t x)
+{
+  return __builtin_fabsf (x);
+}
+static inline v_f32_t
+v_fma_f32 (v_f32_t x, v_f32_t y, v_f32_t z)
+{
+  return __builtin_fmaf (x, y, z);
+}
+static inline v_f32_t
+v_round_f32 (v_f32_t x)
+{
+  return __builtin_roundf (x);
+}
+static inline v_s32_t
+v_round_s32 (v_f32_t x)
+{
+  return __builtin_lroundf (x); /* relies on -fno-math-errno.  */
+}
+/* convert to type1 from type2.  */
+static inline v_f32_t
+v_to_f32_s32 (v_s32_t x)
+{
+  return x;
+}
+static inline v_f32_t
+v_to_f32_u32 (v_u32_t x)
+{
+  return x;
+}
+/* reinterpret as type1 from type2.  */
+static inline v_u32_t
+v_as_u32_f32 (v_f32_t x)
+{
+  union { v_f32_t f; v_u32_t u; } r = {x};
+  return r.u;
+}
+static inline v_f32_t
+v_as_f32_u32 (v_u32_t x)
+{
+  union { v_u32_t u; v_f32_t f; } r = {x};
+  return r.f;
+}
+static inline v_s32_t
+v_as_s32_u32 (v_u32_t x)
+{
+  union { v_u32_t u; v_s32_t i; } r = {x};
+  return r.i;
+}
+static inline v_u32_t
+v_as_u32_s32 (v_s32_t x)
+{
+  union { v_s32_t i; v_u32_t u; } r = {x};
+  return r.u;
+}
+static inline v_f32_t
+v_lookup_f32 (const f32_t *tab, v_u32_t idx)
+{
+  return tab[idx];
+}
+static inline v_u32_t
+v_lookup_u32 (const u32_t *tab, v_u32_t idx)
+{
+  return tab[idx];
+}
+static inline v_f32_t
+v_call_f32 (f32_t (*f) (f32_t), v_f32_t x, v_f32_t y, v_u32_t p)
+{
+  return f (x);
+}
+static inline v_f32_t
+v_call2_f32 (f32_t (*f) (f32_t, f32_t), v_f32_t x1, v_f32_t x2, v_f32_t y,
+	     v_u32_t p)
+{
+  return f (x1, x2);
+}
+
+static inline int
+v_lanes64 (void)
+{
+  return 1;
+}
+static inline v_f64_t
+v_f64 (f64_t x)
+{
+  return x;
+}
+static inline v_u64_t
+v_u64 (u64_t x)
+{
+  return x;
+}
+static inline v_s64_t
+v_s64 (s64_t x)
+{
+  return x;
+}
+static inline f64_t
+v_get_f64 (v_f64_t x, int i)
+{
+  return x;
+}
+static inline void
+v_set_f64 (v_f64_t *x, int i, f64_t v)
+{
+  *x = v;
+}
+/* true if any elements of a v_cond result is non-zero.  */
+static inline int
+v_any_u64 (v_u64_t x)
+{
+  return x != 0;
+}
+/* to wrap the result of relational operators.  */
+static inline v_u64_t
+v_cond_u64 (v_u64_t x)
+{
+  return x ? -1 : 0;
+}
+static inline v_f64_t
+v_abs_f64 (v_f64_t x)
+{
+  return __builtin_fabs (x);
+}
+static inline v_f64_t
+v_fma_f64 (v_f64_t x, v_f64_t y, v_f64_t z)
+{
+  return __builtin_fma (x, y, z);
+}
+static inline v_f64_t
+v_round_f64 (v_f64_t x)
+{
+  return __builtin_round (x);
+}
+static inline v_s64_t
+v_round_s64 (v_f64_t x)
+{
+  return __builtin_lround (x); /* relies on -fno-math-errno.  */
+}
+/* convert to type1 from type2.  */
+static inline v_f64_t
+v_to_f64_s64 (v_s64_t x)
+{
+  return x;
+}
+static inline v_f64_t
+v_to_f64_u64 (v_u64_t x)
+{
+  return x;
+}
+/* reinterpret as type1 from type2.  */
+static inline v_u64_t
+v_as_u64_f64 (v_f64_t x)
+{
+  union { v_f64_t f; v_u64_t u; } r = {x};
+  return r.u;
+}
+static inline v_f64_t
+v_as_f64_u64 (v_u64_t x)
+{
+  union { v_u64_t u; v_f64_t f; } r = {x};
+  return r.f;
+}
+static inline v_s64_t
+v_as_s64_u64 (v_u64_t x)
+{
+  union { v_u64_t u; v_s64_t i; } r = {x};
+  return r.i;
+}
+static inline v_u64_t
+v_as_u64_s64 (v_s64_t x)
+{
+  union { v_s64_t i; v_u64_t u; } r = {x};
+  return r.u;
+}
+static inline v_f64_t
+v_lookup_f64 (const f64_t *tab, v_u64_t idx)
+{
+  return tab[idx];
+}
+static inline v_u64_t
+v_lookup_u64 (const u64_t *tab, v_u64_t idx)
+{
+  return tab[idx];
+}
+static inline v_f64_t
+v_call_f64 (f64_t (*f) (f64_t), v_f64_t x, v_f64_t y, v_u64_t p)
+{
+  return f (x);
+}
+
+#elif __aarch64__
+#define V_SUPPORTED 1
+#include <arm_neon.h>
+typedef float32x4_t v_f32_t;
+typedef uint32x4_t v_u32_t;
+typedef int32x4_t v_s32_t;
+typedef float64x2_t v_f64_t;
+typedef uint64x2_t v_u64_t;
+typedef int64x2_t v_s64_t;
+
+static inline int
+v_lanes32 (void)
+{
+  return 4;
+}
+
+static inline v_f32_t
+v_f32 (f32_t x)
+{
+  return (v_f32_t){x, x, x, x};
+}
+static inline v_u32_t
+v_u32 (u32_t x)
+{
+  return (v_u32_t){x, x, x, x};
+}
+static inline v_s32_t
+v_s32 (s32_t x)
+{
+  return (v_s32_t){x, x, x, x};
+}
+
+static inline f32_t
+v_get_f32 (v_f32_t x, int i)
+{
+  return x[i];
+}
+static inline u32_t
+v_get_u32 (v_u32_t x, int i)
+{
+  return x[i];
+}
+static inline s32_t
+v_get_s32 (v_s32_t x, int i)
+{
+  return x[i];
+}
+
+static inline void
+v_set_f32 (v_f32_t *x, int i, f32_t v)
+{
+  (*x)[i] = v;
+}
+static inline void
+v_set_u32 (v_u32_t *x, int i, u32_t v)
+{
+  (*x)[i] = v;
+}
+static inline void
+v_set_s32 (v_s32_t *x, int i, s32_t v)
+{
+  (*x)[i] = v;
+}
+
+/* true if any elements of a v_cond result is non-zero.  */
+static inline int
+v_any_u32 (v_u32_t x)
+{
+  /* assume elements in x are either 0 or -1u.  */
+  return vpaddd_u64 (vreinterpretq_u64_u32 (x)) != 0;
+}
+/* to wrap the result of relational operators.  */
+static inline v_u32_t
+v_cond_u32 (v_u32_t x)
+{
+  return x;
+}
+static inline v_f32_t
+v_abs_f32 (v_f32_t x)
+{
+  return vabsq_f32 (x);
+}
+static inline v_f32_t
+v_fma_f32 (v_f32_t x, v_f32_t y, v_f32_t z)
+{
+  return vfmaq_f32 (z, x, y);
+}
+static inline v_f32_t
+v_round_f32 (v_f32_t x)
+{
+  return vrndaq_f32 (x);
+}
+static inline v_s32_t
+v_round_s32 (v_f32_t x)
+{
+  return vcvtaq_s32_f32 (x);
+}
+/* convert to type1 from type2.  */
+static inline v_f32_t
+v_to_f32_s32 (v_s32_t x)
+{
+  return (v_f32_t){x[0], x[1], x[2], x[3]};
+}
+static inline v_f32_t
+v_to_f32_u32 (v_u32_t x)
+{
+  return (v_f32_t){x[0], x[1], x[2], x[3]};
+}
+/* reinterpret as type1 from type2.  */
+static inline v_u32_t
+v_as_u32_f32 (v_f32_t x)
+{
+  union { v_f32_t f; v_u32_t u; } r = {x};
+  return r.u;
+}
+static inline v_f32_t
+v_as_f32_u32 (v_u32_t x)
+{
+  union { v_u32_t u; v_f32_t f; } r = {x};
+  return r.f;
+}
+static inline v_s32_t
+v_as_s32_u32 (v_u32_t x)
+{
+  union { v_u32_t u; v_s32_t i; } r = {x};
+  return r.i;
+}
+static inline v_u32_t
+v_as_u32_s32 (v_s32_t x)
+{
+  union { v_s32_t i; v_u32_t u; } r = {x};
+  return r.u;
+}
+static inline v_f32_t
+v_lookup_f32 (const f32_t *tab, v_u32_t idx)
+{
+  return (v_f32_t){tab[idx[0]], tab[idx[1]], tab[idx[2]], tab[idx[3]]};
+}
+static inline v_u32_t
+v_lookup_u32 (const u32_t *tab, v_u32_t idx)
+{
+  return (v_u32_t){tab[idx[0]], tab[idx[1]], tab[idx[2]], tab[idx[3]]};
+}
+static inline v_f32_t
+v_call_f32 (f32_t (*f) (f32_t), v_f32_t x, v_f32_t y, v_u32_t p)
+{
+  return (v_f32_t){p[0] ? f (x[0]) : y[0], p[1] ? f (x[1]) : y[1],
+		   p[2] ? f (x[2]) : y[2], p[3] ? f (x[3]) : y[3]};
+}
+static inline v_f32_t
+v_call2_f32 (f32_t (*f) (f32_t, f32_t), v_f32_t x1, v_f32_t x2, v_f32_t y,
+	     v_u32_t p)
+{
+  return (
+    v_f32_t){p[0] ? f (x1[0], x2[0]) : y[0], p[1] ? f (x1[1], x2[1]) : y[1],
+	     p[2] ? f (x1[2], x2[2]) : y[2], p[3] ? f (x1[3], x2[3]) : y[3]};
+}
+
+static inline int
+v_lanes64 (void)
+{
+  return 2;
+}
+static inline v_f64_t
+v_f64 (f64_t x)
+{
+  return (v_f64_t){x, x};
+}
+static inline v_u64_t
+v_u64 (u64_t x)
+{
+  return (v_u64_t){x, x};
+}
+static inline v_s64_t
+v_s64 (s64_t x)
+{
+  return (v_s64_t){x, x};
+}
+static inline f64_t
+v_get_f64 (v_f64_t x, int i)
+{
+  return x[i];
+}
+static inline void
+v_set_f64 (v_f64_t *x, int i, f64_t v)
+{
+  (*x)[i] = v;
+}
+/* true if any elements of a v_cond result is non-zero.  */
+static inline int
+v_any_u64 (v_u64_t x)
+{
+  /* assume elements in x are either 0 or -1u.  */
+  return vpaddd_u64 (x) != 0;
+}
+/* to wrap the result of relational operators.  */
+static inline v_u64_t
+v_cond_u64 (v_u64_t x)
+{
+  return x;
+}
+static inline v_f64_t
+v_abs_f64 (v_f64_t x)
+{
+  return vabsq_f64 (x);
+}
+static inline v_f64_t
+v_fma_f64 (v_f64_t x, v_f64_t y, v_f64_t z)
+{
+  return vfmaq_f64 (z, x, y);
+}
+static inline v_f64_t
+v_round_f64 (v_f64_t x)
+{
+  return vrndaq_f64 (x);
+}
+static inline v_s64_t
+v_round_s64 (v_f64_t x)
+{
+  return vcvtaq_s64_f64 (x);
+}
+/* convert to type1 from type2.  */
+static inline v_f64_t
+v_to_f64_s64 (v_s64_t x)
+{
+  return (v_f64_t){x[0], x[1]};
+}
+static inline v_f64_t
+v_to_f64_u64 (v_u64_t x)
+{
+  return (v_f64_t){x[0], x[1]};
+}
+/* reinterpret as type1 from type2.  */
+static inline v_u64_t
+v_as_u64_f64 (v_f64_t x)
+{
+  union { v_f64_t f; v_u64_t u; } r = {x};
+  return r.u;
+}
+static inline v_f64_t
+v_as_f64_u64 (v_u64_t x)
+{
+  union { v_u64_t u; v_f64_t f; } r = {x};
+  return r.f;
+}
+static inline v_s64_t
+v_as_s64_u64 (v_u64_t x)
+{
+  union {  v_u64_t u; v_s64_t i; } r = {x};
+  return r.i;
+}
+static inline v_u64_t
+v_as_u64_s64 (v_s64_t x)
+{
+  union { v_s64_t i; v_u64_t u; } r = {x};
+  return r.u;
+}
+static inline v_f64_t
+v_lookup_f64 (const f64_t *tab, v_u64_t idx)
+{
+  return (v_f64_t){tab[idx[0]], tab[idx[1]]};
+}
+static inline v_u64_t
+v_lookup_u64 (const u64_t *tab, v_u64_t idx)
+{
+  return (v_u64_t){tab[idx[0]], tab[idx[1]]};
+}
+static inline v_f64_t
+v_call_f64 (f64_t (*f) (f64_t), v_f64_t x, v_f64_t y, v_u64_t p)
+{
+  return (v_f64_t){p[0] ? f (x[0]) : y[0], p[1] ? f (x[1]) : y[1]};
+}
+#endif
+
+#endif
+#endif
diff --git a/libc/AOR_v20.02/math/v_pow.c b/libc/AOR_v20.02/math/v_pow.c
new file mode 100644
index 0000000000000..e42873416f742
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_pow.c
@@ -0,0 +1,28 @@
+/*
+ * Double-precision vector pow function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+VPCS_ATTR
+v_f64_t
+V_NAME(pow) (v_f64_t x, v_f64_t y)
+{
+  v_f64_t z;
+  for (int lane = 0; lane < v_lanes64 (); lane++)
+    {
+      f64_t sx = v_get_f64 (x, lane);
+      f64_t sy = v_get_f64 (y, lane);
+      f64_t sz = pow (sx, sy);
+      v_set_f64 (&z, lane, sz);
+    }
+  return z;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_powf.c b/libc/AOR_v20.02/math/v_powf.c
new file mode 100644
index 0000000000000..c4d8db0e38fa1
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_powf.c
@@ -0,0 +1,236 @@
+/*
+ * Single-precision vector powf function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+#define Min v_u32 (0x00800000)
+#define Max v_u32 (0x7f800000)
+#define SBITS 5
+#define Tlog v__powf_log2_data.tab
+#define Texp v__exp2f_data.tab
+#define A v__powf_log2_data.poly
+#define C v__exp2f_data.poly
+#define LOGDEG 4
+
+#if LOGDEG == 5
+/* 1.01 ulp */
+#define OFF v_u32 (0x3f330000)
+#define TBITS 4
+#elif LOGDEG == 4
+/* 2.6 ulp ~ 0.5 + 2^24 (128*Ln2*relerr_log2 + relerr_exp2) */
+#define OFF v_u32 (0x3f35d000)
+#define TBITS 5
+#endif
+
+#define V_EXP2F_TABLE_BITS SBITS
+#define V_EXP2F_POLY_ORDER 3
+struct v_exp2f_data
+{
+  uint64_t tab[1 << V_EXP2F_TABLE_BITS];
+  double poly[V_EXP2F_POLY_ORDER];
+};
+
+#define V_POWF_LOG2_TABLE_BITS TBITS
+#define V_POWF_LOG2_POLY_ORDER LOGDEG
+#define SCALE ((double) (1 << SBITS))
+struct v_powf_log2_data
+{
+  struct
+  {
+    double invc, logc;
+  } tab[1 << V_POWF_LOG2_TABLE_BITS];
+  double poly[V_POWF_LOG2_POLY_ORDER];
+};
+
+static const struct v_powf_log2_data v__powf_log2_data = {
+#if LOGDEG == 5
+  .tab = {
+{ 0x1.661ec79f8f3bep+0, -0x1.efec65b963019p-2 * SCALE },
+{ 0x1.571ed4aaf883dp+0, -0x1.b0b6832d4fca4p-2 * SCALE },
+{ 0x1.49539f0f010bp+0, -0x1.7418b0a1fb77bp-2 * SCALE },
+{ 0x1.3c995b0b80385p+0, -0x1.39de91a6dcf7bp-2 * SCALE },
+{ 0x1.30d190c8864a5p+0, -0x1.01d9bf3f2b631p-2 * SCALE },
+{ 0x1.25e227b0b8eap+0, -0x1.97c1d1b3b7afp-3 * SCALE },
+{ 0x1.1bb4a4a1a343fp+0, -0x1.2f9e393af3c9fp-3 * SCALE },
+{ 0x1.12358f08ae5bap+0, -0x1.960cbbf788d5cp-4 * SCALE },
+{ 0x1.0953f419900a7p+0, -0x1.a6f9db6475fcep-5 * SCALE },
+{ 0x1p+0, 0x0p+0 * SCALE },
+{ 0x1.e608cfd9a47acp-1, 0x1.338ca9f24f53dp-4 * SCALE },
+{ 0x1.ca4b31f026aap-1, 0x1.476a9543891bap-3 * SCALE },
+{ 0x1.b2036576afce6p-1, 0x1.e840b4ac4e4d2p-3 * SCALE },
+{ 0x1.9c2d163a1aa2dp-1, 0x1.40645f0c6651cp-2 * SCALE },
+{ 0x1.886e6037841edp-1, 0x1.88e9c2c1b9ff8p-2 * SCALE },
+{ 0x1.767dcf5534862p-1, 0x1.ce0a44eb17bccp-2 * SCALE },
+  },
+/* rel err: 1.46 * 2^-32 */
+  .poly = {
+0x1.27616c9496e0bp-2 * SCALE, -0x1.71969a075c67ap-2 * SCALE,
+0x1.ec70a6ca7baddp-2 * SCALE, -0x1.7154748bef6c8p-1 * SCALE,
+0x1.71547652ab82bp0 * SCALE,
+  }
+#elif LOGDEG == 4
+  .tab = {
+{0x1.6489890582816p+0, -0x1.e960f97b22702p-2 * SCALE},
+{0x1.5cf19b35e3472p+0, -0x1.c993406cd4db6p-2 * SCALE},
+{0x1.55aac0e956d65p+0, -0x1.aa711d9a7d0f3p-2 * SCALE},
+{0x1.4eb0022977e01p+0, -0x1.8bf37bacdce9bp-2 * SCALE},
+{0x1.47fcccda1dd1fp+0, -0x1.6e13b3519946ep-2 * SCALE},
+{0x1.418ceabab68c1p+0, -0x1.50cb8281e4089p-2 * SCALE},
+{0x1.3b5c788f1edb3p+0, -0x1.341504a237e2bp-2 * SCALE},
+{0x1.3567de48e9c9ap+0, -0x1.17eaab624ffbbp-2 * SCALE},
+{0x1.2fabc80fd19bap+0, -0x1.f88e708f8c853p-3 * SCALE},
+{0x1.2a25200ce536bp+0, -0x1.c24b6da113914p-3 * SCALE},
+{0x1.24d108e0152e3p+0, -0x1.8d02ee397cb1dp-3 * SCALE},
+{0x1.1facd8ab2fbe1p+0, -0x1.58ac1223408b3p-3 * SCALE},
+{0x1.1ab614a03efdfp+0, -0x1.253e6fd190e89p-3 * SCALE},
+{0x1.15ea6d03af9ffp+0, -0x1.e5641882c12ffp-4 * SCALE},
+{0x1.1147b994bb776p+0, -0x1.81fea712926f7p-4 * SCALE},
+{0x1.0ccbf650593aap+0, -0x1.203e240de64a3p-4 * SCALE},
+{0x1.0875408477302p+0, -0x1.8029b86a78281p-5 * SCALE},
+{0x1.0441d42a93328p+0, -0x1.85d713190fb9p-6 * SCALE},
+{0x1p+0, 0x0p+0 * SCALE},
+{0x1.f1d006c855e86p-1, 0x1.4c1cc07312997p-5 * SCALE},
+{0x1.e28c3341aa301p-1, 0x1.5e1848ccec948p-4 * SCALE},
+{0x1.d4bdf9aa64747p-1, 0x1.04cfcb7f1196fp-3 * SCALE},
+{0x1.c7b45a24e5803p-1, 0x1.582813d463c21p-3 * SCALE},
+{0x1.bb5f5eb2ed60ap-1, 0x1.a936fa68760ccp-3 * SCALE},
+{0x1.afb0bff8fe6b4p-1, 0x1.f81bc31d6cc4ep-3 * SCALE},
+{0x1.a49badf7ab1f5p-1, 0x1.2279a09fae6b1p-2 * SCALE},
+{0x1.9a14a111fc4c9p-1, 0x1.47ec0b6df5526p-2 * SCALE},
+{0x1.901131f5b2fdcp-1, 0x1.6c71762280f1p-2 * SCALE},
+{0x1.8687f73f6d865p-1, 0x1.90155070798dap-2 * SCALE},
+{0x1.7d7067eb77986p-1, 0x1.b2e23b1d3068cp-2 * SCALE},
+{0x1.74c2c1cf97b65p-1, 0x1.d4e21b0daa86ap-2 * SCALE},
+{0x1.6c77f37cff2a1p-1, 0x1.f61e2a2f67f3fp-2 * SCALE},
+  },
+/* rel err: 1.5 * 2^-30 */
+  .poly = {
+ -0x1.6ff5daa3b3d7cp-2 * SCALE,
+ 0x1.ec81d03c01aebp-2 * SCALE,
+ -0x1.71547bb43f101p-1 * SCALE,
+ 0x1.7154764a815cbp0 * SCALE,
+  }
+#endif
+};
+
+static const struct v_exp2f_data v__exp2f_data = {
+  .tab = {
+0x3ff0000000000000, 0x3fefd9b0d3158574, 0x3fefb5586cf9890f, 0x3fef9301d0125b51,
+0x3fef72b83c7d517b, 0x3fef54873168b9aa, 0x3fef387a6e756238, 0x3fef1e9df51fdee1,
+0x3fef06fe0a31b715, 0x3feef1a7373aa9cb, 0x3feedea64c123422, 0x3feece086061892d,
+0x3feebfdad5362a27, 0x3feeb42b569d4f82, 0x3feeab07dd485429, 0x3feea47eb03a5585,
+0x3feea09e667f3bcd, 0x3fee9f75e8ec5f74, 0x3feea11473eb0187, 0x3feea589994cce13,
+0x3feeace5422aa0db, 0x3feeb737b0cdc5e5, 0x3feec49182a3f090, 0x3feed503b23e255d,
+0x3feee89f995ad3ad, 0x3feeff76f2fb5e47, 0x3fef199bdd85529c, 0x3fef3720dcef9069,
+0x3fef5818dcfba487, 0x3fef7c97337b9b5f, 0x3fefa4afa2a490da, 0x3fefd0765b6e4540,
+  },
+/* rel err: 1.69 * 2^-34 */
+  .poly = {
+0x1.c6af84b912394p-5/SCALE/SCALE/SCALE, 0x1.ebfce50fac4f3p-3/SCALE/SCALE, 0x1.62e42ff0c52d6p-1/SCALE
+  },
+};
+
+VPCS_ATTR
+__attribute__ ((noinline)) static v_f32_t
+specialcase (v_f32_t x, v_f32_t y, v_f32_t ret, v_u32_t cmp)
+{
+  return v_call2_f32 (powf, x, y, ret, cmp);
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(powf) (v_f32_t x, v_f32_t y)
+{
+  v_u32_t u, tmp, cmp, i, top, iz;
+  v_s32_t k;
+  v_f32_t ret;
+
+  u = v_as_u32_f32 (x);
+  cmp = v_cond_u32 (u - Min >= Max - Min);
+  tmp = u - OFF;
+  i = (tmp >> (23 - TBITS)) % (1 << TBITS);
+  top = tmp & 0xff800000;
+  iz = u - top;
+  k = v_as_s32_u32 (top) >> (23 - SBITS); /* arithmetic shift */
+
+  for (int lane = 0; lane < v_lanes32 (); lane++)
+    {
+      uint32_t si, siz;
+      int32_t sk;
+      float sy;
+
+      /* Use double precision for each lane.  */
+      double invc, logc, z, r, p, y0, logx, ylogx, kd, s;
+      uint64_t ki, t;
+
+      si = v_get_u32 (i, lane);
+      siz = v_get_u32 (iz, lane);
+      sk = v_get_s32 (k, lane);
+      sy = v_get_f32 (y, lane);
+
+      invc = Tlog[si].invc;
+      logc = Tlog[si].logc;
+      z = (double) as_f32_u32 (siz);
+
+      /* log2(x) = log1p(z/c-1)/ln2 + log2(c) + k */
+      r = __builtin_fma (z, invc, -1.0);
+      y0 = logc + (double) sk;
+
+      /* Polynomial to approximate log1p(r)/ln2.  */
+#if LOGDEG == 5
+      logx = A[0];
+      logx = r * logx + A[1];
+      logx = r * logx + A[2];
+      logx = r * logx + A[3];
+      logx = r * logx + A[4];
+      logx = r * logx + y0;
+#elif LOGDEG == 4
+      logx = A[0];
+      logx = r * logx + A[1];
+      logx = r * logx + A[2];
+      logx = r * logx + A[3];
+      logx = r * logx + y0;
+#endif
+      ylogx = sy * logx;
+      v_set_u32 (&cmp, lane,
+		 (as_u64_f64 (ylogx) >> 47 & 0xffff)
+		     >= as_u64_f64 (126.0 * (1 << SBITS)) >> 47
+		   ? 1
+		   : v_get_u32 (cmp, lane));
+
+      /* N*x = k + r with r in [-1/2, 1/2] */
+#if TOINT_INTRINSICS
+      kd = roundtoint (ylogx); /* k */
+      ki = converttoint (ylogx);
+#else
+# define SHIFT 0x1.8p52
+      kd = eval_as_double (ylogx + SHIFT);
+      ki = asuint64 (kd);
+      kd -= SHIFT;
+#endif
+      r = ylogx - kd;
+
+      /* exp2(x) = 2^(k/N) * 2^r ~= s * (C0*r^3 + C1*r^2 + C2*r + 1) */
+      t = Texp[ki % (1 << SBITS)];
+      t += ki << (52 - SBITS);
+      s = as_f64_u64 (t);
+      p = C[0];
+      p = __builtin_fma (p, r, C[1]);
+      p = __builtin_fma (p, r, C[2]);
+      p = __builtin_fma (p, s * r, s);
+
+      v_set_f32 (&ret, lane, p);
+    }
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (x, y, ret, cmp);
+  return ret;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_sin.c b/libc/AOR_v20.02/math/v_sin.c
new file mode 100644
index 0000000000000..899d1f558089e
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_sin.c
@@ -0,0 +1,87 @@
+/*
+ * Double-precision vector sin function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const double Poly[] = {
+/* worst-case error is 3.5 ulp.
+   abs error: 0x1.be222a58p-53 in [-pi/2, pi/2].  */
+-0x1.9f4a9c8b21dc9p-41,
+ 0x1.60e88a10163f2p-33,
+-0x1.ae6361b7254e7p-26,
+ 0x1.71de382e8d62bp-19,
+-0x1.a01a019aeb4ffp-13,
+ 0x1.111111110b25ep-7,
+-0x1.55555555554c3p-3,
+};
+
+#define C7 v_f64 (Poly[0])
+#define C6 v_f64 (Poly[1])
+#define C5 v_f64 (Poly[2])
+#define C4 v_f64 (Poly[3])
+#define C3 v_f64 (Poly[4])
+#define C2 v_f64 (Poly[5])
+#define C1 v_f64 (Poly[6])
+
+#define InvPi v_f64 (0x1.45f306dc9c883p-2)
+#define Pi1 v_f64 (0x1.921fb54442d18p+1)
+#define Pi2 v_f64 (0x1.1a62633145c06p-53)
+#define Pi3 v_f64 (0x1.c1cd129024e09p-106)
+#define Shift v_f64 (0x1.8p52)
+#define RangeVal v_f64 (0x1p23)
+#define AbsMask v_u64 (0x7fffffffffffffff)
+
+VPCS_ATTR
+__attribute__ ((noinline)) static v_f64_t
+specialcase (v_f64_t x, v_f64_t y, v_u64_t cmp)
+{
+  return v_call_f64 (sin, x, y, cmp);
+}
+
+VPCS_ATTR
+v_f64_t
+V_NAME(sin) (v_f64_t x)
+{
+  v_f64_t n, r, r2, y;
+  v_u64_t sign, odd, cmp;
+
+  r = v_as_f64_u64 (v_as_u64_f64 (x) & AbsMask);
+  sign = v_as_u64_f64 (x) & ~AbsMask;
+  cmp = v_cond_u64 (v_as_u64_f64 (r) >= v_as_u64_f64 (RangeVal));
+
+  /* n = rint(|x|/pi).  */
+  n = v_fma_f64 (InvPi, r, Shift);
+  odd = v_as_u64_f64 (n) << 63;
+  n -= Shift;
+
+  /* r = |x| - n*pi  (range reduction into -pi/2 .. pi/2).  */
+  r = v_fma_f64 (-Pi1, n, r);
+  r = v_fma_f64 (-Pi2, n, r);
+  r = v_fma_f64 (-Pi3, n, r);
+
+  /* sin(r) poly approx.  */
+  r2 = r * r;
+  y = v_fma_f64 (C7, r2, C6);
+  y = v_fma_f64 (y, r2, C5);
+  y = v_fma_f64 (y, r2, C4);
+  y = v_fma_f64 (y, r2, C3);
+  y = v_fma_f64 (y, r2, C2);
+  y = v_fma_f64 (y, r2, C1);
+  y = v_fma_f64 (y * r2, r, r);
+
+  /* sign.  */
+  y = v_as_f64_u64 (v_as_u64_f64 (y) ^ sign ^ odd);
+
+  if (unlikely (v_any_u64 (cmp)))
+    return specialcase (x, y, cmp);
+  return y;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/v_sinf.c b/libc/AOR_v20.02/math/v_sinf.c
new file mode 100644
index 0000000000000..de7a18f3e4ff1
--- /dev/null
+++ b/libc/AOR_v20.02/math/v_sinf.c
@@ -0,0 +1,76 @@
+/*
+ * Single-precision vector sin function.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "mathlib.h"
+#include "v_math.h"
+#if V_SUPPORTED
+
+static const float Poly[] = {
+  /* 1.886 ulp error */
+  0x1.5b2e76p-19f,
+  -0x1.9f42eap-13f,
+  0x1.110df4p-7f,
+  -0x1.555548p-3f,
+};
+#define Pi1 v_f32 (0x1.921fb6p+1f)
+#define Pi2 v_f32 (-0x1.777a5cp-24f)
+#define Pi3 v_f32 (-0x1.ee59dap-49f)
+#define A3 v_f32 (Poly[3])
+#define A5 v_f32 (Poly[2])
+#define A7 v_f32 (Poly[1])
+#define A9 v_f32 (Poly[0])
+#define RangeVal v_f32 (0x1p20f)
+#define InvPi v_f32 (0x1.45f306p-2f)
+#define Shift v_f32 (0x1.8p+23f)
+#define AbsMask v_u32 (0x7fffffff)
+
+VPCS_ATTR
+static v_f32_t
+specialcase (v_f32_t x, v_f32_t y, v_u32_t cmp)
+{
+  /* Fall back to scalar code.  */
+  return v_call_f32 (sinf, x, y, cmp);
+}
+
+VPCS_ATTR
+v_f32_t
+V_NAME(sinf) (v_f32_t x)
+{
+  v_f32_t n, r, r2, y;
+  v_u32_t sign, odd, cmp;
+
+  r = v_as_f32_u32 (v_as_u32_f32 (x) & AbsMask);
+  sign = v_as_u32_f32 (x) & ~AbsMask;
+  cmp = v_cond_u32 (v_as_u32_f32 (r) >= v_as_u32_f32 (RangeVal));
+
+  /* n = rint(|x|/pi) */
+  n = v_fma_f32 (InvPi, r, Shift);
+  odd = v_as_u32_f32 (n) << 31;
+  n -= Shift;
+
+  /* r = |x| - n*pi  (range reduction into -pi/2 .. pi/2) */
+  r = v_fma_f32 (-Pi1, n, r);
+  r = v_fma_f32 (-Pi2, n, r);
+  r = v_fma_f32 (-Pi3, n, r);
+
+  /* y = sin(r) */
+  r2 = r * r;
+  y = v_fma_f32 (A9, r2, A7);
+  y = v_fma_f32 (y, r2, A5);
+  y = v_fma_f32 (y, r2, A3);
+  y = v_fma_f32 (y * r2, r, r);
+
+  /* sign fix */
+  y = v_as_f32_u32 (v_as_u32_f32 (y) ^ sign ^ odd);
+
+  if (unlikely (v_any_u32 (cmp)))
+    return specialcase (x, y, cmp);
+  return y;
+}
+VPCS_ALIAS
+#endif
diff --git a/libc/AOR_v20.02/math/vn_cos.c b/libc/AOR_v20.02/math/vn_cos.c
new file mode 100644
index 0000000000000..76fc8b86657f2
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_cos.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_cos.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_cos, _ZGVnN2v_cos)
+#include "v_cos.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_cosf.c b/libc/AOR_v20.02/math/vn_cosf.c
new file mode 100644
index 0000000000000..2ed24ae059355
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_cosf.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_cosf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_cosf, _ZGVnN4v_cosf)
+#include "v_cosf.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_exp.c b/libc/AOR_v20.02/math/vn_exp.c
new file mode 100644
index 0000000000000..7492014dca07a
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_exp.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_exp.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_exp, _ZGVnN2v_exp)
+#include "v_exp.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_exp2f.c b/libc/AOR_v20.02/math/vn_exp2f.c
new file mode 100644
index 0000000000000..df3d56fd17f7d
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_exp2f.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_exp2f.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_exp2f, _ZGVnN4v_exp2f)
+#include "v_exp2f.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_exp2f_1u.c b/libc/AOR_v20.02/math/vn_exp2f_1u.c
new file mode 100644
index 0000000000000..b974e5b18bcc0
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_exp2f_1u.c
@@ -0,0 +1,12 @@
+/*
+ * AdvSIMD vector PCS variant of __v_exp2f_1u.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#include "v_exp2f_1u.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_expf.c b/libc/AOR_v20.02/math/vn_expf.c
new file mode 100644
index 0000000000000..de5a8cf4f316f
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_expf.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_expf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_expf, _ZGVnN4v_expf)
+#include "v_expf.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_expf_1u.c b/libc/AOR_v20.02/math/vn_expf_1u.c
new file mode 100644
index 0000000000000..20b625b25aa70
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_expf_1u.c
@@ -0,0 +1,12 @@
+/*
+ * AdvSIMD vector PCS variant of __v_expf_1u.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#include "v_expf_1u.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_log.c b/libc/AOR_v20.02/math/vn_log.c
new file mode 100644
index 0000000000000..c766d727d60db
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_log.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_log.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_log, _ZGVnN2v_log)
+#include "v_log.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_logf.c b/libc/AOR_v20.02/math/vn_logf.c
new file mode 100644
index 0000000000000..03edb1961dc4f
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_logf.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_logf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_logf, _ZGVnN4v_logf)
+#include "v_logf.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_pow.c b/libc/AOR_v20.02/math/vn_pow.c
new file mode 100644
index 0000000000000..dbad0aaa4f27e
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_pow.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_pow.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_pow, _ZGVnN2vv_pow)
+#include "v_pow.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_powf.c b/libc/AOR_v20.02/math/vn_powf.c
new file mode 100644
index 0000000000000..6fd4c76527c72
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_powf.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_powf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_powf, _ZGVnN4vv_powf)
+#include "v_powf.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_sin.c b/libc/AOR_v20.02/math/vn_sin.c
new file mode 100644
index 0000000000000..be0585be8ad9a
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_sin.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_sin.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_sin, _ZGVnN2v_sin)
+#include "v_sin.c"
+#endif
diff --git a/libc/AOR_v20.02/math/vn_sinf.c b/libc/AOR_v20.02/math/vn_sinf.c
new file mode 100644
index 0000000000000..32cd11e2fdbae
--- /dev/null
+++ b/libc/AOR_v20.02/math/vn_sinf.c
@@ -0,0 +1,13 @@
+/*
+ * AdvSIMD vector PCS variant of __v_sinf.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+#include "mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS strong_alias (__vn_sinf, _ZGVnN4v_sinf)
+#include "v_sinf.c"
+#endif
diff --git a/libc/AOR_v20.02/networking/Dir.mk b/libc/AOR_v20.02/networking/Dir.mk
new file mode 100644
index 0000000000000..68bc94b41e3d6
--- /dev/null
+++ b/libc/AOR_v20.02/networking/Dir.mk
@@ -0,0 +1,77 @@
+# Makefile fragment - requires GNU make
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+S := $(srcdir)/networking
+B := build/networking
+
+ifeq ($(ARCH),)
+all-networking check-networking install-networking clean-networking:
+	@echo "*** Please set ARCH in config.mk. ***"
+	@exit 1
+else
+
+networking-lib-srcs := $(wildcard $(S)/*.[cS]) $(wildcard $(S)/$(ARCH)/*.[cS])
+networking-test-srcs := $(wildcard $(S)/test/*.c)
+
+networking-includes := $(patsubst $(S)/%,build/%,$(wildcard $(S)/include/*.h))
+
+networking-libs := \
+	build/lib/libnetworking.so \
+	build/lib/libnetworking.a \
+
+networking-tools := \
+	build/bin/test/chksum
+
+networking-lib-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(networking-lib-srcs)))
+networking-test-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(networking-test-srcs)))
+
+networking-objs := \
+	$(networking-lib-objs) \
+	$(networking-lib-objs:%.o=%.os) \
+	$(networking-test-objs) \
+
+networking-files := \
+	$(networking-objs) \
+	$(networking-libs) \
+	$(networking-tools) \
+	$(networking-includes) \
+
+all-networking: $(networking-libs) $(networking-tools) $(networking-includes)
+
+$(networking-objs): $(networking-includes)
+$(networking-objs): CFLAGS_ALL += $(networking-cflags)
+
+build/lib/libnetworking.so: $(networking-lib-objs:%.o=%.os)
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -shared -o $@ $^
+
+build/lib/libnetworkinglib.a: $(networking-lib-objs)
+	rm -f $@
+	$(AR) rc $@ $^
+	$(RANLIB) $@
+
+build/bin/test/%: $(B)/test/%.o build/lib/libnetworkinglib.a
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -static -o $@ $^ $(LDLIBS)
+
+build/include/%.h: $(S)/include/%.h
+	cp $< $@
+
+build/bin/%.sh: $(S)/test/%.sh
+	cp $< $@
+
+check-networking: $(networking-tools)
+	$(EMULATOR) build/bin/test/chksum -i simple
+	$(EMULATOR) build/bin/test/chksum -i scalar
+	$(EMULATOR) build/bin/test/chksum -i simd || true # simd is not always available
+
+install-networking: \
+ $(networking-libs:build/lib/%=$(DESTDIR)$(libdir)/%) \
+ $(networking-includes:build/include/%=$(DESTDIR)$(includedir)/%)
+
+clean-networking:
+	rm -f $(networking-files)
+endif
+
+.PHONY: all-networking check-networking install-networking clean-networking
diff --git a/libc/AOR_v20.02/networking/aarch64/chksum_simd.c b/libc/AOR_v20.02/networking/aarch64/chksum_simd.c
new file mode 100644
index 0000000000000..eaa0f3bc3e170
--- /dev/null
+++ b/libc/AOR_v20.02/networking/aarch64/chksum_simd.c
@@ -0,0 +1,147 @@
+/*
+ * AArch64-specific checksum implementation using NEON
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "networking.h"
+#include "../chksum_common.h"
+
+#ifndef __ARM_NEON
+#pragma GCC target("+simd")
+#endif
+
+#include <arm_neon.h>
+
+always_inline
+static inline uint64_t
+slurp_head64(const void **pptr, uint32_t *nbytes)
+{
+    Assert(*nbytes >= 8);
+    uint64_t sum = 0;
+    uint32_t off = (uintptr_t) *pptr % 8;
+    if (likely(off != 0))
+    {
+	/* Get rid of bytes 0..off-1 */
+	const unsigned char *ptr64 = align_ptr(*pptr, 8);
+	uint64_t mask = ALL_ONES << (CHAR_BIT * off);
+	uint64_t val = load64(ptr64) & mask;
+	/* Fold 64-bit sum to 33 bits */
+	sum = val >> 32;
+	sum += (uint32_t) val;
+	*pptr = ptr64 + 8;
+	*nbytes -= 8 - off;
+    }
+    return sum;
+}
+
+always_inline
+static inline uint64_t
+slurp_tail64(uint64_t sum, const void *ptr, uint32_t nbytes)
+{
+    Assert(nbytes < 8);
+    if (likely(nbytes != 0))
+    {
+	/* Get rid of bytes 7..nbytes */
+	uint64_t mask = ALL_ONES >> (CHAR_BIT * (8 - nbytes));
+	Assert(__builtin_popcountl(mask) / CHAR_BIT == nbytes);
+	uint64_t val = load64(ptr) & mask;
+	sum += val >> 32;
+	sum += (uint32_t) val;
+	nbytes = 0;
+    }
+    Assert(nbytes == 0);
+    return sum;
+}
+
+unsigned short
+__chksum_aarch64_simd(const void *ptr, unsigned int nbytes)
+{
+    bool swap = (uintptr_t) ptr & 1;
+    uint64_t sum;
+
+    if (unlikely(nbytes < 50))
+    {
+	sum = slurp_small(ptr, nbytes);
+	swap = false;
+	goto fold;
+    }
+
+    /* 8-byte align pointer */
+    Assert(nbytes >= 8);
+    sum = slurp_head64(&ptr, &nbytes);
+    Assert(((uintptr_t) ptr & 7) == 0);
+
+    const uint32_t *may_alias ptr32 = ptr;
+
+    uint64x2_t vsum0 = { 0, 0 };
+    uint64x2_t vsum1 = { 0, 0 };
+    uint64x2_t vsum2 = { 0, 0 };
+    uint64x2_t vsum3 = { 0, 0 };
+
+    /* Sum groups of 64 bytes */
+    for (uint32_t i = 0; i < nbytes / 64; i++)
+    {
+	uint32x4_t vtmp0 = vld1q_u32(ptr32);
+	uint32x4_t vtmp1 = vld1q_u32(ptr32 + 4);
+	uint32x4_t vtmp2 = vld1q_u32(ptr32 + 8);
+	uint32x4_t vtmp3 = vld1q_u32(ptr32 + 12);
+	vsum0 = vpadalq_u32(vsum0, vtmp0);
+	vsum1 = vpadalq_u32(vsum1, vtmp1);
+	vsum2 = vpadalq_u32(vsum2, vtmp2);
+	vsum3 = vpadalq_u32(vsum3, vtmp3);
+	ptr32 += 16;
+    }
+    nbytes %= 64;
+
+    /* Fold vsum2 and vsum3 into vsum0 and vsum1 */
+    vsum0 = vpadalq_u32(vsum0, vreinterpretq_u32_u64(vsum2));
+    vsum1 = vpadalq_u32(vsum1, vreinterpretq_u32_u64(vsum3));
+
+    /* Add any trailing group of 32 bytes */
+    if (nbytes & 32)
+    {
+	uint32x4_t vtmp0 = vld1q_u32(ptr32);
+	uint32x4_t vtmp1 = vld1q_u32(ptr32 + 4);
+	vsum0 = vpadalq_u32(vsum0, vtmp0);
+	vsum1 = vpadalq_u32(vsum1, vtmp1);
+	ptr32 += 8;
+	nbytes -= 32;
+    }
+    Assert(nbytes < 32);
+
+    /* Fold vsum1 into vsum0 */
+    vsum0 = vpadalq_u32(vsum0, vreinterpretq_u32_u64(vsum1));
+
+    /* Add any trailing group of 16 bytes */
+    if (nbytes & 16)
+    {
+	uint32x4_t vtmp = vld1q_u32(ptr32);
+	vsum0 = vpadalq_u32(vsum0, vtmp);
+	ptr32 += 4;
+	nbytes -= 16;
+    }
+    Assert(nbytes < 16);
+
+    /* Add any trailing group of 8 bytes */
+    if (nbytes & 8)
+    {
+	uint32x2_t vtmp = vld1_u32(ptr32);
+	vsum0 = vaddw_u32(vsum0, vtmp);
+	ptr32 += 2;
+	nbytes -= 8;
+    }
+    Assert(nbytes < 8);
+
+    uint64_t val = vaddlvq_u32(vreinterpretq_u32_u64(vsum0));
+    sum += val >> 32;
+    sum += (uint32_t) val;
+
+    /* Handle any trailing 0..7 bytes */
+    sum = slurp_tail64(sum, ptr32, nbytes);
+
+fold:
+    return fold_and_swap(sum, swap);
+}
diff --git a/libc/AOR_v20.02/networking/arm/chksum_simd.c b/libc/AOR_v20.02/networking/arm/chksum_simd.c
new file mode 100644
index 0000000000000..aa70a3c81e18e
--- /dev/null
+++ b/libc/AOR_v20.02/networking/arm/chksum_simd.c
@@ -0,0 +1,150 @@
+/*
+ * Armv7-A specific checksum implementation using NEON
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "networking.h"
+#include "../chksum_common.h"
+
+#ifndef __ARM_NEON
+#pragma GCC target("+simd")
+#endif
+
+#include <arm_neon.h>
+
+unsigned short
+__chksum_arm_simd(const void *ptr, unsigned int nbytes)
+{
+    bool swap = (uintptr_t) ptr & 1;
+    uint64x1_t vsum = { 0 };
+
+    if (unlikely(nbytes < 40))
+    {
+	uint64_t sum = slurp_small(ptr, nbytes);
+	return fold_and_swap(sum, false);
+    }
+
+    /* 8-byte align pointer */
+    /* Inline slurp_head-like code since we use NEON here */
+    Assert(nbytes >= 8);
+    uint32_t off = (uintptr_t) ptr & 7;
+    if (likely(off != 0))
+    {
+	const uint64_t *may_alias ptr64 = align_ptr(ptr, 8);
+	uint64x1_t vword64 = vld1_u64(ptr64);
+	/* Get rid of bytes 0..off-1 */
+	uint64x1_t vmask = vdup_n_u64(ALL_ONES);
+	int64x1_t vshiftl = vdup_n_s64(CHAR_BIT * off);
+	vmask = vshl_u64(vmask, vshiftl);
+	vword64 = vand_u64(vword64, vmask);
+	uint32x2_t vtmp = vreinterpret_u32_u64(vword64);
+	/* Set accumulator */
+	vsum = vpaddl_u32(vtmp);
+	/* Update pointer and remaining size */
+	ptr = (char *) ptr64 + 8;
+	nbytes -= 8 - off;
+    }
+    Assert(((uintptr_t) ptr & 7) == 0);
+
+    /* Sum groups of 64 bytes */
+    uint64x2_t vsum0 = { 0, 0 };
+    uint64x2_t vsum1 = { 0, 0 };
+    uint64x2_t vsum2 = { 0, 0 };
+    uint64x2_t vsum3 = { 0, 0 };
+    const uint32_t *may_alias ptr32 = ptr;
+    for (uint32_t i = 0; i < nbytes / 64; i++)
+    {
+	uint32x4_t vtmp0 = vld1q_u32(ptr32);
+	uint32x4_t vtmp1 = vld1q_u32(ptr32 + 4);
+	uint32x4_t vtmp2 = vld1q_u32(ptr32 + 8);
+	uint32x4_t vtmp3 = vld1q_u32(ptr32 + 12);
+	vsum0 = vpadalq_u32(vsum0, vtmp0);
+	vsum1 = vpadalq_u32(vsum1, vtmp1);
+	vsum2 = vpadalq_u32(vsum2, vtmp2);
+	vsum3 = vpadalq_u32(vsum3, vtmp3);
+	ptr32 += 16;
+    }
+    nbytes %= 64;
+
+    /* Fold vsum1/vsum2/vsum3 into vsum0 */
+    vsum0 = vpadalq_u32(vsum0, vreinterpretq_u32_u64(vsum2));
+    vsum1 = vpadalq_u32(vsum1, vreinterpretq_u32_u64(vsum3));
+    vsum0 = vpadalq_u32(vsum0, vreinterpretq_u32_u64(vsum1));
+
+    /* Add any trailing 16-byte groups */
+    while (likely(nbytes >= 16))
+    {
+	uint32x4_t vtmp0 = vld1q_u32(ptr32);
+	vsum0 = vpadalq_u32(vsum0, vtmp0);
+	ptr32 += 4;
+	nbytes -= 16;
+    }
+    Assert(nbytes < 16);
+
+    /* Fold vsum0 into vsum */
+    {
+	/* 4xu32 (4x32b) -> 2xu64 (2x33b) */
+	vsum0 = vpaddlq_u32(vreinterpretq_u32_u64(vsum0));
+	/* 4xu32 (2x(1b+32b)) -> 2xu64 (2x(0b+32b)) */
+	vsum0 = vpaddlq_u32(vreinterpretq_u32_u64(vsum0));
+	/* 4xu32 (4x32b) -> 2xu64 (2x33b) */
+	Assert((vgetq_lane_u64(vsum0, 0) >> 32) == 0);
+	Assert((vgetq_lane_u64(vsum0, 1) >> 32) == 0);
+	uint32x2_t vtmp = vmovn_u64(vsum0);
+	/* Add to accumulator */
+	vsum = vpadal_u32(vsum, vtmp);
+    }
+
+    /* Add any trailing group of 8 bytes */
+    if (nbytes & 8)
+    {
+	uint32x2_t vtmp = vld1_u32(ptr32);
+	/* Add to accumulator */
+	vsum = vpadal_u32(vsum, vtmp);
+	ptr32 += 2;
+	nbytes -= 8;
+    }
+    Assert(nbytes < 8);
+
+    /* Handle any trailing 1..7 bytes */
+    if (likely(nbytes != 0))
+    {
+	Assert(((uintptr_t) ptr32 & 7) == 0);
+	Assert(nbytes < 8);
+	uint64x1_t vword64 = vld1_u64((const uint64_t *) ptr32);
+	/* Get rid of bytes 7..nbytes */
+	uint64x1_t vmask = vdup_n_u64(ALL_ONES);
+	int64x1_t vshiftr = vdup_n_s64(-CHAR_BIT * (8 - nbytes));
+	vmask = vshl_u64(vmask, vshiftr);/* Shift right */
+	vword64 = vand_u64(vword64, vmask);
+	/* Fold 64-bit sum to 33 bits */
+	vword64 = vpaddl_u32(vreinterpret_u32_u64(vword64));
+	/* Add to accumulator */
+	vsum = vpadal_u32(vsum, vreinterpret_u32_u64(vword64));
+    }
+
+    /* Fold 64-bit vsum to 32 bits */
+    vsum = vpaddl_u32(vreinterpret_u32_u64(vsum));
+    vsum = vpaddl_u32(vreinterpret_u32_u64(vsum));
+    Assert(vget_lane_u32(vreinterpret_u32_u64(vsum), 1) == 0);
+
+    /* Fold 32-bit vsum to 16 bits */
+    uint32x2_t vsum32 = vreinterpret_u32_u64(vsum);
+    vsum32 = vpaddl_u16(vreinterpret_u16_u32(vsum32));
+    vsum32 = vpaddl_u16(vreinterpret_u16_u32(vsum32));
+    Assert(vget_lane_u16(vreinterpret_u16_u32(vsum32), 1) == 0);
+    Assert(vget_lane_u16(vreinterpret_u16_u32(vsum32), 2) == 0);
+    Assert(vget_lane_u16(vreinterpret_u16_u32(vsum32), 3) == 0);
+
+    /* Convert to 16-bit scalar */
+    uint16_t sum = vget_lane_u16(vreinterpret_u16_u32(vsum32), 0);
+
+    if (unlikely(swap))/* Odd base pointer is unexpected */
+    {
+	sum = bswap16(sum);
+    }
+    return sum;
+}
diff --git a/libc/AOR_v20.02/networking/chksum.c b/libc/AOR_v20.02/networking/chksum.c
new file mode 100644
index 0000000000000..5f9033402cd5f
--- /dev/null
+++ b/libc/AOR_v20.02/networking/chksum.c
@@ -0,0 +1,82 @@
+/*
+ * Compute 16-bit sum in ones' complement arithmetic (with end-around carry).
+ * This sum is often used as a simple checksum in networking.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "networking.h"
+#include "chksum_common.h"
+
+always_inline
+static inline uint32_t
+slurp_head32(const void **pptr, uint32_t *nbytes)
+{
+    uint32_t sum = 0;
+    Assert(*nbytes >= 4);
+    uint32_t off = (uintptr_t) *pptr % 4;
+    if (likely(off != 0))
+    {
+	/* Get rid of bytes 0..off-1 */
+	const unsigned char *ptr32 = align_ptr(*pptr, 4);
+	uint32_t mask = ~0U << (CHAR_BIT * off);
+	sum = load32(ptr32) & mask;
+	*pptr = ptr32 + 4;
+	*nbytes -= 4 - off;
+    }
+    return sum;
+}
+
+/* Additional loop unrolling would help when not auto-vectorizing */
+unsigned short
+__chksum(const void *ptr, unsigned int nbytes)
+{
+    bool swap = false;
+    uint64_t sum = 0;
+
+    if (nbytes > 300)
+    {
+	/* 4-byte align pointer */
+	swap = (uintptr_t) ptr & 1;
+	sum = slurp_head32(&ptr, &nbytes);
+    }
+    /* Else benefit of aligning not worth the overhead */
+
+    /* Sum all 16-byte chunks */
+    const char *cptr = ptr;
+    for (uint32_t nquads = nbytes / 16; nquads != 0; nquads--)
+    {
+	uint64_t h0 = load32(cptr + 0);
+	uint64_t h1 = load32(cptr + 4);
+	uint64_t h2 = load32(cptr + 8);
+	uint64_t h3 = load32(cptr + 12);
+	sum += h0 + h1 + h2 + h3;
+	cptr += 16;
+    }
+    nbytes %= 16;
+    Assert(nbytes < 16);
+
+    /* Handle any trailing 4-byte chunks */
+    while (nbytes >= 4)
+    {
+	sum += load32(cptr);
+	cptr += 4;
+	nbytes -= 4;
+    }
+    Assert(nbytes < 4);
+
+    if (nbytes & 2)
+    {
+	sum += load16(cptr);
+	cptr += 2;
+    }
+
+    if (nbytes & 1)
+    {
+	sum += *(uint8_t *)cptr;
+    }
+
+    return fold_and_swap(sum, swap);
+}
diff --git a/libc/AOR_v20.02/networking/chksum_common.h b/libc/AOR_v20.02/networking/chksum_common.h
new file mode 100644
index 0000000000000..afb0552830f04
--- /dev/null
+++ b/libc/AOR_v20.02/networking/chksum_common.h
@@ -0,0 +1,133 @@
+/*
+ * Common code for checksum implementations
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef CHKSUM_COMMON_H
+#define CHKSUM_COMMON_H
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+#error Only little endian supported
+#endif
+
+#include <limits.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+/* Assertions must be explicitly enabled */
+#if WANT_ASSERT
+#undef NDEBUG
+#include <assert.h>
+#define Assert(exp) assert(exp)
+#else
+#define Assert(exp) (void) (exp)
+#endif
+
+#ifdef __GNUC__
+#define likely(x)     __builtin_expect(!!(x), 1)
+#define unlikely(x)   __builtin_expect(!!(x), 0)
+#define may_alias     __attribute__((__may_alias__))
+#define always_inline __attribute__((always_inline))
+#ifdef __clang__
+#define no_unroll_loops
+#else
+#define no_unroll_loops  __attribute__((optimize("no-unroll-loops")))
+#endif
+#define bswap16(x)    __builtin_bswap16((x))
+#else
+#define likely(x)     (x)
+#define unlikely(x)   (x)
+#define may_alias
+#define always_inline
+#define no_unroll_loops
+#define bswap16(x)    ((uint8_t)((x) >> 8) | ((uint8_t)(x) << 8))
+#endif
+
+#define ALL_ONES ~UINT64_C(0)
+
+static inline
+uint64_t load64(const void *ptr)
+{
+    /* GCC will optimise this to a normal load instruction */
+    uint64_t v;
+    memcpy(&v, ptr, sizeof v);
+    return v;
+}
+
+static inline
+uint32_t load32(const void *ptr)
+{
+    /* GCC will optimise this to a normal load instruction */
+    uint32_t v;
+    memcpy(&v, ptr, sizeof v);
+    return v;
+}
+
+static inline
+uint16_t load16(const void *ptr)
+{
+    /* GCC will optimise this to a normal load instruction */
+    uint16_t v;
+    memcpy(&v, ptr, sizeof v);
+    return v;
+}
+
+/* slurp_small() is for small buffers, don't waste cycles on alignment */
+no_unroll_loops
+always_inline
+static inline uint64_t
+slurp_small(const void *ptr, uint32_t nbytes)
+{
+    const unsigned char *cptr = ptr;
+    uint64_t sum = 0;
+    while (nbytes >= 4)
+    {
+	sum += load32(cptr);
+	cptr += 4;
+	nbytes -= 4;
+    }
+    if (nbytes & 2)
+    {
+	sum += load16(cptr);
+	cptr += 2;
+    }
+    if (nbytes & 1)
+    {
+	sum += (uint8_t) *cptr;
+    }
+    return sum;
+}
+
+static inline const void *
+align_ptr(const void *ptr, size_t bytes)
+{
+    return (void *) ((uintptr_t) ptr & -(uintptr_t) bytes);
+}
+
+always_inline
+static inline uint16_t
+fold_and_swap(uint64_t sum, bool swap)
+{
+    /* Fold 64-bit sum to 32 bits */
+    sum = (sum & 0xffffffff) + (sum >> 32);
+    sum = (sum & 0xffffffff) + (sum >> 32);
+    Assert(sum == (uint32_t) sum);
+
+    /* Fold 32-bit sum to 16 bits */
+    sum = (sum & 0xffff) + (sum >> 16);
+    sum = (sum & 0xffff) + (sum >> 16);
+    Assert(sum == (uint16_t) sum);
+
+    if (unlikely(swap)) /* Odd base pointer is unexpected */
+    {
+	sum = bswap16(sum);
+    }
+
+    return (uint16_t) sum;
+}
+
+#endif
diff --git a/libc/AOR_v20.02/networking/include/networking.h b/libc/AOR_v20.02/networking/include/networking.h
new file mode 100644
index 0000000000000..2f91a9efb883c
--- /dev/null
+++ b/libc/AOR_v20.02/networking/include/networking.h
@@ -0,0 +1,15 @@
+/*
+ * Public API.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+unsigned short __chksum (const void *, unsigned int);
+#if __aarch64__ && __ARM_NEON
+unsigned short __chksum_aarch64_simd (const void *, unsigned int);
+#endif
+#if __arm__ && __ARM_NEON
+unsigned short __chksum_arm_simd (const void *, unsigned int);
+#endif
diff --git a/libc/AOR_v20.02/networking/test/chksum.c b/libc/AOR_v20.02/networking/test/chksum.c
new file mode 100644
index 0000000000000..c4ac3fe6bf009
--- /dev/null
+++ b/libc/AOR_v20.02/networking/test/chksum.c
@@ -0,0 +1,382 @@
+/*
+ * Ones' complement checksum test & benchmark
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define _GNU_SOURCE
+#include <inttypes.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <time.h>
+#include <unistd.h>
+#include "../include/networking.h"
+
+#if WANT_ASSERT
+#undef NDEBUG
+#include <assert.h>
+#define Assert(exp) assert(exp)
+#else
+#define Assert(exp) (void) (exp)
+#endif
+
+#ifdef __GNUC__
+#define may_alias __attribute__((__may_alias__))
+#else
+#define may_alias
+#endif
+
+#define CACHE_LINE 64
+#define ALIGN(x, y) (((x) + (y) - 1) & ~((y) - 1))
+
+/* Reference implementation - do not modify! */
+static uint16_t
+checksum_simple(const void *ptr, uint32_t nbytes)
+{
+    const uint16_t *may_alias hptr = ptr;
+    uint64_t sum = 0;/* Need 64-bit accumulator when nbytes > 64K */
+
+    /* Sum all halfwords, assume misaligned accesses are handled in HW */
+    for (uint32_t nhalfs = nbytes >> 1; nhalfs != 0; nhalfs--)
+    {
+	sum += *hptr++;
+    }
+
+    /* Add any trailing odd byte */
+    if ((nbytes & 0x01) != 0)
+    {
+	sum += *(uint8_t *) hptr;
+    }
+
+    /* Fold 64-bit sum to 32 bits */
+    sum = (sum & 0xffffffff) + (sum >> 32);
+    sum = (sum & 0xffffffff) + (sum >> 32);
+    Assert(sum == (uint32_t) sum);
+
+    /* Fold 32-bit sum to 16 bits */
+    sum = (sum & 0xffff) + (sum >> 16);
+    sum = (sum & 0xffff) + (sum >> 16);
+    Assert(sum == (uint16_t) sum);
+
+    return (uint16_t) sum;
+}
+
+static struct
+{
+    uint16_t (*cksum_fp)(const void *, uint32_t);
+    const char *name;
+} implementations[] =
+{
+    { checksum_simple, "simple"},
+    { __chksum, "scalar"},
+#if __arm__
+    { __chksum_arm_simd, "simd" },
+#elif __aarch64__
+    { __chksum_aarch64_simd, "simd" },
+#endif
+    { NULL, NULL}
+};
+
+static int
+find_impl(const char *name)
+{
+    for (int i = 0; implementations[i].name != NULL; i++)
+    {
+	if (strcmp(implementations[i].name, name) == 0)
+	{
+	    return i;
+	}
+    }
+    return -1;
+}
+
+static uint16_t (*CKSUM_FP)(const void *, uint32_t);
+static volatile uint16_t SINK;
+
+static bool
+verify(const void *data, uint32_t offset, uint32_t size)
+{
+
+    uint16_t csum_expected = checksum_simple(data, size);
+    uint16_t csum_actual = CKSUM_FP(data, size);
+    if (csum_actual != csum_expected)
+    {
+	fprintf(stderr, "\nInvalid checksum for offset %u size %u: "
+		"actual %04x expected %04x (valid)",
+		offset, size, csum_actual, csum_expected);
+	if (size < 65536)
+	{
+	    /* Fatal error */
+	    exit(EXIT_FAILURE);
+	}
+	/* Else some implementations only support sizes up to 2^16 */
+	return false;
+    }
+    return true;
+}
+
+static uint64_t
+clock_get_ns(void)
+{
+    struct timespec ts;
+    clock_gettime(CLOCK_MONOTONIC, &ts);
+    return ts.tv_sec * (uint64_t) 1000000000 + ts.tv_nsec;
+}
+
+static void
+benchmark(const uint8_t *base,
+	  size_t poolsize,
+	  uint32_t blksize,
+	  uint32_t numops,
+	  uint64_t cpufreq)
+{
+    printf("%11u ", (unsigned int) blksize); fflush(stdout);
+
+    uint64_t start = clock_get_ns();
+    for (uint32_t i = 0; i < numops; i ++)
+    {
+	/* Read a random value from the pool */
+	uint32_t random = ((uint32_t *) base)[i % (poolsize / 4)];
+	/* Generate a random starting address */
+	const void *data = &base[random % (poolsize - blksize)];
+	SINK = CKSUM_FP(data, blksize);
+    }
+    uint64_t end = clock_get_ns();
+
+#define MEGABYTE 1000000 /* Decimal megabyte (MB) */
+    uint64_t elapsed_ns = end - start;
+    uint64_t elapsed_ms = elapsed_ns / 1000000;
+    uint32_t blks_per_s = (uint32_t) ((numops / elapsed_ms) * 1000);
+    uint64_t accbytes = (uint64_t) numops * blksize;
+    printf("%11ju ", (uintmax_t) ((accbytes / elapsed_ms) * 1000) / MEGABYTE);
+    unsigned int cyc_per_blk = cpufreq / blks_per_s;
+    printf("%11u ", cyc_per_blk);
+    if (blksize != 0)
+    {
+	unsigned int cyc_per_byte = 1000 * cyc_per_blk / blksize;
+	printf("%7u.%03u ",
+		cyc_per_byte / 1000, cyc_per_byte % 1000);
+    }
+    printf("\n");
+}
+
+int main(int argc, char *argv[])
+{
+    int c;
+    bool DUMP = false;
+    uint32_t IMPL = 0;/* Simple implementation */
+    uint64_t CPUFREQ = 0;
+    uint32_t BLKSIZE = 0;
+    uint32_t NUMOPS = 1000000;
+    uint32_t POOLSIZE = 512 * 1024;/* Typical ARM L2 cache size */
+
+    setvbuf(stdout, NULL, _IOLBF, 160);
+    while ((c = getopt(argc, argv, "b:df:i:n:p:")) != -1)
+    {
+	switch (c)
+	{
+	    case 'b' :
+		{
+		    int blksize = atoi(optarg);
+		    if (blksize < 1 || blksize > POOLSIZE / 2)
+		    {
+			fprintf(stderr, "Invalid block size %d\n", blksize);
+			exit(EXIT_FAILURE);
+		    }
+		    BLKSIZE = (unsigned) blksize;
+		    break;
+		}
+	    case 'd' :
+		DUMP = true;
+		break;
+	    case 'f' :
+		{
+		    int64_t cpufreq = atoll(optarg);
+		    if (cpufreq < 1)
+		    {
+			fprintf(stderr, "Invalid CPU frequency %"PRId64"\n",
+				cpufreq);
+			exit(EXIT_FAILURE);
+		    }
+		    CPUFREQ = cpufreq;
+		    break;
+		}
+	    case 'i' :
+		{
+		    int impl = find_impl(optarg);
+		    if (impl < 0)
+		    {
+			fprintf(stderr, "Invalid implementation %s\n", optarg);
+			goto usage;
+		    }
+		    IMPL = (unsigned) impl;
+		    break;
+		}
+	    case 'n' :
+		{
+		    int numops = atoi(optarg);
+		    if (numops < 1)
+		    {
+			fprintf(stderr, "Invalid number of operations %d\n", numops);
+			exit(EXIT_FAILURE);
+		    }
+		    NUMOPS = (unsigned) numops;
+		    break;
+		}
+	    case 'p' :
+		{
+		    int poolsize = atoi(optarg);
+		    if (poolsize < 4096)
+		    {
+			fprintf(stderr, "Invalid pool size %d\n", poolsize);
+			exit(EXIT_FAILURE);
+		    }
+		    char c = optarg[strlen(optarg) - 1];
+		    if (c == 'M')
+		    {
+			POOLSIZE = (unsigned) poolsize * 1024 * 1024;
+		    }
+		    else if (c == 'K')
+		    {
+			POOLSIZE = (unsigned) poolsize * 1024;
+		    }
+		    else
+		    {
+			POOLSIZE = (unsigned) poolsize;
+		    }
+		    break;
+		}
+	    default :
+usage :
+		fprintf(stderr, "Usage: checksum <options>\n"
+			"-b <blksize>    Block size\n"
+			"-d              Dump first 96 bytes of data\n"
+			"-f <cpufreq>    CPU frequency (Hz)\n"
+			"-i <impl>       Implementation\n"
+			"-n <numops>     Number of operations\n"
+			"-p <poolsize>   Pool size (K or M suffix)\n"
+		       );
+		printf("Implementations:");
+		for (int i = 0; implementations[i].name != NULL; i++)
+		{
+		    printf(" %s", implementations[i].name);
+		}
+		printf("\n");
+		exit(EXIT_FAILURE);
+	}
+    }
+    if (optind > argc)
+    {
+	goto usage;
+    }
+
+    CKSUM_FP = implementations[IMPL].cksum_fp;
+    POOLSIZE = ALIGN(POOLSIZE, CACHE_LINE);
+    uint8_t *base = mmap(0, POOLSIZE, PROT_READ|PROT_WRITE,
+			MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
+    if (base == MAP_FAILED)
+    {
+	perror("aligned_alloc"), exit(EXIT_FAILURE);
+    }
+    for (size_t i = 0; i < POOLSIZE / 4; i++)
+    {
+	((uint32_t *) base)[i] = rand();
+    }
+
+    printf("Implementation: %s\n", implementations[IMPL].name);
+    printf("numops %u, poolsize ", NUMOPS);
+    if (POOLSIZE % (1024 * 1024) == 0)
+    {
+	printf("%uMiB", POOLSIZE / (1024 * 1024));
+    }
+    else if (POOLSIZE % 1024 == 0)
+    {
+	printf("%uKiB", POOLSIZE / 1024);
+    }
+    else
+    {
+	printf("%uB", POOLSIZE);
+    }
+    printf(", blocksize %u, CPU frequency %juMHz\n",
+	   BLKSIZE, (uintmax_t) (CPUFREQ / 1000000));
+#if WANT_ASSERT
+    printf("Warning: assertions are enabled\n");
+#endif
+
+    if (DUMP)
+    {
+	/* Print out first 96 bytes of data for human debugging */
+	for (int i = 0; i < 96; i++)
+	{
+	    if (i % 8 == 0)
+		printf("%2u:", i);
+	    printf(" %02x", base[i]);
+	    if (i % 8 == 7)
+		printf("\n");
+	}
+    }
+
+    /* Verify that chosen algorithm handles all combinations of offsets and sizes */
+    printf("Verifying..."); fflush(stdout);
+    bool success = true;
+    /* Check all (relevant) combinations of size and offset */
+    for (int size = 0; size <= 256; size++)
+    {
+	for (int offset = 0; offset < 255; offset++)
+	{
+	    /* Check at start of mapped memory */
+	    success &= verify(&base[offset], offset, size);
+	    /* Check at end of mapped memory */
+	    uint8_t *p = base + POOLSIZE - (size + offset);
+	    success &= verify(p, (uintptr_t) p % 64, size);
+	}
+    }
+    /* Check increasingly larger sizes */
+    for (size_t size = 1; size < POOLSIZE; size *= 2)
+    {
+	success &= verify(base, 0, size);
+    }
+    /* Check the full size, this can detect accumulator overflows */
+    success &= verify(base, 0, POOLSIZE);
+    printf("%s\n", success ? "OK" : "failure");
+
+    /* Print throughput in decimal megabyte (1000000B) per second */
+    if (CPUFREQ != 0)
+    {
+	printf("%11s %11s %11s %11s\n",
+	       "block size", "MB/s", "cycles/blk", "cycles/byte");
+    }
+    else
+    {
+	printf("%11s %11s %11s %11s\n",
+	       "block size", "MB/s", "ns/blk", "ns/byte");
+	CPUFREQ = 1000000000;
+    }
+    if (BLKSIZE != 0)
+    {
+	benchmark(base, POOLSIZE, BLKSIZE, NUMOPS, CPUFREQ);
+    }
+    else
+    {
+	static const uint16_t sizes[] =
+	    { 20, 42, 102, 250, 612, 1500, 3674, 9000, 0 };
+	for (int i = 0; sizes[i] != 0; i++)
+	{
+	    uint32_t numops = NUMOPS * 10000 / (40 + sizes[i]);
+	    benchmark(base, POOLSIZE, sizes[i], numops, CPUFREQ);
+	}
+    }
+
+    if (munmap(base, POOLSIZE) != 0)
+    {
+	perror("munmap"), exit(EXIT_FAILURE);
+    }
+
+    return success ? EXIT_SUCCESS : EXIT_FAILURE;
+}
diff --git a/libc/AOR_v20.02/string/Dir.mk b/libc/AOR_v20.02/string/Dir.mk
new file mode 100644
index 0000000000000..215452c8dc386
--- /dev/null
+++ b/libc/AOR_v20.02/string/Dir.mk
@@ -0,0 +1,101 @@
+# Makefile fragment - requires GNU make
+#
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+S := $(srcdir)/string
+B := build/string
+
+ifeq ($(ARCH),)
+all-string check-string install-string clean-string:
+	@echo "*** Please set ARCH in config.mk. ***"
+	@exit 1
+else
+
+string-lib-srcs := $(wildcard $(S)/$(ARCH)/*.[cS])
+string-test-srcs := $(wildcard $(S)/test/*.c)
+
+string-includes := $(patsubst $(S)/%,build/%,$(wildcard $(S)/include/*.h))
+
+string-libs := \
+	build/lib/libstringlib.so \
+	build/lib/libstringlib.a \
+
+string-tools := \
+	build/bin/test/memcpy \
+	build/bin/test/memmove \
+	build/bin/test/memset \
+	build/bin/test/memchr \
+	build/bin/test/memcmp \
+	build/bin/test/strcpy \
+	build/bin/test/stpcpy \
+	build/bin/test/strcmp \
+	build/bin/test/strchr \
+	build/bin/test/strrchr \
+	build/bin/test/strchrnul \
+	build/bin/test/strlen \
+	build/bin/test/strnlen \
+	build/bin/test/strncmp
+
+string-lib-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(string-lib-srcs)))
+string-test-objs := $(patsubst $(S)/%,$(B)/%.o,$(basename $(string-test-srcs)))
+
+string-objs := \
+	$(string-lib-objs) \
+	$(string-lib-objs:%.o=%.os) \
+	$(string-test-objs) \
+
+string-files := \
+	$(string-objs) \
+	$(string-libs) \
+	$(string-tools) \
+	$(string-includes) \
+
+all-string: $(string-libs) $(string-tools) $(string-includes)
+
+$(string-objs): $(string-includes)
+$(string-objs): CFLAGS_ALL += $(string-cflags)
+
+build/lib/libstringlib.so: $(string-lib-objs:%.o=%.os)
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -shared -o $@ $^
+
+build/lib/libstringlib.a: $(string-lib-objs)
+	rm -f $@
+	$(AR) rc $@ $^
+	$(RANLIB) $@
+
+build/bin/test/%: $(B)/test/%.o build/lib/libstringlib.a
+	$(CC) $(CFLAGS_ALL) $(LDFLAGS) -static -o $@ $^ $(LDLIBS)
+
+build/include/%.h: $(S)/include/%.h
+	cp $< $@
+
+build/bin/%.sh: $(S)/test/%.sh
+	cp $< $@
+
+check-string: $(string-tools)
+	$(EMULATOR) build/bin/test/memcpy
+	$(EMULATOR) build/bin/test/memmove
+	$(EMULATOR) build/bin/test/memset
+	$(EMULATOR) build/bin/test/memchr
+	$(EMULATOR) build/bin/test/memcmp
+	$(EMULATOR) build/bin/test/strcpy
+	$(EMULATOR) build/bin/test/stpcpy
+	$(EMULATOR) build/bin/test/strcmp
+	$(EMULATOR) build/bin/test/strchr
+	$(EMULATOR) build/bin/test/strrchr
+	$(EMULATOR) build/bin/test/strchrnul
+	$(EMULATOR) build/bin/test/strlen
+	$(EMULATOR) build/bin/test/strnlen
+	$(EMULATOR) build/bin/test/strncmp
+
+install-string: \
+ $(string-libs:build/lib/%=$(DESTDIR)$(libdir)/%) \
+ $(string-includes:build/include/%=$(DESTDIR)$(includedir)/%)
+
+clean-string:
+	rm -f $(string-files)
+endif
+
+.PHONY: all-string check-string install-string clean-string
diff --git a/libc/AOR_v20.02/string/aarch64/check-arch.S b/libc/AOR_v20.02/string/aarch64/check-arch.S
new file mode 100644
index 0000000000000..7783503b3c667
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/check-arch.S
@@ -0,0 +1,11 @@
+/*
+ * check ARCH setting.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if !__aarch64__
+# error ARCH setting does not match the compiler.
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/memchr-sve.S b/libc/AOR_v20.02/string/aarch64/memchr-sve.S
new file mode 100644
index 0000000000000..d9c5fdd18673d
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memchr-sve.S
@@ -0,0 +1,65 @@
+/*
+ * memchr - find a character in a memory zone
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__memchr_aarch64_sve
+	.type	__memchr_aarch64_sve, %function
+	.p2align 4
+__memchr_aarch64_sve:
+	dup	z1.b, w1			/* duplicate c to a vector */
+	setffr					/* initialize FFR */
+	mov	x3, 0				/* initialize off */
+	nop
+
+0:	whilelo	p1.b, x3, x2			/* make sure off < max */
+	b.none	9f
+
+	/* Read a vector's worth of bytes, bounded by max,
+	   stopping on first fault.  */
+	ldff1b	z0.b, p1/z, [x0, x3]
+	rdffrs	p0.b, p1/z
+	b.nlast	2f
+
+	/* First fault did not fail: the vector bounded by max is valid.
+	   Avoid depending on the contents of FFR beyond the branch.  */
+	incb	x3				/* speculate increment */
+	cmpeq	p2.b, p1/z, z0.b, z1.b		/* search for c */
+	b.none	0b
+	decb	x3				/* undo speculate */
+
+	/* Found C.  */
+1:	brkb	p2.b, p1/z, p2.b	/* find the first c */
+	add	x0, x0, x3		/* form partial pointer */
+	incp	x0, p2.b		/* form final pointer to c */
+	ret
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparision only on the valid bytes.  */
+2:	cmpeq	p2.b, p0/z, z0.b, z1.b
+	b.any	1b
+
+	/* No C found.  Re-init FFR, increment, and loop.  */
+	setffr
+	incp	x3, p0.b
+	b	0b
+
+	/* Found end of count.  */
+9:	mov	x0, 0			/* return null */
+	ret
+
+	.size	__memchr_aarch64_sve, . - __memchr_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/memchr.S b/libc/AOR_v20.02/string/aarch64/memchr.S
new file mode 100644
index 0000000000000..a454d6b896af5
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memchr.S
@@ -0,0 +1,144 @@
+/*
+ * memchr - find a character in a memory zone
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+#define cntin		x2
+
+#define result		x0
+
+#define src		x3
+#define	tmp		x4
+#define wtmp2		w5
+#define synd		x6
+#define soff		x9
+#define cntrem		x10
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_chr1	v3
+#define vhas_chr2	v4
+#define vrepmask	v5
+#define vend		v6
+
+/*
+ * Core algorithm:
+ *
+ * For each 32-byte chunk we calculate a 64-bit syndrome value, with two bits
+ * per byte. For each tuple, bit 0 is set if the relevant byte matched the
+ * requested character and bit 1 is not used (faster than using a 32bit
+ * syndrome). Since the bits in the syndrome reflect exactly the order in which
+ * things occur in the original string, counting trailing zeros allows to
+ * identify exactly which byte has matched.
+ */
+
+ENTRY (__memchr_aarch64)
+	/* Do not dereference srcin if no bytes to compare.  */
+	cbz	cntin, L(zero_length)
+	/*
+	 * Magic constant 0x40100401 allows us to identify which lane matches
+	 * the requested byte.
+	 */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	/* Work with aligned 32-byte chunks */
+	bic	src, srcin, #31
+	dup	vrepmask.4s, wtmp2
+	ands	soff, srcin, #31
+	and	cntrem, cntin, #31
+	b.eq	L(loop)
+
+	/*
+	 * Input string is not 32-byte aligned. We calculate the syndrome
+	 * value for the aligned 32 bytes block containing the first bytes
+	 * and mask the irrelevant part.
+	 */
+
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	sub	tmp, soff, #32
+	adds	cntin, cntin, tmp
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	addp	vend.16b, vhas_chr1.16b, vhas_chr2.16b		/* 256->128 */
+	addp	vend.16b, vend.16b, vend.16b			/* 128->64 */
+	mov	synd, vend.d[0]
+	/* Clear the soff*2 lower bits */
+	lsl	tmp, soff, #1
+	lsr	synd, synd, tmp
+	lsl	synd, synd, tmp
+	/* The first block can also be the last */
+	b.ls	L(masklast)
+	/* Have we found something already? */
+	cbnz	synd, L(tail)
+
+L(loop):
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	subs	cntin, cntin, #32
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	/* If we're out of data we finish regardless of the result */
+	b.ls	L(end)
+	/* Use a fast check for the termination condition */
+	orr	vend.16b, vhas_chr1.16b, vhas_chr2.16b
+	addp	vend.2d, vend.2d, vend.2d
+	mov	synd, vend.d[0]
+	/* We're not out of data, loop if we haven't found the character */
+	cbz	synd, L(loop)
+
+L(end):
+	/* Termination condition found, let's calculate the syndrome value */
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	addp	vend.16b, vhas_chr1.16b, vhas_chr2.16b		/* 256->128 */
+	addp	vend.16b, vend.16b, vend.16b			/* 128->64 */
+	mov	synd, vend.d[0]
+	/* Only do the clear for the last possible block */
+	b.hi	L(tail)
+
+L(masklast):
+	/* Clear the (32 - ((cntrem + soff) % 32)) * 2 upper bits */
+	add	tmp, cntrem, soff
+	and	tmp, tmp, #31
+	sub	tmp, tmp, #32
+	neg	tmp, tmp, lsl #1
+	lsl	synd, synd, tmp
+	lsr	synd, synd, tmp
+
+L(tail):
+	/* Count the trailing zeros using bit reversing */
+	rbit	synd, synd
+	/* Compensate the last post-increment */
+	sub	src, src, #32
+	/* Check that we have found a character */
+	cmp	synd, #0
+	/* And count the leading zeros */
+	clz	synd, synd
+	/* Compute the potential result */
+	add	result, src, synd, lsr #1
+	/* Select result or NULL */
+	csel	result, xzr, result, eq
+	ret
+
+L(zero_length):
+	mov	result, #0
+	ret
+
+END (__memchr_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/memcmp-sve.S b/libc/AOR_v20.02/string/aarch64/memcmp-sve.S
new file mode 100644
index 0000000000000..0a3962f587bfb
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memcmp-sve.S
@@ -0,0 +1,51 @@
+/*
+ * memcmp - compare memory
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__memcmp_aarch64_sve
+	.type	__memcmp_aarch64_sve, %function
+	.p2align 4
+__memcmp_aarch64_sve:
+	mov	x3, 0			/* initialize off */
+
+0:	whilelo	p0.b, x3, x2		/* while off < max */
+	b.none	9f
+
+	ld1b	z0.b, p0/z, [x0, x3]	/* read vectors bounded by max.  */
+	ld1b	z1.b, p0/z, [x1, x3]
+
+	/* Increment for a whole vector, even if we've only read a partial.
+	   This is significantly cheaper than INCP, and since OFF is not
+	   used after the loop it is ok to increment OFF past MAX.  */
+	incb	x3
+
+	cmpne	p1.b, p0/z, z0.b, z1.b	/* while no inequalities */
+	b.none	0b
+
+	/* Found inequality.  */
+1:	brkb	p1.b, p0/z, p1.b	/* find first such */
+	lasta	w0, p1, z0.b		/* extract each byte */
+	lasta	w1, p1, z1.b
+	sub	x0, x0, x1		/* return comparison */
+	ret
+
+	/* Found end-of-count.  */
+9:	mov	x0, 0			/* return equality */
+	ret
+
+	.size	__memcmp_aarch64_sve, . - __memcmp_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/memcmp.S b/libc/AOR_v20.02/string/aarch64/memcmp.S
new file mode 100644
index 0000000000000..fab69b5320eeb
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memcmp.S
@@ -0,0 +1,134 @@
+/* memcmp - compare memory
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses.
+ */
+
+#include "../asmdefs.h"
+
+/* Parameters and result.  */
+#define src1		x0
+#define src2		x1
+#define limit		x2
+#define result		w0
+
+/* Internal variables.  */
+#define data1		x3
+#define data1w		w3
+#define data1h		x4
+#define data2		x5
+#define data2w		w5
+#define data2h		x6
+#define tmp1		x7
+#define tmp2		x8
+
+ENTRY (__memcmp_aarch64)
+	subs	limit, limit, 8
+	b.lo	L(less8)
+
+	ldr	data1, [src1], 8
+	ldr	data2, [src2], 8
+	cmp	data1, data2
+	b.ne	L(return)
+
+	subs	limit, limit, 8
+	b.gt	L(more16)
+
+	ldr	data1, [src1, limit]
+	ldr	data2, [src2, limit]
+	b	L(return)
+
+L(more16):
+	ldr	data1, [src1], 8
+	ldr	data2, [src2], 8
+	cmp	data1, data2
+	bne	L(return)
+
+	/* Jump directly to comparing the last 16 bytes for 32 byte (or less)
+	   strings.  */
+	subs	limit, limit, 16
+	b.ls	L(last_bytes)
+
+	/* We overlap loads between 0-32 bytes at either side of SRC1 when we
+	   try to align, so limit it only to strings larger than 128 bytes.  */
+	cmp	limit, 96
+	b.ls	L(loop16)
+
+	/* Align src1 and adjust src2 with bytes not yet done.  */
+	and	tmp1, src1, 15
+	add	limit, limit, tmp1
+	sub	src1, src1, tmp1
+	sub	src2, src2, tmp1
+
+	/* Loop performing 16 bytes per iteration using aligned src1.
+	   Limit is pre-decremented by 16 and must be larger than zero.
+	   Exit if <= 16 bytes left to do or if the data is not equal.  */
+	.p2align 4
+L(loop16):
+	ldp	data1, data1h, [src1], 16
+	ldp	data2, data2h, [src2], 16
+	subs	limit, limit, 16
+	ccmp	data1, data2, 0, hi
+	ccmp	data1h, data2h, 0, eq
+	b.eq	L(loop16)
+
+	cmp	data1, data2
+	bne	L(return)
+	mov	data1, data1h
+	mov	data2, data2h
+	cmp	data1, data2
+	bne	L(return)
+
+	/* Compare last 1-16 bytes using unaligned access.  */
+L(last_bytes):
+	add	src1, src1, limit
+	add	src2, src2, limit
+	ldp	data1, data1h, [src1]
+	ldp	data2, data2h, [src2]
+	cmp     data1, data2
+	bne	L(return)
+	mov	data1, data1h
+	mov	data2, data2h
+	cmp	data1, data2
+
+	/* Compare data bytes and set return value to 0, -1 or 1.  */
+L(return):
+#ifndef __AARCH64EB__
+	rev	data1, data1
+	rev	data2, data2
+#endif
+	cmp     data1, data2
+L(ret_eq):
+	cset	result, ne
+	cneg	result, result, lo
+	ret
+
+	.p2align 4
+	/* Compare up to 8 bytes.  Limit is [-8..-1].  */
+L(less8):
+	adds	limit, limit, 4
+	b.lo	L(less4)
+	ldr	data1w, [src1], 4
+	ldr	data2w, [src2], 4
+	cmp	data1w, data2w
+	b.ne	L(return)
+	sub	limit, limit, 4
+L(less4):
+	adds	limit, limit, 4
+	beq	L(ret_eq)
+L(byte_loop):
+	ldrb	data1w, [src1], 1
+	ldrb	data2w, [src2], 1
+	subs	limit, limit, 1
+	ccmp	data1w, data2w, 0, ne	/* NZCV = 0b0000.  */
+	b.eq	L(byte_loop)
+	sub	result, data1w, data2w
+	ret
+
+END (__memcmp_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/memcpy-advsimd.S b/libc/AOR_v20.02/string/aarch64/memcpy-advsimd.S
new file mode 100644
index 0000000000000..befd32bb98c72
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memcpy-advsimd.S
@@ -0,0 +1,202 @@
+/*
+ * memcpy - copy memory area
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
+ *
+ */
+
+#include "../asmdefs.h"
+
+#define dstin	x0
+#define src	x1
+#define count	x2
+#define dst	x3
+#define srcend	x4
+#define dstend	x5
+#define A_l	x6
+#define A_lw	w6
+#define A_h	x7
+#define B_l	x8
+#define B_lw	w8
+#define B_h	x9
+#define C_lw	w10
+#define tmp1	x14
+
+#define A_q	q0
+#define B_q	q1
+#define C_q	q2
+#define D_q	q3
+#define E_q	q4
+#define F_q	q5
+#define G_q	q6
+#define H_q	q7
+
+/* This implementation handles overlaps and supports both memcpy and memmove
+   from a single entry point.  It uses unaligned accesses and branchless
+   sequences to keep the code small, simple and improve performance.
+
+   Copies are split into 3 main cases: small copies of up to 32 bytes, medium
+   copies of up to 128 bytes, and large copies.  The overhead of the overlap
+   check is negligible since it is only required for large copies.
+
+   Large copies use a software pipelined loop processing 64 bytes per iteration.
+   The source pointer is 16-byte aligned to minimize unaligned accesses.
+   The loop tail is handled by always copying 64 bytes from the end.
+*/
+
+ENTRY (__memcpy_aarch64_simd)
+ENTRY_ALIAS (__memmove_aarch64_simd)
+	add	srcend, src, count
+	add	dstend, dstin, count
+	cmp	count, 128
+	b.hi	L(copy_long)
+	cmp	count, 32
+	b.hi	L(copy32_128)
+
+	/* Small copies: 0..32 bytes.  */
+	cmp	count, 16
+	b.lo	L(copy16)
+	ldr	A_q, [src]
+	ldr	B_q, [srcend, -16]
+	str	A_q, [dstin]
+	str	B_q, [dstend, -16]
+	ret
+
+	/* Copy 8-15 bytes.  */
+L(copy16):
+	tbz	count, 3, L(copy8)
+	ldr	A_l, [src]
+	ldr	A_h, [srcend, -8]
+	str	A_l, [dstin]
+	str	A_h, [dstend, -8]
+	ret
+
+	.p2align 3
+	/* Copy 4-7 bytes.  */
+L(copy8):
+	tbz	count, 2, L(copy4)
+	ldr	A_lw, [src]
+	ldr	B_lw, [srcend, -4]
+	str	A_lw, [dstin]
+	str	B_lw, [dstend, -4]
+	ret
+
+	/* Copy 0..3 bytes using a branchless sequence.  */
+L(copy4):
+	cbz	count, L(copy0)
+	lsr	tmp1, count, 1
+	ldrb	A_lw, [src]
+	ldrb	C_lw, [srcend, -1]
+	ldrb	B_lw, [src, tmp1]
+	strb	A_lw, [dstin]
+	strb	B_lw, [dstin, tmp1]
+	strb	C_lw, [dstend, -1]
+L(copy0):
+	ret
+
+	.p2align 4
+	/* Medium copies: 33..128 bytes.  */
+L(copy32_128):
+	ldp	A_q, B_q, [src]
+	ldp	C_q, D_q, [srcend, -32]
+	cmp	count, 64
+	b.hi	L(copy128)
+	stp	A_q, B_q, [dstin]
+	stp	C_q, D_q, [dstend, -32]
+	ret
+
+	.p2align 4
+	/* Copy 65..128 bytes.  */
+L(copy128):
+	ldp	E_q, F_q, [src, 32]
+	cmp	count, 96
+	b.ls	L(copy96)
+	ldp	G_q, H_q, [srcend, -64]
+	stp	G_q, H_q, [dstend, -64]
+L(copy96):
+	stp	A_q, B_q, [dstin]
+	stp	E_q, F_q, [dstin, 32]
+	stp	C_q, D_q, [dstend, -32]
+	ret
+
+	/* Copy more than 128 bytes.  */
+L(copy_long):
+	/* Use backwards copy if there is an overlap.  */
+	sub	tmp1, dstin, src
+	cmp	tmp1, count
+	b.lo	L(copy_long_backwards)
+
+	/* Copy 16 bytes and then align src to 16-byte alignment.  */
+	ldr	D_q, [src]
+	and	tmp1, src, 15
+	bic	src, src, 15
+	sub	dst, dstin, tmp1
+	add	count, count, tmp1	/* Count is now 16 too large.  */
+	ldp	A_q, B_q, [src, 16]
+	str	D_q, [dstin]
+	ldp	C_q, D_q, [src, 48]
+	subs	count, count, 128 + 16	/* Test and readjust count.  */
+	b.ls	L(copy64_from_end)
+L(loop64):
+	stp	A_q, B_q, [dst, 16]
+	ldp	A_q, B_q, [src, 80]
+	stp	C_q, D_q, [dst, 48]
+	ldp	C_q, D_q, [src, 112]
+	add	src, src, 64
+	add	dst, dst, 64
+	subs	count, count, 64
+	b.hi	L(loop64)
+
+	/* Write the last iteration and copy 64 bytes from the end.  */
+L(copy64_from_end):
+	ldp	E_q, F_q, [srcend, -64]
+	stp	A_q, B_q, [dst, 16]
+	ldp	A_q, B_q, [srcend, -32]
+	stp	C_q, D_q, [dst, 48]
+	stp	E_q, F_q, [dstend, -64]
+	stp	A_q, B_q, [dstend, -32]
+	ret
+
+	/* Large backwards copy for overlapping copies.
+	   Copy 16 bytes and then align srcend to 16-byte alignment.  */
+L(copy_long_backwards):
+	cbz	tmp1, L(copy0)
+	ldr	D_q, [srcend, -16]
+	and	tmp1, srcend, 15
+	bic	srcend, srcend, 15
+	sub	count, count, tmp1
+	ldp	A_q, B_q, [srcend, -32]
+	str	D_q, [dstend, -16]
+	ldp	C_q, D_q, [srcend, -64]
+	sub	dstend, dstend, tmp1
+	subs	count, count, 128
+	b.ls	L(copy64_from_start)
+
+L(loop64_backwards):
+	stp	A_q, B_q, [dstend, -32]
+	ldp	A_q, B_q, [srcend, -96]
+	stp	C_q, D_q, [dstend, -64]
+	ldp	C_q, D_q, [srcend, -128]
+	sub	srcend, srcend, 64
+	sub	dstend, dstend, 64
+	subs	count, count, 64
+	b.hi	L(loop64_backwards)
+
+	/* Write the last iteration and copy 64 bytes from the start.  */
+L(copy64_from_start):
+	ldp	E_q, F_q, [src, 32]
+	stp	A_q, B_q, [dstend, -32]
+	ldp	A_q, B_q, [src]
+	stp	C_q, D_q, [dstend, -64]
+	stp	E_q, F_q, [dstin, 32]
+	stp	A_q, B_q, [dstin]
+	ret
+
+END (__memcpy_aarch64_simd)
diff --git a/libc/AOR_v20.02/string/aarch64/memcpy.S b/libc/AOR_v20.02/string/aarch64/memcpy.S
new file mode 100644
index 0000000000000..459e22848e257
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memcpy.S
@@ -0,0 +1,240 @@
+/*
+ * memcpy - copy memory area
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses.
+ *
+ */
+
+#include "../asmdefs.h"
+
+#define dstin	x0
+#define src	x1
+#define count	x2
+#define dst	x3
+#define srcend	x4
+#define dstend	x5
+#define A_l	x6
+#define A_lw	w6
+#define A_h	x7
+#define B_l	x8
+#define B_lw	w8
+#define B_h	x9
+#define C_l	x10
+#define C_lw	w10
+#define C_h	x11
+#define D_l	x12
+#define D_h	x13
+#define E_l	x14
+#define E_h	x15
+#define F_l	x16
+#define F_h	x17
+#define G_l	count
+#define G_h	dst
+#define H_l	src
+#define H_h	srcend
+#define tmp1	x14
+
+/* This implementation handles overlaps and supports both memcpy and memmove
+   from a single entry point.  It uses unaligned accesses and branchless
+   sequences to keep the code small, simple and improve performance.
+
+   Copies are split into 3 main cases: small copies of up to 32 bytes, medium
+   copies of up to 128 bytes, and large copies.  The overhead of the overlap
+   check is negligible since it is only required for large copies.
+
+   Large copies use a software pipelined loop processing 64 bytes per iteration.
+   The destination pointer is 16-byte aligned to minimize unaligned accesses.
+   The loop tail is handled by always copying 64 bytes from the end.
+*/
+
+ENTRY (__memcpy_aarch64)
+ENTRY_ALIAS (__memmove_aarch64)
+	add	srcend, src, count
+	add	dstend, dstin, count
+	cmp	count, 128
+	b.hi	L(copy_long)
+	cmp	count, 32
+	b.hi	L(copy32_128)
+
+	/* Small copies: 0..32 bytes.  */
+	cmp	count, 16
+	b.lo	L(copy16)
+	ldp	A_l, A_h, [src]
+	ldp	D_l, D_h, [srcend, -16]
+	stp	A_l, A_h, [dstin]
+	stp	D_l, D_h, [dstend, -16]
+	ret
+
+	/* Copy 8-15 bytes.  */
+L(copy16):
+	tbz	count, 3, L(copy8)
+	ldr	A_l, [src]
+	ldr	A_h, [srcend, -8]
+	str	A_l, [dstin]
+	str	A_h, [dstend, -8]
+	ret
+
+	.p2align 3
+	/* Copy 4-7 bytes.  */
+L(copy8):
+	tbz	count, 2, L(copy4)
+	ldr	A_lw, [src]
+	ldr	B_lw, [srcend, -4]
+	str	A_lw, [dstin]
+	str	B_lw, [dstend, -4]
+	ret
+
+	/* Copy 0..3 bytes using a branchless sequence.  */
+L(copy4):
+	cbz	count, L(copy0)
+	lsr	tmp1, count, 1
+	ldrb	A_lw, [src]
+	ldrb	C_lw, [srcend, -1]
+	ldrb	B_lw, [src, tmp1]
+	strb	A_lw, [dstin]
+	strb	B_lw, [dstin, tmp1]
+	strb	C_lw, [dstend, -1]
+L(copy0):
+	ret
+
+	.p2align 4
+	/* Medium copies: 33..128 bytes.  */
+L(copy32_128):
+	ldp	A_l, A_h, [src]
+	ldp	B_l, B_h, [src, 16]
+	ldp	C_l, C_h, [srcend, -32]
+	ldp	D_l, D_h, [srcend, -16]
+	cmp	count, 64
+	b.hi	L(copy128)
+	stp	A_l, A_h, [dstin]
+	stp	B_l, B_h, [dstin, 16]
+	stp	C_l, C_h, [dstend, -32]
+	stp	D_l, D_h, [dstend, -16]
+	ret
+
+	.p2align 4
+	/* Copy 65..128 bytes.  */
+L(copy128):
+	ldp	E_l, E_h, [src, 32]
+	ldp	F_l, F_h, [src, 48]
+	cmp	count, 96
+	b.ls	L(copy96)
+	ldp	G_l, G_h, [srcend, -64]
+	ldp	H_l, H_h, [srcend, -48]
+	stp	G_l, G_h, [dstend, -64]
+	stp	H_l, H_h, [dstend, -48]
+L(copy96):
+	stp	A_l, A_h, [dstin]
+	stp	B_l, B_h, [dstin, 16]
+	stp	E_l, E_h, [dstin, 32]
+	stp	F_l, F_h, [dstin, 48]
+	stp	C_l, C_h, [dstend, -32]
+	stp	D_l, D_h, [dstend, -16]
+	ret
+
+	.p2align 4
+	/* Copy more than 128 bytes.  */
+L(copy_long):
+	/* Use backwards copy if there is an overlap.  */
+	sub	tmp1, dstin, src
+	cbz	tmp1, L(copy0)
+	cmp	tmp1, count
+	b.lo	L(copy_long_backwards)
+
+	/* Copy 16 bytes and then align dst to 16-byte alignment.  */
+
+	ldp	D_l, D_h, [src]
+	and	tmp1, dstin, 15
+	bic	dst, dstin, 15
+	sub	src, src, tmp1
+	add	count, count, tmp1	/* Count is now 16 too large.  */
+	ldp	A_l, A_h, [src, 16]
+	stp	D_l, D_h, [dstin]
+	ldp	B_l, B_h, [src, 32]
+	ldp	C_l, C_h, [src, 48]
+	ldp	D_l, D_h, [src, 64]!
+	subs	count, count, 128 + 16	/* Test and readjust count.  */
+	b.ls	L(copy64_from_end)
+
+L(loop64):
+	stp	A_l, A_h, [dst, 16]
+	ldp	A_l, A_h, [src, 16]
+	stp	B_l, B_h, [dst, 32]
+	ldp	B_l, B_h, [src, 32]
+	stp	C_l, C_h, [dst, 48]
+	ldp	C_l, C_h, [src, 48]
+	stp	D_l, D_h, [dst, 64]!
+	ldp	D_l, D_h, [src, 64]!
+	subs	count, count, 64
+	b.hi	L(loop64)
+
+	/* Write the last iteration and copy 64 bytes from the end.  */
+L(copy64_from_end):
+	ldp	E_l, E_h, [srcend, -64]
+	stp	A_l, A_h, [dst, 16]
+	ldp	A_l, A_h, [srcend, -48]
+	stp	B_l, B_h, [dst, 32]
+	ldp	B_l, B_h, [srcend, -32]
+	stp	C_l, C_h, [dst, 48]
+	ldp	C_l, C_h, [srcend, -16]
+	stp	D_l, D_h, [dst, 64]
+	stp	E_l, E_h, [dstend, -64]
+	stp	A_l, A_h, [dstend, -48]
+	stp	B_l, B_h, [dstend, -32]
+	stp	C_l, C_h, [dstend, -16]
+	ret
+
+	.p2align 4
+
+	/* Large backwards copy for overlapping copies.
+	   Copy 16 bytes and then align dst to 16-byte alignment.  */
+L(copy_long_backwards):
+	ldp	D_l, D_h, [srcend, -16]
+	and	tmp1, dstend, 15
+	sub	srcend, srcend, tmp1
+	sub	count, count, tmp1
+	ldp	A_l, A_h, [srcend, -16]
+	stp	D_l, D_h, [dstend, -16]
+	ldp	B_l, B_h, [srcend, -32]
+	ldp	C_l, C_h, [srcend, -48]
+	ldp	D_l, D_h, [srcend, -64]!
+	sub	dstend, dstend, tmp1
+	subs	count, count, 128
+	b.ls	L(copy64_from_start)
+
+L(loop64_backwards):
+	stp	A_l, A_h, [dstend, -16]
+	ldp	A_l, A_h, [srcend, -16]
+	stp	B_l, B_h, [dstend, -32]
+	ldp	B_l, B_h, [srcend, -32]
+	stp	C_l, C_h, [dstend, -48]
+	ldp	C_l, C_h, [srcend, -48]
+	stp	D_l, D_h, [dstend, -64]!
+	ldp	D_l, D_h, [srcend, -64]!
+	subs	count, count, 64
+	b.hi	L(loop64_backwards)
+
+	/* Write the last iteration and copy 64 bytes from the start.  */
+L(copy64_from_start):
+	ldp	G_l, G_h, [src, 48]
+	stp	A_l, A_h, [dstend, -16]
+	ldp	A_l, A_h, [src, 32]
+	stp	B_l, B_h, [dstend, -32]
+	ldp	B_l, B_h, [src, 16]
+	stp	C_l, C_h, [dstend, -48]
+	ldp	C_l, C_h, [src]
+	stp	D_l, D_h, [dstend, -64]
+	stp	G_l, G_h, [dstin, 48]
+	stp	A_l, A_h, [dstin, 32]
+	stp	B_l, B_h, [dstin, 16]
+	stp	C_l, C_h, [dstin]
+	ret
+
+END (__memcpy_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/memset.S b/libc/AOR_v20.02/string/aarch64/memset.S
new file mode 100644
index 0000000000000..39c78dcd76941
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/memset.S
@@ -0,0 +1,115 @@
+/*
+ * memset - fill memory with a constant byte
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
+ *
+ */
+
+#include "../asmdefs.h"
+
+#define dstin	x0
+#define val	x1
+#define valw	w1
+#define count	x2
+#define dst	x3
+#define dstend	x4
+#define zva_val	x5
+
+ENTRY (__memset_aarch64)
+
+	dup	v0.16B, valw
+	add	dstend, dstin, count
+
+	cmp	count, 96
+	b.hi	L(set_long)
+	cmp	count, 16
+	b.hs	L(set_medium)
+	mov	val, v0.D[0]
+
+	/* Set 0..15 bytes.  */
+	tbz	count, 3, 1f
+	str	val, [dstin]
+	str	val, [dstend, -8]
+	ret
+	nop
+1:	tbz	count, 2, 2f
+	str	valw, [dstin]
+	str	valw, [dstend, -4]
+	ret
+2:	cbz	count, 3f
+	strb	valw, [dstin]
+	tbz	count, 1, 3f
+	strh	valw, [dstend, -2]
+3:	ret
+
+	/* Set 17..96 bytes.  */
+L(set_medium):
+	str	q0, [dstin]
+	tbnz	count, 6, L(set96)
+	str	q0, [dstend, -16]
+	tbz	count, 5, 1f
+	str	q0, [dstin, 16]
+	str	q0, [dstend, -32]
+1:	ret
+
+	.p2align 4
+	/* Set 64..96 bytes.  Write 64 bytes from the start and
+	   32 bytes from the end.  */
+L(set96):
+	str	q0, [dstin, 16]
+	stp	q0, q0, [dstin, 32]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+	.p2align 4
+L(set_long):
+	and	valw, valw, 255
+	bic	dst, dstin, 15
+	str	q0, [dstin]
+	cmp	count, 160
+	ccmp	valw, 0, 0, hs
+	b.ne	L(no_zva)
+
+#ifndef SKIP_ZVA_CHECK
+	mrs	zva_val, dczid_el0
+	and	zva_val, zva_val, 31
+	cmp	zva_val, 4		/* ZVA size is 64 bytes.  */
+	b.ne	L(no_zva)
+#endif
+	str	q0, [dst, 16]
+	stp	q0, q0, [dst, 32]
+	bic	dst, dst, 63
+	sub	count, dstend, dst	/* Count is now 64 too large.  */
+	sub	count, count, 128	/* Adjust count and bias for loop.  */
+
+	.p2align 4
+L(zva_loop):
+	add	dst, dst, 64
+	dc	zva, dst
+	subs	count, count, 64
+	b.hi	L(zva_loop)
+	stp	q0, q0, [dstend, -64]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+L(no_zva):
+	sub	count, dstend, dst	/* Count is 16 too large.  */
+	sub	dst, dst, 16		/* Dst is biased by -32.  */
+	sub	count, count, 64 + 16	/* Adjust count and bias for loop.  */
+L(no_zva_loop):
+	stp	q0, q0, [dst, 32]
+	stp	q0, q0, [dst, 64]!
+	subs	count, count, 64
+	b.hi	L(no_zva_loop)
+	stp	q0, q0, [dstend, -64]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+END (__memset_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/stpcpy-sve.S b/libc/AOR_v20.02/string/aarch64/stpcpy-sve.S
new file mode 100644
index 0000000000000..54afdab725294
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/stpcpy-sve.S
@@ -0,0 +1,11 @@
+/*
+ * stpcpy - copy a string returning pointer to end.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define BUILD_STPCPY 1
+
+#include "strcpy-sve.S"
diff --git a/libc/AOR_v20.02/string/aarch64/stpcpy.S b/libc/AOR_v20.02/string/aarch64/stpcpy.S
new file mode 100644
index 0000000000000..8cf98db4ba25a
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/stpcpy.S
@@ -0,0 +1,11 @@
+/*
+ * stpcpy - copy a string returning pointer to end.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define BUILD_STPCPY 1
+
+#include "strcpy.S"
diff --git a/libc/AOR_v20.02/string/aarch64/strchr-mte.S b/libc/AOR_v20.02/string/aarch64/strchr-mte.S
new file mode 100644
index 0000000000000..7c517916212a1
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strchr-mte.S
@@ -0,0 +1,131 @@
+/*
+ * strchr - find a character in a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+
+#define result		x0
+
+#define src		x2
+#define	tmp1		x3
+#define wtmp2		w4
+#define tmp3		x5
+
+#define vrepchr		v0
+#define qdata		q1
+#define vdata		v1
+#define vhas_nul	v2
+#define vhas_chr	v3
+#define vrepmask_0	v4
+#define vrepmask_c	v5
+#define vend		v6
+
+#define L(l) .L ## l
+
+/* Core algorithm.
+
+   For each 16-byte chunk we calculate a 64-bit syndrome value, with
+   four bits per byte (LSB is always in bits 0 and 1, for both big
+   and little-endian systems).  For each tuple, bit 0 is set if
+   the relevant byte matched the requested character; bit 1 is set
+   if the relevant byte matched the NUL end of string (we trigger
+   off bit0 for the special case of looking for NUL) and bits 2 and 3
+   are not used.
+   Since the bits in the syndrome reflect exactly the order in which
+   things occur in the original string a count_trailing_zeros()
+   operation will identify exactly which byte is causing the termination,
+   and why. */
+
+/* Locals and temporaries. */
+
+ENTRY(__strchr_aarch64_mte)
+	/* Magic constant 0x10011001 to allow us to identify which lane
+	   matches the requested byte.  Magic constant 0x20022002 used
+	   similarly for NUL termination. */
+	mov	wtmp2, #0x1001
+	movk	wtmp2, #0x1001, lsl #16
+	dup	vrepchr.16b, chrin
+	bic	src, srcin, #15		/* Work with aligned 16-byte chunks. */
+	dup	vrepmask_c.4s, wtmp2
+	ands	tmp1, srcin, #15
+	add	vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */
+	b.eq	L(loop)
+
+	/* Input string is not 16-byte aligned.  Rather than forcing
+	   the padding bytes to a safe value, we calculate the syndrome
+	   for all the bytes, but then mask off those bits of the
+	   syndrome that are related to the padding.  */
+	ldr	qdata, [src], #16
+	cmeq	vhas_nul.16b, vdata.16b, #0
+	cmeq	vhas_chr.16b, vdata.16b, vrepchr.16b
+	and	vhas_nul.16b, vhas_nul.16b, vrepmask_0.16b
+	and	vhas_chr.16b, vhas_chr.16b, vrepmask_c.16b
+	lsl	tmp1, tmp1, #2
+	orr	vend.16b, vhas_nul.16b, vhas_chr.16b
+	mov	tmp3, #~0
+	addp	vend.16b, vend.16b, vend.16b		/* 128->64 */
+	lsl	tmp1, tmp3, tmp1
+
+	mov	tmp3, vend.d[0]
+	ands	tmp1, tmp3, tmp1	/* Mask padding bits. */
+	b.ne	L(tail)
+
+L(loop):
+	ldr	qdata, [src], #32
+	cmeq	vhas_nul.16b, vdata.16b, #0
+	cmeq	vhas_chr.16b, vdata.16b, vrepchr.16b
+	/* Use a fast check for the termination condition.  */
+	orr	vend.16b, vhas_nul.16b, vhas_chr.16b
+	addp	vend.16b, vend.16b, vend.16b		/* 128->64 */
+	mov	tmp1, vend.d[0]
+	cbnz	tmp1, L(end)
+
+	ldr	qdata, [src, #-16]
+	cmeq	vhas_nul.16b, vdata.16b, #0
+	cmeq	vhas_chr.16b, vdata.16b, vrepchr.16b
+	/* Use a fast check for the termination condition.  */
+	orr	vend.16b, vhas_nul.16b, vhas_chr.16b
+	addp	vend.16b, vend.16b, vend.16b		/* 128->64 */
+	mov	tmp1, vend.d[0]
+	cbz	tmp1, L(loop)
+
+	/* Adjust src for next two subtractions. */
+	add	src, src, #16
+L(end):
+	/* Termination condition found.  Now need to establish exactly why
+	   we terminated.  */
+	and	vhas_nul.16b, vhas_nul.16b, vrepmask_0.16b
+	and	vhas_chr.16b, vhas_chr.16b, vrepmask_c.16b
+	sub	src, src, #16
+	orr	vend.16b, vhas_nul.16b, vhas_chr.16b
+	addp	vend.16b, vend.16b, vend.16b		/* 128->64 */
+
+	mov	tmp1, vend.d[0]
+L(tail):
+	/* Count the trailing zeros, by bit reversing...  */
+	rbit	tmp1, tmp1
+	/* Re-bias source.  */
+	sub	src, src, #16
+	clz	tmp1, tmp1	/* And counting the leading zeros.  */
+	/* Tmp1 is even if the target character was found first.  Otherwise
+	   we've found the end of string and we weren't looking for NUL.  */
+	tst	tmp1, #1
+	add	result, src, tmp1, lsr #2
+	csel	result, result, xzr, eq
+	ret
+
+END(__strchr_aarch64_mte)
diff --git a/libc/AOR_v20.02/string/aarch64/strchr-sve.S b/libc/AOR_v20.02/string/aarch64/strchr-sve.S
new file mode 100644
index 0000000000000..3f7d782c00273
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strchr-sve.S
@@ -0,0 +1,72 @@
+/*
+ * strchr/strchrnul - find a character in a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+/* To build as strchrnul, define BUILD_STRCHRNUL before compiling this file.  */
+#ifdef BUILD_STRCHRNUL
+#define FUNC  __strchrnul_aarch64_sve
+#else
+#define FUNC  __strchr_aarch64_sve
+#endif
+
+	.globl	FUNC
+	.type	FUNC, %function
+	.p2align 4
+FUNC:
+	dup	z1.b, w1		/* replicate byte across vector */
+	setffr				/* initialize FFR */
+	ptrue	p1.b			/* all ones; loop invariant */
+
+	.p2align 4
+	/* Read a vector's worth of bytes, stopping on first fault.  */
+0:	ldff1b	z0.b, p1/z, [x0, xzr]
+	rdffrs	p0.b, p1/z
+	b.nlast	2f
+
+	/* First fault did not fail: the whole vector is valid.
+	   Avoid depending on the contents of FFR beyond the branch.  */
+	incb	x0				/* speculate increment */
+	cmpeq	p2.b, p1/z, z0.b, z1.b		/* search for c */
+	cmpeq	p3.b, p1/z, z0.b, 0		/* search for 0 */
+	orrs	p4.b, p1/z, p2.b, p3.b		/* c | 0 */
+	b.none	0b
+	decb	x0				/* undo speculate */
+
+	/* Found C or 0.  */
+1:	brka	p4.b, p1/z, p4.b	/* find first such */
+	sub	x0, x0, 1		/* adjust pointer for that byte */
+	incp	x0, p4.b
+#ifndef BUILD_STRCHRNUL
+	ptest	p4, p2.b		/* was first in c? */
+	csel	x0, xzr, x0, none	/* if there was no c, return null */
+#endif
+	ret
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparision only on the valid bytes.  */
+2:	cmpeq	p2.b, p0/z, z0.b, z1.b		/* search for c */
+	cmpeq	p3.b, p0/z, z0.b, 0		/* search for 0 */
+	orrs	p4.b, p0/z, p2.b, p3.b		/* c | 0 */
+	b.any	1b
+
+	/* No C or 0 found.  Re-init FFR, increment, and loop.  */
+	setffr
+	incp	x0, p0.b
+	b	0b
+
+	.size	FUNC, . - FUNC
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strchr.S b/libc/AOR_v20.02/string/aarch64/strchr.S
new file mode 100644
index 0000000000000..4c7617f219481
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strchr.S
@@ -0,0 +1,132 @@
+/*
+ * strchr - find a character in a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+
+#define result		x0
+
+#define src		x2
+#define	tmp1		x3
+#define wtmp2		w4
+#define tmp3		x5
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_nul1	v3
+#define vhas_nul2	v4
+#define vhas_chr1	v5
+#define vhas_chr2	v6
+#define vrepmask_0	v7
+#define vrepmask_c	v16
+#define vend1		v17
+#define vend2		v18
+
+/* Core algorithm.
+
+   For each 32-byte hunk we calculate a 64-bit syndrome value, with
+   two bits per byte (LSB is always in bits 0 and 1, for both big
+   and little-endian systems).  For each tuple, bit 0 is set iff
+   the relevant byte matched the requested character; bit 1 is set
+   iff the relevant byte matched the NUL end of string (we trigger
+   off bit0 for the special case of looking for NUL).  Since the bits
+   in the syndrome reflect exactly the order in which things occur
+   in the original string a count_trailing_zeros() operation will
+   identify exactly which byte is causing the termination, and why.  */
+
+/* Locals and temporaries.  */
+
+ENTRY (__strchr_aarch64)
+	/* Magic constant 0x40100401 to allow us to identify which lane
+	   matches the requested byte.  Magic constant 0x80200802 used
+	   similarly for NUL termination.  */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	bic	src, srcin, #31		/* Work with aligned 32-byte hunks.  */
+	dup	vrepmask_c.4s, wtmp2
+	ands	tmp1, srcin, #31
+	add	vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */
+	b.eq	L(loop)
+
+	/* Input string is not 32-byte aligned.  Rather than forcing
+	   the padding bytes to a safe value, we calculate the syndrome
+	   for all the bytes, but then mask off those bits of the
+	   syndrome that are related to the padding.  */
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	neg	tmp1, tmp1
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	and	vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
+	and	vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
+	orr	vend1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vend2.16b, vhas_nul2.16b, vhas_chr2.16b
+	lsl	tmp1, tmp1, #1
+	addp	vend1.16b, vend1.16b, vend2.16b		// 256->128
+	mov	tmp3, #~0
+	addp	vend1.16b, vend1.16b, vend2.16b		// 128->64
+	lsr	tmp1, tmp3, tmp1
+
+	mov	tmp3, vend1.d[0]
+	bic	tmp1, tmp3, tmp1	// Mask padding bits.
+	cbnz	tmp1, L(tail)
+
+L(loop):
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	/* Use a fast check for the termination condition.  */
+	orr	vend1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vend2.16b, vhas_nul2.16b, vhas_chr2.16b
+	orr	vend1.16b, vend1.16b, vend2.16b
+	addp	vend1.2d, vend1.2d, vend1.2d
+	mov	tmp1, vend1.d[0]
+	cbz	tmp1, L(loop)
+
+	/* Termination condition found.  Now need to establish exactly why
+	   we terminated.  */
+	and	vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
+	and	vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
+	orr	vend1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vend2.16b, vhas_nul2.16b, vhas_chr2.16b
+	addp	vend1.16b, vend1.16b, vend2.16b		// 256->128
+	addp	vend1.16b, vend1.16b, vend2.16b		// 128->64
+
+	mov	tmp1, vend1.d[0]
+L(tail):
+	/* Count the trailing zeros, by bit reversing...  */
+	rbit	tmp1, tmp1
+	/* Re-bias source.  */
+	sub	src, src, #32
+	clz	tmp1, tmp1	/* And counting the leading zeros.  */
+	/* Tmp1 is even if the target charager was found first.  Otherwise
+	   we've found the end of string and we weren't looking for NUL.  */
+	tst	tmp1, #1
+	add	result, src, tmp1, lsr #1
+	csel	result, result, xzr, eq
+	ret
+
+END (__strchr_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/strchrnul-sve.S b/libc/AOR_v20.02/string/aarch64/strchrnul-sve.S
new file mode 100644
index 0000000000000..0a3a60bbece83
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strchrnul-sve.S
@@ -0,0 +1,10 @@
+/*
+ * strchrnul - find a character or nul in a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define BUILD_STRCHRNUL
+#include "strchr-sve.S"
diff --git a/libc/AOR_v20.02/string/aarch64/strchrnul.S b/libc/AOR_v20.02/string/aarch64/strchrnul.S
new file mode 100644
index 0000000000000..50bd90c56922c
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strchrnul.S
@@ -0,0 +1,117 @@
+/*
+ * strchrnul - find a character or nul in a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+
+#define result		x0
+
+#define src		x2
+#define	tmp1		x3
+#define wtmp2		w4
+#define tmp3		x5
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_nul1	v3
+#define vhas_nul2	v4
+#define vhas_chr1	v5
+#define vhas_chr2	v6
+#define vrepmask	v7
+#define vend1		v16
+
+/* Core algorithm.
+
+   For each 32-byte hunk we calculate a 64-bit syndrome value, with
+   two bits per byte (LSB is always in bits 0 and 1, for both big
+   and little-endian systems).  For each tuple, bit 0 is set iff
+   the relevant byte matched the requested character or nul.  Since the
+   bits in the syndrome reflect exactly the order in which things occur
+   in the original string a count_trailing_zeros() operation will
+   identify exactly which byte is causing the termination.  */
+
+/* Locals and temporaries.  */
+
+ENTRY (__strchrnul_aarch64)
+	/* Magic constant 0x40100401 to allow us to identify which lane
+	   matches the termination condition.  */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	bic	src, srcin, #31		/* Work with aligned 32-byte hunks.  */
+	dup	vrepmask.4s, wtmp2
+	ands	tmp1, srcin, #31
+	b.eq	L(loop)
+
+	/* Input string is not 32-byte aligned.  Rather than forcing
+	   the padding bytes to a safe value, we calculate the syndrome
+	   for all the bytes, but then mask off those bits of the
+	   syndrome that are related to the padding.  */
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	neg	tmp1, tmp1
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	orr	vhas_chr1.16b, vhas_chr1.16b, vhas_nul1.16b
+	orr	vhas_chr2.16b, vhas_chr2.16b, vhas_nul2.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	lsl	tmp1, tmp1, #1
+	addp	vend1.16b, vhas_chr1.16b, vhas_chr2.16b	// 256->128
+	mov	tmp3, #~0
+	addp	vend1.16b, vend1.16b, vend1.16b		// 128->64
+	lsr	tmp1, tmp3, tmp1
+
+	mov	tmp3, vend1.d[0]
+	bic	tmp1, tmp3, tmp1	// Mask padding bits.
+	cbnz	tmp1, L(tail)
+
+L(loop):
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	/* Use a fast check for the termination condition.  */
+	orr	vhas_chr1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vhas_chr2.16b, vhas_nul2.16b, vhas_chr2.16b
+	orr	vend1.16b, vhas_chr1.16b, vhas_chr2.16b
+	addp	vend1.2d, vend1.2d, vend1.2d
+	mov	tmp1, vend1.d[0]
+	cbz	tmp1, L(loop)
+
+	/* Termination condition found.  Now need to establish exactly why
+	   we terminated.  */
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	addp	vend1.16b, vhas_chr1.16b, vhas_chr2.16b		// 256->128
+	addp	vend1.16b, vend1.16b, vend1.16b		// 128->64
+
+	mov	tmp1, vend1.d[0]
+L(tail):
+	/* Count the trailing zeros, by bit reversing...  */
+	rbit	tmp1, tmp1
+	/* Re-bias source.  */
+	sub	src, src, #32
+	clz	tmp1, tmp1	/* ... and counting the leading zeros.  */
+	/* tmp1 is twice the offset into the fragment.  */
+	add	result, src, tmp1, lsr #1
+	ret
+
+END (__strchrnul_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/strcmp-sve.S b/libc/AOR_v20.02/string/aarch64/strcmp-sve.S
new file mode 100644
index 0000000000000..35aac0b7d0d2a
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strcmp-sve.S
@@ -0,0 +1,60 @@
+/*
+ * __strcmp_aarch64_sve - compare two strings
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__strcmp_aarch64_sve
+	.type	__strcmp_aarch64_sve, %function
+	.p2align 4
+__strcmp_aarch64_sve:
+	setffr				/* initialize FFR */
+	ptrue	p1.b, all		/* all ones; loop invariant */
+	mov	x2, 0			/* initialize offset */
+	nop
+
+	/* Read a vector's worth of bytes, stopping on first fault.  */
+0:	ldff1b	z0.b, p1/z, [x0, x2]
+	ldff1b	z1.b, p1/z, [x1, x2]
+	rdffrs	p0.b, p1/z
+	b.nlast	2f
+
+	/* First fault did not fail: the whole vector is valid.
+	   Avoid depending on the contents of FFR beyond the branch.  */
+	incb	x2, all			/* skip bytes for next round */
+	cmpeq	p2.b, p1/z, z0.b, z1.b	/* compare strings */
+	cmpne	p3.b, p1/z, z0.b, 0	/* search for ~zero */
+	nands	p2.b, p1/z, p2.b, p3.b	/* ~(eq & ~zero) -> ne | zero */
+	b.none	0b
+
+	/* Found end-of-string or inequality.  */
+1:	brkb	p2.b, p1/z, p2.b	/* find first such */
+	lasta	w0, p2, z0.b		/* extract each char */
+	lasta	w1, p2, z1.b
+	sub	x0, x0, x1		/* return comparison */
+	ret
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparison only on the valid bytes.  */
+2:	incp	x2, p0.b		/* skip bytes for next round */
+	setffr				/* re-init FFR for next round */
+	cmpeq	p2.b, p0/z, z0.b, z1.b	/* compare strings, as above */
+	cmpne	p3.b, p0/z, z0.b, 0
+	nands	p2.b, p0/z, p2.b, p3.b
+	b.none	0b
+	b	1b
+
+	.size	__strcmp_aarch64_sve, . - __strcmp_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strcmp.S b/libc/AOR_v20.02/string/aarch64/strcmp.S
new file mode 100644
index 0000000000000..0dc5031e73265
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strcmp.S
@@ -0,0 +1,171 @@
+/*
+ * strcmp - compare two strings
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+#include "../asmdefs.h"
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+/* Parameters and result.  */
+#define src1		x0
+#define src2		x1
+#define result		x0
+
+/* Internal variables.  */
+#define data1		x2
+#define data1w		w2
+#define data2		x3
+#define data2w		w3
+#define has_nul		x4
+#define diff		x5
+#define syndrome	x6
+#define tmp1		x7
+#define tmp2		x8
+#define tmp3		x9
+#define zeroones	x10
+#define pos		x11
+
+	/* Start of performance-critical section  -- one 64B cache line.  */
+ENTRY (__strcmp_aarch64)
+	eor	tmp1, src1, src2
+	mov	zeroones, #REP8_01
+	tst	tmp1, #7
+	b.ne	L(misaligned8)
+	ands	tmp1, src1, #7
+	b.ne	L(mutual_align)
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+L(loop_aligned):
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+L(start_realigned):
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	bic	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	orr	syndrome, diff, has_nul
+	cbz	syndrome, L(loop_aligned)
+	/* End of performance-critical section  -- one 64B cache line.  */
+
+L(end):
+#ifndef	__AARCH64EB__
+	rev	syndrome, syndrome
+	rev	data1, data1
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	clz	pos, syndrome
+	rev	data2, data2
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#else
+	/* For big-endian we cannot use the trick with the syndrome value
+	   as carry-propagation can corrupt the upper bits if the trailing
+	   bytes in the string contain 0x01.  */
+	/* However, if there is no NUL byte in the dword, we can generate
+	   the result directly.  We can't just subtract the bytes as the
+	   MSB might be significant.  */
+	cbnz	has_nul, 1f
+	cmp	data1, data2
+	cset	result, ne
+	cneg	result, result, lo
+	ret
+1:
+	/* Re-compute the NUL-byte detection, using a byte-reversed value.  */
+	rev	tmp3, data1
+	sub	tmp1, tmp3, zeroones
+	orr	tmp2, tmp3, #REP8_7f
+	bic	has_nul, tmp1, tmp2
+	rev	has_nul, has_nul
+	orr	syndrome, diff, has_nul
+	clz	pos, syndrome
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#endif
+
+L(mutual_align):
+	/* Sources are mutually aligned, but are not currently at an
+	   alignment boundary.  Round down the addresses and then mask off
+	   the bytes that preceed the start point.  */
+	bic	src1, src1, #7
+	bic	src2, src2, #7
+	lsl	tmp1, tmp1, #3		/* Bytes beyond alignment -> bits.  */
+	ldr	data1, [src1], #8
+	neg	tmp1, tmp1		/* Bits to alignment -64.  */
+	ldr	data2, [src2], #8
+	mov	tmp2, #~0
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	orr	data1, data1, tmp2
+	orr	data2, data2, tmp2
+	b	L(start_realigned)
+
+L(misaligned8):
+	/* Align SRC1 to 8 bytes and then compare 8 bytes at a time, always
+	   checking to make sure that we don't access beyond page boundary in
+	   SRC2.  */
+	tst	src1, #7
+	b.eq	L(loop_misaligned)
+L(do_misaligned):
+	ldrb	data1w, [src1], #1
+	ldrb	data2w, [src2], #1
+	cmp	data1w, #1
+	ccmp	data1w, data2w, #0, cs	/* NZCV = 0b0000.  */
+	b.ne	L(done)
+	tst	src1, #7
+	b.ne	L(do_misaligned)
+
+L(loop_misaligned):
+	/* Test if we are within the last dword of the end of a 4K page.  If
+	   yes then jump back to the misaligned loop to copy a byte at a time.  */
+	and	tmp1, src2, #0xff8
+	eor	tmp1, tmp1, #0xff8
+	cbz	tmp1, L(do_misaligned)
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	bic	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	orr	syndrome, diff, has_nul
+	cbz	syndrome, L(loop_misaligned)
+	b	L(end)
+
+L(done):
+	sub	result, data1, data2
+	ret
+
+END (__strcmp_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/strcpy-sve.S b/libc/AOR_v20.02/string/aarch64/strcpy-sve.S
new file mode 100644
index 0000000000000..43e7621b6261c
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strcpy-sve.S
@@ -0,0 +1,72 @@
+/*
+ * strcpy/stpcpy - copy a string returning pointer to start/end.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+/* To build as stpcpy, define BUILD_STPCPY before compiling this file.  */
+#ifdef BUILD_STPCPY
+#define FUNC  __stpcpy_aarch64_sve
+#else
+#define FUNC  __strcpy_aarch64_sve
+#endif
+
+	.globl	FUNC
+	.type	FUNC, %function
+	.p2align 4
+FUNC:
+	setffr				/* initialize FFR */
+	ptrue	p2.b, all		/* all ones; loop invariant */
+	mov	x2, 0			/* initialize offset */
+
+	.p2align 4
+	/* Read a vector's worth of bytes, stopping on first fault.  */
+0:	ldff1b	z0.b, p2/z, [x1, x2]
+	rdffrs	p0.b, p2/z
+	b.nlast	1f
+
+	/* First fault did not fail: the whole vector is valid.
+	   Avoid depending on the contexts of FFR beyond the branch.  */
+	cmpeq	p1.b, p2/z, z0.b, 0	/* search for zeros */
+	b.any	2f
+
+	/* No zero found.  Store the whole vector and loop.  */
+	st1b	z0.b, p2, [x0, x2]
+	incb	x2, all
+	b	0b
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparison only on the valid bytes.  */
+1:	cmpeq	p1.b, p0/z, z0.b, 0	/* search for zeros */
+	b.any	2f
+
+	/* No zero found.  Store the valid portion of the vector and loop.  */
+	setffr				/* re-init FFR */
+	st1b	z0.b, p0, [x0, x2]
+	incp	x2, p0.b
+	b	0b
+
+	/* Zero found.  Crop the vector to the found zero and finish.  */
+2:	brka	p0.b, p2/z, p1.b
+	st1b	z0.b, p0, [x0, x2]
+#ifdef BUILD_STPCPY
+	add	x0, x0, x2
+	sub	x0, x0, 1
+	incp	x0, p0.b
+#endif
+	ret
+
+	.size	FUNC, . - FUNC
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strcpy.S b/libc/AOR_v20.02/string/aarch64/strcpy.S
new file mode 100644
index 0000000000000..dde9afbb7fb18
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strcpy.S
@@ -0,0 +1,309 @@
+/*
+ * strcpy/stpcpy - copy a string returning pointer to start/end.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses, min page size 4k.
+ */
+
+#include "../asmdefs.h"
+
+/* To build as stpcpy, define BUILD_STPCPY before compiling this file.
+
+   To test the page crossing code path more thoroughly, compile with
+   -DSTRCPY_TEST_PAGE_CROSS - this will force all copies through the slower
+   entry path.  This option is not intended for production use.  */
+
+/* Arguments and results.  */
+#define dstin		x0
+#define srcin		x1
+
+/* Locals and temporaries.  */
+#define src		x2
+#define dst		x3
+#define data1		x4
+#define data1w		w4
+#define data2		x5
+#define data2w		w5
+#define has_nul1	x6
+#define has_nul2	x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define tmp4		x11
+#define zeroones	x12
+#define data1a		x13
+#define data2a		x14
+#define pos		x15
+#define len		x16
+#define to_align	x17
+
+#ifdef BUILD_STPCPY
+#define STRCPY __stpcpy_aarch64
+#else
+#define STRCPY __strcpy_aarch64
+#endif
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+	/* AArch64 systems have a minimum page size of 4k.  We can do a quick
+	   page size check for crossing this boundary on entry and if we
+	   do not, then we can short-circuit much of the entry code.  We
+	   expect early page-crossing strings to be rare (probability of
+	   16/MIN_PAGE_SIZE ~= 0.4%), so the branch should be quite
+	   predictable, even with random strings.
+
+	   We don't bother checking for larger page sizes, the cost of setting
+	   up the correct page size is just not worth the extra gain from
+	   a small reduction in the cases taking the slow path.  Note that
+	   we only care about whether the first fetch, which may be
+	   misaligned, crosses a page boundary - after that we move to aligned
+	   fetches for the remainder of the string.  */
+
+#ifdef STRCPY_TEST_PAGE_CROSS
+	/* Make everything that isn't Qword aligned look like a page cross.  */
+#define MIN_PAGE_P2 4
+#else
+#define MIN_PAGE_P2 12
+#endif
+
+#define MIN_PAGE_SIZE (1 << MIN_PAGE_P2)
+
+ENTRY (STRCPY)
+	/* For moderately short strings, the fastest way to do the copy is to
+	   calculate the length of the string in the same way as strlen, then
+	   essentially do a memcpy of the result.  This avoids the need for
+	   multiple byte copies and further means that by the time we
+	   reach the bulk copy loop we know we can always use DWord
+	   accesses.  We expect __strcpy_aarch64 to rarely be called repeatedly
+	   with the same source string, so branch prediction is likely to
+	   always be difficult - we mitigate against this by preferring
+	   conditional select operations over branches whenever this is
+	   feasible.  */
+	and	tmp2, srcin, #(MIN_PAGE_SIZE - 1)
+	mov	zeroones, #REP8_01
+	and	to_align, srcin, #15
+	cmp	tmp2, #(MIN_PAGE_SIZE - 16)
+	neg	tmp1, to_align
+	/* The first fetch will straddle a (possible) page boundary iff
+	   srcin + 15 causes bit[MIN_PAGE_P2] to change value.  A 16-byte
+	   aligned string will never fail the page align check, so will
+	   always take the fast path.  */
+	b.gt	L(page_cross)
+
+L(page_cross_ok):
+	ldp	data1, data2, [srcin]
+#ifdef __AARCH64EB__
+	/* Because we expect the end to be found within 16 characters
+	   (profiling shows this is the most common case), it's worth
+	   swapping the bytes now to save having to recalculate the
+	   termination syndrome later.  We preserve data1 and data2
+	   so that we can re-use the values later on.  */
+	rev	tmp2, data1
+	sub	tmp1, tmp2, zeroones
+	orr	tmp2, tmp2, #REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	b.ne	L(fp_le8)
+	rev	tmp4, data2
+	sub	tmp3, tmp4, zeroones
+	orr	tmp4, tmp4, #REP8_7f
+#else
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	b.ne	L(fp_le8)
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+#endif
+	bics	has_nul2, tmp3, tmp4
+	b.eq	L(bulk_entry)
+
+	/* The string is short (<=16 bytes).  We don't know exactly how
+	   short though, yet.  Work out the exact length so that we can
+	   quickly select the optimal copy strategy.  */
+L(fp_gt8):
+	rev	has_nul2, has_nul2
+	clz	pos, has_nul2
+	mov	tmp2, #56
+	add	dst, dstin, pos, lsr #3		/* Bits to bytes.  */
+	sub	pos, tmp2, pos
+#ifdef __AARCH64EB__
+	lsr	data2, data2, pos
+#else
+	lsl	data2, data2, pos
+#endif
+	str	data2, [dst, #1]
+	str	data1, [dstin]
+#ifdef BUILD_STPCPY
+	add	dstin, dst, #8
+#endif
+	ret
+
+L(fp_le8):
+	rev	has_nul1, has_nul1
+	clz	pos, has_nul1
+	add	dst, dstin, pos, lsr #3		/* Bits to bytes.  */
+	subs	tmp2, pos, #24			/* Pos in bits. */
+	b.lt	L(fp_lt4)
+#ifdef __AARCH64EB__
+	mov	tmp2, #56
+	sub	pos, tmp2, pos
+	lsr	data2, data1, pos
+	lsr	data1, data1, #32
+#else
+	lsr	data2, data1, tmp2
+#endif
+	/* 4->7 bytes to copy.  */
+	str	data2w, [dst, #-3]
+	str	data1w, [dstin]
+#ifdef BUILD_STPCPY
+	mov	dstin, dst
+#endif
+	ret
+L(fp_lt4):
+	cbz	pos, L(fp_lt2)
+	/* 2->3 bytes to copy.  */
+#ifdef __AARCH64EB__
+	lsr	data1, data1, #48
+#endif
+	strh	data1w, [dstin]
+	/* Fall-through, one byte (max) to go.  */
+L(fp_lt2):
+	/* Null-terminated string.  Last character must be zero!  */
+	strb	wzr, [dst]
+#ifdef BUILD_STPCPY
+	mov	dstin, dst
+#endif
+	ret
+
+	.p2align 6
+	/* Aligning here ensures that the entry code and main loop all lies
+	   within one 64-byte cache line.  */
+L(bulk_entry):
+	sub	to_align, to_align, #16
+	stp	data1, data2, [dstin]
+	sub	src, srcin, to_align
+	sub	dst, dstin, to_align
+	b	L(entry_no_page_cross)
+
+	/* The inner loop deals with two Dwords at a time.  This has a
+	   slightly higher start-up cost, but we should win quite quickly,
+	   especially on cores with a high number of issue slots per
+	   cycle, as we get much better parallelism out of the operations.  */
+L(main_loop):
+	stp	data1, data2, [dst], #16
+L(entry_no_page_cross):
+	ldp	data1, data2, [src], #16
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+	bics	has_nul2, tmp3, tmp4
+	ccmp	has_nul1, #0, #0, eq	/* NZCV = 0000  */
+	b.eq	L(main_loop)
+
+	/* Since we know we are copying at least 16 bytes, the fastest way
+	   to deal with the tail is to determine the location of the
+	   trailing NUL, then (re)copy the 16 bytes leading up to that.  */
+	cmp	has_nul1, #0
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	csel	data1, data1, data2, ne
+	rev	data1, data1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+#else
+	csel	has_nul1, has_nul1, has_nul2, ne
+#endif
+	rev	has_nul1, has_nul1
+	clz	pos, has_nul1
+	add	tmp1, pos, #72
+	add	pos, pos, #8
+	csel	pos, pos, tmp1, ne
+	add	src, src, pos, lsr #3
+	add	dst, dst, pos, lsr #3
+	ldp	data1, data2, [src, #-32]
+	stp	data1, data2, [dst, #-16]
+#ifdef BUILD_STPCPY
+	sub	dstin, dst, #1
+#endif
+	ret
+
+L(page_cross):
+	bic	src, srcin, #15
+	/* Start by loading two words at [srcin & ~15], then forcing the
+	   bytes that precede srcin to 0xff.  This means they never look
+	   like termination bytes.  */
+	ldp	data1, data2, [src]
+	lsl	tmp1, tmp1, #3	/* Bytes beyond alignment -> bits.  */
+	tst	to_align, #7
+	csetm	tmp2, ne
+#ifdef __AARCH64EB__
+	lsl	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	lsr	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	orr	data1, data1, tmp2
+	orr	data2a, data2, tmp2
+	cmp	to_align, #8
+	csinv	data1, data1, xzr, lt
+	csel	data2, data2, data2a, lt
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+	bics	has_nul2, tmp3, tmp4
+	ccmp	has_nul1, #0, #0, eq	/* NZCV = 0000  */
+	b.eq	L(page_cross_ok)
+	/* We now need to make data1 and data2 look like they've been
+	   loaded directly from srcin.  Do a rotate on the 128-bit value.  */
+	lsl	tmp1, to_align, #3	/* Bytes->bits.  */
+	neg	tmp2, to_align, lsl #3
+#ifdef __AARCH64EB__
+	lsl	data1a, data1, tmp1
+	lsr	tmp4, data2, tmp2
+	lsl	data2, data2, tmp1
+	orr	tmp4, tmp4, data1a
+	cmp	to_align, #8
+	csel	data1, tmp4, data2, lt
+	rev	tmp2, data1
+	rev	tmp4, data2
+	sub	tmp1, tmp2, zeroones
+	orr	tmp2, tmp2, #REP8_7f
+	sub	tmp3, tmp4, zeroones
+	orr	tmp4, tmp4, #REP8_7f
+#else
+	lsr	data1a, data1, tmp1
+	lsl	tmp4, data2, tmp2
+	lsr	data2, data2, tmp1
+	orr	tmp4, tmp4, data1a
+	cmp	to_align, #8
+	csel	data1, tmp4, data2, lt
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+#endif
+	bic	has_nul1, tmp1, tmp2
+	cbnz	has_nul1, L(fp_le8)
+	bic	has_nul2, tmp3, tmp4
+	b	L(fp_gt8)
+
+END (STRCPY)
diff --git a/libc/AOR_v20.02/string/aarch64/strlen-mte.S b/libc/AOR_v20.02/string/aarch64/strlen-mte.S
new file mode 100644
index 0000000000000..8037abff865cd
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strlen-mte.S
@@ -0,0 +1,186 @@
+/*
+ * strlen - calculate the length of a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64.
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define len		x0
+
+/* Locals and temporaries.  */
+#define src		x1
+#define data1		x2
+#define data2		x3
+#define has_nul1	x4
+#define has_nul2	x5
+#define tmp1		x4
+#define tmp2		x5
+#define tmp3		x6
+#define tmp4		x7
+#define zeroones	x8
+#define offset		x9
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word. A faster check
+	   (X - 1) & 0x80 is zero for non-NUL ASCII characters, but gives
+	   false hits for characters 129..255.	*/
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+
+	/* This implementation is compatible with Memory Tagging. All loads
+	   are 16 bytes in size and 16 bytes aligned. This also avoids the
+	   need for page boundary checks. This implementation is correct
+	   even without Memory Tagging, but other implementations could be
+	   more beneficial if Memory Tagging is not enabled.
+
+	   First load is aligned down and can contain bytes that are located
+	   before the string. This is handled by modifying the "zeroones"
+	   mask. The bytes that need to be ignored are set to zero.
+	   If the string is aligned in such a way that 8 or more bytes from
+	   the first load should be ignored, there is a special case
+	   (skip_first_8_bytes) which only compares the second 8 bytes.
+
+	   If there is a NUL byte in the first load, we calculate the length
+	   from the 2 8-byte words using conditional select to reduce branch
+	   mispredictions.
+
+	   If the string is longer than 16 bytes, we check 32 bytes per
+	   iteration using the fast NUL check (main_loop). If we encounter
+	   non-ASCII characters, we fallback to a second loop
+	   (nonascii_loop) using the full NUL check.  */
+
+ENTRY(__strlen_aarch64_mte)
+	bic	src, srcin, 15	/* Align down to 16 bytes.  */
+	mov	zeroones, REP8_01
+	/* (offset & 63) holds number of bits to ignore in a register.*/
+	lsl	offset, srcin, 3
+	ldp	data1, data2, [src], -16
+	lsl	tmp1, zeroones, offset	/* Shift (offset & 63).  */
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul1/2 directly.
+	   e.g. 0x0100 - 0x0101 = 0xffff, so 0x01 will be mistaken for NUL.
+	   Since we expect strings to be small and early-exit,
+	   byte-swap the data now so has_null1/2 will be correct.  */
+	rev	data1, data1
+	rev	data2, data2
+#endif
+	tbnz	srcin, 3, L(skip_first_8_bytes)
+	sub	tmp1, data1, tmp1
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	/* If comparison happens, C flag is always set. */
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(main_loop)
+
+	/* Enter with C = has_nul1 == 0.  */
+	csel	has_nul1, has_nul1, has_nul2, cc
+	and	tmp2, srcin, 7	/* Bytes to ignore. */
+	rev	has_nul1, has_nul1
+	neg	tmp2, tmp2
+	clz	tmp1, has_nul1	/* Count bits before NUL. */
+	/* Add 8 if NUL byte is not in first register. */
+	add	tmp3, tmp2, 8
+	csel	len, tmp2, tmp3, cc
+	add	len, len, tmp1, lsr 3
+	ret
+
+L(skip_first_8_bytes):
+	sub	tmp1, data2, tmp1
+	orr	tmp2, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	beq	L(main_loop)
+
+	rev	has_nul1, has_nul1
+	lsl	tmp1, has_nul1, offset	/* Ignore bytes before string. */
+	clz	tmp1, tmp1	/* Count bits before NUL. */
+	lsr	len, tmp1, 3
+	ret
+
+	/* The inner loop processes 32 bytes per iteration and uses the fast
+	   NUL check.  If we encounter non-ASCII characters, use a second
+	   loop with the accurate NUL check.  */
+	.p2align 4
+L(main_loop):
+	ldp	data1, data2, [src, 32]!
+	sub	tmp1, data1, zeroones
+	sub	tmp3, data2, zeroones
+	orr	tmp2, tmp1, tmp3
+	tst	tmp2, zeroones, lsl 7
+	bne	1f
+	ldp	data1, data2, [src, 16]
+	sub	tmp1, data1, zeroones
+	sub	tmp3, data2, zeroones
+	orr	tmp2, tmp1, tmp3
+	tst	tmp2, zeroones, lsl 7
+	beq	L(main_loop)
+	add	src, src, 16
+1:
+	/* The fast check failed, so do the slower, accurate NUL check.	 */
+	orr	tmp2, data1, REP8_7f
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(nonascii_loop)
+
+	/* Enter with C = has_nul1 == 0.  */
+L(tail):
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul1/2 directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	csel	data1, data1, data2, cc
+	rev	data1, data1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	bic	has_nul1, tmp1, tmp2
+#else
+	csel	has_nul1, has_nul1, has_nul2, cc
+#endif
+	sub	len, src, srcin
+	rev	has_nul1, has_nul1
+	add	tmp2, len, 8
+	clz	tmp1, has_nul1
+	csel	len, len, tmp2, cc
+	add	len, len, tmp1, lsr 3
+	ret
+
+L(nonascii_loop):
+	ldp	data1, data2, [src, 16]!
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	bne	L(tail)
+	ldp	data1, data2, [src, 16]!
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(nonascii_loop)
+	b	L(tail)
+
+END(__strlen_aarch64_mte)
diff --git a/libc/AOR_v20.02/string/aarch64/strlen-sve.S b/libc/AOR_v20.02/string/aarch64/strlen-sve.S
new file mode 100644
index 0000000000000..88bf0ee91bcdf
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strlen-sve.S
@@ -0,0 +1,58 @@
+/*
+ * __strlen_aarch64_sve - compute the length of a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__strlen_aarch64_sve
+	.type	__strlen_aarch64_sve, %function
+	.p2align 4
+__strlen_aarch64_sve:
+	setffr			/* initialize FFR */
+	ptrue	p2.b		/* all ones; loop invariant */
+	mov	x1, 0		/* initialize length */
+	nop
+
+	/* Read a vector's worth of bytes, stopping on first fault.  */
+0:	ldff1b	z0.b, p2/z, [x0, x1]
+	nop
+	rdffrs	p0.b, p2/z
+	b.nlast	2f
+
+	/* First fault did not fail: the whole vector is valid.
+	   Avoid depending on the contents of FFR beyond the branch.  */
+	incb	x1, all			/* speculate increment */
+	cmpeq	p1.b, p2/z, z0.b, 0	/* loop if no zeros */
+	b.none	0b
+	decb	x1, all			/* undo speculate */
+
+	/* Zero found.  Select the bytes before the first and count them.  */
+1:	brkb	p0.b, p2/z, p1.b
+	incp	x1, p0.b
+	mov	x0, x1
+	ret
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparison only on the valid bytes.  */
+2:	cmpeq	p1.b, p0/z, z0.b, 0
+	b.any	1b
+
+	/* No zero found.  Re-init FFR, increment, and loop.  */
+	setffr
+	incp	x1, p0.b
+	b	0b
+
+	.size	__strlen_aarch64_sve, . - __strlen_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strlen.S b/libc/AOR_v20.02/string/aarch64/strlen.S
new file mode 100644
index 0000000000000..2d560db2cfba1
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strlen.S
@@ -0,0 +1,207 @@
+/*
+ * strlen - calculate the length of a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses, min page size 4k.
+ */
+
+#include "../asmdefs.h"
+
+/* To test the page crossing code path more thoroughly, compile with
+   -DTEST_PAGE_CROSS - this will force all calls through the slower
+   entry path.  This option is not intended for production use.	 */
+
+/* Arguments and results.  */
+#define srcin		x0
+#define len		x0
+
+/* Locals and temporaries.  */
+#define src		x1
+#define data1		x2
+#define data2		x3
+#define has_nul1	x4
+#define has_nul2	x5
+#define tmp1		x4
+#define tmp2		x5
+#define tmp3		x6
+#define tmp4		x7
+#define zeroones	x8
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word. A faster check
+	   (X - 1) & 0x80 is zero for non-NUL ASCII characters, but gives
+	   false hits for characters 129..255.	*/
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+#ifdef TEST_PAGE_CROSS
+# define MIN_PAGE_SIZE 15
+#else
+# define MIN_PAGE_SIZE 4096
+#endif
+
+	/* Since strings are short on average, we check the first 16 bytes
+	   of the string for a NUL character.  In order to do an unaligned ldp
+	   safely we have to do a page cross check first.  If there is a NUL
+	   byte we calculate the length from the 2 8-byte words using
+	   conditional select to reduce branch mispredictions (it is unlikely
+	   __strlen_aarch64 will be repeatedly called on strings with the same length).
+
+	   If the string is longer than 16 bytes, we align src so don't need
+	   further page cross checks, and process 32 bytes per iteration
+	   using the fast NUL check.  If we encounter non-ASCII characters,
+	   fallback to a second loop using the full NUL check.
+
+	   If the page cross check fails, we read 16 bytes from an aligned
+	   address, remove any characters before the string, and continue
+	   in the main loop using aligned loads.  Since strings crossing a
+	   page in the first 16 bytes are rare (probability of
+	   16/MIN_PAGE_SIZE ~= 0.4%), this case does not need to be optimized.
+
+	   AArch64 systems have a minimum page size of 4k.  We don't bother
+	   checking for larger page sizes - the cost of setting up the correct
+	   page size is just not worth the extra gain from a small reduction in
+	   the cases taking the slow path.  Note that we only care about
+	   whether the first fetch, which may be misaligned, crosses a page
+	   boundary.  */
+
+ENTRY (__strlen_aarch64)
+	and	tmp1, srcin, MIN_PAGE_SIZE - 1
+	mov	zeroones, REP8_01
+	cmp	tmp1, MIN_PAGE_SIZE - 16
+	b.gt	L(page_cross)
+	ldp	data1, data2, [srcin]
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul1/2 directly.
+	   Since we expect strings to be small and early-exit,
+	   byte-swap the data now so has_null1/2 will be correct.  */
+	rev	data1, data1
+	rev	data2, data2
+#endif
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(main_loop_entry)
+
+	/* Enter with C = has_nul1 == 0.  */
+	csel	has_nul1, has_nul1, has_nul2, cc
+	mov	len, 8
+	rev	has_nul1, has_nul1
+	clz	tmp1, has_nul1
+	csel	len, xzr, len, cc
+	add	len, len, tmp1, lsr 3
+	ret
+
+	/* The inner loop processes 32 bytes per iteration and uses the fast
+	   NUL check.  If we encounter non-ASCII characters, use a second
+	   loop with the accurate NUL check.  */
+	.p2align 4
+L(main_loop_entry):
+	bic	src, srcin, 15
+	sub	src, src, 16
+L(main_loop):
+	ldp	data1, data2, [src, 32]!
+L(page_cross_entry):
+	sub	tmp1, data1, zeroones
+	sub	tmp3, data2, zeroones
+	orr	tmp2, tmp1, tmp3
+	tst	tmp2, zeroones, lsl 7
+	bne	1f
+	ldp	data1, data2, [src, 16]
+	sub	tmp1, data1, zeroones
+	sub	tmp3, data2, zeroones
+	orr	tmp2, tmp1, tmp3
+	tst	tmp2, zeroones, lsl 7
+	beq	L(main_loop)
+	add	src, src, 16
+1:
+	/* The fast check failed, so do the slower, accurate NUL check.	 */
+	orr	tmp2, data1, REP8_7f
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(nonascii_loop)
+
+	/* Enter with C = has_nul1 == 0.  */
+L(tail):
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul1/2 directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	csel	data1, data1, data2, cc
+	rev	data1, data1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	bic	has_nul1, tmp1, tmp2
+#else
+	csel	has_nul1, has_nul1, has_nul2, cc
+#endif
+	sub	len, src, srcin
+	rev	has_nul1, has_nul1
+	add	tmp2, len, 8
+	clz	tmp1, has_nul1
+	csel	len, len, tmp2, cc
+	add	len, len, tmp1, lsr 3
+	ret
+
+L(nonascii_loop):
+	ldp	data1, data2, [src, 16]!
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	bne	L(tail)
+	ldp	data1, data2, [src, 16]!
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(nonascii_loop)
+	b	L(tail)
+
+	/* Load 16 bytes from [srcin & ~15] and force the bytes that precede
+	   srcin to 0x7f, so we ignore any NUL bytes before the string.
+	   Then continue in the aligned loop.  */
+L(page_cross):
+	bic	src, srcin, 15
+	ldp	data1, data2, [src]
+	lsl	tmp1, srcin, 3
+	mov	tmp4, -1
+#ifdef __AARCH64EB__
+	/* Big-endian.	Early bytes are at MSB.	 */
+	lsr	tmp1, tmp4, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsl	tmp1, tmp4, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	orr	tmp1, tmp1, REP8_80
+	orn	data1, data1, tmp1
+	orn	tmp2, data2, tmp1
+	tst	srcin, 8
+	csel	data1, data1, tmp4, eq
+	csel	data2, data2, tmp2, eq
+	b	L(page_cross_entry)
+
+END (__strlen_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/strncmp-sve.S b/libc/AOR_v20.02/string/aarch64/strncmp-sve.S
new file mode 100644
index 0000000000000..f5d4f95fdf0fa
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strncmp-sve.S
@@ -0,0 +1,69 @@
+/*
+ * strncmp - compare two strings with limit
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__strncmp_aarch64_sve
+	.type	__strncmp_aarch64_sve, %function
+	.p2align 4
+__strncmp_aarch64_sve:
+	setffr				/* initialize FFR */
+	mov	x3, 0			/* initialize off */
+
+0:	whilelo	p0.b, x3, x2		/* while off < max */
+	b.none	9f
+
+	ldff1b	z0.b, p0/z, [x0, x3]
+	ldff1b	z1.b, p0/z, [x1, x3]
+	rdffrs	p1.b, p0/z
+	b.nlast	2f
+
+	/* First fault did not fail: the vector up to max is valid.
+	   Avoid depending on the contents of FFR beyond the branch.
+	   Increment for a whole vector, even if we've only read a partial.
+	   This is significantly cheaper than INCP, and since OFF is not
+	   used after the loop it is ok to increment OFF past MAX.  */
+	incb	x3
+	cmpeq	p1.b, p0/z, z0.b, z1.b	/* compare strings */
+	cmpne	p2.b, p0/z, z0.b, 0	/* search for ~zero */
+	nands	p2.b, p0/z, p1.b, p2.b	/* ~(eq & ~zero) -> ne | zero */
+	b.none	0b
+
+	/* Found end-of-string or inequality.  */
+1:	brkb	p2.b, p0/z, p2.b	/* find first such */
+	lasta	w0, p2, z0.b		/* extract each char */
+	lasta	w1, p2, z1.b
+	sub	x0, x0, x1		/* return comparison */
+	ret
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparison only on the valid bytes.  */
+2:	cmpeq	p2.b, p1/z, z0.b, z1.b	/* compare strings, as above */
+	cmpne	p3.b, p1/z, z0.b, 0
+	nands	p2.b, p1/z, p2.b, p3.b
+	b.any	1b
+
+	/* No inequality or zero found.  Re-init FFR, incr and loop.  */
+	setffr
+	incp	x3, p1.b
+	b	0b
+
+	/* Found end-of-count.  */
+9:	mov	x0, 0			/* return equal */
+	ret
+
+	.size	__strncmp_aarch64_sve, . - __strncmp_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strncmp.S b/libc/AOR_v20.02/string/aarch64/strncmp.S
new file mode 100644
index 0000000000000..d5a2752324e33
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strncmp.S
@@ -0,0 +1,262 @@
+/*
+ * strncmp - compare two strings
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+#include "../asmdefs.h"
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+/* Parameters and result.  */
+#define src1		x0
+#define src2		x1
+#define limit		x2
+#define result		x0
+
+/* Internal variables.  */
+#define data1		x3
+#define data1w		w3
+#define data2		x4
+#define data2w		w4
+#define has_nul		x5
+#define diff		x6
+#define syndrome	x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define zeroones	x11
+#define pos		x12
+#define limit_wd	x13
+#define mask		x14
+#define endloop		x15
+#define count		mask
+
+	.text
+	.p2align 6
+	.rep 7
+	nop	/* Pad so that the loop below fits a cache line.  */
+	.endr
+ENTRY_ALIGN (__strncmp_aarch64, 0)
+	cbz	limit, L(ret0)
+	eor	tmp1, src1, src2
+	mov	zeroones, #REP8_01
+	tst	tmp1, #7
+	and	count, src1, #7
+	b.ne	L(misaligned8)
+	cbnz	count, L(mutual_align)
+	/* Calculate the number of full and partial words -1.  */
+	sub	limit_wd, limit, #1	/* limit != 0, so no underflow.  */
+	lsr	limit_wd, limit_wd, #3	/* Convert to Dwords.  */
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+	/* Start of performance-critical section  -- one 64B cache line.  */
+L(loop_aligned):
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+L(start_realigned):
+	subs	limit_wd, limit_wd, #1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	csinv	endloop, diff, xzr, pl	/* Last Dword or differences.  */
+	bics	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	ccmp	endloop, #0, #0, eq
+	b.eq	L(loop_aligned)
+	/* End of performance-critical section  -- one 64B cache line.  */
+
+	/* Not reached the limit, must have found the end or a diff.  */
+	tbz	limit_wd, #63, L(not_limit)
+
+	/* Limit % 8 == 0 => all bytes significant.  */
+	ands	limit, limit, #7
+	b.eq	L(not_limit)
+
+	lsl	limit, limit, #3	/* Bits -> bytes.  */
+	mov	mask, #~0
+#ifdef __AARCH64EB__
+	lsr	mask, mask, limit
+#else
+	lsl	mask, mask, limit
+#endif
+	bic	data1, data1, mask
+	bic	data2, data2, mask
+
+	/* Make sure that the NUL byte is marked in the syndrome.  */
+	orr	has_nul, has_nul, mask
+
+L(not_limit):
+	orr	syndrome, diff, has_nul
+
+#ifndef	__AARCH64EB__
+	rev	syndrome, syndrome
+	rev	data1, data1
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	clz	pos, syndrome
+	rev	data2, data2
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#else
+	/* For big-endian we cannot use the trick with the syndrome value
+	   as carry-propagation can corrupt the upper bits if the trailing
+	   bytes in the string contain 0x01.  */
+	/* However, if there is no NUL byte in the dword, we can generate
+	   the result directly.  We can't just subtract the bytes as the
+	   MSB might be significant.  */
+	cbnz	has_nul, 1f
+	cmp	data1, data2
+	cset	result, ne
+	cneg	result, result, lo
+	ret
+1:
+	/* Re-compute the NUL-byte detection, using a byte-reversed value.  */
+	rev	tmp3, data1
+	sub	tmp1, tmp3, zeroones
+	orr	tmp2, tmp3, #REP8_7f
+	bic	has_nul, tmp1, tmp2
+	rev	has_nul, has_nul
+	orr	syndrome, diff, has_nul
+	clz	pos, syndrome
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#endif
+
+L(mutual_align):
+	/* Sources are mutually aligned, but are not currently at an
+	   alignment boundary.  Round down the addresses and then mask off
+	   the bytes that precede the start point.
+	   We also need to adjust the limit calculations, but without
+	   overflowing if the limit is near ULONG_MAX.  */
+	bic	src1, src1, #7
+	bic	src2, src2, #7
+	ldr	data1, [src1], #8
+	neg	tmp3, count, lsl #3	/* 64 - bits(bytes beyond align). */
+	ldr	data2, [src2], #8
+	mov	tmp2, #~0
+	sub	limit_wd, limit, #1	/* limit != 0, so no underflow.  */
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp3	/* Shift (count & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp3	/* Shift (count & 63).  */
+#endif
+	and	tmp3, limit_wd, #7
+	lsr	limit_wd, limit_wd, #3
+	/* Adjust the limit. Only low 3 bits used, so overflow irrelevant.  */
+	add	limit, limit, count
+	add	tmp3, tmp3, count
+	orr	data1, data1, tmp2
+	orr	data2, data2, tmp2
+	add	limit_wd, limit_wd, tmp3, lsr #3
+	b	L(start_realigned)
+
+	.p2align 6
+	/* Don't bother with dwords for up to 16 bytes.  */
+L(misaligned8):
+	cmp	limit, #16
+	b.hs	L(try_misaligned_words)
+
+L(byte_loop):
+	/* Perhaps we can do better than this.  */
+	ldrb	data1w, [src1], #1
+	ldrb	data2w, [src2], #1
+	subs	limit, limit, #1
+	ccmp	data1w, #1, #0, hi	/* NZCV = 0b0000.  */
+	ccmp	data1w, data2w, #0, cs	/* NZCV = 0b0000.  */
+	b.eq	L(byte_loop)
+L(done):
+	sub	result, data1, data2
+	ret
+	/* Align the SRC1 to a dword by doing a bytewise compare and then do
+	   the dword loop.  */
+L(try_misaligned_words):
+	lsr	limit_wd, limit, #3
+	cbz	count, L(do_misaligned)
+
+	neg	count, count
+	and	count, count, #7
+	sub	limit, limit, count
+	lsr	limit_wd, limit, #3
+
+L(page_end_loop):
+	ldrb	data1w, [src1], #1
+	ldrb	data2w, [src2], #1
+	cmp	data1w, #1
+	ccmp	data1w, data2w, #0, cs	/* NZCV = 0b0000.  */
+	b.ne	L(done)
+	subs	count, count, #1
+	b.hi	L(page_end_loop)
+
+L(do_misaligned):
+	/* Prepare ourselves for the next page crossing.  Unlike the aligned
+	   loop, we fetch 1 less dword because we risk crossing bounds on
+	   SRC2.  */
+	mov	count, #8
+	subs	limit_wd, limit_wd, #1
+	b.lo	L(done_loop)
+L(loop_misaligned):
+	and	tmp2, src2, #0xff8
+	eor	tmp2, tmp2, #0xff8
+	cbz	tmp2, L(page_end_loop)
+
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	bics	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	ccmp	diff, #0, #0, eq
+	b.ne	L(not_limit)
+	subs	limit_wd, limit_wd, #1
+	b.pl	L(loop_misaligned)
+
+L(done_loop):
+	/* We found a difference or a NULL before the limit was reached.  */
+	and	limit, limit, #7
+	cbz	limit, L(not_limit)
+	/* Read the last word.  */
+	sub	src1, src1, 8
+	sub	src2, src2, 8
+	ldr	data1, [src1, limit]
+	ldr	data2, [src2, limit]
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	bics	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	ccmp	diff, #0, #0, eq
+	b.ne	L(not_limit)
+
+L(ret0):
+	mov	result, #0
+	ret
+
+END ( __strncmp_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/strnlen-sve.S b/libc/AOR_v20.02/string/aarch64/strnlen-sve.S
new file mode 100644
index 0000000000000..5d3957348a0c1
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strnlen-sve.S
@@ -0,0 +1,75 @@
+/*
+ * strnlen - calculate the length of a string with limit.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__strnlen_aarch64_sve
+	.type	__strnlen_aarch64_sve, %function
+	.p2align 4
+__strnlen_aarch64_sve:
+	setffr				/* initialize FFR */
+	mov	x2, 0			/* initialize len */
+	b	1f
+
+	.p2align 4
+	/* We have off + vl <= max, and so may read the whole vector.  */
+0:	ldff1b	z0.b, p0/z, [x0, x2]
+	rdffrs	p1.b, p0/z
+	b.nlast	2f
+
+	/* First fault did not fail: the whole vector is valid.
+	   Avoid depending on the contents of FFR beyond the branch.  */
+	cmpeq	p2.b, p0/z, z0.b, 0
+	b.any	8f
+	incb	x2
+
+1:	whilelo	p0.b, x2, x1
+	b.last	0b
+
+	/* We have off + vl < max.  Test for off == max before proceeding.  */
+	b.none	9f
+
+	ldff1b	z0.b, p0/z, [x0, x2]
+	rdffrs	p1.b, p0/z
+	b.nlast	2f
+
+	/* First fault did not fail: the vector up to max is valid.
+	   Avoid depending on the contents of FFR beyond the branch.
+	   Compare for end-of-string, but there are no more bytes.  */
+	cmpeq	p2.b, p0/z, z0.b, 0
+
+	/* Found end-of-string or zero.  */
+8:	brkb	p2.b, p0/z, p2.b
+	mov	x0, x2
+	incp	x0, p2.b
+	ret
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparison only on the valid bytes.  */
+2:	cmpeq	p2.b, p1/z, z0.b, 0
+	b.any	8b
+
+	/* No inequality or zero found.  Re-init FFR, incr and loop.  */
+	setffr
+	incp	x2, p1.b
+	b	1b
+
+	/* End of count.  Return max.  */
+9:	mov	x0, x2
+	ret
+
+	.size	__strnlen_aarch64_sve, . - __strnlen_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strnlen.S b/libc/AOR_v20.02/string/aarch64/strnlen.S
new file mode 100644
index 0000000000000..72b74563a5a73
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strnlen.S
@@ -0,0 +1,156 @@
+/*
+ * strnlen - calculate the length of a string with limit.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define len		x0
+#define limit		x1
+
+/* Locals and temporaries.  */
+#define src		x2
+#define data1		x3
+#define data2		x4
+#define data2a		x5
+#define has_nul1	x6
+#define has_nul2	x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define tmp4		x11
+#define zeroones	x12
+#define pos		x13
+#define limit_wd	x14
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+	.text
+	.p2align	6
+L(start):
+	/* Pre-pad to ensure critical loop begins an icache line.  */
+	.rep 7
+	nop
+	.endr
+	/* Put this code here to avoid wasting more space with pre-padding.  */
+L(hit_limit):
+	mov	len, limit
+	ret
+
+ENTRY_ALIGN (__strnlen_aarch64, 0)
+	cbz	limit, L(hit_limit)
+	mov	zeroones, #REP8_01
+	bic	src, srcin, #15
+	ands	tmp1, srcin, #15
+	b.ne	L(misaligned)
+	/* Calculate the number of full and partial words -1.  */
+	sub	limit_wd, limit, #1	/* Limit != 0, so no underflow.  */
+	lsr	limit_wd, limit_wd, #4	/* Convert to Qwords.  */
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+	/* The inner loop deals with two Dwords at a time.  This has a
+	   slightly higher start-up cost, but we should win quite quickly,
+	   especially on cores with a high number of issue slots per
+	   cycle, as we get much better parallelism out of the operations.  */
+
+	/* Start of critial section -- keep to one 64Byte cache line.  */
+L(loop):
+	ldp	data1, data2, [src], #16
+L(realigned):
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	subs	limit_wd, limit_wd, #1
+	orr	tmp1, has_nul1, has_nul2
+	ccmp	tmp1, #0, #0, pl	/* NZCV = 0000  */
+	b.eq	L(loop)
+	/* End of critical section -- keep to one 64Byte cache line.  */
+
+	orr	tmp1, has_nul1, has_nul2
+	cbz	tmp1, L(hit_limit)	/* No null in final Qword.  */
+
+	/* We know there's a null in the final Qword.  The easiest thing
+	   to do now is work out the length of the string and return
+	   MIN (len, limit).  */
+
+	sub	len, src, srcin
+	cbz	has_nul1, L(nul_in_data2)
+#ifdef __AARCH64EB__
+	mov	data2, data1
+#endif
+	sub	len, len, #8
+	mov	has_nul2, has_nul1
+L(nul_in_data2):
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	rev	data2, data2
+	sub	tmp1, data2, zeroones
+	orr	tmp2, data2, #REP8_7f
+	bic	has_nul2, tmp1, tmp2
+#endif
+	sub	len, len, #8
+	rev	has_nul2, has_nul2
+	clz	pos, has_nul2
+	add	len, len, pos, lsr #3		/* Bits to bytes.  */
+	cmp	len, limit
+	csel	len, len, limit, ls		/* Return the lower value.  */
+	ret
+
+L(misaligned):
+	/* Deal with a partial first word.
+	   We're doing two things in parallel here;
+	   1) Calculate the number of words (but avoiding overflow if
+	      limit is near ULONG_MAX) - to do this we need to work out
+	      limit + tmp1 - 1 as a 65-bit value before shifting it;
+	   2) Load and mask the initial data words - we force the bytes
+	      before the ones we are interested in to 0xff - this ensures
+	      early bytes will not hit any zero detection.  */
+	sub	limit_wd, limit, #1
+	neg	tmp4, tmp1
+	cmp	tmp1, #8
+
+	and	tmp3, limit_wd, #15
+	lsr	limit_wd, limit_wd, #4
+	mov	tmp2, #~0
+
+	ldp	data1, data2, [src], #16
+	lsl	tmp4, tmp4, #3		/* Bytes beyond alignment -> bits.  */
+	add	tmp3, tmp3, tmp1
+
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp4	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp4	/* Shift (tmp1 & 63).  */
+#endif
+	add	limit_wd, limit_wd, tmp3, lsr #4
+
+	orr	data1, data1, tmp2
+	orr	data2a, data2, tmp2
+
+	csinv	data1, data1, xzr, le
+	csel	data2, data2, data2a, le
+	b	L(realigned)
+
+END (__strnlen_aarch64)
diff --git a/libc/AOR_v20.02/string/aarch64/strrchr-sve.S b/libc/AOR_v20.02/string/aarch64/strrchr-sve.S
new file mode 100644
index 0000000000000..0b4fcb0656319
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strrchr-sve.S
@@ -0,0 +1,86 @@
+/*
+ * strrchr - find the last of a character in a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_FEATURE_SVE
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * SVE Available.
+ */
+
+	.arch	armv8-a+sve
+	.text
+
+	.globl	__strrchr_aarch64_sve
+	.type	__strrchr_aarch64_sve, %function
+	.p2align 4
+__strrchr_aarch64_sve:
+	dup	z1.b, w1		/* replicate byte across vector */
+	setffr				/* initialize FFR */
+	ptrue	p1.b			/* all ones; loop invariant */
+	mov	x2, 0			/* no match found so far */
+	pfalse	p2.b
+
+	.p2align 4
+	/* Read a vector's worth of bytes, stopping on first fault.  */
+0:	ldff1b	z0.b, p1/z, [x0, xzr]
+	rdffrs	p0.b, p1/z
+	b.nlast	1f
+
+	/* First fault did not fail: the whole vector is valid.
+	   Avoid depending on the contents of FFR beyond the branch.  */
+	incb	x0, all			/* skip bytes this round */
+	cmpeq	p3.b, p1/z, z0.b, 0	/* search for 0 */
+	b.any	3f
+
+	cmpeq	p3.b, p1/z, z0.b, z1.b	/* search for c; no eos */
+	b.none	0b
+
+	mov	x2, x0			/* save advanced base */
+	mov	p2.b, p3.b		/* save current search */
+	b	0b
+
+	/* First fault failed: only some of the vector is valid.
+	   Perform the comparisions only on the valid bytes.  */
+1:	cmpeq	p3.b, p0/z, z0.b, 0	/* search for 0 */
+	b.any	2f
+
+	cmpeq	p3.b, p0/z, z0.b, z1.b	/* search for c; no eos */
+	mov	x3, x0
+	incp	x0, p0.b		/* skip bytes this round */
+	setffr				/* re-init FFR */
+	b.none	0b
+
+	addvl	x2, x3, 1		/* save advanced base */
+	mov	p2.b, p3.b		/* save current search */
+	b	0b
+
+	/* Found end-of-string.  */
+2:	incb	x0, all			/* advance base */
+3:	brka	p3.b, p1/z, p3.b	/* mask after first 0 */
+	cmpeq	p3.b, p3/z, z0.b, z1.b	/* search for c not after eos */
+	b.any	4f
+
+	/* No C within last vector.  Did we have one before?  */
+	cbz	x2, 5f
+	mov	x0, x2			/* restore advanced base */
+	mov	p3.b, p2.b		/* restore saved search */
+
+	/* Find the *last* match in the predicate.  This is slightly
+	   more complicated than finding the first match.  */
+4:	rev	p3.b, p3.b		/* reverse the bits */
+	brka	p3.b, p1/z, p3.b	/* find position of last match */
+	decp	x0, p3.b		/* retard pointer to last match */
+	ret
+
+	/* No C whatsoever.  Return NULL.  */
+5:	mov	x0, 0
+	ret
+
+	.size	__strrchr_aarch64_sve, . - __strrchr_aarch64_sve
+#endif
diff --git a/libc/AOR_v20.02/string/aarch64/strrchr.S b/libc/AOR_v20.02/string/aarch64/strrchr.S
new file mode 100644
index 0000000000000..48df4865064d3
--- /dev/null
+++ b/libc/AOR_v20.02/string/aarch64/strrchr.S
@@ -0,0 +1,148 @@
+/*
+ * strrchr - find last position of a character in a string.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+#include "../asmdefs.h"
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+
+#define result		x0
+
+#define src		x2
+#define	tmp1		x3
+#define wtmp2		w4
+#define tmp3		x5
+#define src_match	x6
+#define src_offset	x7
+#define const_m1	x8
+#define tmp4		x9
+#define nul_match	x10
+#define chr_match	x11
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_nul1	v3
+#define vhas_nul2	v4
+#define vhas_chr1	v5
+#define vhas_chr2	v6
+#define vrepmask_0	v7
+#define vrepmask_c	v16
+#define vend1		v17
+#define vend2		v18
+
+/* Core algorithm.
+
+   For each 32-byte hunk we calculate a 64-bit syndrome value, with
+   two bits per byte (LSB is always in bits 0 and 1, for both big
+   and little-endian systems).  For each tuple, bit 0 is set iff
+   the relevant byte matched the requested character; bit 1 is set
+   iff the relevant byte matched the NUL end of string (we trigger
+   off bit0 for the special case of looking for NUL).  Since the bits
+   in the syndrome reflect exactly the order in which things occur
+   in the original string a count_trailing_zeros() operation will
+   identify exactly which byte is causing the termination, and why.  */
+
+ENTRY (__strrchr_aarch64)
+	/* Magic constant 0x40100401 to allow us to identify which lane
+	   matches the requested byte.  Magic constant 0x80200802 used
+	   similarly for NUL termination.  */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	bic	src, srcin, #31		/* Work with aligned 32-byte hunks.  */
+	dup	vrepmask_c.4s, wtmp2
+	mov	src_offset, #0
+	ands	tmp1, srcin, #31
+	add	vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */
+	b.eq	L(aligned)
+
+	/* Input string is not 32-byte aligned.  Rather than forcing
+	   the padding bytes to a safe value, we calculate the syndrome
+	   for all the bytes, but then mask off those bits of the
+	   syndrome that are related to the padding.  */
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	neg	tmp1, tmp1
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	and	vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
+	and	vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
+	addp	vhas_nul1.16b, vhas_nul1.16b, vhas_nul2.16b	// 256->128
+	addp	vhas_chr1.16b, vhas_chr1.16b, vhas_chr2.16b	// 256->128
+	addp	vhas_nul1.16b, vhas_nul1.16b, vhas_nul1.16b	// 128->64
+	addp	vhas_chr1.16b, vhas_chr1.16b, vhas_chr1.16b	// 128->64
+	mov	nul_match, vhas_nul1.d[0]
+	lsl	tmp1, tmp1, #1
+	mov	const_m1, #~0
+	mov	chr_match, vhas_chr1.d[0]
+	lsr	tmp3, const_m1, tmp1
+
+	bic	nul_match, nul_match, tmp3	// Mask padding bits.
+	bic	chr_match, chr_match, tmp3	// Mask padding bits.
+	cbnz	nul_match, L(tail)
+
+L(loop):
+	cmp	chr_match, #0
+	csel	src_match, src, src_match, ne
+	csel	src_offset, chr_match, src_offset, ne
+L(aligned):
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	addp	vend1.16b, vhas_nul1.16b, vhas_nul2.16b	// 256->128
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
+	addp	vhas_chr1.16b, vhas_chr1.16b, vhas_chr2.16b	// 256->128
+	addp	vend1.16b, vend1.16b, vend1.16b	// 128->64
+	addp	vhas_chr1.16b, vhas_chr1.16b, vhas_chr1.16b	// 128->64
+	mov	nul_match, vend1.d[0]
+	mov	chr_match, vhas_chr1.d[0]
+	cbz	nul_match, L(loop)
+
+	and	vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
+	and	vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
+	addp	vhas_nul1.16b, vhas_nul1.16b, vhas_nul2.16b
+	addp	vhas_nul1.16b, vhas_nul1.16b, vhas_nul1.16b
+	mov	nul_match, vhas_nul1.d[0]
+
+L(tail):
+	/* Work out exactly where the string ends.  */
+	sub	tmp4, nul_match, #1
+	eor	tmp4, tmp4, nul_match
+	ands	chr_match, chr_match, tmp4
+	/* And pick the values corresponding to the last match.  */
+	csel	src_match, src, src_match, ne
+	csel	src_offset, chr_match, src_offset, ne
+
+	/* Count down from the top of the syndrome to find the last match.  */
+	clz	tmp3, src_offset
+	/* Src_match points beyond the word containing the match, so we can
+	   simply subtract half the bit-offset into the syndrome.  Because
+	   we are counting down, we need to go back one more character.  */
+	add	tmp3, tmp3, #2
+	sub	result, src_match, tmp3, lsr #1
+	/* But if the syndrome shows no match was found, then return NULL.  */
+	cmp	src_offset, #0
+	csel	result, result, xzr, ne
+
+	ret
+
+END (__strrchr_aarch64)
diff --git a/libc/AOR_v20.02/string/arm/check-arch.S b/libc/AOR_v20.02/string/arm/check-arch.S
new file mode 100644
index 0000000000000..64ffdd0eec7ab
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/check-arch.S
@@ -0,0 +1,11 @@
+/*
+ * check ARCH setting.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if !__arm__
+# error ARCH setting does not match the compiler.
+#endif
diff --git a/libc/AOR_v20.02/string/arm/memchr.S b/libc/AOR_v20.02/string/arm/memchr.S
new file mode 100644
index 0000000000000..a9bba052fb7ee
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/memchr.S
@@ -0,0 +1,134 @@
+/*
+ * memchr - scan memory for a character
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/*
+   Written by Dave Gilbert <david.gilbert@linaro.org>
+
+   This __memchr_arm routine is optimised on a Cortex-A9 and should work on
+   all ARMv7 processors.   It has a fast past for short sizes, and has
+   an optimised path for large data sets; the worst case is finding the
+   match early in a large data set.
+
+ */
+
+@ 2011-02-07 david.gilbert@linaro.org
+@    Extracted from local git a5b438d861
+@ 2011-07-14 david.gilbert@linaro.org
+@    Import endianness fix from local git ea786f1b
+@ 2011-12-07 david.gilbert@linaro.org
+@    Removed unneeded cbz from align loop
+
+	.syntax unified
+	.arch armv7-a
+
+@ this lets us check a flag in a 00/ff byte easily in either endianness
+#ifdef __ARMEB__
+#define CHARTSTMASK(c) 1<<(31-(c*8))
+#else
+#define CHARTSTMASK(c) 1<<(c*8)
+#endif
+	.text
+	.thumb
+
+@ ---------------------------------------------------------------------------
+	.thumb_func
+	.align 2
+	.p2align 4,,15
+	.global __memchr_arm
+	.type __memchr_arm,%function
+__memchr_arm:
+	@ r0 = start of memory to scan
+	@ r1 = character to look for
+	@ r2 = length
+	@ returns r0 = pointer to character or NULL if not found
+	and	r1,r1,#0xff	@ Don't think we can trust the caller to actually pass a char
+
+	cmp	r2,#16		@ If it's short don't bother with anything clever
+	blt	20f 
+
+	tst	r0, #7		@ If it's already aligned skip the next bit
+	beq	10f
+
+	@ Work up to an aligned point
+5:
+	ldrb	r3, [r0],#1
+	subs	r2, r2, #1
+	cmp	r3, r1
+	beq	50f		@ If it matches exit found
+	tst	r0, #7
+	bne	5b		@ If not aligned yet then do next byte
+	
+10:
+	@ At this point, we are aligned, we know we have at least 8 bytes to work with
+	push	{r4,r5,r6,r7}
+	orr	r1, r1, r1, lsl #8	@ expand the match word across to all bytes
+	orr	r1, r1, r1, lsl #16
+	bic	r4, r2, #7	@ Number of double words to work with
+	mvns	r7, #0		@ all F's
+	movs	r3, #0
+	
+15:
+	ldmia	r0!,{r5,r6}
+	subs	r4, r4, #8
+	eor	r5,r5, r1	@ Get it so that r5,r6 have 00's where the bytes match the target
+	eor	r6,r6, r1
+	uadd8	r5, r5, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
+	sel	r5, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+	uadd8	r6, r6, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
+	sel	r6, r5, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+	cbnz	r6, 60f
+	bne	15b		@ (Flags from the subs above) If not run out of bytes then go around again
+
+	pop	{r4,r5,r6,r7}
+	and	r1,r1,#0xff	@ Get r1 back to a single character from the expansion above
+	and	r2,r2,#7	@ Leave the count remaining as the number after the double words have been done
+ 
+20:
+	cbz	r2, 40f		@ 0 length or hit the end already then not found
+
+21:  @ Post aligned section, or just a short call
+	ldrb	r3,[r0],#1
+	subs	r2,r2,#1
+	eor	r3,r3,r1	@ r3 = 0 if match - doesn't break flags from sub
+	cbz	r3, 50f
+	bne	21b		@ on r2 flags
+
+40:
+	movs	r0,#0		@ not found
+	bx	lr
+
+50:
+	subs	r0,r0,#1	@ found
+	bx	lr
+
+60:  @ We're here because the fast path found a hit - now we have to track down exactly which word it was
+	@ r0 points to the start of the double word after the one that was tested
+	@ r5 has the 00/ff pattern for the first word, r6 has the chained value
+	cmp	r5, #0
+	itte	eq
+	moveq	r5, r6		@ the end is in the 2nd word
+	subeq	r0,r0,#3	@ Points to 2nd byte of 2nd word
+	subne	r0,r0,#7	@ or 2nd byte of 1st word
+
+	@ r0 currently points to the 3rd byte of the word containing the hit
+	tst	r5, # CHARTSTMASK(0)	@ 1st character
+	bne	61f
+	adds	r0,r0,#1
+	tst	r5, # CHARTSTMASK(1)	@ 2nd character
+	ittt	eq
+	addeq	r0,r0,#1
+	tsteq	r5, # (3<<15)		@ 2nd & 3rd character
+	@ If not the 3rd must be the last one
+	addeq	r0,r0,#1
+
+61:
+	pop	{r4,r5,r6,r7}
+	subs	r0,r0,#1
+	bx	lr
+
+	.size	__memchr_arm, . - __memchr_arm
diff --git a/libc/AOR_v20.02/string/arm/memcpy.S b/libc/AOR_v20.02/string/arm/memcpy.S
new file mode 100644
index 0000000000000..a410be5ba0f40
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/memcpy.S
@@ -0,0 +1,588 @@
+/*
+ * memcpy - copy memory area
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/*
+   This memcpy routine is optimised for Cortex-A15 cores and takes advantage
+   of VFP or NEON when built with the appropriate flags.
+
+   Assumptions:
+
+    ARMv6 (ARMv7-a if using Neon)
+    ARM state
+    Unaligned accesses
+
+ */
+
+#include "../asmdefs.h"
+
+	.syntax unified
+	/* This implementation requires ARM state.  */
+	.arm
+
+#ifdef __ARM_NEON__
+
+	.fpu	neon
+	.arch	armv7-a
+# define FRAME_SIZE	4
+# define USE_VFP
+# define USE_NEON
+
+#elif !defined (__SOFTFP__)
+
+	.arch	armv6
+	.fpu	vfpv2
+# define FRAME_SIZE	32
+# define USE_VFP
+
+#else
+	.arch	armv6
+# define FRAME_SIZE    32
+
+#endif
+
+/* Old versions of GAS incorrectly implement the NEON align semantics.  */
+#ifdef BROKEN_ASM_NEON_ALIGN
+#define ALIGN(addr, align) addr,:align
+#else
+#define ALIGN(addr, align) addr:align
+#endif
+
+#define PC_OFFSET	8	/* PC pipeline compensation.  */
+#define INSN_SIZE	4
+
+/* Call parameters.  */
+#define dstin	r0
+#define src	r1
+#define count	r2
+
+/* Locals.  */
+#define tmp1	r3
+#define dst	ip
+#define tmp2	r10
+
+#ifndef USE_NEON
+/* For bulk copies using GP registers.  */
+#define	A_l	r2		/* Call-clobbered.  */
+#define	A_h	r3		/* Call-clobbered.  */
+#define	B_l	r4
+#define	B_h	r5
+#define	C_l	r6
+#define	C_h	r7
+#define	D_l	r8
+#define	D_h	r9
+#endif
+
+/* Number of lines ahead to pre-fetch data.  If you change this the code
+   below will need adjustment to compensate.  */
+
+#define prefetch_lines	5
+
+#ifdef USE_VFP
+	.macro	cpy_line_vfp vreg, base
+	vstr	\vreg, [dst, #\base]
+	vldr	\vreg, [src, #\base]
+	vstr	d0, [dst, #\base + 8]
+	vldr	d0, [src, #\base + 8]
+	vstr	d1, [dst, #\base + 16]
+	vldr	d1, [src, #\base + 16]
+	vstr	d2, [dst, #\base + 24]
+	vldr	d2, [src, #\base + 24]
+	vstr	\vreg, [dst, #\base + 32]
+	vldr	\vreg, [src, #\base + prefetch_lines * 64 - 32]
+	vstr	d0, [dst, #\base + 40]
+	vldr	d0, [src, #\base + 40]
+	vstr	d1, [dst, #\base + 48]
+	vldr	d1, [src, #\base + 48]
+	vstr	d2, [dst, #\base + 56]
+	vldr	d2, [src, #\base + 56]
+	.endm
+
+	.macro	cpy_tail_vfp vreg, base
+	vstr	\vreg, [dst, #\base]
+	vldr	\vreg, [src, #\base]
+	vstr	d0, [dst, #\base + 8]
+	vldr	d0, [src, #\base + 8]
+	vstr	d1, [dst, #\base + 16]
+	vldr	d1, [src, #\base + 16]
+	vstr	d2, [dst, #\base + 24]
+	vldr	d2, [src, #\base + 24]
+	vstr	\vreg, [dst, #\base + 32]
+	vstr	d0, [dst, #\base + 40]
+	vldr	d0, [src, #\base + 40]
+	vstr	d1, [dst, #\base + 48]
+	vldr	d1, [src, #\base + 48]
+	vstr	d2, [dst, #\base + 56]
+	vldr	d2, [src, #\base + 56]
+	.endm
+#endif
+
+ENTRY (__memcpy_arm)
+
+	mov	dst, dstin	/* Preserve dstin, we need to return it.  */
+	cmp	count, #64
+	bge	L(cpy_not_short)
+	/* Deal with small copies quickly by dropping straight into the
+	   exit block.  */
+
+L(tail63unaligned):
+#ifdef USE_NEON
+	and	tmp1, count, #0x38
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+	vld1.8	{d0}, [src]!	/* 14 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 12 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 10 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 8 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 6 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 4 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 2 words to go.  */
+	vst1.8	{d0}, [dst]!
+
+	tst	count, #4
+	ldrne	tmp1, [src], #4
+	strne	tmp1, [dst], #4
+#else
+	/* Copy up to 15 full words of data.  May not be aligned.  */
+	/* Cannot use VFP for unaligned data.  */
+	and	tmp1, count, #0x3c
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(60 - PC_OFFSET/2 + INSN_SIZE/2)
+	/* Jump directly into the sequence below at the correct offset.  */
+	add	pc, pc, tmp1, lsl #1
+
+	ldr	tmp1, [src, #-60]	/* 15 words to go.  */
+	str	tmp1, [dst, #-60]
+
+	ldr	tmp1, [src, #-56]	/* 14 words to go.  */
+	str	tmp1, [dst, #-56]
+	ldr	tmp1, [src, #-52]
+	str	tmp1, [dst, #-52]
+
+	ldr	tmp1, [src, #-48]	/* 12 words to go.  */
+	str	tmp1, [dst, #-48]
+	ldr	tmp1, [src, #-44]
+	str	tmp1, [dst, #-44]
+
+	ldr	tmp1, [src, #-40]	/* 10 words to go.  */
+	str	tmp1, [dst, #-40]
+	ldr	tmp1, [src, #-36]
+	str	tmp1, [dst, #-36]
+
+	ldr	tmp1, [src, #-32]	/* 8 words to go.  */
+	str	tmp1, [dst, #-32]
+	ldr	tmp1, [src, #-28]
+	str	tmp1, [dst, #-28]
+
+	ldr	tmp1, [src, #-24]	/* 6 words to go.  */
+	str	tmp1, [dst, #-24]
+	ldr	tmp1, [src, #-20]
+	str	tmp1, [dst, #-20]
+
+	ldr	tmp1, [src, #-16]	/* 4 words to go.  */
+	str	tmp1, [dst, #-16]
+	ldr	tmp1, [src, #-12]
+	str	tmp1, [dst, #-12]
+
+	ldr	tmp1, [src, #-8]	/* 2 words to go.  */
+	str	tmp1, [dst, #-8]
+	ldr	tmp1, [src, #-4]
+	str	tmp1, [dst, #-4]
+#endif
+
+	lsls	count, count, #31
+	ldrhcs	tmp1, [src], #2
+	ldrbne	src, [src]		/* Src is dead, use as a scratch.  */
+	strhcs	tmp1, [dst], #2
+	strbne	src, [dst]
+	bx	lr
+
+L(cpy_not_short):
+	/* At least 64 bytes to copy, but don't know the alignment yet.  */
+	str	tmp2, [sp, #-FRAME_SIZE]!
+	and	tmp2, src, #7
+	and	tmp1, dst, #7
+	cmp	tmp1, tmp2
+	bne	L(cpy_notaligned)
+
+#ifdef USE_VFP
+	/* Magic dust alert!  Force VFP on Cortex-A9.  Experiments show
+	   that the FP pipeline is much better at streaming loads and
+	   stores.  This is outside the critical loop.  */
+	vmov.f32	s0, s0
+#endif
+
+	/* SRC and DST have the same mutual 64-bit alignment, but we may
+	   still need to pre-copy some bytes to get to natural alignment.
+	   We bring SRC and DST into full 64-bit alignment.  */
+	lsls	tmp2, dst, #29
+	beq	1f
+	rsbs	tmp2, tmp2, #0
+	sub	count, count, tmp2, lsr #29
+	ldrmi	tmp1, [src], #4
+	strmi	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #2
+	ldrhcs	tmp1, [src], #2
+	ldrbne	tmp2, [src], #1
+	strhcs	tmp1, [dst], #2
+	strbne	tmp2, [dst], #1
+
+1:
+	subs	tmp2, count, #64	/* Use tmp2 for count.  */
+	blt	L(tail63aligned)
+
+	cmp	tmp2, #512
+	bge	L(cpy_body_long)
+
+L(cpy_body_medium):			/* Count in tmp2.  */
+#ifdef USE_VFP
+1:
+	vldr	d0, [src, #0]
+	subs	tmp2, tmp2, #64
+	vldr	d1, [src, #8]
+	vstr	d0, [dst, #0]
+	vldr	d0, [src, #16]
+	vstr	d1, [dst, #8]
+	vldr	d1, [src, #24]
+	vstr	d0, [dst, #16]
+	vldr	d0, [src, #32]
+	vstr	d1, [dst, #24]
+	vldr	d1, [src, #40]
+	vstr	d0, [dst, #32]
+	vldr	d0, [src, #48]
+	vstr	d1, [dst, #40]
+	vldr	d1, [src, #56]
+	vstr	d0, [dst, #48]
+	add	src, src, #64
+	vstr	d1, [dst, #56]
+	add	dst, dst, #64
+	bge	1b
+	tst	tmp2, #0x3f
+	beq	L(done)
+
+L(tail63aligned):			/* Count in tmp2.  */
+	and	tmp1, tmp2, #0x38
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+
+	vldr	d0, [src, #-56]	/* 14 words to go.  */
+	vstr	d0, [dst, #-56]
+	vldr	d0, [src, #-48]	/* 12 words to go.  */
+	vstr	d0, [dst, #-48]
+	vldr	d0, [src, #-40]	/* 10 words to go.  */
+	vstr	d0, [dst, #-40]
+	vldr	d0, [src, #-32]	/* 8 words to go.  */
+	vstr	d0, [dst, #-32]
+	vldr	d0, [src, #-24]	/* 6 words to go.  */
+	vstr	d0, [dst, #-24]
+	vldr	d0, [src, #-16]	/* 4 words to go.  */
+	vstr	d0, [dst, #-16]
+	vldr	d0, [src, #-8]	/* 2 words to go.  */
+	vstr	d0, [dst, #-8]
+#else
+	sub	src, src, #8
+	sub	dst, dst, #8
+1:
+	ldrd	A_l, A_h, [src, #8]
+	strd	A_l, A_h, [dst, #8]
+	ldrd	A_l, A_h, [src, #16]
+	strd	A_l, A_h, [dst, #16]
+	ldrd	A_l, A_h, [src, #24]
+	strd	A_l, A_h, [dst, #24]
+	ldrd	A_l, A_h, [src, #32]
+	strd	A_l, A_h, [dst, #32]
+	ldrd	A_l, A_h, [src, #40]
+	strd	A_l, A_h, [dst, #40]
+	ldrd	A_l, A_h, [src, #48]
+	strd	A_l, A_h, [dst, #48]
+	ldrd	A_l, A_h, [src, #56]
+	strd	A_l, A_h, [dst, #56]
+	ldrd	A_l, A_h, [src, #64]!
+	strd	A_l, A_h, [dst, #64]!
+	subs	tmp2, tmp2, #64
+	bge	1b
+	tst	tmp2, #0x3f
+	bne	1f
+	ldr	tmp2,[sp], #FRAME_SIZE
+	bx	lr
+1:
+	add	src, src, #8
+	add	dst, dst, #8
+
+L(tail63aligned):			/* Count in tmp2.  */
+	/* Copy up to 7 d-words of data.  Similar to Ltail63unaligned, but
+	   we know that the src and dest are 64-bit aligned so we can use
+	   LDRD/STRD to improve efficiency.  */
+	/* TMP2 is now negative, but we don't care about that.  The bottom
+	   six bits still tell us how many bytes are left to copy.  */
+
+	and	tmp1, tmp2, #0x38
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+	ldrd	A_l, A_h, [src, #-56]	/* 14 words to go.  */
+	strd	A_l, A_h, [dst, #-56]
+	ldrd	A_l, A_h, [src, #-48]	/* 12 words to go.  */
+	strd	A_l, A_h, [dst, #-48]
+	ldrd	A_l, A_h, [src, #-40]	/* 10 words to go.  */
+	strd	A_l, A_h, [dst, #-40]
+	ldrd	A_l, A_h, [src, #-32]	/* 8 words to go.  */
+	strd	A_l, A_h, [dst, #-32]
+	ldrd	A_l, A_h, [src, #-24]	/* 6 words to go.  */
+	strd	A_l, A_h, [dst, #-24]
+	ldrd	A_l, A_h, [src, #-16]	/* 4 words to go.  */
+	strd	A_l, A_h, [dst, #-16]
+	ldrd	A_l, A_h, [src, #-8]	/* 2 words to go.  */
+	strd	A_l, A_h, [dst, #-8]
+
+#endif
+	tst	tmp2, #4
+	ldrne	tmp1, [src], #4
+	strne	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #31		/* Count (tmp2) now dead. */
+	ldrhcs	tmp1, [src], #2
+	ldrbne	tmp2, [src]
+	strhcs	tmp1, [dst], #2
+	strbne	tmp2, [dst]
+
+L(done):
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bx	lr
+
+L(cpy_body_long):			/* Count in tmp2.  */
+
+	/* Long copy.  We know that there's at least (prefetch_lines * 64)
+	   bytes to go.  */
+#ifdef USE_VFP
+	/* Don't use PLD.  Instead, read some data in advance of the current
+	   copy position into a register.  This should act like a PLD
+	   operation but we won't have to repeat the transfer.  */
+
+	vldr	d3, [src, #0]
+	vldr	d4, [src, #64]
+	vldr	d5, [src, #128]
+	vldr	d6, [src, #192]
+	vldr	d7, [src, #256]
+
+	vldr	d0, [src, #8]
+	vldr	d1, [src, #16]
+	vldr	d2, [src, #24]
+	add	src, src, #32
+
+	subs	tmp2, tmp2, #prefetch_lines * 64 * 2
+	blt	2f
+1:
+	cpy_line_vfp	d3, 0
+	cpy_line_vfp	d4, 64
+	cpy_line_vfp	d5, 128
+	add	dst, dst, #3 * 64
+	add	src, src, #3 * 64
+	cpy_line_vfp	d6, 0
+	cpy_line_vfp	d7, 64
+	add	dst, dst, #2 * 64
+	add	src, src, #2 * 64
+	subs	tmp2, tmp2, #prefetch_lines * 64
+	bge	1b
+
+2:
+	cpy_tail_vfp	d3, 0
+	cpy_tail_vfp	d4, 64
+	cpy_tail_vfp	d5, 128
+	add	src, src, #3 * 64
+	add	dst, dst, #3 * 64
+	cpy_tail_vfp	d6, 0
+	vstr	d7, [dst, #64]
+	vldr	d7, [src, #64]
+	vstr	d0, [dst, #64 + 8]
+	vldr	d0, [src, #64 + 8]
+	vstr	d1, [dst, #64 + 16]
+	vldr	d1, [src, #64 + 16]
+	vstr	d2, [dst, #64 + 24]
+	vldr	d2, [src, #64 + 24]
+	vstr	d7, [dst, #64 + 32]
+	add	src, src, #96
+	vstr	d0, [dst, #64 + 40]
+	vstr	d1, [dst, #64 + 48]
+	vstr	d2, [dst, #64 + 56]
+	add	dst, dst, #128
+	add	tmp2, tmp2, #prefetch_lines * 64
+	b	L(cpy_body_medium)
+#else
+	/* Long copy.  Use an SMS style loop to maximize the I/O
+	   bandwidth of the core.  We don't have enough spare registers
+	   to synthesise prefetching, so use PLD operations.  */
+	/* Pre-bias src and dst.  */
+	sub	src, src, #8
+	sub	dst, dst, #8
+	pld	[src, #8]
+	pld	[src, #72]
+	subs	tmp2, tmp2, #64
+	pld	[src, #136]
+	ldrd	A_l, A_h, [src, #8]
+	strd	B_l, B_h, [sp, #8]
+	ldrd	B_l, B_h, [src, #16]
+	strd	C_l, C_h, [sp, #16]
+	ldrd	C_l, C_h, [src, #24]
+	strd	D_l, D_h, [sp, #24]
+	pld	[src, #200]
+	ldrd	D_l, D_h, [src, #32]!
+	b	1f
+	.p2align	6
+2:
+	pld	[src, #232]
+	strd	A_l, A_h, [dst, #40]
+	ldrd	A_l, A_h, [src, #40]
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [src, #48]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [src, #56]
+	strd	D_l, D_h, [dst, #64]!
+	ldrd	D_l, D_h, [src, #64]!
+	subs	tmp2, tmp2, #64
+1:
+	strd	A_l, A_h, [dst, #8]
+	ldrd	A_l, A_h, [src, #8]
+	strd	B_l, B_h, [dst, #16]
+	ldrd	B_l, B_h, [src, #16]
+	strd	C_l, C_h, [dst, #24]
+	ldrd	C_l, C_h, [src, #24]
+	strd	D_l, D_h, [dst, #32]
+	ldrd	D_l, D_h, [src, #32]
+	bcs	2b
+	/* Save the remaining bytes and restore the callee-saved regs.  */
+	strd	A_l, A_h, [dst, #40]
+	add	src, src, #40
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [sp, #8]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [sp, #16]
+	strd	D_l, D_h, [dst, #64]
+	ldrd	D_l, D_h, [sp, #24]
+	add	dst, dst, #72
+	tst	tmp2, #0x3f
+	bne	L(tail63aligned)
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bx	lr
+#endif
+
+L(cpy_notaligned):
+	pld	[src]
+	pld	[src, #64]
+	/* There's at least 64 bytes to copy, but there is no mutual
+	   alignment.  */
+	/* Bring DST to 64-bit alignment.  */
+	lsls	tmp2, dst, #29
+	pld	[src, #(2 * 64)]
+	beq	1f
+	rsbs	tmp2, tmp2, #0
+	sub	count, count, tmp2, lsr #29
+	ldrmi	tmp1, [src], #4
+	strmi	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #2
+	ldrbne	tmp1, [src], #1
+	ldrhcs	tmp2, [src], #2
+	strbne	tmp1, [dst], #1
+	strhcs	tmp2, [dst], #2
+1:
+	pld	[src, #(3 * 64)]
+	subs	count, count, #64
+	ldrmi	tmp2, [sp], #FRAME_SIZE
+	bmi	L(tail63unaligned)
+	pld	[src, #(4 * 64)]
+
+#ifdef USE_NEON
+	vld1.8	{d0-d3}, [src]!
+	vld1.8	{d4-d7}, [src]!
+	subs	count, count, #64
+	bmi	2f
+1:
+	pld	[src, #(4 * 64)]
+	vst1.8	{d0-d3}, [ALIGN (dst, 64)]!
+	vld1.8	{d0-d3}, [src]!
+	vst1.8	{d4-d7}, [ALIGN (dst, 64)]!
+	vld1.8	{d4-d7}, [src]!
+	subs	count, count, #64
+	bpl	1b
+2:
+	vst1.8	{d0-d3}, [ALIGN (dst, 64)]!
+	vst1.8	{d4-d7}, [ALIGN (dst, 64)]!
+	ands	count, count, #0x3f
+#else
+	/* Use an SMS style loop to maximize the I/O bandwidth.  */
+	sub	src, src, #4
+	sub	dst, dst, #8
+	subs	tmp2, count, #64	/* Use tmp2 for count.  */
+	ldr	A_l, [src, #4]
+	ldr	A_h, [src, #8]
+	strd	B_l, B_h, [sp, #8]
+	ldr	B_l, [src, #12]
+	ldr	B_h, [src, #16]
+	strd	C_l, C_h, [sp, #16]
+	ldr	C_l, [src, #20]
+	ldr	C_h, [src, #24]
+	strd	D_l, D_h, [sp, #24]
+	ldr	D_l, [src, #28]
+	ldr	D_h, [src, #32]!
+	b	1f
+	.p2align	6
+2:
+	pld	[src, #(5 * 64) - (32 - 4)]
+	strd	A_l, A_h, [dst, #40]
+	ldr	A_l, [src, #36]
+	ldr	A_h, [src, #40]
+	strd	B_l, B_h, [dst, #48]
+	ldr	B_l, [src, #44]
+	ldr	B_h, [src, #48]
+	strd	C_l, C_h, [dst, #56]
+	ldr	C_l, [src, #52]
+	ldr	C_h, [src, #56]
+	strd	D_l, D_h, [dst, #64]!
+	ldr	D_l, [src, #60]
+	ldr	D_h, [src, #64]!
+	subs	tmp2, tmp2, #64
+1:
+	strd	A_l, A_h, [dst, #8]
+	ldr	A_l, [src, #4]
+	ldr	A_h, [src, #8]
+	strd	B_l, B_h, [dst, #16]
+	ldr	B_l, [src, #12]
+	ldr	B_h, [src, #16]
+	strd	C_l, C_h, [dst, #24]
+	ldr	C_l, [src, #20]
+	ldr	C_h, [src, #24]
+	strd	D_l, D_h, [dst, #32]
+	ldr	D_l, [src, #28]
+	ldr	D_h, [src, #32]
+	bcs	2b
+
+	/* Save the remaining bytes and restore the callee-saved regs.  */
+	strd	A_l, A_h, [dst, #40]
+	add	src, src, #36
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [sp, #8]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [sp, #16]
+	strd	D_l, D_h, [dst, #64]
+	ldrd	D_l, D_h, [sp, #24]
+	add	dst, dst, #72
+	ands	count, tmp2, #0x3f
+#endif
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bne	L(tail63unaligned)
+	bx	lr
+
+END (__memcpy_arm)
diff --git a/libc/AOR_v20.02/string/arm/memset.S b/libc/AOR_v20.02/string/arm/memset.S
new file mode 100644
index 0000000000000..a3185b957f2fd
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/memset.S
@@ -0,0 +1,100 @@
+/*
+ * memset - fill memory with a constant
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+/*
+   Written by Dave Gilbert <david.gilbert@linaro.org>
+
+   This memset routine is optimised on a Cortex-A9 and should work on
+   all ARMv7 processors.
+
+ */
+
+	.syntax unified
+	.arch armv7-a
+
+@ 2011-08-30 david.gilbert@linaro.org
+@    Extracted from local git 2f11b436
+
+@ this lets us check a flag in a 00/ff byte easily in either endianness
+#ifdef __ARMEB__
+#define CHARTSTMASK(c) 1<<(31-(c*8))
+#else
+#define CHARTSTMASK(c) 1<<(c*8)
+#endif
+	.text
+	.thumb
+
+@ ---------------------------------------------------------------------------
+	.thumb_func
+	.align 2
+	.p2align 4,,15
+	.global __memset_arm
+	.type __memset_arm,%function
+__memset_arm:
+	@ r0 = address
+	@ r1 = character
+	@ r2 = count
+	@ returns original address in r0
+
+	mov	r3, r0		@ Leave r0 alone
+	cbz	r2, 10f		@ Exit if 0 length
+
+	tst	r0, #7
+	beq	2f		@ Already aligned
+
+	@ Ok, so we're misaligned here
+1:
+	strb	r1, [r3], #1
+	subs	r2,r2,#1
+	tst	r3, #7
+	cbz	r2, 10f		@ Exit if we hit the end
+	bne	1b		@ go round again if still misaligned
+
+2:
+	@ OK, so we're aligned
+	push	{r4,r5,r6,r7}
+	bics	r4, r2, #15	@ if less than 16 bytes then need to finish it off
+	beq	5f
+
+3:
+	@ POSIX says that ch is cast to an unsigned char.  A uxtb is one
+	@ byte and takes two cycles, where an AND is four bytes but one
+	@ cycle.
+	and	r1, #0xFF
+	orr	r1, r1, r1, lsl#8	@ Same character into all bytes
+	orr	r1, r1, r1, lsl#16
+	mov	r5,r1
+	mov	r6,r1
+	mov	r7,r1
+
+4:
+	subs	r4,r4,#16
+	stmia	r3!,{r1,r5,r6,r7}
+	bne	4b
+	and	r2,r2,#15
+
+	@ At this point we're still aligned and we have upto align-1 bytes left to right
+	@ we can avoid some of the byte-at-a time now by testing for some big chunks
+	tst	r2,#8
+	itt	ne
+	subne	r2,r2,#8
+	stmiane	r3!,{r1,r5}
+
+5:
+	pop	{r4,r5,r6,r7}
+	cbz	r2, 10f
+
+	@ Got to do any last < alignment bytes
+6:
+	subs	r2,r2,#1
+	strb	r1,[r3],#1
+	bne	6b
+
+10:
+	bx	lr		@ goodbye
+	.size	__memset_arm, . - __memset_arm
diff --git a/libc/AOR_v20.02/string/arm/strcmp-armv6m.S b/libc/AOR_v20.02/string/arm/strcmp-armv6m.S
new file mode 100644
index 0000000000000..462233d06004c
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/strcmp-armv6m.S
@@ -0,0 +1,118 @@
+/*
+ * strcmp for ARMv6-M (optimized for performance, not size)
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_ARCH == 6 && __ARM_ARCH_6M__ >= 1
+
+	.thumb_func
+	.syntax unified
+	.arch	armv6-m
+
+	.macro DoSub n, label
+	subs	r0, r0, r1
+#ifdef __ARM_BIG_ENDIAN
+	lsrs	r1, r4, \n
+#else
+	lsls	r1, r4, \n
+#endif
+	orrs	r1, r0
+	bne	\label
+	.endm
+
+	.macro Byte_Test n, label
+	lsrs	r0, r2, \n
+	lsrs	r1, r3, \n
+	DoSub	\n, \label
+	.endm
+
+ENTRY_ALIGN (__strcmp_armv6m, 4)
+	mov	r2, r0
+	push	{r4, r5, r6, lr}
+	orrs	r2, r1
+	lsls	r2, r2, #30
+	bne	6f
+	ldr	r5, =0x01010101
+	lsls	r6, r5, #7
+1:
+	ldmia	r0!, {r2}
+	ldmia	r1!, {r3}
+	subs	r4, r2, r5
+	bics	r4, r2
+	ands	r4, r6
+	beq	3f
+
+#ifdef __ARM_BIG_ENDIAN
+	Byte_Test #24, 4f
+	Byte_Test #16, 4f
+	Byte_Test #8, 4f
+
+	b       7f
+3:
+	cmp     r2, r3
+	beq     1b
+	cmp     r2, r3
+#else
+	uxtb    r0, r2
+	uxtb    r1, r3
+	DoSub   #24, 2f
+
+	uxth    r0, r2
+	uxth    r1, r3
+	DoSub   #16, 2f
+
+	lsls    r0, r2, #8
+	lsls    r1, r3, #8
+	lsrs    r0, r0, #8
+	lsrs    r1, r1, #8
+	DoSub   #8, 2f
+
+	lsrs    r0, r2, #24
+	lsrs    r1, r3, #24
+	subs    r0, r0, r1
+2:
+	pop     {r4, r5, r6, pc}
+
+3:
+	cmp     r2, r3
+	beq     1b
+	rev     r0, r2
+	rev     r1, r3
+	cmp     r0, r1
+#endif
+
+	bls	5f
+	movs	r0, #1
+4:
+	pop	{r4, r5, r6, pc}
+5:
+	movs	r0, #0
+	mvns	r0, r0
+	pop	{r4, r5, r6, pc}
+6:
+	ldrb	r2, [r0, #0]
+	ldrb	r3, [r1, #0]
+	adds	r0, #1
+	adds	r1, #1
+	cmp	r2, #0
+	beq	7f
+	cmp	r2, r3
+	bne	7f
+	ldrb	r2, [r0, #0]
+	ldrb	r3, [r1, #0]
+	adds	r0, #1
+	adds	r1, #1
+	cmp	r2, #0
+	beq	7f
+	cmp	r2, r3
+	beq	6b
+7:
+	subs	r0, r2, r3
+	pop	{r4, r5, r6, pc}
+
+END (__strcmp_armv6m)
+
+#endif /* __ARM_ARCH == 6 && __ARM_ARCH_6M__ >= 1  */
diff --git a/libc/AOR_v20.02/string/arm/strcmp.S b/libc/AOR_v20.02/string/arm/strcmp.S
new file mode 100644
index 0000000000000..db7cc0549fe28
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/strcmp.S
@@ -0,0 +1,477 @@
+/*
+ * strcmp for ARMv7
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_ARCH >= 7 && __ARM_ARCH_ISA_ARM >= 1
+
+/* Implementation of strcmp for ARMv7 when DSP instructions are
+   available.  Use ldrd to support wider loads, provided the data
+   is sufficiently aligned.  Use saturating arithmetic to optimize
+   the compares.  */
+
+#include "../asmdefs.h"
+
+/* Build Options:
+   STRCMP_NO_PRECHECK: Don't run a quick pre-check of the first
+   byte in the string.  If comparing completely random strings
+   the pre-check will save time, since there is a very high
+   probability of a mismatch in the first character: we save
+   significant overhead if this is the common case.  However,
+   if strings are likely to be identical (eg because we're
+   verifying a hit in a hash table), then this check is largely
+   redundant.  */
+
+#define STRCMP_NO_PRECHECK	0
+
+	/* This version uses Thumb-2 code.  */
+	.thumb
+	.syntax unified
+
+#ifdef __ARM_BIG_ENDIAN
+#define S2LO lsl
+#define S2LOEQ lsleq
+#define S2HI lsr
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#define BYTE0_OFFSET 24
+#define BYTE1_OFFSET 16
+#define BYTE2_OFFSET 8
+#define BYTE3_OFFSET 0
+#else /* not  __ARM_BIG_ENDIAN */
+#define S2LO lsr
+#define S2LOEQ lsreq
+#define S2HI lsl
+#define BYTE0_OFFSET 0
+#define BYTE1_OFFSET 8
+#define BYTE2_OFFSET 16
+#define BYTE3_OFFSET 24
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif /* not  __ARM_BIG_ENDIAN */
+
+/* Parameters and result.  */
+#define src1		r0
+#define src2		r1
+#define result		r0	/* Overlaps src1.  */
+
+/* Internal variables.  */
+#define tmp1		r4
+#define tmp2		r5
+#define const_m1	r12
+
+/* Additional internal variables for 64-bit aligned data.  */
+#define data1a		r2
+#define data1b		r3
+#define data2a		r6
+#define data2b		r7
+#define syndrome_a	tmp1
+#define syndrome_b	tmp2
+
+/* Additional internal variables for 32-bit aligned data.  */
+#define data1		r2
+#define data2		r3
+#define syndrome	tmp2
+
+
+	/* Macro to compute and return the result value for word-aligned
+	   cases.  */
+	.macro strcmp_epilogue_aligned synd d1 d2 restore_r6
+#ifdef __ARM_BIG_ENDIAN
+	/* If data1 contains a zero byte, then syndrome will contain a 1 in
+	   bit 7 of that byte.  Otherwise, the highest set bit in the
+	   syndrome will highlight the first different bit.  It is therefore
+	   sufficient to extract the eight bits starting with the syndrome
+	   bit.  */
+	clz	tmp1, \synd
+	lsl	r1, \d2, tmp1
+	.if \restore_r6
+	ldrd	r6, r7, [sp, #8]
+	.endif
+	.cfi_restore 6
+	.cfi_restore 7
+	lsl	\d1, \d1, tmp1
+	.cfi_remember_state
+	lsr	result, \d1, #24
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	sub	result, result, r1, lsr #24
+	bx	lr
+#else
+	/* To use the big-endian trick we'd have to reverse all three words.
+	   that's slower than this approach.  */
+	rev	\synd, \synd
+	clz	tmp1, \synd
+	bic	tmp1, tmp1, #7
+	lsr	r1, \d2, tmp1
+	.cfi_remember_state
+	.if \restore_r6
+	ldrd	r6, r7, [sp, #8]
+	.endif
+	.cfi_restore 6
+	.cfi_restore 7
+	lsr	\d1, \d1, tmp1
+	and	result, \d1, #255
+	and	r1, r1, #255
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	sub	result, result, r1
+
+	bx	lr
+#endif
+	.endm
+
+	.text
+	.p2align	5
+L(strcmp_start_addr):
+#if STRCMP_NO_PRECHECK == 0
+L(fastpath_exit):
+	sub	r0, r2, r3
+	bx	lr
+	nop
+#endif
+ENTRY_ALIGN (__strcmp_arm, 0)
+#if STRCMP_NO_PRECHECK == 0
+	ldrb	r2, [src1]
+	ldrb	r3, [src2]
+	cmp	r2, #1
+	it	cs
+	cmpcs	r2, r3
+	bne	L(fastpath_exit)
+#endif
+	strd	r4, r5, [sp, #-16]!
+	.cfi_def_cfa_offset 16
+	.cfi_offset 4, -16
+	.cfi_offset 5, -12
+	orr	tmp1, src1, src2
+	strd	r6, r7, [sp, #8]
+	.cfi_offset 6, -8
+	.cfi_offset 7, -4
+	mvn	const_m1, #0
+	lsl	r2, tmp1, #29
+	cbz	r2, L(loop_aligned8)
+
+L(not_aligned):
+	eor	tmp1, src1, src2
+	tst	tmp1, #7
+	bne	L(misaligned8)
+
+	/* Deal with mutual misalignment by aligning downwards and then
+	   masking off the unwanted loaded data to prevent a difference.  */
+	and	tmp1, src1, #7
+	bic	src1, src1, #7
+	and	tmp2, tmp1, #3
+	bic	src2, src2, #7
+	lsl	tmp2, tmp2, #3	/* Bytes -> bits.  */
+	ldrd	data1a, data1b, [src1], #16
+	tst	tmp1, #4
+	ldrd	data2a, data2b, [src2], #16
+	/* In thumb code we can't use MVN with a register shift, but
+	   we do have ORN.  */
+	S2HI	tmp1, const_m1, tmp2
+	orn	data1a, data1a, tmp1
+	orn	data2a, data2a, tmp1
+	beq	L(start_realigned8)
+	orn	data1b, data1b, tmp1
+	mov	data1a, const_m1
+	orn	data2b, data2b, tmp1
+	mov	data2a, const_m1
+	b	L(start_realigned8)
+
+	/* Unwind the inner loop by a factor of 2, giving 16 bytes per
+	   pass.  */
+	.p2align 5,,12  /* Don't start in the tail bytes of a cache line.  */
+	.p2align 2	/* Always word aligned.  */
+L(loop_aligned8):
+	ldrd	data1a, data1b, [src1], #16
+	ldrd	data2a, data2b, [src2], #16
+L(start_realigned8):
+	uadd8	syndrome_b, data1a, const_m1	/* Only want GE bits,  */
+	eor	syndrome_a, data1a, data2a
+	sel	syndrome_a, syndrome_a, const_m1
+	cbnz	syndrome_a, L(diff_in_a)
+	uadd8	syndrome_b, data1b, const_m1	/* Only want GE bits.  */
+	eor	syndrome_b, data1b, data2b
+	sel	syndrome_b, syndrome_b, const_m1
+	cbnz	syndrome_b, L(diff_in_b)
+
+	ldrd	data1a, data1b, [src1, #-8]
+	ldrd	data2a, data2b, [src2, #-8]
+	uadd8	syndrome_b, data1a, const_m1	/* Only want GE bits,  */
+	eor	syndrome_a, data1a, data2a
+	sel	syndrome_a, syndrome_a, const_m1
+	uadd8	syndrome_b, data1b, const_m1	/* Only want GE bits.  */
+	eor	syndrome_b, data1b, data2b
+	sel	syndrome_b, syndrome_b, const_m1
+	/* Can't use CBZ for backwards branch.  */
+	orrs	syndrome_b, syndrome_b, syndrome_a /* Only need if s_a == 0 */
+	beq	L(loop_aligned8)
+
+L(diff_found):
+	cbnz	syndrome_a, L(diff_in_a)
+
+L(diff_in_b):
+	strcmp_epilogue_aligned syndrome_b, data1b, data2b 1
+
+L(diff_in_a):
+	.cfi_restore_state
+	strcmp_epilogue_aligned syndrome_a, data1a, data2a 1
+
+	.cfi_restore_state
+L(misaligned8):
+	tst	tmp1, #3
+	bne	L(misaligned4)
+	ands	tmp1, src1, #3
+	bne	L(mutual_align4)
+
+	/* Unrolled by a factor of 2, to reduce the number of post-increment
+	   operations.  */
+L(loop_aligned4):
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+L(start_realigned4):
+	uadd8	syndrome, data1, const_m1	/* Only need GE bits.  */
+	eor	syndrome, data1, data2
+	sel	syndrome, syndrome, const_m1
+	cbnz	syndrome, L(aligned4_done)
+	ldr	data1, [src1, #-4]
+	ldr	data2, [src2, #-4]
+	uadd8	syndrome, data1, const_m1
+	eor	syndrome, data1, data2
+	sel	syndrome, syndrome, const_m1
+	cmp	syndrome, #0
+	beq	L(loop_aligned4)
+
+L(aligned4_done):
+	strcmp_epilogue_aligned syndrome, data1, data2, 0
+
+L(mutual_align4):
+	.cfi_restore_state
+	/* Deal with mutual misalignment by aligning downwards and then
+	   masking off the unwanted loaded data to prevent a difference.  */
+	lsl	tmp1, tmp1, #3	/* Bytes -> bits.  */
+	bic	src1, src1, #3
+	ldr	data1, [src1], #8
+	bic	src2, src2, #3
+	ldr	data2, [src2], #8
+
+	/* In thumb code we can't use MVN with a register shift, but
+	   we do have ORN.  */
+	S2HI	tmp1, const_m1, tmp1
+	orn	data1, data1, tmp1
+	orn	data2, data2, tmp1
+	b	L(start_realigned4)
+
+L(misaligned4):
+	ands	tmp1, src1, #3
+	beq	L(src1_aligned)
+	sub	src2, src2, tmp1
+	bic	src1, src1, #3
+	lsls	tmp1, tmp1, #31
+	ldr	data1, [src1], #4
+	beq	L(aligned_m2)
+	bcs	L(aligned_m1)
+
+#if STRCMP_NO_PRECHECK == 1
+	ldrb	data2, [src2, #1]
+	uxtb	tmp1, data1, ror #BYTE1_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	L(misaligned_exit)
+	cbz	data2, L(misaligned_exit)
+
+L(aligned_m2):
+	ldrb	data2, [src2, #2]
+	uxtb	tmp1, data1, ror #BYTE2_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	L(misaligned_exit)
+	cbz	data2, L(misaligned_exit)
+
+L(aligned_m1):
+	ldrb	data2, [src2, #3]
+	uxtb	tmp1, data1, ror #BYTE3_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	L(misaligned_exit)
+	add	src2, src2, #4
+	cbnz	data2, L(src1_aligned)
+#else  /* STRCMP_NO_PRECHECK */
+	/* If we've done the pre-check, then we don't need to check the
+	   first byte again here.  */
+	ldrb	data2, [src2, #2]
+	uxtb	tmp1, data1, ror #BYTE2_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	L(misaligned_exit)
+	cbz	data2, L(misaligned_exit)
+
+L(aligned_m2):
+	ldrb	data2, [src2, #3]
+	uxtb	tmp1, data1, ror #BYTE3_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	L(misaligned_exit)
+	cbnz	data2, L(aligned_m1)
+#endif
+
+L(misaligned_exit):
+	.cfi_remember_state
+	mov	result, tmp1
+	ldr	r4, [sp], #16
+	.cfi_restore 4
+	bx	lr
+
+#if STRCMP_NO_PRECHECK == 0
+L(aligned_m1):
+	add	src2, src2, #4
+#endif
+L(src1_aligned):
+	.cfi_restore_state
+	/* src1 is word aligned, but src2 has no common alignment
+	   with it.  */
+	ldr	data1, [src1], #4
+	lsls	tmp1, src2, #31		/* C=src2[1], Z=src2[0].  */
+
+	bic	src2, src2, #3
+	ldr	data2, [src2], #4
+	bhi	L(overlap1)		/* C=1, Z=0 => src2[1:0] = 0b11.  */
+	bcs	L(overlap2)		/* C=1, Z=1 => src2[1:0] = 0b10.  */
+
+	/* (overlap3) C=0, Z=0 => src2[1:0] = 0b01.  */
+L(overlap3):
+	bic	tmp1, data1, #MSB
+	uadd8	syndrome, data1, const_m1
+	eors	syndrome, tmp1, data2, S2LO #8
+	sel	syndrome, syndrome, const_m1
+	bne	4f
+	cbnz	syndrome, 5f
+	ldr	data2, [src2], #4
+	eor	tmp1, tmp1, data1
+	cmp	tmp1, data2, S2HI #24
+	bne	6f
+	ldr	data1, [src1], #4
+	b	L(overlap3)
+4:
+	S2LO	data2, data2, #8
+	b	L(strcmp_tail)
+
+5:
+	bics	syndrome, syndrome, #MSB
+	bne	L(strcmp_done_equal)
+
+	/* We can only get here if the MSB of data1 contains 0, so
+	   fast-path the exit.  */
+	ldrb	result, [src2]
+	.cfi_remember_state
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	/* R6/7 Not used in this sequence.  */
+	.cfi_restore 6
+	.cfi_restore 7
+	neg	result, result
+	bx	lr
+
+6:
+	.cfi_restore_state
+	S2LO	data1, data1, #24
+	and	data2, data2, #LSB
+	b	L(strcmp_tail)
+
+	.p2align 5,,12	/* Ensure at least 3 instructions in cache line.  */
+L(overlap2):
+	and	tmp1, data1, const_m1, S2LO #16
+	uadd8	syndrome, data1, const_m1
+	eors	syndrome, tmp1, data2, S2LO #16
+	sel	syndrome, syndrome, const_m1
+	bne	4f
+	cbnz	syndrome, 5f
+	ldr	data2, [src2], #4
+	eor	tmp1, tmp1, data1
+	cmp	tmp1, data2, S2HI #16
+	bne	6f
+	ldr	data1, [src1], #4
+	b	L(overlap2)
+4:
+	S2LO	data2, data2, #16
+	b	L(strcmp_tail)
+5:
+	ands	syndrome, syndrome, const_m1, S2LO #16
+	bne	L(strcmp_done_equal)
+
+	ldrh	data2, [src2]
+	S2LO	data1, data1, #16
+#ifdef __ARM_BIG_ENDIAN
+	lsl	data2, data2, #16
+#endif
+	b	L(strcmp_tail)
+
+6:
+	S2LO	data1, data1, #16
+	and	data2, data2, const_m1, S2LO #16
+	b	L(strcmp_tail)
+
+	.p2align 5,,12	/* Ensure at least 3 instructions in cache line.  */
+L(overlap1):
+	and	tmp1, data1, #LSB
+	uadd8	syndrome, data1, const_m1
+	eors	syndrome, tmp1, data2, S2LO #24
+	sel	syndrome, syndrome, const_m1
+	bne	4f
+	cbnz	syndrome, 5f
+	ldr	data2, [src2], #4
+	eor	tmp1, tmp1, data1
+	cmp	tmp1, data2, S2HI #8
+	bne	6f
+	ldr	data1, [src1], #4
+	b	L(overlap1)
+4:
+	S2LO	data2, data2, #24
+	b	L(strcmp_tail)
+5:
+	tst	syndrome, #LSB
+	bne	L(strcmp_done_equal)
+	ldr	data2, [src2]
+6:
+	S2LO	data1, data1, #8
+	bic	data2, data2, #MSB
+	b	L(strcmp_tail)
+
+L(strcmp_done_equal):
+	mov	result, #0
+	.cfi_remember_state
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	/* R6/7 not used in this sequence.  */
+	.cfi_restore 6
+	.cfi_restore 7
+	bx	lr
+
+L(strcmp_tail):
+	.cfi_restore_state
+#ifndef __ARM_BIG_ENDIAN
+	rev	data1, data1
+	rev	data2, data2
+	/* Now everything looks big-endian...  */
+#endif
+	uadd8	tmp1, data1, const_m1
+	eor	tmp1, data1, data2
+	sel	syndrome, tmp1, const_m1
+	clz	tmp1, syndrome
+	lsl	data1, data1, tmp1
+	lsl	data2, data2, tmp1
+	lsr	result, data1, #24
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	/* R6/7 not used in this sequence.  */
+	.cfi_restore 6
+	.cfi_restore 7
+	sub	result, result, data2, lsr #24
+	bx	lr
+
+END (__strcmp_arm)
+
+#endif /* __ARM_ARCH >= 7 && __ARM_ARCH_ISA_ARM >= 1  */
diff --git a/libc/AOR_v20.02/string/arm/strcpy.c b/libc/AOR_v20.02/string/arm/strcpy.c
new file mode 100644
index 0000000000000..ce472ced2c45d
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/strcpy.c
@@ -0,0 +1,134 @@
+/*
+ * strcpy
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if defined (__thumb2__) && !defined (__thumb__)
+
+/* For GLIBC:
+#include <string.h>
+#include <memcopy.h>
+
+#undef strcmp
+*/
+
+#ifdef __thumb2__
+#define magic1(REG) "#0x01010101"
+#define magic2(REG) "#0x80808080"
+#else
+#define magic1(REG) #REG
+#define magic2(REG) #REG ", lsl #7"
+#endif
+
+char* __attribute__((naked))
+__strcpy_arm (char* dst, const char* src)
+{
+  __asm__ (
+       "pld	[r1, #0]\n\t"
+       "eor	r2, r0, r1\n\t"
+       "mov	ip, r0\n\t"
+       "tst	r2, #3\n\t"
+       "bne	4f\n\t"
+       "tst	r1, #3\n\t"
+       "bne	3f\n"
+  "5:\n\t"
+# ifndef __thumb2__
+       "str	r5, [sp, #-4]!\n\t"
+       "mov	r5, #0x01\n\t"
+       "orr	r5, r5, r5, lsl #8\n\t"
+       "orr	r5, r5, r5, lsl #16\n\t"
+# endif
+
+       "str	r4, [sp, #-4]!\n\t"
+       "tst	r1, #4\n\t"
+       "ldr	r3, [r1], #4\n\t"
+       "beq	2f\n\t"
+       "sub	r2, r3, "magic1(r5)"\n\t"
+       "bics	r2, r2, r3\n\t"
+       "tst	r2, "magic2(r5)"\n\t"
+       "itt	eq\n\t"
+       "streq	r3, [ip], #4\n\t"
+       "ldreq	r3, [r1], #4\n"
+       "bne	1f\n\t"
+       /* Inner loop.  We now know that r1 is 64-bit aligned, so we
+	  can safely fetch up to two words.  This allows us to avoid
+	  load stalls.  */
+       ".p2align 2\n"
+  "2:\n\t"
+       "pld	[r1, #8]\n\t"
+       "ldr	r4, [r1], #4\n\t"
+       "sub	r2, r3, "magic1(r5)"\n\t"
+       "bics	r2, r2, r3\n\t"
+       "tst	r2, "magic2(r5)"\n\t"
+       "sub	r2, r4, "magic1(r5)"\n\t"
+       "bne	1f\n\t"
+       "str	r3, [ip], #4\n\t"
+       "bics	r2, r2, r4\n\t"
+       "tst	r2, "magic2(r5)"\n\t"
+       "itt	eq\n\t"
+       "ldreq	r3, [r1], #4\n\t"
+       "streq	r4, [ip], #4\n\t"
+       "beq	2b\n\t"
+       "mov	r3, r4\n"
+  "1:\n\t"
+# ifdef __ARMEB__
+       "rors	r3, r3, #24\n\t"
+# endif
+       "strb	r3, [ip], #1\n\t"
+       "tst	r3, #0xff\n\t"
+# ifdef __ARMEL__
+       "ror	r3, r3, #8\n\t"
+# endif
+       "bne	1b\n\t"
+       "ldr	r4, [sp], #4\n\t"
+# ifndef __thumb2__
+       "ldr	r5, [sp], #4\n\t"
+# endif
+       "BX LR\n"
+
+       /* Strings have the same offset from word alignment, but it's
+	  not zero.  */
+  "3:\n\t"
+       "tst	r1, #1\n\t"
+       "beq	1f\n\t"
+       "ldrb	r2, [r1], #1\n\t"
+       "strb	r2, [ip], #1\n\t"
+       "cmp	r2, #0\n\t"
+       "it	eq\n"
+       "BXEQ LR\n"
+  "1:\n\t"
+       "tst	r1, #2\n\t"
+       "beq	5b\n\t"
+       "ldrh	r2, [r1], #2\n\t"
+# ifdef __ARMEB__
+       "tst	r2, #0xff00\n\t"
+       "iteet	ne\n\t"
+       "strneh	r2, [ip], #2\n\t"
+       "lsreq	r2, r2, #8\n\t"
+       "streqb	r2, [ip]\n\t"
+       "tstne	r2, #0xff\n\t"
+# else
+       "tst	r2, #0xff\n\t"
+       "itet	ne\n\t"
+       "strneh	r2, [ip], #2\n\t"
+       "streqb	r2, [ip]\n\t"
+       "tstne	r2, #0xff00\n\t"
+# endif
+       "bne	5b\n\t"
+       "BX LR\n"
+
+       /* src and dst do not have a common word-alignement.  Fall back to
+	  byte copying.  */
+  "4:\n\t"
+       "ldrb	r2, [r1], #1\n\t"
+       "strb	r2, [ip], #1\n\t"
+       "cmp	r2, #0\n\t"
+       "bne	4b\n\t"
+       "BX LR");
+}
+/* For GLIBC: libc_hidden_builtin_def (strcpy) */
+
+#endif /* defined (__thumb2__) && !defined (__thumb__)  */
diff --git a/libc/AOR_v20.02/string/arm/strlen-armv6t2.S b/libc/AOR_v20.02/string/arm/strlen-armv6t2.S
new file mode 100644
index 0000000000000..e368e62336140
--- /dev/null
+++ b/libc/AOR_v20.02/string/arm/strlen-armv6t2.S
@@ -0,0 +1,125 @@
+/*
+ * strlen - calculate the length of a string
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if __ARM_ARCH >= 6 && __ARM_ARCH_ISA_THUMB == 2
+
+/*
+   Assumes:
+   ARMv6T2, AArch32
+
+ */
+
+#include "../asmdefs.h"
+
+#ifdef __ARMEB__
+#define S2LO		lsl
+#define S2HI		lsr
+#else
+#define S2LO		lsr
+#define S2HI		lsl
+#endif
+
+	/* This code requires Thumb.  */
+	.thumb
+	.syntax unified
+
+/* Parameters and result.  */
+#define srcin		r0
+#define result		r0
+
+/* Internal variables.  */
+#define src		r1
+#define data1a		r2
+#define data1b		r3
+#define const_m1	r12
+#define const_0		r4
+#define tmp1		r4		/* Overlaps const_0  */
+#define tmp2		r5
+
+ENTRY (__strlen_armv6t2)
+	pld	[srcin, #0]
+	strd	r4, r5, [sp, #-8]!
+	bic	src, srcin, #7
+	mvn	const_m1, #0
+	ands	tmp1, srcin, #7		/* (8 - bytes) to alignment.  */
+	pld	[src, #32]
+	bne.w	L(misaligned8)
+	mov	const_0, #0
+	mov	result, #-8
+L(loop_aligned):
+	/* Bytes 0-7.  */
+	ldrd	data1a, data1b, [src]
+	pld	[src, #64]
+	add	result, result, #8
+L(start_realigned):
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cbnz	data1b, L(null_found)
+
+	/* Bytes 8-15.  */
+	ldrd	data1a, data1b, [src, #8]
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	add	result, result, #8
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cbnz	data1b, L(null_found)
+
+	/* Bytes 16-23.  */
+	ldrd	data1a, data1b, [src, #16]
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	add	result, result, #8
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cbnz	data1b, L(null_found)
+
+	/* Bytes 24-31.  */
+	ldrd	data1a, data1b, [src, #24]
+	add	src, src, #32
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	add	result, result, #8
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cmp	data1b, #0
+	beq	L(loop_aligned)
+
+L(null_found):
+	cmp	data1a, #0
+	itt	eq
+	addeq	result, result, #4
+	moveq	data1a, data1b
+#ifndef __ARMEB__
+	rev	data1a, data1a
+#endif
+	clz	data1a, data1a
+	ldrd	r4, r5, [sp], #8
+	add	result, result, data1a, lsr #3	/* Bits -> Bytes.  */
+	bx	lr
+
+L(misaligned8):
+	ldrd	data1a, data1b, [src]
+	and	tmp2, tmp1, #3
+	rsb	result, tmp1, #0
+	lsl	tmp2, tmp2, #3			/* Bytes -> bits.  */
+	tst	tmp1, #4
+	pld	[src, #64]
+	S2HI	tmp2, const_m1, tmp2
+	orn	data1a, data1a, tmp2
+	itt	ne
+	ornne	data1b, data1b, tmp2
+	movne	data1a, const_m1
+	mov	const_0, #0
+	b	L(start_realigned)
+
+END (__strlen_armv6t2)
+
+#endif /* __ARM_ARCH >= 6 && __ARM_ARCH_ISA_THUMB == 2  */
diff --git a/libc/AOR_v20.02/string/asmdefs.h b/libc/AOR_v20.02/string/asmdefs.h
new file mode 100644
index 0000000000000..dcdd109ca0c06
--- /dev/null
+++ b/libc/AOR_v20.02/string/asmdefs.h
@@ -0,0 +1,32 @@
+/*
+ * Macros for asm code.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#ifndef _ASMDEFS_H
+#define _ASMDEFS_H
+
+#define ENTRY_ALIGN(name, alignment)	\
+  .global name;		\
+  .type name,%function;	\
+  .align alignment;		\
+  name:			\
+  .cfi_startproc;
+
+#define ENTRY(name)	ENTRY_ALIGN(name, 6)
+
+#define ENTRY_ALIAS(name)	\
+  .global name;		\
+  .type name,%function;	\
+  name:
+
+#define END(name)	\
+  .cfi_endproc;		\
+  .size name, .-name;
+
+#define L(l) .L ## l
+
+#endif
diff --git a/libc/AOR_v20.02/string/include/stringlib.h b/libc/AOR_v20.02/string/include/stringlib.h
new file mode 100644
index 0000000000000..252df46cfab3b
--- /dev/null
+++ b/libc/AOR_v20.02/string/include/stringlib.h
@@ -0,0 +1,58 @@
+/*
+ * Public API.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stddef.h>
+
+/* restrict is not needed, but kept for documenting the interface contract.  */
+#ifndef __restrict
+# define __restrict
+#endif
+
+#if __aarch64__
+void *__memcpy_aarch64 (void *__restrict, const void *__restrict, size_t);
+void *__memmove_aarch64 (void *, const void *, size_t);
+void *__memset_aarch64 (void *, int, size_t);
+void *__memchr_aarch64 (const void *, int, size_t);
+int __memcmp_aarch64 (const void *, const void *, size_t);
+char *__strcpy_aarch64 (char *__restrict, const char *__restrict);
+char *__stpcpy_aarch64 (char *__restrict, const char *__restrict);
+int __strcmp_aarch64 (const char *, const char *);
+char *__strchr_aarch64 (const char *, int);
+char *__strrchr_aarch64 (const char *, int);
+char *__strchrnul_aarch64 (const char *, int );
+size_t __strlen_aarch64 (const char *);
+size_t __strnlen_aarch64 (const char *, size_t);
+int __strncmp_aarch64 (const char *, const char *, size_t);
+char *__strchr_aarch64_mte (const char *, int);
+size_t __strlen_aarch64_mte (const char *);
+#if __ARM_NEON
+void *__memcpy_aarch64_simd (void *__restrict, const void *__restrict, size_t);
+void *__memmove_aarch64_simd (void *, const void *, size_t);
+#endif
+# if __ARM_FEATURE_SVE
+void *__memchr_aarch64_sve (const void *, int, size_t);
+int __memcmp_aarch64_sve (const void *, const void *, size_t);
+char *__strchr_aarch64_sve (const char *, int);
+char *__strrchr_aarch64_sve (const char *, int);
+char *__strchrnul_aarch64_sve (const char *, int );
+int __strcmp_aarch64_sve (const char *, const char *);
+char *__strcpy_aarch64_sve (char *__restrict, const char *__restrict);
+char *__stpcpy_aarch64_sve (char *__restrict, const char *__restrict);
+size_t __strlen_aarch64_sve (const char *);
+size_t __strnlen_aarch64_sve (const char *, size_t);
+int __strncmp_aarch64_sve (const char *, const char *, size_t);
+# endif
+#elif __arm__
+void *__memcpy_arm (void *__restrict, const void *__restrict, size_t);
+void *__memset_arm (void *, int, size_t);
+void *__memchr_arm (const void *, int, size_t);
+char *__strcpy_arm (char *__restrict, const char *__restrict);
+int __strcmp_arm (const char *, const char *);
+int __strcmp_armv6m (const char *, const char *);
+size_t __strlen_armv6t2 (const char *);
+#endif
diff --git a/libc/AOR_v20.02/string/test/memchr.c b/libc/AOR_v20.02/string/test/memchr.c
new file mode 100644
index 0000000000000..ee7f2131a458e
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/memchr.c
@@ -0,0 +1,94 @@
+/*
+ * memchr test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	void *(*fun)(const void *, int c, size_t n);
+} funtab[] = {
+#define F(x) {#x, x},
+F(memchr)
+#if __aarch64__
+F(__memchr_aarch64)
+# if __ARM_FEATURE_SVE
+F(__memchr_aarch64_sve)
+# endif
+#elif __arm__
+F(__memchr_arm)
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define SP 512
+#define LEN 250000
+static unsigned char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int align, int seekpos, int len)
+{
+	unsigned char *src = alignup(sbuf);
+	unsigned char *s = src + align;
+	unsigned char *f = len ? s + seekpos : 0;
+	int seekchar = 0x1;
+	int i;
+	void *p;
+
+	if (len > LEN || seekpos >= len || align >= A)
+		abort();
+
+	for (i = 0; i < seekpos; i++)
+		s[i] = 'a' + i%23;
+	s[i++] = seekchar;
+	for (; i < len; i++)
+		s[i] = 'a' + i%23;
+
+	p = fun->fun(s, seekchar, len);
+
+	if (p != f) {
+		ERR("%s(%p,0x%02x,%d) returned %p\n", fun->name, s, seekchar, len, p);
+		ERR("expected: %p\n", f);
+		abort();
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int a = 0; a < A; a++) {
+			for (int n = 0; n < 100; n++)
+				for (int sp = 0; sp < n-1; sp++)
+					test(funtab+i, a, sp, n);
+			for (int n = 100; n < LEN; n *= 2) {
+				test(funtab+i, a, n-1, n);
+				test(funtab+i, a, n/2, n);
+			}
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/memcmp.c b/libc/AOR_v20.02/string/test/memcmp.c
new file mode 100644
index 0000000000000..ece23bc571b5f
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/memcmp.c
@@ -0,0 +1,97 @@
+/*
+ * memcmp test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	int (*fun)(const void *s1, const void *s2, size_t n);
+} funtab[] = {
+#define F(x) {#x, x},
+F(memcmp)
+#if __aarch64__
+F(__memcmp_aarch64)
+# if __ARM_FEATURE_SVE
+F(__memcmp_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static unsigned char s1buf[LEN+2*A];
+static unsigned char s2buf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int s1align, int s2align, int len, int diffpos)
+{
+	unsigned char *src1 = alignup(s1buf);
+	unsigned char *src2 = alignup(s2buf);
+	unsigned char *s1 = src1 + s1align;
+	unsigned char *s2 = src2 + s2align;
+	int r;
+
+	if (len > LEN || s1align >= A || s2align >= A)
+		abort();
+	if (diffpos && diffpos >= len)
+		abort();
+
+	for (int i = 0; i < len+A; i++)
+		src1[i] = src2[i] = '?';
+	for (int i = 0; i < len; i++)
+		s1[i] = s2[i] = 'a' + i%23;
+	if (diffpos)
+		s1[diffpos]++;
+
+	r = fun->fun(s1, s2, len);
+
+	if ((!diffpos && r != 0) || (diffpos && r == 0)) {
+		ERR("%s(align %d, align %d, %d) failed, returned %d\n",
+			fun->name, s1align, s2align, len, r);
+		ERR("src1: %.*s\n", s1align+len+1, src1);
+		ERR("src2: %.*s\n", s2align+len+1, src2);
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++) {
+					test(funtab+i, d, s, n, 0);
+					test(funtab+i, d, s, n, n / 2);
+				}
+				for (; n < LEN; n *= 2) {
+					test(funtab+i, d, s, n, 0);
+					test(funtab+i, d, s, n, n / 2);
+				}
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/memcpy.c b/libc/AOR_v20.02/string/test/memcpy.c
new file mode 100644
index 0000000000000..62823af331ee7
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/memcpy.c
@@ -0,0 +1,99 @@
+/*
+ * memcpy test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	void *(*fun)(void *, const void *, size_t);
+} funtab[] = {
+#define F(x) {#x, x},
+F(memcpy)
+#if __aarch64__
+F(__memcpy_aarch64)
+# if __ARM_NEON
+F(__memcpy_aarch64_simd)
+# endif
+#elif __arm__
+F(__memcpy_arm)
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static unsigned char dbuf[LEN+2*A];
+static unsigned char sbuf[LEN+2*A];
+static unsigned char wbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int dalign, int salign, int len)
+{
+	unsigned char *src = alignup(sbuf);
+	unsigned char *dst = alignup(dbuf);
+	unsigned char *want = wbuf;
+	unsigned char *s = src + salign;
+	unsigned char *d = dst + dalign;
+	unsigned char *w = want + dalign;
+	void *p;
+	int i;
+
+	if (len > LEN || dalign >= A || salign >= A)
+		abort();
+	for (i = 0; i < len+A; i++) {
+		src[i] = '?';
+		want[i] = dst[i] = '*';
+	}
+	for (i = 0; i < len; i++)
+		s[i] = w[i] = 'a' + i%23;
+
+	p = fun->fun(d, s, len);
+	if (p != d)
+		ERR("%s(%p,..) returned %p\n", fun->name, d, p);
+	for (i = 0; i < len+A; i++) {
+		if (dst[i] != want[i]) {
+			ERR("%s(align %d, align %d, %d) failed\n", fun->name, dalign, salign, len);
+			ERR("got : %.*s\n", dalign+len+1, dst);
+			ERR("want: %.*s\n", dalign+len+1, want);
+			break;
+		}
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++)
+					test(funtab+i, d, s, n);
+				for (; n < LEN; n *= 2)
+					test(funtab+i, d, s, n);
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/memmove.c b/libc/AOR_v20.02/string/test/memmove.c
new file mode 100644
index 0000000000000..6bb9eee1c3d97
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/memmove.c
@@ -0,0 +1,145 @@
+/*
+ * memmove test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	void *(*fun)(void *, const void *, size_t);
+} funtab[] = {
+#define F(x) {#x, x},
+F(memmove)
+#if __aarch64__
+F(__memmove_aarch64)
+# if __ARM_NEON
+F(__memmove_aarch64_simd)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static unsigned char dbuf[LEN+2*A];
+static unsigned char sbuf[LEN+2*A];
+static unsigned char wbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int dalign, int salign, int len)
+{
+	unsigned char *src = alignup(sbuf);
+	unsigned char *dst = alignup(dbuf);
+	unsigned char *want = wbuf;
+	unsigned char *s = src + salign;
+	unsigned char *d = dst + dalign;
+	unsigned char *w = want + dalign;
+	void *p;
+	int i;
+
+	if (len > LEN || dalign >= A || salign >= A)
+		abort();
+	for (i = 0; i < len+A; i++) {
+		src[i] = '?';
+		want[i] = dst[i] = '*';
+	}
+	for (i = 0; i < len; i++)
+		s[i] = w[i] = 'a' + i%23;
+
+	p = fun->fun(d, s, len);
+	if (p != d)
+		ERR("%s(%p,..) returned %p\n", fun->name, d, p);
+	for (i = 0; i < len+A; i++) {
+		if (dst[i] != want[i]) {
+			ERR("%s(align %d, align %d, %d) failed\n", fun->name, dalign, salign, len);
+			ERR("got : %.*s\n", dalign+len+1, dst);
+			ERR("want: %.*s\n", dalign+len+1, want);
+			break;
+		}
+	}
+}
+
+static void test_overlap(const struct fun *fun, int dalign, int salign, int len)
+{
+	unsigned char *src = alignup(sbuf);
+	unsigned char *dst = alignup(sbuf);
+	unsigned char *want = wbuf;
+	unsigned char *s = src + salign;
+	unsigned char *d = dst + dalign;
+	unsigned char *w = wbuf + dalign;
+	void *p;
+
+	if (len > LEN || dalign >= A || salign >= A)
+		abort();
+
+	for (int i = 0; i < len+A; i++)
+		src[i] = want[i] = '?';
+
+	for (int i = 0; i < len; i++)
+		s[i] = w[i] = 'a' + i%23;
+
+	/* Copy the potential overlap range.  */
+	if (s < d) {
+		for (int i = 0; i < (uintptr_t)d-(uintptr_t)s; i++)
+			want[salign+i] = src[salign+i];
+	} else {
+		for (int i = 0; i < (uintptr_t)s-(uintptr_t)d; i++)
+			want[len + dalign + i] = src[len + dalign + i];
+	}
+
+	p = fun->fun(d, s, len);
+	if (p != d)
+		ERR("%s(%p,..) returned %p\n", fun->name, d, p);
+	for (int i = 0; i < len+A; i++) {
+		if (dst[i] != want[i]) {
+			ERR("%s(align %d, align %d, %d) failed\n", fun->name, dalign, salign, len);
+			ERR("got : %.*s\n", dalign+len+1, dst);
+			ERR("want: %.*s\n", dalign+len+1, want);
+			abort();
+			break;
+		}
+	}
+}
+
+int main()
+{
+	test_overlap(funtab+0, 2, 1, 1);
+
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++) {
+					test(funtab+i, d, s, n);
+					test_overlap(funtab+i, d, s, n);
+				}
+				for (; n < LEN; n *= 2) {
+					test(funtab+i, d, s, n);
+					test_overlap(funtab+i, d, s, n);
+				}
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/memset.c b/libc/AOR_v20.02/string/test/memset.c
new file mode 100644
index 0000000000000..b977ceeb3102d
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/memset.c
@@ -0,0 +1,112 @@
+/*
+ * memset test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	void *(*fun)(void *s, int c, size_t n);
+} funtab[] = {
+#define F(x) {#x, x},
+F(memset)
+#if __aarch64__
+F(__memset_aarch64)
+#elif __arm__
+F(__memset_arm)
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static unsigned char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void err(const char *name, unsigned char *src, int salign, int c, int len)
+{
+	ERR("%s(align %d, %d, %d) failed\n", name, salign, c, len);
+	ERR("got : %.*s\n", salign+len+1, src);
+}
+
+static void test(const struct fun *fun, int salign, int c, int len)
+{
+	unsigned char *src = alignup(sbuf);
+	unsigned char *s = src + salign;
+	void *p;
+	int i;
+
+	if (len > LEN || salign >= A)
+		abort();
+	for (i = 0; i < len+A; i++)
+		src[i] = '?';
+	for (i = 0; i < len; i++)
+		s[i] = 'a' + i%23;
+	for (; i<len%A; i++)
+		s[i] = '*';
+
+	p = fun->fun(s, c, len);
+	if (p != s)
+		ERR("%s(%p,..) returned %p\n", fun->name, s, p);
+
+	for (i = 0; i < salign; i++) {
+		if (src[i] != '?') {
+			err(fun->name, src, salign, c, len);
+			return;
+		}
+	}
+	for (i = salign; i < len; i++) {
+		if (src[i] != (unsigned char)c) {
+			err(fun->name, src, salign, c, len);
+			return;
+		}
+	}
+	for (; i < len%A; i++) {
+		if (src[i] != '*') {
+			err(fun->name, src, salign, c, len);
+			return;
+		}
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int s = 0; s < A; s++) {
+			int n;
+			for (n = 0; n < 100; n++) {
+				test(funtab+i, s, 0, n);
+				test(funtab+i, s, 0x25, n);
+				test(funtab+i, s, 0xaa25, n);
+			}
+			for (; n < LEN; n *= 2) {
+				test(funtab+i, s, 0, n);
+				test(funtab+i, s, 0x25, n);
+				test(funtab+i, s, 0xaa25, n);
+			}
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/stpcpy.c b/libc/AOR_v20.02/string/test/stpcpy.c
new file mode 100644
index 0000000000000..eea9be1cac6cc
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/stpcpy.c
@@ -0,0 +1,99 @@
+/*
+ * stpcpy test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define _GNU_SOURCE
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	char *(*fun)(char *dest, const char *src);
+} funtab[] = {
+#define F(x) {#x, x},
+F(stpcpy)
+#if __aarch64__
+F(__stpcpy_aarch64)
+# if __ARM_FEATURE_SVE
+F(__stpcpy_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static char dbuf[LEN+2*A];
+static char sbuf[LEN+2*A];
+static char wbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int dalign, int salign, int len)
+{
+	char *src = alignup(sbuf);
+	char *dst = alignup(dbuf);
+	char *want = wbuf;
+	char *s = src + salign;
+	char *d = dst + dalign;
+	char *w = want + dalign;
+	void *p;
+	int i;
+
+	if (len > LEN || dalign >= A || salign >= A)
+		abort();
+	for (i = 0; i < len+A; i++) {
+		src[i] = '?';
+		want[i] = dst[i] = '*';
+	}
+	for (i = 0; i < len; i++)
+		s[i] = w[i] = 'a' + i%23;
+	s[i] = w[i] = '\0';
+
+	p = fun->fun(d, s);
+	if (p != d + len)
+		ERR("%s(%p,..) returned %p\n", fun->name, d, p);
+	for (i = 0; i < len+A; i++) {
+		if (dst[i] != want[i]) {
+			ERR("%s(align %d, align %d, %d) failed\n", fun->name, dalign, salign, len);
+			ERR("got : %.*s\n", dalign+len+1, dst);
+			ERR("want: %.*s\n", dalign+len+1, want);
+			break;
+		}
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++)
+					test(funtab+i, d, s, n);
+				for (; n < LEN; n *= 2)
+					test(funtab+i, d, s, n);
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strchr.c b/libc/AOR_v20.02/string/test/strchr.c
new file mode 100644
index 0000000000000..6076e03809555
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strchr.c
@@ -0,0 +1,99 @@
+/*
+ * strchr test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	char *(*fun)(const char *s, int c);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strchr)
+#if __aarch64__
+F(__strchr_aarch64)
+F(__strchr_aarch64_mte)
+# if __ARM_FEATURE_SVE
+F(__strchr_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define SP 512
+#define LEN 250000
+static char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int align, int seekpos, int len)
+{
+	char *src = alignup(sbuf);
+	char *s = src + align;
+	char *f = seekpos != -1 ? s + seekpos : 0;
+	int seekchar = 0x1;
+	void *p;
+
+	if (len > LEN || seekpos >= len - 1 || align >= A)
+		abort();
+	if (seekchar >= 'a' && seekchar <= 'a' + 23)
+		abort();
+
+	for (int i = 0; i < len + A; i++)
+		src[i] = '?';
+	for (int i = 0; i < len - 2; i++)
+		s[i] = 'a' + i%23;
+	if (seekpos != -1)
+		s[seekpos] = seekchar;
+	s[len - 1] = '\0';
+
+	p = fun->fun(s, seekchar);
+
+	if (p != f) {
+		ERR("%s(%p,0x%02x,%d) returned %p\n", fun->name, s, seekchar, len, p);
+		ERR("expected: %p\n", f);
+		abort();
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int a = 0; a < A; a++) {
+			int n;
+			for (n = 1; n < 100; n++) {
+				for (int sp = 0; sp < n - 1; sp++)
+					test(funtab+i, a, sp, n);
+				test(funtab+i, a, -1, n);
+			}
+			for (; n < LEN; n *= 2) {
+				test(funtab+i, a, -1, n);
+				test(funtab+i, a, n / 2, n);
+			}
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strchrnul.c b/libc/AOR_v20.02/string/test/strchrnul.c
new file mode 100644
index 0000000000000..6be1ec6f1dc09
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strchrnul.c
@@ -0,0 +1,100 @@
+/*
+ * strchrnul test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define _GNU_SOURCE
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	char *(*fun)(const char *s, int c);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strchrnul)
+#if __aarch64__
+F(__strchrnul_aarch64)
+# if __ARM_FEATURE_SVE
+F(__strchrnul_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define SP 512
+#define LEN 250000
+static char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int align, int seekpos, int len)
+{
+	char *src = alignup(sbuf);
+	char *s = src + align;
+	char *f = seekpos != -1 ? s + seekpos : s + len - 1;
+	int seekchar = 0x1;
+	void *p;
+
+	if (len > LEN || seekpos >= len - 1 || align >= A)
+		abort();
+	if (seekchar >= 'a' && seekchar <= 'a' + 23)
+		abort();
+
+	for (int i = 0; i < len + A; i++)
+		src[i] = '?';
+	for (int i = 0; i < len - 2; i++)
+		s[i] = 'a' + i%23;
+	if (seekpos != -1)
+		s[seekpos] = seekchar;
+	s[len - 1] = '\0';
+
+	p = fun->fun(s, seekchar);
+
+	if (p != f) {
+		ERR("%s(%p,0x%02x,%d) returned %p\n", fun->name, s, seekchar, len, p);
+		ERR("expected: %p\n", f);
+		abort();
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int a = 0; a < A; a++) {
+			int n;
+			for (n = 1; n < 100; n++) {
+				for (int sp = 0; sp < n - 1; sp++)
+					test(funtab+i, a, sp, n);
+				test(funtab+i, a, -1, n);
+			}
+			for (; n < LEN; n *= 2) {
+				test(funtab+i, a, -1, n);
+				test(funtab+i, a, n / 2, n);
+			}
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strcmp.c b/libc/AOR_v20.02/string/test/strcmp.c
new file mode 100644
index 0000000000000..40aa6fdf6cdd6
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strcmp.c
@@ -0,0 +1,104 @@
+/*
+ * strcmp test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	int (*fun)(const char *s1, const char *s2);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strcmp)
+#if __aarch64__
+F(__strcmp_aarch64)
+# if __ARM_FEATURE_SVE
+F(__strcmp_aarch64_sve)
+# endif
+#elif __arm__
+# if __ARM_ARCH >= 7 && __ARM_ARCH_ISA_ARM >= 1
+F(__strcmp_arm)
+# elif __ARM_ARCH == 6 && __ARM_ARCH_6M__ >= 1
+F(__strcmp_armv6m)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static char s1buf[LEN+2*A];
+static char s2buf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int s1align, int s2align, int len, int diffpos)
+{
+	char *src1 = alignup(s1buf);
+	char *src2 = alignup(s2buf);
+	char *s1 = src1 + s1align;
+	char *s2 = src2 + s2align;
+	int r;
+
+	if (len > LEN || s1align >= A || s2align >= A)
+		abort();
+	if (diffpos > 1 && diffpos >= len-1)
+		abort();
+
+	for (int i = 0; i < len+A; i++)
+		src1[i] = src2[i] = '?';
+	for (int i = 0; i < len-1; i++)
+		s1[i] = s2[i] = 'a' + i%23;
+	if (diffpos > 1)
+		s1[diffpos]++;
+	s1[len] = s2[len] = '\0';
+
+	r = fun->fun(s1, s2);
+
+	if (((diffpos <= 1) && r != 0) || (diffpos > 1 && r == 0)) {
+		ERR("%s(align %d, align %d, %d) failed, returned %d\n",
+			fun->name, s1align, s2align, len, r);
+		ERR("src1: %.*s\n", s1align+len+1, src1);
+		ERR("src2: %.*s\n", s2align+len+1, src2);
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++) {
+					test(funtab+i, d, s, n, 0);
+					test(funtab+i, d, s, n, n / 2);
+				}
+				for (; n < LEN; n *= 2) {
+					test(funtab+i, d, s, n, 0);
+					test(funtab+i, d, s, n, n / 2);
+				}
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strcpy.c b/libc/AOR_v20.02/string/test/strcpy.c
new file mode 100644
index 0000000000000..d00fbefd792d0
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strcpy.c
@@ -0,0 +1,100 @@
+/*
+ * strcpy test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	char *(*fun)(char *dest, const char *src);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strcpy)
+#if __aarch64__
+F(__strcpy_aarch64)
+# if __ARM_FEATURE_SVE
+F(__strcpy_aarch64_sve)
+# endif
+#elif __arm__ && defined (__thumb2__) && !defined (__thumb__)
+F(__strcpy_arm)
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static char dbuf[LEN+2*A];
+static char sbuf[LEN+2*A];
+static char wbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int dalign, int salign, int len)
+{
+	char *src = alignup(sbuf);
+	char *dst = alignup(dbuf);
+	char *want = wbuf;
+	char *s = src + salign;
+	char *d = dst + dalign;
+	char *w = want + dalign;
+	void *p;
+	int i;
+
+	if (len > LEN || dalign >= A || salign >= A)
+		abort();
+	for (i = 0; i < len+A; i++) {
+		src[i] = '?';
+		want[i] = dst[i] = '*';
+	}
+	for (i = 0; i < len; i++)
+		s[i] = w[i] = 'a' + i%23;
+	s[i] = w[i] = '\0';
+
+	p = fun->fun(d, s);
+	if (p != d)
+		ERR("%s(%p,..) returned %p\n", fun->name, d, p);
+	for (i = 0; i < len+A; i++) {
+		if (dst[i] != want[i]) {
+			ERR("%s(align %d, align %d, %d) failed\n", fun->name, dalign, salign, len);
+			ERR("got : %.*s\n", dalign+len+1, dst);
+			ERR("want: %.*s\n", dalign+len+1, want);
+			break;
+		}
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++)
+					test(funtab+i, d, s, n);
+				for (; n < LEN; n *= 2)
+					test(funtab+i, d, s, n);
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strlen.c b/libc/AOR_v20.02/string/test/strlen.c
new file mode 100644
index 0000000000000..16a9176495c51
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strlen.c
@@ -0,0 +1,92 @@
+/*
+ * strlen test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	size_t (*fun)(const char *s);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strlen)
+#if __aarch64__
+F(__strlen_aarch64)
+F(__strlen_aarch64_mte)
+# if __ARM_FEATURE_SVE
+F(__strlen_aarch64_sve)
+# endif
+#elif __arm__
+# if __ARM_ARCH >= 6 && __ARM_ARCH_ISA_THUMB == 2
+F(__strlen_armv6t2)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define SP 512
+#define LEN 250000
+static char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int align, int len)
+{
+	char *src = alignup(sbuf);
+	char *s = src + align;
+	size_t r;
+
+	if (len > LEN || align >= A)
+		abort();
+
+	for (int i = 0; i < len + A; i++)
+		src[i] = '?';
+	for (int i = 0; i < len - 2; i++)
+		s[i] = 'a' + i%23;
+	s[len - 1] = '\0';
+
+	r = fun->fun(s);
+	if (r != len-1) {
+		ERR("%s(%p) returned %zu\n", fun->name, s, r);
+		ERR("input:    %.*s\n", align+len+1, src);
+		ERR("expected: %d\n", len);
+		abort();
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int a = 0; a < A; a++) {
+			int n;
+			for (n = 1; n < 100; n++)
+				test(funtab+i, a, n);
+			for (; n < LEN; n *= 2)
+				test(funtab+i, a, n);
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strncmp.c b/libc/AOR_v20.02/string/test/strncmp.c
new file mode 100644
index 0000000000000..db2ef264aca1a
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strncmp.c
@@ -0,0 +1,104 @@
+/*
+ * strncmp test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	int (*fun)(const char *, const char *, size_t);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strncmp)
+#if __aarch64__
+F(__strncmp_aarch64)
+# if __ARM_FEATURE_SVE
+F(__strncmp_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define LEN 250000
+static char s1buf[LEN+2*A];
+static char s2buf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int s1align, int s2align, int maxlen, int diffpos, int len)
+{
+	char *src1 = alignup(s1buf);
+	char *src2 = alignup(s2buf);
+	char *s1 = src1 + s1align;
+	char *s2 = src2 + s2align;
+	int r;
+
+	if (len > LEN || s1align >= A || s2align >= A)
+		abort();
+	if (diffpos > 1 && diffpos >= len-1)
+		abort();
+
+	for (int i = 0; i < len+A; i++)
+		src1[i] = src2[i] = '?';
+	for (int i = 0; i < len-1; i++)
+		s1[i] = s2[i] = 'a' + i%23;
+	if (diffpos > 1)
+		s1[diffpos]++;
+	s1[len] = s2[len] = '\0';
+
+	r = fun->fun(s1, s2, maxlen);
+
+	diffpos = maxlen <= diffpos ? 0 : diffpos;
+
+	if (((diffpos <= 1) && r != 0) || (diffpos > 1 && r == 0)) {
+		ERR("%s(align %d, align %d, %d (%d)) failed, returned %d (%d)\n",
+			fun->name, s1align, s2align, maxlen, len, r, diffpos);
+		ERR("src1: %.*s\n", s1align+len+1, src1);
+		ERR("src2: %.*s\n", s2align+len+1, src2);
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int d = 0; d < A; d++)
+			for (int s = 0; s < A; s++) {
+				int n;
+				for (n = 0; n < 100; n++) {
+					test(funtab+i, d, s, n,   0,   n);
+					test(funtab+i, d, s, n,   n/2, n);
+					test(funtab+i, d, s, n/2, 0,   n);
+					test(funtab+i, d, s, n/2, n/2, n);
+				}
+				for (; n < LEN; n *= 2) {
+					test(funtab+i, d, s, n,   0,   n);
+					test(funtab+i, d, s, n,   n/2, n);
+					test(funtab+i, d, s, n/2, 0,   n);
+					test(funtab+i, d, s, n/2, n/2, n);
+				}
+			}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strnlen.c b/libc/AOR_v20.02/string/test/strnlen.c
new file mode 100644
index 0000000000000..d71272f16db24
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strnlen.c
@@ -0,0 +1,94 @@
+/*
+ * strnlen test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#define _POSIX_C_SOURCE 200809L
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	size_t (*fun)(const char *s, size_t m);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strnlen)
+#if __aarch64__
+F(__strnlen_aarch64)
+# if __ARM_FEATURE_SVE
+F(__strnlen_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define SP 512
+#define LEN 250000
+static char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int align, int maxlen, int len)
+{
+	char *src = alignup(sbuf);
+	char *s = src + align;
+	size_t r;
+	size_t e = maxlen < len ? maxlen : len - 1;
+
+	if (len > LEN || align >= A)
+		abort();
+
+	for (int i = 0; i < len + A; i++)
+		src[i] = '?';
+	for (int i = 0; i < len - 2; i++)
+		s[i] = 'a' + i%23;
+	s[len - 1] = '\0';
+
+	r = fun->fun(s, maxlen);
+	if (r != e) {
+		ERR("%s(%p) returned %zu\n", fun->name, s, r);
+		ERR("input:    %.*s\n", align+len+1, src);
+		ERR("expected: %d\n", len);
+		abort();
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int a = 0; a < A; a++) {
+			int n;
+			for (n = 1; n < 100; n++)
+				for (int maxlen = 0; maxlen < 100; maxlen++)
+					test(funtab+i, a, maxlen, n);
+			for (; n < LEN; n *= 2) {
+				test(funtab+i, a, n*2, n);
+				test(funtab+i, a, n, n);
+				test(funtab+i, a, n/2, n);
+			}
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/test/strrchr.c b/libc/AOR_v20.02/string/test/strrchr.c
new file mode 100644
index 0000000000000..b2c3c873fcb67
--- /dev/null
+++ b/libc/AOR_v20.02/string/test/strrchr.c
@@ -0,0 +1,98 @@
+/*
+ * strrchr test.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include "stringlib.h"
+
+static const struct fun
+{
+	const char *name;
+	char *(*fun)(const char *s, int c);
+} funtab[] = {
+#define F(x) {#x, x},
+F(strrchr)
+#if __aarch64__
+F(__strrchr_aarch64)
+# if __ARM_FEATURE_SVE
+F(__strrchr_aarch64_sve)
+# endif
+#endif
+#undef F
+	{0, 0}
+};
+
+static int test_status;
+#define ERR(...) (test_status=1, printf(__VA_ARGS__))
+
+#define A 32
+#define SP 512
+#define LEN 250000
+static char sbuf[LEN+2*A];
+
+static void *alignup(void *p)
+{
+	return (void*)(((uintptr_t)p + A-1) & -A);
+}
+
+static void test(const struct fun *fun, int align, int seekpos, int len)
+{
+	char *src = alignup(sbuf);
+	char *s = src + align;
+	char *f = seekpos != -1 ? s + seekpos : 0;
+	int seekchar = 0x1;
+	void *p;
+
+	if (len > LEN || seekpos >= len - 1 || align >= A)
+		abort();
+	if (seekchar >= 'a' && seekchar <= 'a' + 23)
+		abort();
+
+	for (int i = 0; i < len + A; i++)
+		src[i] = '?';
+	for (int i = 0; i < len - 2; i++)
+		s[i] = 'a' + i%23;
+	if (seekpos != -1)
+		s[seekpos/2] = s[seekpos] = seekchar;
+	s[len - 1] = '\0';
+
+	p = fun->fun(s, seekchar);
+
+	if (p != f) {
+		ERR("%s(%p,0x%02x,%d) returned %p\n", fun->name, s, seekchar, len, p);
+		ERR("expected: %p\n", f);
+		abort();
+	}
+}
+
+int main()
+{
+	int r = 0;
+	for (int i=0; funtab[i].name; i++) {
+		test_status = 0;
+		for (int a = 0; a < A; a++) {
+			int n;
+			for (n = 1; n < 100; n++) {
+				for (int sp = 0; sp < n - 1; sp++)
+					test(funtab+i, a, sp, n);
+				test(funtab+i, a, -1, n);
+			}
+			for (; n < LEN; n *= 2) {
+				test(funtab+i, a, -1, n);
+				test(funtab+i, a, n / 2, n);
+			}
+		}
+		printf("%s %s\n", test_status ? "FAIL" : "PASS", funtab[i].name);
+		if (test_status)
+			r = -1;
+	}
+	return r;
+}
diff --git a/libc/AOR_v20.02/string/x86_64/check-arch.S b/libc/AOR_v20.02/string/x86_64/check-arch.S
new file mode 100644
index 0000000000000..8c29aa5a7b3f4
--- /dev/null
+++ b/libc/AOR_v20.02/string/x86_64/check-arch.S
@@ -0,0 +1,11 @@
+/*
+ * check ARCH setting.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#if !__x86_64__
+# error ARCH setting does not match the compiler.
+#endif
diff --git a/libc/CMakeLists.txt b/libc/CMakeLists.txt
index fd750a06e0e14..4ee4d7dca5733 100644
--- a/libc/CMakeLists.txt
+++ b/libc/CMakeLists.txt
@@ -21,6 +21,7 @@ set(LIBC_TARGET_MACHINE ${CMAKE_SYSTEM_PROCESSOR})
 
 include(CMakeParseArguments)
 include(LLVMLibCRules)
+include(LLVMLibCCheckCpuFeatures)
 
 add_subdirectory(src)
 add_subdirectory(config)
diff --git a/libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake b/libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
index adf81f3e38ab9..0bb4af869487b 100644
--- a/libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
+++ b/libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
@@ -1,99 +1,129 @@
-#------------------------------------------------------------------------------
+# ------------------------------------------------------------------------------
 # Cpu features definition and flags
-#
-# Declare a list of all supported cpu features in ALL_CPU_FEATURES.
-#
-# Declares associated flags to enable/disable individual feature of the form:
-# - CPU_FEATURE_<FEATURE>_ENABLE_FLAG
-# - CPU_FEATURE_<FEATURE>_DISABLE_FLAG
-#
-#------------------------------------------------------------------------------
+# ------------------------------------------------------------------------------
 
 if(${LIBC_TARGET_MACHINE} MATCHES "x86|x86_64")
-  set(ALL_CPU_FEATURES SSE SSE2 AVX AVX512F)
+  set(ALL_CPU_FEATURES SSE SSE2 AVX AVX2 AVX512F)
 endif()
 
-function(_define_cpu_feature_flags feature)
-  if(${CMAKE_CXX_COMPILER_ID} MATCHES "Clang")
-    string(TOLOWER ${feature} lowercase_feature)
-    set(CPU_FEATURE_${feature}_ENABLE_FLAG "-m${lowercase_feature}" PARENT_SCOPE)
-    set(CPU_FEATURE_${feature}_DISABLE_FLAG "-mno-${lowercase_feature}" PARENT_SCOPE)
+list(SORT ALL_CPU_FEATURES)
+
+# Function to check whether the host supports the provided set of features.
+# Usage:
+# host_supports(
+#   <output variable>
+#   <list of cpu features>
+# )
+function(host_supports output_var features)
+  _intersection(a "${HOST_CPU_FEATURES}" "${features}")
+  if("${a}" STREQUAL "${features}")
+    set(${output_var} TRUE PARENT_SCOPE)
+  else()
+    unset(${output_var} PARENT_SCOPE)
+  endif()
+endfunction()
+
+# Function to compute the flags to pass down to the compiler.
+# Usage:
+# compute_flags(
+#   <output variable>
+#   MARCH <arch name or "native">
+#   REQUIRE <list of mandatory features to enable>
+#   REJECT <list of features to disable>
+# )
+function(compute_flags output_var)
+  cmake_parse_arguments(
+    "COMPUTE_FLAGS"
+    "" # Optional arguments
+    "MARCH" # Single value arguments
+    "REQUIRE;REJECT" # Multi value arguments
+    ${ARGN})
+  # Check that features are not required and rejected at the same time.
+  if(COMPUTE_FLAGS_REQUIRE AND COMPUTE_FLAGS_REJECT)
+    _intersection(var ${COMPUTE_FLAGS_REQUIRE} ${COMPUTE_FLAGS_REJECT})
+    if(var)
+      message(FATAL_ERROR "Cpu Features REQUIRE and REJECT ${var}")
+    endif()
+  endif()
+  # Generate the compiler flags in `current`.
+  if(${CMAKE_CXX_COMPILER_ID} MATCHES "Clang|GNU")
+    if(COMPUTE_FLAGS_MARCH)
+      list(APPEND current "-march=${COMPUTE_FLAGS_MARCH}")
+    endif()
+    foreach(feature IN LISTS COMPUTE_FLAGS_REQUIRE)
+      string(TOLOWER ${feature} lowercase_feature)
+      list(APPEND current "-m${lowercase_feature}")
+    endforeach()
+    foreach(feature IN LISTS COMPUTE_FLAGS_REJECT)
+      string(TOLOWER ${feature} lowercase_feature)
+      list(APPEND current "-mno-${lowercase_feature}")
+    endforeach()
   else()
     # In future, we can extend for other compilers.
     message(FATAL_ERROR "Unkown compiler ${CMAKE_CXX_COMPILER_ID}.")
   endif()
+  # Export the list of flags.
+  set(${output_var} "${current}" PARENT_SCOPE)
 endfunction()
 
-# Defines cpu features flags
-foreach(feature IN LISTS ALL_CPU_FEATURES)
-  _define_cpu_feature_flags(${feature})
-endforeach()
-
-#------------------------------------------------------------------------------
-# Optimization level flags
-#
-# Generates the set of flags needed to compile for a up to a particular
-# optimization level.
-#
-# Creates variables of the form `CPU_FEATURE_OPT_<FEATURE>_FLAGS`.
-# CPU_FEATURE_OPT_NONE_FLAGS is a special flag for which no feature is needed.
-#
-# e.g.
-# CPU_FEATURE_OPT_NONE_FLAGS : -mno-sse;-mno-sse2;-mno-avx;-mno-avx512f
-# CPU_FEATURE_OPT_SSE_FLAGS : -msse;-mno-sse2;-mno-avx;-mno-avx512f
-# CPU_FEATURE_OPT_SSE2_FLAGS : -msse;-msse2;-mno-avx;-mno-avx512f
-# CPU_FEATURE_OPT_AVX_FLAGS : -msse;-msse2;-mavx;-mno-avx512f
-# CPU_FEATURE_OPT_AVX512F_FLAGS : -msse;-msse2;-mavx;-mavx512f
-#------------------------------------------------------------------------------
+# ------------------------------------------------------------------------------
+# Internal helpers and utilities.
+# ------------------------------------------------------------------------------
 
-# Helper function to concatenate flags needed to support optimization up to
-# a particular feature.
-function(_generate_flags_for_up_to feature flag_variable)
-  list(FIND ALL_CPU_FEATURES ${feature} feature_index)
-  foreach(current_feature IN LISTS ALL_CPU_FEATURES)
-    list(FIND ALL_CPU_FEATURES ${current_feature} current_feature_index)  
-    if(${current_feature_index} GREATER ${feature_index})
-      list(APPEND flags ${CPU_FEATURE_${current_feature}_DISABLE_FLAG})
-    else()
-      list(APPEND flags ${CPU_FEATURE_${current_feature}_ENABLE_FLAG})
+# Computes the intersection between two lists.
+function(_intersection output_var list1 list2)
+  foreach(element IN LISTS list1)
+    if("${list2}" MATCHES "(^|;)${element}(;|$)")
+      list(APPEND tmp "${element}")
     endif()
   endforeach()
-  set(${flag_variable} ${flags} PARENT_SCOPE)
+  set(${output_var} ${tmp} PARENT_SCOPE)
 endfunction()
 
-function(_generate_opt_levels)
-  set(opt_levels NONE)
-  list(APPEND opt_levels ${ALL_CPU_FEATURES})
-  foreach(feature IN LISTS opt_levels)
-    set(flag_name "CPU_FEATURE_OPT_${feature}_FLAGS")
-    _generate_flags_for_up_to(${feature} ${flag_name})
-    set(${flag_name} ${${flag_name}} PARENT_SCOPE)
+# Generates a cpp file to introspect the compiler defined flags.
+function(_generate_check_code)
+  foreach(feature IN LISTS ALL_CPU_FEATURES)
+    set(DEFINITIONS
+        "${DEFINITIONS}
+#ifdef __${feature}__
+    \"${feature}\",
+#endif")
   endforeach()
+  configure_file(
+    "${LIBC_SOURCE_DIR}/cmake/modules/cpu_features/check_cpu_features.cpp.in"
+    "cpu_features/check_cpu_features.cpp" @ONLY)
 endfunction()
+_generate_check_code()
 
-_generate_opt_levels()
-
-#------------------------------------------------------------------------------
-# Host cpu feature introspection
-#
-# Populates a HOST_CPU_FEATURES list containing the available CPU_FEATURE.
-#------------------------------------------------------------------------------
-function(_check_host_cpu_feature feature)
-  string(TOLOWER ${feature} lowercase_feature)
+# Compiles and runs the code generated above with the specified requirements.
+# This is helpful to infer which features a particular target supports or if
+# a specific features implies other features (e.g. BMI2 implies SSE2 and SSE).
+function(_check_defined_cpu_feature output_var)
+  cmake_parse_arguments(
+    "CHECK_DEFINED"
+    "" # Optional arguments
+    "MARCH" # Single value arguments
+    "REQUIRE;REJECT" # Multi value arguments
+    ${ARGN})
+  compute_flags(
+    flags
+    MARCH  ${CHECK_DEFINED_MARCH}
+    REQUIRE ${CHECK_DEFINED_REQUIRE}
+    REJECT  ${CHECK_DEFINED_REJECT})
   try_run(
-    run_result
-    compile_result
-    "${CMAKE_CURRENT_BINARY_DIR}/check_${lowercase_feature}"
-    "${CMAKE_MODULE_PATH}/cpu_features/check_${lowercase_feature}.cpp"
-    COMPILE_DEFINITIONS ${CPU_FEATURE_${feature}_ENABLE_FLAG}
-    OUTPUT_VARIABLE compile_output
-  )
+    run_result compile_result "${CMAKE_CURRENT_BINARY_DIR}/check_${feature}"
+    "${CMAKE_CURRENT_BINARY_DIR}/cpu_features/check_cpu_features.cpp"
+    COMPILE_DEFINITIONS ${flags}
+    COMPILE_OUTPUT_VARIABLE compile_output
+    RUN_OUTPUT_VARIABLE run_output)
   if(${compile_result} AND ("${run_result}" EQUAL 0))
-    list(APPEND HOST_CPU_FEATURES ${feature})
-    set(HOST_CPU_FEATURES ${HOST_CPU_FEATURES} PARENT_SCOPE)
+    set(${output_var}
+        "${run_output}"
+        PARENT_SCOPE)
+  else()
+    message(FATAL_ERROR "${compile_output}")
   endif()
 endfunction()
 
-foreach(feature IN LISTS ALL_CPU_FEATURES)
-  _check_host_cpu_feature(${feature})
-endforeach()
+# Populates the HOST_CPU_FEATURES list.
+_check_defined_cpu_feature(HOST_CPU_FEATURES MARCH native)
diff --git a/libc/cmake/modules/LLVMLibCRules.cmake b/libc/cmake/modules/LLVMLibCRules.cmake
index 2fdaa630f48f1..2391ea50b0db5 100644
--- a/libc/cmake/modules/LLVMLibCRules.cmake
+++ b/libc/cmake/modules/LLVMLibCRules.cmake
@@ -94,6 +94,58 @@ function(add_gen_header target_name)
   )
 endfunction(add_gen_header)
 
+set(SINGLE_OBJECT_TARGET_TYPE "LIBC_SINGLE_OBJECT")
+
+# Function to generate single object file.
+# Usage:
+#     add_object(
+#       <target_name>
+#       SRC <source file to compile>
+#       DEPENDS <list of dependencies>
+#       COMPILE_OPTIONS <optional list of special compile options for this target>
+function(add_object target_name)
+  cmake_parse_arguments(
+    "ADD_OBJECT"
+    "" # No option arguments
+    "SRC" # Single value arguments
+    "COMPILE_OPTIONS;DEPENDS" # Multivalue arguments
+    ${ARGN}
+  )
+
+  if(NOT ADD_OBJECT_SRC)
+    message(FATAL_ERROR "'add_object' rules requires a SRC to be specified.")
+  endif()
+
+  add_library(
+    ${target_name}
+    OBJECT
+    ${ADD_OBJECT_SRC}
+  )
+  target_include_directories(
+    ${target_name}
+    PRIVATE
+      "${LIBC_BUILD_DIR}/include;${LIBC_SOURCE_DIR};${LIBC_BUILD_DIR}"
+  )
+  if(ADD_OBJECT_COMPILE_OPTIONS)
+    target_compile_options(
+      ${target_name}
+      PRIVATE ${ADD_OBJECT_COMPILE_OPTIONS}
+    )
+  endif()
+  if(ADD_OBJECT_DEPENDS)
+    add_dependencies(
+      ${target_name}
+      ${ADD_OBJECT_DEPENDS}
+    )
+  endif()
+  set_target_properties(
+    ${target_name}
+    PROPERTIES
+      "TARGET_TYPE" ${SINGLE_OBJECT_TARGET_TYPE}
+      "OBJECT_FILE" $<TARGET_OBJECTS:${target_name}>
+  )
+endfunction(add_object)
+
 set(ENTRYPOINT_OBJ_TARGET_TYPE "ENTRYPOINT_OBJ")
 
 # A rule for entrypoint object targets.
@@ -105,14 +157,15 @@ set(ENTRYPOINT_OBJ_TARGET_TYPE "ENTRYPOINT_OBJ")
 #       SRCS <list of .cpp files>
 #       HDRS <list of .h files>
 #       DEPENDS <list of dependencies>
-#       COMPILE_OPTIONS <list of special compile options for this target>
+#       COMPILE_OPTIONS <optional list of special compile options for this target>
+#       SPECIAL_OBJECTS <optional list of special object targets added by the rule `add_object`>
 #     )
 function(add_entrypoint_object target_name)
   cmake_parse_arguments(
     "ADD_ENTRYPOINT_OBJ"
     "REDIRECTED" # Optional argument
     "NAME" # Single value arguments
-    "SRCS;HDRS;DEPENDS;COMPILE_OPTIONS"  # Multi value arguments
+    "SRCS;HDRS;SPECIAL_OBJECTS;DEPENDS;COMPILE_OPTIONS"  # Multi value arguments
     ${ARGN}
   )
   if(NOT ADD_ENTRYPOINT_OBJ_SRCS)
@@ -166,10 +219,21 @@ function(add_entrypoint_object target_name)
   set(object_file_raw "${CMAKE_CURRENT_BINARY_DIR}/${target_name}_raw.o")
   set(object_file "${CMAKE_CURRENT_BINARY_DIR}/${target_name}.o")
 
+  set(input_objects $<TARGET_OBJECTS:${target_name}_objects>)
+  if(ADD_ENTRYPOINT_OBJ_SPECIAL_OBJECTS)
+    foreach(obj_target IN LISTS ADD_ENTRYPOINT_OBJ_SPECIAL_OBJECTS)
+      get_target_property(obj_type ${obj_target} "TARGET_TYPE")
+      if((NOT obj_type) OR (NOT (${obj_type} STREQUAL ${SINGLE_OBJECT_TARGET_TYPE})))
+        message(FATAL_ERROR "Unexpected target type for 'SPECIAL_OBJECT' - should be a target introduced by the `add_object` rule.")
+      endif()
+      list(APPEND input_objects $<TARGET_OBJECTS:${obj_target}>)
+    endforeach(obj_target)
+  endif()
+
   add_custom_command(
     OUTPUT ${object_file_raw}
-    DEPENDS $<TARGET_OBJECTS:${target_name}_objects>
-    COMMAND ${CMAKE_LINKER} -r $<TARGET_OBJECTS:${target_name}_objects> -o ${object_file_raw}
+    DEPENDS ${input_objects}
+    COMMAND ${CMAKE_LINKER} -r ${input_objects} -o ${object_file_raw}
   )
 
   set(alias_attributes "0,function,global")
@@ -308,6 +372,7 @@ endfunction(add_redirector_library)
 #      SRCS  <list of .cpp files for the test>
 #      HDRS  <list of .h files for the test>
 #      DEPENDS <list of dependencies>
+#      COMPILE_OPTIONS <list of special compile options for this target>
 #    )
 function(add_libc_unittest target_name)
   if(NOT LLVM_INCLUDE_TESTS)
@@ -318,7 +383,7 @@ function(add_libc_unittest target_name)
     "LIBC_UNITTEST"
     "" # No optional arguments
     "SUITE" # Single value arguments
-    "SRCS;HDRS;DEPENDS" # Multi-value arguments
+    "SRCS;HDRS;DEPENDS;COMPILE_OPTIONS" # Multi-value arguments
     ${ARGN}
   )
   if(NOT LIBC_UNITTEST_SRCS)
@@ -356,6 +421,12 @@ function(add_libc_unittest target_name)
       ${LIBC_BUILD_DIR}
       ${LIBC_BUILD_DIR}/include
   )
+  if(LIBC_UNITTEST_COMPILE_OPTIONS)
+    target_compile_options(
+      ${target_name}
+      PRIVATE ${LIBC_UNITTEST_COMPILE_OPTIONS}
+    )
+  endif()
 
   if(library_deps)
     target_link_libraries(${target_name} PRIVATE ${library_deps})
diff --git a/libc/cmake/modules/cpu_features/check_avx.cpp b/libc/cmake/modules/cpu_features/check_avx.cpp
deleted file mode 100644
index f0db3abab4e5f..0000000000000
--- a/libc/cmake/modules/cpu_features/check_avx.cpp
+++ /dev/null
@@ -1,8 +0,0 @@
-#if !defined __AVX__
-#error "missing __AVX__"
-#endif
-#include <immintrin.h>
-int main() {
-  (void)_mm256_set1_epi8('0');
-  return 0;
-}
diff --git a/libc/cmake/modules/cpu_features/check_avx512f.cpp b/libc/cmake/modules/cpu_features/check_avx512f.cpp
deleted file mode 100644
index 93444e737ef4f..0000000000000
--- a/libc/cmake/modules/cpu_features/check_avx512f.cpp
+++ /dev/null
@@ -1,8 +0,0 @@
-#if !defined __AVX512F__
-#error "missing __AVX512F__"
-#endif
-#include <immintrin.h>
-int main() {
-  (void)_mm512_undefined();
-  return 0;
-}
diff --git a/libc/cmake/modules/cpu_features/check_cpu_features.cpp.in b/libc/cmake/modules/cpu_features/check_cpu_features.cpp.in
new file mode 100644
index 0000000000000..25f67a63e192a
--- /dev/null
+++ b/libc/cmake/modules/cpu_features/check_cpu_features.cpp.in
@@ -0,0 +1,29 @@
+#include <cstdio>
+#include <cstdlib>
+
+// This file is instantiated by CMake.
+// DEFINITIONS below is replaced with a set of lines like so:
+//   #ifdef __SSE2__
+//     "SSE2",
+//   #endif
+//
+// This allows for introspection of compiler definitions.
+// The output of the program is a single line of semi colon separated feature
+// names.
+
+// MSVC is using a different set of preprocessor definitions for 
+// SSE and SSE2, see _M_IX86_FP in
+// https://docs.microsoft.com/en-us/cpp/preprocessor/predefined-macros
+
+int main(int, char **) {
+  const char *strings[] = {
+      @DEFINITIONS@
+  };
+  const size_t size = sizeof(strings) / sizeof(strings[0]);
+  for (size_t i = 0; i < size; ++i) {
+    if (i)
+      putchar(';');
+    fputs(strings[i], stdout);
+  }
+  return EXIT_SUCCESS;
+}
diff --git a/libc/cmake/modules/cpu_features/check_sse.cpp b/libc/cmake/modules/cpu_features/check_sse.cpp
deleted file mode 100644
index 1c1f67179fded..0000000000000
--- a/libc/cmake/modules/cpu_features/check_sse.cpp
+++ /dev/null
@@ -1,8 +0,0 @@
-#if !defined __SSE__
-#error "missing __SSE__"
-#endif
-#include <immintrin.h>
-int main() {
-  (void)_mm_set_ss(1.0f);
-  return 0;
-}
diff --git a/libc/cmake/modules/cpu_features/check_sse2.cpp b/libc/cmake/modules/cpu_features/check_sse2.cpp
deleted file mode 100644
index f1e598de58775..0000000000000
--- a/libc/cmake/modules/cpu_features/check_sse2.cpp
+++ /dev/null
@@ -1,8 +0,0 @@
-#if !defined __SSE2__
-#error "missing __SSE2__"
-#endif
-#include <immintrin.h>
-int main() {
-  (void)_mm_set1_epi8('0');
-  return 0;
-}
diff --git a/libc/config/linux/CMakeLists.txt b/libc/config/linux/CMakeLists.txt
index 86b178abb0dec..91135bedcd50b 100644
--- a/libc/config/linux/CMakeLists.txt
+++ b/libc/config/linux/CMakeLists.txt
@@ -6,6 +6,8 @@ add_gen_header(
     inline_syscalls=${LIBC_TARGET_MACHINE}/syscall.h.inc
   DATA_FILES
     ${LIBC_TARGET_MACHINE}/syscall.h.inc
+  DEPENDS
+    support_common_h
 )
 
 add_subdirectory(x86_64)
diff --git a/libc/config/linux/api.td b/libc/config/linux/api.td
index aecdce206f656..e9391cb52febb 100644
--- a/libc/config/linux/api.td
+++ b/libc/config/linux/api.td
@@ -180,9 +180,28 @@ def SysMManAPI : PublicAPI<"sys/mman.h"> {
   ];
 }
 
+def StructSigactionDefn : TypeDecl<"struct sigaction"> {
+  let Decl = [{
+    struct __sigaction {
+      union {
+        void (*sa_handler)(int);
+        void (*sa_action)(int, siginfo_t *, void *);
+      };
+      sigset_t sa_mask;
+      int sa_flags;
+      void (*sa_restorer)(void);
+    };
+  }];
+}
+
 def SignalAPI : PublicAPI<"signal.h"> {
+  let TypeDeclarations = [
+    StructSigactionDefn,
+  ];
+
   let Functions = [
     "raise",
+    "sigaction",
     "sigprocmask",
     "sigemptyset",
     "sigaddset",
diff --git a/libc/config/linux/signal.h.in b/libc/config/linux/signal.h.in
index 1c2a30779f2be..fc7ca9a54206a 100644
--- a/libc/config/linux/signal.h.in
+++ b/libc/config/linux/signal.h.in
@@ -9,3 +9,7 @@
 %%begin()
 
 #include <linux/signal.h>
+
+#ifndef __LLVM_LIBC_INTERNAL_SIGACTION
+#define sigaction __sigaction
+#endif
diff --git a/libc/lib/CMakeLists.txt b/libc/lib/CMakeLists.txt
index 238bcb4475121..b234c91704a9d 100644
--- a/libc/lib/CMakeLists.txt
+++ b/libc/lib/CMakeLists.txt
@@ -11,6 +11,7 @@ add_entrypoint_library(
     # string.h entrypoints
     strcpy
     strcat
+    memcpy
 
     # sys/mman.h entrypoints
     mmap
@@ -18,6 +19,7 @@ add_entrypoint_library(
 
     # signal.h entrypoints
     raise
+    sigaction
     sigaddset
     sigemptyset
     sigprocmask
diff --git a/libc/spec/posix.td b/libc/spec/posix.td
index edd670a5f1491..172b0c30fede3 100644
--- a/libc/spec/posix.td
+++ b/libc/spec/posix.td
@@ -4,6 +4,12 @@ def ConstSigSetPtrType : ConstType<SigSetPtrType>;
 def RestrictSigSetType : RestrictedPtrType<SigSetType>;
 def ConstRestrictSigSetType : ConstType<RestrictSigSetType>;
 
+def StructSigaction : NamedType<"struct sigaction">;
+def StructSigactionPtr : PtrType<StructSigaction>;
+def ConstStructSigactionPtr : ConstType<StructSigactionPtr>;
+def RestrictStructSigactionPtr : RestrictedPtrType<StructSigaction>;
+def ConstRestrictStructSigactionPtr : ConstType<RestrictStructSigactionPtr>;
+
 def POSIX : StandardSpec<"POSIX"> {
   NamedType OffTType = NamedType<"off_t">;
 
@@ -137,9 +143,19 @@ def POSIX : StandardSpec<"POSIX"> {
   HeaderSpec Signal = HeaderSpec<
       "signal.h",
       [], // Macros
-      [], // Types
+      [
+        SigSetType,
+        StructSigaction,
+      ],
       [], // Enumerations
       [
+        FunctionSpec<
+          "sigaction",
+          RetValSpec<IntType>,
+          [ArgSpec<IntType>,
+           ArgSpec<ConstRestrictStructSigactionPtr>,
+           ArgSpec<RestrictStructSigactionPtr>]
+        >,
         FunctionSpec<
           "sigprocmask",
           RetValSpec<IntType>,
diff --git a/libc/spec/stdc.td b/libc/spec/stdc.td
index 4df855056e9b0..dfac8ebed3c7f 100644
--- a/libc/spec/stdc.td
+++ b/libc/spec/stdc.td
@@ -225,7 +225,6 @@ def StdC : StandardSpec<"stdc"> {
         Macro<"SIGTERM">
       ],
       [
-        NamedType<"sigset_t">,
         SizeTType,
       ],
       [], // Enumerations
diff --git a/libc/src/signal/linux/CMakeLists.txt b/libc/src/signal/linux/CMakeLists.txt
index 022f41b5a0ebb..1d59b7502f7b6 100644
--- a/libc/src/signal/linux/CMakeLists.txt
+++ b/libc/src/signal/linux/CMakeLists.txt
@@ -12,6 +12,39 @@ add_entrypoint_object(
     signal_h
 )
 
+add_object(
+  __restore
+  SRC
+    __restore.cpp
+  COMPILE_OPTIONS
+    -fomit-frame-pointer
+    -O3
+    -Wframe-larger-than=0
+    -Werror
+    -Wno-attributes
+    # asan creates asan.module_ctor which uses stack space, causing warinngs.
+    -fno-sanitize=address
+  DEPENDS
+    linux_syscall_h
+    sys_syscall_h
+)
+
+add_entrypoint_object(
+  sigaction
+  SRCS
+    sigaction.cpp
+  HDRS
+    signal.h
+    ../sigaction.h
+  DEPENDS
+    __restore
+    sys_syscall_h
+    linux_syscall_h
+    signal_h
+  SPECIAL_OBJECTS
+    __restore
+)
+
 add_entrypoint_object(
   sigprocmask
   SRCS
diff --git a/libc/src/signal/linux/__restore.cpp b/libc/src/signal/linux/__restore.cpp
new file mode 100644
index 0000000000000..bfdee4bab1c38
--- /dev/null
+++ b/libc/src/signal/linux/__restore.cpp
@@ -0,0 +1,20 @@
+//===----------------- Linux implementation of __restore_rt ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// This file is implemented seperately from sigaction.cpp so that we can
+// strongly control the options this file is compiled with. __restore_rt cannot
+// make any stack allocations so we must ensure this.
+
+#include "config/linux/syscall.h"
+#include "include/sys/syscall.h"
+
+extern "C" void __restore_rt()
+    __attribute__((no_sanitize("thread", "memory", "undefined", "fuzzer"),
+                   hidden));
+
+extern "C" void __restore_rt() { __llvm_libc::syscall(SYS_rt_sigreturn); }
diff --git a/libc/src/signal/linux/sigaction.cpp b/libc/src/signal/linux/sigaction.cpp
new file mode 100644
index 0000000000000..18caeacb48193
--- /dev/null
+++ b/libc/src/signal/linux/sigaction.cpp
@@ -0,0 +1,56 @@
+//===----------------- Linux implementation of sigaction ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#define __LLVM_LIBC_INTERNAL_SIGACTION
+#include "src/signal/sigaction.h"
+#include "src/errno/llvmlibc_errno.h"
+#include "src/signal/linux/signal.h"
+
+#include "src/__support/common.h"
+
+namespace __llvm_libc {
+
+// TOOD: Some architectures will have their signal trampoline functions in the
+// vdso, use those when available.
+
+extern "C" void __restore_rt();
+
+template <typename T, typename V>
+static void copySigaction(T &dest, const V &source) {
+  dest.sa_handler = source.sa_handler;
+  dest.sa_mask = source.sa_mask;
+  dest.sa_flags = source.sa_flags;
+  dest.sa_restorer = source.sa_restorer;
+}
+
+int LLVM_LIBC_ENTRYPOINT(sigaction)(
+    int signal, const struct __sigaction *__restrict libc_new,
+    struct __sigaction *__restrict libc_old) {
+  struct sigaction kernel_new;
+  if (libc_new) {
+    copySigaction(kernel_new, *libc_new);
+    if (!(kernel_new.sa_flags & SA_RESTORER)) {
+      kernel_new.sa_flags |= SA_RESTORER;
+      kernel_new.sa_restorer = __restore_rt;
+    }
+  }
+
+  struct sigaction kernel_old;
+  int ret = syscall(SYS_rt_sigaction, signal, libc_new ? &kernel_new : nullptr,
+                    libc_old ? &kernel_old : nullptr, sizeof(sigset_t));
+  if (ret) {
+    llvmlibc_errno = -ret;
+    return -1;
+  }
+
+  if (libc_old)
+    copySigaction(*libc_old, kernel_old);
+  return 0;
+}
+
+} // namespace __llvm_libc
diff --git a/libc/src/signal/sigaction.h b/libc/src/signal/sigaction.h
new file mode 100644
index 0000000000000..c2e8f4b397625
--- /dev/null
+++ b/libc/src/signal/sigaction.h
@@ -0,0 +1,22 @@
+//===------------ Implementation header for sigaction --------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_SIGNAL_SIGACTION_H
+#define LLVM_LIBC_SRC_SIGNAL_SIGACTION_H
+
+#define __LLVM_LIBC_INTERNAL_SIGACTION
+#include "include/signal.h"
+
+namespace __llvm_libc {
+
+int sigaction(int signal, const struct __sigaction *__restrict libc_new,
+              struct __sigaction *__restrict libc_old);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_SIGNAL_SIGACTION_H
diff --git a/libc/src/string/CMakeLists.txt b/libc/src/string/CMakeLists.txt
index 49b0afd2cedf9..729ccaaa2b20a 100644
--- a/libc/src/string/CMakeLists.txt
+++ b/libc/src/string/CMakeLists.txt
@@ -1,3 +1,5 @@
+add_subdirectory(memory_utils)
+
 add_entrypoint_object(
   strcat
   SRCS
@@ -19,4 +21,63 @@ add_entrypoint_object(
     string_h
 )
 
-add_subdirectory(memory_utils)
+# ------------------------------------------------------------------------------
+# memcpy
+# ------------------------------------------------------------------------------
+
+# include the relevant architecture specific implementations
+if(${LIBC_TARGET_MACHINE} STREQUAL "x86_64")
+  set(LIBC_MEMCPY_IMPL_FOLDER "x86")
+else()
+  set(LIBC_MEMCPY_IMPL_FOLDER ${LIBC_TARGET_MACHINE})
+endif()
+
+add_gen_header(
+  memcpy_arch_specific
+  DEF_FILE
+    memcpy_arch_specific.h.def
+  GEN_HDR
+    memcpy_arch_specific.h
+  PARAMS
+    memcpy_arch_specific=${LIBC_MEMCPY_IMPL_FOLDER}/memcpy_arch_specific.h.inc
+  DATA_FILES
+    ${LIBC_MEMCPY_IMPL_FOLDER}/memcpy_arch_specific.h.inc
+)
+
+# Helper to define an implementation of memcpy.
+# - Computes flags to satisfy required/rejected features and arch,
+# - Declares an entry point,
+# - Attach the REQUIRE_CPU_FEATURES property to the target,
+# - Add the target to `memcpy_implementations` global property for tests.
+function(add_memcpy memcpy_name)
+  cmake_parse_arguments(
+    "ADD_MEMCPY"
+    "" # Optional arguments
+    "MARCH" # Single value arguments
+    "REQUIRE;REJECT" # Multi value arguments
+    ${ARGN})
+  compute_flags(flags
+    MARCH ${ADD_MEMCPY_MARCH}
+    REQUIRE ${ADD_MEMCPY_REQUIRE}
+    REJECT ${ADD_MEMCPY_REJECT}
+  )
+  add_entrypoint_object(
+    ${memcpy_name}
+    SRCS ${LIBC_SOURCE_DIR}/src/string/memcpy.cpp
+    HDRS ${LIBC_SOURCE_DIR}/src/string/memcpy.h
+    DEPENDS
+      string_h
+      memory_utils
+      memcpy_arch_specific
+    COMPILE_OPTIONS
+      -fno-builtin-memcpy
+      ${flags}
+  )
+  set_target_properties(${memcpy_name} PROPERTIES REQUIRE_CPU_FEATURES "${ADD_MEMCPY_REQUIRE}")
+  get_property(all GLOBAL PROPERTY memcpy_implementations)
+  list(APPEND all ${memcpy_name})
+  set_property(GLOBAL PROPERTY memcpy_implementations "${all}")
+endfunction()
+
+add_subdirectory(${LIBC_MEMCPY_IMPL_FOLDER})
+add_memcpy(memcpy MARCH native)
diff --git a/libc/src/string/memcpy.cpp b/libc/src/string/memcpy.cpp
new file mode 100644
index 0000000000000..216e22938e7fd
--- /dev/null
+++ b/libc/src/string/memcpy.cpp
@@ -0,0 +1,22 @@
+//===--------------------- Implementation of memcpy -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/string/memcpy.h"
+#include "src/__support/common.h"
+#include "src/string/memcpy_arch_specific.h"
+
+namespace __llvm_libc {
+
+void *LLVM_LIBC_ENTRYPOINT(memcpy)(void *__restrict dst,
+                                   const void *__restrict src, size_t size) {
+  memcpy_no_return(reinterpret_cast<char *>(dst),
+                   reinterpret_cast<const char *>(src), size);
+  return dst;
+}
+
+} // namespace __llvm_libc
diff --git a/libc/src/string/memcpy.h b/libc/src/string/memcpy.h
new file mode 100644
index 0000000000000..a3ae4d40c874b
--- /dev/null
+++ b/libc/src/string/memcpy.h
@@ -0,0 +1,21 @@
+//===----------------- Implementation header for memcpy -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_STRING_MEMCPY_H
+#define LLVM_LIBC_SRC_STRING_MEMCPY_H
+
+#include "include/string.h"
+#include <stddef.h> // size_t
+
+namespace __llvm_libc {
+
+void *memcpy(void *__restrict, const void *__restrict, size_t);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_STRING_MEMCPY_H
diff --git a/libc/src/string/memcpy_arch_specific.h.def b/libc/src/string/memcpy_arch_specific.h.def
new file mode 100644
index 0000000000000..a9bb35223ef8b
--- /dev/null
+++ b/libc/src/string/memcpy_arch_specific.h.def
@@ -0,0 +1,65 @@
+//===-------------- Implementation of arch specific memcpy ----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_STRING_MEMORY_ARCH_H
+#define LLVM_LIBC_SRC_STRING_MEMORY_ARCH_H
+
+%%include_file(${memcpy_arch_specific})
+
+namespace __llvm_libc {
+
+// Design rationale
+// ================
+//
+// Using a profiler to observe size distributions for calls into libc
+// functions, it was found most operations act on a small number of bytes.
+// This makes it important to favor small sizes.
+//
+// The tests for `count` are in ascending order so the cost of branching is
+// proportional to the cost of copying.
+//
+// The function is written in C++ for several reasons:
+// - The compiler can __see__ the code, this is useful when performing Profile
+//   Guided Optimization as the optimized code can take advantage of branching
+//   probabilities.
+// - It also allows for easier customization and favors testing multiple
+//   implementation parameters.
+// - As compilers and processors get better, the generated code is improved
+//   with little change on the code side.
+static void memcpy_no_return(char *__restrict dst, const char *__restrict src,
+                             size_t count) {
+  if (count == 0)
+    return;
+  if (count == 1)
+    return Copy<1>(dst, src);
+  if (count == 2)
+    return Copy<2>(dst, src);
+  if (count == 3)
+    return Copy<3>(dst, src);
+  if (count == 4)
+    return Copy<4>(dst, src);
+  if (count < 8)
+    return CopyOverlap<4>(dst, src, count);
+  if (count == 8)
+    return Copy<8>(dst, src);
+  if (count < 16)
+    return CopyOverlap<8>(dst, src, count);
+  if (count == 16)
+    return Copy<16>(dst, src);
+  if (count < 32)
+    return CopyOverlap<16>(dst, src, count);
+  if (count < 64)
+    return CopyOverlap<32>(dst, src, count);
+  if (count < 128)
+    return CopyOverlap<64>(dst, src, count);
+  CopyGE128(dst, src, count);
+}
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_STRING_MEMORY_ARCH_H
diff --git a/libc/src/string/memory_utils/CMakeLists.txt b/libc/src/string/memory_utils/CMakeLists.txt
index 259ed0a758281..b826f1f68707f 100644
--- a/libc/src/string/memory_utils/CMakeLists.txt
+++ b/libc/src/string/memory_utils/CMakeLists.txt
@@ -12,6 +12,9 @@ add_gen_header(
 
 add_header_library(
   memory_utils
-  HDRS utils.h
-  DEPENDS cacheline_size
+  HDRS
+    utils.h
+    memcpy_utils.h
+  DEPENDS
+    cacheline_size
 )
diff --git a/libc/src/string/memory_utils/memcpy_utils.h b/libc/src/string/memory_utils/memcpy_utils.h
new file mode 100644
index 0000000000000..c69e557574c05
--- /dev/null
+++ b/libc/src/string/memory_utils/memcpy_utils.h
@@ -0,0 +1,100 @@
+//===---------------------------- Memcpy utils ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MEMORY_UTILS_MEMCPY_UTILS_H
+#define LLVM_LIBC_SRC_MEMORY_UTILS_MEMCPY_UTILS_H
+
+#include "src/string/memory_utils/utils.h"
+#include <stddef.h> // size_t
+
+// __builtin_memcpy_inline guarantees to never call external functions.
+// Unfortunately it is not widely available.
+#if defined(__clang__) && __has_builtin(__builtin_memcpy_inline)
+#define USE_BUILTIN_MEMCPY_INLINE
+#elif defined(__GNUC__)
+#define USE_BUILTIN_MEMCPY
+#endif
+
+// This is useful for testing.
+#if defined(LLVM_LIBC_MEMCPY_MONITOR)
+extern "C" void LLVM_LIBC_MEMCPY_MONITOR(char *__restrict,
+                                         const char *__restrict, size_t);
+#endif
+
+namespace __llvm_libc {
+
+// Copies `kBlockSize` bytes from `src` to `dst`.
+template <size_t kBlockSize>
+static void Copy(char *__restrict dst, const char *__restrict src) {
+#if defined(LLVM_LIBC_MEMCPY_MONITOR)
+  LLVM_LIBC_MEMCPY_MONITOR(dst, src, kBlockSize);
+#elif defined(USE_BUILTIN_MEMCPY_INLINE)
+  __builtin_memcpy_inline(dst, src, kBlockSize);
+#elif defined(USE_BUILTIN_MEMCPY)
+  __builtin_memcpy(dst, src, kBlockSize);
+#else
+  for (size_t i = 0; i < kBlockSize; ++i)
+    dst[i] = src[i];
+#endif
+}
+
+// Copies `kBlockSize` bytes from `src + count - kBlockSize` to
+// `dst + count - kBlockSize`.
+// Precondition: `count >= kBlockSize`.
+template <size_t kBlockSize>
+static void CopyLastBlock(char *__restrict dst, const char *__restrict src,
+                          size_t count) {
+  const size_t offset = count - kBlockSize;
+  Copy<kBlockSize>(dst + offset, src + offset);
+}
+
+// Copies `kBlockSize` bytes twice with an overlap between the two.
+//
+// [1234567812345678123]
+// [__XXXXXXXXXXXXXX___]
+// [__XXXXXXXX_________]
+// [________XXXXXXXX___]
+//
+// Precondition: `count >= kBlockSize && count <= kBlockSize`.
+template <size_t kBlockSize>
+static void CopyOverlap(char *__restrict dst, const char *__restrict src,
+                        size_t count) {
+  Copy<kBlockSize>(dst, src);
+  CopyLastBlock<kBlockSize>(dst, src, count);
+}
+
+// Copies `count` bytes by blocks of `kBlockSize` bytes.
+// Copies at the start and end of the buffer are unaligned.
+// Copies in the middle of the buffer are aligned to `kBlockSize`.
+//
+// e.g. with
+// [12345678123456781234567812345678]
+// [__XXXXXXXXXXXXXXXXXXXXXXXXXXX___]
+// [__XXXXXXXX______________________]
+// [________XXXXXXXX________________]
+// [________________XXXXXXXX________]
+// [_____________________XXXXXXXX___]
+//
+// Precondition: `count > 2 * kBlockSize` for efficiency.
+//               `count >= kBlockSize` for correctness.
+template <size_t kBlockSize>
+static void CopyAligned(char *__restrict dst, const char *__restrict src,
+                        size_t count) {
+  Copy<kBlockSize>(dst, src); // Copy first block
+
+  // Copy aligned blocks
+  size_t offset = kBlockSize - offset_from_last_aligned<kBlockSize>(dst);
+  for (; offset + kBlockSize < count; offset += kBlockSize)
+    Copy<kBlockSize>(dst + offset, src + offset);
+
+  CopyLastBlock<kBlockSize>(dst, src, count); // Copy last block
+}
+
+} // namespace __llvm_libc
+
+#endif //  LLVM_LIBC_SRC_MEMORY_UTILS_MEMCPY_UTILS_H
diff --git a/libc/src/string/memory_utils/utils.h b/libc/src/string/memory_utils/utils.h
index 33df113213b5c..af9b6aeeee513 100644
--- a/libc/src/string/memory_utils/utils.h
+++ b/libc/src/string/memory_utils/utils.h
@@ -43,6 +43,11 @@ static constexpr size_t ge_power2(size_t value) {
   return is_power2_or_zero(value) ? value : 1ULL << (log2(value) + 1);
 }
 
+template <size_t alignment> intptr_t offset_from_last_aligned(const void *ptr) {
+  static_assert(is_power2(alignment), "alignment must be a power of 2");
+  return reinterpret_cast<uintptr_t>(ptr) & (alignment - 1U);
+}
+
 template <size_t alignment> intptr_t offset_to_next_aligned(const void *ptr) {
   static_assert(is_power2(alignment), "alignment must be a power of 2");
   // The logic is not straightforward and involves unsigned modulo arithmetic
@@ -51,7 +56,7 @@ template <size_t alignment> intptr_t offset_to_next_aligned(const void *ptr) {
 }
 
 // Returns the offset from `ptr` to the next cache line.
-static intptr_t offset_to_next_cache_line(const void *ptr) {
+static inline intptr_t offset_to_next_cache_line(const void *ptr) {
   return offset_to_next_aligned<LLVM_LIBC_CACHELINE_SIZE>(ptr);
 }
 
diff --git a/libc/src/string/x86/CMakeLists.txt b/libc/src/string/x86/CMakeLists.txt
new file mode 100644
index 0000000000000..b5365733fb808
--- /dev/null
+++ b/libc/src/string/x86/CMakeLists.txt
@@ -0,0 +1,4 @@
+add_memcpy("memcpy_${LIBC_TARGET_MACHINE}_opt_none" REJECT "${ALL_CPU_FEATURES}")
+add_memcpy("memcpy_${LIBC_TARGET_MACHINE}_opt_sse" REQUIRE "SSE" REJECT "SSE2")
+add_memcpy("memcpy_${LIBC_TARGET_MACHINE}_opt_avx" REQUIRE "AVX" REJECT "AVX2")
+add_memcpy("memcpy_${LIBC_TARGET_MACHINE}_opt_avx512f" REQUIRE "AVX512F")
diff --git a/libc/src/string/x86/memcpy_arch_specific.h.inc b/libc/src/string/x86/memcpy_arch_specific.h.inc
new file mode 100644
index 0000000000000..ace98ba2e8111
--- /dev/null
+++ b/libc/src/string/x86/memcpy_arch_specific.h.inc
@@ -0,0 +1,35 @@
+#include "src/string/memory_utils/memcpy_utils.h"
+
+namespace __llvm_libc {
+
+static void CopyRepMovsb(char *__restrict dst, const char *__restrict src,
+                         size_t count) {
+  // FIXME: Add MSVC suppport with
+  // #include <intrin.h>
+  // __movsb(reinterpret_cast<unsigned char *>(dst),
+  //         reinterpret_cast<const unsigned char *>(src), count);
+  asm volatile("rep movsb" : "+D"(dst), "+S"(src), "+c"(count) : : "memory");
+}
+
+#if defined(__AVX__)
+#define BEST_SIZE 64
+#else
+#define BEST_SIZE 32
+#endif
+
+static void CopyGE128(char *__restrict dst, const char *__restrict src,
+                      size_t count) {
+#if defined(__AVX__)
+  if (count < 256)
+    return CopyOverlap<128>(dst, src, count);
+#endif
+  // kRepMovsBSize == -1 : Only CopyAligned is used.
+  // kRepMovsBSize ==  0 : Only RepMovsb is used.
+  // else CopyAligned is used to to kRepMovsBSize and then RepMovsb.
+  constexpr size_t kRepMovsBSize = -1;
+  if (count <= kRepMovsBSize)
+    return CopyAligned<BEST_SIZE>(dst, src, count);
+  CopyRepMovsb(dst, src, count);
+}
+
+} // namespace __llvm_libc
diff --git a/libc/test/src/signal/CMakeLists.txt b/libc/test/src/signal/CMakeLists.txt
index 38f6961920d16..db919b6f5d01d 100644
--- a/libc/test/src/signal/CMakeLists.txt
+++ b/libc/test/src/signal/CMakeLists.txt
@@ -11,6 +11,21 @@ add_libc_unittest(
     signal_h
 )
 
+add_libc_unittest(
+  sigaction_test
+  SUITE
+    libc_signal_unittests
+  SRCS
+    sigaction_test.cpp
+  DEPENDS
+    sigaction
+    raise
+    signal_h
+    errno_h
+    __errno_location
+    __restore
+)
+
 add_libc_unittest(
   sigprocmask_test
   SUITE
diff --git a/libc/test/src/signal/sigaction_test.cpp b/libc/test/src/signal/sigaction_test.cpp
new file mode 100644
index 0000000000000..fc7d143a10df4
--- /dev/null
+++ b/libc/test/src/signal/sigaction_test.cpp
@@ -0,0 +1,66 @@
+//===----------------------- Unittests for sigaction ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "include/errno.h"
+#define __LLVM_LIBC_INTERNAL_SIGACTION
+#include "include/signal.h"
+#include "src/signal/raise.h"
+#include "src/signal/sigaction.h"
+
+#include "utils/UnitTest/ErrnoSetterMatcher.h"
+#include "utils/UnitTest/Test.h"
+
+using __llvm_libc::testing::ErrnoSetterMatcher::Fails;
+using __llvm_libc::testing::ErrnoSetterMatcher::Succeeds;
+
+TEST(Sigaction, Invalid) {
+  // -1 is a much larger signal that NSIG, so this should fail.
+  EXPECT_THAT(__llvm_libc::sigaction(-1, nullptr, nullptr), Fails(EINVAL));
+}
+
+// SIGKILL cannot have its action changed, but it can be examined.
+TEST(Sigaction, Sigkill) {
+  struct __sigaction action;
+  EXPECT_THAT(__llvm_libc::sigaction(SIGKILL, nullptr, &action), Succeeds());
+  EXPECT_THAT(__llvm_libc::sigaction(SIGKILL, &action, nullptr), Fails(EINVAL));
+}
+
+static int sigusr1Count;
+static bool correctSignal;
+
+TEST(Sigaction, CustomAction) {
+  // Zero this incase tests get run multiple times in the future.
+  sigusr1Count = 0;
+
+  struct __sigaction action;
+  EXPECT_THAT(__llvm_libc::sigaction(SIGUSR1, nullptr, &action), Succeeds());
+
+  action.sa_handler = +[](int signal) {
+    correctSignal = signal == SIGUSR1;
+    sigusr1Count++;
+  };
+  EXPECT_THAT(__llvm_libc::sigaction(SIGUSR1, &action, nullptr), Succeeds());
+
+  __llvm_libc::raise(SIGUSR1);
+  EXPECT_EQ(sigusr1Count, 1);
+  EXPECT_TRUE(correctSignal);
+
+  action.sa_handler = SIG_DFL;
+  EXPECT_THAT(__llvm_libc::sigaction(SIGUSR1, &action, nullptr), Succeeds());
+
+  EXPECT_DEATH([] { __llvm_libc::raise(SIGUSR1); }, SIGUSR1);
+}
+
+TEST(Sigaction, Ignore) {
+  struct __sigaction action;
+  EXPECT_THAT(__llvm_libc::sigaction(SIGUSR1, nullptr, &action), Succeeds());
+  action.sa_handler = SIG_IGN;
+  EXPECT_THAT(__llvm_libc::sigaction(SIGUSR1, &action, nullptr), Succeeds());
+
+  EXPECT_EXITS([] { __llvm_libc::raise(SIGUSR1); }, 0);
+}
diff --git a/libc/test/src/string/CMakeLists.txt b/libc/test/src/string/CMakeLists.txt
index 258937c7f4f61..43536e96d5525 100644
--- a/libc/test/src/string/CMakeLists.txt
+++ b/libc/test/src/string/CMakeLists.txt
@@ -22,3 +22,24 @@ add_libc_unittest(
   DEPENDS
     strcpy
 )
+
+# Tests all implementations of memcpy that can run on the host.
+get_property(memcpy_implementations GLOBAL PROPERTY memcpy_implementations)
+foreach(memcpy_config_name IN LISTS memcpy_implementations)
+  get_target_property(require_cpu_features ${memcpy_config_name} REQUIRE_CPU_FEATURES)
+  host_supports(can_run "${require_cpu_features}")
+  if(can_run)
+    add_libc_unittest(
+      ${memcpy_config_name}_test
+      SUITE
+        libc_string_unittests
+      SRCS
+        memcpy_test.cpp
+      DEPENDS
+        ${memcpy_config_name}
+    )
+  else()
+    message(STATUS "Skipping test for '${memcpy_config_name}' insufficient host cpu features")
+  endif()
+endforeach()
+
diff --git a/libc/test/src/string/memcpy_test.cpp b/libc/test/src/string/memcpy_test.cpp
new file mode 100644
index 0000000000000..c83cdb60fc96f
--- /dev/null
+++ b/libc/test/src/string/memcpy_test.cpp
@@ -0,0 +1,53 @@
+//===----------------------- Unittests for memcpy -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "utils/CPP/ArrayRef.h"
+#include "utils/UnitTest/Test.h"
+#include "src/string/memcpy.h"
+
+using __llvm_libc::cpp::Array;
+using __llvm_libc::cpp::ArrayRef;
+using __llvm_libc::cpp::MutableArrayRef;
+using Data = Array<char, 2048>;
+
+static const ArrayRef<char> kNumbers("0123456789", 10);
+static const ArrayRef<char> kDeadcode("DEADC0DE", 8);
+
+// Returns a Data object filled with a repetition of `filler`.
+Data getData(ArrayRef<char> filler) {
+  Data out;
+  for (size_t i = 0; i < out.size(); ++i)
+    out[i] = filler[i % filler.size()];
+  return out;
+}
+
+TEST(MemcpyTest, Thorough) {
+  const Data groundtruth = getData(kNumbers);
+  const Data dirty = getData(kDeadcode);
+  for (size_t count = 0; count < 1024; ++count) {
+    for (size_t align = 0; align < 64; ++align) {
+      auto buffer = dirty;
+      const char *const src = groundtruth.data();
+      char *const dst = &buffer[align];
+      __llvm_libc::memcpy(dst, src, count);
+      // Everything before copy is untouched.
+      for (size_t i = 0; i < align; ++i)
+        ASSERT_EQ(buffer[i], dirty[i]);
+      // Everything in between is copied.
+      for (size_t i = 0; i < count; ++i)
+        ASSERT_EQ(buffer[align + i], groundtruth[i]);
+      // Everything after copy is untouched.
+      for (size_t i = align + count; i < dirty.size(); ++i)
+        ASSERT_EQ(buffer[i], dirty[i]);
+    }
+  }
+}
+
+// FIXME: Add tests with reads and writes on the boundary of a read/write
+// protected page to check we're not reading nor writing prior/past the allowed
+// regions.
diff --git a/libc/test/src/string/memory_utils/CMakeLists.txt b/libc/test/src/string/memory_utils/CMakeLists.txt
index e3ec8eb40cf3e..c02fa865fcaa0 100644
--- a/libc/test/src/string/memory_utils/CMakeLists.txt
+++ b/libc/test/src/string/memory_utils/CMakeLists.txt
@@ -4,7 +4,14 @@ add_libc_unittest(
     libc_string_unittests
   SRCS
     utils_test.cpp
+    memcpy_utils_test.cpp
   DEPENDS
     memory_utils
     standalone_cpp
 )
+
+target_compile_definitions(
+  utils_test
+  PRIVATE
+  LLVM_LIBC_MEMCPY_MONITOR=memcpy_monitor
+)
diff --git a/libc/test/src/string/memory_utils/memcpy_utils_test.cpp b/libc/test/src/string/memory_utils/memcpy_utils_test.cpp
new file mode 100644
index 0000000000000..813e86fe65dbd
--- /dev/null
+++ b/libc/test/src/string/memory_utils/memcpy_utils_test.cpp
@@ -0,0 +1,208 @@
+//===-------------------- Unittests for memory_utils ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/string/memory_utils/memcpy_utils.h"
+#include "utils/CPP/Array.h"
+#include "utils/UnitTest/Test.h"
+
+#include <assert.h>
+#include <stdint.h> // uintptr_t
+
+#ifndef LLVM_LIBC_MEMCPY_MONITOR
+#error LLVM_LIBC_MEMCPY_MONITOR must be defined for this test.
+#endif
+
+namespace __llvm_libc {
+
+struct Buffer {
+  static constexpr size_t kMaxBuffer = 1024;
+  char buffer[kMaxBuffer + 1];
+  size_t last = 0;
+
+  void Clear() {
+    last = 0;
+    for (size_t i = 0; i < kMaxBuffer; ++i)
+      buffer[i] = '0';
+    buffer[kMaxBuffer] = '\0';
+  }
+
+  void Increment(const void *ptr) {
+    const auto offset = reinterpret_cast<uintptr_t>(ptr);
+    assert(offset < kMaxBuffer);
+    ++buffer[offset];
+    if (offset > last)
+      last = offset;
+  }
+
+  char *Finish() {
+    assert(last < kMaxBuffer);
+    buffer[last + 1] = '\0';
+    return buffer;
+  }
+};
+
+struct Trace {
+  Buffer read;
+  Buffer write;
+
+  void Add(char *__restrict dst, const char *__restrict src, size_t count) {
+    for (size_t i = 0; i < count; ++i)
+      read.Increment(src + i);
+    for (size_t i = 0; i < count; ++i)
+      write.Increment(dst + i);
+  }
+
+  void Clear() {
+    read.Clear();
+    write.Clear();
+  }
+
+  char *Read() { return read.Finish(); }
+  char *Write() { return write.Finish(); }
+};
+
+static Trace &GetTrace() {
+  static thread_local Trace events;
+  return events;
+}
+
+extern "C" void LLVM_LIBC_MEMCPY_MONITOR(char *__restrict dst,
+                                         const char *__restrict src,
+                                         size_t count) {
+  GetTrace().Add(dst, src, count);
+}
+
+char *I(uintptr_t offset) { return reinterpret_cast<char *>(offset); }
+
+TEST(MemcpyUtilsTest, CopyTrivial) {
+  auto &trace = GetTrace();
+
+  trace.Clear();
+  Copy<1>(I(0), I(0));
+  EXPECT_STREQ(trace.Write(), "1");
+  EXPECT_STREQ(trace.Read(), "1");
+
+  trace.Clear();
+  Copy<2>(I(0), I(0));
+  EXPECT_STREQ(trace.Write(), "11");
+  EXPECT_STREQ(trace.Read(), "11");
+
+  trace.Clear();
+  Copy<4>(I(0), I(0));
+  EXPECT_STREQ(trace.Write(), "1111");
+  EXPECT_STREQ(trace.Read(), "1111");
+
+  trace.Clear();
+  Copy<8>(I(0), I(0));
+  EXPECT_STREQ(trace.Write(), "11111111");
+  EXPECT_STREQ(trace.Read(), "11111111");
+
+  trace.Clear();
+  Copy<16>(I(0), I(0));
+  EXPECT_STREQ(trace.Write(), "1111111111111111");
+  EXPECT_STREQ(trace.Read(), "1111111111111111");
+
+  trace.Clear();
+  Copy<32>(I(0), I(0));
+  EXPECT_STREQ(trace.Write(), "11111111111111111111111111111111");
+  EXPECT_STREQ(trace.Read(), "11111111111111111111111111111111");
+
+  trace.Clear();
+  Copy<64>(I(0), I(0));
+  EXPECT_STREQ(
+      trace.Write(),
+      "1111111111111111111111111111111111111111111111111111111111111111");
+  EXPECT_STREQ(
+      trace.Read(),
+      "1111111111111111111111111111111111111111111111111111111111111111");
+}
+
+TEST(MemcpyUtilsTest, CopyOffset) {
+  auto &trace = GetTrace();
+
+  trace.Clear();
+  Copy<1>(I(3), I(1));
+  EXPECT_STREQ(trace.Write(), "0001");
+  EXPECT_STREQ(trace.Read(), "01");
+
+  trace.Clear();
+  Copy<1>(I(2), I(1));
+  EXPECT_STREQ(trace.Write(), "001");
+  EXPECT_STREQ(trace.Read(), "01");
+}
+
+TEST(MemcpyUtilsTest, CopyOverlap) {
+  auto &trace = GetTrace();
+
+  trace.Clear();
+  CopyOverlap<2>(I(0), I(0), 2);
+  EXPECT_STREQ(trace.Write(), "22");
+  EXPECT_STREQ(trace.Read(), "22");
+
+  trace.Clear();
+  CopyOverlap<2>(I(0), I(0), 3);
+  EXPECT_STREQ(trace.Write(), "121");
+  EXPECT_STREQ(trace.Read(), "121");
+
+  trace.Clear();
+  CopyOverlap<2>(I(0), I(0), 4);
+  EXPECT_STREQ(trace.Write(), "1111");
+  EXPECT_STREQ(trace.Read(), "1111");
+
+  trace.Clear();
+  CopyOverlap<4>(I(2), I(1), 7);
+  EXPECT_STREQ(trace.Write(), "001112111");
+  EXPECT_STREQ(trace.Read(), "01112111");
+}
+
+TEST(MemcpyUtilsTest, CopyAligned) {
+  auto &trace = GetTrace();
+  // Destination is aligned already.
+  //   "1111000000000"
+  // + "0000111100000"
+  // + "0000000011110"
+  // + "0000000001111"
+  // = "1111111112221"
+  trace.Clear();
+  CopyAligned<4>(I(0), I(0), 13);
+  EXPECT_STREQ(trace.Write(), "1111111112221");
+  EXPECT_STREQ(trace.Read(), "1111111112221");
+
+  // Misaligned destination
+  //   "01111000000000"
+  // + "00001111000000"
+  // + "00000000111100"
+  // + "00000000001111"
+  // = "01112111112211"
+  trace.Clear();
+  CopyAligned<4>(I(1), I(0), 13);
+  EXPECT_STREQ(trace.Write(), "01112111112211");
+  EXPECT_STREQ(trace.Read(), "1112111112211");
+}
+
+TEST(MemcpyUtilsTest, MaxReloads) {
+  auto &trace = GetTrace();
+  for (size_t alignment = 0; alignment < 32; ++alignment) {
+    for (size_t count = 64; count < 768; ++count) {
+      trace.Clear();
+      // We should never reload more than twice when copying from count = 2x32.
+      CopyAligned<32>(I(alignment), I(0), count);
+      const char *const written = trace.Write();
+      // First bytes are untouched.
+      for (size_t i = 0; i < alignment; ++i)
+        EXPECT_EQ(written[i], '0');
+      // Next bytes are loaded once or twice but no more.
+      for (size_t i = alignment; i < count; ++i) {
+        EXPECT_GE(written[i], '1');
+        EXPECT_LE(written[i], '2');
+      }
+    }
+  }
+}
+
+} // namespace __llvm_libc
diff --git a/libc/test/src/string/memory_utils/utils_test.cpp b/libc/test/src/string/memory_utils/utils_test.cpp
index 5a14cb1df8e49..c1564334c640b 100644
--- a/libc/test/src/string/memory_utils/utils_test.cpp
+++ b/libc/test/src/string/memory_utils/utils_test.cpp
@@ -87,6 +87,14 @@ TEST(UtilsTest, OffsetToNextAligned) {
   EXPECT_EQ(offset_to_next_aligned<32>(forge(16)), I(16));
 }
 
+TEST(UtilsTest, OffsetFromLastAligned) {
+  EXPECT_EQ(offset_from_last_aligned<16>(forge(0)), I(0));
+  EXPECT_EQ(offset_from_last_aligned<16>(forge(1)), I(1));
+  EXPECT_EQ(offset_from_last_aligned<16>(forge(16)), I(0));
+  EXPECT_EQ(offset_from_last_aligned<16>(forge(15)), I(15));
+  EXPECT_EQ(offset_from_last_aligned<32>(forge(16)), I(16));
+}
+
 TEST(UtilsTest, OffsetToNextCacheLine) {
   EXPECT_GT(LLVM_LIBC_CACHELINE_SIZE, 0);
   EXPECT_EQ(offset_to_next_cache_line(forge(0)), I(0));
diff --git a/libc/utils/buildbot/Dockerfile b/libc/utils/buildbot/Dockerfile
index 21369961e865d..b63c117939218 100644
--- a/libc/utils/buildbot/Dockerfile
+++ b/libc/utils/buildbot/Dockerfile
@@ -8,6 +8,9 @@ RUN apt-get install -y build-essential clang subversion git vim \
   ninja-build
 RUN python -m pip install buildbot-slave==0.8.12
 
+# Temporary dependecies for AOR tests.
+RUN apt-get install -y libmpfr-dev libmpc-dev
+
 # Change linker to gold.
 RUN update-alternatives --install "/usr/bin/ld" "ld" "/usr/bin/ld.gold" 20
 
diff --git a/libc/utils/testutils/ExecuteFunctionUnix.cpp b/libc/utils/testutils/ExecuteFunctionUnix.cpp
index e920e50f71472..1ddb24d812d73 100644
--- a/libc/utils/testutils/ExecuteFunctionUnix.cpp
+++ b/libc/utils/testutils/ExecuteFunctionUnix.cpp
@@ -67,8 +67,12 @@ ProcessStatus invokeInSubprocess(FunctionCaller *Func, unsigned timeoutMS) {
   }
 
   int WStatus = 0;
-  int status = ::waitpid(Pid, &WStatus, WNOHANG);
-  assert(status == Pid && "wait call should not block here");
+  // Wait on the pid of the subprocess here so it gets collected by the system
+  // and doesn't turn into a zombie.
+  pid_t status = ::waitpid(Pid, &WStatus, 0);
+  if (status == -1)
+    return ProcessStatus::Error("waitpid(2) failed");
+  assert(status == Pid);
   (void)status;
   return {WStatus};
 }
diff --git a/libcxx/include/codecvt b/libcxx/include/codecvt
index 5ea411ea781b7..05fa765c31804 100644
--- a/libcxx/include/codecvt
+++ b/libcxx/include/codecvt
@@ -102,11 +102,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -137,11 +137,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -172,11 +172,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <class _Elem, unsigned long _Maxcode = 0x10ffff,
@@ -225,11 +225,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -260,11 +260,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -295,11 +295,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -330,11 +330,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -365,11 +365,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -400,11 +400,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <class _Elem, unsigned long _Maxcode = 0x10ffff,
@@ -453,11 +453,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -488,11 +488,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <>
@@ -523,11 +523,11 @@ protected:
     virtual result
         do_unshift(state_type& __st,
                    extern_type* __to, extern_type* __to_end, extern_type*& __to_nxt) const;
-    virtual int do_encoding() const throw();
-    virtual bool do_always_noconv() const throw();
+    virtual int do_encoding() const _NOEXCEPT;
+    virtual bool do_always_noconv() const _NOEXCEPT;
     virtual int do_length(state_type&, const extern_type* __frm, const extern_type* __end,
                           size_t __mx) const;
-    virtual int do_max_length() const throw();
+    virtual int do_max_length() const _NOEXCEPT;
 };
 
 template <class _Elem, unsigned long _Maxcode = 0x10ffff,
diff --git a/libcxx/include/exception b/libcxx/include/exception
index c7dcac2b2b334..8e32979f5749a 100644
--- a/libcxx/include/exception
+++ b/libcxx/include/exception
@@ -98,6 +98,8 @@ class _LIBCPP_EXCEPTION_ABI exception
 {
 public:
     _LIBCPP_INLINE_VISIBILITY exception() _NOEXCEPT {}
+    _LIBCPP_INLINE_VISIBILITY exception(const exception&) _NOEXCEPT = default;
+
     virtual ~exception() _NOEXCEPT;
     virtual const char* what() const _NOEXCEPT;
 };
diff --git a/libcxx/include/filesystem b/libcxx/include/filesystem
index 0f7a4d5569888..1363b630271ac 100644
--- a/libcxx/include/filesystem
+++ b/libcxx/include/filesystem
@@ -1346,6 +1346,7 @@ public:
   _LIBCPP_INLINE_VISIBILITY
   const path& path2() const noexcept { return __storage_->__p2_; }
 
+  filesystem_error(const filesystem_error&) = default;
   ~filesystem_error() override; // key function
 
   _LIBCPP_INLINE_VISIBILITY
diff --git a/libcxx/include/future b/libcxx/include/future
index 751d122a60002..bdf74e3055c03 100644
--- a/libcxx/include/future
+++ b/libcxx/include/future
@@ -506,6 +506,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY
     const error_code& code() const _NOEXCEPT {return __ec_;}
 
+    future_error(const future_error&) _NOEXCEPT = default;
     virtual ~future_error() _NOEXCEPT;
 };
 
diff --git a/libcxx/include/ios b/libcxx/include/ios
index 88efefb46ff2b..d6967edbccdb7 100644
--- a/libcxx/include/ios
+++ b/libcxx/include/ios
@@ -431,7 +431,8 @@ class _LIBCPP_EXCEPTION_ABI ios_base::failure
 public:
     explicit failure(const string& __msg, const error_code& __ec = io_errc::stream);
     explicit failure(const char* __msg, const error_code& __ec = io_errc::stream);
-    virtual ~failure() throw();
+    failure(const failure&) _NOEXCEPT = default;
+    virtual ~failure() _NOEXCEPT;
 };
 
 _LIBCPP_NORETURN inline _LIBCPP_INLINE_VISIBILITY
diff --git a/libcxx/include/memory b/libcxx/include/memory
index bf31bfca5130d..729b8b5c874ec 100644
--- a/libcxx/include/memory
+++ b/libcxx/include/memory
@@ -2198,39 +2198,39 @@ private:
 public:
     typedef _Tp element_type;
 
-    _LIBCPP_INLINE_VISIBILITY explicit auto_ptr(_Tp* __p = 0) throw() : __ptr_(__p) {}
-    _LIBCPP_INLINE_VISIBILITY auto_ptr(auto_ptr& __p) throw() : __ptr_(__p.release()) {}
-    template<class _Up> _LIBCPP_INLINE_VISIBILITY auto_ptr(auto_ptr<_Up>& __p) throw()
+    _LIBCPP_INLINE_VISIBILITY explicit auto_ptr(_Tp* __p = 0) _NOEXCEPT : __ptr_(__p) {}
+    _LIBCPP_INLINE_VISIBILITY auto_ptr(auto_ptr& __p) _NOEXCEPT : __ptr_(__p.release()) {}
+    template<class _Up> _LIBCPP_INLINE_VISIBILITY auto_ptr(auto_ptr<_Up>& __p) _NOEXCEPT
         : __ptr_(__p.release()) {}
-    _LIBCPP_INLINE_VISIBILITY auto_ptr& operator=(auto_ptr& __p) throw()
+    _LIBCPP_INLINE_VISIBILITY auto_ptr& operator=(auto_ptr& __p) _NOEXCEPT
         {reset(__p.release()); return *this;}
-    template<class _Up> _LIBCPP_INLINE_VISIBILITY auto_ptr& operator=(auto_ptr<_Up>& __p) throw()
+    template<class _Up> _LIBCPP_INLINE_VISIBILITY auto_ptr& operator=(auto_ptr<_Up>& __p) _NOEXCEPT
         {reset(__p.release()); return *this;}
-    _LIBCPP_INLINE_VISIBILITY auto_ptr& operator=(auto_ptr_ref<_Tp> __p) throw()
+    _LIBCPP_INLINE_VISIBILITY auto_ptr& operator=(auto_ptr_ref<_Tp> __p) _NOEXCEPT
         {reset(__p.__ptr_); return *this;}
-    _LIBCPP_INLINE_VISIBILITY ~auto_ptr() throw() {delete __ptr_;}
+    _LIBCPP_INLINE_VISIBILITY ~auto_ptr() _NOEXCEPT {delete __ptr_;}
 
-    _LIBCPP_INLINE_VISIBILITY _Tp& operator*() const throw()
+    _LIBCPP_INLINE_VISIBILITY _Tp& operator*() const _NOEXCEPT
         {return *__ptr_;}
-    _LIBCPP_INLINE_VISIBILITY _Tp* operator->() const throw() {return __ptr_;}
-    _LIBCPP_INLINE_VISIBILITY _Tp* get() const throw() {return __ptr_;}
-    _LIBCPP_INLINE_VISIBILITY _Tp* release() throw()
+    _LIBCPP_INLINE_VISIBILITY _Tp* operator->() const _NOEXCEPT {return __ptr_;}
+    _LIBCPP_INLINE_VISIBILITY _Tp* get() const _NOEXCEPT {return __ptr_;}
+    _LIBCPP_INLINE_VISIBILITY _Tp* release() _NOEXCEPT
     {
         _Tp* __t = __ptr_;
         __ptr_ = 0;
         return __t;
     }
-    _LIBCPP_INLINE_VISIBILITY void reset(_Tp* __p = 0) throw()
+    _LIBCPP_INLINE_VISIBILITY void reset(_Tp* __p = 0) _NOEXCEPT
     {
         if (__ptr_ != __p)
             delete __ptr_;
         __ptr_ = __p;
     }
 
-    _LIBCPP_INLINE_VISIBILITY auto_ptr(auto_ptr_ref<_Tp> __p) throw() : __ptr_(__p.__ptr_) {}
-    template<class _Up> _LIBCPP_INLINE_VISIBILITY operator auto_ptr_ref<_Up>() throw()
+    _LIBCPP_INLINE_VISIBILITY auto_ptr(auto_ptr_ref<_Tp> __p) _NOEXCEPT : __ptr_(__p.__ptr_) {}
+    template<class _Up> _LIBCPP_INLINE_VISIBILITY operator auto_ptr_ref<_Up>() _NOEXCEPT
         {auto_ptr_ref<_Up> __t; __t.__ptr_ = release(); return __t;}
-    template<class _Up> _LIBCPP_INLINE_VISIBILITY operator auto_ptr<_Up>() throw()
+    template<class _Up> _LIBCPP_INLINE_VISIBILITY operator auto_ptr<_Up>() _NOEXCEPT
         {return auto_ptr<_Up>(release());}
 };
 
@@ -3457,6 +3457,8 @@ class _LIBCPP_EXCEPTION_ABI bad_weak_ptr
     : public std::exception
 {
 public:
+    bad_weak_ptr() _NOEXCEPT = default;
+    bad_weak_ptr(const bad_weak_ptr&) _NOEXCEPT = default;
     virtual ~bad_weak_ptr() _NOEXCEPT;
     virtual const char* what() const  _NOEXCEPT;
 };
diff --git a/libcxx/include/random b/libcxx/include/random
index 7c4054f7eea83..ce3d135e064ab 100644
--- a/libcxx/include/random
+++ b/libcxx/include/random
@@ -4048,10 +4048,12 @@ binomial_distribution<_IntType>::operator()(_URNG& __g, const param_type& __pr)
     result_type __rd = __ru;
     while (true)
     {
+        bool __break = true;
         if (__rd >= 1)
         {
             __pd *= __rd / (__pr.__odds_ratio_ * (__pr.__t_ - __rd + 1));
             __u -= __pd;
+            __break = false;
             if (__u < 0)
                 return __rd - 1;
         }
@@ -4062,9 +4064,12 @@ binomial_distribution<_IntType>::operator()(_URNG& __g, const param_type& __pr)
         {
             __pu *= (__pr.__t_ - __ru + 1) * __pr.__odds_ratio_ / __ru;
             __u -= __pu;
+            __break = false;
             if (__u < 0)
                 return __ru;
         }
+        if (__break)
+            return 0;
     }
 }
 
diff --git a/libcxx/include/regex b/libcxx/include/regex
index 68cfbb2843477..e33ac25b8b385 100644
--- a/libcxx/include/regex
+++ b/libcxx/include/regex
@@ -977,7 +977,8 @@ class _LIBCPP_EXCEPTION_ABI regex_error
     regex_constants::error_type __code_;
 public:
     explicit regex_error(regex_constants::error_type __ecode);
-    virtual ~regex_error() throw();
+    regex_error(const regex_error&) _NOEXCEPT = default;
+    virtual ~regex_error() _NOEXCEPT;
      _LIBCPP_INLINE_VISIBILITY
     regex_constants::error_type code() const {return __code_;}
 };
diff --git a/libcxx/include/stdexcept b/libcxx/include/stdexcept
index 481f9043c50dc..7a7f367940995 100644
--- a/libcxx/include/stdexcept
+++ b/libcxx/include/stdexcept
@@ -129,6 +129,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit domain_error(const char* __s)   : logic_error(__s) {}
 
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    domain_error(const domain_error&) _NOEXCEPT = default;
     virtual ~domain_error() _NOEXCEPT;
 #endif
 };
@@ -141,6 +142,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit invalid_argument(const char* __s)   : logic_error(__s) {}
 
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    invalid_argument(const invalid_argument&) _NOEXCEPT = default;
     virtual ~invalid_argument() _NOEXCEPT;
 #endif
 };
@@ -152,6 +154,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit length_error(const string& __s) : logic_error(__s) {}
     _LIBCPP_INLINE_VISIBILITY explicit length_error(const char* __s)   : logic_error(__s) {}
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    length_error(const length_error&) _NOEXCEPT = default;
     virtual ~length_error() _NOEXCEPT;
 #endif
 };
@@ -164,6 +167,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit out_of_range(const char* __s)   : logic_error(__s) {}
 
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    out_of_range(const out_of_range&) _NOEXCEPT = default;
     virtual ~out_of_range() _NOEXCEPT;
 #endif
 };
@@ -176,6 +180,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit range_error(const char* __s)   : runtime_error(__s) {}
 
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    range_error(const range_error&) _NOEXCEPT = default;
     virtual ~range_error() _NOEXCEPT;
 #endif
 };
@@ -188,6 +193,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit overflow_error(const char* __s)   : runtime_error(__s) {}
 
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    overflow_error(const overflow_error&) _NOEXCEPT = default;
     virtual ~overflow_error() _NOEXCEPT;
 #endif
 };
@@ -200,6 +206,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY explicit underflow_error(const char* __s)   : runtime_error(__s) {}
 
 #ifndef _LIBCPP_ABI_VCRUNTIME
+    underflow_error(const underflow_error&) _NOEXCEPT = default;
     virtual ~underflow_error() _NOEXCEPT;
 #endif
 };
diff --git a/libcxx/include/system_error b/libcxx/include/system_error
index 05ef07950d059..74e889aa9ac74 100644
--- a/libcxx/include/system_error
+++ b/libcxx/include/system_error
@@ -469,6 +469,7 @@ public:
     system_error(int __ev, const error_category& __ecat, const string& __what_arg);
     system_error(int __ev, const error_category& __ecat, const char* __what_arg);
     system_error(int __ev, const error_category& __ecat);
+    system_error(const system_error&) _NOEXCEPT = default;
     ~system_error() _NOEXCEPT;
 
     _LIBCPP_INLINE_VISIBILITY
diff --git a/libcxx/include/typeinfo b/libcxx/include/typeinfo
index 74813cc5016df..8b86c61b974d4 100644
--- a/libcxx/include/typeinfo
+++ b/libcxx/include/typeinfo
@@ -319,6 +319,7 @@ class _LIBCPP_EXCEPTION_ABI bad_cast
 {
  public:
   bad_cast() _NOEXCEPT;
+  bad_cast(const bad_cast&) _NOEXCEPT = default;
   virtual ~bad_cast() _NOEXCEPT;
   virtual const char* what() const _NOEXCEPT;
 };
diff --git a/libcxx/test/std/numerics/rand/rand.dis/rand.dist.bern/rand.dist.bern.bin/eval.pass.cpp b/libcxx/test/std/numerics/rand/rand.dis/rand.dist.bern/rand.dist.bern.bin/eval.pass.cpp
index 7885ff6f7c02e..4a547ee75c537 100644
--- a/libcxx/test/std/numerics/rand/rand.dis/rand.dist.bern/rand.dist.bern.bin/eval.pass.cpp
+++ b/libcxx/test/std/numerics/rand/rand.dis/rand.dist.bern/rand.dist.bern.bin/eval.pass.cpp
@@ -19,6 +19,7 @@
 #include <numeric>
 #include <vector>
 #include <cassert>
+#include <sstream>
 
 #include "test_macros.h"
 
@@ -508,6 +509,145 @@ test11()
 //    assert(kurtosis == x_kurtosis);
 }
 
+void
+test12()
+{
+    typedef std::binomial_distribution<> D;
+    typedef std::mt19937 G;
+
+    G g;
+    D d(128738942, 1.6941441471907126e-08);
+
+    std::string state = "1740222423 1665913615 1140355283 124152834 434145240"
+                        "2553002688 4143320714 1810519474 447745536 1439409640 1596060396 1243637295"
+                        "452117361 734967774 3276935081 35650473 682607275 4208082251 3209082916"
+                        "638915489 4127185595 2859436515 309105096 837982734 796854873 4271538185"
+                        "2447193692 607594006 4035165093 4230150671 2567368782 1000242037 2469514821"
+                        "1843373462 1751084370 1033341643 3506396674 4169541123 1191187784 3479797390"
+                        "3785371742 1475391851 878730063 2661164420 63166678 4127393159 2797714867"
+                        "1295211604 2717051330 1009514623 1963164571 561646784 819612826 3340955171"
+                        "1338523647 1675643732 458583760 698472119 3233594836 2901754568 4222994242"
+                        "51167459 2501563254 2175997686 1673326467 3722097469 2183287831 2155925807"
+                        "1071447253 1857934241 320830903 1514449149 103571877 839083116 3893321384"
+                        "4236495022 766393502 2729490440 290181118 3191537542 1077578150 3066185245"
+                        "3193085445 3786728494 2938418649 3410121447 1453867071 698346001 3037921161"
+                        "839425565 2245305640 2806447261 3196149514 1071872132 2337761397 3632554165"
+                        "190093341 4248613644 2372806256 3290113603 3852853233 272818390 3168842643"
+                        "25788407 4197010683 3864965812 1635548247 2364439227 3344377087 4284620573"
+                        "3351117493 3398532219 2757166123 1127999905 2988564217 3707129726 3652489018"
+                        "4035370271 475801332 2109377392 2128345729 3920803035 4271338685 509459802"
+                        "4158256844 1850467175 1579214935 8921175 4068350958 2951987840 506827330"
+                        "3520651040 3359838267 1120109827 3917280670 2748947423 3672973280 1566164613"
+                        "2986317531 1204099196 3080678121 3574913280 4009316336 3034181160 1818230129"
+                        "3757769877 2464713972 2812294843 782960615 1228678223 2571358051 4260066020"
+                        "2439643840 3500737183 1433940923 1031851687 190066625 3777385171 4142770213"
+                        "3539275502 1622933657 425231043 3715607557 260333136 4198959706 358418"
+                        "1799817566 2839827743 437785672 2967249029 949856347 2081447702 1102224171"
+                        "479701434 1781895167 2965560025 264797633 2564778619 2515037023 1320978995"
+                        "780140943 2372404879 3823445604 2917613108 143505740 3507288260 2803553229"
+                        "4195962819 4072604717 3155823087 323755011 601944215 1840441037 2850820195"
+                        "915623058 3306124208 3069788039 1553985704 411632899 3200645375 2973968812"
+                        "4263574437 3360058162 144760024 845487010 3508028432 4091510967 3925394277"
+                        "71566492 3432433113 3266920114 3539050491 51719451 1245373835 1469278112"
+                        "3298302496 753088653 2942352102 1565378440 494477947 971879195 482756304"
+                        "2475493857 143180757 324876427 1610205542 1829295320 1937949038 3733336232"
+                        "2542145235 3636527510 2347609126 2343078538 2526896356 167862270 2299577281"
+                        "3382958264 1911078293 531208917 3588214476 1086101513 1838672874 2119663667"
+                        "491092052 2961424745 3048925589 486607333 3505822195 3888367 2949031946"
+                        "2684841832 433147539 2333660325 3142554719 435207743 3063000516 4043979879"
+                        "3290075088 1114755542 18368971 876637247 3352816011 1421909753 3339898083"
+                        "740553432 3682683666 2699730850 2861403632 1971653904 900380480 2635160544"
+                        "1318218867 411940 2141321523 2349820793 280562368 3816712514 3790707429"
+                        "1619023591 2858103376 1462886666 1723686126 3766879240 1918781537 2792938366"
+                        "166155425 803108075 722833545 220020495 880029214 2901984266 609985526"
+                        "1367283597 132804580 903066665 131582208 64374393 2006102725 3422930158"
+                        "4209296423 380263053 3978926691 3310851236 4245770487 4166043866 4080757525"
+                        "3329599259 258706185 2452129516 3191265966 2958285912 1070664670 921876197"
+                        "2421722823 2568477756 382467393 2196144533 213270233 116974426 2230947214"
+                        "2576421741 393776471 2796472698 3647710433 3264988906 726903864 817800486"
+                        "628224092 2707785007 3517963926 596980027 2466711387 3156540408 2517803670"
+                        "3408123552 4142066739 3779818910 2988899011 2732117432 3579427018 1513070048"
+                        "1566052861 20225341 997297613 3219855094 2777075639 1656025420 3670325076"
+                        "1469330501 3061438653 4264717436 1305791144 1237197751 2943926634 1566843825"
+                        "3359878993 4037226997 4044024653 3611863927 1375344610 211134383 2406252392"
+                        "1349912770 1023874273 1912665158 1762983936 407124872 2936278199 1821966634"
+                        "3337187112 2546090236 2594870585 823411965 126464686 4041388220 1686530706"
+                        "2780657745 1945569350 203691199 2532411242 1830339266 674003798 2192329968"
+                        "2425624005 2819484460 3743368462 2565769418 4179439526 216134386 2880090718"
+                        "623297558 3913067470 745959159 2499436157 373025119 3423124368 2522302278"
+                        "3719518513 999390119 159673547 228111094 3391079061 1761352720 2549048062"
+                        "1125219697 2052834337 3743842626 2433549637 3636723358 1860785315 2387664013"
+                        "581140755 11086848 4199179079 1180488689 2060816030 2550665319 1314472090"
+                        "1402807876 304522082 3382175195 4260677857 1724818219 2183493354 1004322779"
+                        "4166984056 889220724 553883566 582971548 2046113107 2080208105 3473121134"
+                        "1959681858 1840897428 2595714120 855065022 4191762128 3679914005 3623561445"
+                        "3437337182 3269107597 2019021510 2112281155 985458687 1364815423 514093990"
+                        "3711847302 704129707 3398127374 517373404 2646977457 3048605419 1372350917"
+                        "3831335422 2263542968 2283942504 2193996512 824623017 1707815852 3337156739"
+                        "2301398895 2077322758 193542893 869960695 3878520140 403616946 3228943765"
+                        "1037753596 2949947821 379992823 2251850209 1614533146 1704886337 108361232"
+                        "3840616436 2932809257 2375700648 596391307 4226846855 191943050 1271990524"
+                        "1335422537 3085696177 2030313449 3272604577 1148556450 1184357181 3558074012"
+                        "3259720214 2755915415 2720703536 31861322 1740307221 1860884298 3922103763"
+                        "4066872392 1756734488 394294796 2505236387 2456914682 639788702 52063410"
+                        "2855173018 3307964490 556762160 3624145788 3793504468 4252003358 3690335184"
+                        "688245281 2259823605 2617950220 1045718164 3091539813 1330130477 736722350"
+                        "3100437052 3900855736 4183439368 1735720081 2644768495 819274730 2364834023"
+                        "1393374098 981219339 3969251105 332522940 850159909 646738867 3413137687"
+                        "1646732884 80027487 2196948979 5295580 3530173036 767814907 2573204209"
+                        "491686200 1287955820 3095830596 2152743903 1738320986 1900678059 3613699900"
+                        "3076191184 2917243255 2236492002 3504114019 604643631 3324769580 4078090927"
+                        "1245379462 2026215662 1566278916 2832509655 3010562339 1269806412 835199342"
+                        "2561789927 163108895 524878390 833167775 3551760739 3008059185 1133970834"
+                        "26821616 2846321927 3803209991 581001826 3764614926 3893778555 617853085"
+                        "183809431 3510530944 350044681 429839558 1238110552 265276207 205294443"
+                        "3092821176 2003027316 2577165836 1277274629 87531073 63821123 354781812"
+                        "3700767000 3451421881 990626144 3763226681 3373715717 2360928651 2412110189"
+                        "3362121672 3080578947 1604861935 3186376735 2989392261 3550022914 756392571"
+                        "1580512570 2584626785 2727753459 730699388 3379402897 3050444856 2244390108"
+                        "3941150486 1990708800 2462735 195459645 761670582 1067695927 984662039"
+                        "2678082647 1839150009 2113552968 406021267 2193154754 720977131 2445722325"
+                        "2482507181 2062595810 1015226482";
+
+    std::istringstream iss(state);
+    iss >> g;
+
+    const int N = 1000000;
+    std::vector<D::result_type> u;
+    for (int i = 0; i < N; ++i)
+    {
+        D::result_type v = d(g);
+        assert(d.min() <= v && v <= d.max());
+        u.push_back(v);
+    }
+    double mean = std::accumulate(u.begin(), u.end(),
+                                          double(0)) / u.size();
+    double var = 0;
+    double skew = 0;
+    double kurtosis = 0;
+    for (unsigned i = 0; i < u.size(); ++i)
+    {
+        double dbl = (u[i] - mean);
+        double d2 = sqr(dbl);
+        var += d2;
+        skew += dbl * d2;
+        kurtosis += d2 * d2;
+    }
+    var /= u.size();
+    double dev = std::sqrt(var);
+    skew /= u.size() * dev * var;
+    kurtosis /= u.size() * var * var;
+    kurtosis -= 3;
+    double x_mean = d.t() * d.p();
+    double x_var = x_mean*(1-d.p());
+    double x_skew = (1-2*d.p()) / std::sqrt(x_var);
+    double x_kurtosis = (1-6*d.p()*(1-d.p())) / x_var;
+    assert(std::abs((mean - x_mean) / x_mean) < 0.01);
+    assert(std::abs((var - x_var) / x_var) < 0.01);
+    assert(std::abs((skew - x_skew) / x_skew) < 0.01);
+    assert(std::abs((kurtosis - x_kurtosis) / x_kurtosis) < 0.04);
+}
+
 int main(int, char**)
 {
     test1();
@@ -521,6 +661,7 @@ int main(int, char**)
     test9();
     test10();
     test11();
+    test12();
 
   return 0;
 }
diff --git a/libcxx/test/support/msvc_stdlib_force_include.h b/libcxx/test/support/msvc_stdlib_force_include.h
index fd47af4e7983b..768558efe76ff 100644
--- a/libcxx/test/support/msvc_stdlib_force_include.h
+++ b/libcxx/test/support/msvc_stdlib_force_include.h
@@ -91,7 +91,19 @@ const AssertionDialogAvoider assertion_dialog_avoider{};
 #endif
 
 #define _LIBCPP_AVAILABILITY_THROW_BAD_ANY_CAST
-#define _LIBCPP_SUPPRESS_DEPRECATED_PUSH
-#define _LIBCPP_SUPPRESS_DEPRECATED_POP
+
+#ifdef __clang__
+#define _LIBCPP_SUPPRESS_DEPRECATED_PUSH \
+    _Pragma("GCC diagnostic push") \
+    _Pragma("GCC diagnostic ignored \"-Wdeprecated\"")
+#define _LIBCPP_SUPPRESS_DEPRECATED_POP \
+    _Pragma("GCC diagnostic pop")
+#else // ^^^ clang / MSVC vvv
+#define _LIBCPP_SUPPRESS_DEPRECATED_PUSH \
+    __pragma(warning(push)) \
+    __pragma(warning(disable : 4996))
+#define _LIBCPP_SUPPRESS_DEPRECATED_POP \
+    __pragma(warning(pop))
+#endif // __clang__
 
 #endif // SUPPORT_MSVC_STDLIB_FORCE_INCLUDE_H
diff --git a/libcxx/utils/libcxx/test/config.py b/libcxx/utils/libcxx/test/config.py
index 215faf2368c95..459a5ccdf225f 100644
--- a/libcxx/utils/libcxx/test/config.py
+++ b/libcxx/utils/libcxx/test/config.py
@@ -602,7 +602,7 @@ def configure_default_compile_flags(self):
 
         # FIXME(EricWF): variant_size.pass.cpp requires a slightly larger
         # template depth with older Clang versions.
-        self.cxx.addFlagIfSupported('-ftemplate-depth=270')
+        self.cxx.addCompileFlagIfSupported('-ftemplate-depth=270')
 
     def configure_compile_flags_header_includes(self):
         support_path = os.path.join(self.libcxx_src_root, 'test', 'support')
@@ -1043,7 +1043,7 @@ def configure_substitutions(self):
         if self.target_info.is_darwin():
             # Do not pass DYLD_LIBRARY_PATH to the compiler, linker, etc. as
             # these tools are not meant to exercise the just-built libraries.
-            tool_env += 'DYLD_LIBRARY_PATH="" '
+            tool_env += 'env DYLD_LIBRARY_PATH="" '
 
         sub = self.config.substitutions
         cxx_path = tool_env + pipes.quote(self.cxx.path)
@@ -1200,7 +1200,7 @@ def configure_deployment(self):
                 self.config.available_features.add('dylib-has-no-filesystem')
                 self.lit_config.note("the deployment target does not support <filesystem>")
         else:
-            self.cxx.flags += ['-D_LIBCPP_DISABLE_AVAILABILITY']
+            self.cxx.compile_flags += ['-D_LIBCPP_DISABLE_AVAILABILITY']
 
     def configure_env(self):
         self.target_info.configure_env(self.exec_env)
diff --git a/lld/COFF/Config.h b/lld/COFF/Config.h
index 2690ea5c40826..af86b69922729 100644
--- a/lld/COFF/Config.h
+++ b/lld/COFF/Config.h
@@ -211,6 +211,7 @@ struct Configuration {
   uint32_t functionPadMin = 0;
   bool dynamicBase = true;
   bool allowBind = true;
+  bool cetCompat = false;
   bool nxCompat = true;
   bool allowIsolation = true;
   bool terminalServerAware = true;
diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp
index a85dfda2dea14..5320b8b83ce0a 100644
--- a/lld/COFF/Driver.cpp
+++ b/lld/COFF/Driver.cpp
@@ -1549,6 +1549,7 @@ void LinkerDriver::link(ArrayRef<const char *> argsArr) {
                        !args.hasArg(OPT_profile));
   config->integrityCheck =
       args.hasFlag(OPT_integritycheck, OPT_integritycheck_no, false);
+  config->cetCompat = args.hasFlag(OPT_cetcompat, OPT_cetcompat_no, false);
   config->nxCompat = args.hasFlag(OPT_nxcompat, OPT_nxcompat_no, true);
   for (auto *arg : args.filtered(OPT_swaprun))
     parseSwaprun(arg->getValue());
diff --git a/lld/COFF/Options.td b/lld/COFF/Options.td
index 328a120cb711d..cea02e7a0042c 100644
--- a/lld/COFF/Options.td
+++ b/lld/COFF/Options.td
@@ -148,6 +148,8 @@ defm allowisolation : B<"allowisolation", "Enable DLL isolation (default)",
 defm appcontainer : B<"appcontainer",
                       "Image can only be run in an app container",
                       "Image can run outside an app container (default)">;
+defm cetcompat : B<"cetcompat", "Mark executable image as compatible with Control-flow Enforcement Technology (CET) Shadow Stack",
+                   "Don't mark executable image as compatible with Control-flow Enforcement Technology (CET) Shadow Stack (default)">;
 defm dynamicbase : B<"dynamicbase", "Enable ASLR (default unless /fixed)",
                      "Disable ASLR (default when /fixed)">;
 defm fixed : B<"fixed", "Disable base relocations",
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index fbef82af9d361..7e7aaafe18ed5 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -91,7 +91,8 @@ namespace {
 
 class DebugDirectoryChunk : public NonSectionChunk {
 public:
-  DebugDirectoryChunk(const std::vector<Chunk *> &r, bool writeRepro)
+  DebugDirectoryChunk(const std::vector<std::pair<COFF::DebugType, Chunk *>> &r,
+                      bool writeRepro)
       : records(r), writeRepro(writeRepro) {}
 
   size_t getSize() const override {
@@ -101,11 +102,11 @@ class DebugDirectoryChunk : public NonSectionChunk {
   void writeTo(uint8_t *b) const override {
     auto *d = reinterpret_cast<debug_directory *>(b);
 
-    for (const Chunk *record : records) {
-      OutputSection *os = record->getOutputSection();
-      uint64_t offs = os->getFileOff() + (record->getRVA() - os->getRVA());
-      fillEntry(d, COFF::IMAGE_DEBUG_TYPE_CODEVIEW, record->getSize(),
-                record->getRVA(), offs);
+    for (const std::pair<COFF::DebugType, Chunk *>& record : records) {
+      Chunk *c = record.second;
+      OutputSection *os = c->getOutputSection();
+      uint64_t offs = os->getFileOff() + (c->getRVA() - os->getRVA());
+      fillEntry(d, record.first, c->getSize(), c->getRVA(), offs);
       ++d;
     }
 
@@ -140,7 +141,7 @@ class DebugDirectoryChunk : public NonSectionChunk {
   }
 
   mutable std::vector<support::ulittle32_t *> timeDateStamps;
-  const std::vector<Chunk *> &records;
+  const std::vector<std::pair<COFF::DebugType, Chunk *>> &records;
   bool writeRepro;
 };
 
@@ -165,6 +166,17 @@ class CVDebugRecordChunk : public NonSectionChunk {
   mutable codeview::DebugInfo *buildId = nullptr;
 };
 
+class ExtendedDllCharacteristicsChunk : public NonSectionChunk {
+public:
+  ExtendedDllCharacteristicsChunk(uint32_t c) : characteristics(c) {}
+
+  size_t getSize() const override { return 4; }
+
+  void writeTo(uint8_t *buf) const override { write32le(buf, characteristics); }
+
+  uint32_t characteristics = 0;
+};
+
 // PartialSection represents a group of chunks that contribute to an
 // OutputSection. Collating a collection of PartialSections of same name and
 // characteristics constitutes the OutputSection.
@@ -250,7 +262,7 @@ class Writer {
   bool setNoSEHCharacteristic = false;
 
   DebugDirectoryChunk *debugDirectory = nullptr;
-  std::vector<Chunk *> debugRecords;
+  std::vector<std::pair<COFF::DebugType, Chunk *>> debugRecords;
   CVDebugRecordChunk *buildId = nullptr;
   ArrayRef<uint8_t> sectionTable;
 
@@ -920,8 +932,9 @@ void Writer::createMiscChunks() {
 
   // Create Debug Information Chunks
   OutputSection *debugInfoSec = config->mingw ? buildidSec : rdataSec;
-  if (config->debug || config->repro) {
+  if (config->debug || config->repro || config->cetCompat) {
     debugDirectory = make<DebugDirectoryChunk>(debugRecords, config->repro);
+    debugDirectory->setAlignment(4);
     debugInfoSec->addChunk(debugDirectory);
   }
 
@@ -931,10 +944,20 @@ void Writer::createMiscChunks() {
     // allowing a debugger to match a PDB and an executable.  So we need it even
     // if we're ultimately not going to write CodeView data to the PDB.
     buildId = make<CVDebugRecordChunk>();
-    debugRecords.push_back(buildId);
+    debugRecords.push_back({COFF::IMAGE_DEBUG_TYPE_CODEVIEW, buildId});
+  }
+
+  if (config->cetCompat) {
+    ExtendedDllCharacteristicsChunk *extendedDllChars =
+        make<ExtendedDllCharacteristicsChunk>(
+            IMAGE_DLL_CHARACTERISTICS_EX_CET_COMPAT);
+    debugRecords.push_back(
+        {COFF::IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS, extendedDllChars});
+  }
 
-    for (Chunk *c : debugRecords)
-      debugInfoSec->addChunk(c);
+  if (debugRecords.size() > 0) {
+    for (std::pair<COFF::DebugType, Chunk *> r : debugRecords)
+      debugInfoSec->addChunk(r.second);
   }
 
   // Create SEH table. x86-only.
diff --git a/lld/Common/TargetOptionsCommandFlags.cpp b/lld/Common/TargetOptionsCommandFlags.cpp
index 0137feb63f371..9b166a3e130a5 100644
--- a/lld/Common/TargetOptionsCommandFlags.cpp
+++ b/lld/Common/TargetOptionsCommandFlags.cpp
@@ -5,35 +5,26 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
-//
-// This file exists as a place for global variables defined in LLVM's
-// CodeGen/CommandFlags.inc. By putting the resulting object file in
-// an archive and linking with it, the definitions will automatically be
-// included when needed and skipped when already present.
-//
-//===----------------------------------------------------------------------===//
 
 #include "lld/Common/TargetOptionsCommandFlags.h"
 
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/Target/TargetOptions.h"
 
-// Define an externally visible version of
-// initTargetOptionsFromCodeGenFlags, so that its functionality can be
-// used without having to include llvm/CodeGen/CommandFlags.inc, which
-// would lead to multiple definitions of the command line flags.
+static llvm::codegen::RegisterCodeGenFlags CGF;
+
 llvm::TargetOptions lld::initTargetOptionsFromCodeGenFlags() {
-  return ::InitTargetOptionsFromCodeGenFlags();
+  return llvm::codegen::InitTargetOptionsFromCodeGenFlags();
 }
 
 llvm::Optional<llvm::Reloc::Model> lld::getRelocModelFromCMModel() {
-  return getRelocModel();
+  return llvm::codegen::getExplicitRelocModel();
 }
 
 llvm::Optional<llvm::CodeModel::Model> lld::getCodeModelFromCMModel() {
-  return getCodeModel();
+  return llvm::codegen::getExplicitCodeModel();
 }
 
-std::string lld::getCPUStr() { return ::getCPUStr(); }
+std::string lld::getCPUStr() { return llvm::codegen::getCPUStr(); }
 
-std::vector<std::string> lld::getMAttrs() { return ::MAttrs; }
+std::vector<std::string> lld::getMAttrs() { return llvm::codegen::getMAttrs(); }
diff --git a/lld/test/COFF/arm-thumb-thunks-multipass.s b/lld/test/COFF/arm-thumb-thunks-multipass.s
index 5e64e8df49c83..ddee007b8ba87 100644
--- a/lld/test/COFF/arm-thumb-thunks-multipass.s
+++ b/lld/test/COFF/arm-thumb-thunks-multipass.s
@@ -1,8 +1,8 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=thumbv7-windows %s -o %t.obj
 // RUN: lld-link -entry:main -subsystem:console %t.obj -out:%t.exe -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
-// RUN: llvm-objdump -d %t.exe -start-address=0x403000 -stop-address=0x403008 | FileCheck -check-prefix=FUNC01 %s
-// RUN: llvm-objdump -d %t.exe -start-address=0x404ffa -stop-address=0x405012 | FileCheck -check-prefix=FUNC01-THUNKS %s
+// RUN: llvm-objdump -d %t.exe --start-address=0x403000 --stop-address=0x403008 | FileCheck --check-prefix=FUNC01 %s
+// RUN: llvm-objdump -d %t.exe --start-address=0x404ffa --stop-address=0x405012 | FileCheck --check-prefix=FUNC01-THUNKS %s
 
 // VERBOSE: Added {{.*}} thunks with margin 204800 in 2 passes
 
diff --git a/lld/test/COFF/arm-thumb-thunks.s b/lld/test/COFF/arm-thumb-thunks.s
index 33c3740ba8cba..0437a4d7501b5 100644
--- a/lld/test/COFF/arm-thumb-thunks.s
+++ b/lld/test/COFF/arm-thumb-thunks.s
@@ -1,9 +1,9 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=thumbv7-windows %s -o %t.obj
 // RUN: lld-link -entry:main -subsystem:console %t.obj -out:%t.exe -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
-// RUN: llvm-objdump -d %t.exe -start-address=0x401000 -stop-address=0x401022 | FileCheck -check-prefix=MAIN %s
-// RUN: llvm-objdump -d %t.exe -start-address=0x501022 -stop-address=0x501032 | FileCheck -check-prefix=FUNC1 %s
-// RUN: llvm-objdump -d %t.exe -start-address=0x601032 | FileCheck -check-prefix=FUNC2 %s
+// RUN: llvm-objdump -d %t.exe --start-address=0x401000 --stop-address=0x401022 | FileCheck --check-prefix=MAIN %s
+// RUN: llvm-objdump -d %t.exe --start-address=0x501022 --stop-address=0x501032 | FileCheck --check-prefix=FUNC1 %s
+// RUN: llvm-objdump -d %t.exe --start-address=0x601032 | FileCheck --check-prefix=FUNC2 %s
 
 // VERBOSE: Added 3 thunks with margin {{.*}} in 1 passes
 
diff --git a/lld/test/COFF/arm64-delayimport.yaml b/lld/test/COFF/arm64-delayimport.yaml
index 24a47ef592a24..122dd1dea6e40 100644
--- a/lld/test/COFF/arm64-delayimport.yaml
+++ b/lld/test/COFF/arm64-delayimport.yaml
@@ -2,7 +2,7 @@
 
 # RUN: yaml2obj < %s > %t.obj
 # RUN: lld-link /entry:main /subsystem:console /out:%t.exe %t.obj %p/Inputs/library-arm64.lib /alternatename:__delayLoadHelper2=main /delayload:library.dll
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix DISASM
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix DISASM
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck %s -check-prefix IMPORTS
 
 # DISASM:  140001014:      11 00 00 d0     adrp    x17, #8192
diff --git a/lld/test/COFF/arm64-import2.test b/lld/test/COFF/arm64-import2.test
index 7f3ce03680223..d4b4c83d62163 100644
--- a/lld/test/COFF/arm64-import2.test
+++ b/lld/test/COFF/arm64-import2.test
@@ -1,9 +1,9 @@
 # REQUIRES: aarch64
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /entry:main /subsystem:console /out:%t.exe %t.obj %p/Inputs/library-arm64.lib %p/Inputs/library2-arm64.lib
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix AFTER
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck %s -check-prefix IMPORTS
 
 # BEFORE: Disassembly of section .text:
diff --git a/lld/test/COFF/arm64-relocs-imports.test b/lld/test/COFF/arm64-relocs-imports.test
index 05748f9fa8d69..539f9b7907344 100644
--- a/lld/test/COFF/arm64-relocs-imports.test
+++ b/lld/test/COFF/arm64-relocs-imports.test
@@ -1,9 +1,9 @@
 # REQUIRES: aarch64
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /entry:main /subsystem:console /out:%t.exe %t.obj %p/Inputs/library-arm64.lib
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix AFTER
 
 # BEFORE: Disassembly of section .text:
 # BEFORE-EMPTY:
diff --git a/lld/test/COFF/arm64-thunks.s b/lld/test/COFF/arm64-thunks.s
index 2638f7bacb19a..17f87ff8fcdb9 100644
--- a/lld/test/COFF/arm64-thunks.s
+++ b/lld/test/COFF/arm64-thunks.s
@@ -1,7 +1,7 @@
 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-windows %s -o %t.obj
 // RUN: lld-link -entry:main -subsystem:console %t.obj -out:%t.exe -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
-// RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=DISASM %s
+// RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=DISASM %s
 
 // VERBOSE: Added 2 thunks with margin {{.*}} in 1 passes
 
diff --git a/lld/test/COFF/armnt-blx23t.test b/lld/test/COFF/armnt-blx23t.test
index 3e522be7cd790..136834b66b62e 100644
--- a/lld/test/COFF/armnt-blx23t.test
+++ b/lld/test/COFF/armnt-blx23t.test
@@ -1,9 +1,9 @@
 # REQUIRES: arm
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /entry:function /subsystem:console /out:%t.exe %t.obj
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix AFTER
 
 # BEFORE: Disassembly of section .text:
 # BEFORE-EMPTY:
diff --git a/lld/test/COFF/armnt-branch24t.test b/lld/test/COFF/armnt-branch24t.test
index b049cdae4fd65..264c27b7041a7 100644
--- a/lld/test/COFF/armnt-branch24t.test
+++ b/lld/test/COFF/armnt-branch24t.test
@@ -1,9 +1,9 @@
 # REQUIRES: arm
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /entry:function /subsystem:console /out:%t.exe %t.obj
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix AFTER
 
 # BEFORE: Disassembly of section .text:
 # BEFORE-EMPTY:
diff --git a/lld/test/COFF/armnt-mov32t-exec.test b/lld/test/COFF/armnt-mov32t-exec.test
index d1170a33ef8ee..418dc4ad1d5d8 100644
--- a/lld/test/COFF/armnt-mov32t-exec.test
+++ b/lld/test/COFF/armnt-mov32t-exec.test
@@ -1,9 +1,9 @@
 # REQUIRES: arm
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /out:%t.exe /subsystem:console /entry:get_function %t.obj
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix AFTER
 
 # BEFORE: Disassembly of section .text:
 # BEFORE-EMPTY:
diff --git a/lld/test/COFF/armnt-movt32t.test b/lld/test/COFF/armnt-movt32t.test
index 7febe9d753de0..f145530649629 100644
--- a/lld/test/COFF/armnt-movt32t.test
+++ b/lld/test/COFF/armnt-movt32t.test
@@ -1,9 +1,9 @@
 # REQUIRES: arm
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /entry:get_buffer /subsystem:console /out:%t.exe %t.obj
-# RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -d %t.exe | FileCheck %s --check-prefix AFTER
 
 # BEFORE: Disassembly of section .text:
 # BEFORE-EMPTY:
diff --git a/lld/test/COFF/armnt-rel32.yaml b/lld/test/COFF/armnt-rel32.yaml
index fa385c5fd7d51..b81558640c1f3 100644
--- a/lld/test/COFF/armnt-rel32.yaml
+++ b/lld/test/COFF/armnt-rel32.yaml
@@ -1,9 +1,9 @@
 # REQUIRES: arm
 
 # RUN: yaml2obj < %s > %t.obj
-# RUN: llvm-objdump -s %t.obj | FileCheck %s -check-prefix BEFORE
+# RUN: llvm-objdump -s %t.obj | FileCheck %s --check-prefix BEFORE
 # RUN: lld-link /entry:function /subsystem:console /out:%t.exe %t.obj
-# RUN: llvm-objdump -s %t.exe | FileCheck %s -check-prefix AFTER
+# RUN: llvm-objdump -s %t.exe | FileCheck %s --check-prefix AFTER
 
 # BEFORE: Contents of section .text:
 # BEFORE:    0000 704700bf 01000000 01000000
diff --git a/lld/test/COFF/autoimport-arm-data.s b/lld/test/COFF/autoimport-arm-data.s
index aa24e90115c77..74604aa5c8234 100644
--- a/lld/test/COFF/autoimport-arm-data.s
+++ b/lld/test/COFF/autoimport-arm-data.s
@@ -8,7 +8,7 @@
 # RUN: lld-link -lldmingw -out:%t.exe -entry:main %t.obj %t-lib.lib -verbose
 
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORTS %s
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=CONTENTS %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=CONTENTS %s
 
 # IMPORTS: Import {
 # IMPORTS-NEXT: Name: autoimport-arm-data.s.tmp-lib.dll
diff --git a/lld/test/COFF/autoimport-arm64-data.s b/lld/test/COFF/autoimport-arm64-data.s
index 9ac6daf48d2e6..fa3654be3a71d 100644
--- a/lld/test/COFF/autoimport-arm64-data.s
+++ b/lld/test/COFF/autoimport-arm64-data.s
@@ -8,7 +8,7 @@
 # RUN: lld-link -lldmingw -out:%t.exe -entry:main %t.obj %t-lib.lib -verbose
 
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORTS %s
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=CONTENTS %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=CONTENTS %s
 
 # IMPORTS: Import {
 # IMPORTS-NEXT: Name: autoimport-arm64-data.s.tmp-lib.dll
diff --git a/lld/test/COFF/autoimport-list-ptrs.s b/lld/test/COFF/autoimport-list-ptrs.s
index d3c9d3d07dbb6..7606e14b634a4 100644
--- a/lld/test/COFF/autoimport-list-ptrs.s
+++ b/lld/test/COFF/autoimport-list-ptrs.s
@@ -3,7 +3,7 @@
 # RUN: llvm-mc -triple=x86_64-windows-gnu %s -filetype=obj -o %t.obj
 # RUN: lld-link -lldmingw -out:%t.exe -entry:main %t.obj -verbose
 
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=CONTENTS %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=CONTENTS %s
 
 # Even if we didn't actually write any pseudo relocations,
 # check that the synthetic pointers still are set to a non-null value
diff --git a/lld/test/COFF/autoimport-refptr.s b/lld/test/COFF/autoimport-refptr.s
index 20717cd258ac4..6d69255a737a1 100644
--- a/lld/test/COFF/autoimport-refptr.s
+++ b/lld/test/COFF/autoimport-refptr.s
@@ -8,8 +8,8 @@
 # RUN: lld-link -lldmingw -out:%t.exe -entry:main %t.obj %t-lib.lib -verbose
 
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORTS %s
-# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=DISASM %s
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=CONTENTS %s
+# RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=DISASM %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=CONTENTS %s
 
 # IMPORTS: Import {
 # IMPORTS-NEXT: Name: autoimport-refptr.s.tmp-lib.dll
diff --git a/lld/test/COFF/autoimport-x86.s b/lld/test/COFF/autoimport-x86.s
index 8e4301d8f381e..2244a1ed868b3 100644
--- a/lld/test/COFF/autoimport-x86.s
+++ b/lld/test/COFF/autoimport-x86.s
@@ -8,8 +8,8 @@
 # RUN: lld-link -lldmingw -debug:symtab -out:%t.exe -entry:main %t.obj %t-lib.lib -verbose
 
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORTS %s
-# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=DISASM %s
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=CONTENTS %s
+# RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=DISASM %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=CONTENTS %s
 # RUN: llvm-nm %t.exe | FileCheck -check-prefix=SYMBOLS %s
 
 # IMPORTS: Import {
diff --git a/lld/test/COFF/base.test b/lld/test/COFF/base.test
index b6c43f9594eeb..25284bbfebda5 100644
--- a/lld/test/COFF/base.test
+++ b/lld/test/COFF/base.test
@@ -2,7 +2,7 @@
 
 # RUN: lld-link /out:%t.exe /entry:main %t.obj
 # RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=DEFAULT-HEADER %s
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=DEFAULT-TEXT %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=DEFAULT-TEXT %s
 
 # DEFAULT-HEADER:    ImageBase: 0x140000000
 # DEFAULT-TEXT:      Contents of section .text:
@@ -10,7 +10,7 @@
 
 # RUN: lld-link /out:%t.exe /entry:main %t.obj /base:0x280000000
 # RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=BASE-HEADER %s
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=BASE-TEXT %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=BASE-TEXT %s
 
 # BASE-HEADER: ImageBase: 0x280000000
 # BASE-TEXT:      Contents of section .text:
diff --git a/lld/test/COFF/delayimports-armnt.yaml b/lld/test/COFF/delayimports-armnt.yaml
index 6437877018121..48a5ad1471ddd 100644
--- a/lld/test/COFF/delayimports-armnt.yaml
+++ b/lld/test/COFF/delayimports-armnt.yaml
@@ -5,7 +5,7 @@
 # RUN:   /delayload:library.dll /out:%t.exe
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
 # RUN: llvm-readobj --coff-basereloc %t.exe | FileCheck -check-prefix=BASEREL %s
-# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=DISASM %s
+# RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=DISASM %s
 
 # IMPORT:      Format: COFF-ARM
 # IMPORT-NEXT: Arch: thumb
diff --git a/lld/test/COFF/delayimports32.test b/lld/test/COFF/delayimports32.test
index 0fc90200c1bfa..41b4bdc97ef10 100644
--- a/lld/test/COFF/delayimports32.test
+++ b/lld/test/COFF/delayimports32.test
@@ -5,7 +5,7 @@
 # RUN:   /delayload:std32.dll /out:%t.exe
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
 # RUN: llvm-readobj --coff-basereloc %t.exe | FileCheck -check-prefix=BASEREL %s
-# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=DISASM %s
+# RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=DISASM %s
 
 IMPORT:      Format: COFF-i386
 IMPORT-NEXT: Arch: i386
diff --git a/lld/test/COFF/dll.test b/lld/test/COFF/dll.test
index b2681609beecf..66186b1dcc643 100644
--- a/lld/test/COFF/dll.test
+++ b/lld/test/COFF/dll.test
@@ -2,7 +2,7 @@
 # RUN: yaml2obj < %p/Inputs/export.yaml > %t.obj
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:exportfn1 /export:exportfn2 \
 # RUN:   /export:mangled
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=EXPORT %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=EXPORT %s
 
 EXPORT:      Export Table:
 EXPORT:      DLL name: dll.test.tmp.dll
@@ -17,7 +17,7 @@ EXPORT-NEXT:       4   0x1010  mangled
 # RUN: rm -f %t5.lib
 # RUN: llvm-ar cru %t5.lib %t5.obj
 # RUN: lld-link /out:%t5.dll /dll %t.obj %t5.lib /export:mangled2
-# RUN: llvm-objdump -p %t5.dll | FileCheck -check-prefix=EXPORT2 %s
+# RUN: llvm-objdump -p %t5.dll | FileCheck --check-prefix=EXPORT2 %s
 
 EXPORT2:      Export Table:
 EXPORT2:      DLL name: dll.test.tmp5.dll
@@ -28,7 +28,7 @@ EXPORT2-NEXT:       2   0x101c  mangled2
 
 # RUN: llvm-as -o %t.lto.obj %p/Inputs/export.ll
 # RUN: lld-link -opt:noicf /out:%t.lto.dll /dll %t.lto.obj /export:exportfn1 /export:exportfn2
-# RUN: llvm-objdump -p %t.lto.dll | FileCheck -check-prefix=EXPORT-LTO %s
+# RUN: llvm-objdump -p %t.lto.dll | FileCheck --check-prefix=EXPORT-LTO %s
 
 EXPORT-LTO:      Export Table:
 EXPORT-LTO:      DLL name: dll.test.tmp.lto.dll
diff --git a/lld/test/COFF/export-arm64.yaml b/lld/test/COFF/export-arm64.yaml
index ad9a96db41006..ce2b56c0f6c7f 100644
--- a/lld/test/COFF/export-arm64.yaml
+++ b/lld/test/COFF/export-arm64.yaml
@@ -3,7 +3,7 @@
 # RUN: yaml2obj < %s > %t.obj
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:exportfn1 /export:exportfn2 /implib:%t.lib
 # RUN: llvm-objdump -p %t.dll | FileCheck %s
-# RUN: llvm-objdump -r %t.lib | FileCheck %s -check-prefix=RELOCS
+# RUN: llvm-objdump -r %t.lib | FileCheck %s --check-prefix=RELOCS
 
 # CHECK:      Export Table:
 # CHECK:      DLL name: export-arm64.yaml.tmp.dll
diff --git a/lld/test/COFF/export.test b/lld/test/COFF/export.test
index 8bf8c44c81dc6..32dbbfdba4351 100644
--- a/lld/test/COFF/export.test
+++ b/lld/test/COFF/export.test
@@ -1,7 +1,7 @@
 # RUN: yaml2obj < %p/Inputs/export.yaml > %t.obj
 #
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:exportfn1 /export:exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK1 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK1 %s
 
 CHECK1:      Export Table:
 CHECK1:      DLL name: export.test.tmp.dll
@@ -11,7 +11,7 @@ CHECK1-NEXT:       1   0x1008  exportfn1
 CHECK1-NEXT:       2   0x1010  exportfn2
 
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:exportfn1,@5 /export:exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK2 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK2 %s
 
 CHECK2:      Export Table:
 CHECK2:      DLL name: export.test.tmp.dll
@@ -26,7 +26,7 @@ CHECK2-NEXT:       6   0x1010  exportfn2
 CHECK2-NEXT:       7   0x1010  exportfn3
 
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:exportfn1,@5,noname /export:exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK3 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK3 %s
 
 CHECK3:      Export Table:
 CHECK3:      DLL name: export.test.tmp.dll
@@ -40,7 +40,7 @@ CHECK3-NEXT:       5   0x1008
 CHECK3-NEXT:       6   0x1010  exportfn2
 
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:f1=exportfn1 /export:f2=exportfn2 /implib:%t.lib
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK4 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK4 %s
 # RUN: llvm-nm %t.lib | FileCheck -check-prefix=CHECK4-NM %s
 
 CHECK4:      Export Table:
@@ -56,7 +56,7 @@ CHECK4-NM: 00000000 T f2
 # RUN: echo "EXPORTS exportfn1 @3" > %t.def
 # RUN: echo "fn2=exportfn2 @2" >> %t.def
 # RUN: lld-link /out:%t.dll /dll %t.obj /def:%t.def
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK5 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK5 %s
 
 CHECK5:      Export Table:
 CHECK5:      DLL name: export.test.tmp.dll
@@ -84,11 +84,11 @@ SYMTAB: __imp_exportfn3 in export.test.tmp.DLL
 SYMTAB: exportfn3 in export.test.tmp.DLL
 
 # RUN: lld-link /out:%t.dll /dll %t.obj /export:foo=kernel32.foobar
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=FORWARDER %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=FORWARDER %s
 
 # RUN: echo "EXPORTS foo=kernel32.foobar" > %t.def
 # RUN: lld-link /out:%t.dll /dll %t.obj /def:%t.def
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=FORWARDER %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=FORWARDER %s
 
 FORWARDER: Export Table:
 FORWARDER:  DLL name: export.test.tmp.dll
@@ -99,7 +99,7 @@ FORWARDER:        1   0x1010  exportfn
 FORWARDER:        2           foo (forwarded to kernel32.foobar)
 
 # RUN: lld-link /out:%t.dll /dll %t.obj /merge:.rdata=.text /export:exportfn1 /export:exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=MERGE -match-full-lines %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=MERGE --match-full-lines %s
 
 MERGE:      DLL name: export.test.tmp.dll
 MERGE:      Ordinal      RVA  Name
diff --git a/lld/test/COFF/export32.test b/lld/test/COFF/export32.test
index 1251d43aacbc7..bd7231b364b44 100644
--- a/lld/test/COFF/export32.test
+++ b/lld/test/COFF/export32.test
@@ -1,10 +1,10 @@
 # RUN: yaml2obj < %s > %t.obj
 #
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /export:exportfn1 /export:exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK1 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK1 %s
 #
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /export:exportfn1 /export:exportfn2 /merge:.edata=.rdata
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK1 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK1 %s
 # RUN: llvm-readobj --file-headers --sections %t.dll | FileCheck -check-prefix=HEADER-MERGE %s
 
 # CHECK1:      Export Table:
@@ -22,7 +22,7 @@
 
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /export:exportfn1,@5 \
 # RUN:   /export:exportfn2 /export:mangled
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK2 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK2 %s
 
 # CHECK2:      Export Table:
 # CHECK2:      DLL name: export32.test.tmp.dll
@@ -38,7 +38,7 @@
 # CHECK2-NEXT:       8   0x1010  mangled
 
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /export:exportfn1,@5,noname /export:exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK3 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK3 %s
 
 # CHECK3:      Export Table:
 # CHECK3:      DLL name: export32.test.tmp.dll
@@ -52,7 +52,7 @@
 # CHECK3-NEXT:       6   0x1010  exportfn2
 
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /export:f1=exportfn1 /export:f2=exportfn2
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK4 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK4 %s
 
 # CHECK4:      Export Table:
 # CHECK4:      DLL name: export32.test.tmp.dll
@@ -65,12 +65,12 @@
 # RUN: echo "EXPORTS exportfn1 @3" > %t.def
 # RUN: echo "fn2=exportfn2 @2" >> %t.def
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /def:%t.def
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK5 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK5 %s
 
 # RUN: echo "EXPORTS exportfn1 @ 3" > %t.def
 # RUN: echo "fn2=exportfn2 @ 2" >> %t.def
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /def:%t.def
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK5 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK5 %s
 
 # CHECK5:      Export Table:
 # CHECK5:      DLL name: export32.test.tmp.dll
@@ -89,7 +89,7 @@
 # CHECK6-NOT: duplicate /export option: _exportfn1
 
 # RUN: lld-link -safeseh:no /out:%t.dll /dll %t.obj /export:foo=mangled
-# RUN: llvm-objdump -p %t.dll | FileCheck -check-prefix=CHECK7 %s
+# RUN: llvm-objdump -p %t.dll | FileCheck --check-prefix=CHECK7 %s
 
 # CHECK7:      Export Table:
 # CHECK7:      DLL name: export32.test.tmp.dll
diff --git a/lld/test/COFF/imports-gnu-only.s b/lld/test/COFF/imports-gnu-only.s
index 8483598ede973..0895e1a7bdf98 100644
--- a/lld/test/COFF/imports-gnu-only.s
+++ b/lld/test/COFF/imports-gnu-only.s
@@ -8,7 +8,7 @@
 # RUN: llvm-mc -triple=x86_64-windows-gnu %s -filetype=obj -o %t.obj
 # RUN: lld-link -out:%t.exe -entry:main -subsystem:console \
 # RUN:   %t.obj %t-implib.a
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=DATA %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=DATA %s
 
         .text
         .global main
diff --git a/lld/test/COFF/imports-ordinal-only.s b/lld/test/COFF/imports-ordinal-only.s
index c560a73b9cf85..b55b60d7ef0c2 100644
--- a/lld/test/COFF/imports-ordinal-only.s
+++ b/lld/test/COFF/imports-ordinal-only.s
@@ -3,7 +3,7 @@
 # RUN: lld-link -machine:x86 -def:%p/Inputs/ordinal-only-implib.def -implib:%t-implib.a
 # RUN: llvm-mc -triple=i386-pc-win32 %s -filetype=obj -o %t.obj
 # RUN: lld-link -out:%t.exe -entry:main -subsystem:console -safeseh:no -debug %t.obj %t-implib.a
-# RUN: llvm-objdump -private-headers %t.exe | FileCheck --match-full-lines %s
+# RUN: llvm-objdump --private-headers %t.exe | FileCheck --match-full-lines %s
 
 .text
 .global _main
diff --git a/lld/test/COFF/imports.test b/lld/test/COFF/imports.test
index a3dbb86ec96cb..c120b82055edb 100644
--- a/lld/test/COFF/imports.test
+++ b/lld/test/COFF/imports.test
@@ -3,12 +3,12 @@
 #
 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console \
 # RUN:   %p/Inputs/hello64.obj %p/Inputs/std64.lib
-# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=TEXT %s
+# RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=TEXT %s
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
 
 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console \
 # RUN:   %p/Inputs/hello64.obj %p/Inputs/std64.lib /include:ExitProcess
-# RUN: llvm-objdump -d %t.exe | FileCheck -check-prefix=TEXT %s
+# RUN: llvm-objdump -d %t.exe | FileCheck --check-prefix=TEXT %s
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck -check-prefix=IMPORT %s
 
 TEXT: Disassembly of section .text:
diff --git a/lld/test/COFF/lto-comdat.ll b/lld/test/COFF/lto-comdat.ll
index ca7fa25546518..68a82c6d584a5 100644
--- a/lld/test/COFF/lto-comdat.ll
+++ b/lld/test/COFF/lto-comdat.ll
@@ -15,30 +15,30 @@
 ; of f1, f2, and comdat.
 ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.lto.obj %T/comdat1.lto.obj %T/comdat2.lto.obj
 ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-11 %s
-; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-11 %s
+; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck --check-prefix=TEXT-11 %s
 ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.lto.obj %T/comdat.lto.lib
 ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-11 %s
-; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-11 %s
+; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck --check-prefix=TEXT-11 %s
 
 ; Check that, when we use a non-LTO main with LTO objects, we pick the comdat
 ; implementation in LTO, elide calls to it from inside LTO, and retain the
 ; call to comdat from main.
 ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.obj %T/comdat1.lto.obj %T/comdat2.lto.obj
 ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-01 %s
-; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-01 %s
+; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck --check-prefix=TEXT-01 %s
 ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.obj %T/comdat.lto.lib
 ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-01 %s
-; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-01 %s
+; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck --check-prefix=TEXT-01 %s
 
 ; Check that, when we use an LTO main with non-LTO objects, we pick the comdat
 ; implementation in LTO, elide the call to it from inside LTO, and keep the
 ; calls to comdat from the non-LTO objects.
 ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.lto.obj %T/comdat1.obj %T/comdat2.obj
 ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-10 %s
-; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-10 %s
+; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck --check-prefix=TEXT-10 %s
 ; RUN: lld-link /out:%T/comdat-main.exe /entry:main /subsystem:console %T/comdat-main.lto.obj %T/comdat.lib
 ; RUN: llvm-readobj --file-headers %T/comdat-main.exe | FileCheck -check-prefix=HEADERS-10 %s
-; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck -check-prefix=TEXT-10 %s
+; RUN: llvm-objdump -d %T/comdat-main.exe | FileCheck --check-prefix=TEXT-10 %s
 
 ; HEADERS-11: AddressOfEntryPoint: 0x1000
 ; TEXT-11: Disassembly of section .text:
diff --git a/lld/test/COFF/lto-cpu-string.ll b/lld/test/COFF/lto-cpu-string.ll
index b31b6bf310db0..c2a8df5f75bad 100644
--- a/lld/test/COFF/lto-cpu-string.ll
+++ b/lld/test/COFF/lto-cpu-string.ll
@@ -2,11 +2,11 @@
 ; RUN: llvm-as %s -o %t.obj
 
 ; RUN: lld-link %t.obj -noentry -nodefaultlib -out:%t.dll -dll
-; RUN: llvm-objdump -d -section=".text" -no-leading-addr -no-show-raw-insn %t.dll | FileCheck %s
+; RUN: llvm-objdump -d --section=".text" --no-leading-addr --no-show-raw-insn %t.dll | FileCheck %s
 ; CHECK: nop{{$}}
 
 ; RUN: lld-link -mllvm:-mcpu=znver1 -noentry -nodefaultlib %t.obj -out:%t.znver1.dll -dll
-; RUN: llvm-objdump -d -section=".text" -no-leading-addr -no-show-raw-insn %t.znver1.dll | FileCheck -check-prefix=ZNVER1 %s
+; RUN: llvm-objdump -d --section=".text" --no-leading-addr --no-show-raw-insn %t.znver1.dll | FileCheck --check-prefix=ZNVER1 %s
 ; ZNVER1: nopw
 
 target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/lld/test/COFF/lto.ll b/lld/test/COFF/lto.ll
index 5a8b621303bf0..f00d25dda68a3 100644
--- a/lld/test/COFF/lto.ll
+++ b/lld/test/COFF/lto.ll
@@ -11,24 +11,24 @@
 
 ; RUN: lld-link /out:%T/main.exe /entry:main /include:f2 /subsystem:console %T/main.lto.obj %T/foo.lto.obj
 ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-11 %s
-; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-11 %s
+; RUN: llvm-objdump -d %T/main.exe | FileCheck --check-prefix=TEXT-11 %s
 ; RUN: lld-link /out:%T/main.exe /entry:main /include:f2 /subsystem:console %T/main.lto.obj %T/foo.lto.lib /verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
 ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-11 %s
-; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-11 %s
+; RUN: llvm-objdump -d %T/main.exe | FileCheck --check-prefix=TEXT-11 %s
 
 ; RUN: lld-link /out:%T/main.exe /entry:main /subsystem:console %T/main.obj %T/foo.lto.obj
 ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-01 %s
-; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-01 %s
+; RUN: llvm-objdump -d %T/main.exe | FileCheck --check-prefix=TEXT-01 %s
 ; RUN: lld-link /out:%T/main.exe /entry:main /subsystem:console %T/main.obj %T/foo.lto.lib
 ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-01 %s
-; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-01 %s
+; RUN: llvm-objdump -d %T/main.exe | FileCheck --check-prefix=TEXT-01 %s
 
 ; RUN: lld-link /out:%T/main.exe /entry:main /subsystem:console %T/main.lto.obj %T/foo.obj
 ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-10 %s
-; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-10 %s
+; RUN: llvm-objdump -d %T/main.exe | FileCheck --check-prefix=TEXT-10 %s
 ; RUN: lld-link /out:%T/main.exe /entry:main /subsystem:console %T/main.lto.obj %T/foo.lib
 ; RUN: llvm-readobj --file-headers %T/main.exe | FileCheck -check-prefix=HEADERS-10 %s
-; RUN: llvm-objdump -d %T/main.exe | FileCheck -check-prefix=TEXT-10 %s
+; RUN: llvm-objdump -d %T/main.exe | FileCheck --check-prefix=TEXT-10 %s
 
 ; VERBOSE: foo.lto.lib({{.*}}foo.lto.obj)
 
diff --git a/lld/test/COFF/no-idata.s b/lld/test/COFF/no-idata.s
index 419e58874570a..f19acce8cddb6 100644
--- a/lld/test/COFF/no-idata.s
+++ b/lld/test/COFF/no-idata.s
@@ -2,7 +2,7 @@
 #
 # RUN: llvm-mc -triple=x86_64-windows-gnu %s -filetype=obj -o %t.obj
 # RUN: lld-link -out:%t.exe -entry:main -subsystem:console %t.obj
-# RUN: llvm-objdump -s %t.exe | FileCheck -check-prefix=DUMP %s
+# RUN: llvm-objdump -s %t.exe | FileCheck --check-prefix=DUMP %s
 # RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=DIRECTORY %s
 
         .text
diff --git a/lld/test/COFF/options.test b/lld/test/COFF/options.test
index 37220f93de182..b700c6529f9f1 100644
--- a/lld/test/COFF/options.test
+++ b/lld/test/COFF/options.test
@@ -50,6 +50,16 @@ NXCOMPAT: IMAGE_DLL_CHARACTERISTICS_NX_COMPAT
 # RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=NONXCOMPAT %s
 NONXCOMPAT-NOT: IMAGE_DLL_CHARACTERISTICS_NX_COMPAT
 
+# RUN: lld-link /out:%t.exe /entry:main /cetcompat %t.obj
+# RUN: llvm-readobj --coff-debug-directory %t.exe | FileCheck -check-prefix=CETCOMPAT %s
+CETCOMPAT: IMAGE_DLL_CHARACTERISTICS_EX_CET_COMPAT
+
+# RUN: lld-link /out:%t.exe /entry:main %t.obj
+# RUN: llvm-readobj --coff-debug-directory %t.exe | FileCheck -check-prefix=NONCETCOMPAT %s
+# RUN: lld-link /out:%t.exe /entry:main /cetcompat:no %t.obj
+# RUN: llvm-readobj --coff-debug-directory %t.exe | FileCheck -check-prefix=NONCETCOMPAT %s
+NONCETCOMPAT-NOT: IMAGE_DLL_CHARACTERISTICS_EX_CET_COMPAT
+
 # RUN: lld-link /out:%t.exe /entry:main /swaprun:CD %t.obj
 # RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=SWAPCD %s
 # RUN: lld-link /out:%t.exe /entry:main /swaprun:cd,net %t.obj
diff --git a/lld/test/COFF/pdata-arm64.yaml b/lld/test/COFF/pdata-arm64.yaml
index 4f5210c4da81a..f868cb86058f8 100644
--- a/lld/test/COFF/pdata-arm64.yaml
+++ b/lld/test/COFF/pdata-arm64.yaml
@@ -1,7 +1,7 @@
 # RUN: yaml2obj < %s > %t.obj
 #
 # RUN: lld-link /out:%t.exe /entry:func1 /subsystem:console %t.obj
-# RUN: llvm-objdump -s -section=.pdata %t.exe | FileCheck -check-prefix=PDATA %s
+# RUN: llvm-objdump -s --section=.pdata %t.exe | FileCheck --check-prefix=PDATA %s
 
 # PDATA: 00100000 2500a100 24100000 31002201
 
diff --git a/lld/test/COFF/unwind.test b/lld/test/COFF/unwind.test
index 080174315d35d..b6d533a0901f1 100644
--- a/lld/test/COFF/unwind.test
+++ b/lld/test/COFF/unwind.test
@@ -2,7 +2,7 @@
 #
 # RUN: lld-link /out:%t.exe /entry:main %t.obj
 # RUN: llvm-readobj --file-headers %t.exe | FileCheck -check-prefix=HEADER %s
-# RUN: llvm-objdump -unwind-info %t.exe | FileCheck -check-prefix=UNWIND %s
+# RUN: llvm-objdump --unwind-info %t.exe | FileCheck --check-prefix=UNWIND %s
 #
 # RUN: lld-link /merge:.pdata=.rdata /out:%t.exe /entry:main %t.obj
 # RUN: llvm-readobj --file-headers --sections %t.exe | FileCheck -check-prefix=HEADER-MERGE %s
diff --git a/lld/test/ELF/aarch64-abs16.s b/lld/test/ELF/aarch64-abs16.s
index 5701be26dcebc..ee878ce7f5656 100644
--- a/lld/test/ELF/aarch64-abs16.s
+++ b/lld/test/ELF/aarch64-abs16.s
@@ -11,7 +11,7 @@ _start:
   .hword foo - 0x8100
 
 // RUN: ld.lld %t.o %t256.o -o %t2
-// RUN: llvm-objdump -s -section=.data %t2 | FileCheck %s
+// RUN: llvm-objdump -s --section=.data %t2 | FileCheck %s
 
 // CHECK: Contents of section .data:
 // 220158: S = 0x100, A = 0xfeff
diff --git a/lld/test/ELF/aarch64-abs32.s b/lld/test/ELF/aarch64-abs32.s
index 8e9a6b07148b9..147bdc0758cb8 100644
--- a/lld/test/ELF/aarch64-abs32.s
+++ b/lld/test/ELF/aarch64-abs32.s
@@ -11,7 +11,7 @@ _start:
   .word foo - 0x80000100
 
 // RUN: ld.lld %t.o %t256.o -o %t2
-// RUN: llvm-objdump -s -section=.data %t2 | FileCheck %s
+// RUN: llvm-objdump -s --section=.data %t2 | FileCheck %s
 
 // CHECK: Contents of section .data:
 // 220158: S = 0x100, A = 0xfffffeff
diff --git a/lld/test/ELF/aarch64-condb-reloc.s b/lld/test/ELF/aarch64-condb-reloc.s
index c0ca56360b5e6..8db1ebd1b3a8e 100644
--- a/lld/test/ELF/aarch64-condb-reloc.s
+++ b/lld/test/ELF/aarch64-condb-reloc.s
@@ -4,7 +4,7 @@
 # RUN: ld.lld %t1.o %t2.o -o %t
 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 # RUN: ld.lld -shared %t1.o %t2.o -o %t.so
-# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=DSO %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=DSO %s
 # RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s
 
 # 0x11024 - 36 = 0x11000
diff --git a/lld/test/ELF/aarch64-copy.s b/lld/test/ELF/aarch64-copy.s
index f3ef6b1de0fc8..ba7c8afd5ee13 100644
--- a/lld/test/ELF/aarch64-copy.s
+++ b/lld/test/ELF/aarch64-copy.s
@@ -4,8 +4,8 @@
 // RUN: ld.lld -shared %t2.o -soname fixed-length-string.so -o %t2.so
 // RUN: ld.lld %t.o %t2.so -o %t
 // RUN: llvm-readobj -S -r --symbols %t | FileCheck %s
-// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck -check-prefix=CODE %s
-// RUN: llvm-objdump -s -section=.rodata %t | FileCheck -check-prefix=RODATA %s
+// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=CODE %s
+// RUN: llvm-objdump -s --section=.rodata %t | FileCheck --check-prefix=RODATA %s
 
 .text
 .globl _start
diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-address.s b/lld/test/ELF/aarch64-cortex-a53-843419-address.s
index ebbaf01642e05..976c485bb2c9c 100644
--- a/lld/test/ELF/aarch64-cortex-a53-843419-address.s
+++ b/lld/test/ELF/aarch64-cortex-a53-843419-address.s
@@ -6,7 +6,7 @@
 // RUN:          .data : { *(.data) } }" > %t.script
 // RUN: ld.lld --script %t.script -fix-cortex-a53-843419 -verbose %t.o -o %t2 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-PRINT %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 | FileCheck %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 | FileCheck %s
 
 // Test cases for Cortex-A53 Erratum 843419 that involve interactions
 // between the generated patches and the address of sections.
diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-large.s b/lld/test/ELF/aarch64-cortex-a53-843419-large.s
index 8d13e36a391c6..e42303970f7b6 100644
--- a/lld/test/ELF/aarch64-cortex-a53-843419-large.s
+++ b/lld/test/ELF/aarch64-cortex-a53-843419-large.s
@@ -1,13 +1,13 @@
 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
 // RUN: ld.lld --fix-cortex-a53-843419 -z separate-code %t.o -o %t2
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2162688   -stop-address=2162700   | FileCheck --check-prefix=CHECK1 %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2166784   -stop-address=2166788   | FileCheck --check-prefix=CHECK2 %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=2170872   -stop-address=2170888   | FileCheck --check-prefix=CHECK3 %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=69287928  -stop-address=69287944  | FileCheck --check-prefix=CHECK4 %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=102842376 -stop-address=102842392 | FileCheck --check-prefix=CHECK5 %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136384524 -stop-address=136384528 | FileCheck --check-prefix=CHECK6 %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 -start-address=136388604 -stop-address=136388628 | FileCheck --check-prefix=CHECK7 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=2162688   --stop-address=2162700   | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=2166784   --stop-address=2166788   | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=2170872   --stop-address=2170888   | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=69287928  --stop-address=69287944  | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=102842376 --stop-address=102842392 | FileCheck --check-prefix=CHECK5 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=136384524 --stop-address=136384528 | FileCheck --check-prefix=CHECK6 %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 --start-address=136388604 --stop-address=136388628 | FileCheck --check-prefix=CHECK7 %s
 // Test case for Cortex-A53 Erratum 843419 in an OutputSection exceeding
 // the maximum branch range. Both range extension thunks and patches are
 // required.					      
diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s b/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s
index 0933b1aac16eb..0a737eaa152b4 100644
--- a/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s
+++ b/lld/test/ELF/aarch64-cortex-a53-843419-recognize.s
@@ -1,11 +1,11 @@
 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
 // RUN: ld.lld -fix-cortex-a53-843419 -z separate-code -verbose %t.o -o %t2 2>&1 | FileCheck -check-prefix CHECK-PRINT %s
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 | FileCheck %s -check-prefixes=CHECK,CHECK-FIX
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 | FileCheck %s --check-prefixes=CHECK,CHECK-FIX
 // RUN: ld.lld %t.o -z separate-code -o %t3
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t3 | FileCheck %s -check-prefixes=CHECK,CHECK-NOFIX
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t3 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFIX
 // RUN: ld.lld -fix-cortex-a53-843419 -r -z separate-code %t.o -o %t4
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t4 | FileCheck %s -check-prefixes=CHECK-RELOCATABLE
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t4 | FileCheck %s --check-prefixes=CHECK-RELOCATABLE
 // Test cases for Cortex-A53 Erratum 843419
 // See ARM-EPM-048406 Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
 // for full erratum details.
diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-thunk-align.s b/lld/test/ELF/aarch64-cortex-a53-843419-thunk-align.s
index a410233dcdfbf..9320d510d9110 100644
--- a/lld/test/ELF/aarch64-cortex-a53-843419-thunk-align.s
+++ b/lld/test/ELF/aarch64-cortex-a53-843419-thunk-align.s
@@ -7,7 +7,7 @@
 // RUN:                  *(.text.02) } \
 // RUN:                  .foo : { *(.foo_sec) } } " > %t.script
 // RUN: ld.lld -pie --fix-cortex-a53-843419 --script=%t.script %t.o -o %t2
-// RUN: llvm-objdump --no-show-raw-insn -triple=aarch64-linux-gnu -d %t2
+// RUN: llvm-objdump --no-show-raw-insn --triple=aarch64-linux-gnu -d %t2
 
 
 /// %t2 is > 128 Megabytes, so delete it early.
diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-thunk.s b/lld/test/ELF/aarch64-cortex-a53-843419-thunk.s
index 4e449b7fd7875..5510dde285551 100644
--- a/lld/test/ELF/aarch64-cortex-a53-843419-thunk.s
+++ b/lld/test/ELF/aarch64-cortex-a53-843419-thunk.s
@@ -5,7 +5,7 @@
 // RUN:          .text2 0x8010000 : { *(.text.04) } } " > %t.script
 // RUN: ld.lld --script %t.script -fix-cortex-a53-843419 -verbose %t.o -o %t2 \
 // RUN:   2>&1 | FileCheck -check-prefix=CHECK-PRINT %s
-// RUN: llvm-objdump --no-show-raw-insn -triple=aarch64-linux-gnu -d %t2 | FileCheck %s
+// RUN: llvm-objdump --no-show-raw-insn --triple=aarch64-linux-gnu -d %t2 | FileCheck %s
 
 /// %t2 is 128 Megabytes, so delete it early.
 // RUN: rm %t2
diff --git a/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s b/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s
index b7e4121646ff1..3be0315a75174 100644
--- a/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s
+++ b/lld/test/ELF/aarch64-cortex-a53-843419-tlsrelax.s
@@ -1,7 +1,7 @@
 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
 // RUN: ld.lld -fix-cortex-a53-843419 %t.o -o %t2
-// RUN: llvm-objdump -triple=aarch64-linux-gnu -d %t2 | FileCheck %s
+// RUN: llvm-objdump --triple=aarch64-linux-gnu -d %t2 | FileCheck %s
 
 // The following code sequence is covered by the TLS IE to LE relaxation. It
 // transforms the ADRP, LDR to MOVZ, MOVK. The former can trigger a
diff --git a/lld/test/ELF/aarch64-feature-bti.s b/lld/test/ELF/aarch64-feature-bti.s
index 6b4520791f2a9..b37527924d13a 100644
--- a/lld/test/ELF/aarch64-feature-bti.s
+++ b/lld/test/ELF/aarch64-feature-bti.s
@@ -9,7 +9,7 @@
 ## field.
 
 # RUN: ld.lld %tno.o %t3.o --shared -o %tno.so
-# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOBTI %s
+# RUN: llvm-objdump -d --mattr=+bti --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOBTI %s
 # RUN: llvm-readelf -x .got.plt %tno.so | FileCheck --check-prefix SOGOTPLT %s
 # RUN: llvm-readelf --dynamic-table %tno.so | FileCheck --check-prefix NOBTIDYN %s
 
@@ -46,7 +46,7 @@
 
 # RUN: ld.lld %t1.o %t3.o --shared --soname=t.so -o %t.so
 # RUN: llvm-readelf -n %t.so | FileCheck --check-prefix BTIPROP %s
-# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %t.so | FileCheck --check-prefix BTISO %s
+# RUN: llvm-objdump -d --mattr=+bti --no-show-raw-insn %t.so | FileCheck --check-prefix BTISO %s
 # RUN: llvm-readelf -x .got.plt %t.so | FileCheck --check-prefix SOGOTPLT2 %s
 # RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix BTIDYN %s
 
@@ -88,7 +88,7 @@
 
 # RUN: ld.lld %t.o %t.so %t2.so -o %t.exe
 # RUN: llvm-readelf --dynamic-table -n %t.exe | FileCheck --check-prefix=BTIPROP %s
-# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %t.exe | FileCheck --check-prefix=EXECBTI %s
+# RUN: llvm-objdump -d --mattr=+bti --no-show-raw-insn %t.exe | FileCheck --check-prefix=EXECBTI %s
 
 # EXECBTI: Disassembly of section .text:
 # EXECBTI: 0000000000210348 <func1>:
@@ -116,7 +116,7 @@
 # RUN: ld.lld --pie %t.o %t.so %t2.so -o %tpie.exe
 # RUN: llvm-readelf -n %tpie.exe | FileCheck --check-prefix=BTIPROP %s
 # RUN: llvm-readelf --dynamic-table -n %tpie.exe | FileCheck --check-prefix=BTIPROP %s
-# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tpie.exe | FileCheck --check-prefix=PIE %s
+# RUN: llvm-objdump -d --mattr=+bti --no-show-raw-insn %tpie.exe | FileCheck --check-prefix=PIE %s
 
 # PIE: Disassembly of section .text:
 # PIE: 0000000000010348 <func1>:
@@ -145,7 +145,7 @@
 
 # RUN: ld.lld %t.o %t2.o %t.so -o %tnobti.exe
 # RUN: llvm-readelf --dynamic-table %tnobti.exe | FileCheck --check-prefix NOBTIDYN %s
-# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tnobti.exe | FileCheck --check-prefix=NOEX %s
+# RUN: llvm-objdump -d --mattr=+bti --no-show-raw-insn %tnobti.exe | FileCheck --check-prefix=NOEX %s
 
 # NOEX: Disassembly of section .text:
 # NOEX: 00000000002102e0 <func1>:
@@ -179,7 +179,7 @@
 
 # RUN: llvm-readelf -n %tforcebti.exe | FileCheck --check-prefix=BTIPROP %s
 # RUN: llvm-readelf --dynamic-table %tforcebti.exe | FileCheck --check-prefix BTIDYN %s
-# RUN: llvm-objdump -d -mattr=+bti --no-show-raw-insn %tforcebti.exe | FileCheck --check-prefix=FORCE %s
+# RUN: llvm-objdump -d --mattr=+bti --no-show-raw-insn %tforcebti.exe | FileCheck --check-prefix=FORCE %s
 
 # FORCE: Disassembly of section .text:
 # FORCE: 0000000000210370 <func1>:
diff --git a/lld/test/ELF/aarch64-feature-btipac.s b/lld/test/ELF/aarch64-feature-btipac.s
index 708e336b0add0..da08b66010076 100644
--- a/lld/test/ELF/aarch64-feature-btipac.s
+++ b/lld/test/ELF/aarch64-feature-btipac.s
@@ -11,7 +11,7 @@
 
 # RUN: ld.lld %t1.o %t3btipac.o --shared --soname=t.so -o %t.so
 # RUN: llvm-readelf -n %t.so | FileCheck --check-prefix BTIPACPROP %s
-# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.so | FileCheck --check-prefix BTIPACSO %s
+# RUN: llvm-objdump -d --mattr=+v8.5a --no-show-raw-insn %t.so | FileCheck --check-prefix BTIPACSO %s
 # RUN: llvm-readelf --dynamic-table %t.so | FileCheck --check-prefix BTIPACDYN %s
 
 # BTIPACSO: Disassembly of section .text:
@@ -47,7 +47,7 @@
 
 # RUN: ld.lld %t.o %t3btipac.o %t.so -o %t.exe
 # RUN: llvm-readelf -n %t.exe | FileCheck --check-prefix=BTIPACPROP %s
-# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix BTIPACEX %s
+# RUN: llvm-objdump -d --mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix BTIPACEX %s
 # RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix BTIPACDYNEX %s
 
 # BTIPACEX: Disassembly of section .text:
@@ -80,7 +80,7 @@
 ## Check that combinations of BTI+PAC with 0 properties results in standard PLT
 
 # RUN: ld.lld %t.o %t3.o %t.so -o %t.exe
-# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix EX %s
+# RUN: llvm-objdump -d --mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix EX %s
 # RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix=NODYN %s
 
 # EX: Disassembly of section .text:
@@ -121,7 +121,7 @@
 # FORCE-WARN: aarch64-feature-btipac.s.tmp3.o: -z force-bti: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_BTI property
 
 # RUN: llvm-readelf -n %t.exe | FileCheck --check-prefix=BTIPACPROP %s
-# RUN: llvm-objdump -d -mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix BTIPACEX2 %s
+# RUN: llvm-objdump -d --mattr=+v8.5a --no-show-raw-insn %t.exe | FileCheck --check-prefix BTIPACEX2 %s
 # RUN: llvm-readelf --dynamic-table %t.exe | FileCheck --check-prefix BTIPACDYN2 %s
 .section ".note.gnu.property", "a"
 .long 4
diff --git a/lld/test/ELF/aarch64-feature-pac.s b/lld/test/ELF/aarch64-feature-pac.s
index e75cc7025cd4c..b71428d57eb45 100644
--- a/lld/test/ELF/aarch64-feature-pac.s
+++ b/lld/test/ELF/aarch64-feature-pac.s
@@ -9,7 +9,7 @@
 ## field.
 
 # RUN: ld.lld %tno.o %t3.o --shared -o %tno.so
-# RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOPAC %s
+# RUN: llvm-objdump -d --mattr=+v8.3a --no-show-raw-insn %tno.so | FileCheck --check-prefix=NOPAC %s
 # RUN: llvm-readelf -x .got.plt %tno.so | FileCheck --check-prefix SOGOTPLT %s
 # RUN: llvm-readelf --dynamic-table %tno.so | FileCheck --check-prefix NOPACDYN %s
 
@@ -41,7 +41,7 @@
 
 # RUN: ld.lld %t1.o %t3.o --shared --soname=t.so -o %t.so
 # RUN: llvm-readelf -n %t.so | FileCheck --check-prefix PACPROP %s
-# RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %t.so | FileCheck --check-prefix PACSO %s
+# RUN: llvm-objdump -d --mattr=+v8.3a --no-show-raw-insn %t.so | FileCheck --check-prefix PACSO %s
 # RUN: llvm-readelf -x .got.plt %t.so | FileCheck --check-prefix SOGOTPLT2 %s
 # RUN: llvm-readelf --dynamic-table %t.so |  FileCheck --check-prefix PACDYN %s
 
@@ -84,7 +84,7 @@
 # RUN: ld.lld %t.o %t2.o -z pac-plt %t.so -o %tpacplt.exe
 # RUN: llvm-readelf -n %tpacplt.exe | FileCheck --check-prefix=PACPROP %s
 # RUN: llvm-readelf --dynamic-table %tpacplt.exe | FileCheck --check-prefix PACDYN2 %s
-# RUN: llvm-objdump -d -mattr=+v8.3a --no-show-raw-insn %tpacplt.exe | FileCheck --check-prefix PACPLT %s
+# RUN: llvm-objdump -d --mattr=+v8.3a --no-show-raw-insn %tpacplt.exe | FileCheck --check-prefix PACPLT %s
 
 # PACPLT: Disassembly of section .text:
 # PACPLT: 0000000000210370 <func1>:
diff --git a/lld/test/ELF/aarch64-ifunc-bti.s b/lld/test/ELF/aarch64-ifunc-bti.s
index cb32d95198f8c..a6434289691a2 100644
--- a/lld/test/ELF/aarch64-ifunc-bti.s
+++ b/lld/test/ELF/aarch64-ifunc-bti.s
@@ -4,7 +4,7 @@
 
 # RUN: ld.lld --shared --soname=t1.so %t1.o -o %t1.so
 # RUN: ld.lld --pie %t1.so %t.o -o %t
-# RUN: llvm-objdump -d --no-show-raw-insn -mattr=+bti -triple=aarch64-linux-gnu %t | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn --mattr=+bti --triple=aarch64-linux-gnu %t | FileCheck %s
 
 # When the address of an ifunc is taken using a non-got reference which clang
 # can do, LLD exports a canonical PLT entry that may have its address taken so
diff --git a/lld/test/ELF/aarch64-plt.s b/lld/test/ELF/aarch64-plt.s
index 5595596b21429..50a65497fb45e 100644
--- a/lld/test/ELF/aarch64-plt.s
+++ b/lld/test/ELF/aarch64-plt.s
@@ -5,10 +5,10 @@
 // RUN: ld.lld -shared %t.o %t2.so -o %t.so
 // RUN: ld.lld %t.o %t2.so -o %t.exe
 // RUN: llvm-readobj -S -r %t.so | FileCheck --check-prefix=CHECKDSO %s
-// RUN: llvm-objdump -s -section=.got.plt %t.so | FileCheck --check-prefix=DUMPDSO %s
+// RUN: llvm-objdump -s --section=.got.plt %t.so | FileCheck --check-prefix=DUMPDSO %s
 // RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.so | FileCheck --check-prefix=DISASMDSO %s
 // RUN: llvm-readobj -S -r %t.exe | FileCheck --check-prefix=CHECKEXE %s
-// RUN: llvm-objdump -s -section=.got.plt %t.exe | FileCheck --check-prefix=DUMPEXE %s
+// RUN: llvm-objdump -s --section=.got.plt %t.exe | FileCheck --check-prefix=DUMPEXE %s
 // RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.exe | FileCheck --check-prefix=DISASMEXE %s
 
 // CHECKDSO:     Name: .plt
diff --git a/lld/test/ELF/aarch64-prel16.s b/lld/test/ELF/aarch64-prel16.s
index 078336f6ae38c..2335dfb5cd70c 100644
--- a/lld/test/ELF/aarch64-prel16.s
+++ b/lld/test/ELF/aarch64-prel16.s
@@ -15,7 +15,7 @@ _start:
 //       You may found the correct address in the aarch64_abs16.s test,
 //       if it is already fixed. Then, update addends accordingly.
 // RUN: ld.lld -z max-page-size=4096 %t.o %t256.o -o %t2
-// RUN: llvm-objdump -s -section=.data %t2 | FileCheck %s
+// RUN: llvm-objdump -s --section=.data %t2 | FileCheck %s
 
 // CHECK: Contents of section .data:
 // 202158: S = 0x100, A = 0x212157, P = 0x202158
diff --git a/lld/test/ELF/aarch64-prel32.s b/lld/test/ELF/aarch64-prel32.s
index 760f60040ce59..8dd71792e2ed0 100644
--- a/lld/test/ELF/aarch64-prel32.s
+++ b/lld/test/ELF/aarch64-prel32.s
@@ -15,7 +15,7 @@ _start:
 //       You may found the correct address in the aarch64_abs32.s test,
 //       if it is already fixed. Then, update addends accordingly.
 // RUN: ld.lld -z max-page-size=4096 %t.o %t256.o -o %t2
-// RUN: llvm-objdump -s -section=.data %t2 | FileCheck %s
+// RUN: llvm-objdump -s --section=.data %t2 | FileCheck %s
 
 // CHECK: Contents of section .data:
 // 202158: S = 0x100, A = 0x100202057, P = 0x202158
diff --git a/lld/test/ELF/aarch64-thunk-section-location.s b/lld/test/ELF/aarch64-thunk-section-location.s
index 5fb575c5b7d4e..11963e705c6c2 100644
--- a/lld/test/ELF/aarch64-thunk-section-location.s
+++ b/lld/test/ELF/aarch64-thunk-section-location.s
@@ -1,7 +1,7 @@
 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %s -o %t.o
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -d --start-address=0x81d1008 -stop-address=0x81d1014 --no-show-raw-insn %t | FileCheck %s
+// RUN: llvm-objdump -d --start-address=0x81d1008 --stop-address=0x81d1014 --no-show-raw-insn %t | FileCheck %s
 // Check that the range extension thunks are dumped close to the aarch64 branch
 // range of 128 MiB
  .section .text.1, "ax", %progbits
diff --git a/lld/test/ELF/aarch64-tstbr14-reloc.s b/lld/test/ELF/aarch64-tstbr14-reloc.s
index 94ed45a19b60c..dd946ebda52c1 100644
--- a/lld/test/ELF/aarch64-tstbr14-reloc.s
+++ b/lld/test/ELF/aarch64-tstbr14-reloc.s
@@ -4,7 +4,7 @@
 # RUN: ld.lld %t1 %t2 -o %t
 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 # RUN: ld.lld -shared %t1 %t2 -o %t3
-# RUN: llvm-objdump -d --no-show-raw-insn %t3 | FileCheck -check-prefix=DSO %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t3 | FileCheck --check-prefix=DSO %s
 # RUN: llvm-readobj -S -r %t3 | FileCheck -check-prefix=DSOREL %s
 
 # CHECK:      <_foo>:
diff --git a/lld/test/ELF/allow-multiple-definition.s b/lld/test/ELF/allow-multiple-definition.s
index aa151d827c956..8a3b97c0102e5 100644
--- a/lld/test/ELF/allow-multiple-definition.s
+++ b/lld/test/ELF/allow-multiple-definition.s
@@ -7,12 +7,12 @@
 # RUN: ld.lld --allow-multiple-definition --fatal-warnings %t1 %t2 -o %t3
 # RUN: ld.lld --allow-multiple-definition --fatal-warnings %t2 %t1 -o %t4
 # RUN: llvm-objdump -d %t3 | FileCheck %s
-# RUN: llvm-objdump -d %t4 | FileCheck -check-prefix=REVERT %s
+# RUN: llvm-objdump -d %t4 | FileCheck --check-prefix=REVERT %s
 
 # RUN: ld.lld -z muldefs --fatal-warnings  %t1 %t2 -o %t3
 # RUN: ld.lld -z muldefs --fatal-warnings  %t2 %t1 -o %t4
 # RUN: llvm-objdump -d %t3 | FileCheck %s
-# RUN: llvm-objdump -d %t4 | FileCheck -check-prefix=REVERT %s
+# RUN: llvm-objdump -d %t4 | FileCheck --check-prefix=REVERT %s
 
 # inputs contain different constants for instuction movl.
 # Tests below checks that order of files in command line
diff --git a/lld/test/ELF/arm-bl-v6-inrange.s b/lld/test/ELF/arm-bl-v6-inrange.s
index d4f81f855a730..7a0abf276ae7c 100644
--- a/lld/test/ELF/arm-bl-v6-inrange.s
+++ b/lld/test/ELF/arm-bl-v6-inrange.s
@@ -5,7 +5,7 @@
 // RUN:          .caller  0x500000 : { *(.text) } \
 // RUN:          .callee2 0x900004 : { *(.callee_high) } } " > %t.script
 // RUN: ld.lld %t --script %t.script -o %t2
-// RUN: llvm-objdump -d -triple=armv6-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi %t2 | FileCheck %s
 
 // On older Arm Architectures such as v5 and v6 the Thumb BL and BLX relocation
 // uses a slightly different encoding that has a lower range. These relocations
diff --git a/lld/test/ELF/arm-bl-v6.s b/lld/test/ELF/arm-bl-v6.s
index 2f7f11ad5972c..353ec56296470 100644
--- a/lld/test/ELF/arm-bl-v6.s
+++ b/lld/test/ELF/arm-bl-v6.s
@@ -1,10 +1,10 @@
 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv6-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -d -triple=armv6-none-linux-gnueabi -start-address=0x12000 -stop-address=0x12008 %t2 | FileCheck -check-prefix=CHECK-ARM1 %s
-// RUN: llvm-objdump -d -triple=thumbv6-none-linux-gnueabi %t2 -start-address=0x12008 -stop-address=0x1200c | FileCheck -check-prefix=CHECK-THUMB1 %s
-// RUN: llvm-objdump -d -triple=armv6-none-linux-gnueabi -start-address=0x21200c -stop-address=0x212014 %t2 | FileCheck -check-prefix=CHECK-ARM2 %s
-// RUN: llvm-objdump -d -triple=thumbv6-none-linux-gnueabi %t2 -start-address=0x613000 -stop-address=0x613002 | FileCheck -check-prefix=CHECK-THUMB2 %s
+// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi --start-address=0x12000 --stop-address=0x12008 %t2 | FileCheck --check-prefix=CHECK-ARM1 %s
+// RUN: llvm-objdump -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x12008 --stop-address=0x1200c | FileCheck --check-prefix=CHECK-THUMB1 %s
+// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi --start-address=0x21200c --stop-address=0x212014 %t2 | FileCheck --check-prefix=CHECK-ARM2 %s
+// RUN: llvm-objdump -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x613000 --stop-address=0x613002 | FileCheck --check-prefix=CHECK-THUMB2 %s
 
 // On Arm v6 the range of a Thumb BL instruction is only 4 megabytes as the
 // extended range encoding is not supported. The following example has a Thumb
diff --git a/lld/test/ELF/arm-blx.s b/lld/test/ELF/arm-blx.s
index deb5544e13eac..5be3faa4c947f 100644
--- a/lld/test/ELF/arm-blx.s
+++ b/lld/test/ELF/arm-blx.s
@@ -9,7 +9,7 @@
 // RUN:          .callee3 : { *(.callee_high) } \
 // RUN:          .callee4 : { *(.callee_arm_high) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %tfar -o %t2
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 
 // Test BLX instruction is chosen for ARM BL/BLX instruction and Thumb callee
 // Using two callees to ensure at least one has 2-byte alignment.
diff --git a/lld/test/ELF/arm-branch-rangethunk.s b/lld/test/ELF/arm-branch-rangethunk.s
index d00f446e554a8..81c0618871f4b 100644
--- a/lld/test/ELF/arm-branch-rangethunk.s
+++ b/lld/test/ELF/arm-branch-rangethunk.s
@@ -2,10 +2,10 @@
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-abs.s -o %tfar
 // RUN: ld.lld  %t %tfar -o %t2
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=SHORT %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=SHORT %s
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-long-arm-abs.s -o %tfarlong
 // RUN: ld.lld  %t %tfarlong -o %t3
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=LONG %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=LONG %s
  .syntax unified
  .section .text, "ax",%progbits
  .globl _start
diff --git a/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s b/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s
index bcf801371879d..9a4a41fd800b0 100644
--- a/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s
+++ b/lld/test/ELF/arm-branch-undef-weak-plt-thunk.s
@@ -3,7 +3,7 @@
 // RUN: ld.lld %t1.o --shared -soname=t1.so -o %t1.so
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o %t1.so -o %t
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi -start-address=0x111e4 -stop-address=0x11204 %t | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --start-address=0x111e4 --stop-address=0x11204 %t | FileCheck %s
 
 // When we are dynamic linking, undefined weak references have a PLT entry so
 // we must create a thunk for the branch to the PLT entry.
diff --git a/lld/test/ELF/arm-branch.s b/lld/test/ELF/arm-branch.s
index c20b575f2e9a7..c2fab0571bcb0 100644
--- a/lld/test/ELF/arm-branch.s
+++ b/lld/test/ELF/arm-branch.s
@@ -7,7 +7,7 @@
 // RUN:          .caller : { *(.text) } \
 // RUN:          .callee2 : { *(.callee_high) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %tfar -o %t2
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck  %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck  %s
  .syntax unified
  .section .callee_low, "ax",%progbits
  .align 2
diff --git a/lld/test/ELF/arm-copy.s b/lld/test/ELF/arm-copy.s
index 942825528289c..afdfb9f93dbd8 100644
--- a/lld/test/ELF/arm-copy.s
+++ b/lld/test/ELF/arm-copy.s
@@ -4,8 +4,8 @@
 // RUN: ld.lld -shared %t2.o -soname fixed-length-string.so -o %t2.so
 // RUN: ld.lld --hash-style=sysv %t.o %t2.so -o %t3
 // RUN: llvm-readobj -S -r --expand-relocs --symbols %t3 | FileCheck %s
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t3 | FileCheck -check-prefix=CODE %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi -section=.rodata %t3 | FileCheck -check-prefix=RODATA %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t3 | FileCheck --check-prefix=CODE %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi --section=.rodata %t3 | FileCheck --check-prefix=RODATA %s
 
 // Copy relocations R_ARM_COPY are required for y and z
  .syntax unified
diff --git a/lld/test/ELF/arm-exidx-add-missing.s b/lld/test/ELF/arm-exidx-add-missing.s
index 5661996286367..1beaa299a82e0 100644
--- a/lld/test/ELF/arm-exidx-add-missing.s
+++ b/lld/test/ELF/arm-exidx-add-missing.s
@@ -3,7 +3,7 @@
 // RUN: ld.lld %t --no-merge-exidx-entries -o %t2
 // RUN: llvm-objdump -s %t2 | FileCheck %s
 // RUN: ld.lld %t -o %t3
-// RUN: llvm-objdump -s %t3 | FileCheck %s -check-prefix=CHECK-MERGE
+// RUN: llvm-objdump -s %t3 | FileCheck %s --check-prefix=CHECK-MERGE
 
 // The ARM.exidx section is a table of 8-byte entries of the form:
 // | PREL31 Relocation to start of function | Unwinding information |
diff --git a/lld/test/ELF/arm-exidx-canunwind.s b/lld/test/ELF/arm-exidx-canunwind.s
index d701e208a0537..765892ef544d9 100644
--- a/lld/test/ELF/arm-exidx-canunwind.s
+++ b/lld/test/ELF/arm-exidx-canunwind.s
@@ -1,8 +1,8 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EXIDX %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-EXIDX %s
 // RUN: llvm-readobj --program-headers --sections %t2 | FileCheck -check-prefix=CHECK-PT %s
 
 // Test that inline unwinding table entries and references to .ARM.extab
diff --git a/lld/test/ELF/arm-exidx-dedup-and-sentinel.s b/lld/test/ELF/arm-exidx-dedup-and-sentinel.s
index 84ef318a3850f..522c86daef738 100644
--- a/lld/test/ELF/arm-exidx-dedup-and-sentinel.s
+++ b/lld/test/ELF/arm-exidx-dedup-and-sentinel.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -shared -o %t.so --section-start .text=0x2000 --section-start .ARM.exidx=0x1000
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t.so | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t.so | FileCheck %s
 
  .syntax unified
 
diff --git a/lld/test/ELF/arm-exidx-emit-relocs.s b/lld/test/ELF/arm-exidx-emit-relocs.s
index 8df50178829c2..f0d2941bf38fd 100644
--- a/lld/test/ELF/arm-exidx-emit-relocs.s
+++ b/lld/test/ELF/arm-exidx-emit-relocs.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld --emit-relocs %t -o %t2
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 // RUN: llvm-readelf --relocs %t2 | FileCheck -check-prefix=CHECK-RELOCS %s
 
 // LLD does not support --emit-relocs for .ARM.exidx sections as the relocations
diff --git a/lld/test/ELF/arm-exidx-gc.s b/lld/test/ELF/arm-exidx-gc.s
index d50b90c4c56ff..117f2cfb51734 100644
--- a/lld/test/ELF/arm-exidx-gc.s
+++ b/lld/test/ELF/arm-exidx-gc.s
@@ -1,8 +1,8 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t --no-merge-exidx-entries -o %t2 --gc-sections
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EXIDX %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-EXIDX %s
 
 // Test the behavior of .ARM.exidx sections under garbage collection
 // A .ARM.exidx section is live if it has a relocation to a live executable
diff --git a/lld/test/ELF/arm-exidx-order.s b/lld/test/ELF/arm-exidx-order.s
index 40715c0c1a993..7cae2b2acc7c5 100644
--- a/lld/test/ELF/arm-exidx-order.s
+++ b/lld/test/ELF/arm-exidx-order.s
@@ -2,16 +2,16 @@
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/arm-exidx-cantunwind.s -o %tcantunwind
 // RUN: ld.lld --no-merge-exidx-entries %t %tcantunwind -o %t2
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-EXIDX %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-EXIDX %s
 // RUN: llvm-readobj --program-headers --sections %t2 | FileCheck -check-prefix=CHECK-PT %s
 // Use Linker script to place .ARM.exidx in between .text and orphan sections
 // RUN: echo "SECTIONS { \
 // RUN:          .text 0x11000 : { *(.text*) } \
 // RUN:          .ARM.exidx : { *(.ARM.exidx) } } " > %t.script
 // RUN: ld.lld --no-merge-exidx-entries --script %t.script %tcantunwind %t -o %t3
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-SCRIPT %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-SCRIPT-EXIDX %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=CHECK-SCRIPT %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=CHECK-SCRIPT-EXIDX %s
 
 // Each assembler created .ARM.exidx section has the SHF_LINK_ORDER flag set
 // with the sh_link containing the section index of the executable section
diff --git a/lld/test/ELF/arm-exidx-sentinel-orphan.s b/lld/test/ELF/arm-exidx-sentinel-orphan.s
index 9aebc4299184b..61e8dfc1840d9 100644
--- a/lld/test/ELF/arm-exidx-sentinel-orphan.s
+++ b/lld/test/ELF/arm-exidx-sentinel-orphan.s
@@ -6,7 +6,7 @@
 // RUN:          .text 0x11000 : { *(.text*) } \
 // RUN:          } " > %t.script
 // RUN: ld.lld --no-merge-exidx-entries --script %t.script %t -o %t2
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 
  .syntax unified
  .text
diff --git a/lld/test/ELF/arm-exidx-shared.s b/lld/test/ELF/arm-exidx-shared.s
index e5ad085cbd24e..8f7e7ae2f05f6 100644
--- a/lld/test/ELF/arm-exidx-shared.s
+++ b/lld/test/ELF/arm-exidx-shared.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc -filetype=obj -arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld --hash-style=sysv %t --shared -o %t2
 // RUN: llvm-readobj --relocations %t2 | FileCheck %s
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-EXTAB-NEXT %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-EXTAB-NEXT %s
 
 // Check that the relative R_ARM_PREL31 relocation can access a PLT entry
 // for when the personality routine is referenced from a shared library.
diff --git a/lld/test/ELF/arm-extreme-range-pi-thunk.s b/lld/test/ELF/arm-extreme-range-pi-thunk.s
index 84941663d93d6..cba81ef30510f 100644
--- a/lld/test/ELF/arm-extreme-range-pi-thunk.s
+++ b/lld/test/ELF/arm-extreme-range-pi-thunk.s
@@ -5,11 +5,11 @@
 // RUN: echo "          .text_high 0xf0000000 : AT(0x1000) { *(.text_high) }" >> %t.script
 // RUN: echo "       } " >> %t.script
 // RUN: ld.lld --script %t.script --pie --static %t -o %t2
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --no-show-raw-insn %t2 | FileCheck %s
 
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t3
 // RUN: ld.lld --script %t.script --pie %t3 -o %t4
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi --no-show-raw-insn %t4 | FileCheck -check-prefix=CHECK-THUMB %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi --no-show-raw-insn %t4 | FileCheck --check-prefix=CHECK-THUMB %s
 
 // Check that we can create Arm and Thumb v7a Position Independent Thunks that
 // can span the address space without triggering overflow errors. We use an
diff --git a/lld/test/ELF/arm-force-pi-thunk.s b/lld/test/ELF/arm-force-pi-thunk.s
index 3b7b2976cc58e..5504b4e19bd9d 100644
--- a/lld/test/ELF/arm-force-pi-thunk.s
+++ b/lld/test/ELF/arm-force-pi-thunk.s
@@ -6,7 +6,7 @@
 // RUN:       .text_high 0x2000000 : { *(.text_high) *(.text_high2) } \
 // RUN:       } " > %t.script
 // RUN: ld.lld --pic-veneer --script %t.script %t -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
 
 // Test that we can force generation of position independent thunks even when
 // inputs are not pic.
diff --git a/lld/test/ELF/arm-fpic-got.s b/lld/test/ELF/arm-fpic-got.s
index e89a4aa3db7a0..6d9eb4b0326e2 100644
--- a/lld/test/ELF/arm-fpic-got.s
+++ b/lld/test/ELF/arm-fpic-got.s
@@ -3,7 +3,7 @@
 // RUN: ld.lld %t.o -o %t
 // RUN: llvm-readobj -S %t | FileCheck %s
 // RUN: llvm-readobj -S --symbols %t | FileCheck -check-prefix=SYMBOLS %s
-// RUN: llvm-objdump -d --no-show-raw-insn -triple=armv7a-none-linux-gnueabi %t | FileCheck -check-prefix=CODE %s
+// RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7a-none-linux-gnueabi %t | FileCheck --check-prefix=CODE %s
 
 // Test the R_ARM_GOT_PREL relocation
  .syntax unified
diff --git a/lld/test/ELF/arm-gnu-ifunc-plt.s b/lld/test/ELF/arm-gnu-ifunc-plt.s
index c9119a2dbaeeb..35e2fd7b31b81 100644
--- a/lld/test/ELF/arm-gnu-ifunc-plt.s
+++ b/lld/test/ELF/arm-gnu-ifunc-plt.s
@@ -3,7 +3,7 @@
 // RUN: ld.lld %t1.o --shared -soname=t.so -o %t.so
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf %s -o %t.o
 // RUN: ld.lld %t.so %t.o -o %tout
-// RUN: llvm-objdump -triple=armv7a-linux-gnueabihf -d --no-show-raw-insn %tout | FileCheck %s --check-prefix=DISASM
+// RUN: llvm-objdump --triple=armv7a-linux-gnueabihf -d --no-show-raw-insn %tout | FileCheck %s --check-prefix=DISASM
 // RUN: llvm-objdump -s %tout | FileCheck %s --check-prefix=GOTPLT
 // RUN: llvm-readobj -r --dynamic-table %tout | FileCheck %s
 
diff --git a/lld/test/ELF/arm-gnu-ifunc.s b/lld/test/ELF/arm-gnu-ifunc.s
index c790c6d86bd52..916ea2ccfc7e5 100644
--- a/lld/test/ELF/arm-gnu-ifunc.s
+++ b/lld/test/ELF/arm-gnu-ifunc.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -triple armv7a-none-linux-gnueabi -d --no-show-raw-insn %t | FileCheck %s --check-prefix=DISASM
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t | FileCheck %s --check-prefix=DISASM
 // RUN: llvm-readobj -r --symbols --sections %t | FileCheck %s
  .syntax unified
  .text
diff --git a/lld/test/ELF/arm-got-relative.s b/lld/test/ELF/arm-got-relative.s
index cef7aee4fc099..32a99491d8869 100644
--- a/lld/test/ELF/arm-got-relative.s
+++ b/lld/test/ELF/arm-got-relative.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc -position-independent -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -shared -o %t
 // RUN: llvm-readobj -S --symbols --dyn-relocations %t | FileCheck %s
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t | FileCheck -check-prefix=CODE %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t | FileCheck --check-prefix=CODE %s
  .syntax unified
  .text
  .globl _start
diff --git a/lld/test/ELF/arm-gotoff.s b/lld/test/ELF/arm-gotoff.s
index cc53351bc85a1..dd64d93b256d1 100644
--- a/lld/test/ELF/arm-gotoff.s
+++ b/lld/test/ELF/arm-gotoff.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -o %t
 // RUN: llvm-readobj -S -r --symbols %t | FileCheck %s
-// RUN: llvm-objdump -triple=armv7a-linux-gnueabi -d %t | FileCheck --check-prefix=DISASM %s
+// RUN: llvm-objdump --triple=armv7a-linux-gnueabi -d %t | FileCheck --check-prefix=DISASM %s
 
 // Test the R_ARM_GOTOFF32 relocation
 
diff --git a/lld/test/ELF/arm-icf-exidx.s b/lld/test/ELF/arm-icf-exidx.s
index 459faf5d647fd..ba659b630986c 100644
--- a/lld/test/ELF/arm-icf-exidx.s
+++ b/lld/test/ELF/arm-icf-exidx.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2 --icf=all
-// RUN: llvm-objdump -s -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -s -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 
  .syntax unified
  .section        .text.f,"axG",%progbits,f,comdat
diff --git a/lld/test/ELF/arm-long-thunk-converge.s b/lld/test/ELF/arm-long-thunk-converge.s
index 679258e316705..f88a16c3d6f5c 100644
--- a/lld/test/ELF/arm-long-thunk-converge.s
+++ b/lld/test/ELF/arm-long-thunk-converge.s
@@ -1,8 +1,8 @@
 // REQUIRES: arm
 // RUN: llvm-mc -triple armv7-unknown-gnu -arm-add-build-attributes -filetype=obj -o %t %s
 // RUN: ld.lld %t %S/Inputs/arm-long-thunk-converge.lds -o %t2
-// RUN: llvm-objdump -d -start-address=0x00000000 -stop-address=0x00000010 -triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d -start-address=0x02000000 -stop-address=0x02000010 -triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d --start-address=0x00000000 --stop-address=0x00000010 --triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d --start-address=0x02000000 --stop-address=0x02000010 --triple=armv7a-linux-gnueabihf %t2 | FileCheck --check-prefix=CHECK2 %s
 // RUN: rm -f %t2
 
 // CHECK1: <__ARMv7ABSLongThunk_bar>:
diff --git a/lld/test/ELF/arm-mov-relocs.s b/lld/test/ELF/arm-mov-relocs.s
index 39fdfb3885a54..50a36a793d822 100644
--- a/lld/test/ELF/arm-mov-relocs.s
+++ b/lld/test/ELF/arm-mov-relocs.s
@@ -1,10 +1,10 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-unknown-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -d %t2 -triple=armv7a-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
+// RUN: llvm-objdump -d %t2 --triple=armv7a-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
 // RUN: llvm-mc -filetype=obj -triple=thumbv7a-unknown-linux-gnueabi %s -o %t3
 // RUN: ld.lld %t3 -o %t4
-// RUN: llvm-objdump -d %t4 -triple=thumbv7a-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
+// RUN: llvm-objdump -d %t4 --triple=thumbv7a-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
 
 /// Test the following relocation pairs:
 ///  * R_ARM_MOVW_ABS_NC and R_ARM_MOVT_ABS
diff --git a/lld/test/ELF/arm-plt-reloc.s b/lld/test/ELF/arm-plt-reloc.s
index 1bc7383478ef1..7cb597ffea785 100644
--- a/lld/test/ELF/arm-plt-reloc.s
+++ b/lld/test/ELF/arm-plt-reloc.s
@@ -2,9 +2,9 @@
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %p/Inputs/arm-plt-reloc.s -o %t1
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t2
 // RUN: ld.lld %t1 %t2 -o %t
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t | FileCheck %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t | FileCheck %s
 // RUN: ld.lld -shared %t1 %t2 -o %t3
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t3 | FileCheck -check-prefix=DSO %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t3 | FileCheck --check-prefix=DSO %s
 // RUN: llvm-readobj -S -r %t3 | FileCheck -check-prefix=DSOREL %s
 //
 // Test PLT entry generation
@@ -114,7 +114,7 @@ _start:
 // RUN:       .got.plt 0x1100000 : { *(.got.plt) } \
 // RUN:       }" > %t.script
 // RUN: ld.lld --hash-style=sysv --script %t.script -shared %t1 %t2 -o %t4
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t4 | FileCheck --check-prefix=CHECKHIGH %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t4 | FileCheck --check-prefix=CHECKHIGH %s
 // RUN: llvm-readobj -S -r %t4 | FileCheck --check-prefix=DSORELHIGH %s
 
 // CHECKHIGH: Disassembly of section .text:
@@ -182,7 +182,7 @@ _start:
 // RUN:       .got.plt 0x11111100 : { *(.got.plt) } \
 // RUN:       }" > %t2.script
 // RUN: ld.lld --hash-style=sysv --script %t2.script -shared %t1 %t2 -o %t5
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t5 | FileCheck --check-prefix=CHECKLONG %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t5 | FileCheck --check-prefix=CHECKLONG %s
 // RUN: llvm-readobj -S -r %t5 | FileCheck --check-prefix=DSORELLONG %s
 
 // CHECKLONG: Disassembly of section .text:
@@ -251,7 +251,7 @@ _start:
 // RUN:       .got.plt 0x8002020 : { *(.got.plt) } \
 // RUN:       }" > %t3.script
 // RUN: ld.lld --hash-style=sysv --script %t3.script -shared %t1 %t2 -o %t6
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t6 | FileCheck --check-prefix=CHECKMIX %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t6 | FileCheck --check-prefix=CHECKMIX %s
 // RUN: llvm-readobj -S -r %t6 | FileCheck --check-prefix=DSORELMIX %s
 
 // CHECKMIX: Disassembly of section .text:
diff --git a/lld/test/ELF/arm-sbrel32.s b/lld/test/ELF/arm-sbrel32.s
index c598e0f68349a..0bb2c1eb033eb 100644
--- a/lld/test/ELF/arm-sbrel32.s
+++ b/lld/test/ELF/arm-sbrel32.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t | FileCheck %s
 
 // Test the R_ARM_SBREL32 relocation which calculates the offset of the Symbol
 // from the static base. We define the static base to be the address of the
diff --git a/lld/test/ELF/arm-target2.s b/lld/test/ELF/arm-target2.s
index 15e6c045a9924..1ac7b9666342f 100644
--- a/lld/test/ELF/arm-target2.s
+++ b/lld/test/ELF/arm-target2.s
@@ -1,13 +1,13 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t | FileCheck %s
 // RUN: ld.lld %t.o --target2=got-rel -o %t2
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
 // RUN: ld.lld %t.o --target2=abs -o %t3
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-ABS %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=CHECK-ABS %s
 // RUN: ld.lld %t.o --target2=rel -o %t4
-// RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t4 | FileCheck -check-prefix=CHECK-REL %s
+// RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t4 | FileCheck --check-prefix=CHECK-REL %s
 
 // The R_ARM_TARGET2 is present in .ARM.extab sections. It can be handled as
 // either R_ARM_ABS32, R_ARM_REL32 or R_ARM_GOT_PREL. For ARM linux the default
diff --git a/lld/test/ELF/arm-thumb-blx.s b/lld/test/ELF/arm-thumb-blx.s
index 281d1615b240c..8c9673b4ca520 100644
--- a/lld/test/ELF/arm-thumb-blx.s
+++ b/lld/test/ELF/arm-thumb-blx.s
@@ -8,7 +8,7 @@
 // RUN:          .R_ARM_CALL24_callee3 : { *(.R_ARM_CALL24_callee_high) } \
 // RUN:          .R_ARM_CALL24_callee4 : { *(.R_ARM_CALL24_callee_thumb_high) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %ttarget -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
 // Test BLX instruction is chosen for Thumb BL/BLX instruction and ARM callee
 // 2 byte nops are used to test the pc-rounding behaviour. As a BLX from a
 // 2 byte aligned destination is defined as Align(PC,4) + immediate:00
diff --git a/lld/test/ELF/arm-thumb-branch-rangethunk.s b/lld/test/ELF/arm-thumb-branch-rangethunk.s
index 976a69abb6db4..01e4d6119d952 100644
--- a/lld/test/ELF/arm-thumb-branch-rangethunk.s
+++ b/lld/test/ELF/arm-thumb-branch-rangethunk.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %S/Inputs/far-arm-thumb-abs.s -o %tfar
 // RUN: ld.lld  %t %tfar -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2
  .syntax unified
  .thumb
  .section .text, "ax",%progbits
diff --git a/lld/test/ELF/arm-thumb-branch.s b/lld/test/ELF/arm-thumb-branch.s
index 932fdacb07abd..e0396b30db5f8 100644
--- a/lld/test/ELF/arm-thumb-branch.s
+++ b/lld/test/ELF/arm-thumb-branch.s
@@ -7,7 +7,7 @@
 // RUN:          .caller : { *(.text) } \
 // RUN:          .callee2 : { *(.callee_high) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %tfar -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck  %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck  %s
 
  .syntax unified
  .thumb
diff --git a/lld/test/ELF/arm-thumb-condbranch-thunk.s b/lld/test/ELF/arm-thumb-condbranch-thunk.s
index 5f53096d0a07d..3a20f4e6af255 100644
--- a/lld/test/ELF/arm-thumb-condbranch-thunk.s
+++ b/lld/test/ELF/arm-thumb-condbranch-thunk.s
@@ -3,13 +3,13 @@
 // RUN: ld.lld %t.o -o %t
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x80000 --stop-address=0x80010 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x100000 --stop-address=0x100008 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x180000 --stop-address=0x18000a -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK3 %s
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x500004 --stop-address=0x500008 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK4 %s
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x580000 --stop-address=0x580006 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK5 %s
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x1000004 --stop-address=0x100000c -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK6 %s
-// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x1100000 --stop-address=0x1100006 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK7 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x80000 --stop-address=0x80010 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x100000 --stop-address=0x100008 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x180000 --stop-address=0x18000a --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x500004 --stop-address=0x500008 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x580000 --stop-address=0x580006 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK5 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x1000004 --stop-address=0x100000c --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK6 %s
+// RUN: llvm-objdump -d %t --print-imm-hex --start-address=0x1100000 --stop-address=0x1100006 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK7 %s
 // Test Range extension Thunks for the Thumb conditional branch instruction.
 // This instruction only has a range of 1Mb whereas all the other Thumb wide
 // Branch instructions have 16Mb range. We still place our pre-created Thunk
diff --git a/lld/test/ELF/arm-thumb-interwork-ifunc.s b/lld/test/ELF/arm-thumb-interwork-ifunc.s
index a0e4239ff3f39..319737a08aad5 100644
--- a/lld/test/ELF/arm-thumb-interwork-ifunc.s
+++ b/lld/test/ELF/arm-thumb-interwork-ifunc.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc --triple=armv7a-linux-gnueabihf -arm-add-build-attributes -filetype=obj -o %t.o %s
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -triple armv7a-none-linux-gnueabi -d --no-show-raw-insn %t
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d --no-show-raw-insn %t
 
 /// Non-preemptible ifuncs are called via a PLT entry which is always Arm
 /// state, expect the ARM callers to go direct to the PLT entry, Thumb
diff --git a/lld/test/ELF/arm-thumb-interwork-notfunc.s b/lld/test/ELF/arm-thumb-interwork-notfunc.s
index cbf6456b10b3d..40ef24ff7fcfb 100644
--- a/lld/test/ELF/arm-thumb-interwork-notfunc.s
+++ b/lld/test/ELF/arm-thumb-interwork-notfunc.s
@@ -1,7 +1,6 @@
 // REQUIRES: arm
 // RUN: llvm-mc -g --triple=armv7a-linux-gnueabihf -arm-add-build-attributes -filetype=obj -o %t.o %s
-// RUN: ld.lld %t.o --no-threads -o %t 2>&1
-// RUN: ld.lld %t.o --no-threads -o %t 2>&1 | FileCheck %s --check-prefix=WARN
+// RUN: ld.lld %t.o -o %t 2>&1 | FileCheck %s --check-prefix=WARN
 // RUN: llvm-objdump --no-show-raw-insn -d %t | FileCheck %s
 
 .syntax unified
diff --git a/lld/test/ELF/arm-thumb-interwork-shared.s b/lld/test/ELF/arm-thumb-interwork-shared.s
index 30370ddc1b222..dee44afc11535 100644
--- a/lld/test/ELF/arm-thumb-interwork-shared.s
+++ b/lld/test/ELF/arm-thumb-interwork-shared.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t --shared -o %t.so
-// RUN: llvm-objdump -d --no-show-raw-insn -triple=thumbv7a-none-linux-gnueabi %t.so | FileCheck %s
+// RUN: llvm-objdump -d --no-show-raw-insn --triple=thumbv7a-none-linux-gnueabi %t.so | FileCheck %s
  .syntax unified
  .global sym1
  .global elsewhere
diff --git a/lld/test/ELF/arm-thumb-interwork-thunk-v5.s b/lld/test/ELF/arm-thumb-interwork-thunk-v5.s
index bed6b8cbc9dc0..1e397f7ef8971 100644
--- a/lld/test/ELF/arm-thumb-interwork-thunk-v5.s
+++ b/lld/test/ELF/arm-thumb-interwork-thunk-v5.s
@@ -1,9 +1,9 @@
 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv5-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -d %t2 -triple=armv5-none-linux-gnueabi | FileCheck %s
+// RUN: llvm-objdump -d %t2 --triple=armv5-none-linux-gnueabi | FileCheck %s
 // RUN: ld.lld %t -o %t3 --shared
-// RUN: llvm-objdump -d %t3 -triple=armv5-none-linux-gnueabi | FileCheck --check-prefix=CHECK-PI %s
+// RUN: llvm-objdump -d %t3 --triple=armv5-none-linux-gnueabi | FileCheck --check-prefix=CHECK-PI %s
 
 // Test ARM Thumb Interworking on older Arm architectures using Thunks that do
 // not use MOVT/MOVW instructions.
diff --git a/lld/test/ELF/arm-thumb-interwork-thunk.s b/lld/test/ELF/arm-thumb-interwork-thunk.s
index b22ac49140e71..fe573200af14f 100644
--- a/lld/test/ELF/arm-thumb-interwork-thunk.s
+++ b/lld/test/ELF/arm-thumb-interwork-thunk.s
@@ -11,14 +11,14 @@
 // RUN:       .R_ARM_THM_JUMP_callee_2 : { *(.R_ARM_THM_JUMP_callee_high) } \
 // RUN:       .got.plt 0x18b4 : {  }  } " > %t.script
 // RUN: ld.lld --script %t.script %t -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-THUMB -check-prefix=CHECK-ABS-THUMB %s
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck -check-prefix=CHECK-ARM -check-prefix=CHECK-ABS-ARM %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-THUMB --check-prefix=CHECK-ABS-THUMB %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK-ABS-ARM %s
 // RUN: ld.lld --script %t.script %t -pie -o %t3
 // RUN: ld.lld --script %t.script %t --shared -o %t4
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-THUMB -check-prefix=CHECK-PI-THUMB %s
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t3 | FileCheck -check-prefix=CHECK-ARM -check-prefix=CHECK-PI-ARM %s
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t4 | FileCheck -check-prefix=CHECK-THUMB -check-prefix=CHECK-PI-PLT-THUMB %s
-// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t4 | FileCheck -check-prefix=CHECK-ARM -check-prefix=CHECK-PI-PLT-ARM %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=CHECK-THUMB --check-prefix=CHECK-PI-THUMB %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK-PI-ARM %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t4 | FileCheck --check-prefix=CHECK-THUMB --check-prefix=CHECK-PI-PLT-THUMB %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t4 | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK-PI-PLT-ARM %s
 // RUN: llvm-readobj -S -r %t4 | FileCheck -check-prefix=CHECK-DSO-REL %s
 
 // Test ARM Thumb Interworking
diff --git a/lld/test/ELF/arm-thumb-mix-range-thunk-os.s b/lld/test/ELF/arm-thumb-mix-range-thunk-os.s
index 16eba5db13a7a..33b698d6d886b 100644
--- a/lld/test/ELF/arm-thumb-mix-range-thunk-os.s
+++ b/lld/test/ELF/arm-thumb-mix-range-thunk-os.s
@@ -3,17 +3,17 @@
 // RUN: ld.lld %t -o %t2
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t2 -start-address=1048576 -stop-address=1048604 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t2 -start-address=2097152 -stop-address=2097162 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t2 -start-address=16777220 -stop-address=16777232 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK3 %s
-// RUN: llvm-objdump -d %t2 -start-address=16777232 -stop-address=16777242 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK4 %s
-// RUN: llvm-objdump -d %t2 -start-address=32505860 -stop-address=32505870 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK5 %s
-// RUN: llvm-objdump -d %t2 -start-address=35651584 -stop-address=35651590 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK6 %s
-// RUN: llvm-objdump -d %t2 -start-address=36700160 -stop-address=36700168 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK7 %s
-// RUN: llvm-objdump -d %t2 -start-address=48234500 -stop-address=48234512 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK8 %s
-// RUN: llvm-objdump -d %t2 -start-address=53477380 -stop-address=53477392 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK9 %s
-// RUN: llvm-objdump -d %t2 -start-address=68157440 -stop-address=68157452 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK10 %s
-// RUN: llvm-objdump -d %t2 -start-address=69206016 -stop-address=69206024 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK11 %s
+// RUN: llvm-objdump -d %t2 --start-address=1048576 --stop-address=1048604 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t2 --start-address=2097152 --stop-address=2097162 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t2 --start-address=16777220 --stop-address=16777232 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t2 --start-address=16777232 --stop-address=16777242 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump -d %t2 --start-address=32505860 --stop-address=32505870 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK5 %s
+// RUN: llvm-objdump -d %t2 --start-address=35651584 --stop-address=35651590 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK6 %s
+// RUN: llvm-objdump -d %t2 --start-address=36700160 --stop-address=36700168 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK7 %s
+// RUN: llvm-objdump -d %t2 --start-address=48234500 --stop-address=48234512 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK8 %s
+// RUN: llvm-objdump -d %t2 --start-address=53477380 --stop-address=53477392 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK9 %s
+// RUN: llvm-objdump -d %t2 --start-address=68157440 --stop-address=68157452 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK10 %s
+// RUN: llvm-objdump -d %t2 --start-address=69206016 --stop-address=69206024 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK11 %s
 
 // Test the Range extension Thunks for ARM and Thumb when all the code is in a
 // single OutputSection. The ARM branches and branch and link instructions
diff --git a/lld/test/ELF/arm-thumb-narrow-branch-check.s b/lld/test/ELF/arm-thumb-narrow-branch-check.s
index 60ad9f1646bac..6dc8c0b2978c1 100644
--- a/lld/test/ELF/arm-thumb-narrow-branch-check.s
+++ b/lld/test/ELF/arm-thumb-narrow-branch-check.s
@@ -7,7 +7,7 @@
 // RUN:          .R_ARM_PC11_2 : { *(.R_ARM_PC11_2) } \
 // RUN:          .text : { *(.text) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %S/Inputs/arm-thumb-narrow-branch.o -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
 
 // Test the R_ARM_PC11 relocation which is used with the narrow encoding of B.N
 // the source of these relocations is a binary file arm-thumb-narrow-branch.o
diff --git a/lld/test/ELF/arm-thumb-no-undefined-thunk.s b/lld/test/ELF/arm-thumb-no-undefined-thunk.s
index b47c291bed7d7..2fbca671e14e3 100644
--- a/lld/test/ELF/arm-thumb-no-undefined-thunk.s
+++ b/lld/test/ELF/arm-thumb-no-undefined-thunk.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -triple=thumbv7a-none-linux-gnueabi -d %t2 | FileCheck %s
+// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %t2 | FileCheck %s
 
 // Check that no thunks are created for an undefined weak symbol
  .syntax unified
diff --git a/lld/test/ELF/arm-thumb-pc8-weak.s b/lld/test/ELF/arm-thumb-pc8-weak.s
index aeb9036ff0c85..e0fe2442347ea 100644
--- a/lld/test/ELF/arm-thumb-pc8-weak.s
+++ b/lld/test/ELF/arm-thumb-pc8-weak.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc --arm-add-build-attributes -filetype=obj -triple=thumbv6a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump --no-show-raw-insn -triple=thumbv6a-none-linux-gnueabi -d %t2
+// RUN: llvm-objdump --no-show-raw-insn --triple=thumbv6a-none-linux-gnueabi -d %t2
 
 /// Check that the ARM ABI rules for undefined weak symbols are applied.
 /// Relative relocations are resolved to the place. Although we can't encode
diff --git a/lld/test/ELF/arm-thumb-plt-range-thunk-os.s b/lld/test/ELF/arm-thumb-plt-range-thunk-os.s
index e6227fc9f4620..ba151c9b9db0b 100644
--- a/lld/test/ELF/arm-thumb-plt-range-thunk-os.s
+++ b/lld/test/ELF/arm-thumb-plt-range-thunk-os.s
@@ -3,10 +3,10 @@
 // RUN: ld.lld %t --shared --icf=all -o %t.so
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t.so -start-address=0x2000000 -stop-address=0x2000018 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t.so -start-address=0x2800004 -stop-address=0x2800034 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t.so -start-address=0x4000000 -stop-address=0x4000010 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK3 %s
-// RUN: llvm-objdump -d %t.so -start-address=0x4000010 -stop-address=0x4000100 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK4 %s
+// RUN: llvm-objdump -d %t.so --start-address=0x2000000 --stop-address=0x2000018 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t.so --start-address=0x2800004 --stop-address=0x2800034 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t.so --start-address=0x4000000 --stop-address=0x4000010 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t.so --start-address=0x4000010 --stop-address=0x4000100 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK4 %s
  .syntax unified
  .thumb
 
diff --git a/lld/test/ELF/arm-thumb-plt-reloc.s b/lld/test/ELF/arm-thumb-plt-reloc.s
index d12477609b673..f252852ec1477 100644
--- a/lld/test/ELF/arm-thumb-plt-reloc.s
+++ b/lld/test/ELF/arm-thumb-plt-reloc.s
@@ -2,9 +2,9 @@
 // RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %p/Inputs/arm-plt-reloc.s -o %t1
 // RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t2
 // RUN: ld.lld %t1 %t2 -o %t
-// RUN: llvm-objdump -triple=thumbv7a-none-linux-gnueabi -d %t | FileCheck %s
+// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %t | FileCheck %s
 // RUN: ld.lld -shared %t1 %t2 -o %t.so
-// RUN: llvm-objdump -triple=thumbv7a-none-linux-gnueabi -d %t.so | FileCheck -check-prefix=DSO %s
+// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %t.so | FileCheck --check-prefix=DSO %s
 // RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s
 //
 // Test PLT entry generation
diff --git a/lld/test/ELF/arm-thumb-range-thunk-os.s b/lld/test/ELF/arm-thumb-range-thunk-os.s
index b09411ce1d8b7..ba89159aeac46 100644
--- a/lld/test/ELF/arm-thumb-range-thunk-os.s
+++ b/lld/test/ELF/arm-thumb-range-thunk-os.s
@@ -3,16 +3,16 @@
 // RUN: ld.lld %t -o %t2
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t2 -start-address=1048576 -stop-address=1048588 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t2 -start-address=2097152 -stop-address=2097154 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t2 -start-address=3145728 -stop-address=3145730 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK3 %s
-// RUN: llvm-objdump -d %t2 -start-address=4194304 -stop-address=4194310 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK4 %s
-// RUN: llvm-objdump -d %t2 -start-address=16777216 -stop-address=16777270 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK5 %s
-// RUN: llvm-objdump -d %t2 -start-address=17825792 -stop-address=17825808 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK6 %s
-// RUN: llvm-objdump -d %t2 -start-address=20971524 -stop-address=20971532 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK7 %s
-// RUN: llvm-objdump -d %t2 -start-address=31457280 -stop-address=31457286 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK8 %s
-// RUN: llvm-objdump -d %t2 -start-address=35651584 -stop-address=35651594 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK9 %s
-// RUN: llvm-objdump -d %t2 -start-address=36700160 -stop-address=36700170 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK10 %s
+// RUN: llvm-objdump -d %t2 --start-address=1048576 --stop-address=1048588 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t2 --start-address=2097152 --stop-address=2097154 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t2 --start-address=3145728 --stop-address=3145730 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t2 --start-address=4194304 --stop-address=4194310 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump -d %t2 --start-address=16777216 --stop-address=16777270 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK5 %s
+// RUN: llvm-objdump -d %t2 --start-address=17825792 --stop-address=17825808 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK6 %s
+// RUN: llvm-objdump -d %t2 --start-address=20971524 --stop-address=20971532 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK7 %s
+// RUN: llvm-objdump -d %t2 --start-address=31457280 --stop-address=31457286 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK8 %s
+// RUN: llvm-objdump -d %t2 --start-address=35651584 --stop-address=35651594 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK9 %s
+// RUN: llvm-objdump -d %t2 --start-address=36700160 --stop-address=36700170 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK10 %s
 
 // Test the Range extension Thunks for Thumb when all the code is in a single
 // OutputSection. The Thumb unconditional branch b.w and branch and link bl
diff --git a/lld/test/ELF/arm-thumb-thunk-empty-pass.s b/lld/test/ELF/arm-thumb-thunk-empty-pass.s
index d6eb111f8bd26..271d88dcf9d76 100644
--- a/lld/test/ELF/arm-thumb-thunk-empty-pass.s
+++ b/lld/test/ELF/arm-thumb-thunk-empty-pass.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -d %t -triple=thumbv7a | FileCheck %s
+// RUN: llvm-objdump -d %t --triple=thumbv7a | FileCheck %s
  .syntax unified
  .global _start, foo
  .type _start, %function
diff --git a/lld/test/ELF/arm-thumb-thunk-v6m.s b/lld/test/ELF/arm-thumb-thunk-v6m.s
index 65367a53a8c6c..b97f9f767adf6 100644
--- a/lld/test/ELF/arm-thumb-thunk-v6m.s
+++ b/lld/test/ELF/arm-thumb-thunk-v6m.s
@@ -6,9 +6,9 @@
 // RUN:       .text_high 0x2000000 : { *(.text_high) *(.text_high2) } \
 // RUN:       } " > %t.script
 // RUN: ld.lld --script %t.script %t -o %t2
-// RUN: llvm-objdump -d %t2 -triple=armv6m-none-eabi | FileCheck %s
+// RUN: llvm-objdump -d %t2 --triple=armv6m-none-eabi | FileCheck %s
 // RUN: ld.lld --script %t.script %t -o %t3 --pie
-// RUN: llvm-objdump -d %t3 -triple=armv6m-none-eabi | FileCheck -check-prefix=CHECK-PI %s
+// RUN: llvm-objdump -d %t3 --triple=armv6m-none-eabi | FileCheck --check-prefix=CHECK-PI %s
 
 // Range extension thunks for Arm Architecture v6m. Only Thumb instructions
 // are permitted which limits the access to instructions that can access the
diff --git a/lld/test/ELF/arm-thumb-undefined-weak-narrow.test b/lld/test/ELF/arm-thumb-undefined-weak-narrow.test
index f3997c1ef6fb2..1de346d8b7a0b 100644
--- a/lld/test/ELF/arm-thumb-undefined-weak-narrow.test
+++ b/lld/test/ELF/arm-thumb-undefined-weak-narrow.test
@@ -1,7 +1,7 @@
 # REQUIRES: arm
 # RUN: yaml2obj %s -o %t.o
 # RUN: ld.lld %t.o -o %t
-# RUN: llvm-objdump -triple=thumbv7a-linux-gnueabi -d %t | FileCheck %s
+# RUN: llvm-objdump --triple=thumbv7a-linux-gnueabi -d %t | FileCheck %s
 
 # CHECK: Disassembly of section .text:
 # CHECK-EMPTY:
diff --git a/lld/test/ELF/arm-thumb-undefined-weak.s b/lld/test/ELF/arm-thumb-undefined-weak.s
index 3bdc3d7730225..d56480575fdb8 100644
--- a/lld/test/ELF/arm-thumb-undefined-weak.s
+++ b/lld/test/ELF/arm-thumb-undefined-weak.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc --arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -triple=thumbv7a-none-linux-gnueabi -d %t2 | FileCheck %s
+// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %t2 | FileCheck %s
 
 // Check that the ARM ABI rules for undefined weak symbols are applied.
 // Branch instructions are resolved to the next instruction. Relative
diff --git a/lld/test/ELF/arm-thunk-edgecase.s b/lld/test/ELF/arm-thunk-edgecase.s
index d66f3348a9fdc..1f9b588f55942 100644
--- a/lld/test/ELF/arm-thunk-edgecase.s
+++ b/lld/test/ELF/arm-thunk-edgecase.s
@@ -10,8 +10,8 @@
 // RUN:       }" > %tthumb_to_arm.script
 // RUN: ld.lld -shared -Bsymbolic -script %tarm_to_thumb.script %t.o -o %tarm_to_thumb.so
 // RUN: ld.lld -shared -Bsymbolic -script %tthumb_to_arm.script %t.o -o %tthumb_to_arm.so
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi -d %tarm_to_thumb.so | FileCheck -check-prefix=ARM-TO-THUMB %s
-// RUN: llvm-objdump -triple=thumbv7a-none-linux-gnueabi -d %tthumb_to_arm.so | FileCheck -check-prefix=THUMB-TO-ARM %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi -d %tarm_to_thumb.so | FileCheck --check-prefix=ARM-TO-THUMB %s
+// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %tthumb_to_arm.so | FileCheck --check-prefix=THUMB-TO-ARM %s
 
 .syntax unified
 
diff --git a/lld/test/ELF/arm-thunk-largesection.s b/lld/test/ELF/arm-thunk-largesection.s
index c8f10e30283e9..1fc37cf3b4c5a 100644
--- a/lld/test/ELF/arm-thunk-largesection.s
+++ b/lld/test/ELF/arm-thunk-largesection.s
@@ -1,11 +1,11 @@
 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi --start-address=0x12000 --stop-address=0x12006 %t2 | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi --start-address=0x13004 --stop-address=0x13008 %t2 | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi --start-address=0x1012ff8 --stop-address=0x1012ffc %t2 | FileCheck -check-prefix=CHECK3 %s
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi --start-address=0x2012ff8 --stop-address=0x2012ffc %t2 | FileCheck -check-prefix=CHECK4 %s
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi --start-address=0x3012fec --stop-address=0x3012ff6 %t2 | FileCheck -check-prefix=CHECK5 %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi --start-address=0x12000 --stop-address=0x12006 %t2 | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi --start-address=0x13004 --stop-address=0x13008 %t2 | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi --start-address=0x1012ff8 --stop-address=0x1012ffc %t2 | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi --start-address=0x2012ff8 --stop-address=0x2012ffc %t2 | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi --start-address=0x3012fec --stop-address=0x3012ff6 %t2 | FileCheck --check-prefix=CHECK5 %s
  .syntax unified
  .balign 0x1000
  .thumb
diff --git a/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s b/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
index 7e053dfda6bbc..1da6da5f33bab 100644
--- a/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
+++ b/lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
@@ -5,8 +5,8 @@
 // RUN:       .text_low : { *(.text_low) *(.text_low2) . = . + 0x2000000 ; *(.text_high) *(.text_high2) } \
 // RUN:       } " > %t.script
 // RUN: ld.lld --script %t.script %t -o %t2
-// RUN: llvm-objdump -d %t2 -start-address=148 -stop-address=188 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t2 -start-address=33554620 -stop-address=33554654 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t2 --start-address=148 --stop-address=188 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t2 --start-address=33554620 --stop-address=33554654 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
 // Test that range extension thunks can handle location expressions within
 // a Section Description
  .syntax unified
diff --git a/lld/test/ELF/arm-thunk-linkerscript-large.s b/lld/test/ELF/arm-thunk-linkerscript-large.s
index 325cee02ebffe..580719f6e11de 100644
--- a/lld/test/ELF/arm-thunk-linkerscript-large.s
+++ b/lld/test/ELF/arm-thunk-linkerscript-large.s
@@ -8,12 +8,12 @@
 // RUN: ld.lld --script %t.script %t -o %t2
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t2 -start-address=1048576 -stop-address=1048594 -triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t2 -start-address=2097152 -stop-address=2097160 -triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t2 -start-address=11534340 -stop-address=11534350 -triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
-// RUN: llvm-objdump -d %t2 -start-address=34603008 -stop-address=34603034 -triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK4 %s
-// RUN: llvm-objdump -d %t2 -start-address=35651584 -stop-address=35651598 -triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK5 %s
-// RUN: llvm-objdump -d %t2 -start-address=68157440 -stop-address=68157472 -triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK6 %s
+// RUN: llvm-objdump -d %t2 --start-address=1048576 --stop-address=1048594 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t2 --start-address=2097152 --stop-address=2097160 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t2 --start-address=11534340 --stop-address=11534350 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t2 --start-address=34603008 --stop-address=34603034 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK4 %s
+// RUN: llvm-objdump -d %t2 --start-address=35651584 --stop-address=35651598 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK5 %s
+// RUN: llvm-objdump -d %t2 --start-address=68157440 --stop-address=68157472 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK6 %s
 
 // Test the range extensions in a linker script where there are several
 // OutputSections requiring range extension Thunks. We should be able to reuse
diff --git a/lld/test/ELF/arm-thunk-linkerscript-orphan.s b/lld/test/ELF/arm-thunk-linkerscript-orphan.s
index f1eb75a4e5493..103e2c66c98f5 100644
--- a/lld/test/ELF/arm-thunk-linkerscript-orphan.s
+++ b/lld/test/ELF/arm-thunk-linkerscript-orphan.s
@@ -6,7 +6,7 @@
 // RUN:       .data : { *(.data) } \
 // RUN:       }" > %t.script
 // RUN: ld.lld --script %t.script %t -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
  .syntax unified
  .section .text_low, "ax", %progbits
  .thumb
diff --git a/lld/test/ELF/arm-thunk-linkerscript-sort.s b/lld/test/ELF/arm-thunk-linkerscript-sort.s
index 555bcb3cf9afc..511ec52d3e4bd 100644
--- a/lld/test/ELF/arm-thunk-linkerscript-sort.s
+++ b/lld/test/ELF/arm-thunk-linkerscript-sort.s
@@ -4,8 +4,8 @@
 // RUN:       .text 0x100000 : { *(SORT_BY_NAME(.text.*)) } \
 // RUN:       }" > %t.script
 // RUN: ld.lld --script %t.script %t -o %t2
-// RUN: llvm-objdump -d %t2 -start-address=1048576 -stop-address=1048584 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t2 -start-address=16777220 -stop-address=16777230 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t2 --start-address=1048576 --stop-address=1048584 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t2 --start-address=16777220 --stop-address=16777230 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
 
  .syntax unified
 
diff --git a/lld/test/ELF/arm-thunk-linkerscript.s b/lld/test/ELF/arm-thunk-linkerscript.s
index 6a1fe2fd5aa9e..5de80fc0d5c40 100644
--- a/lld/test/ELF/arm-thunk-linkerscript.s
+++ b/lld/test/ELF/arm-thunk-linkerscript.s
@@ -6,7 +6,7 @@
 // RUN:       .text_high 0x2000000 : { *(.text_high) *(.text_high2) } \
 // RUN:       } " > %t.script
 // RUN: ld.lld --script %t.script %t -o %t2
-// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
+// RUN: llvm-objdump -d --triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
 // Simple test that we can support range extension thunks with linker scripts
  .syntax unified
  .section .text_low, "ax", %progbits
diff --git a/lld/test/ELF/arm-thunk-multipass-plt.s b/lld/test/ELF/arm-thunk-multipass-plt.s
index 97ff755b89d83..c39ff5021a44c 100644
--- a/lld/test/ELF/arm-thunk-multipass-plt.s
+++ b/lld/test/ELF/arm-thunk-multipass-plt.s
@@ -2,8 +2,8 @@
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv5-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2 --shared
 // RUN: llvm-objdump --start-address=7340044 --stop-address=7340048 --triple=armv5-none-linux-gnueabi -d %t2 | FileCheck %s
-// RUN: llvm-objdump --start-address=8388620 --stop-address=8388624 --triple=thumbv5-none-linux-gnueabi -d %t2 | FileCheck %s -check-prefix=CHECK-CALL
-// RUN: llvm-objdump --start-address=13631520 --stop-address=13631584 --triple=armv5-none-linux-gnueabi -d %t2 | FileCheck %s -check-prefix=CHECK-PLT
+// RUN: llvm-objdump --start-address=8388620 --stop-address=8388624 --triple=thumbv5-none-linux-gnueabi -d %t2 | FileCheck %s --check-prefix=CHECK-CALL
+// RUN: llvm-objdump --start-address=13631520 --stop-address=13631584 --triple=armv5-none-linux-gnueabi -d %t2 | FileCheck %s --check-prefix=CHECK-PLT
 // When we create a thunk to a PLT entry the relocation is redirected to the
 // Thunk, changing its expression to a non-PLT equivalent. If the thunk
 // becomes unusable we need to restore the relocation expression to the PLT
diff --git a/lld/test/ELF/arm-thunk-multipass.s b/lld/test/ELF/arm-thunk-multipass.s
index ff6b282bd8cb4..5e8d9a239942f 100644
--- a/lld/test/ELF/arm-thunk-multipass.s
+++ b/lld/test/ELF/arm-thunk-multipass.s
@@ -3,9 +3,9 @@
 // RUN: ld.lld %t -o %t2
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t2 -start-address=1048578 -stop-address=1048586 -triple=thumbv7a-linux-gnueabihf  | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t2 -start-address=16777224 -stop-address=16777254 -triple=thumbv7a-linux-gnueabihf  | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t2 -start-address=17825812 -stop-address=17825826 -triple=thumbv7a-linux-gnueabihf  | FileCheck -check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t2 --start-address=1048578 --stop-address=1048586 --triple=thumbv7a-linux-gnueabihf  | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t2 --start-address=16777224 --stop-address=16777254 --triple=thumbv7a-linux-gnueabihf  | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t2 --start-address=17825812 --stop-address=17825826 --triple=thumbv7a-linux-gnueabihf  | FileCheck --check-prefix=CHECK3 %s
 // In this test case a branch that is in range and does not need its range
 // extended can be pushed out of range by another Thunk, necessitating another
 // pass
diff --git a/lld/test/ELF/arm-thunk-nosuitable.s b/lld/test/ELF/arm-thunk-nosuitable.s
index f149fa9839e7d..aea8d7fc431c8 100644
--- a/lld/test/ELF/arm-thunk-nosuitable.s
+++ b/lld/test/ELF/arm-thunk-nosuitable.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc %s --arm-add-build-attributes --triple=armv7a-linux-gnueabihf --filetype=obj -o %t.o
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -triple=thumbv7a -d --start-address=0x2110b4 --stop-address=0x2110be %t | FileCheck %s
+// RUN: llvm-objdump --triple=thumbv7a -d --start-address=0x2110b4 --stop-address=0x2110be %t | FileCheck %s
 
         // Create a conditional branch too far away from a precreated thunk
         // section. This will need a thunk section created within range.
diff --git a/lld/test/ELF/arm-thunk-re-add.s b/lld/test/ELF/arm-thunk-re-add.s
index c65ee90a3e29d..0ba22b158b05b 100644
--- a/lld/test/ELF/arm-thunk-re-add.s
+++ b/lld/test/ELF/arm-thunk-re-add.s
@@ -3,9 +3,9 @@
 // RUN: ld.lld %t --shared -o %t.so
 // The output file is large, most of it zeroes. We dissassemble only the
 // parts we need to speed up the test and avoid a large output file
-// RUN: llvm-objdump -d %t.so -start-address=16777220 -stop-address=16777244 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
-// RUN: llvm-objdump -d %t.so -start-address=17825800 -stop-address=17825826 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
-// RUN: llvm-objdump -d %t.so -start-address=17825824 -stop-address=17825892 -triple=armv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK3 %s
+// RUN: llvm-objdump -d %t.so --start-address=16777220 --stop-address=16777244 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK1 %s
+// RUN: llvm-objdump -d %t.so --start-address=17825800 --stop-address=17825826 --triple=thumbv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK2 %s
+// RUN: llvm-objdump -d %t.so --start-address=17825824 --stop-address=17825892 --triple=armv7a-linux-gnueabihf | FileCheck --check-prefix=CHECK3 %s
 
 // A branch to a Thunk that we create on pass N, can drift out of range if
 // other Thunks are added in between. In this case we must create a new Thunk
diff --git a/lld/test/ELF/arm-tls-gd-nonpreemptible.s b/lld/test/ELF/arm-tls-gd-nonpreemptible.s
index bfb9f495ef680..f629eb6f113fe 100644
--- a/lld/test/ELF/arm-tls-gd-nonpreemptible.s
+++ b/lld/test/ELF/arm-tls-gd-nonpreemptible.s
@@ -4,7 +4,7 @@
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
 // RUN: llvm-objdump -s %t2 | FileCheck %s
 // RUN: ld.lld %t --shared -o %t3.so
-// RUN: llvm-objdump -s %t3.so | FileCheck -check-prefix=CHECK-SHARED %s
+// RUN: llvm-objdump -s %t3.so | FileCheck --check-prefix=CHECK-SHARED %s
 
 // For an executable, we write the module index 1 and the offset into the TLS
 // directly into the GOT. For a shared library we can only write the offset
diff --git a/lld/test/ELF/arm-tls-gd32.s b/lld/test/ELF/arm-tls-gd32.s
index f5ec0a3a456c1..07d92584ee34b 100644
--- a/lld/test/ELF/arm-tls-gd32.s
+++ b/lld/test/ELF/arm-tls-gd32.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
 // RUN: ld.lld %t.o -o %t.so -shared
 // RUN: llvm-readobj -S --dyn-relocations %t.so | FileCheck --check-prefix=SEC %s
-// RUN: llvm-objdump -d -triple=armv7a-linux-gnueabi %t.so | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-linux-gnueabi %t.so | FileCheck %s
 
 // Test the handling of the global-dynamic TLS model. Dynamic Loader finds
 // module index R_ARM_TLS_DTPMOD32 and the offset within the module
diff --git a/lld/test/ELF/arm-tls-ie32.s b/lld/test/ELF/arm-tls-ie32.s
index e87ca06ca6fec..2a9c8a4b2a31d 100644
--- a/lld/test/ELF/arm-tls-ie32.s
+++ b/lld/test/ELF/arm-tls-ie32.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
 // RUN: ld.lld %t.o -o %t.so -shared
 // RUN: llvm-readobj -S --dyn-relocations %t.so | FileCheck --check-prefix=SEC %s
-// RUN: llvm-objdump -d -triple=armv7a-linux-gnueabi %t.so | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-linux-gnueabi %t.so | FileCheck %s
 
 // Test the handling of the initial-exec TLS model. Relative location within
 // static TLS is a run-time constant computed by dynamic loader as a result
diff --git a/lld/test/ELF/arm-tls-ldm32.s b/lld/test/ELF/arm-tls-ldm32.s
index 980afd4a34971..62be2d49dba3c 100644
--- a/lld/test/ELF/arm-tls-ldm32.s
+++ b/lld/test/ELF/arm-tls-ldm32.s
@@ -2,9 +2,9 @@
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
 // RUN: ld.lld %t.o -o %t.so -shared
 // RUN: llvm-readobj -S --dyn-relocations %t.so | FileCheck --check-prefix=SEC %s
-// RUN: llvm-objdump -d -triple=armv7a-linux-gnueabi %t.so | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-linux-gnueabi %t.so | FileCheck %s
 // RUN: ld.lld %t.o -o %t
-// RUN: llvm-objdump -d -triple=armv7a-linux-gnueabi %t | FileCheck --check-prefix=CHECK-EXE %s
+// RUN: llvm-objdump -d --triple=armv7a-linux-gnueabi %t | FileCheck --check-prefix=CHECK-EXE %s
 
 // Test the handling of the local-dynamic TLS model. Dynamic loader finds
 // module index R_ARM_TLS_DTPMOD32. The offset in the next GOT slot is 0
diff --git a/lld/test/ELF/arm-tls-le32.s b/lld/test/ELF/arm-tls-le32.s
index f7553d3baf633..6c572e870bb2e 100644
--- a/lld/test/ELF/arm-tls-le32.s
+++ b/lld/test/ELF/arm-tls-le32.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
 // RUN: ld.lld %t.o -o %t
 // RUN: llvm-readobj -S --dyn-relocations %t | FileCheck --check-prefix=SEC %s
-// RUN: llvm-objdump -d -triple=armv7a-linux-gnueabi %t | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-linux-gnueabi %t | FileCheck %s
 
 // Test the handling of the local exec TLS model. TLS can be resolved
 // statically for an application. The code sequences assume a thread pointer
diff --git a/lld/test/ELF/arm-tls-norelax-ie-le.s b/lld/test/ELF/arm-tls-norelax-ie-le.s
index 7dfe4bcff787c..90c75afe09141 100644
--- a/lld/test/ELF/arm-tls-norelax-ie-le.s
+++ b/lld/test/ELF/arm-tls-norelax-ie-le.s
@@ -3,7 +3,7 @@
 // RUN: ld.lld %t1.o --shared -soname=t1.so -o %t1.so
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
 // RUN: ld.lld %t1.so %t.o -o %t
-// RUN: llvm-objdump -s -triple=armv7a-linux-gnueabi %t | FileCheck %s
+// RUN: llvm-objdump -s --triple=armv7a-linux-gnueabi %t | FileCheck %s
 
 // This tls Initial Exec sequence is with respect to a non-preemptible symbol
 // so a relaxation would normally be possible. This would result in an assertion
diff --git a/lld/test/ELF/arm-undefined-weak.s b/lld/test/ELF/arm-undefined-weak.s
index db3fa9a296af2..727b9a7b07db6 100644
--- a/lld/test/ELF/arm-undefined-weak.s
+++ b/lld/test/ELF/arm-undefined-weak.s
@@ -1,7 +1,7 @@
 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld --image-base=0x10000000 %t -o %t2
-// RUN: llvm-objdump -triple=armv7a-none-linux-gnueabi --no-show-raw-insn -d %t2 | FileCheck %s
+// RUN: llvm-objdump --triple=armv7a-none-linux-gnueabi --no-show-raw-insn -d %t2 | FileCheck %s
 
 // Check that the ARM ABI rules for undefined weak symbols are applied.
 // Branch instructions are resolved to the next instruction. Undefined
diff --git a/lld/test/ELF/basic-ppc.s b/lld/test/ELF/basic-ppc.s
index ff753c8cebadd..b67841e691a2c 100644
--- a/lld/test/ELF/basic-ppc.s
+++ b/lld/test/ELF/basic-ppc.s
@@ -9,7 +9,7 @@
  li      3,1
  sc
 
-// CHECK: Format: ELF32-ppc
+// CHECK:      Format: elf32-powerpc
 // CHECK-NEXT: Arch: powerpc
 // CHECK-NEXT: AddressSize: 32bit
 // CHECK-NEXT: LoadName:
diff --git a/lld/test/ELF/basic-ppc64.s b/lld/test/ELF/basic-ppc64.s
index 59a406bc83fa0..a768436f222ce 100644
--- a/lld/test/ELF/basic-ppc64.s
+++ b/lld/test/ELF/basic-ppc64.s
@@ -14,7 +14,7 @@
   li 3,55
   sc
 
-// CHECK:Format: ELF64-ppc64
+// CHECK:      Format: elf64-powerpc
 // LE-NEXT:    Arch: powerpc64le
 // BE-NEXT:    Arch: powerpc64{{$}}
 // CHECK-NEXT: AddressSize: 64bit
diff --git a/lld/test/ELF/bss-start-common.s b/lld/test/ELF/bss-start-common.s
index afb157f3521cb..7bbab83df033c 100644
--- a/lld/test/ELF/bss-start-common.s
+++ b/lld/test/ELF/bss-start-common.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: ld.lld %t -o %t2
-# RUN: llvm-objdump -t -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump -t --section-headers %t2 | FileCheck %s
 
 ## Test __bss_start is defined at the start of .bss
 
diff --git a/lld/test/ELF/build-id.s b/lld/test/ELF/build-id.s
index 2e555805fa3e0..32966b8a378b8 100644
--- a/lld/test/ELF/build-id.s
+++ b/lld/test/ELF/build-id.s
@@ -6,42 +6,42 @@
 # RUN: llvm-readobj -S %t2 | FileCheck -check-prefix=ALIGN %s
 
 # RUN: ld.lld --build-id %t -o %t2 -threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=DEFAULT %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=DEFAULT %s
 # RUN: ld.lld --build-id=fast %t -o %t2 -threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=DEFAULT %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=DEFAULT %s
 # RUN: ld.lld --build-id %t -o %t2 -no-threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=DEFAULT %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=DEFAULT %s
 
 # RUN: ld.lld --build-id=md5 %t -o %t2 -threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=MD5 %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=MD5 %s
 # RUN: ld.lld --build-id=md5 %t -o %t2 -no-threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=MD5 %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=MD5 %s
 
 # RUN: ld.lld --build-id=sha1 %t -o %t2 -threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SHA1 %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SHA1 %s
 # RUN: ld.lld --build-id=sha1 %t -o %t2 -no-threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SHA1 %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SHA1 %s
 
 # RUN: ld.lld --build-id=tree %t -o %t2 -threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SHA1 %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SHA1 %s
 # RUN: ld.lld --build-id=tree %t -o %t2 -no-threads
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SHA1 %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SHA1 %s
 
 # RUN: ld.lld --build-id=uuid %t -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=UUID %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=UUID %s
 
 # RUN: ld.lld --build-id=0x12345678 %t -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=HEX %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=HEX %s
 
 # RUN: ld.lld %t -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=NONE %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=NONE %s
 
 # RUN: ld.lld --build-id=md5 --build-id=none %t -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=NONE %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=NONE %s
 # RUN: ld.lld --build-id --build-id=none %t -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=NONE %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=NONE %s
 # RUN: ld.lld --build-id=none --build-id %t -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=DEFAULT %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=DEFAULT %s
 
 .globl _start
 _start:
diff --git a/lld/test/ELF/defsym.s b/lld/test/ELF/defsym.s
index 2e07ca7c1cfbb..94c1bc0179b00 100644
--- a/lld/test/ELF/defsym.s
+++ b/lld/test/ELF/defsym.s
@@ -2,12 +2,12 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld -o %t %t.o --defsym=foo2=foo1
 # RUN: llvm-readobj --symbols -S %t | FileCheck %s
-# RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s --check-prefix=USE
+# RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s --check-prefix=USE
 
 ## Check that we accept --defsym foo2=foo1 form.
 # RUN: ld.lld -o %t2 %t.o --defsym foo2=foo1
 # RUN: llvm-readobj --symbols -S %t2 | FileCheck %s
-# RUN: llvm-objdump -d -print-imm-hex %t2 | FileCheck %s --check-prefix=USE
+# RUN: llvm-objdump -d --print-imm-hex %t2 | FileCheck %s --check-prefix=USE
 
 ## Check we are reporting the error correctly and don't crash
 ## when handling the second --defsym.
diff --git a/lld/test/ELF/edata-etext.s b/lld/test/ELF/edata-etext.s
index f7048c310290e..f0f515f1dcc53 100644
--- a/lld/test/ELF/edata-etext.s
+++ b/lld/test/ELF/edata-etext.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t
-# RUN: llvm-objdump -t -section-headers %t | FileCheck %s
+# RUN: llvm-objdump -t --section-headers %t | FileCheck %s
 
 ## This checks that:
 ## 1) Address of _etext is the first location after the last read-only loadable segment.
diff --git a/lld/test/ELF/edata-no-bss.s b/lld/test/ELF/edata-no-bss.s
index c5f0c776d8c77..751f490f35078 100644
--- a/lld/test/ELF/edata-no-bss.s
+++ b/lld/test/ELF/edata-no-bss.s
@@ -4,7 +4,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t --gc-sections
-# RUN: llvm-objdump -t -section-headers %t | FileCheck %s
+# RUN: llvm-objdump -t --section-headers %t | FileCheck %s
 
 # CHECK: .data         00000008 000000000020215c DATA
 
diff --git a/lld/test/ELF/eh-frame-hdr-abs-fde.s b/lld/test/ELF/eh-frame-hdr-abs-fde.s
index f3b3cace56db2..9f199471311f9 100644
--- a/lld/test/ELF/eh-frame-hdr-abs-fde.s
+++ b/lld/test/ELF/eh-frame-hdr-abs-fde.s
@@ -5,7 +5,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld --eh-frame-hdr %t.o -o %t
-# RUN: llvm-objdump -s -dwarf=frames %t | FileCheck %s
+# RUN: llvm-objdump -s --dwarf=frames %t | FileCheck %s
 
 # CHECK: Augmentation:          "zLR"
 # CHECK: Augmentation data:     00 1B
diff --git a/lld/test/ELF/eh-frame-hdr-icf.s b/lld/test/ELF/eh-frame-hdr-icf.s
index 0ef3f97de8d37..40c518fcbcc1a 100644
--- a/lld/test/ELF/eh-frame-hdr-icf.s
+++ b/lld/test/ELF/eh-frame-hdr-icf.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: ld.lld %t -o %t2 --icf=all --eh-frame-hdr
-# RUN: llvm-objdump -s -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump -s --section-headers %t2 | FileCheck %s
 
 ## Check .eh_frame_hdr contains single FDE and no garbage data at tail.
 # CHECK: Sections:
diff --git a/lld/test/ELF/emit-relocs-gc.s b/lld/test/ELF/emit-relocs-gc.s
index 9379630e7bffa..97ff8074013a8 100644
--- a/lld/test/ELF/emit-relocs-gc.s
+++ b/lld/test/ELF/emit-relocs-gc.s
@@ -3,7 +3,7 @@
 
 ## Show that we emit .rela.bar and .rela.text when GC is disabled.
 # RUN: ld.lld --emit-relocs %t.o -o %t
-# RUN: llvm-objdump %t -section-headers | FileCheck %s --check-prefix=NOGC
+# RUN: llvm-objdump %t --section-headers | FileCheck %s --check-prefix=NOGC
 # NOGC: .rela.text
 # NOGC: .rela.bar
 
@@ -13,7 +13,7 @@
 # RUN:   | FileCheck --check-prefix=MSG %s
 # MSG: removing unused section {{.*}}.o:(.bar)
 # MSG: removing unused section {{.*}}.o:(.rela.bar)
-# RUN: llvm-objdump %t -section-headers | FileCheck %s --check-prefix=GC
+# RUN: llvm-objdump %t --section-headers | FileCheck %s --check-prefix=GC
 # GC-NOT:  rela.bar
 # GC:      rela.text
 # GC-NOT:  rela.bar
diff --git a/lld/test/ELF/exclude.s b/lld/test/ELF/exclude.s
index 8fe003747b148..bb7bbfbe21253 100644
--- a/lld/test/ELF/exclude.s
+++ b/lld/test/ELF/exclude.s
@@ -1,9 +1,9 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: ld.lld -o %t1 %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # RUN: ld.lld -r -o %t1 %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck --check-prefix=RELOCATABLE %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck --check-prefix=RELOCATABLE %s
 
 # CHECK-NOT:      .aaa
 # RELOCATABLE:    .aaa
diff --git a/lld/test/ELF/format-binary.test b/lld/test/ELF/format-binary.test
index 7c554bb60e43a..fc843345cbb52 100644
--- a/lld/test/ELF/format-binary.test
+++ b/lld/test/ELF/format-binary.test
@@ -60,10 +60,10 @@
 # RUN: ld.lld -b binary %t.binary -T %t.script -o %t.out
 # RUN: llvm-readobj %t.out -sections -section-data -symbols | FileCheck -check-prefix=X86-64 %s
 
-# X86-64: Format: ELF64-x86-64
+# X86-64: Format: elf64-x86-64
 
 # RUN: echo 'OUTPUT_FORMAT("elf64-x86-64")' > %t.script
 # RUN: ld.lld -b binary %t.binary -T %t.script -o %t.out
 # RUN: llvm-readobj %t.out -sections -section-data -symbols | FileCheck -check-prefix=X86-64-in-quotes %s
 
-# X86-64-in-quotes: Format: ELF64-x86-64
+# X86-64-in-quotes: Format: elf64-x86-64
diff --git a/lld/test/ELF/gc-sections-metadata-startstop.s b/lld/test/ELF/gc-sections-metadata-startstop.s
index 3e005ae176419..51324261cc8db 100644
--- a/lld/test/ELF/gc-sections-metadata-startstop.s
+++ b/lld/test/ELF/gc-sections-metadata-startstop.s
@@ -3,7 +3,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld --gc-sections %t.o -o %t
-# RUN: llvm-objdump -section-headers -t %t | FileCheck  %s
+# RUN: llvm-objdump --section-headers -t %t | FileCheck  %s
 
 # CHECK: Sections:
 # CHECK-NOT: yy
diff --git a/lld/test/ELF/gnu-hash-table.s b/lld/test/ELF/gnu-hash-table.s
index 092e584cf47aa..91ebe5d7ab95a 100644
--- a/lld/test/ELF/gnu-hash-table.s
+++ b/lld/test/ELF/gnu-hash-table.s
@@ -68,7 +68,7 @@
 # EMPTY-NEXT:   Values: []
 # EMPTY-NEXT: }
 
-# I386:      Format: ELF32-i386
+# I386:      Format: elf32-i386
 # I386:      Arch: i386
 # I386:      AddressSize: 32bit
 # I386:      Sections [
@@ -127,7 +127,7 @@
 # I386-NEXT:   Values: [0xB8860BA, 0xB887389]
 # I386-NEXT: }
 
-# X86_64:      Format: ELF64-x86-64
+# X86_64:      Format: elf64-x86-64
 # X86_64:      Arch: x86_64
 # X86_64:      AddressSize: 64bit
 # X86_64:      Sections [
@@ -187,7 +187,7 @@
 # X86_64-NEXT:   Values: [0xB8860BA, 0xB887389]
 # X86_64-NEXT: }
 
-# PPC64:      Format: ELF64-ppc64
+# PPC64:      Format: elf64-powerpc
 # PPC64:      Arch: powerpc64
 # PPC64:      AddressSize: 64bit
 # PPC64:      Sections [
diff --git a/lld/test/ELF/gnu-ifunc-dyntags.s b/lld/test/ELF/gnu-ifunc-dyntags.s
index 1b5eb1b3dde3e..9d1a0c5e23ad7 100644
--- a/lld/test/ELF/gnu-ifunc-dyntags.s
+++ b/lld/test/ELF/gnu-ifunc-dyntags.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld -pie %t.o -o %tout
-# RUN: llvm-objdump -section-headers %tout | FileCheck %s
+# RUN: llvm-objdump --section-headers %tout | FileCheck %s
 # RUN: llvm-readobj --dynamic-table -r %tout | FileCheck %s --check-prefix=TAGS
 
 ## Check we produce DT_PLTREL/DT_JMPREL/DT_PLTGOT and DT_PLTRELSZ tags
diff --git a/lld/test/ELF/got32-i386.s b/lld/test/ELF/got32-i386.s
index d83becd624210..071ad0f5aae26 100644
--- a/lld/test/ELF/got32-i386.s
+++ b/lld/test/ELF/got32-i386.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t
-# RUN: llvm-objdump -section-headers -d %t | FileCheck %s
+# RUN: llvm-objdump --section-headers -d %t | FileCheck %s
 
 ## We have R_386_GOT32 relocation here.
 .globl foo
diff --git a/lld/test/ELF/got32x-i386.s b/lld/test/ELF/got32x-i386.s
index b72411f6f2b54..6d93a90727798 100644
--- a/lld/test/ELF/got32x-i386.s
+++ b/lld/test/ELF/got32x-i386.s
@@ -29,7 +29,7 @@
 ## is only allowed for non-PIC code.
 ##
 # RUN: ld.lld %S/Inputs/i386-got32x-baseless.elf -o %t1
-# RUN: llvm-objdump -section-headers -d %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers -d %t1 | FileCheck %s
 
 ## 73728 == 0x12000 == ADDR(.got)
 # CHECK: Sections:
diff --git a/lld/test/ELF/i386-pc16.test b/lld/test/ELF/i386-pc16.test
index a422e5bac9056..e0ae31d2da000 100644
--- a/lld/test/ELF/i386-pc16.test
+++ b/lld/test/ELF/i386-pc16.test
@@ -2,7 +2,7 @@
 
 # RUN: yaml2obj %s -o %t.o
 # RUN: ld.lld -Ttext 0x0 %t.o -o %t.exe
-# RUN: llvm-objdump -s -section=.text %t.exe 2>&1 | FileCheck %s
+# RUN: llvm-objdump -s --section=.text %t.exe 2>&1 | FileCheck %s
 
 # CHECK:      Contents of section .text:
 # CHECK-NEXT:  0000 45231111 41231111
diff --git a/lld/test/ELF/i386-pc8.s b/lld/test/ELF/i386-pc8.s
index 65cbd21ccb62e..db3bcac2aa632 100644
--- a/lld/test/ELF/i386-pc8.s
+++ b/lld/test/ELF/i386-pc8.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=i386-pc-linux-gnu %s -o %t1.o
 # RUN: ld.lld -Ttext 0x0 %t1.o -o %t.out
-# RUN: llvm-objdump -s -section=.text %t.out | FileCheck %s
+# RUN: llvm-objdump -s --section=.text %t.out | FileCheck %s
 
 # CHECK:      Contents of section .text:
 # CHECK-NEXT:  0000 15253748
diff --git a/lld/test/ELF/i386-reloc-large-addend.s b/lld/test/ELF/i386-reloc-large-addend.s
index f17e5c6bf7dc8..7d4816dc0a6f3 100644
--- a/lld/test/ELF/i386-reloc-large-addend.s
+++ b/lld/test/ELF/i386-reloc-large-addend.s
@@ -5,7 +5,7 @@
 // RUN: llvm-mc %t1.s -o %t1.o -triple i386-pc-linux -filetype=obj
 
 // RUN: ld.lld -Ttext 0x7000 %t.o %t1.o -o %t
-// RUN: llvm-objdump -d -triple=i386-pc-linux-code16 %t | FileCheck %s
+// RUN: llvm-objdump -d --triple=i386-pc-linux-code16 %t | FileCheck %s
 
 // CHECK:        Disassembly of section .text:
 // CHECK-EMPTY:
diff --git a/lld/test/ELF/i386-reloc-range.s b/lld/test/ELF/i386-reloc-range.s
index bdaeac24138b2..ffdae86f516ad 100644
--- a/lld/test/ELF/i386-reloc-range.s
+++ b/lld/test/ELF/i386-reloc-range.s
@@ -7,7 +7,7 @@
 // RUN: llvm-mc %t2.s -o %t2.o -triple i386-pc-linux -filetype=obj
 
 // RUN: ld.lld -Ttext 0x200 %t.o %t1.o -o %t1
-// RUN: llvm-objdump -d --no-show-raw-insn -triple=i386-pc-linux-code16 %t1 | FileCheck %s
+// RUN: llvm-objdump -d --no-show-raw-insn --triple=i386-pc-linux-code16 %t1 | FileCheck %s
 
 // CHECK:        Disassembly of section .text:
 // CHECK-EMPTY:
diff --git a/lld/test/ELF/icf7.s b/lld/test/ELF/icf7.s
index 554056099aa75..1046dd56474a6 100644
--- a/lld/test/ELF/icf7.s
+++ b/lld/test/ELF/icf7.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: ld.lld %t -o %t2 --icf=all --print-icf-sections | FileCheck %s
-# RUN: llvm-objdump -t %t2 | FileCheck -check-prefix=ALIGN %s
+# RUN: llvm-objdump -t %t2 | FileCheck --check-prefix=ALIGN %s
 
 # CHECK: selected section {{.*}}:(.text.f1)
 # CHECK:   removing identical section {{.*}}:(.text.f2)
diff --git a/lld/test/ELF/init_fini_priority.s b/lld/test/ELF/init_fini_priority.s
index 17003ce30dfeb..0e5ba8fe44932 100644
--- a/lld/test/ELF/init_fini_priority.s
+++ b/lld/test/ELF/init_fini_priority.s
@@ -1,6 +1,6 @@
 // REQUIRES: x86
 // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
-// RUN: llvm-objdump -section-headers %t | FileCheck %s --check-prefix=OBJ
+// RUN: llvm-objdump --section-headers %t | FileCheck %s --check-prefix=OBJ
 // RUN: ld.lld %t -o %t.exe
 // RUN: llvm-objdump -s %t.exe | FileCheck %s
 
diff --git a/lld/test/ELF/linkerscript/addr.test b/lld/test/ELF/linkerscript/addr.test
index 2e68cc271c03b..faec4f91da897 100644
--- a/lld/test/ELF/linkerscript/addr.test
+++ b/lld/test/ELF/linkerscript/addr.test
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/addr.s -o %t
 # RUN: ld.lld %t --script %s -o %t1
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # CHECK:      Sections:
 # CHECK-NEXT: Idx Name          Size     VMA              Type
diff --git a/lld/test/ELF/linkerscript/align-empty.test b/lld/test/ELF/linkerscript/align-empty.test
index 06d3945ddc4f3..13edafe92eff7 100644
--- a/lld/test/ELF/linkerscript/align-empty.test
+++ b/lld/test/ELF/linkerscript/align-empty.test
@@ -3,7 +3,7 @@
 # RUN:   | llvm-mc -filetype=obj -triple=x86_64-unknown-linux - -o %t.o
 
 # RUN: ld.lld -o %t1 --script %s %t.o -shared
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 SECTIONS {
   . = SIZEOF_HEADERS;
diff --git a/lld/test/ELF/linkerscript/align1.test b/lld/test/ELF/linkerscript/align1.test
index bc3a89cbbcca0..e7b65fc75ffe2 100644
--- a/lld/test/ELF/linkerscript/align1.test
+++ b/lld/test/ELF/linkerscript/align1.test
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/align.s -o %t.o
 # RUN: ld.lld -o %t --script %s %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 SECTIONS {
   . = 0x10000;
@@ -22,7 +22,7 @@ SECTIONS {
 ## Check that ALIGN zero do nothing and does not crash #1.
 # RUN: echo "SECTIONS { . = ALIGN(0x123, 0); .aaa : { *(.aaa) } }" > %t.script
 # RUN: ld.lld -o %t4 --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t4 | FileCheck %s -check-prefix=ZERO
+# RUN: llvm-objdump --section-headers %t4 | FileCheck %s --check-prefix=ZERO
 
 # ZERO:      Sections:
 # ZERO-NEXT: Idx Name          Size     VMA              Type
@@ -32,7 +32,7 @@ SECTIONS {
 ## Check that ALIGN zero do nothing and does not crash #2.
 # RUN: echo "SECTIONS { . = 0x123; . = ALIGN(0); .aaa : { *(.aaa) } }" > %t.script
 # RUN: ld.lld -o %t5 --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t5 | FileCheck %s -check-prefix=ZERO
+# RUN: llvm-objdump --section-headers %t5 | FileCheck %s --check-prefix=ZERO
 
 ## Test we fail gracefuly when alignment value is not a power of 2 (#1).
 # RUN: echo "SECTIONS { . = 0x123; . = ALIGN(0x123, 3); .aaa : { *(.aaa) } }" > %t.script
diff --git a/lld/test/ELF/linkerscript/align2.test b/lld/test/ELF/linkerscript/align2.test
index 56aba4738a795..54307b249f070 100644
--- a/lld/test/ELF/linkerscript/align2.test
+++ b/lld/test/ELF/linkerscript/align2.test
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/align.s -o %t.o
 # RUN: ld.lld -o %t --script %s %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 SECTIONS {
   . = ALIGN(0x1234, 0x10000);
diff --git a/lld/test/ELF/linkerscript/align3.test b/lld/test/ELF/linkerscript/align3.test
index 8c9146e016d10..aca0f6eed5483 100644
--- a/lld/test/ELF/linkerscript/align3.test
+++ b/lld/test/ELF/linkerscript/align3.test
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/align.s -o %t.o
 # RUN: ld.lld -o %t --script %s %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 SECTIONS {
   . = 0x10000;
diff --git a/lld/test/ELF/linkerscript/arm-exidx-sentinel-and-assignment.s b/lld/test/ELF/linkerscript/arm-exidx-sentinel-and-assignment.s
index ea3548ca820ee..9053863147779 100644
--- a/lld/test/ELF/linkerscript/arm-exidx-sentinel-and-assignment.s
+++ b/lld/test/ELF/linkerscript/arm-exidx-sentinel-and-assignment.s
@@ -7,7 +7,7 @@
 ## We used to crash if the last output section command for .ARM.exidx
 ## was anything but an input section description.
 # RUN: ld.lld --no-merge-exidx-entries -T %t.script %t.o -shared -o %t.so
-# RUN: llvm-objdump -s -triple=armv7a-none-linux-gnueabi %t.so | FileCheck %s
+# RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t.so | FileCheck %s
 # RUN: llvm-readobj -S --symbols %t.so | FileCheck %s --check-prefix=SYMBOL
 
  .syntax unified
diff --git a/lld/test/ELF/linkerscript/at2.test b/lld/test/ELF/linkerscript/at2.test
index 84c9db99d7fed..d744fce911b48 100644
--- a/lld/test/ELF/linkerscript/at2.test
+++ b/lld/test/ELF/linkerscript/at2.test
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/at2.s -o %t.o
 # RUN: ld.lld -o %t.exe %t.o --script %s
 # RUN: llvm-readelf -l %t.exe | FileCheck %s
-# RUN: llvm-objdump -section-headers %t.exe | FileCheck %s --check-prefix=SECTIONS
+# RUN: llvm-objdump --section-headers %t.exe | FileCheck %s --check-prefix=SECTIONS
 
 MEMORY {
   AX (ax)    : ORIGIN = 0x2000, LENGTH = 0x100
diff --git a/lld/test/ELF/linkerscript/constructor.test b/lld/test/ELF/linkerscript/constructor.test
index edd2cd297997d..c4098245d652b 100644
--- a/lld/test/ELF/linkerscript/constructor.test
+++ b/lld/test/ELF/linkerscript/constructor.test
@@ -3,7 +3,7 @@
 # RUN:   | llvm-mc -filetype=obj -triple=x86_64-unknown-linux - -o %t.o
 # RUN: ld.lld -o %t1 --script %s %t.o
 
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # CHECK:      Sections:
 # CHECK-NEXT: Idx Name          Size
 # CHECK-NEXT:   0               00000000
diff --git a/lld/test/ELF/linkerscript/data-commands1.test b/lld/test/ELF/linkerscript/data-commands1.test
index 32c5978c30a8a..e15e420d2a194 100644
--- a/lld/test/ELF/linkerscript/data-commands1.test
+++ b/lld/test/ELF/linkerscript/data-commands1.test
@@ -36,7 +36,7 @@ SECTIONS {
 
 # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %p/Inputs/data-commands.s -o %t2.o
 # RUN: ld.lld --script %s %t2.o -o %t2
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=BIGENDIAN %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=BIGENDIAN %s
 # BIGENDIAN:      Contents of section .foo:
 # BIGENDIAN-NEXT:   ff11ff11 22ff1122 3344ff11 22334455
 # BIGENDIAN-NEXT:   667788
diff --git a/lld/test/ELF/linkerscript/define.test b/lld/test/ELF/linkerscript/define.test
index 3a2e242e015c2..689476ba32ad0 100644
--- a/lld/test/ELF/linkerscript/define.test
+++ b/lld/test/ELF/linkerscript/define.test
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/define.s -o %t.o
 # RUN: ld.lld -o %t --script %s %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 SECTIONS {
   . = DEFINED(defined) ? 0x11000 : .;
diff --git a/lld/test/ELF/linkerscript/discard-gnu-hash.s b/lld/test/ELF/linkerscript/discard-gnu-hash.s
index 77f168de9cafa..5ebad7e26244b 100644
--- a/lld/test/ELF/linkerscript/discard-gnu-hash.s
+++ b/lld/test/ELF/linkerscript/discard-gnu-hash.s
@@ -2,13 +2,13 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 
 # RUN: ld.lld --hash-style both -shared -o %t1 %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # CHECK: .gnu.hash
 # CHECK: .hash
 
 # RUN: echo "SECTIONS { /DISCARD/ : { *(.hash) } }" > %t.script
 # RUN: ld.lld --hash-style both -shared -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 \
+# RUN: llvm-objdump --section-headers %t1 \
 # RUN:   | FileCheck %s --check-prefix=HASH
 # HASH-NOT: .hash
 # HASH:     .gnu.hash
@@ -16,7 +16,7 @@
 
 # RUN: echo "SECTIONS { /DISCARD/ : { *(.gnu.hash) } }" > %t.script
 # RUN: ld.lld --hash-style both -shared -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 \
+# RUN: llvm-objdump --section-headers %t1 \
 # RUN:   | FileCheck %s --check-prefix=GNUHASH
 # GNUHASH-NOT: .gnu.hash
 # GNUHASH:     .hash
diff --git a/lld/test/ELF/linkerscript/discard-linkorder.s b/lld/test/ELF/linkerscript/discard-linkorder.s
index 961615d51c98d..8fa831a7844d5 100644
--- a/lld/test/ELF/linkerscript/discard-linkorder.s
+++ b/lld/test/ELF/linkerscript/discard-linkorder.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: echo "SECTIONS { /DISCARD/ : { *(.foo) } }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # CHECK-NOT: .foo
 # CHECK-NOT: .bar
diff --git a/lld/test/ELF/linkerscript/discard-section.s b/lld/test/ELF/linkerscript/discard-section.s
index a5af908068297..fbdff5dfbe849 100644
--- a/lld/test/ELF/linkerscript/discard-section.s
+++ b/lld/test/ELF/linkerscript/discard-section.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: echo "SECTIONS { /DISCARD/ : { *(.aaa*) } }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # CHECK-NOT: .aaa
 
diff --git a/lld/test/ELF/linkerscript/double-bss.test b/lld/test/ELF/linkerscript/double-bss.test
index 32b796d01c2e2..59eb4cb1d6152 100644
--- a/lld/test/ELF/linkerscript/double-bss.test
+++ b/lld/test/ELF/linkerscript/double-bss.test
@@ -2,7 +2,7 @@
 # RUN: echo '.short 0; .bss; .zero 4; .comm q,128,8' \
 # RUN:   | llvm-mc -filetype=obj -triple=x86_64-unknown-linux - -o %t
 # RUN: ld.lld -o %t1 --script %s %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # CHECK:      .bss1          00000004 0000000000000122 BSS
 # CHECK-NEXT: .bss2          00000080 0000000000000128 BSS
 
diff --git a/lld/test/ELF/linkerscript/eh-frame-emit-relocs.s b/lld/test/ELF/linkerscript/eh-frame-emit-relocs.s
index d951cbc261b97..d0fcf7a16db56 100644
--- a/lld/test/ELF/linkerscript/eh-frame-emit-relocs.s
+++ b/lld/test/ELF/linkerscript/eh-frame-emit-relocs.s
@@ -2,7 +2,7 @@
 # RUN: echo "SECTIONS { .foo : { *(.eh_frame) } }" > %t.script
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld --emit-relocs %t.o -T %t.script -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 # CHECK-NOT: eh_frame
 # CHECK:     .rela.foo
diff --git a/lld/test/ELF/linkerscript/eh-frame-hdr.s b/lld/test/ELF/linkerscript/eh-frame-hdr.s
index a7892b2259e09..1a1cf8d220c9c 100644
--- a/lld/test/ELF/linkerscript/eh-frame-hdr.s
+++ b/lld/test/ELF/linkerscript/eh-frame-hdr.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: echo "SECTIONS { .eh_frame_hdr : {} .eh_frame : {} }" > %t.script
 # RUN: ld.lld -o %t1 --eh-frame-hdr --script %t.script %t
-# RUN: llvm-objdump -s -section=".eh_frame_hdr" %t1 | FileCheck %s
+# RUN: llvm-objdump -s --section=".eh_frame_hdr" %t1 | FileCheck %s
 
 # CHECK:      011b033b 14000000 01000000 4d000000
 # CHECK-NEXT: 30000000
diff --git a/lld/test/ELF/linkerscript/eh-frame-merge.s b/lld/test/ELF/linkerscript/eh-frame-merge.s
index ac25399df4178..7a9c40b5797e8 100644
--- a/lld/test/ELF/linkerscript/eh-frame-merge.s
+++ b/lld/test/ELF/linkerscript/eh-frame-merge.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: echo "SECTIONS { .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame) } }" > %t.script
-# RUN: ld.lld -o %t --no-threads --eh-frame-hdr --script %t.script %t.o
+# RUN: ld.lld -o %t --eh-frame-hdr --script %t.script %t.o
 # RUN: llvm-readobj -S -u %t | FileCheck %s
 
 # CHECK: Name: .dah
diff --git a/lld/test/ELF/linkerscript/eh-frame.s b/lld/test/ELF/linkerscript/eh-frame.s
index 5e43ec738f7bf..ef7fe4257494c 100644
--- a/lld/test/ELF/linkerscript/eh-frame.s
+++ b/lld/test/ELF/linkerscript/eh-frame.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: echo "SECTIONS { .eh_frame : { *(.eh_frame) } }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -s -section=".eh_frame" %t1 | FileCheck %s
+# RUN: llvm-objdump -s --section=".eh_frame" %t1 | FileCheck %s
 
 # CHECK: 0000 14000000 00000000 017a5200 01781001
 # CHECK-NEXT: 0010 1b0c0708 90010000
diff --git a/lld/test/ELF/linkerscript/emit-reloc-section-names.s b/lld/test/ELF/linkerscript/emit-reloc-section-names.s
index 7f76057322e88..805d3c2cad4b2 100644
--- a/lld/test/ELF/linkerscript/emit-reloc-section-names.s
+++ b/lld/test/ELF/linkerscript/emit-reloc-section-names.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: echo "SECTIONS { .text.zed : { *(.text.foo) } .text.qux : { *(.text.bar) } }" > %t.script
 # RUN: ld.lld -T %t.script --emit-relocs %t.o -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 ## Check we name relocation sections in according to
 ## their target sections names.
diff --git a/lld/test/ELF/linkerscript/emit-relocs-ehframe-discard.s b/lld/test/ELF/linkerscript/emit-relocs-ehframe-discard.s
index 9df0e8ce9dcb3..b83c83a7654e4 100644
--- a/lld/test/ELF/linkerscript/emit-relocs-ehframe-discard.s
+++ b/lld/test/ELF/linkerscript/emit-relocs-ehframe-discard.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
 # RUN: echo "SECTIONS { /DISCARD/ : { *(.eh_frame) } }" > %t.script
 # RUN: ld.lld --emit-relocs --script %t.script %t1.o -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 # CHECK-NOT: .rela.eh_frame
 
diff --git a/lld/test/ELF/linkerscript/empty-load.s b/lld/test/ELF/linkerscript/empty-load.s
index a2b7d8227f607..9e6beb679162c 100644
--- a/lld/test/ELF/linkerscript/empty-load.s
+++ b/lld/test/ELF/linkerscript/empty-load.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: echo "SECTIONS { .rw : { *(.rw) } .text : { *(.text) } }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -private-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --private-headers %t1 | FileCheck %s
 
 ## We expect 2 PT_LOAD segments
 # CHECK:     Program Header:
diff --git a/lld/test/ELF/linkerscript/empty-sections-expressions.s b/lld/test/ELF/linkerscript/empty-sections-expressions.s
index 3c9a9edf5786e..44b245cfc9981 100644
--- a/lld/test/ELF/linkerscript/empty-sections-expressions.s
+++ b/lld/test/ELF/linkerscript/empty-sections-expressions.s
@@ -6,12 +6,12 @@
 
 # RUN: echo "SECTIONS { .debug_info 0 : { *(.debug_info) } }" > %t.script
 # RUN: ld.lld -o %t --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 # CHECK-NOT: .debug_info
 
 # RUN: echo "SECTIONS { .debug_info foo : { *(.debug_info) } }" > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t.o
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s --check-prefix=SEC
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s --check-prefix=SEC
 # SEC: .debug_info
 
 .globl foo
diff --git a/lld/test/ELF/linkerscript/input-order.s b/lld/test/ELF/linkerscript/input-order.s
index cb9ea354cdbfb..071d49de7b3a6 100644
--- a/lld/test/ELF/linkerscript/input-order.s
+++ b/lld/test/ELF/linkerscript/input-order.s
@@ -5,7 +5,7 @@
 # .foo.1 .foo.2 .bar.1 .bar.2
 # RUN: echo "SECTIONS { . = 0x1000; .foo : {*(.foo.*) *(.bar.*)  } }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section=.foo -s %t1 | FileCheck --check-prefix=SCRIPT_ORDER %s
+# RUN: llvm-objdump --section=.foo -s %t1 | FileCheck --check-prefix=SCRIPT_ORDER %s
 # SCRIPT_ORDER: Contents of section .foo:
 # SCRIPT_ORDER-NEXT: 1000 00000000 00000000 ffffffff eeeeeeee
 
@@ -13,7 +13,7 @@
 # .bar.1 .foo.1 .bar.2 .foo.2
 # RUN: echo "SECTIONS { . = 0x1000; .foo : {*(.foo.* .bar.*)} }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section=.foo -s %t1 | FileCheck --check-prefix=FILE_ORDER %s
+# RUN: llvm-objdump --section=.foo -s %t1 | FileCheck --check-prefix=FILE_ORDER %s
 # FILE_ORDER: Contents of section .foo:
 # FILE_ORDER-NEXT: 1000 ffffffff 00000000 eeeeeeee 00000000
 
diff --git a/lld/test/ELF/linkerscript/input-sec-dup.s b/lld/test/ELF/linkerscript/input-sec-dup.s
index fd889393c74c7..8ac362b45377d 100644
--- a/lld/test/ELF/linkerscript/input-sec-dup.s
+++ b/lld/test/ELF/linkerscript/input-sec-dup.s
@@ -3,7 +3,7 @@
 
 # RUN: echo "SECTIONS {.foo : { *(.foo) *(.foo) } }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # CHECK:      Sections:
 # CHECK-NEXT: Idx Name          Size
 # CHECK-NEXT:   0               00000000
diff --git a/lld/test/ELF/linkerscript/linker-script-in-search-path.s b/lld/test/ELF/linkerscript/linker-script-in-search-path.s
index d411becb48f8f..49bf6c0089de5 100644
--- a/lld/test/ELF/linkerscript/linker-script-in-search-path.s
+++ b/lld/test/ELF/linkerscript/linker-script-in-search-path.s
@@ -7,7 +7,7 @@
 # RUN: echo 'OUTPUT("%t.out")' > %t.dir/script
 # RUN: ld.lld -T%t.dir/script %t.o
 # RUN: llvm-readobj %t.out | FileCheck %s
-# CHECK: Format: ELF64-x86-64
+# CHECK: Format: elf64-x86-64
 
 # If the linker script specified with -T is missing we should emit an error
 # RUN: not ld.lld -Tscript %t.o 2>&1 | FileCheck %s -check-prefix ERROR
diff --git a/lld/test/ELF/linkerscript/locationcountererr2.s b/lld/test/ELF/linkerscript/locationcountererr2.s
index 3a0c7692c54ec..f456da7cf8769 100644
--- a/lld/test/ELF/linkerscript/locationcountererr2.s
+++ b/lld/test/ELF/linkerscript/locationcountererr2.s
@@ -3,7 +3,7 @@
 # RUN: echo "SECTIONS {" > %t.script
 # RUN: echo ". = 0x150; . = 0x10; .text : {} }" >> %t.script
 # RUN: ld.lld %t.o --script %t.script -o %t -shared
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 # CHECK:  Name   Size   VMA
 # CHECK: .text 00000000 0000000000000010
 
diff --git a/lld/test/ELF/linkerscript/memory-include.test b/lld/test/ELF/linkerscript/memory-include.test
index aa2f1f8864705..c233a81e2298c 100644
--- a/lld/test/ELF/linkerscript/memory-include.test
+++ b/lld/test/ELF/linkerscript/memory-include.test
@@ -7,7 +7,7 @@
 # RUN: rm -rf %t.dir && mkdir -p %t.dir
 # RUN: echo "RAM2 (rwx): ORIGIN = 0x3000, LENGTH = 0x100" > %t.dir/inc.script
 # RUN: ld.lld -o %t.elf --script %s %t.o -L %t.dir
-# RUN: llvm-objdump -section-headers %t.elf | FileCheck %s
+# RUN: llvm-objdump --section-headers %t.elf | FileCheck %s
 # CHECK: .data         00000008 0000000000002000 DATA
 # CHECK: .data2        00000008 0000000000003000 DATA
 
diff --git a/lld/test/ELF/linkerscript/memory3.s b/lld/test/ELF/linkerscript/memory3.s
index 3a4913724c5f6..b9d609e59e31c 100644
--- a/lld/test/ELF/linkerscript/memory3.s
+++ b/lld/test/ELF/linkerscript/memory3.s
@@ -4,13 +4,13 @@
 # RUN:                ram1 (ax) : ORIGIN = 0x4000, LENGTH = 1K } \
 # RUN: SECTIONS {}" > %t1.script
 # RUN: ld.lld -o %t1 --script %t1.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # RUN: echo "MEMORY { ram1 (ax) : ORIGIN = 0x1000, LENGTH = 1K   \
 # RUN:                ram2 (ax) : ORIGIN = 0x4000, LENGTH = 1K } \
 # RUN: SECTIONS {}" > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s
 
 ## Check we place .text into first defined memory region with appropriate flags.
 # CHECK: Sections:
diff --git a/lld/test/ELF/linkerscript/merge-nonalloc.s b/lld/test/ELF/linkerscript/merge-nonalloc.s
index de4a1d5c3e49f..41d306b24196d 100644
--- a/lld/test/ELF/linkerscript/merge-nonalloc.s
+++ b/lld/test/ELF/linkerscript/merge-nonalloc.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: echo "SECTIONS { .text : { *(.text) *(.nonalloc) } }" > %t.script
 # RUN: ld.lld -shared -o %t.exe %t.script %t.o
-# RUN: llvm-objdump -syms %t.exe | FileCheck %s
+# RUN: llvm-objdump --syms %t.exe | FileCheck %s
 
 # CHECK: .text 0000000000000000 nonalloc_start
 
diff --git a/lld/test/ELF/linkerscript/multi-sections-constraint.s b/lld/test/ELF/linkerscript/multi-sections-constraint.s
index c1a253a69c1cc..811c0006582f4 100644
--- a/lld/test/ELF/linkerscript/multi-sections-constraint.s
+++ b/lld/test/ELF/linkerscript/multi-sections-constraint.s
@@ -5,7 +5,7 @@
 # RUN:  . = 0x1000; .aaa : ONLY_IF_RO { *(.aaa.*) } \
 # RUN:  . = 0x2000; .aaa : ONLY_IF_RW { *(.aaa.*) } } " > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # CHECK:      Sections:
 # CHECK-NEXT: Idx Name          Size      VMA          Type
@@ -17,7 +17,7 @@
 # RUN:  . = 0x1000; .aaa : ONLY_IF_RW { *(.aaa.*) } \
 # RUN:  . = 0x2000; .aaa : ONLY_IF_RO { *(.aaa.*) } } " > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s --check-prefix=REV
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s --check-prefix=REV
 
 # REV:      Sections:
 # REV-NEXT: Idx Name          Size       VMA          Type
diff --git a/lld/test/ELF/linkerscript/numbers.s b/lld/test/ELF/linkerscript/numbers.s
index 43a676f9d4668..af394399c5137 100644
--- a/lld/test/ELF/linkerscript/numbers.s
+++ b/lld/test/ELF/linkerscript/numbers.s
@@ -15,7 +15,7 @@
 # RUN:  .mega2 : { *(.mega.2) } \
 # RUN: }" > %t.script
 # RUN: ld.lld %t --script %t.script -o %t2
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s
 
 # CHECK:     Sections:
 # CHECK-NEXT: Idx Name          Size     VMA
@@ -65,7 +65,7 @@
 # RUN:  .hex2 0x500:{ *(.hex.2) } \
 # RUN: }" > %t8.script
 # RUN: ld.lld %t --script %t8.script -o %t6
-# RUN: llvm-objdump -section-headers %t6 | FileCheck -check-prefix=SECADDR %s
+# RUN: llvm-objdump --section-headers %t6 | FileCheck --check-prefix=SECADDR %s
 # SECADDR:     Sections:
 # SECADDR-NEXT: Idx Name          Size     VMA
 # SECADDR-NEXT:   0               00000000 0000000000000000
diff --git a/lld/test/ELF/linkerscript/orphan.s b/lld/test/ELF/linkerscript/orphan.s
index 8a61b74d56c4f..d141f0e45587f 100644
--- a/lld/test/ELF/linkerscript/orphan.s
+++ b/lld/test/ELF/linkerscript/orphan.s
@@ -7,7 +7,7 @@
 # RUN:  .rw3 : { *(.rw3) }    \
 # RUN: }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 ## .jcr is a relro section and should be placed before other RW sections.
 ## .bss is SHT_NOBITS section and should be last RW section, so some space
diff --git a/lld/test/ELF/linkerscript/orphans.s b/lld/test/ELF/linkerscript/orphans.s
index 0a8c7ab1129bc..03088b5bc92c9 100644
--- a/lld/test/ELF/linkerscript/orphans.s
+++ b/lld/test/ELF/linkerscript/orphans.s
@@ -3,12 +3,12 @@
 
 # RUN: echo "SECTIONS { .writable : { *(.writable) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck -check-prefix=TEXTORPHAN %s
 
 # RUN: echo "SECTIONS { .text : { *(.text) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck -check-prefix=WRITABLEORPHAN %s
 
 # TEXTORPHAN:      Sections:
diff --git a/lld/test/ELF/linkerscript/out-of-order-section-in-region.test b/lld/test/ELF/linkerscript/out-of-order-section-in-region.test
index e7ea39610ad59..3fa8cadf27ad9 100644
--- a/lld/test/ELF/linkerscript/out-of-order-section-in-region.test
+++ b/lld/test/ELF/linkerscript/out-of-order-section-in-region.test
@@ -4,7 +4,7 @@
 # RUN:   | llvm-mc -filetype=obj -triple=x86_64-pc-linux - -o %t
 # RUN: ld.lld %t --script %s -o %t2
 
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s
 # CHECK: .aaa 00000008 0000000000001008 DATA
 # CHECK: .bbb 00000008 0000000000001000 DATA
 
diff --git a/lld/test/ELF/linkerscript/out-of-order.s b/lld/test/ELF/linkerscript/out-of-order.s
index 6dc479b752903..9b834cf712038 100644
--- a/lld/test/ELF/linkerscript/out-of-order.s
+++ b/lld/test/ELF/linkerscript/out-of-order.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-linux %s -o %t.o
 # RUN: echo "SECTIONS { .data 0x4000 : {*(.data)} .dynsym 0x2000 : {*(.dynsym)} .dynstr : {*(.dynstr)} }" > %t.script
 # RUN: ld.lld --hash-style=sysv -o %t.so --script %t.script %t.o -shared
-# RUN: llvm-objdump -section-headers %t.so | FileCheck %s
+# RUN: llvm-objdump --section-headers %t.so | FileCheck %s
 
 # Note: how the layout is done:
 #  we need to layout 2 segments, each contains sections:
diff --git a/lld/test/ELF/linkerscript/output-section-include.test b/lld/test/ELF/linkerscript/output-section-include.test
index 9d0228fa6b763..c4d502c307d3e 100644
--- a/lld/test/ELF/linkerscript/output-section-include.test
+++ b/lld/test/ELF/linkerscript/output-section-include.test
@@ -8,13 +8,13 @@
 # RUN: rm -rf %t.dir && mkdir -p %t.dir
 # RUN: echo "" > %t.dir/inc.script
 # RUN: ld.lld -o %t.elf --script %s %t.o -L %t.dir
-# RUN: llvm-objdump -section-headers %t.elf | FileCheck %s --check-prefix=CHECK1
+# RUN: llvm-objdump --section-headers %t.elf | FileCheck %s --check-prefix=CHECK1
 # CHECK1: .data         00000008 0000000000002000 DATA
 
 ## Non-empty include file.
 # RUN: echo "QUAD(0)" > %t.dir/inc.script
 # RUN: ld.lld -o %t.elf --script %s %t.o -L %t.dir
-# RUN: llvm-objdump -section-headers %t.elf | FileCheck %s --check-prefix=CHECK2
+# RUN: llvm-objdump --section-headers %t.elf | FileCheck %s --check-prefix=CHECK2
 # CHECK2: .data         00000010 0000000000002000 DATA
 
 MEMORY {
diff --git a/lld/test/ELF/linkerscript/overlapping-sections.s b/lld/test/ELF/linkerscript/overlapping-sections.s
index 8d886424c5405..a6c63d5d8d0e7 100644
--- a/lld/test/ELF/linkerscript/overlapping-sections.s
+++ b/lld/test/ELF/linkerscript/overlapping-sections.s
@@ -82,7 +82,7 @@
 # However, in order to create such a broken binary the user has to ignore a
 # fatal error by passing --noinhibit-exec, so this behaviour is fine.
 
-# RUN: llvm-objdump -s %t.so | FileCheck %s -check-prefix BROKEN-OUTPUT-FILE
+# RUN: llvm-objdump -s %t.so | FileCheck %s --check-prefix BROKEN-OUTPUT-FILE
 # BROKEN-OUTPUT-FILE-LABEL: Contents of section .sec1:
 # BROKEN-OUTPUT-FILE-NEXT: 8000 01010101 01010101 01010101 01010101
 # BROKEN-OUTPUT-FILE-NEXT: 8010 01010101 01010101 01010101 01010101
diff --git a/lld/test/ELF/linkerscript/region-alias.s b/lld/test/ELF/linkerscript/region-alias.s
index ec1582bd283cb..db716e180cc52 100644
--- a/lld/test/ELF/linkerscript/region-alias.s
+++ b/lld/test/ELF/linkerscript/region-alias.s
@@ -14,7 +14,7 @@
 # RUN: echo "REGION_ALIAS (\"ALIAS_TEXT\", ROM);" > %t.script.inc
 # RUN: echo "REGION_ALIAS (\"ALIAS_DATA\", RAM);" >> %t.script.inc
 # RUN: ld.lld %t --script %t.script -o %t2
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s
 # CHECK: .text       00000001 0000000000001000 TEXT
 # CHECK: .data       00000008 0000000000002000 DATA
 
@@ -22,7 +22,7 @@
 # RUN: echo "REGION_ALIAS (\"ALIAS_TEXT\", ROM);" > %t.script.inc
 # RUN: echo "REGION_ALIAS (\"ALIAS_DATA\", ROM);" >> %t.script.inc
 # RUN: ld.lld %t --script %t.script -o %t2
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s --check-prefix=RAM
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s --check-prefix=RAM
 # RAM: .text         00000001 0000000000001000 TEXT
 # RAM: .data         00000008 0000000000001001 DATA
 
diff --git a/lld/test/ELF/linkerscript/repsection-va.s b/lld/test/ELF/linkerscript/repsection-va.s
index 5da94d020e934..e92647a37e94e 100644
--- a/lld/test/ELF/linkerscript/repsection-va.s
+++ b/lld/test/ELF/linkerscript/repsection-va.s
@@ -3,7 +3,7 @@
 
 # RUN: echo "SECTIONS {.foo : {*(.foo.*)} }" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # CHECK:      Sections:
 # CHECK-NEXT: Idx Name          Size     VMA          Type
 # CHECK-NOT: .foo
diff --git a/lld/test/ELF/linkerscript/section-include.test b/lld/test/ELF/linkerscript/section-include.test
index 698d7597f7638..d1ea5eb31e3f1 100644
--- a/lld/test/ELF/linkerscript/section-include.test
+++ b/lld/test/ELF/linkerscript/section-include.test
@@ -8,14 +8,14 @@
 # RUN: rm -rf %t.dir && mkdir -p %t.dir
 # RUN: echo "" > %t.dir/inc.script
 # RUN: ld.lld -o %t.elf --script %s %t.o -L %t.dir
-# RUN: llvm-objdump -section-headers %t.elf | FileCheck %s --check-prefix=CHECK1
+# RUN: llvm-objdump --section-headers %t.elf | FileCheck %s --check-prefix=CHECK1
 # CHECK1:      .data         00000008 0000000000002000 DATA
 # CHECK1-NEXT: .data3        00000008 0000000000002008 DATA
 
 ## Non-empty include file.
 # RUN: echo ".data2 : { QUAD(0) } > RAM" > %t.dir/inc.script
 # RUN: ld.lld -o %t.elf --script %s %t.o -L %t.dir
-# RUN: llvm-objdump -section-headers %t.elf | FileCheck %s --check-prefix=CHECK2
+# RUN: llvm-objdump --section-headers %t.elf | FileCheck %s --check-prefix=CHECK2
 # CHECK2:      .data         00000008 0000000000002000 DATA
 # CHECK2-NEXT: .data2        00000008 0000000000002008 DATA
 # CHECK2-NEXT: .data3        00000008 0000000000002010 DATA
diff --git a/lld/test/ELF/linkerscript/sections-constraint.s b/lld/test/ELF/linkerscript/sections-constraint.s
index 4d95ec18336cc..b0dc51c9f711d 100644
--- a/lld/test/ELF/linkerscript/sections-constraint.s
+++ b/lld/test/ELF/linkerscript/sections-constraint.s
@@ -4,7 +4,7 @@
 # RUN:  .writable : ONLY_IF_RW { *(.writable) } \
 # RUN:  .readable : ONLY_IF_RO { *(.readable) }}" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | \
+# RUN: llvm-objdump --section-headers %t1 | \
 # RUN:   FileCheck -check-prefix=BASE %s
 # BASE: Sections:
 # BASE-NEXT: Idx Name          Size
@@ -17,7 +17,7 @@
 # RUN:  .writable : ONLY_IF_RW { *(.writable) } \
 # RUN:  .readable : ONLY_IF_RO { *(.readable) }}" > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t
-# RUN: llvm-objdump -section-headers %t2 | \
+# RUN: llvm-objdump --section-headers %t2 | \
 # RUN:   FileCheck -check-prefix=NO1 %s
 # NO1: Sections:
 # NO1-NEXT: Idx Name          Size
diff --git a/lld/test/ELF/linkerscript/sections-gc.s b/lld/test/ELF/linkerscript/sections-gc.s
index d71dc652511f2..10ff929132c25 100644
--- a/lld/test/ELF/linkerscript/sections-gc.s
+++ b/lld/test/ELF/linkerscript/sections-gc.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: echo "SECTIONS { .text : { *(.text*) } }" > %t.script
 # RUN: ld.lld %t --gc-sections --script %t.script -o %t1
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # CHECK:      Sections:
 # CHECK-NEXT:  Name      Size
diff --git a/lld/test/ELF/linkerscript/sections-keep.s b/lld/test/ELF/linkerscript/sections-keep.s
index 2c778e3e936b5..6532f7b93930e 100644
--- a/lld/test/ELF/linkerscript/sections-keep.s
+++ b/lld/test/ELF/linkerscript/sections-keep.s
@@ -8,7 +8,7 @@
 # RUN:  .keep : { *(.keep) } \
 # RUN:  .temp : { *(.temp) }}" > %t.script
 # RUN: ld.lld --gc-sections -o %t --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t | \
+# RUN: llvm-objdump --section-headers %t | \
 # RUN:   FileCheck -check-prefix=SECGC %s
 # SECGC:      Sections:
 # SECGC-NEXT: Idx Name          Size
@@ -22,7 +22,7 @@
 # RUN:  .keep : { KEEP(*(.keep)) } \
 # RUN:  .temp : { *(.temp) }}" > %t.script
 # RUN: ld.lld --gc-sections -o %t --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t | \
+# RUN: llvm-objdump --section-headers %t | \
 # RUN:   FileCheck -check-prefix=SECNOGC %s
 # SECNOGC:      Sections:
 # SECNOGC-NEXT: Idx Name          Size
@@ -39,7 +39,7 @@
 # RUN:  .keep : { KEEP(*(.keep)) } \
 # RUN:  .nokeep : { *(.keep) }}" > %t.script
 # RUN: ld.lld --gc-sections -o %t --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck -check-prefix=MIXED1 %s
+# RUN: llvm-objdump --section-headers %t | FileCheck --check-prefix=MIXED1 %s
 # MIXED1:      Sections:
 # MIXED1-NEXT: Idx Name          Size
 # MIXED1-NEXT:   0               00000000
@@ -60,7 +60,7 @@
 # RUN:  .nokeep : { *(.keep) } \
 # RUN:  .keep : { KEEP(*(.keep)) }}" > %t.script
 # RUN: ld.lld --gc-sections -o %t --script %t.script %t.o
-# RUN: llvm-objdump -section-headers %t | FileCheck -check-prefix=MIXED2 %s
+# RUN: llvm-objdump --section-headers %t | FileCheck --check-prefix=MIXED2 %s
 # MIXED2:      Sections:
 # MIXED2-NEXT: Idx Name          Size
 # MIXED2-NEXT:   0               00000000
@@ -78,7 +78,7 @@
 # RUN:  .keep : { KEEP(*1.o(.keep)) } \
 # RUN:  }" > %t.script
 # RUN: ld.lld --gc-sections -o %t --script %t.script %t1.o %t.o
-# RUN: llvm-objdump -s %t | FileCheck -check-prefix=FILEMATCH %s
+# RUN: llvm-objdump -s %t | FileCheck --check-prefix=FILEMATCH %s
 # FILEMATCH:        Contents of section .keep:
 # FILEMATCH-NEXT:   00e8 41414141  AAAA
 
diff --git a/lld/test/ELF/linkerscript/sections-padding.s b/lld/test/ELF/linkerscript/sections-padding.s
index 2e914626bb9f5..5ec0ddbe767a7 100644
--- a/lld/test/ELF/linkerscript/sections-padding.s
+++ b/lld/test/ELF/linkerscript/sections-padding.s
@@ -4,30 +4,30 @@
 ## Check that padding value works:
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =0x1122 }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES %s
 # YES: 66000011 22000011 22000011 22000011
 
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =0x1100+0x22 }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES2 %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES2 %s
 # YES2: 66000011 22000011 22000011 22000011
 
 ## Confirming that address was correct:
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =0x99887766 }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES3 %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES3 %s
 # YES3: 66998877 66998877 66998877 66998877
 
 ## Default padding value is 0x00:
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=NO %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=NO %s
 # NO: 66000000 00000000 00000000 00000000
 
 ## Decimal value.
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =777 }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=DEC %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=DEC %s
 # DEC: 66000003 09000003 09000003 09000003
 
 ## Invalid hex value:
@@ -39,22 +39,22 @@
 ## Check case with space between '=' and a value:
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } = 0x1122 }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES %s
 
 ## Check case with optional comma following output section command:
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =0x1122, .a : { *(.a*) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES %s
 
 ## Check we can use an artbitrary expression as a filler.
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } = ((0x11<<8) | 0x22) }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES %s
 
 ## Check case with space between '=' and expression:
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =((0x11 << 8) | 0x22) }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -s %t.out | FileCheck -check-prefix=YES %s
+# RUN: llvm-objdump -s %t.out | FileCheck --check-prefix=YES %s
 
 ## Check we report an error if expression value is larger than 32-bits.
 # RUN: echo "SECTIONS { .mysec : { *(.mysec*) } =(0x11 << 32) }" > %t.script
diff --git a/lld/test/ELF/linkerscript/sections.s b/lld/test/ELF/linkerscript/sections.s
index b1e8fb5e9a122..14a9ac5ab75bb 100644
--- a/lld/test/ELF/linkerscript/sections.s
+++ b/lld/test/ELF/linkerscript/sections.s
@@ -4,7 +4,7 @@
 # Empty SECTIONS command.
 # RUN: echo "SECTIONS {}" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | \
+# RUN: llvm-objdump --section-headers %t1 | \
 # RUN:   FileCheck -check-prefix=SEC-DEFAULT %s
 
 # SECTIONS command with the same order as default.
@@ -12,7 +12,7 @@
 # RUN:          .text : { *(.text) } \
 # RUN:          .data : { *(.data) } }" > %t.script
 # RUN: ld.lld -o %t2 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t2 | \
+# RUN: llvm-objdump --section-headers %t2 | \
 # RUN:   FileCheck -check-prefix=SEC-DEFAULT %s
 
 #             Idx Name          Size
@@ -36,7 +36,7 @@
 # RUN:          .data : { *(.data) } \
 # RUN:          .text : { *(.text) } }" > %t.script
 # RUN: ld.lld -o %t3 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t3 | \
+# RUN: llvm-objdump --section-headers %t3 | \
 # RUN:   FileCheck -check-prefix=SEC-ORDER %s
 
 #           Idx Name          Size
@@ -54,7 +54,7 @@
 # RUN:          .data : { *(.text) } \
 # RUN:          .text : { *(.data) } }" > %t.script
 # RUN: ld.lld -o %t4 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t4 | \
+# RUN: llvm-objdump --section-headers %t4 | \
 # RUN:   FileCheck -check-prefix=SEC-SWAP-NAMES %s
 
 #                Idx Name          Size
@@ -76,7 +76,7 @@
 # RUN:       SECTIONS { \
 # RUN:          .data : { *(other) } }" > %t.script
 # RUN: ld.lld -o %t6 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t6 | \
+# RUN: llvm-objdump --section-headers %t6 | \
 # RUN:   FileCheck -check-prefix=SEC-MULTI %s
 
 #           Idx Name          Size
diff --git a/lld/test/ELF/linkerscript/sort-nested.s b/lld/test/ELF/linkerscript/sort-nested.s
index fb1d1a3dd0708..51454a7681475 100644
--- a/lld/test/ELF/linkerscript/sort-nested.s
+++ b/lld/test/ELF/linkerscript/sort-nested.s
@@ -6,7 +6,7 @@
 ## Check sorting first by alignment and then by name.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.aaa.*))) } }" > %t1.script
 # RUN: ld.lld -o %t1 --script %t1.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t1 | FileCheck -check-prefix=SORTED_AN %s
+# RUN: llvm-objdump -s %t1 | FileCheck --check-prefix=SORTED_AN %s
 # SORTED_AN:      Contents of section .aaa:
 # SORTED_AN-NEXT:   01000000 00000000 00000000 00000000
 # SORTED_AN-NEXT:   11000000 00000000 00000000 00000000
@@ -16,7 +16,7 @@
 ## Check sorting first by name and then by alignment.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_NAME(SORT_BY_ALIGNMENT(.aaa.*))) } }" > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SORTED_NA %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SORTED_NA %s
 # SORTED_NA: Contents of section .aaa:
 # SORTED_NA:   01000000 00000000 00000000 00000000
 # SORTED_NA:   11000000 00000000 22000000 00000000
@@ -28,10 +28,10 @@
 ## as nested sorting command.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_ALIGNMENT(.aaa.*)) } }" > %t3.script
 # RUN: ld.lld --sort-section name -o %t3 --script %t3.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t3 | FileCheck -check-prefix=SORTED_AN %s
+# RUN: llvm-objdump -s %t3 | FileCheck --check-prefix=SORTED_AN %s
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_NAME(.aaa.*)) } }" > %t4.script
 # RUN: ld.lld --sort-section alignment -o %t4 --script %t4.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t4 | FileCheck -check-prefix=SORTED_NA %s
+# RUN: llvm-objdump -s %t4 | FileCheck --check-prefix=SORTED_NA %s
 
 .global _start
 _start:
diff --git a/lld/test/ELF/linkerscript/sort.s b/lld/test/ELF/linkerscript/sort.s
index 6390ced122892..730076044bac4 100644
--- a/lld/test/ELF/linkerscript/sort.s
+++ b/lld/test/ELF/linkerscript/sort.s
@@ -5,7 +5,7 @@
 
 # RUN: echo "SECTIONS { .aaa : { *(.aaa.*) } }" > %t1.script
 # RUN: ld.lld -o %t1 --script %t1.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t1 | FileCheck -check-prefix=UNSORTED %s
+# RUN: llvm-objdump -s %t1 | FileCheck --check-prefix=UNSORTED %s
 # UNSORTED:       Contents of section .aaa:
 # UNSORTED-NEXT:   55000000 00000000 00000000 00000000
 # UNSORTED-NEXT:   00000000 00000000 00000000 00000000
@@ -18,7 +18,7 @@
 ## Check that SORT works (sorted by name of section).
 # RUN: echo "SECTIONS { .aaa : { *(SORT(.aaa.*)) } }" > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SORTED_A %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SORTED_A %s
 # SORTED_A:      Contents of section .aaa:
 # SORTED_A-NEXT:  11000000 00000000 01000000 00000000
 # SORTED_A-NEXT:  22000000 00000000 02000000 00000000
@@ -32,7 +32,7 @@
 ## section names is stable.
 # RUN: echo "SECTIONS { .aaa : { *(SORT(.aaa.*)) } }" > %t3.script
 # RUN: ld.lld -o %t3 --script %t3.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t3 | FileCheck -check-prefix=SORTED_B %s
+# RUN: llvm-objdump -s %t3 | FileCheck --check-prefix=SORTED_B %s
 # SORTED_B:      Contents of section .aaa:
 # SORTED_B-NEXT:  01000000 00000000 00000000 00000000
 # SORTED_B-NEXT:  00000000 00000000 00000000 00000000
@@ -45,17 +45,17 @@
 ## Check that SORT surrounded with KEEP also works.
 # RUN: echo "SECTIONS { .aaa : { KEEP (*(SORT(.aaa.*))) } }" > %t3.script
 # RUN: ld.lld -o %t3 --script %t3.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t3 | FileCheck -check-prefix=SORTED_A %s
+# RUN: llvm-objdump -s %t3 | FileCheck --check-prefix=SORTED_A %s
 
 ## Check that SORT_BY_NAME works (SORT is alias).
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_NAME(.aaa.*)) } }" > %t4.script
 # RUN: ld.lld -o %t4 --script %t4.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t4 | FileCheck -check-prefix=SORTED_A %s
+# RUN: llvm-objdump -s %t4 | FileCheck --check-prefix=SORTED_A %s
 
 ## Check that sections ordered by alignment.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_ALIGNMENT(.aaa.*)) } }" > %t5.script
 # RUN: ld.lld -o %t5 --script %t5.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t5 | FileCheck -check-prefix=SORTED_ALIGNMENT %s
+# RUN: llvm-objdump -s %t5 | FileCheck --check-prefix=SORTED_ALIGNMENT %s
 # SORTED_ALIGNMENT:      Contents of section .aaa:
 # SORTED_ALIGNMENT-NEXT:  05000000 00000000 00000000 00000000
 # SORTED_ALIGNMENT-NEXT:  00000000 00000000 00000000 00000000
@@ -69,31 +69,31 @@
 ## SORT_NONE itself does not sort anything.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_NONE(.aaa.*)) } }" > %t6.script
 # RUN: ld.lld -o %t7 --script %t6.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t7 | FileCheck -check-prefix=UNSORTED %s
+# RUN: llvm-objdump -s %t7 | FileCheck --check-prefix=UNSORTED %s
 
 ## Check --sort-section alignment option.
 # RUN: echo "SECTIONS { .aaa : { *(.aaa.*) } }" > %t7.script
 # RUN: ld.lld --sort-section alignment -o %t8 --script %t7.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t8 | FileCheck -check-prefix=SORTED_ALIGNMENT %s
+# RUN: llvm-objdump -s %t8 | FileCheck --check-prefix=SORTED_ALIGNMENT %s
 
 ## Check --sort-section= form.
 # RUN: ld.lld --sort-section=alignment -o %t8_1 --script %t7.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t8_1 | FileCheck -check-prefix=SORTED_ALIGNMENT %s
+# RUN: llvm-objdump -s %t8_1 | FileCheck --check-prefix=SORTED_ALIGNMENT %s
 
 ## Check --sort-section name option.
 # RUN: echo "SECTIONS { .aaa : { *(.aaa.*) } }" > %t8.script
 # RUN: ld.lld --sort-section name -o %t9 --script %t8.script %t1.o %t2.o
-# RUN: llvm-objdump -s %t9 | FileCheck -check-prefix=SORTED_B %s
+# RUN: llvm-objdump -s %t9 | FileCheck --check-prefix=SORTED_B %s
 
 ## SORT_NONE disables the --sort-section.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_NONE(.aaa.*)) } }" > %t9.script
 # RUN: ld.lld --sort-section name -o %t10 --script %t9.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t10 | FileCheck -check-prefix=UNSORTED %s
+# RUN: llvm-objdump -s %t10 | FileCheck --check-prefix=UNSORTED %s
 
 ## SORT_NONE as a inner sort directive.
 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_NAME(SORT_NONE(.aaa.*))) } }" > %t10.script
 # RUN: ld.lld -o %t11 --script %t10.script %t2.o %t1.o
-# RUN: llvm-objdump -s %t11 | FileCheck -check-prefix=SORTED_A %s
+# RUN: llvm-objdump -s %t11 | FileCheck --check-prefix=SORTED_A %s
 
 .global _start
 _start:
diff --git a/lld/test/ELF/linkerscript/subalign.s b/lld/test/ELF/linkerscript/subalign.s
index 8d8420c0f77a9..bf812d17bb870 100644
--- a/lld/test/ELF/linkerscript/subalign.s
+++ b/lld/test/ELF/linkerscript/subalign.s
@@ -3,7 +3,7 @@
 
 # RUN: echo "SECTIONS { .aaa : { *(.aaa.*) } }" > %t1.script
 # RUN: ld.lld -o %t1 --script %t1.script %t1.o
-# RUN: llvm-objdump -s %t1 | FileCheck -check-prefix=NOALIGN %s
+# RUN: llvm-objdump -s %t1 | FileCheck --check-prefix=NOALIGN %s
 # NOALIGN:      Contents of section .aaa:
 # NOALIGN-NEXT:   01000000 00000000 00000000 00000000
 # NOALIGN-NEXT:   00000000 00000000 00000000 00000000
@@ -17,7 +17,7 @@
 
 # RUN: echo "SECTIONS { .aaa : SUBALIGN(1) { *(.aaa.*) } }" > %t2.script
 # RUN: ld.lld -o %t2 --script %t2.script %t1.o
-# RUN: llvm-objdump -s %t2 | FileCheck -check-prefix=SUBALIGN %s
+# RUN: llvm-objdump -s %t2 | FileCheck --check-prefix=SUBALIGN %s
 # SUBALIGN: Contents of section .aaa:
 # SUBALIGN:   01000000 00000000 02000000 00000000
 # SUBALIGN:   03000000 00000000 04000000 00000000
@@ -32,7 +32,7 @@
 ## Test we are able to link with zero alignment, this is consistent with bfd 2.26.1.
 # RUN: echo "SECTIONS { .aaa : SUBALIGN(0) { *(.aaa*) } }" > %t4.script
 # RUN: ld.lld %t1.o --script %t4.script -o %t4
-# RUN: llvm-objdump -s %t4 | FileCheck -check-prefix=SUBALIGN %s
+# RUN: llvm-objdump -s %t4 | FileCheck --check-prefix=SUBALIGN %s
 
 ## Test we fail gracefuly when alignment value is not a power of 2.
 # RUN: echo "SECTIONS { .aaa : SUBALIGN(3) { *(.aaa*) } }" > %t5.script
diff --git a/lld/test/ELF/linkerscript/symbol-only.test b/lld/test/ELF/linkerscript/symbol-only.test
index b8101d851ca7b..4fed3032a6cdd 100644
--- a/lld/test/ELF/linkerscript/symbol-only.test
+++ b/lld/test/ELF/linkerscript/symbol-only.test
@@ -2,7 +2,7 @@
 # RUN: echo '.section bar, "a"' \
 # RUN:   | llvm-mc -filetype=obj -triple=x86_64-unknown-linux - -o %t
 # RUN: ld.lld -o %t1 --script %s %t -shared
-# RUN: llvm-objdump -section-headers -t %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers -t %t1 | FileCheck %s
 
 SECTIONS {
   . = SIZEOF_HEADERS;
diff --git a/lld/test/ELF/linkerscript/symbols-non-alloc.test b/lld/test/ELF/linkerscript/symbols-non-alloc.test
index 19cc605530a3a..920cff96a3a26 100644
--- a/lld/test/ELF/linkerscript/symbols-non-alloc.test
+++ b/lld/test/ELF/linkerscript/symbols-non-alloc.test
@@ -2,7 +2,7 @@
 # RUN: echo '.section .nonalloc,""; .quad 0' \
 # RUN:   | llvm-mc -filetype=obj -triple=x86_64-unknown-linux - -o %t
 # RUN: ld.lld -o %t2 --script %s %t
-# RUN: llvm-objdump -section-headers -t %t2 | FileCheck %s
+# RUN: llvm-objdump --section-headers -t %t2 | FileCheck %s
 
 # CHECK: Sections:
 # CHECK:  .nonalloc     00000008 0000000000000000
diff --git a/lld/test/ELF/linkerscript/unused-synthetic.s b/lld/test/ELF/linkerscript/unused-synthetic.s
index de494fa4975fe..9419917484afa 100644
--- a/lld/test/ELF/linkerscript/unused-synthetic.s
+++ b/lld/test/ELF/linkerscript/unused-synthetic.s
@@ -20,7 +20,7 @@
 # RUN:    .got.plt : { a_sym = .; *(.got.plt) } \
 # RUN:  }" > %t2.script
 # RUN: ld.lld -shared -o %t2.so --script %t2.script %t.o
-# RUN: llvm-objdump -section-headers %t2.so | FileCheck %s --check-prefix=CHECK2
+# RUN: llvm-objdump --section-headers %t2.so | FileCheck %s --check-prefix=CHECK2
 # CHECK2: .got.plt 00000000
 
 .global _start
diff --git a/lld/test/ELF/linkerscript/unused-synthetic2.test b/lld/test/ELF/linkerscript/unused-synthetic2.test
index 755d1af00be0f..f2355b86786ab 100644
--- a/lld/test/ELF/linkerscript/unused-synthetic2.test
+++ b/lld/test/ELF/linkerscript/unused-synthetic2.test
@@ -4,7 +4,7 @@
 ## We incorrectly removed unused synthetic sections and crashed before.
 ## Check we do not crash and do not produce .trap output section.
 # RUN: ld.lld -shared -o %t.so --script %s %t.o
-# RUN: llvm-objdump -section-headers %t.so | FileCheck %s
+# RUN: llvm-objdump --section-headers %t.so | FileCheck %s
 # CHECK-NOT: .trap
 
 SECTIONS {
diff --git a/lld/test/ELF/linkerscript/va.s b/lld/test/ELF/linkerscript/va.s
index bbf55cb45b35e..c59cb794b5858 100644
--- a/lld/test/ELF/linkerscript/va.s
+++ b/lld/test/ELF/linkerscript/va.s
@@ -3,7 +3,7 @@
 
 # RUN: echo "SECTIONS {}" > %t.script
 # RUN: ld.lld -o %t1 --script %t.script %t
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 # CHECK:      Sections:
 # CHECK-NEXT: Idx Name          Size     VMA
 # CHECK-NEXT:   0               00000000 0000000000000000
diff --git a/lld/test/ELF/linkerscript/wildcards.s b/lld/test/ELF/linkerscript/wildcards.s
index 4e9469e407737..43533564c081b 100644
--- a/lld/test/ELF/linkerscript/wildcards.s
+++ b/lld/test/ELF/linkerscript/wildcards.s
@@ -5,7 +5,7 @@
 # RUN: echo "SECTIONS { \
 # RUN:      .text : { *(.abc .abx) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck -check-prefix=SEC-DEFAULT %s
 # SEC-DEFAULT:      Sections:
 # SEC-DEFAULT-NEXT: Idx Name          Size
@@ -23,14 +23,14 @@
 # RUN: echo "SECTIONS { \
 # RUN:      .text : { *(.abc .ab?) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck -check-prefix=SEC-DEFAULT %s
 
 ## Now see how replacing '?' with '*' will consume whole abcd.
 # RUN: echo "SECTIONS { \
 # RUN:      .text : { *(.abc .ab*) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck -check-prefix=SEC-ALL %s
 # SEC-ALL:      Sections:
 # SEC-ALL-NEXT: Idx Name          Size
@@ -47,7 +47,7 @@
 # RUN: echo "SECTIONS { \
 # RUN:      .text : { *(.a*) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck -check-prefix=SEC-NO %s
 # SEC-NO: Sections:
 # SEC-NO-NEXT: Idx Name          Size
diff --git a/lld/test/ELF/linkerscript/wildcards2.s b/lld/test/ELF/linkerscript/wildcards2.s
index 5e8d6a3d309a1..65386e5ad7df7 100644
--- a/lld/test/ELF/linkerscript/wildcards2.s
+++ b/lld/test/ELF/linkerscript/wildcards2.s
@@ -5,7 +5,7 @@
 # RUN: echo "SECTIONS { \
 # RUN:      .text : { *(.abc) } }" > %t.script
 # RUN: ld.lld -o %t.out --script %t.script %t
-# RUN: llvm-objdump -section-headers %t.out | \
+# RUN: llvm-objdump --section-headers %t.out | \
 # RUN:   FileCheck %s
 # CHECK:      Sections:
 # CHECK-NEXT:  Idx Name          Size
diff --git a/lld/test/ELF/lto/cpu-string.ll b/lld/test/ELF/lto/cpu-string.ll
index 66af4a1c2daa8..3697cbd6d9472 100644
--- a/lld/test/ELF/lto/cpu-string.ll
+++ b/lld/test/ELF/lto/cpu-string.ll
@@ -2,16 +2,16 @@
 ; RUN: llvm-as %s -o %t.o
 
 ; RUN: ld.lld %t.o -o %t.so -shared
-; RUN: llvm-objdump -d -section=".text" -no-leading-addr -no-show-raw-insn %t.so | FileCheck %s
+; RUN: llvm-objdump -d --section=".text" --no-leading-addr --no-show-raw-insn %t.so | FileCheck %s
 ; CHECK: nop{{$}}
 
 ; RUN: ld.lld -mllvm -mcpu=znver1 %t.o -o %t.znver1.so -shared
-; RUN: llvm-objdump -d -section=".text" -no-leading-addr -no-show-raw-insn %t.znver1.so | FileCheck -check-prefix=ZNVER1 %s
+; RUN: llvm-objdump -d --section=".text" --no-leading-addr --no-show-raw-insn %t.znver1.so | FileCheck --check-prefix=ZNVER1 %s
 ; ZNVER1: nopw
 
 ; Check we are able to use -plugin-opt=mcpu=<CPU> to set CPU string.
 ; RUN: ld.lld -plugin-opt=mcpu=znver1 %t.o -o %t.znver1.so -shared
-; RUN: llvm-objdump -d -section=".text" -no-leading-addr -no-show-raw-insn %t.znver1.so | FileCheck -check-prefix=ZNVER1 %s
+; RUN: llvm-objdump -d --section=".text" --no-leading-addr --no-show-raw-insn %t.znver1.so | FileCheck --check-prefix=ZNVER1 %s
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/lld/test/ELF/lto/lto-start.ll b/lld/test/ELF/lto/lto-start.ll
index e39c35f17e072..541f15b3a9883 100644
--- a/lld/test/ELF/lto/lto-start.ll
+++ b/lld/test/ELF/lto/lto-start.ll
@@ -3,7 +3,7 @@
 ; RUN: ld.lld %t.o -o %t2
 ; RUN: llvm-readobj --symbols %t2 | FileCheck %s
 
-; CHECK:      Format: ELF64-x86-64
+; CHECK:      Format: elf64-x86-64
 ; CHECK-NEXT: Arch: x86_64
 ; CHECK-NEXT: AddressSize: 64bit
 
diff --git a/lld/test/ELF/lto/obj-path.ll b/lld/test/ELF/lto/obj-path.ll
index 07e30e2a500f7..1fbffe7932fe2 100644
--- a/lld/test/ELF/lto/obj-path.ll
+++ b/lld/test/ELF/lto/obj-path.ll
@@ -16,10 +16,10 @@
 ; CHECK-NEXT: T g
 
 ; NM1: T f
-; ELF1: Format: ELF64-x86-64
+; ELF1: Format: elf64-x86-64
 
 ; NM2: T g
-; ELF2: Format: ELF64-x86-64
+; ELF2: Format: elf64-x86-64
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/lld/test/ELF/lto/thinlto-debug-fission.ll b/lld/test/ELF/lto/thinlto-debug-fission.ll
index 64da345d7af02..3b471dc20e11d 100644
--- a/lld/test/ELF/lto/thinlto-debug-fission.ll
+++ b/lld/test/ELF/lto/thinlto-debug-fission.ll
@@ -7,7 +7,7 @@
 ; RUN: ld.lld --plugin-opt=dwo_dir=%t.dir -shared %t1.o -o /dev/null
 ; RUN: llvm-readobj -h %t.dir/0.dwo | FileCheck %s
 
-; CHECK: Format: ELF64-x86-64
+; CHECK: Format: elf64-x86-64
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/lld/test/ELF/lto/thinlto-obj-path.ll b/lld/test/ELF/lto/thinlto-obj-path.ll
index 52338f9df375a..787c1c03b6651 100644
--- a/lld/test/ELF/lto/thinlto-obj-path.ll
+++ b/lld/test/ELF/lto/thinlto-obj-path.ll
@@ -14,7 +14,7 @@
 ; RUN: ld.lld -thinlto-index-only -lto-obj-path=%t4.o -shared %t1.o %t2.o -o /dev/null
 ; RUN: llvm-readobj -h %t4.o | FileCheck %s
 
-; CHECK: Format: ELF64-x86-64
+; CHECK: Format: elf64-x86-64
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/lld/test/ELF/mips-32.s b/lld/test/ELF/mips-32.s
index af9db0108dadc..0a19700fb3dac 100644
--- a/lld/test/ELF/mips-32.s
+++ b/lld/test/ELF/mips-32.s
@@ -7,13 +7,13 @@
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t-be.o
 # RUN: ld.lld -shared %t-be.o -script %t.script -o %t-be.so
-# RUN: llvm-objdump -t -s %t-be.so | FileCheck -check-prefixes=SYM,BE %s
+# RUN: llvm-objdump -t -s %t-be.so | FileCheck --check-prefixes=SYM,BE %s
 # RUN: llvm-readelf -r -s --dynamic-table -A %t-be.so \
 # RUN:   | FileCheck -check-prefix=REL %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux %s -o %t-el.o
 # RUN: ld.lld -shared %t-el.o -script %t.script -o %t-el.so
-# RUN: llvm-objdump -t -s %t-el.so | FileCheck -check-prefixes=SYM,EL %s
+# RUN: llvm-objdump -t -s %t-el.so | FileCheck --check-prefixes=SYM,EL %s
 # RUN: llvm-readelf --dynamic-table -r -s -A %t-el.so \
 # RUN:   | FileCheck -check-prefix=REL %s
 
diff --git a/lld/test/ELF/mips-64.s b/lld/test/ELF/mips-64.s
index 45a88ea968d99..8c135b598413e 100644
--- a/lld/test/ELF/mips-64.s
+++ b/lld/test/ELF/mips-64.s
@@ -3,7 +3,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux %s -o %t.o
 # RUN: ld.lld -shared %t.o -o %t.so
-# RUN: llvm-objdump -s -t %t.so | FileCheck -check-prefix=SYM %s
+# RUN: llvm-objdump -s -t %t.so | FileCheck --check-prefix=SYM %s
 # RUN: llvm-readelf --dynamic-table -r -s -A %t.so | FileCheck %s
 
   .data
diff --git a/lld/test/ELF/mips-got-relocs.s b/lld/test/ELF/mips-got-relocs.s
index 6e3e4b371d3b9..f2667b831b199 100644
--- a/lld/test/ELF/mips-got-relocs.s
+++ b/lld/test/ELF/mips-got-relocs.s
@@ -10,23 +10,23 @@
 # RUN: ld.lld %t-be.o --script %t.script -o %t-be.exe
 # RUN: llvm-readobj --sections -r --symbols -A %t-be.exe \
 # RUN:   | FileCheck -check-prefix=ELF %s
-# RUN: llvm-objdump -d %t-be.exe | FileCheck -check-prefix=DIS %s
+# RUN: llvm-objdump -d %t-be.exe | FileCheck --check-prefix=DIS %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux %s -o %t-el.o
 # RUN: ld.lld %t-el.o --script %t.script -o %t-el.exe
 # RUN: llvm-readobj --sections -r --symbols -A %t-el.exe \
 # RUN:   | FileCheck -check-prefix=ELF %s
-# RUN: llvm-objdump -d %t-el.exe | FileCheck -check-prefix=DIS %s
+# RUN: llvm-objdump -d %t-el.exe | FileCheck --check-prefix=DIS %s
 
 # RUN: ld.lld -shared %t-be.o --script %t.script -o %t-be.so
 # RUN: llvm-readobj --sections -r --symbols -A %t-be.so \
 # RUN:   | FileCheck -check-prefix=ELF %s
-# RUN: llvm-objdump -d %t-be.so | FileCheck -check-prefix=DIS %s
+# RUN: llvm-objdump -d %t-be.so | FileCheck --check-prefix=DIS %s
 
 # RUN: ld.lld -shared %t-el.o --script %t.script -o %t-el.so
 # RUN: llvm-readobj --sections -r --symbols -A %t-el.so \
 # RUN:   | FileCheck -check-prefix=ELF %s
-# RUN: llvm-objdump -d %t-el.so | FileCheck -check-prefix=DIS %s
+# RUN: llvm-objdump -d %t-el.so | FileCheck --check-prefix=DIS %s
 
   .text
   .globl  __start
diff --git a/lld/test/ELF/mips-got16-relocatable.s b/lld/test/ELF/mips-got16-relocatable.s
index 046038664b7de..a7ff1793beadd 100644
--- a/lld/test/ELF/mips-got16-relocatable.s
+++ b/lld/test/ELF/mips-got16-relocatable.s
@@ -4,7 +4,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -o %t.o %s
 # RUN: ld.lld -r -o %t %t.o %t.o
-# RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck -check-prefix=OBJ %s
+# RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck --check-prefix=OBJ %s
 # RUN: ld.lld -shared -o %t.so %t
 # RUN: llvm-objdump -d -t --print-imm-hex --no-show-raw-insn %t.so \
 # RUN:   | FileCheck -check-prefix=SO %s
diff --git a/lld/test/ELF/mips-gp-disp.s b/lld/test/ELF/mips-gp-disp.s
index db0f3018129cc..b05761eb4a481 100644
--- a/lld/test/ELF/mips-gp-disp.s
+++ b/lld/test/ELF/mips-gp-disp.s
@@ -11,7 +11,7 @@
 # RUN: llvm-readelf --symbols %t.so | FileCheck -check-prefix=INT-SO %s
 # RUN: llvm-readelf --symbols %S/Inputs/mips-gp-disp.so \
 # RUN:   | FileCheck -check-prefix=EXT-SO %s
-# RUN: llvm-objdump -d -t --no-show-raw-insn %t.so | FileCheck -check-prefix=DIS %s
+# RUN: llvm-objdump -d -t --no-show-raw-insn %t.so | FileCheck --check-prefix=DIS %s
 # RUN: llvm-readelf -r %t.so | FileCheck -check-prefix=REL %s
 
 # INT-SO: 00000000     0 NOTYPE  LOCAL  HIDDEN   ABS _gp_disp
diff --git a/lld/test/ELF/mips-gprel32-relocs.s b/lld/test/ELF/mips-gprel32-relocs.s
index 4087d306dde89..e11bf334a69ba 100644
--- a/lld/test/ELF/mips-gprel32-relocs.s
+++ b/lld/test/ELF/mips-gprel32-relocs.s
@@ -7,7 +7,7 @@
 # RUN:         . = 0x20000; .text :  { *(.text) } \
 # RUN:       }" > %t.script
 # RUN: ld.lld -shared --script %t.script -o %t.so %t.o
-# RUN: llvm-objdump -s -section=.rodata -t %t.so | FileCheck %s
+# RUN: llvm-objdump -s --section=.rodata -t %t.so | FileCheck %s
 
   .text
   .globl  __start
diff --git a/lld/test/ELF/mips-jalr.s b/lld/test/ELF/mips-jalr.s
index 5b3d3967aedee..87a64b258c197 100644
--- a/lld/test/ELF/mips-jalr.s
+++ b/lld/test/ELF/mips-jalr.s
@@ -6,10 +6,10 @@
 # RUN: llvm-readelf -r %t.o | FileCheck -check-prefix=REL %s
 
 # RUN: ld.lld %t.o -shared -o %t.so
-# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=SO %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=SO %s
 
 # RUN: ld.lld %t.o --defsym=bar=__start -o %t.so
-# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=EXE %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=EXE %s
 
 # REL: R_MIPS_JALR   {{.*}} bar
 # REL: R_MIPS_JALR   {{.*}} foo
diff --git a/lld/test/ELF/mips-mgot.s b/lld/test/ELF/mips-mgot.s
index 597517cca2a33..610704f06631f 100644
--- a/lld/test/ELF/mips-mgot.s
+++ b/lld/test/ELF/mips-mgot.s
@@ -11,7 +11,7 @@
 # RUN:         . = 0x70000; .got  : { *(.got)  } \
 # RUN:       }" > %t.script
 # RUN: ld.lld -shared -mips-got-size 52 --script %t.script %t0.o %t1.o %t2.o -o %t.so
-# RUN: llvm-objdump -s -section=.got -t %t.so | FileCheck %s
+# RUN: llvm-objdump -s --section=.got -t %t.so | FileCheck %s
 # RUN: llvm-readobj -r --dyn-syms -A %t.so | FileCheck -check-prefix=GOT %s
 
 # CHECK: SYMBOL TABLE:
diff --git a/lld/test/ELF/mips-micro-cross-calls.s b/lld/test/ELF/mips-micro-cross-calls.s
index deca0ae1934c9..46f9b15d78217 100644
--- a/lld/test/ELF/mips-micro-cross-calls.s
+++ b/lld/test/ELF/mips-micro-cross-calls.s
@@ -7,10 +7,10 @@
 # RUN:         -position-independent -mattr=micromips \
 # RUN:         %S/Inputs/mips-micro.s -o %t-eb-pic.o
 # RUN: ld.lld -o %t-eb.exe %t-eb.o %t-eb-pic.o
-# RUN: llvm-objdump -d -t -mattr=-micromips \
+# RUN: llvm-objdump -d -t --mattr=-micromips \
 # RUN:              --no-show-raw-insn --print-imm-hex %t-eb.exe \
 # RUN:   | FileCheck --check-prefixes=SYM,REG %s
-# RUN: llvm-objdump -d -t -mattr=+micromips \
+# RUN: llvm-objdump -d -t --mattr=+micromips \
 # RUN:              --no-show-raw-insn --print-imm-hex %t-eb.exe \
 # RUN:   | FileCheck --check-prefixes=SYM,MICRO %s
 
diff --git a/lld/test/ELF/mips-micro-jal.s b/lld/test/ELF/mips-micro-jal.s
index 987b5f6c336bb..14267695d9165 100644
--- a/lld/test/ELF/mips-micro-jal.s
+++ b/lld/test/ELF/mips-micro-jal.s
@@ -12,7 +12,7 @@
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2eb.o
 # RUN: ld.lld --script %t.script -o %teb.exe %t2eb.o %teb.so
-# RUN: llvm-objdump -d -mattr=micromips --no-show-raw-insn %teb.exe \
+# RUN: llvm-objdump -d --mattr=micromips --no-show-raw-insn %teb.exe \
 # RUN:   | FileCheck --check-prefix=R2 %s
 # RUN: llvm-readelf -A %teb.exe | FileCheck --check-prefix=PLT %s
 
@@ -22,7 +22,7 @@
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2el.o
 # RUN: ld.lld --script %t.script -o %tel.exe %t2el.o %tel.so
-# RUN: llvm-objdump -d -mattr=micromips --no-show-raw-insn %tel.exe \
+# RUN: llvm-objdump -d --mattr=micromips --no-show-raw-insn %tel.exe \
 # RUN:   | FileCheck --check-prefix=R2 %s
 # RUN: llvm-readelf -A %tel.exe | FileCheck --check-prefix=PLT %s
 
@@ -32,7 +32,7 @@
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips -mcpu=mips32r6 %s -o %t2eb.o
 # RUN: ld.lld --script %t.script -o %teb.exe %t2eb.o %teb.so
-# RUN: llvm-objdump -d -mattr=micromips %teb.exe --no-show-raw-insn \
+# RUN: llvm-objdump -d --mattr=micromips %teb.exe --no-show-raw-insn \
 # RUN: | FileCheck --check-prefix=R6 %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
@@ -41,7 +41,7 @@
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips -mcpu=mips32r6 %s -o %t2el.o
 # RUN: ld.lld --script %t.script -o %tel.exe %t2el.o %tel.so
-# RUN: llvm-objdump -d -mattr=micromips --no-show-raw-insn %tel.exe \
+# RUN: llvm-objdump -d --mattr=micromips --no-show-raw-insn %tel.exe \
 # RUN:   | FileCheck --check-prefix=R6 %s
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
@@ -51,8 +51,8 @@
 # RUN:         %S/Inputs/mips-fpic.s -o %t-reg.o
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2eb.o
-# RUN: ld.lld --script %t.script --no-threads -o %teb.exe %t-reg.o %t2eb.o %teb.so
-# RUN: llvm-objdump -d -mattr=micromips --no-show-raw-insn %teb.exe \
+# RUN: ld.lld --script %t.script -o %teb.exe %t-reg.o %t2eb.o %teb.so
+# RUN: llvm-objdump -d --mattr=micromips --no-show-raw-insn %teb.exe \
 # RUN:   | FileCheck --check-prefix=R2 %s
 
 # R2:      .plt:
diff --git a/lld/test/ELF/mips-micro-plt.s b/lld/test/ELF/mips-micro-plt.s
index f491190f2a3aa..bf6a9dcfc65df 100644
--- a/lld/test/ELF/mips-micro-plt.s
+++ b/lld/test/ELF/mips-micro-plt.s
@@ -12,7 +12,7 @@
 # RUN:       }" > %t.script
 # RUN: ld.lld %t-exe.o %t.so --script %t.script -o %t.exe
 # RUN: llvm-readelf --symbols --dyn-syms -A %t.exe | FileCheck %s
-# RUN: llvm-objdump -d -mattr=micromips --no-show-raw-insn %t.exe \
+# RUN: llvm-objdump -d --mattr=micromips --no-show-raw-insn %t.exe \
 # RUN:   | FileCheck --check-prefix=ASM %s
 
 # CHECK: Symbol table '.dynsym'
diff --git a/lld/test/ELF/mips-micro-relocs.s b/lld/test/ELF/mips-micro-relocs.s
index e72fafb80585d..1a6853baf81fb 100644
--- a/lld/test/ELF/mips-micro-relocs.s
+++ b/lld/test/ELF/mips-micro-relocs.s
@@ -12,7 +12,7 @@
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2eb.o
 # RUN: ld.lld -o %teb.exe -script %t.script %t1eb.o %t2eb.o
-# RUN: llvm-objdump -d -t -s -mattr=micromips --no-show-raw-insn %teb.exe \
+# RUN: llvm-objdump -d -t -s --mattr=micromips --no-show-raw-insn %teb.exe \
 # RUN:   | FileCheck --check-prefixes=ASM,EB %s
 # RUN: llvm-readelf -h %teb.exe | FileCheck --check-prefix=ELF %s
 
@@ -21,7 +21,7 @@
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2el.o
 # RUN: ld.lld -o %tel.exe -script %t.script %t1el.o %t2el.o
-# RUN: llvm-objdump -d -t -s -mattr=micromips --no-show-raw-insn %tel.exe \
+# RUN: llvm-objdump -d -t -s --mattr=micromips --no-show-raw-insn %tel.exe \
 # RUN:   | FileCheck --check-prefixes=ASM,EL %s
 # RUN: llvm-readelf -h %tel.exe | FileCheck --check-prefix=ELF %s
 
diff --git a/lld/test/ELF/mips-micro-thunks.s b/lld/test/ELF/mips-micro-thunks.s
index 733cef87bbbf1..80d62931d6198 100644
--- a/lld/test/ELF/mips-micro-thunks.s
+++ b/lld/test/ELF/mips-micro-thunks.s
@@ -11,7 +11,7 @@
 # RUN:         -position-independent -mcpu=mips32r2 -mattr=micromips \
 # RUN:         %S/Inputs/mips-micro.s -o %t-eb-pic.o
 # RUN: ld.lld -o %t-eb.exe -script %t.script %t-eb.o %t-eb-pic.o
-# RUN: llvm-objdump -d -mattr=+micromips --no-show-raw-insn %t-eb.exe \
+# RUN: llvm-objdump -d --mattr=+micromips --no-show-raw-insn %t-eb.exe \
 # RUN:   | FileCheck --check-prefix=R2 %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
@@ -20,7 +20,7 @@
 # RUN:         -position-independent -mcpu=mips32r2 -mattr=micromips \
 # RUN:         %S/Inputs/mips-micro.s -o %t-el-pic.o
 # RUN: ld.lld -o %t-el.exe -script %t.script %t-el.o %t-el-pic.o
-# RUN: llvm-objdump -d -mattr=+micromips --no-show-raw-insn %t-el.exe \
+# RUN: llvm-objdump -d --mattr=+micromips --no-show-raw-insn %t-el.exe \
 # RUN:   | FileCheck --check-prefix=R2 %s
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
@@ -29,7 +29,7 @@
 # RUN:         -position-independent -mcpu=mips32r6 -mattr=micromips \
 # RUN:         %S/Inputs/mips-micro.s -o %t-eb-pic-r6.o
 # RUN: ld.lld -o %t-eb-r6.exe -script %t.script %t-eb-r6.o %t-eb-pic-r6.o
-# RUN: llvm-objdump -d -mattr=+micromips --no-show-raw-insn %t-eb-r6.exe \
+# RUN: llvm-objdump -d --mattr=+micromips --no-show-raw-insn %t-eb-r6.exe \
 # RUN:   | FileCheck --check-prefix=R6 %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
@@ -38,7 +38,7 @@
 # RUN:         -position-independent -mcpu=mips32r6 -mattr=micromips \
 # RUN:         %S/Inputs/mips-micro.s -o %t-el-pic-r6.o
 # RUN: ld.lld -o %t-el-r6.exe -script %t.script %t-el-r6.o %t-el-pic-r6.o
-# RUN: llvm-objdump -d -mattr=+micromips --no-show-raw-insn %t-el-r6.exe \
+# RUN: llvm-objdump -d --mattr=+micromips --no-show-raw-insn %t-el-r6.exe \
 # RUN:   | FileCheck --check-prefix=R6 %s
 
 # R2: <__start>:
diff --git a/lld/test/ELF/mips-micror6-relocs.s b/lld/test/ELF/mips-micror6-relocs.s
index 7497f1306e1ea..36fd3aa2b5679 100644
--- a/lld/test/ELF/mips-micror6-relocs.s
+++ b/lld/test/ELF/mips-micror6-relocs.s
@@ -10,14 +10,14 @@
 # RUN:         %S/Inputs/mips-micro.s -o %t1eb.o
 # RUN: llvm-mc -filetype=obj -triple=mips -mcpu=mips32r6 %s -o %t2eb.o
 # RUN: ld.lld -o %teb.exe -script %t.script %t1eb.o %t2eb.o
-# RUN: llvm-objdump -d -t -mattr=micromips --no-show-raw-insn %teb.exe \
+# RUN: llvm-objdump -d -t --mattr=micromips --no-show-raw-insn %teb.exe \
 # RUN:   | FileCheck %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel -mcpu=mips32r6 \
 # RUN:         %S/Inputs/mips-micro.s -o %t1el.o
 # RUN: llvm-mc -filetype=obj -triple=mipsel -mcpu=mips32r6 %s -o %t2el.o
 # RUN: ld.lld -o %tel.exe -script %t.script %t1el.o %t2el.o
-# RUN: llvm-objdump -d -t -mattr=micromips --no-show-raw-insn %tel.exe \
+# RUN: llvm-objdump -d -t --mattr=micromips --no-show-raw-insn %tel.exe \
 # RUN:   | FileCheck %s
 
 # CHECK: 00020100 g F     .text  00000000 0x80 foo
diff --git a/lld/test/ELF/mips-npic-call-pic-script.s b/lld/test/ELF/mips-npic-call-pic-script.s
index ff5a582afb136..0ce1bfe947795 100644
--- a/lld/test/ELF/mips-npic-call-pic-script.s
+++ b/lld/test/ELF/mips-npic-call-pic-script.s
@@ -82,7 +82,7 @@ __start:
 # .text.2 sections will be added to .text
 # RUN: echo "SECTIONS { .text 0x20000 : { *(.text) }  }" > %t2.script
 # RUN: ld.lld --script %t2.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t2.exe
-# RUN: llvm-objdump -d --no-show-raw-insn %t2.exe | FileCheck -check-prefix=ORPH1 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t2.exe | FileCheck --check-prefix=ORPH1 %s
 
 # ORPH1: Disassembly of section .text:
 # ORPH1-EMPTY:
@@ -143,7 +143,7 @@ __start:
 # .text.2 sections will form a new OutputSection .text
 # RUN: echo "SECTIONS { .out 0x20000 : { *(.text) }  }" > %t3.script
 # RUN: ld.lld --script %t3.script %t-npic.o %t-pic.o %t-sto-pic.o -o %t3.exe
-# RUN: llvm-objdump -d --no-show-raw-insn %t3.exe | FileCheck -check-prefix=ORPH2 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t3.exe | FileCheck --check-prefix=ORPH2 %s
 
 # ORPH2: Disassembly of section .out:
 # ORPH2-EMPTY:
diff --git a/lld/test/ELF/mips-pc-relocs.s b/lld/test/ELF/mips-pc-relocs.s
index 15d7291338025..72dcee6f74584 100644
--- a/lld/test/ELF/mips-pc-relocs.s
+++ b/lld/test/ELF/mips-pc-relocs.s
@@ -10,7 +10,7 @@
 # RUN:         . = 0x30000; .data                : { *(.data) } \
 # RUN:       }" > %t.script
 # RUN: ld.lld %t1.o %t2.o -script %t.script -o %t.exe
-# RUN: llvm-objdump -mcpu=mips32r6 -d -t -s --no-show-raw-insn %t.exe \
+# RUN: llvm-objdump --mcpu=mips32r6 -d -t -s --no-show-raw-insn %t.exe \
 # RUN:   | FileCheck %s
 
   .text
diff --git a/lld/test/ELF/mips-tls-64-pic-local-variable.s b/lld/test/ELF/mips-tls-64-pic-local-variable.s
index b482458731619..c80464f5cdc9f 100644
--- a/lld/test/ELF/mips-tls-64-pic-local-variable.s
+++ b/lld/test/ELF/mips-tls-64-pic-local-variable.s
@@ -12,7 +12,7 @@
 # RUN:         . = 0x20000; .got  : { *(.got)  } \
 # RUN:       }" > %t.script1
 # RUN: ld.lld --version-script %t.script -script %t.script1 -shared %t.o -o %t.so
-# RUN: llvm-objdump --section=.got -s %t.so | FileCheck %s -check-prefix GOT
+# RUN: llvm-objdump --section=.got -s %t.so | FileCheck %s --check-prefix GOT
 # RUN: llvm-readobj -r %t.so | FileCheck %s -check-prefix RELOCS
 
 # GOT:        Contents of section .got:
diff --git a/lld/test/ELF/mips-tls-hilo.s b/lld/test/ELF/mips-tls-hilo.s
index f37a3118d0abe..4f1417d295258 100644
--- a/lld/test/ELF/mips-tls-hilo.s
+++ b/lld/test/ELF/mips-tls-hilo.s
@@ -4,7 +4,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t.exe
-# RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck -check-prefix=DIS %s
+# RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck --check-prefix=DIS %s
 # RUN: llvm-readobj -r -A %t.exe | FileCheck %s
 
 # RUN: ld.lld %t.o -shared -o %t.so
diff --git a/lld/test/ELF/non-alloc-link-order-gc.s b/lld/test/ELF/non-alloc-link-order-gc.s
index 6012a60642639..c4a1ce65a9b28 100644
--- a/lld/test/ELF/non-alloc-link-order-gc.s
+++ b/lld/test/ELF/non-alloc-link-order-gc.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t1 --gc-sections
-# RUN: llvm-objdump -section-headers -D %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers -D %t1 | FileCheck %s
 
 ## Check that we are able to GC non-allocatable metadata sections without crash.
 
diff --git a/lld/test/ELF/ppc64-local-entry.s b/lld/test/ELF/ppc64-local-entry.s
index 2a2295169b958..62a71b68555f8 100644
--- a/lld/test/ELF/ppc64-local-entry.s
+++ b/lld/test/ELF/ppc64-local-entry.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64 %s -o %t
 # RUN: ld.lld -r %t -o %t2
-# RUN: llvm-objdump -s -section=.symtab %t2 | FileCheck %s
+# RUN: llvm-objdump -s --section=.symtab %t2 | FileCheck %s
 
 .text
 .abiversion 2
diff --git a/lld/test/ELF/ppc64-split-stack-adjust-size-success.s b/lld/test/ELF/ppc64-split-stack-adjust-size-success.s
index ee8596884457b..63e0b414dc09a 100644
--- a/lld/test/ELF/ppc64-split-stack-adjust-size-success.s
+++ b/lld/test/ELF/ppc64-split-stack-adjust-size-success.s
@@ -6,9 +6,9 @@
 # RUN: ld.lld %t1.o %t2.o -o %t --defsym __morestack=0x10010000 -split-stack-adjust-size 32768
 # RUN: llvm-objdump -d %t | FileCheck %s
 # RUN: ld.lld %t1.o %t2.o -o %t --defsym __morestack=0x10010000 -split-stack-adjust-size 4096
-# RUN: llvm-objdump -d %t | FileCheck %s -check-prefix=SMALL
+# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=SMALL
 # RUN: ld.lld %t1.o %t2.o -o %t --defsym __morestack=0x10010000 -split-stack-adjust-size 0
-# RUN: llvm-objdump -d %t | FileCheck %s -check-prefix=ZERO
+# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=ZERO
 # RUN: not ld.lld %t1.o %t2.o -o /dev/null -split-stack-adjust-size -1 2>&1 | FileCheck %s -check-prefix=ERR
 # ERR: error: --split-stack-adjust-size: size must be >= 0
 
@@ -18,9 +18,9 @@
 # RUN: ld.lld %t1.o %t2.o -o %t --defsym __morestack=0x10010000 -split-stack-adjust-size 32768
 # RUN: llvm-objdump -d %t | FileCheck %s
 # RUN: ld.lld %t1.o %t2.o -o %t --defsym __morestack=0x10010000 -split-stack-adjust-size 4096
-# RUN: llvm-objdump -d %t | FileCheck %s -check-prefix=SMALL
+# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=SMALL
 # RUN: ld.lld %t1.o %t2.o -o %t --defsym __morestack=0x10010000 -split-stack-adjust-size 0
-# RUN: llvm-objdump -d %t | FileCheck %s -check-prefix=ZERO
+# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=ZERO
         .p2align    2
         .global caller
         .type caller, @function
diff --git a/lld/test/ELF/pr37735.s b/lld/test/ELF/pr37735.s
index 7e25d1b6f4df8..a9d188a58d6ed 100644
--- a/lld/test/ELF/pr37735.s
+++ b/lld/test/ELF/pr37735.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=i386-pc-linux-gnu %s -o %t.o
 # RUN: ld.lld -r %t.o %t.o -o %t1.o
-# RUN: llvm-objdump -s -section=.bar %t1.o | FileCheck %s
+# RUN: llvm-objdump -s --section=.bar %t1.o | FileCheck %s
 
 .section .foo
 	.byte 0
diff --git a/lld/test/ELF/relocatable-empty-archive.s b/lld/test/ELF/relocatable-empty-archive.s
index 30a711af5509d..9286f9d79fb0b 100644
--- a/lld/test/ELF/relocatable-empty-archive.s
+++ b/lld/test/ELF/relocatable-empty-archive.s
@@ -4,7 +4,7 @@
 # RUN: ld.lld -m elf_x86_64 %t.a -o %t -r
 # RUN: llvm-readobj --file-headers %t | FileCheck %s
 
-# CHECK: Format: ELF64-x86-64
+# CHECK: Format: elf64-x86-64
 # CHECK: Arch: x86_64
 # CHECK: AddressSize: 64bit
 # CHECK: Type: Relocatable
diff --git a/lld/test/ELF/relocatable-sections.s b/lld/test/ELF/relocatable-sections.s
index 75ede137293c4..5d36d91b244f7 100644
--- a/lld/test/ELF/relocatable-sections.s
+++ b/lld/test/ELF/relocatable-sections.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o
 # RUN: ld.lld -r %t1.o -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 # CHECK:      .text
 # CHECK-NEXT: .rela.text
diff --git a/lld/test/ELF/relocatable-symbols.s b/lld/test/ELF/relocatable-symbols.s
index 37dc1952d9cc8..fd49f7d06a5e5 100644
--- a/lld/test/ELF/relocatable-symbols.s
+++ b/lld/test/ELF/relocatable-symbols.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 # RUN: ld.lld -r %t -o %tout
-# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
+# RUN: llvm-objdump -d %tout | FileCheck --check-prefix=DISASM %s
 # RUN: llvm-readobj -r %t | FileCheck -check-prefix=RELOC %s
 # RUN: llvm-readobj --symbols -r %tout | FileCheck -check-prefix=SYMBOL %s
 
diff --git a/lld/test/ELF/relocatable.s b/lld/test/ELF/relocatable.s
index 5811b14361cb5..04516df45cf8b 100644
--- a/lld/test/ELF/relocatable.s
+++ b/lld/test/ELF/relocatable.s
@@ -4,13 +4,13 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/relocatable2.s -o %t3.o
 # RUN: ld.lld -r %t1.o %t2.o %t3.o -o %t
 # RUN: llvm-readobj --file-headers --sections -l --symbols -r %t | FileCheck %s
-# RUN: llvm-objdump -section-headers %t | FileCheck -check-prefix=SECTION %s
-# RUN: llvm-objdump -s -d %t | FileCheck -check-prefix=CHECKTEXT %s
+# RUN: llvm-objdump --section-headers %t | FileCheck --check-prefix=SECTION %s
+# RUN: llvm-objdump -s -d %t | FileCheck --check-prefix=CHECKTEXT %s
 
 ## Test --relocatable alias
 # RUN: ld.lld --relocatable %t1.o %t2.o %t3.o -o %t
 # RUN: llvm-readobj --file-headers --sections -l --symbols -r %t | FileCheck %s
-# RUN: llvm-objdump -s -d %t | FileCheck -check-prefix=CHECKTEXT %s
+# RUN: llvm-objdump -s -d %t | FileCheck --check-prefix=CHECKTEXT %s
 
 ## Verify that we can use our relocation output as input to produce executable
 # RUN: ld.lld -e main %t -o %texec
@@ -75,7 +75,7 @@
 # CHECKTEXT-NEXT: 40: c7 04 25 00 00 00 00 08 00 00 00 movl $8, 0
 # CHECKTEXT-NEXT: 4b: c7 04 25 00 00 00 00 09 00 00 00 movl $9, 0
 
-# CHECKEXE:       Format: ELF64-x86-64
+# CHECKEXE:       Format: elf64-x86-64
 # CHECKEXE-NEXT:  Arch: x86_64
 # CHECKEXE-NEXT:  AddressSize: 64bit
 # CHECKEXE-NEXT:  LoadName:
diff --git a/lld/test/ELF/relocation-copy-i686.s b/lld/test/ELF/relocation-copy-i686.s
index efccea3b4ae58..af78068ae18ac 100644
--- a/lld/test/ELF/relocation-copy-i686.s
+++ b/lld/test/ELF/relocation-copy-i686.s
@@ -4,7 +4,7 @@
 // RUN: ld.lld -shared %t2.o -soname=t.so -o %t.so
 // RUN: ld.lld -e main %t.o %t.so -o %t3
 // RUN: llvm-readobj -S -r --expand-relocs %t3 | FileCheck %s
-// RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t3 | FileCheck -check-prefix=CODE %s
+// RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t3 | FileCheck --check-prefix=CODE %s
 
 .text
 .globl main
diff --git a/lld/test/ELF/relocation-copy.s b/lld/test/ELF/relocation-copy.s
index 7f0c083a8e381..bc8eb59012d74 100644
--- a/lld/test/ELF/relocation-copy.s
+++ b/lld/test/ELF/relocation-copy.s
@@ -4,7 +4,7 @@
 // RUN: ld.lld -shared %t2.o -soname=so -o %t.so
 // RUN: ld.lld %t.o %t.so -o %t3
 // RUN: llvm-readobj -S -r --expand-relocs %t3 | FileCheck %s
-// RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t3 | FileCheck -check-prefix=CODE %s
+// RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t3 | FileCheck --check-prefix=CODE %s
 
 .text
 .global _start
diff --git a/lld/test/ELF/relocation-in-merge.s b/lld/test/ELF/relocation-in-merge.s
index b37eff3ab892d..e919aea539fd2 100644
--- a/lld/test/ELF/relocation-in-merge.s
+++ b/lld/test/ELF/relocation-in-merge.s
@@ -1,7 +1,7 @@
 // REQUIRES: x86
 // RUN: llvm-mc %s -o %t.o -filetype=obj -triple=x86_64-pc-linux
 // RUN: ld.lld %t.o -o %t -shared
-// RUN: llvm-objdump -section-headers %t | FileCheck %s
+// RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 // Test that we accept this by just not merging the section.
 // CHECK:  .foo          00000008
diff --git a/lld/test/ELF/relro-omagic.s b/lld/test/ELF/relro-omagic.s
index f344db23ad3af..b6c9e0d20b9d1 100644
--- a/lld/test/ELF/relro-omagic.s
+++ b/lld/test/ELF/relro-omagic.s
@@ -3,7 +3,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/shared.s -o %t2.o
 # RUN: ld.lld -shared %t2.o -o %t2.so -soname relro-omagic.s.tmp2.so
 # RUN: ld.lld --hash-style=sysv -N %t.o -Bdynamic %t2.so -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck --check-prefix=NORELRO %s
+# RUN: llvm-objdump --section-headers %t | FileCheck --check-prefix=NORELRO %s
 # RUN: llvm-readobj --program-headers %t | FileCheck --check-prefix=NOPHDRS %s
 
 # NORELRO:      Sections:
diff --git a/lld/test/ELF/sectionstart-noallochdr.s b/lld/test/ELF/sectionstart-noallochdr.s
index b32d67c7b789c..9b9cac257e5c0 100644
--- a/lld/test/ELF/sectionstart-noallochdr.s
+++ b/lld/test/ELF/sectionstart-noallochdr.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld %t.o --section-start .data=0x20 \
 # RUN: --section-start .bss=0x30 --section-start .text=0x10 -o %t1
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 # CHECK:      Sections:
 # CHECK-NEXT:  Idx Name          Size     VMA              Type
diff --git a/lld/test/ELF/sectionstart.s b/lld/test/ELF/sectionstart.s
index 340794628acea..d694c9375fd80 100644
--- a/lld/test/ELF/sectionstart.s
+++ b/lld/test/ELF/sectionstart.s
@@ -2,7 +2,7 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 # RUN: ld.lld %t.o --section-start .text=0x100000 \
 # RUN:   --section-start=.data=0x110000 --section-start .bss=0x200000 -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 # CHECK:      Sections:
 # CHECK-NEXT:  Idx Name          Size     VMA              Type
@@ -14,19 +14,19 @@
 ## The same, but dropped "0x" prefix.
 # RUN: ld.lld %t.o --section-start .text=100000 \
 # RUN:   --section-start .data=110000 --section-start .bss=0x200000 -o %t1
-# RUN: llvm-objdump -section-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t1 | FileCheck %s
 
 ## Use -Ttext, -Tdata, -Tbss as replacement for --section-start:
 # RUN: ld.lld %t.o -Ttext=0x100000 -Tdata=0x110000 -Tbss=0x200000 -o %t4
-# RUN: llvm-objdump -section-headers %t4 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t4 | FileCheck %s
 
 ## The same, but dropped "0x" prefix.
 # RUN: ld.lld %t.o -Ttext=100000 -Tdata=110000 -Tbss=200000 -o %t5
-# RUN: llvm-objdump -section-headers %t5 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t5 | FileCheck %s
 
 ## Check form without assignment:
 # RUN: ld.lld %t.o -Ttext 0x100000 -Tdata 0x110000 -Tbss 0x200000 -o %t4
-# RUN: llvm-objdump -section-headers %t4 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t4 | FileCheck %s
 
 ## Errors:
 # RUN: not ld.lld %t.o --section-start .text100000 -o /dev/null 2>&1 \
diff --git a/lld/test/ELF/startstop-gccollect.s b/lld/test/ELF/startstop-gccollect.s
index 300fb19d586b9..8017bca6a55af 100644
--- a/lld/test/ELF/startstop-gccollect.s
+++ b/lld/test/ELF/startstop-gccollect.s
@@ -3,19 +3,19 @@
 
 ## Default run: sections foo and bar exist in output
 # RUN: ld.lld %t -o %tout
-# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
+# RUN: llvm-objdump -d %tout | FileCheck --check-prefix=DISASM %s
 
 ## Check that foo and bar sections are not garbage collected,
 ## we do not want to reclaim sections if they are referred
 ## by __start_* and __stop_* symbols.
 # RUN: ld.lld %t --gc-sections -o %tout
-# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
+# RUN: llvm-objdump -d %tout | FileCheck --check-prefix=DISASM %s
 
 # RUN: echo ".global __start_foo; __start_foo:" > %t2.s
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t2.s -o %t2.o
 # RUN: ld.lld -shared %t2.o -o %t2.so
 # RUN: ld.lld %t --gc-sections -o %tout %t2.so
-# RUN: llvm-objdump -d %tout | FileCheck -check-prefix=DISASM %s
+# RUN: llvm-objdump -d %tout | FileCheck --check-prefix=DISASM %s
 
 # DISASM:      <_start>:
 # DISASM-NEXT:   callq   {{.*}} <__start_foo>
diff --git a/lld/test/ELF/startstop.s b/lld/test/ELF/startstop.s
index 0b318ae943d7b..9eddd4cc91f44 100644
--- a/lld/test/ELF/startstop.s
+++ b/lld/test/ELF/startstop.s
@@ -1,7 +1,7 @@
 // REQUIRES: x86
 // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
 // RUN: ld.lld %t -o %t.so -shared
-// RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck -check-prefix=DISASM %s
+// RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=DISASM %s
 // RUN: llvm-readobj --symbols -r %t.so | FileCheck -check-prefix=SYMBOL %s
 
 // DISASM: <_start>:
diff --git a/lld/test/ELF/strip-all.s b/lld/test/ELF/strip-all.s
index 7e05ba816088d..ee788c69c994f 100644
--- a/lld/test/ELF/strip-all.s
+++ b/lld/test/ELF/strip-all.s
@@ -2,24 +2,24 @@
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld %t.o -o %t1
-#RUN: llvm-objdump -section-headers %t1 | FileCheck %s -check-prefix BEFORE
+#RUN: llvm-objdump --section-headers %t1 | FileCheck %s --check-prefix BEFORE
 #BEFORE:       .symtab
 #BEFORE-NEXT:  .shstrtab
 #BEFORE-NEXT:  .strtab
 
 #RUN: ld.lld %t.o --strip-all -o %t1
-#RUN: llvm-objdump -section-headers %t1 | FileCheck %s -check-prefix AFTER
+#RUN: llvm-objdump --section-headers %t1 | FileCheck %s --check-prefix AFTER
 #AFTER-NOT: .symtab
 #AFTER:     .shstrtab
 #AFTER-NOT: .strtab
 
 # Ignore --strip-all if -r is specified
 #RUN: ld.lld %t.o --strip-all -r -o %t1
-#RUN: llvm-objdump -section-headers %t1 | FileCheck %s -check-prefix BEFORE
+#RUN: llvm-objdump --section-headers %t1 | FileCheck %s --check-prefix BEFORE
 
 # Test alias -s
 #RUN: ld.lld %t.o -s -o %t1
-#RUN: llvm-objdump -section-headers %t1 | FileCheck %s -check-prefix AFTER
+#RUN: llvm-objdump --section-headers %t1 | FileCheck %s --check-prefix AFTER
 
 # RUN: not ld.lld %t.o --strip-all --emit-relocs -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s
 # ERR: error: --strip-all and --emit-relocs may not be used together
diff --git a/lld/test/ELF/synthetic-got.s b/lld/test/ELF/synthetic-got.s
index b0bcabf9e0b78..fc68f0d649ac7 100644
--- a/lld/test/ELF/synthetic-got.s
+++ b/lld/test/ELF/synthetic-got.s
@@ -2,8 +2,8 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: echo "SECTIONS { }" > %t0.script
 # RUN: ld.lld --hash-style=sysv -shared %t.o -o %t0.out --script %t0.script
-# RUN: llvm-objdump -section-headers %t0.out | FileCheck %s --check-prefix=GOT
-# RUN: llvm-objdump -s -section=.got -section=.got.plt %t0.out \
+# RUN: llvm-objdump --section-headers %t0.out | FileCheck %s --check-prefix=GOT
+# RUN: llvm-objdump -s --section=.got --section=.got.plt %t0.out \
 # RUN:   | FileCheck %s --check-prefix=GOTDATA
 
 # GOT:     Sections:
@@ -17,8 +17,8 @@
 
 # RUN: echo "SECTIONS { .mygot : { *(.got) *(.got.plt) } }" > %t1.script
 # RUN: ld.lld --hash-style=sysv -shared %t.o -o %t1.out --script %t1.script
-# RUN: llvm-objdump -section-headers %t1.out | FileCheck %s --check-prefix=MYGOT
-# RUN: llvm-objdump -s -section=.mygot %t1.out | FileCheck %s --check-prefix=MYGOTDATA
+# RUN: llvm-objdump --section-headers %t1.out | FileCheck %s --check-prefix=MYGOT
+# RUN: llvm-objdump -s --section=.mygot %t1.out | FileCheck %s --check-prefix=MYGOTDATA
 
 # MYGOT:     Sections:
 # MYGOT:      8  .mygot     00000028 00000000000000e0 DATA
diff --git a/lld/test/ELF/wrap-no-real.s b/lld/test/ELF/wrap-no-real.s
index 2c30d06c67c23..41a23185093be 100644
--- a/lld/test/ELF/wrap-no-real.s
+++ b/lld/test/ELF/wrap-no-real.s
@@ -5,17 +5,17 @@
 // RUN: ld.lld -o %t3.so -shared %t3.o
 
 // RUN: ld.lld -o %t %t1.o %t2.o -wrap foo
-// RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s
+// RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s
 
 // RUN: ld.lld -o %t %t1.o %t2.o %t3.so -wrap foo
-// RUN: llvm-objdump -d -print-imm-hex %t | FileCheck %s
+// RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s
 
 // CHECK: <_start>:
 // CHECK-NEXT: movl $0x11010, %edx
 // CHECK-NEXT: movl $0x11010, %edx
 // CHECK-NEXT: movl $0x11000, %edx
 
-// RUN: llvm-objdump -t %t | FileCheck -check-prefix=SYM %s
+// RUN: llvm-objdump -t %t | FileCheck --check-prefix=SYM %s
 
 
 // SYM:      {{.*}}           l .dynamic 0000000000000000 .hidden _DYNAMIC
diff --git a/lld/test/ELF/wrap.s b/lld/test/ELF/wrap.s
index 2f76208a35387..5718ea45f669f 100644
--- a/lld/test/ELF/wrap.s
+++ b/lld/test/ELF/wrap.s
@@ -3,11 +3,11 @@
 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/wrap.s -o %t2
 
 // RUN: ld.lld -o %t3 %t %t2 -wrap foo -wrap nosuchsym
-// RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s
+// RUN: llvm-objdump -d --print-imm-hex %t3 | FileCheck %s
 // RUN: ld.lld -o %t3 %t %t2 --wrap foo -wrap=nosuchsym
-// RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s
+// RUN: llvm-objdump -d --print-imm-hex %t3 | FileCheck %s
 // RUN: ld.lld -o %t3 %t %t2 --wrap foo --wrap foo -wrap=nosuchsym
-// RUN: llvm-objdump -d -print-imm-hex %t3 | FileCheck %s
+// RUN: llvm-objdump -d --print-imm-hex %t3 | FileCheck %s
 
 // CHECK: <_start>:
 // CHECK-NEXT: movl $0x11010, %edx
diff --git a/lld/test/ELF/x86-64-plt-high-addr.s b/lld/test/ELF/x86-64-plt-high-addr.s
index 381db32db5f9b..9eef3e15a57c9 100644
--- a/lld/test/ELF/x86-64-plt-high-addr.s
+++ b/lld/test/ELF/x86-64-plt-high-addr.s
@@ -13,7 +13,7 @@
 
 // RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t2.o
 // RUN: ld.lld -o %t2.exe %t2.o %t.so -image-base=0xcafe00000000 -z retpolineplt
-// RUN: llvm-objdump -s -j .got.plt %t2.exe | FileCheck -check-prefix=RETPOLINE %s
+// RUN: llvm-objdump -s -j .got.plt %t2.exe | FileCheck --check-prefix=RETPOLINE %s
 
 // RETPOLINE:      Contents of section .got.plt:
 // RETPOLINE-NEXT: cafe000033b0 e0220000 feca0000 00000000 00000000
diff --git a/lld/test/ELF/x86-64-retpoline-znow-static-iplt.s b/lld/test/ELF/x86-64-retpoline-znow-static-iplt.s
index e0c54c3310fa8..01cc1ec4579b9 100644
--- a/lld/test/ELF/x86-64-retpoline-znow-static-iplt.s
+++ b/lld/test/ELF/x86-64-retpoline-znow-static-iplt.s
@@ -1,7 +1,7 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: ld.lld -z retpolineplt -z now %t.o -o %t
-# RUN: llvm-objdump -d -no-show-raw-insn %t | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
 
 #0x2011a9+5 + 34 = 0x2011d0 (foo@plt)
 # CHECK:      <_start>:
diff --git a/lld/test/mach-o/PIE.yaml b/lld/test/mach-o/PIE.yaml
index e7c15fbc1f14b..ce6487c860b07 100644
--- a/lld/test/mach-o/PIE.yaml
+++ b/lld/test/mach-o/PIE.yaml
@@ -1,14 +1,14 @@
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s \
 # RUN: %p/Inputs/PIE.yaml -o %t  && \
-# RUN: llvm-objdump -macho -private-headers %t | FileCheck %s
+# RUN: llvm-objdump --macho --private-headers %t | FileCheck %s
 #
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s \
 # RUN: %p/Inputs/PIE.yaml -pie -o %t\
-# RUN:  &&  llvm-objdump -macho -private-headers %t | FileCheck %s
+# RUN:  &&  llvm-objdump --macho --private-headers %t | FileCheck %s
 #
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s \
 # RUN: %p/Inputs/PIE.yaml -no_pie -o %t\
-# RUN:  &&  llvm-objdump -macho -private-headers %t \
+# RUN:  &&  llvm-objdump --macho --private-headers %t \
 # RUN:  | FileCheck --check-prefix=CHECK_NO_PIE %s
 #
 # Test various PIE options.
diff --git a/lld/test/mach-o/arm-interworking-movw.yaml b/lld/test/mach-o/arm-interworking-movw.yaml
index ade459c8c8966..6bad3a9ea98b5 100644
--- a/lld/test/mach-o/arm-interworking-movw.yaml
+++ b/lld/test/mach-o/arm-interworking-movw.yaml
@@ -2,7 +2,7 @@
 # RUN: ld64.lld -arch armv7 -r -print_atoms %s -o %t  | FileCheck %s
 # RUN: ld64.lld -arch armv7 -dylib -print_atoms %t -o %t2 \
 # RUN:     %p/Inputs/armv7/libSystem.yaml -sectalign __TEXT __text 0x1000  | FileCheck %s
-# RUN: llvm-objdump -d -macho -no-symbolic-operands %t2 | FileCheck -check-prefix=CODE %s
+# RUN: llvm-objdump -d --macho --no-symbolic-operands %t2 | FileCheck --check-prefix=CODE %s
 #
 # Test thumb and arm branches round trip through -r.
 # Test movw/movt pairs have low bit set properly for thumb vs arm.
diff --git a/lld/test/mach-o/arm64-reloc-negDelta32-fixup.yaml b/lld/test/mach-o/arm64-reloc-negDelta32-fixup.yaml
index b0c86f92a98fa..b512bb755b3d9 100644
--- a/lld/test/mach-o/arm64-reloc-negDelta32-fixup.yaml
+++ b/lld/test/mach-o/arm64-reloc-negDelta32-fixup.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -arch arm64 -r %s -o %t
 # RUN: ld64.lld -arch arm64 -r %t -o %t2
-# RUN: llvm-objdump -s -section="__eh_frame" %t | FileCheck %s
-# RUN: llvm-objdump -s -section="__eh_frame" %t2 | FileCheck %s
+# RUN: llvm-objdump -s --section="__eh_frame" %t | FileCheck %s
+# RUN: llvm-objdump -s --section="__eh_frame" %t2 | FileCheck %s
 
 # The reference from FDE->CIE is implicitly created as a negDelta32.
 # We don't emit these in to the binary as relocations, so we need to
diff --git a/lld/test/mach-o/arm64-section-order.yaml b/lld/test/mach-o/arm64-section-order.yaml
index 0dbf52c2546cd..6e88d6f1a4292 100644
--- a/lld/test/mach-o/arm64-section-order.yaml
+++ b/lld/test/mach-o/arm64-section-order.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -arch arm64 -r -print_atoms %s -o %t
 # RUN: ld64.lld -arch arm64 -r -print_atoms %t -o %t2
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
-# RUN: llvm-objdump -section-headers %t2 | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t2 | FileCheck %s
 
 # Make sure that the sections are sorted.  Currently we want this order:
 # __text, __unwind_info
diff --git a/lld/test/mach-o/data-in-code-load-command.yaml b/lld/test/mach-o/data-in-code-load-command.yaml
index 32c5d9220c51c..a99026b11d212 100644
--- a/lld/test/mach-o/data-in-code-load-command.yaml
+++ b/lld/test/mach-o/data-in-code-load-command.yaml
@@ -1,11 +1,11 @@
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -data_in_code_info && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -no_data_in_code_info && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -data_in_code_info -no_data_in_code_info && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -r && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -r -data_in_code_info && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -r -no_data_in_code_info && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -data_in_code_info && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -no_data_in_code_info && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -data_in_code_info -no_data_in_code_info && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -r && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -r -data_in_code_info && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -r -no_data_in_code_info && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_DATA_IN_CODE_INFO
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/do-not-emit-unwind-fde-arm64.yaml b/lld/test/mach-o/do-not-emit-unwind-fde-arm64.yaml
index 3afdc2be1fb70..25ba88307fc18 100644
--- a/lld/test/mach-o/do-not-emit-unwind-fde-arm64.yaml
+++ b/lld/test/mach-o/do-not-emit-unwind-fde-arm64.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -arch arm64 -r -print_atoms %s -o %t | FileCheck %s
 # RUN: ld64.lld -arch arm64 -r -print_atoms %t -o %t2 | FileCheck %s
-# RUN: llvm-objdump -r -s -section="__eh_frame" -macho %t | FileCheck -check-prefix=CODE %s
-# RUN: llvm-objdump -r -s -section="__eh_frame" -macho %t2 | FileCheck -check-prefix=CODE %s
+# RUN: llvm-objdump -r -s --section="__eh_frame" --macho %t | FileCheck --check-prefix=CODE %s
+# RUN: llvm-objdump -r -s --section="__eh_frame" --macho %t2 | FileCheck --check-prefix=CODE %s
 
 
 --- !mach-o
diff --git a/lld/test/mach-o/dylib-install-names.yaml b/lld/test/mach-o/dylib-install-names.yaml
index 10209ba12abb1..20b7780c073a1 100644
--- a/lld/test/mach-o/dylib-install-names.yaml
+++ b/lld/test/mach-o/dylib-install-names.yaml
@@ -2,25 +2,25 @@
 # RUN: ld64.lld -arch x86_64 -install_name libwibble.dylib -dylib \
 # RUN:     -compatibility_version 2.0 -current_version 5.3 \
 # RUN:     %p/Inputs/x86_64/libSystem.yaml %s -o %t.dylib
-# RUN: llvm-objdump -private-headers %t.dylib | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
+# RUN: llvm-objdump --private-headers %t.dylib | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
 
 # Check we read LC_ID_DYLIB correctly:
 # RUN: ld64.lld -arch x86_64 %p/Inputs/use-dylib-install-names.yaml \
 # RUN:      %p/Inputs/x86_64/libSystem.yaml %t.dylib -dylib -o %t2.dylib
-# RUN: llvm-objdump -private-headers %t2.dylib | FileCheck %s --check-prefix=CHECK-BINARY-READ
+# RUN: llvm-objdump --private-headers %t2.dylib | FileCheck %s --check-prefix=CHECK-BINARY-READ
 
 # Check we default the install-name to the output file:
 # RUN: ld64.lld -arch x86_64 -dylib %s -o libwibble.dylib \
 # RUN:     -compatibility_version 2.0 -current_version 5.3 \
 # RUN:     %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -private-headers libwibble.dylib | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
+# RUN: llvm-objdump --private-headers libwibble.dylib | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
 # RUN: rm -f libwibble.dylib
 
 # Check -single_module does nothing
 # RUN: ld64.lld -arch x86_64 -dylib %s -install_name libwibble.dylib \
 # RUN:     -compatibility_version 2.0 -current_version 5.3 \
 # RUN:     -single_module -o %t2.dylib %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -private-headers %t2.dylib | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
+# RUN: llvm-objdump --private-headers %t2.dylib | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/eh-frame-relocs-arm64.yaml b/lld/test/mach-o/eh-frame-relocs-arm64.yaml
index a71f79e692ffb..f8d538d7c109f 100644
--- a/lld/test/mach-o/eh-frame-relocs-arm64.yaml
+++ b/lld/test/mach-o/eh-frame-relocs-arm64.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -arch arm64 -r -print_atoms %s -o %t | FileCheck %s
 # RUN: ld64.lld -arch arm64 -r -print_atoms %t -o %t2 | FileCheck %s
-# RUN: llvm-objdump -r -s -section="__eh_frame" -macho %t | FileCheck -check-prefix=CODE %s
-# RUN: llvm-objdump -r -s -section="__eh_frame" -macho %t2 | FileCheck -check-prefix=CODE %s
+# RUN: llvm-objdump -r -s --section="__eh_frame" --macho %t | FileCheck --check-prefix=CODE %s
+# RUN: llvm-objdump -r -s --section="__eh_frame" --macho %t2 | FileCheck --check-prefix=CODE %s
 
 
 --- !mach-o
diff --git a/lld/test/mach-o/executable-exports.yaml b/lld/test/mach-o/executable-exports.yaml
index 83d9c210173e9..cd5c1f83bad97 100644
--- a/lld/test/mach-o/executable-exports.yaml
+++ b/lld/test/mach-o/executable-exports.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 \
 # RUN:      %s %p/Inputs/x86_64/libSystem.yaml -o %t  && \
-# RUN: llvm-objdump -macho -exports-trie %t | FileCheck %s
+# RUN: llvm-objdump --macho --exports-trie %t | FileCheck %s
 #
 #
 # Tests that exports trie builds properly.
diff --git a/lld/test/mach-o/export-trie-order.yaml b/lld/test/mach-o/export-trie-order.yaml
index 1b1fc392bf25f..70c2bc1bdf160 100644
--- a/lld/test/mach-o/export-trie-order.yaml
+++ b/lld/test/mach-o/export-trie-order.yaml
@@ -1,5 +1,5 @@
 # RUN: ld64.lld -arch i386 %s %p/Inputs/hello-world-x86.yaml -o %t
-# RUN: llvm-objdump -macho -exports-trie %t | FileCheck %s
+# RUN: llvm-objdump --macho --exports-trie %t | FileCheck %s
 #
 # Test that the export trie is emitted in order.
 #
diff --git a/lld/test/mach-o/function-starts-load-command.yaml b/lld/test/mach-o/function-starts-load-command.yaml
index fadc731e40e11..df1f9cf67eda4 100644
--- a/lld/test/mach-o/function-starts-load-command.yaml
+++ b/lld/test/mach-o/function-starts-load-command.yaml
@@ -1,8 +1,8 @@
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -function_starts && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -no_function_starts && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_FUNCTION_STARTS
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -function_starts -no_function_starts && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_FUNCTION_STARTS
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_FUNCTION_STARTS
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -function_starts && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -no_function_starts && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_FUNCTION_STARTS
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -function_starts -no_function_starts && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_FUNCTION_STARTS
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_FUNCTION_STARTS
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/gcc_except_tab-got-arm64.yaml b/lld/test/mach-o/gcc_except_tab-got-arm64.yaml
index ed517c8bd6b13..d453e56084e3e 100644
--- a/lld/test/mach-o/gcc_except_tab-got-arm64.yaml
+++ b/lld/test/mach-o/gcc_except_tab-got-arm64.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch arm64 %s \
 # RUN: -dylib %p/Inputs/arm64/libSystem.yaml -o %t
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 
 # Make sure that the GOT relocation from gcc_except_tab to the data
 # is not removed.
diff --git a/lld/test/mach-o/got-order.yaml b/lld/test/mach-o/got-order.yaml
index f2488f089a62c..4e2e7f3f81648 100644
--- a/lld/test/mach-o/got-order.yaml
+++ b/lld/test/mach-o/got-order.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch x86_64  %s %p/Inputs/got-order.yaml \
 # RUN: %p/Inputs/got-order2.yaml -o %t %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -macho -bind %t | FileCheck %s
+# RUN: llvm-objdump --macho --bind %t | FileCheck %s
 #
 # Test that GOT slots are sorted by name
 #
diff --git a/lld/test/mach-o/hello-world-arm64.yaml b/lld/test/mach-o/hello-world-arm64.yaml
index b2e73662c13ff..3dee661bc32aa 100644
--- a/lld/test/mach-o/hello-world-arm64.yaml
+++ b/lld/test/mach-o/hello-world-arm64.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch arm64 %s %p/Inputs/hello-world-arm64.yaml -o %t
 # RUN: llvm-nm -m -n %t | FileCheck %s
-# RUN: llvm-objdump -private-headers %t | FileCheck %s --check-prefix=CHECK-PRIVATE-HEADER
+# RUN: llvm-objdump --private-headers %t | FileCheck %s --check-prefix=CHECK-PRIVATE-HEADER
 #
 # Test that arm64 hello-world can be linked into a mach-o executable
 #
diff --git a/lld/test/mach-o/interposing-section.yaml b/lld/test/mach-o/interposing-section.yaml
index 7b45f8a4d834a..aea66b73e34dd 100644
--- a/lld/test/mach-o/interposing-section.yaml
+++ b/lld/test/mach-o/interposing-section.yaml
@@ -1,9 +1,9 @@
 # RUN: ld64.lld -arch x86_64  %s %p/Inputs/interposing-section.yaml \
 # RUN: -dylib -o %t %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -private-headers %t | FileCheck %s
+# RUN: llvm-objdump --private-headers %t | FileCheck %s
 #
 # RUN: ld64.lld -arch x86_64  %s -r -o %t1
-# RUN: llvm-objdump -private-headers %t1 | FileCheck %s
+# RUN: llvm-objdump --private-headers %t1 | FileCheck %s
 #
 # Test that interposing section is preserved by linker.
 #
diff --git a/lld/test/mach-o/lazy-bind-x86_64.yaml b/lld/test/mach-o/lazy-bind-x86_64.yaml
index de97565d5469b..50438fd467d17 100644
--- a/lld/test/mach-o/lazy-bind-x86_64.yaml
+++ b/lld/test/mach-o/lazy-bind-x86_64.yaml
@@ -4,10 +4,10 @@
 # RUN: %p/Inputs/lazy-bind-x86_64.yaml  %p/Inputs/lazy-bind-x86_64-2.yaml \
 # RUN: %p/Inputs/lazy-bind-x86_64-3.yaml -o %t  \
 # RUN:   %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -macho -lazy-bind %t | FileCheck %s
+# RUN: llvm-objdump --macho --lazy-bind %t | FileCheck %s
 # RUN: llvm-nm -m %t | FileCheck --check-prefix=CHECK-NM %s
-# RUN: llvm-objdump -disassemble %t | FileCheck --check-prefix=CHECK-HELPERS %s
-# RUN: llvm-objdump -private-headers %t | FileCheck --check-prefix=CHECK-DYLIBS %s
+# RUN: llvm-objdump --disassemble %t | FileCheck --check-prefix=CHECK-HELPERS %s
+# RUN: llvm-objdump --private-headers %t | FileCheck --check-prefix=CHECK-DYLIBS %s
 #
 # Test that correct two-level namespace ordinals are used for lazy bindings.
 #
diff --git a/lld/test/mach-o/lc_segment_filesize.yaml b/lld/test/mach-o/lc_segment_filesize.yaml
index 71184c2308426..fb9703c7ffbee 100644
--- a/lld/test/mach-o/lc_segment_filesize.yaml
+++ b/lld/test/mach-o/lc_segment_filesize.yaml
@@ -1,4 +1,4 @@
-# RUN: ld64.lld -arch x86_64 -r -o %t %s && llvm-objdump -private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -r -o %t %s && llvm-objdump --private-headers %t | FileCheck %s
 
 # CHECK: filesize 19
 
diff --git a/lld/test/mach-o/mach_header-cpusubtype.yaml b/lld/test/mach-o/mach_header-cpusubtype.yaml
index 95d4627cf99f9..b11305833ee04 100644
--- a/lld/test/mach-o/mach_header-cpusubtype.yaml
+++ b/lld/test/mach-o/mach_header-cpusubtype.yaml
@@ -1,6 +1,6 @@
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.4 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_LIB64
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.5 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=LIB64
-# RUN: ld64.lld -arch x86_64 -dylib -macosx_version_min 10.5 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=DYLIB
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.4 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_LIB64
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.5 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=LIB64
+# RUN: ld64.lld -arch x86_64 -dylib -macosx_version_min 10.5 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=DYLIB
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/parse-data-in-code-armv7.yaml b/lld/test/mach-o/parse-data-in-code-armv7.yaml
index 18eb6ffddc57e..061868cdb5014 100644
--- a/lld/test/mach-o/parse-data-in-code-armv7.yaml
+++ b/lld/test/mach-o/parse-data-in-code-armv7.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -arch armv7 -r -print_atoms %s -o %t  | FileCheck %s
 # RUN: ld64.lld -arch armv7 -r -print_atoms %t -o %t2  | FileCheck %s
 # RUN: ld64.lld -arch armv7 -dylib %s -o %t3.dylib %p/Inputs/armv7/libSystem.yaml \
-# RUN:   && llvm-objdump -macho -private-headers %t3.dylib | FileCheck --check-prefix=CHECK2 %s
+# RUN:   && llvm-objdump --macho --private-headers %t3.dylib | FileCheck --check-prefix=CHECK2 %s
 #
 # Test parsing LC_DATA_IN_CODE
 #
diff --git a/lld/test/mach-o/rpath.yaml b/lld/test/mach-o/rpath.yaml
index b25266ced9936..3ffce99b53e9d 100644
--- a/lld/test/mach-o/rpath.yaml
+++ b/lld/test/mach-o/rpath.yaml
@@ -1,7 +1,7 @@
 # Check we handle -rpath correctly:
 # RUN: ld64.lld -arch x86_64 -rpath @loader_path/../Frameworks \
 # RUN:     %p/Inputs/x86_64/libSystem.yaml %s -o %t
-# RUN: llvm-objdump -private-headers %t | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
+# RUN: llvm-objdump --private-headers %t | FileCheck %s --check-prefix=CHECK-BINARY-WRITE
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/run-tlv-pass-x86-64.yaml b/lld/test/mach-o/run-tlv-pass-x86-64.yaml
index 765e1c1fd1bb3..ca1d8b260f6de 100644
--- a/lld/test/mach-o/run-tlv-pass-x86-64.yaml
+++ b/lld/test/mach-o/run-tlv-pass-x86-64.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -macosx_version_min 10.7 -arch x86_64 -print_atoms %s -o %t | FileCheck %s
 # RUN: not ld64.lld -macosx_version_min 10.6 -arch x86_64 -o %t %s 2> %t2
 # RUN: FileCheck < %t2 %s --check-prefix=CHECK-ERROR
-# RUN: llvm-objdump -macho -private-headers %t | FileCheck %s --check-prefix=CHECK-LOADCMDS
+# RUN: llvm-objdump --macho --private-headers %t | FileCheck %s --check-prefix=CHECK-LOADCMDS
 #
 # Test parsing of x86_64 tlv relocations.
 
diff --git a/lld/test/mach-o/sectattrs.yaml b/lld/test/mach-o/sectattrs.yaml
index 467c2b7fca07c..b9515f36026a8 100644
--- a/lld/test/mach-o/sectattrs.yaml
+++ b/lld/test/mach-o/sectattrs.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -dylib \
 # RUN:    %p/Inputs/x86_64/libSystem.yaml -o %t \
-# RUN: && llvm-objdump -private-headers %t | FileCheck %s
+# RUN: && llvm-objdump --private-headers %t | FileCheck %s
 #
 
 --- !mach-o
diff --git a/lld/test/mach-o/seg-protection-arm64.yaml b/lld/test/mach-o/seg-protection-arm64.yaml
index 6b00fc9cfaea0..f5f57eb3956b7 100644
--- a/lld/test/mach-o/seg-protection-arm64.yaml
+++ b/lld/test/mach-o/seg-protection-arm64.yaml
@@ -1,4 +1,4 @@
-# RUN: ld64.lld -arch arm64 %s %p/Inputs/hello-world-arm64.yaml -o %t && llvm-objdump -private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch arm64 %s %p/Inputs/hello-world-arm64.yaml -o %t && llvm-objdump --private-headers %t | FileCheck %s
 
 --- !mach-o
 arch:            arm64
diff --git a/lld/test/mach-o/seg-protection-x86_64.yaml b/lld/test/mach-o/seg-protection-x86_64.yaml
index 2ce356634c7b4..42915d4f0a3d5 100644
--- a/lld/test/mach-o/seg-protection-x86_64.yaml
+++ b/lld/test/mach-o/seg-protection-x86_64.yaml
@@ -1,4 +1,4 @@
-# RUN: ld64.lld -arch x86_64 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump -private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 %s %p/Inputs/hello-world-x86_64.yaml -o %t && llvm-objdump --private-headers %t | FileCheck %s
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/source-version.yaml b/lld/test/mach-o/source-version.yaml
index ce185f8886b6e..aef1af493e815 100644
--- a/lld/test/mach-o/source-version.yaml
+++ b/lld/test/mach-o/source-version.yaml
@@ -1,5 +1,5 @@
 # RUN: not ld64.lld -arch x86_64 -source_version 10.blah %s -o %t 2>&1 | FileCheck %s --check-prefix=ERROR
-# RUN: ld64.lld -arch x86_64 -source_version 10.1.2.3.4 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump -private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -source_version 10.1.2.3.4 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump --private-headers %t | FileCheck %s
 
 --- !mach-o
 arch:            x86_64
diff --git a/lld/test/mach-o/stack-size.yaml b/lld/test/mach-o/stack-size.yaml
index 6a5e313c45965..9801649a42328 100644
--- a/lld/test/mach-o/stack-size.yaml
+++ b/lld/test/mach-o/stack-size.yaml
@@ -1,7 +1,7 @@
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.9 %s -o %t %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -private-headers %t | FileCheck --check-prefix=CHECK-DEFAULT %s
+# RUN: llvm-objdump --private-headers %t | FileCheck --check-prefix=CHECK-DEFAULT %s
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.9 %s -o %t -stack_size 31415926000 %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -private-headers %t | FileCheck --check-prefix=CHECK-EXPLICIT %s
+# RUN: llvm-objdump --private-headers %t | FileCheck --check-prefix=CHECK-EXPLICIT %s
 # RUN: not ld64.lld -arch x86_64 -stack_size 0x31415926530 %s >/dev/null 2> %t
 # RUN: FileCheck < %t %s --check-prefix=CHECK-ERROR-MISPAGED
 # RUN: not ld64.lld -arch x86_64 -stack_size hithere %s >/dev/null 2> %t
diff --git a/lld/test/mach-o/unwind-info-simple-arm64.yaml b/lld/test/mach-o/unwind-info-simple-arm64.yaml
index 920cc0d7c3633..fa264ef7318e5 100644
--- a/lld/test/mach-o/unwind-info-simple-arm64.yaml
+++ b/lld/test/mach-o/unwind-info-simple-arm64.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch arm64 -o %t %s \
 # RUN: %p/Inputs/unwind-info-simple-arm64.yaml -e _main %p/Inputs/arm64/libSystem.yaml
-# RUN: llvm-objdump -unwind-info %t | FileCheck %s
+# RUN: llvm-objdump --unwind-info %t | FileCheck %s
 
 --- !mach-o
 arch:            arm64
diff --git a/lld/test/mach-o/unwind-info-simple-x86_64.yaml b/lld/test/mach-o/unwind-info-simple-x86_64.yaml
index 0c9b74c478c90..a4efed385f652 100644
--- a/lld/test/mach-o/unwind-info-simple-x86_64.yaml
+++ b/lld/test/mach-o/unwind-info-simple-x86_64.yaml
@@ -1,5 +1,5 @@
 # RUN: ld64.lld -arch x86_64 %s -o %t -e _main %p/Inputs/x86_64/libSystem.yaml
-# RUN: llvm-objdump -unwind-info %t | FileCheck %s
+# RUN: llvm-objdump --unwind-info %t | FileCheck %s
 
 # CHECK: Contents of __unwind_info section:
 # CHECK:   Version:                                   0x1
diff --git a/lld/test/mach-o/upward-dylib-load-command.yaml b/lld/test/mach-o/upward-dylib-load-command.yaml
index 7fc703c7bef5a..0b5af14417789 100644
--- a/lld/test/mach-o/upward-dylib-load-command.yaml
+++ b/lld/test/mach-o/upward-dylib-load-command.yaml
@@ -2,7 +2,7 @@
 # RUN:     -install_name /usr/lib/libbar.dylib %p/Inputs/x86_64/libSystem.yaml -o %t1.dylib
 # RUN: ld64.lld -arch x86_64 -dylib %s -upward_library  %t1.dylib \
 # RUN:      -install_name /usr/lib/libfoo.dylib %p/Inputs/x86_64/libSystem.yaml -o %t
-# RUN: llvm-objdump -private-headers %t | FileCheck %s
+# RUN: llvm-objdump --private-headers %t | FileCheck %s
 #
 #
 # Test upward linking: 1) build libbar.dylib, 2) build libfoo.dylib and upward
diff --git a/lld/test/mach-o/use-dylib.yaml b/lld/test/mach-o/use-dylib.yaml
index bcb2d07e38e8a..7436e180c29fa 100644
--- a/lld/test/mach-o/use-dylib.yaml
+++ b/lld/test/mach-o/use-dylib.yaml
@@ -1,6 +1,6 @@
 # RUN: ld64.lld -arch x86_64 %s \
 # RUN: %p/Inputs/use-simple-dylib.yaml %p/Inputs/x86_64/libSystem.yaml -dylib -o %t.dylib
-# RUN: llvm-objdump -private-headers %t.dylib | FileCheck %s
+# RUN: llvm-objdump --private-headers %t.dylib | FileCheck %s
 
 # This test ensures that we have a LC_LOAD_DYLIB for libspecial.dylib even though we don't
 # use any atoms from it.  This matches the ld64 behaviour.
diff --git a/lld/test/mach-o/version-min-load-command-object.yaml b/lld/test/mach-o/version-min-load-command-object.yaml
index 08eb6ab768bf3..cdfee24ce381c 100644
--- a/lld/test/mach-o/version-min-load-command-object.yaml
+++ b/lld/test/mach-o/version-min-load-command-object.yaml
@@ -1,6 +1,6 @@
-# RUN: ld64.lld -arch x86_64 %s -o %t -r -macosx_version_min 10.8 && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 %s -o %t -r && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 %s -o %t -r %p/Inputs/no-version-min-load-command-object.yaml && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
+# RUN: ld64.lld -arch x86_64 %s -o %t -r -macosx_version_min 10.8 && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 %s -o %t -r && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 %s -o %t -r %p/Inputs/no-version-min-load-command-object.yaml && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
 
 # If we are emitting an object file, then we only emit a min version load command if the source object file(s) all have
 # version(s) and either known platforms or contain min version load commands themselves.
diff --git a/lld/test/mach-o/version-min-load-command.yaml b/lld/test/mach-o/version-min-load-command.yaml
index a4d39b85e4c22..38ceb17e05255 100644
--- a/lld/test/mach-o/version-min-load-command.yaml
+++ b/lld/test/mach-o/version-min-load-command.yaml
@@ -1,11 +1,11 @@
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump -private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump --private-headers %t | FileCheck %s
 # RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml 2>&1 | FileCheck %s --check-prefix=WARNING
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -version_load_command && llvm-objdump -private-headers %t | FileCheck %s
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -no_version_load_command && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -version_load_command -no_version_load_command && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -version_load_command && llvm-objdump --private-headers %t | FileCheck %s
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -no_version_load_command && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static -version_load_command -no_version_load_command && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml -static && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=NO_VERSION_MIN
 
-# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 -sdk_version 10.9 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump -private-headers %t | FileCheck %s --check-prefix=SDK_VERSION
+# RUN: ld64.lld -arch x86_64 -macosx_version_min 10.8 -sdk_version 10.9 %s -o %t -dylib %p/Inputs/x86_64/libSystem.yaml && llvm-objdump --private-headers %t | FileCheck %s --check-prefix=SDK_VERSION
 
 --- !mach-o
 arch:            x86_64
diff --git a/lldb/bindings/interface/SBAddress.i b/lldb/bindings/interface/SBAddress.i
index 4658534d153ea..de277607d8f5e 100644
--- a/lldb/bindings/interface/SBAddress.i
+++ b/lldb/bindings/interface/SBAddress.i
@@ -154,7 +154,7 @@ public:
 
         def __int__(self):
             '''Convert an address to a load address if there is a process and that process is alive, or to a file address otherwise.'''
-            if process.is_alive:
+            if process and process.is_alive:
                 return self.GetLoadAddress (target)
             else:
                 return self.GetFileAddress ()
diff --git a/lldb/include/lldb/Target/StackFrame.h b/lldb/include/lldb/Target/StackFrame.h
index c21916be44aea..667428e7d7498 100644
--- a/lldb/include/lldb/Target/StackFrame.h
+++ b/lldb/include/lldb/Target/StackFrame.h
@@ -367,12 +367,6 @@ class StackFrame : public ExecutionContextScope,
   /// may have limited support for inspecting variables.
   bool IsArtificial() const;
 
-  /// Query whether this frame behaves like the zeroth frame, in the sense
-  /// that its pc value might not immediately follow a call (and thus might
-  /// be the first address of its function).  True for actual frame zero as
-  /// well as any other frame with the same trait.
-  bool BehavesLikeZerothFrame() const;
-
   /// Query this frame to find what frame it is in this Thread's
   /// StackFrameList.
   ///
@@ -517,6 +511,11 @@ class StackFrame : public ExecutionContextScope,
   bool m_cfa_is_valid; // Does this frame have a CFA?  Different from CFA ==
                        // LLDB_INVALID_ADDRESS
   Kind m_stack_frame_kind;
+
+  // Whether this frame behaves like the zeroth frame, in the sense
+  // that its pc value might not immediately follow a call (and thus might
+  // be the first address of its function). True for actual frame zero as
+  // well as any other frame with the same trait.
   bool m_behaves_like_zeroth_frame;
   lldb::VariableListSP m_variable_list_sp;
   ValueObjectList m_variable_list_value_objects; // Value objects for each
diff --git a/lldb/include/lldb/Target/StackFrameRecognizer.h b/lldb/include/lldb/Target/StackFrameRecognizer.h
index 3e4d6abe7aeb6..6be506391deb2 100644
--- a/lldb/include/lldb/Target/StackFrameRecognizer.h
+++ b/lldb/include/lldb/Target/StackFrameRecognizer.h
@@ -101,8 +101,8 @@ class ScriptedStackFrameRecognizer : public StackFrameRecognizer {
 class StackFrameRecognizerManager {
 public:
   static void AddRecognizer(lldb::StackFrameRecognizerSP recognizer,
-                            ConstString module, ConstString symbol,
-                            ConstString alternate_symbol,
+                            ConstString module,
+                            llvm::ArrayRef<ConstString> symbols,
                             bool first_instruction_only = true);
 
   static void AddRecognizer(lldb::StackFrameRecognizerSP recognizer,
@@ -110,11 +110,11 @@ class StackFrameRecognizerManager {
                             lldb::RegularExpressionSP symbol,
                             bool first_instruction_only = true);
 
-  static void ForEach(
-      std::function<void(uint32_t recognizer_id, std::string recognizer_name,
-                         std::string module, std::string symbol,
-                         std::string alternate_symbol, bool regexp)> const
-          &callback);
+  static void
+  ForEach(std::function<void(uint32_t recognizer_id,
+                             std::string recognizer_name, std::string module,
+                             llvm::ArrayRef<ConstString> symbols,
+                             bool regexp)> const &callback);
 
   static bool RemoveRecognizerWithID(uint32_t recognizer_id);
 
diff --git a/lldb/packages/Python/lldbsuite/test/lldbutil.py b/lldb/packages/Python/lldbsuite/test/lldbutil.py
index d603091677f3d..ef0df90c416ea 100644
--- a/lldb/packages/Python/lldbsuite/test/lldbutil.py
+++ b/lldb/packages/Python/lldbsuite/test/lldbutil.py
@@ -797,7 +797,7 @@ def run_to_breakpoint_do_run(test, target, bkpt, launch_info = None,
         test.assertEqual(num_threads, 1, "Expected 1 thread to stop at breakpoint, %d did."%(num_threads))
     else:
         test.assertGreater(num_threads, 0, "No threads stopped at breakpoint")
-        
+
     thread = threads[0]
     return (target, process, thread, bkpt)
 
diff --git a/lldb/source/Commands/CommandObjectExpression.cpp b/lldb/source/Commands/CommandObjectExpression.cpp
index 388f9f0af66ac..7d8de573df0e8 100644
--- a/lldb/source/Commands/CommandObjectExpression.cpp
+++ b/lldb/source/Commands/CommandObjectExpression.cpp
@@ -403,9 +403,9 @@ CommandObjectExpression::GetEvalOptions(const Target &target) {
 }
 
 bool CommandObjectExpression::EvaluateExpression(llvm::StringRef expr,
-                                                 Stream *output_stream,
-                                                 Stream *error_stream,
-                                                 CommandReturnObject *result) {
+                                                 Stream &output_stream,
+                                                 Stream &error_stream,
+                                                 CommandReturnObject &result) {
   // Don't use m_exe_ctx as this might be called asynchronously after the
   // command object DoExecute has finished when doing multi-line expression
   // that use an input reader...
@@ -425,11 +425,10 @@ bool CommandObjectExpression::EvaluateExpression(llvm::StringRef expr,
 
   // We only tell you about the FixIt if we applied it.  The compiler errors
   // will suggest the FixIt if it parsed.
-  if (error_stream && !m_fixed_expression.empty() &&
-      target->GetEnableNotifyAboutFixIts()) {
+  if (!m_fixed_expression.empty() && target->GetEnableNotifyAboutFixIts()) {
     if (success == eExpressionCompleted)
-      error_stream->Printf("  Fix-it applied, fixed expression was: \n    %s\n",
-                           m_fixed_expression.c_str());
+      error_stream.Printf("  Fix-it applied, fixed expression was: \n    %s\n",
+                          m_fixed_expression.c_str());
   }
 
   if (result_valobj_sp) {
@@ -443,10 +442,10 @@ bool CommandObjectExpression::EvaluateExpression(llvm::StringRef expr,
         if (m_varobj_options.elem_count > 0) {
           Status error(CanBeUsedForElementCountPrinting(*result_valobj_sp));
           if (error.Fail()) {
-            result->AppendErrorWithFormat(
+            result.AppendErrorWithFormat(
                 "expression cannot be used with --element-count %s\n",
                 error.AsCString(""));
-            result->SetStatus(eReturnStatusFailed);
+            result.SetStatus(eReturnStatusFailed);
             return false;
           }
         }
@@ -456,36 +455,33 @@ bool CommandObjectExpression::EvaluateExpression(llvm::StringRef expr,
         options.SetVariableFormatDisplayLanguage(
             result_valobj_sp->GetPreferredDisplayLanguage());
 
-        result_valobj_sp->Dump(*output_stream, options);
+        result_valobj_sp->Dump(output_stream, options);
 
-        if (result)
-          result->SetStatus(eReturnStatusSuccessFinishResult);
+        result.SetStatus(eReturnStatusSuccessFinishResult);
       }
     } else {
       if (result_valobj_sp->GetError().GetError() ==
           UserExpression::kNoResult) {
         if (format != eFormatVoid && GetDebugger().GetNotifyVoid()) {
-          error_stream->PutCString("(void)\n");
+          error_stream.PutCString("(void)\n");
         }
 
-        if (result)
-          result->SetStatus(eReturnStatusSuccessFinishResult);
+        result.SetStatus(eReturnStatusSuccessFinishResult);
       } else {
         const char *error_cstr = result_valobj_sp->GetError().AsCString();
         if (error_cstr && error_cstr[0]) {
           const size_t error_cstr_len = strlen(error_cstr);
           const bool ends_with_newline = error_cstr[error_cstr_len - 1] == '\n';
           if (strstr(error_cstr, "error:") != error_cstr)
-            error_stream->PutCString("error: ");
-          error_stream->Write(error_cstr, error_cstr_len);
+            error_stream.PutCString("error: ");
+          error_stream.Write(error_cstr, error_cstr_len);
           if (!ends_with_newline)
-            error_stream->EOL();
+            error_stream.EOL();
         } else {
-          error_stream->PutCString("error: unknown error\n");
+          error_stream.PutCString("error: unknown error\n");
         }
 
-        if (result)
-          result->SetStatus(eReturnStatusFailed);
+        result.SetStatus(eReturnStatusFailed);
       }
     }
   }
@@ -502,7 +498,8 @@ void CommandObjectExpression::IOHandlerInputComplete(IOHandler &io_handler,
   StreamFileSP output_sp = io_handler.GetOutputStreamFileSP();
   StreamFileSP error_sp = io_handler.GetErrorStreamFileSP();
 
-  EvaluateExpression(line.c_str(), output_sp.get(), error_sp.get());
+  CommandReturnObject return_obj;
+  EvaluateExpression(line.c_str(), *output_sp, *error_sp, return_obj);
   if (output_sp)
     output_sp->Flush();
   if (error_sp)
@@ -650,8 +647,8 @@ bool CommandObjectExpression::DoExecute(llvm::StringRef command,
   }
 
   Target &target = GetSelectedOrDummyTarget();
-  if (EvaluateExpression(expr, &(result.GetOutputStream()),
-                         &(result.GetErrorStream()), &result)) {
+  if (EvaluateExpression(expr, result.GetOutputStream(),
+                         result.GetErrorStream(), result)) {
 
     if (!m_fixed_expression.empty() && target.GetEnableNotifyAboutFixIts()) {
       CommandHistory &history = m_interpreter.GetCommandHistory();
diff --git a/lldb/source/Commands/CommandObjectExpression.h b/lldb/source/Commands/CommandObjectExpression.h
index b3bee3ca0e8cc..ddee9c36924d7 100644
--- a/lldb/source/Commands/CommandObjectExpression.h
+++ b/lldb/source/Commands/CommandObjectExpression.h
@@ -71,9 +71,8 @@ class CommandObjectExpression : public CommandObjectRaw,
   /// expression in the given target.
   EvaluateExpressionOptions GetEvalOptions(const Target &target);
 
-  bool EvaluateExpression(llvm::StringRef expr, Stream *output_stream,
-                          Stream *error_stream,
-                          CommandReturnObject *result = nullptr);
+  bool EvaluateExpression(llvm::StringRef expr, Stream &output_stream,
+                          Stream &error_stream, CommandReturnObject &result);
 
   void GetMultilineExpression();
 
diff --git a/lldb/source/Commands/CommandObjectFrame.cpp b/lldb/source/Commands/CommandObjectFrame.cpp
index baf64e5c884d6..4fef9f4847e00 100644
--- a/lldb/source/Commands/CommandObjectFrame.cpp
+++ b/lldb/source/Commands/CommandObjectFrame.cpp
@@ -746,7 +746,7 @@ class CommandObjectFrameRecognizerAdd : public CommandObjectParsed {
         m_module = std::string(option_arg);
         break;
       case 'n':
-        m_function = std::string(option_arg);
+        m_symbols.push_back(std::string(option_arg));
         break;
       case 'x':
         m_regex = true;
@@ -760,7 +760,7 @@ class CommandObjectFrameRecognizerAdd : public CommandObjectParsed {
 
     void OptionParsingStarting(ExecutionContext *execution_context) override {
       m_module = "";
-      m_function = "";
+      m_symbols.clear();
       m_class_name = "";
       m_regex = false;
     }
@@ -772,7 +772,7 @@ class CommandObjectFrameRecognizerAdd : public CommandObjectParsed {
     // Instance variables to hold the values for command options.
     std::string m_class_name;
     std::string m_module;
-    std::string m_function;
+    std::vector<std::string> m_symbols;
     bool m_regex;
   };
 
@@ -854,9 +854,18 @@ bool CommandObjectFrameRecognizerAdd::DoExecute(Args &command,
     return false;
   }
 
-  if (m_options.m_function.empty()) {
-    result.AppendErrorWithFormat("%s needs a function name (-n argument).\n",
-                                 m_cmd_name.c_str());
+  if (m_options.m_symbols.empty()) {
+    result.AppendErrorWithFormat(
+        "%s needs at least one symbol name (-n argument).\n",
+        m_cmd_name.c_str());
+    result.SetStatus(eReturnStatusFailed);
+    return false;
+  }
+
+  if (m_options.m_regex && m_options.m_symbols.size() > 1) {
+    result.AppendErrorWithFormat(
+        "%s needs only one symbol regular expression (-n argument).\n",
+        m_cmd_name.c_str());
     result.SetStatus(eReturnStatusFailed);
     return false;
   }
@@ -876,12 +885,13 @@ bool CommandObjectFrameRecognizerAdd::DoExecute(Args &command,
     auto module =
         RegularExpressionSP(new RegularExpression(m_options.m_module));
     auto func =
-        RegularExpressionSP(new RegularExpression(m_options.m_function));
+        RegularExpressionSP(new RegularExpression(m_options.m_symbols.front()));
     StackFrameRecognizerManager::AddRecognizer(recognizer_sp, module, func);
   } else {
     auto module = ConstString(m_options.m_module);
-    auto func = ConstString(m_options.m_function);
-    StackFrameRecognizerManager::AddRecognizer(recognizer_sp, module, func, {});
+    std::vector<ConstString> symbols(m_options.m_symbols.begin(),
+                                     m_options.m_symbols.end());
+    StackFrameRecognizerManager::AddRecognizer(recognizer_sp, module, symbols);
   }
 #endif
 
@@ -958,9 +968,9 @@ class CommandObjectFrameRecognizerList : public CommandObjectParsed {
   bool DoExecute(Args &command, CommandReturnObject &result) override {
     bool any_printed = false;
     StackFrameRecognizerManager::ForEach(
-        [&result, &any_printed](uint32_t recognizer_id, std::string name,
-                                std::string module, std::string symbol,
-                                std::string alternate_symbol, bool regexp) {
+        [&result, &any_printed](
+            uint32_t recognizer_id, std::string name, std::string module,
+            llvm::ArrayRef<ConstString> symbols, bool regexp) {
           Stream &stream = result.GetOutputStream();
 
           if (name.empty())
@@ -969,10 +979,9 @@ class CommandObjectFrameRecognizerList : public CommandObjectParsed {
           stream << std::to_string(recognizer_id) << ": " << name;
           if (!module.empty())
             stream << ", module " << module;
-          if (!symbol.empty())
-            stream << ", function " << symbol;
-          if (!alternate_symbol.empty())
-            stream << ", symbol " << alternate_symbol;
+          if (!symbols.empty())
+            for (auto &symbol : symbols)
+              stream << ", symbol " << symbol;
           if (regexp)
             stream << " (regexp)";
 
diff --git a/lldb/source/Commands/Options.td b/lldb/source/Commands/Options.td
index fa8f5224cf539..b8a142678b28c 100644
--- a/lldb/source/Commands/Options.td
+++ b/lldb/source/Commands/Options.td
@@ -389,7 +389,8 @@ let Command = "frame recognizer add" in {
     "to.">;
   def frame_recognizer_function : Option<"function", "n">, Arg<"Name">,
     Completion<"Symbol">,
-    Desc<"Name of the function that this recognizer applies to.">;
+    Desc<"Name of the function that this recognizer applies to. "
+         "Can be specified more than once except if -x|--regex is provided.">;
   def frame_recognizer_python_class : Option<"python-class", "l">, Group<2>,
     Arg<"PythonClass">,
     Desc<"Give the name of a Python class to use for this frame recognizer.">;
diff --git a/lldb/source/Host/CMakeLists.txt b/lldb/source/Host/CMakeLists.txt
index ac8655f3dd886..3571404320102 100644
--- a/lldb/source/Host/CMakeLists.txt
+++ b/lldb/source/Host/CMakeLists.txt
@@ -115,7 +115,7 @@ else()
 
   elseif (CMAKE_SYSTEM_NAME MATCHES "NetBSD")
     add_host_subdirectory(netbsd
-      netbsd/Host.cpp
+      netbsd/HostNetBSD.cpp
       netbsd/HostInfoNetBSD.cpp
       )
 
diff --git a/lldb/source/Host/freebsd/Host.cpp b/lldb/source/Host/freebsd/Host.cpp
index 1e8981b00e538..09547e48afa97 100644
--- a/lldb/source/Host/freebsd/Host.cpp
+++ b/lldb/source/Host/freebsd/Host.cpp
@@ -149,8 +149,8 @@ static bool GetFreeBSDProcessUserAndGroup(ProcessInstanceInfo &process_info) {
   return false;
 }
 
-uint32_t Host::FindProcesses(const ProcessInstanceInfoMatch &match_info,
-                             ProcessInstanceInfoList &process_infos) {
+uint32_t Host::FindProcessesImpl(const ProcessInstanceInfoMatch &match_info,
+                                 ProcessInstanceInfoList &process_infos) {
   const ::pid_t our_pid = ::getpid();
   const ::uid_t our_uid = ::getuid();
   std::vector<struct kinfo_proc> kinfos;
diff --git a/lldb/source/Host/netbsd/Host.cpp b/lldb/source/Host/netbsd/HostNetBSD.cpp
similarity index 99%
rename from lldb/source/Host/netbsd/Host.cpp
rename to lldb/source/Host/netbsd/HostNetBSD.cpp
index 57f985129a613..4708fb45deed0 100644
--- a/lldb/source/Host/netbsd/Host.cpp
+++ b/lldb/source/Host/netbsd/HostNetBSD.cpp
@@ -1,4 +1,4 @@
-//===-- source/Host/netbsd/Host.cpp ---------------------------------------===//
+//===-- source/Host/netbsd/HostNetBSD.cpp ---------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
diff --git a/lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp b/lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
index e70ab1ce8d5ae..b9442872c785a 100644
--- a/lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
+++ b/lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
@@ -427,7 +427,7 @@ bool IRForTarget::RewriteObjCConstString(llvm::GlobalVariable *ns_str,
         m_execution_unit.FindSymbol(g_CFStringCreateWithBytes_str, 
                                     missing_weak);
     if (CFStringCreateWithBytes_addr == LLDB_INVALID_ADDRESS || missing_weak) {
-        log->PutCString("Couldn't find CFStringCreateWithBytes in the target");
+      LLDB_LOG(log, "Couldn't find CFStringCreateWithBytes in the target");
 
       m_error_stream.Printf("Error [IRForTarget]: Rewriting an Objective-C "
                             "constant string requires "
diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
index cb1d808d0f1e0..9b3dbb166b687 100644
--- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
+++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
@@ -2685,9 +2685,10 @@ static void RegisterObjCExceptionRecognizer() {
     FileSpec module;
     ConstString function;
     std::tie(module, function) = AppleObjCRuntime::GetExceptionThrowLocation();
+    std::vector<ConstString> symbols = {function};
     StackFrameRecognizerManager::AddRecognizer(
         StackFrameRecognizerSP(new ObjCExceptionThrowFrameRecognizer()),
-        module.GetFilename(), function, /*alternate_symbol*/ {},
+        module.GetFilename(), symbols,
         /*first_instruction_only*/ true);
   });
 }
diff --git a/lldb/source/Plugins/MemoryHistory/asan/MemoryHistoryASan.cpp b/lldb/source/Plugins/MemoryHistory/asan/MemoryHistoryASan.cpp
index 4b9da8f76fd24..333113a0b17a5 100644
--- a/lldb/source/Plugins/MemoryHistory/asan/MemoryHistoryASan.cpp
+++ b/lldb/source/Plugins/MemoryHistory/asan/MemoryHistoryASan.cpp
@@ -138,7 +138,12 @@ static void CreateHistoryThreadFromValueObject(ProcessSP process_sp,
     pcs.push_back(pc);
   }
 
-  HistoryThread *history_thread = new HistoryThread(*process_sp, tid, pcs);
+  // The ASAN runtime already massages the return addresses into call
+  // addresses, we don't want LLDB's unwinder to try to locate the previous
+  // instruction again as this might lead to us reporting a different line.
+  bool pcs_are_call_addresses = true;
+  HistoryThread *history_thread =
+      new HistoryThread(*process_sp, tid, pcs, pcs_are_call_addresses);
   ThreadSP new_thread_sp(history_thread);
   std::ostringstream thread_name_with_number;
   thread_name_with_number << thread_name << " Thread " << tid;
diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
index b21f1a20ba731..aa1f8994ecb66 100644
--- a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
+++ b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
@@ -1268,76 +1268,6 @@ void PlatformDarwin::CalculateTrapHandlerSymbolNames() {
   m_trap_handlers.push_back(ConstString("_sigtramp"));
 }
 
-static const char *const sdk_strings[] = {
-    "MacOSX", "iPhoneSimulator", "iPhoneOS",
-};
-
-static FileSpec CheckPathForXcode(const FileSpec &fspec) {
-  if (FileSystem::Instance().Exists(fspec)) {
-    const char substr[] = ".app/Contents";
-
-    std::string path_to_shlib = fspec.GetPath();
-    size_t pos = path_to_shlib.rfind(substr);
-    if (pos != std::string::npos) {
-      path_to_shlib.erase(pos + strlen(substr));
-      FileSpec ret(path_to_shlib);
-
-      FileSpec xcode_binary_path = ret;
-      xcode_binary_path.AppendPathComponent("MacOS");
-      xcode_binary_path.AppendPathComponent("Xcode");
-
-      if (FileSystem::Instance().Exists(xcode_binary_path)) {
-        return ret;
-      }
-    }
-  }
-  return FileSpec();
-}
-
-static FileSpec GetXcodeContentsPath() {
-  static FileSpec g_xcode_filespec;
-  static llvm::once_flag g_once_flag;
-  llvm::call_once(g_once_flag, []() {
-
-    FileSpec fspec;
-
-    // First get the program file spec. If lldb.so or LLDB.framework is running
-    // in a program and that program is Xcode, the path returned with be the
-    // path to Xcode.app/Contents/MacOS/Xcode, so this will be the correct
-    // Xcode to use.
-    fspec = HostInfo::GetProgramFileSpec();
-
-    if (fspec) {
-      // Ignore the current binary if it is python.
-      std::string basename_lower = fspec.GetFilename().GetCString();
-      std::transform(basename_lower.begin(), basename_lower.end(),
-                     basename_lower.begin(), tolower);
-      if (basename_lower != "python") {
-        g_xcode_filespec = CheckPathForXcode(fspec);
-      }
-    }
-
-    // Next check DEVELOPER_DIR environment variable
-    if (!g_xcode_filespec) {
-      const char *developer_dir_env_var = getenv("DEVELOPER_DIR");
-      if (developer_dir_env_var && developer_dir_env_var[0]) {
-        FileSpec developer_dir_spec = FileSpec(developer_dir_env_var);
-        FileSystem::Instance().Resolve(developer_dir_spec);
-        g_xcode_filespec = CheckPathForXcode(developer_dir_spec);
-      }
-
-      // Fall back to using "xcode-select" to find the selected Xcode
-      if (!g_xcode_filespec) {
-        FileSpec xcode_select_path(GetXcodeSelectPath());
-        xcode_select_path.RemoveLastPathComponent();
-        g_xcode_filespec = CheckPathForXcode(xcode_select_path);
-      }
-    }
-  });
-
-  return g_xcode_filespec;
-}
-
 static FileSpec GetCommandLineToolsLibraryPath() {
   static FileSpec g_command_line_tools_filespec;
 
@@ -1359,7 +1289,14 @@ bool PlatformDarwin::SDKSupportsModules(SDKType sdk_type,
     return version >= llvm::VersionTuple(10, 10);
   case SDKType::iPhoneOS:
   case SDKType::iPhoneSimulator:
+  case SDKType::AppleTVOS:
+  case SDKType::AppleTVSimulator:
     return version >= llvm::VersionTuple(8);
+  case SDKType::watchOS:
+  case SDKType::WatchSimulator:
+    return version >= llvm::VersionTuple(6);
+  default:
+    return false;
   }
 
   return false;
@@ -1372,10 +1309,12 @@ bool PlatformDarwin::SDKSupportsModules(SDKType desired_type,
   if (last_path_component) {
     const llvm::StringRef sdk_name = last_path_component.GetStringRef();
 
-    if (!sdk_name.startswith(sdk_strings[desired_type]))
+    const std::string sdk_name_lower = sdk_name.lower();
+    const llvm::StringRef sdk_string = GetSDKNameForType(desired_type);
+    if (!llvm::StringRef(sdk_name_lower).startswith(sdk_string))
       return false;
-    auto version_part =
-        sdk_name.drop_front(strlen(sdk_strings[desired_type]));
+
+    auto version_part = sdk_name.drop_front(sdk_string.size());
     version_part.consume_back(".sdk");
 
     llvm::VersionTuple version;
@@ -1427,14 +1366,7 @@ FileSpec PlatformDarwin::FindSDKInXcodeForModules(SDKType sdk_type,
 }
 
 FileSpec PlatformDarwin::GetSDKDirectoryForModules(SDKType sdk_type) {
-  switch (sdk_type) {
-  case SDKType::MacOSX:
-  case SDKType::iPhoneSimulator:
-  case SDKType::iPhoneOS:
-    break;
-  }
-
-  FileSpec sdks_spec = GetXcodeContentsPath();
+  FileSpec sdks_spec = GetXcodeContentsDirectory();
   sdks_spec.AppendPathComponent("Developer");
   sdks_spec.AppendPathComponent("Platforms");
 
@@ -1448,6 +1380,8 @@ FileSpec PlatformDarwin::GetSDKDirectoryForModules(SDKType sdk_type) {
   case SDKType::iPhoneOS:
     sdks_spec.AppendPathComponent("iPhoneOS.platform");
     break;
+  default:
+    llvm_unreachable("unsupported sdk");
   }
 
   sdks_spec.AppendPathComponent("Developer");
@@ -1656,6 +1590,8 @@ void PlatformDarwin::AddClangModuleCompilationOptionsForSDKType(
     use_current_os_version = false;
 #endif
     break;
+  default:
+    break;
   }
 
   llvm::VersionTuple version;
@@ -1685,6 +1621,9 @@ void PlatformDarwin::AddClangModuleCompilationOptionsForSDKType(
     case SDKType::MacOSX:
       minimum_version_option.PutCString("-mmacosx-version-min=");
       minimum_version_option.PutCString(version.getAsString());
+      break;
+    default:
+      llvm_unreachable("unsupported sdk");
     }
     options.push_back(std::string(minimum_version_option.GetString()));
   }
@@ -1744,8 +1683,7 @@ llvm::VersionTuple PlatformDarwin::GetOSVersion(Process *process) {
 
 lldb_private::FileSpec PlatformDarwin::LocateExecutable(const char *basename) {
   // A collection of SBFileSpec whose SBFileSpec.m_directory members are filled
-  // in with
-  // any executable directories that should be searched.
+  // in with any executable directories that should be searched.
   static std::vector<FileSpec> g_executable_dirs;
 
   // Find the global list of directories that we will search for executables
@@ -1754,7 +1692,7 @@ lldb_private::FileSpec PlatformDarwin::LocateExecutable(const char *basename) {
   llvm::call_once(g_once_flag, []() {
 
     // When locating executables, trust the DEVELOPER_DIR first if it is set
-    FileSpec xcode_contents_dir = GetXcodeContentsPath();
+    FileSpec xcode_contents_dir = GetXcodeContentsDirectory();
     if (xcode_contents_dir) {
       FileSpec xcode_lldb_resources = xcode_contents_dir;
       xcode_lldb_resources.AppendPathComponent("SharedFrameworks");
@@ -1816,12 +1754,10 @@ PlatformDarwin::LaunchProcess(lldb_private::ProcessLaunchInfo &launch_info) {
   return PlatformPOSIX::LaunchProcess(launch_info);
 }
 
-lldb_private::Status
-PlatformDarwin::FindBundleBinaryInExecSearchPaths (const ModuleSpec &module_spec, Process *process, 
-                                                   ModuleSP &module_sp, 
-                                                   const FileSpecList *module_search_paths_ptr, 
-                                                   ModuleSP *old_module_sp_ptr, bool *did_create_ptr)
-{
+lldb_private::Status PlatformDarwin::FindBundleBinaryInExecSearchPaths(
+    const ModuleSpec &module_spec, Process *process, ModuleSP &module_sp,
+    const FileSpecList *module_search_paths_ptr, ModuleSP *old_module_sp_ptr,
+    bool *did_create_ptr) {
   const FileSpec &platform_file = module_spec.GetFileSpec();
   // See if the file is present in any of the module_search_paths_ptr
   // directories.
@@ -1892,3 +1828,134 @@ PlatformDarwin::FindBundleBinaryInExecSearchPaths (const ModuleSpec &module_spec
   }
   return Status();
 }
+
+std::string
+PlatformDarwin::FindXcodeContentsDirectoryInPath(llvm::StringRef path) {
+  auto begin = llvm::sys::path::begin(path);
+  auto end = llvm::sys::path::end(path);
+
+  // Iterate over the path components until we find something that ends with
+  // .app. If the next component is Contents then we've found the Contents
+  // directory.
+  for (auto it = begin; it != end; ++it) {
+    if (it->endswith(".app")) {
+      auto next = it;
+      if (++next != end && *next == "Contents") {
+        llvm::SmallString<128> buffer;
+        llvm::sys::path::append(buffer, begin, ++next,
+                                llvm::sys::path::Style::posix);
+        return buffer.str().str();
+      }
+    }
+  }
+
+  return {};
+}
+
+llvm::StringRef PlatformDarwin::GetSDKNameForType(SDKType type) {
+  switch (type) {
+  case MacOSX:
+    return "macosx";
+  case iPhoneSimulator:
+    return "iphonesimulator";
+  case iPhoneOS:
+    return "iphoneos";
+  case AppleTVSimulator:
+    return "appletvsimulator";
+  case AppleTVOS:
+    return "appletvos";
+  case WatchSimulator:
+    return "watchsimulator";
+  case watchOS:
+    return "watchos";
+  case bridgeOS:
+    return "bridgeos";
+  case Linux:
+    return "linux";
+  case numSDKTypes:
+  case unknown:
+    return "";
+  }
+  llvm_unreachable("unhandled switch case");
+}
+
+FileSpec PlatformDarwin::GetXcodeSDK(SDKType type) {
+  std::string xcrun_cmd =
+      "xcrun --show-sdk-path --sdk " + GetSDKNameForType(type).str();
+
+  int status = 0;
+  int signo = 0;
+  std::string output_str;
+  lldb_private::Status error =
+      Host::RunShellCommand(xcrun_cmd.c_str(), FileSpec(), &status, &signo,
+                            &output_str, std::chrono::seconds(15));
+
+  // Check that xcrun return something useful.
+  if (status != 0 || output_str.empty())
+    return {};
+
+  // Convert to a StringRef so we can manipulate the string without modifying
+  // the underlying data.
+  llvm::StringRef output(output_str);
+
+  // Remove any trailing newline characters.
+  output = output.rtrim();
+
+  // Strip any leading newline characters and everything before them.
+  const size_t last_newline = output.rfind('\n');
+  if (last_newline != llvm::StringRef::npos)
+    output = output.substr(last_newline + 1);
+
+  // Whatever is left in output should be a valid path.
+  if (!FileSystem::Instance().Exists(output))
+    return {};
+
+  // Find the contents dir in the xcrun provided path.
+  std::string xcode_contents_dir = FindXcodeContentsDirectoryInPath(output);
+  if (xcode_contents_dir.empty())
+    return {};
+
+  return FileSpec(xcode_contents_dir);
+}
+
+FileSpec PlatformDarwin::GetXcodeContentsDirectory() {
+  static FileSpec g_xcode_contents_path;
+  static std::once_flag g_once_flag;
+  std::call_once(g_once_flag, [&]() {
+    // Try the shlib dir first.
+    if (FileSpec fspec = HostInfo::GetShlibDir()) {
+      if (FileSystem::Instance().Exists(fspec)) {
+        std::string xcode_contents_dir =
+            FindXcodeContentsDirectoryInPath(fspec.GetPath());
+        if (!xcode_contents_dir.empty()) {
+          g_xcode_contents_path = FileSpec(xcode_contents_dir);
+          return;
+        }
+      }
+    }
+
+    if (const char *developer_dir_env_var = getenv("DEVELOPER_DIR")) {
+      FileSpec fspec(developer_dir_env_var);
+      if (FileSystem::Instance().Exists(fspec)) {
+        std::string xcode_contents_dir =
+            FindXcodeContentsDirectoryInPath(fspec.GetPath());
+        if (!xcode_contents_dir.empty()) {
+          g_xcode_contents_path = FileSpec(xcode_contents_dir);
+          return;
+        }
+      }
+    }
+
+    if (FileSpec fspec = GetXcodeSDK(SDKType::MacOSX)) {
+      if (FileSystem::Instance().Exists(fspec)) {
+        std::string xcode_contents_dir =
+            FindXcodeContentsDirectoryInPath(fspec.GetPath());
+        if (!xcode_contents_dir.empty()) {
+          g_xcode_contents_path = FileSpec(xcode_contents_dir);
+          return;
+        }
+      }
+    }
+  });
+  return g_xcode_contents_path;
+}
diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
index bd23d50178b77..d385712db8e63 100644
--- a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
+++ b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
@@ -79,15 +79,27 @@ class PlatformDarwin : public PlatformPOSIX {
   static std::tuple<llvm::VersionTuple, llvm::StringRef>
   ParseVersionBuildDir(llvm::StringRef str);
 
-  enum SDKType : unsigned {
+  enum SDKType : int {
     MacOSX = 0,
     iPhoneSimulator,
     iPhoneOS,
+    AppleTVSimulator,
+    AppleTVOS,
+    WatchSimulator,
+    watchOS,
+    bridgeOS,
+    Linux,
+    numSDKTypes,
+    unknown = -1
   };
 
   llvm::Expected<lldb_private::StructuredData::DictionarySP>
   FetchExtendedCrashInformation(lldb_private::Process &process) override;
 
+  static llvm::StringRef GetSDKNameForType(SDKType type);
+  static lldb_private::FileSpec GetXcodeSDK(SDKType type);
+  static lldb_private::FileSpec GetXcodeContentsDirectory();
+
 protected:
   struct CrashInfoAnnotations {
     uint64_t version;          // unsigned long
@@ -154,13 +166,15 @@ class PlatformDarwin : public PlatformPOSIX {
 
   const char *GetDeveloperDirectory();
 
-  lldb_private::Status
-  FindBundleBinaryInExecSearchPaths (const lldb_private::ModuleSpec &module_spec, lldb_private::Process *process,
-                                     lldb::ModuleSP &module_sp, const lldb_private::FileSpecList *module_search_paths_ptr, 
-                                     lldb::ModuleSP *old_module_sp_ptr, bool *did_create_ptr);
+  lldb_private::Status FindBundleBinaryInExecSearchPaths(
+      const lldb_private::ModuleSpec &module_spec,
+      lldb_private::Process *process, lldb::ModuleSP &module_sp,
+      const lldb_private::FileSpecList *module_search_paths_ptr,
+      lldb::ModuleSP *old_module_sp_ptr, bool *did_create_ptr);
 
-  std::string m_developer_directory;
+  static std::string FindXcodeContentsDirectoryInPath(llvm::StringRef path);
 
+  std::string m_developer_directory;
 
 private:
   DISALLOW_COPY_AND_ASSIGN(PlatformDarwin);
diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp b/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
index 38de91a30cf65..5efb041367e3c 100644
--- a/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
+++ b/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
@@ -185,73 +185,35 @@ PlatformMacOSX::~PlatformMacOSX() {}
 
 ConstString PlatformMacOSX::GetSDKDirectory(lldb_private::Target &target) {
   ModuleSP exe_module_sp(target.GetExecutableModule());
-  if (exe_module_sp) {
-    ObjectFile *objfile = exe_module_sp->GetObjectFile();
-    if (objfile) {
-      std::string xcode_contents_path;
-      std::string default_xcode_sdk;
-      FileSpec fspec;
-      llvm::VersionTuple version = objfile->GetSDKVersion();
-      if (!version.empty()) {
-        fspec = HostInfo::GetShlibDir();
-        if (fspec) {
-          std::string path;
-          xcode_contents_path = fspec.GetPath();
-          size_t pos = xcode_contents_path.find("/Xcode.app/Contents/");
-          if (pos != std::string::npos) {
-            // LLDB.framework is inside an Xcode app bundle, we can locate the
-            // SDK from here
-            xcode_contents_path.erase(pos + strlen("/Xcode.app/Contents/"));
-          } else {
-            xcode_contents_path.clear();
-            // Use the selected Xcode
-            int status = 0;
-            int signo = 0;
-            std::string output;
-            const char *command = "xcrun -sdk macosx --show-sdk-path";
-            lldb_private::Status error = RunShellCommand(
-                command,    // shell command to run
-                FileSpec(), // current working directory
-                &status,    // Put the exit status of the process in here
-                &signo,     // Put the signal that caused the process to exit in
-                            // here
-                &output, // Get the output from the command and place it in this
-                         // string
-                std::chrono::seconds(3));
-            if (status == 0 && !output.empty()) {
-              size_t first_non_newline = output.find_last_not_of("\r\n");
-              if (first_non_newline != std::string::npos)
-                output.erase(first_non_newline + 1);
-              default_xcode_sdk = output;
-
-              pos = default_xcode_sdk.find("/Xcode.app/Contents/");
-              if (pos != std::string::npos)
-                xcode_contents_path = default_xcode_sdk.substr(
-                    0, pos + strlen("/Xcode.app/Contents/"));
-            }
-          }
-        }
-
-        if (!xcode_contents_path.empty()) {
-          StreamString sdk_path;
-          sdk_path.Printf("%sDeveloper/Platforms/MacOSX.platform/Developer/"
-                          "SDKs/MacOSX%u.%u.sdk",
-                          xcode_contents_path.c_str(), version.getMajor(),
-                          version.getMinor().getValue());
-          fspec.SetFile(sdk_path.GetString(), FileSpec::Style::native);
-          if (FileSystem::Instance().Exists(fspec))
-            return ConstString(sdk_path.GetString());
-        }
+  if (!exe_module_sp)
+    return {};
+
+  ObjectFile *objfile = exe_module_sp->GetObjectFile();
+  if (!objfile)
+    return {};
+
+  llvm::VersionTuple version = objfile->GetSDKVersion();
+  if (version.empty())
+    return {};
+
+  // First try to find an SDK that matches the given SDK version.
+  if (FileSpec fspec = GetXcodeContentsDirectory()) {
+    StreamString sdk_path;
+    sdk_path.Printf("%s/Developer/Platforms/MacOSX.platform/Developer/"
+                    "SDKs/MacOSX%u.%u.sdk",
+                    fspec.GetPath().c_str(), version.getMajor(),
+                    version.getMinor().getValue());
+    if (FileSystem::Instance().Exists(fspec))
+      return ConstString(sdk_path.GetString());
+  }
 
-        if (!default_xcode_sdk.empty()) {
-          fspec.SetFile(default_xcode_sdk, FileSpec::Style::native);
-          if (FileSystem::Instance().Exists(fspec))
-            return ConstString(default_xcode_sdk);
-        }
-      }
-    }
+  // Use the default SDK as a fallback.
+  if (FileSpec fspec = GetXcodeSDK(SDKType::MacOSX)) {
+    if (FileSystem::Instance().Exists(fspec))
+      return ConstString(fspec.GetPath());
   }
-  return ConstString();
+
+  return {};
 }
 
 Status PlatformMacOSX::GetSymbolFile(const FileSpec &platform_file,
diff --git a/lldb/source/Plugins/Process/FreeBSD/FreeBSDThread.cpp b/lldb/source/Plugins/Process/FreeBSD/FreeBSDThread.cpp
index c01ab750b9481..32c6a440db590 100644
--- a/lldb/source/Plugins/Process/FreeBSD/FreeBSDThread.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/FreeBSDThread.cpp
@@ -14,9 +14,6 @@
 #include <sys/types.h>
 #include <sys/user.h>
 
-#include "lldb/Target/UnixSignals.h"
-#include "lldb/Utility/State.h"
-
 #include "FreeBSDThread.h"
 #include "POSIXStopInfo.h"
 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
@@ -43,6 +40,8 @@
 #include "lldb/Target/StopInfo.h"
 #include "lldb/Target/Target.h"
 #include "lldb/Target/ThreadSpec.h"
+#include "lldb/Target/UnixSignals.h"
+#include "lldb/Target/Unwind.h"
 #include "lldb/Utility/State.h"
 #include "llvm/ADT/SmallString.h"
 
diff --git a/lldb/source/Plugins/Process/Utility/HistoryThread.cpp b/lldb/source/Plugins/Process/Utility/HistoryThread.cpp
index 815883d9e2f64..0649cd2f07de1 100644
--- a/lldb/source/Plugins/Process/Utility/HistoryThread.cpp
+++ b/lldb/source/Plugins/Process/Utility/HistoryThread.cpp
@@ -25,12 +25,13 @@ using namespace lldb_private;
 //  Constructor
 
 HistoryThread::HistoryThread(lldb_private::Process &process, lldb::tid_t tid,
-                             std::vector<lldb::addr_t> pcs)
+                             std::vector<lldb::addr_t> pcs,
+                             bool pcs_are_call_addresses)
     : Thread(process, tid, true), m_framelist_mutex(), m_framelist(),
       m_pcs(pcs), m_extended_unwind_token(LLDB_INVALID_ADDRESS), m_queue_name(),
       m_thread_name(), m_originating_unique_thread_id(tid),
       m_queue_id(LLDB_INVALID_QUEUE_ID) {
-  m_unwinder_up.reset(new HistoryUnwind(*this, pcs));
+  m_unwinder_up.reset(new HistoryUnwind(*this, pcs, pcs_are_call_addresses));
   Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_OBJECT));
   LLDB_LOGF(log, "%p HistoryThread::HistoryThread", static_cast<void *>(this));
 }
diff --git a/lldb/source/Plugins/Process/Utility/HistoryThread.h b/lldb/source/Plugins/Process/Utility/HistoryThread.h
index 434cf6af71975..a66e0f2d4207c 100644
--- a/lldb/source/Plugins/Process/Utility/HistoryThread.h
+++ b/lldb/source/Plugins/Process/Utility/HistoryThread.h
@@ -33,7 +33,8 @@ namespace lldb_private {
 class HistoryThread : public lldb_private::Thread {
 public:
   HistoryThread(lldb_private::Process &process, lldb::tid_t tid,
-                std::vector<lldb::addr_t> pcs);
+                std::vector<lldb::addr_t> pcs,
+                bool pcs_are_call_addresses = false);
 
   ~HistoryThread() override;
 
diff --git a/lldb/source/Plugins/Process/Utility/HistoryUnwind.cpp b/lldb/source/Plugins/Process/Utility/HistoryUnwind.cpp
index 93fcde72bf993..9b9522955de94 100644
--- a/lldb/source/Plugins/Process/Utility/HistoryUnwind.cpp
+++ b/lldb/source/Plugins/Process/Utility/HistoryUnwind.cpp
@@ -23,8 +23,10 @@ using namespace lldb_private;
 
 // Constructor
 
-HistoryUnwind::HistoryUnwind(Thread &thread, std::vector<lldb::addr_t> pcs)
-    : Unwind(thread), m_pcs(pcs) {}
+HistoryUnwind::HistoryUnwind(Thread &thread, std::vector<lldb::addr_t> pcs,
+                             bool pcs_are_call_addresses)
+    : Unwind(thread), m_pcs(pcs),
+      m_pcs_are_call_addresses(pcs_are_call_addresses) {}
 
 // Destructor
 
@@ -59,7 +61,10 @@ bool HistoryUnwind::DoGetFrameInfoAtIndex(uint32_t frame_idx, lldb::addr_t &cfa,
   if (frame_idx < m_pcs.size()) {
     cfa = frame_idx;
     pc = m_pcs[frame_idx];
-    behaves_like_zeroth_frame = (frame_idx == 0);
+    if (m_pcs_are_call_addresses)
+      behaves_like_zeroth_frame = true;
+    else
+      behaves_like_zeroth_frame = (frame_idx == 0);
     return true;
   }
   return false;
diff --git a/lldb/source/Plugins/Process/Utility/HistoryUnwind.h b/lldb/source/Plugins/Process/Utility/HistoryUnwind.h
index b15abd9244759..cb72b5d0a1764 100644
--- a/lldb/source/Plugins/Process/Utility/HistoryUnwind.h
+++ b/lldb/source/Plugins/Process/Utility/HistoryUnwind.h
@@ -18,7 +18,8 @@ namespace lldb_private {
 
 class HistoryUnwind : public lldb_private::Unwind {
 public:
-  HistoryUnwind(Thread &thread, std::vector<lldb::addr_t> pcs);
+  HistoryUnwind(Thread &thread, std::vector<lldb::addr_t> pcs,
+                bool pcs_are_call_addresses = false);
 
   ~HistoryUnwind() override;
 
@@ -35,6 +36,9 @@ class HistoryUnwind : public lldb_private::Unwind {
 
 private:
   std::vector<lldb::addr_t> m_pcs;
+  /// This boolean indicates that the PCs in the non-0 frames are call
+  /// addresses and not return addresses.
+  bool m_pcs_are_call_addresses;
 };
 
 } // namespace lldb_private
diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
index 1ed3e693d8d21..73bd9fb0bed81 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
@@ -810,31 +810,9 @@ GDBRemoteCommunication::CheckForPacket(const uint8_t *src, size_t src_len,
                           GDBRemotePacket::ePacketTypeRecv, total_length);
 
       // Copy the packet from m_bytes to packet_str expanding the run-length
-      // encoding in the process. Reserve enough byte for the most common case
-      // (no RLE used)
-      std ::string packet_str;
-      packet_str.reserve(m_bytes.length());
-      for (std::string::const_iterator c = m_bytes.begin() + content_start;
-           c != m_bytes.begin() + content_end; ++c) {
-        if (*c == '*') {
-          // '*' indicates RLE. Next character will give us the repeat count
-          // and previous character is what is to be repeated.
-          char char_to_repeat = packet_str.back();
-          // Number of time the previous character is repeated
-          int repeat_count = *++c + 3 - ' ';
-          // We have the char_to_repeat and repeat_count. Now push it in the
-          // packet.
-          for (int i = 0; i < repeat_count; ++i)
-            packet_str.push_back(char_to_repeat);
-        } else if (*c == 0x7d) {
-          // 0x7d is the escape character.  The next character is to be XOR'd
-          // with 0x20.
-          char escapee = *++c ^ 0x20;
-          packet_str.push_back(escapee);
-        } else {
-          packet_str.push_back(*c);
-        }
-      }
+      // encoding in the process.
+      std ::string packet_str =
+          ExpandRLE(m_bytes.substr(content_start, content_end - content_start));
       packet = StringExtractorGDBRemote(packet_str);
 
       if (m_bytes[0] == '$' || m_bytes[0] == '%') {
@@ -1382,3 +1360,30 @@ void llvm::format_provider<GDBRemoteCommunication::PacketResult>::format(
     break;
   }
 }
+
+std::string GDBRemoteCommunication::ExpandRLE(std::string packet) {
+  // Reserve enough byte for the most common case (no RLE used).
+  std::string decoded;
+  decoded.reserve(packet.size());
+  for (std::string::const_iterator c = packet.begin(); c != packet.end(); ++c) {
+    if (*c == '*') {
+      // '*' indicates RLE. Next character will give us the repeat count and
+      // previous character is what is to be repeated.
+      char char_to_repeat = decoded.back();
+      // Number of time the previous character is repeated.
+      int repeat_count = *++c + 3 - ' ';
+      // We have the char_to_repeat and repeat_count. Now push it in the
+      // packet.
+      for (int i = 0; i < repeat_count; ++i)
+        decoded.push_back(char_to_repeat);
+    } else if (*c == 0x7d) {
+      // 0x7d is the escape character.  The next character is to be XOR'd with
+      // 0x20.
+      char escapee = *++c ^ 0x20;
+      decoded.push_back(escapee);
+    } else {
+      decoded.push_back(*c);
+    }
+  }
+  return decoded;
+}
diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
index 7c0ef197f89b4..4cc466667c820 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
@@ -142,6 +142,9 @@ class GDBRemoteCommunication : public Communication {
   static llvm::Error ConnectLocally(GDBRemoteCommunication &client,
                                     GDBRemoteCommunication &server);
 
+  /// Expand GDB run-length encoding.
+  static std::string ExpandRLE(std::string);
+
 protected:
   std::chrono::seconds m_packet_timeout;
   uint32_t m_echo_number;
diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationReplayServer.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationReplayServer.cpp
index 8c6efe9ee9e27..910dcf2cf5899 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationReplayServer.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationReplayServer.cpp
@@ -131,22 +131,26 @@ GDBRemoteCommunicationReplayServer::GetPacketAndSendResponse(
     GDBRemotePacket entry = m_packet_history.back();
     m_packet_history.pop_back();
 
+    // Decode run-length encoding.
+    const std::string expanded_data =
+        GDBRemoteCommunication::ExpandRLE(entry.packet.data);
+
     // We've handled the handshake implicitly before. Skip the packet and move
     // on.
     if (entry.packet.data == "+")
       continue;
 
     if (entry.type == GDBRemotePacket::ePacketTypeSend) {
-      if (unexpected(entry.packet.data, packet.GetStringRef())) {
+      if (unexpected(expanded_data, packet.GetStringRef())) {
         LLDB_LOG(log,
                  "GDBRemoteCommunicationReplayServer expected packet: '{0}'",
-                 entry.packet.data);
+                 expanded_data);
         LLDB_LOG(log, "GDBRemoteCommunicationReplayServer actual packet: '{0}'",
                  packet.GetStringRef());
 #ifndef NDEBUG
         // This behaves like a regular assert, but prints the expected and
         // received packet before aborting.
-        printf("Reproducer expected packet: '%s'\n", entry.packet.data.c_str());
+        printf("Reproducer expected packet: '%s'\n", expanded_data.c_str());
         printf("Reproducer received packet: '%s'\n",
                packet.GetStringRef().data());
         llvm::report_fatal_error("Encountered unexpected packet during replay");
@@ -155,7 +159,7 @@ GDBRemoteCommunicationReplayServer::GetPacketAndSendResponse(
       }
 
       // Ignore QEnvironment packets as they're handled earlier.
-      if (entry.packet.data.find("QEnvironment") == 1) {
+      if (expanded_data.find("QEnvironment") == 1) {
         assert(m_packet_history.back().type ==
                GDBRemotePacket::ePacketTypeRecv);
         m_packet_history.pop_back();
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
index b1007d257cc73..8838888b2e23d 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
@@ -35,6 +35,8 @@
 #include "lldb/Utility/Log.h"
 #include "lldb/Utility/StreamString.h"
 
+#include "llvm/Demangle/Demangle.h"
+
 #include "clang/AST/CXXInheritance.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclObjC.h"
@@ -1167,12 +1169,22 @@ TypeSP DWARFASTParserClang::ParseSubroutine(const DWARFDIE &die,
       }
 
       if (!function_decl) {
+        const char *name = attrs.name.GetCString();
+
+        // We currently generate function templates with template parameters in
+        // their name. In order to get closer to the AST that clang generates
+        // we want to strip these from the name when creating the AST.
+        if (attrs.mangled_name) {
+          llvm::ItaniumPartialDemangler D;
+          if (!D.partialDemangle(attrs.mangled_name))
+            name = D.getFunctionBaseName(nullptr, nullptr);
+        }
+
         // We just have a function that isn't part of a class
         function_decl = m_ast.CreateFunctionDeclaration(
             ignore_containing_context ? m_ast.GetTranslationUnitDecl()
                                       : containing_decl_ctx,
-            attrs.name.GetCString(), clang_type, attrs.storage,
-            attrs.is_inline);
+            name, clang_type, attrs.storage, attrs.is_inline);
 
         if (has_template_params) {
           TypeSystemClang::TemplateParameterInfos template_param_infos;
@@ -1180,14 +1192,14 @@ TypeSP DWARFASTParserClang::ParseSubroutine(const DWARFDIE &die,
           template_function_decl = m_ast.CreateFunctionDeclaration(
               ignore_containing_context ? m_ast.GetTranslationUnitDecl()
                                         : containing_decl_ctx,
-              attrs.name.GetCString(), clang_type, attrs.storage,
-              attrs.is_inline);
+              name, clang_type, attrs.storage, attrs.is_inline);
+
           clang::FunctionTemplateDecl *func_template_decl =
-              m_ast.CreateFunctionTemplateDecl(
-                  containing_decl_ctx, template_function_decl,
-                  attrs.name.GetCString(), template_param_infos);
+              m_ast.CreateFunctionTemplateDecl(containing_decl_ctx,
+                                               template_function_decl, name,
+                                               template_param_infos);
           m_ast.CreateFunctionTemplateSpecializationInfo(
-              function_decl, func_template_decl, template_param_infos);
+              template_function_decl, func_template_decl, template_param_infos);
         }
 
         lldbassert(function_decl);
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
index cfb8416215661..da8fec46dba74 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
@@ -125,7 +125,7 @@ SymbolFileDWARFDwo::GetTypeSystemForLanguage(LanguageType language) {
 
 DWARFDIE
 SymbolFileDWARFDwo::GetDIE(const DIERef &die_ref) {
-  if (*die_ref.dwo_num() == GetDwoNum())
+  if (die_ref.dwo_num() == GetDwoNum())
     return DebugInfo().GetDIE(die_ref);
   return GetBaseSymbolFile().GetDIE(die_ref);
 }
diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
index 42655ad6cc24d..c278aef8949e7 100644
--- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -1207,10 +1207,11 @@ CompilerType TypeSystemClang::CreateRecordType(DeclContext *decl_ctx,
   // complete definition just in case.
 
   bool has_name = !name.empty();
-
-  CXXRecordDecl *decl = CXXRecordDecl::Create(
-      ast, (TagDecl::TagKind)kind, decl_ctx, SourceLocation(), SourceLocation(),
-      has_name ? &ast.Idents.get(name) : nullptr);
+  CXXRecordDecl *decl = CXXRecordDecl::CreateDeserialized(ast, 0);
+  decl->setTagKind(static_cast<TagDecl::TagKind>(kind));
+  decl->setDeclContext(decl_ctx);
+  if (has_name)
+    decl->setDeclName(&ast.Idents.get(name));
 
   if (!has_name) {
     // In C++ a lambda is also represented as an unnamed class. This is
@@ -1331,9 +1332,12 @@ clang::FunctionTemplateDecl *TypeSystemClang::CreateFunctionTemplateDecl(
 
   TemplateParameterList *template_param_list = CreateTemplateParameterList(
       ast, template_param_infos, template_param_decls);
-  FunctionTemplateDecl *func_tmpl_decl = FunctionTemplateDecl::Create(
-      ast, decl_ctx, func_decl->getLocation(), func_decl->getDeclName(),
-      template_param_list, func_decl);
+  FunctionTemplateDecl *func_tmpl_decl =
+      FunctionTemplateDecl::CreateDeserialized(ast, 0);
+  func_tmpl_decl->setDeclContext(decl_ctx);
+  func_tmpl_decl->setLocation(func_decl->getLocation());
+  func_tmpl_decl->setDeclName(func_decl->getDeclName());
+  func_tmpl_decl->init(func_decl, template_param_list);
 
   for (size_t i = 0, template_param_decl_count = template_param_decls.size();
        i < template_param_decl_count; ++i) {
@@ -1384,11 +1388,11 @@ ClassTemplateDecl *TypeSystemClang::CreateClassTemplateDecl(
   TemplateParameterList *template_param_list = CreateTemplateParameterList(
       ast, template_param_infos, template_param_decls);
 
-  CXXRecordDecl *template_cxx_decl = CXXRecordDecl::Create(
-      ast, (TagDecl::TagKind)kind,
-      decl_ctx, // What decl context do we use here? TU? The actual decl
-                // context?
-      SourceLocation(), SourceLocation(), &identifier_info);
+  CXXRecordDecl *template_cxx_decl = CXXRecordDecl::CreateDeserialized(ast, 0);
+  template_cxx_decl->setTagKind(static_cast<TagDecl::TagKind>(kind));
+  // What decl context do we use here? TU? The actual decl context?
+  template_cxx_decl->setDeclContext(decl_ctx);
+  template_cxx_decl->setDeclName(decl_name);
 
   for (size_t i = 0, template_param_decl_count = template_param_decls.size();
        i < template_param_decl_count; ++i) {
@@ -1400,11 +1404,11 @@ ClassTemplateDecl *TypeSystemClang::CreateClassTemplateDecl(
   // template_cxx_decl->startDefinition();
   // template_cxx_decl->completeDefinition();
 
-  class_template_decl = ClassTemplateDecl::Create(
-      ast,
-      decl_ctx, // What decl context do we use here? TU? The actual decl
-                // context?
-      SourceLocation(), decl_name, template_param_list, template_cxx_decl);
+  class_template_decl = ClassTemplateDecl::CreateDeserialized(ast, 0);
+  // What decl context do we use here? TU? The actual decl context?
+  class_template_decl->setDeclContext(decl_ctx);
+  class_template_decl->setDeclName(decl_name);
+  class_template_decl->init(template_cxx_decl, template_param_list);
   template_cxx_decl->setDescribedClassTemplate(class_template_decl);
 
   if (class_template_decl) {
@@ -1458,9 +1462,16 @@ TypeSystemClang::CreateClassTemplateSpecializationDecl(
         ast, template_param_infos.packed_args->args);
   }
   ClassTemplateSpecializationDecl *class_template_specialization_decl =
-      ClassTemplateSpecializationDecl::Create(
-          ast, (TagDecl::TagKind)kind, decl_ctx, SourceLocation(),
-          SourceLocation(), class_template_decl, args, nullptr);
+      ClassTemplateSpecializationDecl::CreateDeserialized(ast, 0);
+  class_template_specialization_decl->setTagKind(
+      static_cast<TagDecl::TagKind>(kind));
+  class_template_specialization_decl->setDeclContext(decl_ctx);
+  class_template_specialization_decl->setInstantiationOf(class_template_decl);
+  class_template_specialization_decl->setTemplateArgs(
+      TemplateArgumentList::CreateCopy(ast, args));
+  ast.getTypeDeclType(class_template_specialization_decl, nullptr);
+  class_template_specialization_decl->setDeclName(
+      class_template_decl->getDeclName());
 
   class_template_specialization_decl->setSpecializationKind(
       TSK_ExplicitSpecialization);
@@ -1589,11 +1600,11 @@ CompilerType TypeSystemClang::CreateObjCClass(llvm::StringRef name,
   if (decl_ctx == nullptr)
     decl_ctx = ast.getTranslationUnitDecl();
 
-  ObjCInterfaceDecl *decl = ObjCInterfaceDecl::Create(
-      ast, decl_ctx, SourceLocation(), &ast.Idents.get(name), nullptr, nullptr,
-      SourceLocation(),
-      /*isForwardDecl,*/
-      isInternal);
+  ObjCInterfaceDecl *decl = ObjCInterfaceDecl::CreateDeserialized(ast, 0);
+  decl->setDeclContext(decl_ctx);
+  decl->setDeclName(&ast.Idents.get(name));
+  /*isForwardDecl,*/
+  decl->setImplicit(isInternal);
 
   if (decl && metadata)
     SetMetadata(decl, *metadata);
@@ -1631,7 +1642,7 @@ TypeSystemClang::GetNumBaseClasses(const CXXRecordDecl *cxx_record_decl,
 #pragma mark Namespace Declarations
 
 NamespaceDecl *TypeSystemClang::GetUniqueNamespaceDeclaration(
-    const char *name, DeclContext *decl_ctx, bool is_inline) {
+    const char *name, clang::DeclContext *decl_ctx, bool is_inline) {
   NamespaceDecl *namespace_decl = nullptr;
   ASTContext &ast = getASTContext();
   TranslationUnitDecl *translation_unit_decl = ast.getTranslationUnitDecl();
@@ -1690,9 +1701,10 @@ NamespaceDecl *TypeSystemClang::GetUniqueNamespaceDeclaration(
 
 clang::BlockDecl *
 TypeSystemClang::CreateBlockDeclaration(clang::DeclContext *ctx) {
-  if (ctx != nullptr) {
+  if (ctx) {
     clang::BlockDecl *decl =
-        clang::BlockDecl::Create(getASTContext(), ctx, clang::SourceLocation());
+        clang::BlockDecl::CreateDeserialized(getASTContext(), 0);
+    decl->setDeclContext(ctx);
     ctx->addDecl(decl);
     return decl;
   }
@@ -1718,15 +1730,16 @@ clang::DeclContext *FindLCABetweenDecls(clang::DeclContext *left,
 
 clang::UsingDirectiveDecl *TypeSystemClang::CreateUsingDirectiveDeclaration(
     clang::DeclContext *decl_ctx, clang::NamespaceDecl *ns_decl) {
-  if (decl_ctx != nullptr && ns_decl != nullptr) {
+  if (decl_ctx && ns_decl) {
     auto *translation_unit = getASTContext().getTranslationUnitDecl();
     clang::UsingDirectiveDecl *using_decl = clang::UsingDirectiveDecl::Create(
-        getASTContext(), decl_ctx, clang::SourceLocation(),
-        clang::SourceLocation(), clang::NestedNameSpecifierLoc(),
-        clang::SourceLocation(), ns_decl,
-        FindLCABetweenDecls(decl_ctx, ns_decl, translation_unit));
-    decl_ctx->addDecl(using_decl);
-    return using_decl;
+          getASTContext(), decl_ctx, clang::SourceLocation(),
+          clang::SourceLocation(), clang::NestedNameSpecifierLoc(),
+          clang::SourceLocation(), ns_decl,
+          FindLCABetweenDecls(decl_ctx, ns_decl,
+                              translation_unit));
+      decl_ctx->addDecl(using_decl);
+      return using_decl;
   }
   return nullptr;
 }
@@ -1750,12 +1763,13 @@ TypeSystemClang::CreateUsingDeclaration(clang::DeclContext *current_decl_ctx,
 
 clang::VarDecl *TypeSystemClang::CreateVariableDeclaration(
     clang::DeclContext *decl_context, const char *name, clang::QualType type) {
-  if (decl_context != nullptr) {
-    clang::VarDecl *var_decl = clang::VarDecl::Create(
-        getASTContext(), decl_context, clang::SourceLocation(),
-        clang::SourceLocation(),
-        name && name[0] ? &getASTContext().Idents.getOwn(name) : nullptr, type,
-        nullptr, clang::SC_None);
+  if (decl_context) {
+    clang::VarDecl *var_decl =
+        clang::VarDecl::CreateDeserialized(getASTContext(), 0);
+    var_decl->setDeclContext(decl_context);
+    if (name && name[0])
+      var_decl->setDeclName(&getASTContext().Idents.getOwn(name));
+    var_decl->setType(type);
     var_decl->setAccess(clang::AS_public);
     decl_context->addDecl(var_decl);
     return var_decl;
@@ -1879,11 +1893,15 @@ FunctionDecl *TypeSystemClang::CreateFunctionDeclaration(
 
   clang::DeclarationName declarationName =
       GetDeclarationName(name, function_clang_type);
-  func_decl = FunctionDecl::Create(
-      ast, decl_ctx, SourceLocation(), SourceLocation(), declarationName,
-      ClangUtil::GetQualType(function_clang_type), nullptr,
-      (clang::StorageClass)storage, is_inline, hasWrittenPrototype,
-      isConstexprSpecified ? CSK_constexpr : CSK_unspecified);
+  func_decl = FunctionDecl::CreateDeserialized(ast, 0);
+  func_decl->setDeclContext(decl_ctx);
+  func_decl->setDeclName(declarationName);
+  func_decl->setType(ClangUtil::GetQualType(function_clang_type));
+  func_decl->setStorageClass(static_cast<clang::StorageClass>(storage));
+  func_decl->setInlineSpecified(is_inline);
+  func_decl->setHasWrittenPrototype(hasWrittenPrototype);
+  func_decl->setConstexprKind(isConstexprSpecified ? CSK_constexpr
+                                                   : CSK_unspecified);
   if (func_decl)
     decl_ctx->addDecl(func_decl);
 
@@ -1935,11 +1953,12 @@ ParmVarDecl *TypeSystemClang::CreateParameterDeclaration(
     clang::DeclContext *decl_ctx, const char *name,
     const CompilerType &param_type, int storage, bool add_decl) {
   ASTContext &ast = getASTContext();
-  auto *decl =
-      ParmVarDecl::Create(ast, decl_ctx, SourceLocation(), SourceLocation(),
-                          name && name[0] ? &ast.Idents.get(name) : nullptr,
-                          ClangUtil::GetQualType(param_type), nullptr,
-                          (clang::StorageClass)storage, nullptr);
+  auto *decl = ParmVarDecl::CreateDeserialized(ast, 0);
+  decl->setDeclContext(decl_ctx);
+  if (name && name[0])
+    decl->setDeclName(&ast.Idents.get(name));
+  decl->setType(ClangUtil::GetQualType(param_type));
+  decl->setStorageClass(static_cast<clang::StorageClass>(storage));
   if (add_decl)
     decl_ctx->addDecl(decl);
 
@@ -2036,13 +2055,15 @@ TypeSystemClang::CreateEnumerationType(const char *name, DeclContext *decl_ctx,
   // like maybe filling in the SourceLocation with it...
   ASTContext &ast = getASTContext();
 
-  EnumDecl *enum_decl = EnumDecl::Create(
-      ast, decl_ctx, SourceLocation(), SourceLocation(),
-      name && name[0] ? &ast.Idents.get(name) : nullptr, nullptr,
-      is_scoped, // IsScoped
-      is_scoped, // IsScopedUsingClassTag
-      false);    // TODO: IsFixed
-
+  // TODO: ask about these...
+  //    const bool IsFixed = false;
+  EnumDecl *enum_decl = EnumDecl::CreateDeserialized(ast, 0);
+  enum_decl->setDeclContext(decl_ctx);
+  if (name && name[0])
+    enum_decl->setDeclName(&ast.Idents.get(name));
+  enum_decl->setScoped(is_scoped);
+  enum_decl->setScopedUsingClassTag(is_scoped);
+  enum_decl->setFixed(false);
   if (enum_decl) {
     if (decl_ctx)
       decl_ctx->addDecl(enum_decl);
@@ -4243,10 +4264,11 @@ CompilerType TypeSystemClang::CreateTypedefType(
     if (decl_ctx == nullptr)
       decl_ctx = ast->getASTContext().getTranslationUnitDecl();
 
-    clang::TypedefDecl *decl = clang::TypedefDecl::Create(
-        clang_ast, decl_ctx, clang::SourceLocation(), clang::SourceLocation(),
-        &clang_ast.Idents.get(typedef_name),
-        clang_ast.getTrivialTypeSourceInfo(qual_type));
+    clang::TypedefDecl *decl =
+        clang::TypedefDecl::CreateDeserialized(clang_ast, 0);
+    decl->setDeclContext(decl_ctx);
+    decl->setDeclName(&clang_ast.Idents.get(typedef_name));
+    decl->setTypeSourceInfo(clang_ast.getTrivialTypeSourceInfo(qual_type));
 
     decl->setAccess(clang::AS_public); // TODO respect proper access specifier
 
@@ -4349,10 +4371,11 @@ TypeSystemClang::CreateTypedef(lldb::opaque_compiler_type_t type,
     if (decl_ctx == nullptr)
       decl_ctx = getASTContext().getTranslationUnitDecl();
 
-    clang::TypedefDecl *decl = clang::TypedefDecl::Create(
-        clang_ast, decl_ctx, clang::SourceLocation(), clang::SourceLocation(),
-        &clang_ast.Idents.get(typedef_name),
-        clang_ast.getTrivialTypeSourceInfo(qual_type));
+    clang::TypedefDecl *decl =
+        clang::TypedefDecl::CreateDeserialized(clang_ast, 0);
+    decl->setDeclContext(decl_ctx);
+    decl->setDeclName(&clang_ast.Idents.get(typedef_name));
+    decl->setTypeSourceInfo(clang_ast.getTrivialTypeSourceInfo(qual_type));
 
     clang::TagDecl *tdecl = nullptr;
     if (!qual_type.isNull()) {
@@ -6888,15 +6911,12 @@ clang::FieldDecl *TypeSystemClang::AddFieldToRecordType(
 
   clang::RecordDecl *record_decl = ast->GetAsRecordDecl(type);
   if (record_decl) {
-    field = clang::FieldDecl::Create(
-        clang_ast, record_decl, clang::SourceLocation(),
-        clang::SourceLocation(),
-        ident,                                    // Identifier
-        ClangUtil::GetQualType(field_clang_type), // Field type
-        nullptr,                                  // TInfo *
-        bit_width,                                // BitWidth
-        false,                                    // Mutable
-        clang::ICIS_NoInit);                      // HasInit
+    field = clang::FieldDecl::CreateDeserialized(clang_ast, 0);
+    field->setDeclContext(record_decl);
+    field->setDeclName(ident);
+    field->setType(ClangUtil::GetQualType(field_clang_type));
+    if (bit_width)
+      field->setBitWidth(bit_width);
 
     if (name.empty()) {
       // Determine whether this field corresponds to an anonymous struct or
@@ -6929,14 +6949,15 @@ clang::FieldDecl *TypeSystemClang::AddFieldToRecordType(
 
       field_clang_type.GetCompleteType();
 
-      field = clang::ObjCIvarDecl::Create(
-          clang_ast, class_interface_decl, clang::SourceLocation(),
-          clang::SourceLocation(),
-          ident,                                    // Identifier
-          ClangUtil::GetQualType(field_clang_type), // Field type
-          nullptr,                                  // TypeSourceInfo *
-          ConvertAccessTypeToObjCIvarAccessControl(access), bit_width,
-          is_synthesized);
+      auto ivar = clang::ObjCIvarDecl::CreateDeserialized(clang_ast, 0);
+      ivar->setDeclContext(class_interface_decl);
+      ivar->setDeclName(ident);
+      ivar->setType(ClangUtil::GetQualType(field_clang_type));
+      ivar->setAccessControl(ConvertAccessTypeToObjCIvarAccessControl(access));
+      if (bit_width)
+        ivar->setBitWidth(bit_width);
+      ivar->setSynthesize(is_synthesized);
+      field = ivar;
 
       if (field) {
         class_interface_decl->addDecl(field);
@@ -7089,15 +7110,11 @@ clang::VarDecl *TypeSystemClang::AddVariableToRecordType(
   if (!name.empty())
     ident = &ast->getASTContext().Idents.get(name);
 
-  var_decl = clang::VarDecl::Create(
-      ast->getASTContext(),             // ASTContext &
-      record_decl,                      // DeclContext *
-      clang::SourceLocation(),          // clang::SourceLocation StartLoc
-      clang::SourceLocation(),          // clang::SourceLocation IdLoc
-      ident,                            // clang::IdentifierInfo *
-      ClangUtil::GetQualType(var_type), // Variable clang::QualType
-      nullptr,                          // TypeSourceInfo *
-      clang::SC_Static);                // StorageClass
+  var_decl = clang::VarDecl::CreateDeserialized(ast->getASTContext(), 0);
+  var_decl->setDeclContext(record_decl);
+  var_decl->setDeclName(ident);
+  var_decl->setType(ClangUtil::GetQualType(var_type));
+  var_decl->setStorageClass(clang::SC_Static);
   if (!var_decl)
     return nullptr;
 
@@ -7153,29 +7170,34 @@ clang::CXXMethodDecl *TypeSystemClang::AddMethodToCXXRecordType(
     return nullptr; // skip everything artificial
 
   const clang::ExplicitSpecifier explicit_spec(
-      nullptr /*expr*/, is_explicit
-                            ? clang::ExplicitSpecKind::ResolvedTrue
-                            : clang::ExplicitSpecKind::ResolvedFalse);
+      nullptr /*expr*/, is_explicit ? clang::ExplicitSpecKind::ResolvedTrue
+                                    : clang::ExplicitSpecKind::ResolvedFalse);
+
   if (name.startswith("~")) {
-    cxx_dtor_decl = clang::CXXDestructorDecl::Create(
-        getASTContext(), cxx_record_decl, clang::SourceLocation(),
-        clang::DeclarationNameInfo(
-            getASTContext().DeclarationNames.getCXXDestructorName(
-                getASTContext().getCanonicalType(record_qual_type)),
-            clang::SourceLocation()),
-        method_qual_type, nullptr, is_inline, is_artificial,
-        ConstexprSpecKind::CSK_unspecified);
+    cxx_dtor_decl =
+        clang::CXXDestructorDecl::CreateDeserialized(getASTContext(), 0);
+    cxx_dtor_decl->setDeclContext(cxx_record_decl);
+    cxx_dtor_decl->setDeclName(
+        getASTContext().DeclarationNames.getCXXDestructorName(
+            getASTContext().getCanonicalType(record_qual_type)));
+    cxx_dtor_decl->setType(method_qual_type);
+    cxx_dtor_decl->setImplicit(is_artificial);
+    cxx_dtor_decl->setInlineSpecified(is_inline);
+    cxx_dtor_decl->setConstexprKind(CSK_unspecified);
     cxx_method_decl = cxx_dtor_decl;
   } else if (decl_name == cxx_record_decl->getDeclName()) {
-    cxx_ctor_decl = clang::CXXConstructorDecl::Create(
-        getASTContext(), cxx_record_decl, clang::SourceLocation(),
-        clang::DeclarationNameInfo(
-            getASTContext().DeclarationNames.getCXXConstructorName(
-                getASTContext().getCanonicalType(record_qual_type)),
-            clang::SourceLocation()),
-        method_qual_type,
-        nullptr, // TypeSourceInfo *
-        explicit_spec, is_inline, is_artificial, CSK_unspecified);
+    cxx_ctor_decl = clang::CXXConstructorDecl::CreateDeserialized(
+        getASTContext(), 0, 0);
+    cxx_ctor_decl->setDeclContext(cxx_record_decl);
+    cxx_ctor_decl->setDeclName(
+        getASTContext().DeclarationNames.getCXXConstructorName(
+            getASTContext().getCanonicalType(record_qual_type)));
+    cxx_ctor_decl->setType(method_qual_type);
+    cxx_ctor_decl->setImplicit(is_artificial);
+    cxx_ctor_decl->setInlineSpecified(is_inline);
+    cxx_ctor_decl->setConstexprKind(CSK_unspecified);
+    cxx_ctor_decl->setNumCtorInitializers(0);
+    cxx_ctor_decl->setExplicitSpecifier(explicit_spec);
     cxx_method_decl = cxx_ctor_decl;
   } else {
     clang::StorageClass SC = is_static ? clang::SC_Static : clang::SC_None;
@@ -7191,36 +7213,41 @@ clang::CXXMethodDecl *TypeSystemClang::AddMethodToCXXRecordType(
         if (!TypeSystemClang::CheckOverloadedOperatorKindParameterCount(
                 is_method, op_kind, num_params))
           return nullptr;
-        cxx_method_decl = clang::CXXMethodDecl::Create(
-            getASTContext(), cxx_record_decl, clang::SourceLocation(),
-            clang::DeclarationNameInfo(
-                getASTContext().DeclarationNames.getCXXOperatorName(op_kind),
-                clang::SourceLocation()),
-            method_qual_type,
-            nullptr, // TypeSourceInfo *
-            SC, is_inline, CSK_unspecified, clang::SourceLocation());
+        cxx_method_decl =
+            clang::CXXMethodDecl::CreateDeserialized(getASTContext(), 0);
+        cxx_method_decl->setDeclContext(cxx_record_decl);
+        cxx_method_decl->setDeclName(
+            getASTContext().DeclarationNames.getCXXOperatorName(op_kind));
+        cxx_method_decl->setType(method_qual_type);
+        cxx_method_decl->setStorageClass(SC);
+        cxx_method_decl->setInlineSpecified(is_inline);
+        cxx_method_decl->setConstexprKind(CSK_unspecified);
       } else if (num_params == 0) {
         // Conversion operators don't take params...
-        cxx_method_decl = clang::CXXConversionDecl::Create(
-            getASTContext(), cxx_record_decl, clang::SourceLocation(),
-            clang::DeclarationNameInfo(
-                getASTContext().DeclarationNames.getCXXConversionFunctionName(
-                    getASTContext().getCanonicalType(
-                        function_type->getReturnType())),
-                clang::SourceLocation()),
-            method_qual_type,
-            nullptr, // TypeSourceInfo *
-            is_inline, explicit_spec, CSK_unspecified, clang::SourceLocation());
+        auto *cxx_conversion_decl =
+            clang::CXXConversionDecl::CreateDeserialized(getASTContext(), 0);
+        cxx_conversion_decl->setDeclContext(cxx_record_decl);
+        cxx_conversion_decl->setDeclName(
+            getASTContext().DeclarationNames.getCXXConversionFunctionName(
+                getASTContext().getCanonicalType(
+                    function_type->getReturnType())));
+        cxx_conversion_decl->setType(method_qual_type);
+        cxx_conversion_decl->setInlineSpecified(is_inline);
+        cxx_conversion_decl->setExplicitSpecifier(explicit_spec);        
+        cxx_conversion_decl->setConstexprKind(CSK_unspecified);
+        cxx_method_decl = cxx_conversion_decl;
       }
     }
 
     if (cxx_method_decl == nullptr) {
-      cxx_method_decl = clang::CXXMethodDecl::Create(
-          getASTContext(), cxx_record_decl, clang::SourceLocation(),
-          clang::DeclarationNameInfo(decl_name, clang::SourceLocation()),
-          method_qual_type,
-          nullptr, // TypeSourceInfo *
-          SC, is_inline, CSK_unspecified, clang::SourceLocation());
+      cxx_method_decl =
+          clang::CXXMethodDecl::CreateDeserialized(getASTContext(), 0);
+      cxx_method_decl->setDeclContext(cxx_record_decl);
+      cxx_method_decl->setDeclName(decl_name);
+      cxx_method_decl->setType(method_qual_type);
+      cxx_method_decl->setInlineSpecified(is_inline);
+      cxx_method_decl->setStorageClass(SC);
+      cxx_method_decl->setConstexprKind(CSK_unspecified);
     }
   }
 
@@ -7389,15 +7416,14 @@ bool TypeSystemClang::AddObjCClassProperty(
     prop_type_source = clang_ast.getTrivialTypeSourceInfo(
         ClangUtil::GetQualType(property_clang_type));
 
-  clang::ObjCPropertyDecl *property_decl = clang::ObjCPropertyDecl::Create(
-      clang_ast, class_interface_decl,
-      clang::SourceLocation(), // Source Location
-      &clang_ast.Idents.get(property_name),
-      clang::SourceLocation(), // Source Location for AT
-      clang::SourceLocation(), // Source location for (
-      ivar_decl ? ivar_decl->getType()
-                : ClangUtil::GetQualType(property_clang_type),
-      prop_type_source);
+  clang::ObjCPropertyDecl *property_decl =
+      clang::ObjCPropertyDecl::CreateDeserialized(clang_ast, 0);
+  property_decl->setDeclContext(class_interface_decl);
+  property_decl->setDeclName(&clang_ast.Idents.get(property_name));
+  property_decl->setType(ivar_decl
+                             ? ivar_decl->getType()
+                             : ClangUtil::GetQualType(property_clang_type),
+                         prop_type_source);
 
   if (!property_decl)
     return false;
@@ -7477,12 +7503,18 @@ bool TypeSystemClang::AddObjCClassProperty(
         clang::ObjCMethodDecl::None;
     const bool HasRelatedResultType = false;
 
-    getter = clang::ObjCMethodDecl::Create(
-        clang_ast, clang::SourceLocation(), clang::SourceLocation(), getter_sel,
-        ClangUtil::GetQualType(property_clang_type_to_access), nullptr,
-        class_interface_decl, isInstance, isVariadic, isPropertyAccessor,
-        isSynthesizedAccessorStub, isImplicitlyDeclared, isDefined, impControl,
-        HasRelatedResultType);
+    getter = clang::ObjCMethodDecl::CreateDeserialized(clang_ast, 0);
+    getter->setDeclName(getter_sel);
+    getter->setReturnType(ClangUtil::GetQualType(property_clang_type_to_access));
+    getter->setDeclContext(class_interface_decl);
+    getter->setInstanceMethod(isInstance);
+    getter->setVariadic(isVariadic);
+    getter->setPropertyAccessor(isPropertyAccessor);
+    getter->setSynthesizedAccessorStub(isSynthesizedAccessorStub);
+    getter->setImplicit(isImplicitlyDeclared);
+    getter->setDefined(isDefined);
+    getter->setDeclImplementation(impControl);
+    getter->setRelatedResultType(HasRelatedResultType);
 
     if (getter) {
       if (metadata)
@@ -7512,11 +7544,18 @@ bool TypeSystemClang::AddObjCClassProperty(
         clang::ObjCMethodDecl::None;
     const bool HasRelatedResultType = false;
 
-    setter = clang::ObjCMethodDecl::Create(
-        clang_ast, clang::SourceLocation(), clang::SourceLocation(), setter_sel,
-        result_type, nullptr, class_interface_decl, isInstance, isVariadic,
-        isPropertyAccessor, isSynthesizedAccessorStub, isImplicitlyDeclared,
-        isDefined, impControl, HasRelatedResultType);
+    setter = clang::ObjCMethodDecl::CreateDeserialized(clang_ast, 0);
+    setter->setDeclName(setter_sel);
+    setter->setReturnType(result_type);
+    setter->setDeclContext(class_interface_decl);
+    setter->setInstanceMethod(isInstance);
+    setter->setVariadic(isVariadic);
+    setter->setPropertyAccessor(isPropertyAccessor);
+    setter->setSynthesizedAccessorStub(isSynthesizedAccessorStub);
+    setter->setImplicit(isImplicitlyDeclared);
+    setter->setDefined(isDefined);
+    setter->setDeclImplementation(impControl);
+    setter->setRelatedResultType(HasRelatedResultType);
 
     if (setter) {
       if (metadata)
@@ -7632,15 +7671,19 @@ clang::ObjCMethodDecl *TypeSystemClang::AddMethodToObjCObjectType(
     return nullptr; // some debug information is corrupt.  We are not going to
                     // deal with it.
 
-  clang::ObjCMethodDecl *objc_method_decl = clang::ObjCMethodDecl::Create(
-      ast,
-      clang::SourceLocation(), // beginLoc,
-      clang::SourceLocation(), // endLoc,
-      method_selector, method_function_prototype->getReturnType(),
-      nullptr, // TypeSourceInfo *ResultTInfo,
-      lldb_ast->GetDeclContextForType(ClangUtil::GetQualType(type)), isInstance,
-      isVariadic, isPropertyAccessor, isSynthesizedAccessorStub,
-      isImplicitlyDeclared, isDefined, impControl, HasRelatedResultType);
+  auto *objc_method_decl = clang::ObjCMethodDecl::CreateDeserialized(ast, 0);
+  objc_method_decl->setDeclName(method_selector);
+  objc_method_decl->setReturnType(method_function_prototype->getReturnType());
+  objc_method_decl->setDeclContext(
+      lldb_ast->GetDeclContextForType(ClangUtil::GetQualType(type)));
+  objc_method_decl->setInstanceMethod(isInstance);
+  objc_method_decl->setVariadic(isVariadic);
+  objc_method_decl->setPropertyAccessor(isPropertyAccessor);
+  objc_method_decl->setSynthesizedAccessorStub(isSynthesizedAccessorStub);
+  objc_method_decl->setImplicit(isImplicitlyDeclared);
+  objc_method_decl->setDefined(isDefined);
+  objc_method_decl->setDeclImplementation(impControl);
+  objc_method_decl->setRelatedResultType(HasRelatedResultType);
 
   if (objc_method_decl == nullptr)
     return nullptr;
@@ -7864,10 +7907,13 @@ clang::EnumConstantDecl *TypeSystemClang::AddEnumerationValueToEnumerationType(
   if (!enutype)
     return nullptr;
 
-  clang::EnumConstantDecl *enumerator_decl = clang::EnumConstantDecl::Create(
-      getASTContext(), enutype->getDecl(), clang::SourceLocation(),
-      name ? &getASTContext().Idents.get(name) : nullptr, // Identifier
-      clang::QualType(enutype, 0), nullptr, value);
+  clang::EnumConstantDecl *enumerator_decl =
+      clang::EnumConstantDecl::CreateDeserialized(getASTContext(), 0);
+  enumerator_decl->setDeclContext(enutype->getDecl());
+  if (name && name[0])
+    enumerator_decl->setDeclName(&getASTContext().Idents.get(name));
+  enumerator_decl->setType(clang::QualType(enutype, 0));
+  enumerator_decl->setInitVal(value);
 
   if (!enumerator_decl)
     return nullptr;
diff --git a/lldb/source/Target/AssertFrameRecognizer.cpp b/lldb/source/Target/AssertFrameRecognizer.cpp
index ebeff6c393919..d87459ac2fdd4 100644
--- a/lldb/source/Target/AssertFrameRecognizer.cpp
+++ b/lldb/source/Target/AssertFrameRecognizer.cpp
@@ -21,8 +21,7 @@ namespace lldb_private {
 /// name.
 struct SymbolLocation {
   FileSpec module_spec;
-  ConstString symbol_name;
-  ConstString alternate_symbol_name;
+  std::vector<ConstString> symbols;
 };
 
 /// Fetches the abort frame location depending on the current platform.
@@ -39,12 +38,13 @@ bool GetAbortLocation(llvm::Triple::OSType os, SymbolLocation &location) {
   case llvm::Triple::Darwin:
   case llvm::Triple::MacOSX:
     location.module_spec = FileSpec("libsystem_kernel.dylib");
-    location.symbol_name.SetString("__pthread_kill");
+    location.symbols.push_back(ConstString("__pthread_kill"));
     break;
   case llvm::Triple::Linux:
     location.module_spec = FileSpec("libc.so.6");
-    location.symbol_name.SetString("raise");
-    location.alternate_symbol_name.SetString("__GI_raise");
+    location.symbols.push_back(ConstString("raise"));
+    location.symbols.push_back(ConstString("__GI_raise"));
+    location.symbols.push_back(ConstString("gsignal"));
     break;
   default:
     Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
@@ -69,12 +69,12 @@ bool GetAssertLocation(llvm::Triple::OSType os, SymbolLocation &location) {
   case llvm::Triple::Darwin:
   case llvm::Triple::MacOSX:
     location.module_spec = FileSpec("libsystem_c.dylib");
-    location.symbol_name.SetString("__assert_rtn");
+    location.symbols.push_back(ConstString("__assert_rtn"));
     break;
   case llvm::Triple::Linux:
     location.module_spec = FileSpec("libc.so.6");
-    location.symbol_name.SetString("__assert_fail");
-    location.alternate_symbol_name.SetString("__GI___assert_fail");
+    location.symbols.push_back(ConstString("__assert_fail"));
+    location.symbols.push_back(ConstString("__GI___assert_fail"));
     break;
   default:
     Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
@@ -97,8 +97,7 @@ void RegisterAssertFrameRecognizer(Process *process) {
 
     StackFrameRecognizerManager::AddRecognizer(
         StackFrameRecognizerSP(new AssertFrameRecognizer()),
-        location.module_spec.GetFilename(), ConstString(location.symbol_name),
-        ConstString(location.alternate_symbol_name),
+        location.module_spec.GetFilename(), location.symbols,
         /*first_instruction_only*/ false);
   });
 }
@@ -139,10 +138,7 @@ AssertFrameRecognizer::RecognizeFrame(lldb::StackFrameSP frame_sp) {
 
     ConstString func_name = sym_ctx.GetFunctionName();
 
-    if (func_name == location.symbol_name ||
-        (!location.alternate_symbol_name.IsEmpty() &&
-         func_name == location.alternate_symbol_name)) {
-
+    if (llvm::is_contained(location.symbols, func_name)) {
       // We go a frame beyond the assert location because the most relevant
       // frame for the user is the one in which the assert function was called.
       // If the assert location is the last frame fetched, then it is set as
diff --git a/lldb/source/Target/Platform.cpp b/lldb/source/Target/Platform.cpp
index eaa71b9cbbd0a..3069a363736f9 100644
--- a/lldb/source/Target/Platform.cpp
+++ b/lldb/source/Target/Platform.cpp
@@ -1865,6 +1865,12 @@ size_t Platform::GetSoftwareBreakpointTrapOpcode(Target &target,
     }
   } break;
 
+  case llvm::Triple::avr: {
+    static const uint8_t g_hex_opcode[] = {0x98, 0x95};
+    trap_opcode = g_hex_opcode;
+    trap_opcode_size = sizeof(g_hex_opcode);
+  } break;
+
   case llvm::Triple::mips:
   case llvm::Triple::mips64: {
     static const uint8_t g_hex_opcode[] = {0x00, 0x00, 0x00, 0x0d};
diff --git a/lldb/source/Target/StackFrame.cpp b/lldb/source/Target/StackFrame.cpp
index a81879476cf26..56761a6d10469 100644
--- a/lldb/source/Target/StackFrame.cpp
+++ b/lldb/source/Target/StackFrame.cpp
@@ -1861,6 +1861,7 @@ void StackFrame::UpdatePreviousFrameFromCurrentFrame(StackFrame &curr_frame) {
   m_concrete_frame_index = curr_frame.m_concrete_frame_index;
   m_reg_context_sp = curr_frame.m_reg_context_sp;
   m_frame_code_addr = curr_frame.m_frame_code_addr;
+  m_behaves_like_zeroth_frame = curr_frame.m_behaves_like_zeroth_frame;
   assert(!m_sc.target_sp || !curr_frame.m_sc.target_sp ||
          m_sc.target_sp.get() == curr_frame.m_sc.target_sp.get());
   assert(!m_sc.module_sp || !curr_frame.m_sc.module_sp ||
diff --git a/lldb/source/Target/StackFrameRecognizer.cpp b/lldb/source/Target/StackFrameRecognizer.cpp
index e484019746276..7dc6e9d1e490a 100644
--- a/lldb/source/Target/StackFrameRecognizer.cpp
+++ b/lldb/source/Target/StackFrameRecognizer.cpp
@@ -51,27 +51,25 @@ ScriptedStackFrameRecognizer::RecognizeFrame(lldb::StackFrameSP frame) {
 class StackFrameRecognizerManagerImpl {
 public:
   void AddRecognizer(StackFrameRecognizerSP recognizer, ConstString module,
-                     ConstString symbol, ConstString alternate_symbol,
+                     llvm::ArrayRef<ConstString> symbols,
                      bool first_instruction_only) {
     m_recognizers.push_front({(uint32_t)m_recognizers.size(), false, recognizer,
-                              false, module, RegularExpressionSP(), symbol,
-                              alternate_symbol, RegularExpressionSP(),
-                              first_instruction_only});
+                              false, module, RegularExpressionSP(), symbols,
+                              RegularExpressionSP(), first_instruction_only});
   }
 
   void AddRecognizer(StackFrameRecognizerSP recognizer,
                      RegularExpressionSP module, RegularExpressionSP symbol,
                      bool first_instruction_only) {
-    m_recognizers.push_front({(uint32_t)m_recognizers.size(), false, recognizer,
-                              true, ConstString(), module, ConstString(),
-                              ConstString(), symbol, first_instruction_only});
+    m_recognizers.push_front(
+        {(uint32_t)m_recognizers.size(), false, recognizer, true, ConstString(),
+         module, std::vector<ConstString>(), symbol, first_instruction_only});
   }
 
-  void ForEach(
-      std::function<void(uint32_t recognized_id, std::string recognizer_name,
-                         std::string module, std::string symbol,
-                         std::string alternate_symbol, bool regexp)> const
-          &callback) {
+  void ForEach(std::function<
+               void(uint32_t recognized_id, std::string recognizer_name,
+                    std::string module, llvm::ArrayRef<ConstString> symbols,
+                    bool regexp)> const &callback) {
     for (auto entry : m_recognizers) {
       if (entry.is_regexp) {
         std::string module_name;
@@ -83,16 +81,11 @@ class StackFrameRecognizerManagerImpl {
           symbol_name = entry.symbol_regexp->GetText().str();
 
         callback(entry.recognizer_id, entry.recognizer->GetName(), module_name,
-                 symbol_name, {}, true);
+                 llvm::makeArrayRef(ConstString(symbol_name)), true);
 
       } else {
-        std::string alternate_symbol;
-        if (!entry.alternate_symbol.IsEmpty())
-          alternate_symbol.append(entry.alternate_symbol.GetCString());
-
         callback(entry.recognizer_id, entry.recognizer->GetName(),
-                 entry.module.GetCString(), entry.symbol.GetCString(),
-                 alternate_symbol, false);
+                 entry.module.GetCString(), entry.symbols, false);
       }
     }
   }
@@ -128,10 +121,8 @@ class StackFrameRecognizerManagerImpl {
       if (entry.module_regexp)
         if (!entry.module_regexp->Execute(module_name.GetStringRef())) continue;
 
-      if (entry.symbol)
-        if (entry.symbol != function_name &&
-            (!entry.alternate_symbol ||
-             entry.alternate_symbol != function_name))
+      if (!entry.symbols.empty())
+        if (!llvm::is_contained(entry.symbols, function_name))
           continue;
 
       if (entry.symbol_regexp)
@@ -160,8 +151,7 @@ class StackFrameRecognizerManagerImpl {
     bool is_regexp;
     ConstString module;
     RegularExpressionSP module_regexp;
-    ConstString symbol;
-    ConstString alternate_symbol;
+    std::vector<ConstString> symbols;
     RegularExpressionSP symbol_regexp;
     bool first_instruction_only;
   };
@@ -176,10 +166,10 @@ StackFrameRecognizerManagerImpl &GetStackFrameRecognizerManagerImpl() {
 }
 
 void StackFrameRecognizerManager::AddRecognizer(
-    StackFrameRecognizerSP recognizer, ConstString module, ConstString symbol,
-    ConstString alternate_symbol, bool first_instruction_only) {
+    StackFrameRecognizerSP recognizer, ConstString module,
+    llvm::ArrayRef<ConstString> symbols, bool first_instruction_only) {
   GetStackFrameRecognizerManagerImpl().AddRecognizer(
-      recognizer, module, symbol, alternate_symbol, first_instruction_only);
+      recognizer, module, symbols, first_instruction_only);
 }
 
 void StackFrameRecognizerManager::AddRecognizer(
@@ -191,9 +181,8 @@ void StackFrameRecognizerManager::AddRecognizer(
 
 void StackFrameRecognizerManager::ForEach(
     std::function<void(uint32_t recognized_id, std::string recognizer_name,
-                       std::string module, std::string symbol,
-                       std::string alternate_symbol, bool regexp)> const
-        &callback) {
+                       std::string module, llvm::ArrayRef<ConstString> symbols,
+                       bool regexp)> const &callback) {
   GetStackFrameRecognizerManagerImpl().ForEach(callback);
 }
 
diff --git a/lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py b/lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
index 683b2e8f7b48f..04b940049496e 100644
--- a/lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
+++ b/lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
@@ -18,9 +18,7 @@ class FrameRecognizerTestCase(TestBase):
     @skipUnlessDarwin
     def test_frame_recognizer_1(self):
         self.build()
-
-        target = self.dbg.CreateTarget(self.getBuildArtifact("a.out"))
-        self.assertTrue(target, VALID_TARGET)
+        exe = self.getBuildArtifact("a.out")
 
         # Clear internal & plugins recognizers that get initialized at launch
         self.runCmd("frame recognizer clear")
@@ -33,21 +31,21 @@ def test_frame_recognizer_1(self):
         self.runCmd("frame recognizer add -l recognizer.MyFrameRecognizer -s a.out -n foo")
 
         self.expect("frame recognizer list",
-                    substrs=['0: recognizer.MyFrameRecognizer, module a.out, function foo'])
+                    substrs=['0: recognizer.MyFrameRecognizer, module a.out, symbol foo'])
 
         self.runCmd("frame recognizer add -l recognizer.MyOtherFrameRecognizer -s a.out -n bar -x")
 
         self.expect(
             "frame recognizer list",
             substrs=[
-                '1: recognizer.MyOtherFrameRecognizer, module a.out, function bar (regexp)',
-                '0: recognizer.MyFrameRecognizer, module a.out, function foo'
+                '1: recognizer.MyOtherFrameRecognizer, module a.out, symbol bar (regexp)',
+                '0: recognizer.MyFrameRecognizer, module a.out, symbol foo'
             ])
 
         self.runCmd("frame recognizer delete 0")
 
         self.expect("frame recognizer list",
-                    substrs=['1: recognizer.MyOtherFrameRecognizer, module a.out, function bar (regexp)'])
+                    substrs=['1: recognizer.MyOtherFrameRecognizer, module a.out, symbol bar (regexp)'])
 
         self.runCmd("frame recognizer clear")
 
@@ -56,19 +54,10 @@ def test_frame_recognizer_1(self):
 
         self.runCmd("frame recognizer add -l recognizer.MyFrameRecognizer -s a.out -n foo")
 
-        lldbutil.run_break_set_by_symbol(self, "foo")
-        self.runCmd("r")
-
-        self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT,
-                    substrs=['stopped', 'stop reason = breakpoint'])
-
-        process = target.GetProcess()
-        thread = process.GetSelectedThread()
+        target, process, thread, _ = lldbutil.run_to_name_breakpoint(self, "foo",
+                                                                 exe_name = exe)
         frame = thread.GetSelectedFrame()
 
-        self.assertEqual(frame.GetSymbol().GetName(), "foo")
-        self.assertFalse(frame.GetLineEntry().IsValid())
-
         self.expect("frame variable",
                     substrs=['(int) a = 42', '(int) b = 56'])
 
@@ -110,8 +99,9 @@ def test_frame_recognizer_1(self):
 
         # FIXME: The following doesn't work yet, but should be fixed.
         """
-        lldbutil.run_break_set_by_symbol(self, "bar")
-        self.runCmd("c")
+        target, process, thread, _ = lldbutil.run_to_name_breakpoint(self, "bar",
+                                                                 exe_name = exe)
+        frame = thread.GetSelectedFrame()
 
         self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT,
                     substrs=['stopped', 'stop reason = breakpoint'])
@@ -122,3 +112,35 @@ def test_frame_recognizer_1(self):
         self.expect("frame variable -t *a",
                     substrs=['*a = 78'])
         """
+
+    @skipUnlessDarwin
+    def test_frame_recognizer_multi_symbol(self):
+        self.build()
+        exe = self.getBuildArtifact("a.out")
+
+        # Clear internal & plugins recognizers that get initialized at launch
+        self.runCmd("frame recognizer clear")
+
+        self.runCmd("command script import " + os.path.join(self.getSourceDir(), "recognizer.py"))
+
+        self.expect("frame recognizer list",
+                    substrs=['no matching results found.'])
+
+        self.runCmd("frame recognizer add -l recognizer.MyFrameRecognizer -s a.out -n foo -n bar")
+
+        self.expect("frame recognizer list",
+                    substrs=['recognizer.MyFrameRecognizer, module a.out, symbol foo, symbol bar'])
+
+        target, process, thread, _ = lldbutil.run_to_name_breakpoint(self, "foo",
+                                                                 exe_name = exe)
+        frame = thread.GetSelectedFrame()
+
+        self.expect("frame recognizer info 0",
+                    substrs=['frame 0 is recognized by recognizer.MyFrameRecognizer'])
+
+        target, process, thread, _ = lldbutil.run_to_name_breakpoint(self, "bar",
+                                                                 exe_name = exe)
+        frame = thread.GetSelectedFrame()
+
+        self.expect("frame recognizer info 0",
+                    substrs=['frame 0 is recognized by recognizer.MyFrameRecognizer'])
diff --git a/lldb/test/API/commands/frame/recognizer/main.m b/lldb/test/API/commands/frame/recognizer/main.m
index d903625369ec6..5d064c2564ddc 100644
--- a/lldb/test/API/commands/frame/recognizer/main.m
+++ b/lldb/test/API/commands/frame/recognizer/main.m
@@ -5,10 +5,7 @@ void foo(int a, int b)
     printf("%d %d\n", a, b);
 }
 
-void bar(int *ptr)
-{
-	printf("%d\n", *ptr);
-}
+void bar(int *ptr) { printf("%d\n", *ptr); }
 
 int main (int argc, const char * argv[])
 {
diff --git a/lldb/test/API/commands/statistics/basic/TestStats.py b/lldb/test/API/commands/statistics/basic/TestStats.py
index 4809adf9060f5..76bc224338488 100644
--- a/lldb/test/API/commands/statistics/basic/TestStats.py
+++ b/lldb/test/API/commands/statistics/basic/TestStats.py
@@ -18,8 +18,8 @@ def test(self):
         self.expect("statistics enable", substrs=['already enabled'], error=True)
         self.expect("expr patatino", substrs=['27'])
         self.expect("statistics disable")
-        self.expect("statistics dump", substrs=['expr evaluation successes : 1',
-                                                'expr evaluation failures : 0'])
+        self.expect("statistics dump", substrs=['expr evaluation successes : 1\n',
+                                                'expr evaluation failures : 0\n'])
 
         # 'frame var' with disabled statistics shouldn't change stats.
         self.expect("frame var", substrs=['27'])
@@ -28,5 +28,5 @@ def test(self):
         # 'frame var' with enabled statistics will change stats.
         self.expect("frame var", substrs=['27'])
         self.expect("statistics disable")
-        self.expect("statistics dump", substrs=['frame var successes : 1',
-                                                'frame var failures : 0'])
+        self.expect("statistics dump", substrs=['frame var successes : 1\n',
+                                                'frame var failures : 0\n'])
diff --git a/lldb/test/API/functionalities/reproducers/attach/TestReproducerAttach.py b/lldb/test/API/functionalities/reproducers/attach/TestReproducerAttach.py
index e9a570b50976b..968268d6838bd 100644
--- a/lldb/test/API/functionalities/reproducers/attach/TestReproducerAttach.py
+++ b/lldb/test/API/functionalities/reproducers/attach/TestReproducerAttach.py
@@ -15,7 +15,6 @@ class ReproducerAttachTestCase(TestBase):
     mydir = TestBase.compute_mydir(__file__)
     NO_DEBUG_INFO_TESTCASE = True
 
-    @skipIfLinux # Reproducer received unexpected packet.
     @skipIfFreeBSD
     @skipIfNetBSD
     @skipIfWindows
diff --git a/lldb/test/API/functionalities/unwind/zeroth_frame/Makefile b/lldb/test/API/functionalities/unwind/zeroth_frame/Makefile
new file mode 100644
index 0000000000000..15a931850e17e
--- /dev/null
+++ b/lldb/test/API/functionalities/unwind/zeroth_frame/Makefile
@@ -0,0 +1,3 @@
+C_SOURCES := main.c
+
+include Makefile.rules
diff --git a/lldb/test/API/functionalities/unwind/zeroth_frame/TestZerothFrame.py b/lldb/test/API/functionalities/unwind/zeroth_frame/TestZerothFrame.py
new file mode 100644
index 0000000000000..b85a92e4a92f2
--- /dev/null
+++ b/lldb/test/API/functionalities/unwind/zeroth_frame/TestZerothFrame.py
@@ -0,0 +1,96 @@
+"""
+Test that line information is recalculated properly for a frame when it moves
+from the middle of the backtrace to a zero index.
+
+This is a regression test for a StackFrame bug, where whether frame is zero or
+not depends on an internal field. When LLDB was updating its frame list value
+of the field wasn't copied into existing StackFrame instances, so those
+StackFrame instances, would use an incorrect line entry evaluation logic in
+situations if it was in the middle of the stack frame list (not zeroth), and
+then moved to the top position. The difference in logic is that for zeroth
+frames line entry is returned for program counter, while for other frame
+(except for those that "behave like zeroth") it is for the instruction
+preceding PC, as PC points to the next instruction after function call. When
+the bug is present, when execution stops at the second breakpoint
+SBFrame.GetLineEntry() returns line entry for the previous line, rather than
+the one with a breakpoint. Note that this is specific to
+SBFrame.GetLineEntry(), SBFrame.GetPCAddress().GetLineEntry() would return
+correct entry.
+
+This bug doesn't reproduce through an LLDB interpretator, however it happens
+when using API directly, for example in LLDB-MI.
+"""
+
+from __future__ import print_function
+
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class ZerothFrame(TestBase):
+    mydir = TestBase.compute_mydir(__file__)
+
+    def test(self):
+        """
+        Test that line information is recalculated properly for a frame when it moves
+        from the middle of the backtrace to a zero index.
+        """
+        self.build()
+        self.setTearDownCleanup()
+
+        exe = self.getBuildArtifact("a.out")
+        target = self.dbg.CreateTarget(exe)
+        self.assertTrue(target, VALID_TARGET)
+
+        bp1_line = line_number('main.c', '// Set breakpoint 1 here')
+        bp2_line = line_number('main.c', '// Set breakpoint 2 here')
+
+        lldbutil.run_break_set_by_file_and_line(
+            self,
+            'main.c',
+            bp1_line,
+            num_expected_locations=1)
+        lldbutil.run_break_set_by_file_and_line(
+            self,
+            'main.c',
+            bp2_line,
+            num_expected_locations=1)
+
+        process = target.LaunchSimple(
+            None, None, self.get_process_working_directory())
+        self.assertTrue(process, VALID_PROCESS)
+
+        thread = process.GetThreadAtIndex(0)
+        if self.TraceOn():
+            print("Backtrace at the first breakpoint:")
+            for f in thread.frames:
+                print(f)
+        # Check that we have stopped at correct breakpoint.
+        self.assertEqual(
+            process.GetThreadAtIndex(0).frame[0].GetLineEntry().GetLine(),
+            bp1_line,
+            "LLDB reported incorrect line number.")
+
+        # Important to use SBProcess::Continue() instead of
+        # self.runCmd('continue'), because the problem doesn't reproduce with
+        # 'continue' command.
+        process.Continue()
+
+        thread = process.GetThreadAtIndex(0)
+        if self.TraceOn():
+            print("Backtrace at the second breakpoint:")
+            for f in thread.frames:
+                print(f)
+        # Check that we have stopped at the breakpoint
+        self.assertEqual(
+            thread.frame[0].GetLineEntry().GetLine(),
+            bp2_line,
+            "LLDB reported incorrect line number.")
+        # Double-check with GetPCAddress()
+        self.assertEqual(
+            thread.frame[0].GetLineEntry().GetLine(),
+            thread.frame[0].GetPCAddress().GetLineEntry().GetLine(),
+            "LLDB reported incorrect line number.")
diff --git a/lldb/test/API/functionalities/unwind/zeroth_frame/main.c b/lldb/test/API/functionalities/unwind/zeroth_frame/main.c
new file mode 100644
index 0000000000000..5886846e83580
--- /dev/null
+++ b/lldb/test/API/functionalities/unwind/zeroth_frame/main.c
@@ -0,0 +1,8 @@
+void func_inner() {
+    int a = 1;  // Set breakpoint 1 here
+}
+
+int main() {
+    func_inner();
+    return 0; // Set breakpoint 2 here
+}
diff --git a/lldb/test/API/lang/cpp/template-function/TestTemplateFunctions.py b/lldb/test/API/lang/cpp/template-function/TestTemplateFunctions.py
index 6c9a0ac35f4fd..0e74185546e84 100644
--- a/lldb/test/API/lang/cpp/template-function/TestTemplateFunctions.py
+++ b/lldb/test/API/lang/cpp/template-function/TestTemplateFunctions.py
@@ -13,14 +13,40 @@ class TemplateFunctionsTestCase(TestBase):
 
     def do_test_template_function(self, add_cast):
         self.build()
-        (_, _, thread, _) = lldbutil.run_to_name_breakpoint(self, "main")
-        frame = thread.GetSelectedFrame()
-        expr = "foo(42)"
+        lldbutil.run_to_source_breakpoint(self, '// break here',
+                lldb.SBFileSpec("main.cpp", False))
+
         if add_cast:
-            expr = "(int)" + expr
-        expr_result = frame.EvaluateExpression(expr)
-        self.assertTrue(expr_result.IsValid())
-        self.assertEqual(expr_result.GetValue(), "42")
+          self.expect_expr("(int) foo(42)", result_type="int", result_value="42")
+        else:
+          self.expect("expr b1 <=> b2",  error=True, substrs=["warning: <user expression 0>:1:4: '<=>' is a single token in C++20; add a space to avoid a change in behavior"])
+
+          self.expect_expr("foo(42)", result_type="int", result_value="42")
+
+          # overload with template case
+          self.expect_expr("h(10)", result_type="int", result_value="10")
+
+          # ADL lookup case
+          self.expect_expr("f(A::C{})", result_type="int", result_value="4")
+
+          # ADL lookup but no overload
+          self.expect_expr("g(A::C{})", result_type="int", result_value="4")
+
+          # variadic function cases
+          self.expect_expr("var(1)", result_type="int", result_value="10")
+          self.expect_expr("var(1, 2)", result_type="int", result_value="10")
+
+          # Overloaded templated operator case
+          self.expect_expr("b1 > b2", result_type="bool", result_value="true")
+          self.expect_expr("b1 >> b2", result_type="bool", result_value="true")
+          self.expect_expr("b1 << b2", result_type="bool", result_value="true")
+          self.expect_expr("b1 == b2", result_type="bool", result_value="true")
+
+          # Overloaded operator case
+          self.expect_expr("d1 > d2", result_type="bool", result_value="true")
+          self.expect_expr("d1 >> d2", result_type="bool", result_value="true")
+          self.expect_expr("d1 << d2", result_type="bool", result_value="true")
+          self.expect_expr("d1 == d2", result_type="bool", result_value="true")
 
     @skipIfWindows
     def test_template_function_with_cast(self):
diff --git a/lldb/test/API/lang/cpp/template-function/main.cpp b/lldb/test/API/lang/cpp/template-function/main.cpp
index c0fbc5cee668b..729638147eb3a 100644
--- a/lldb/test/API/lang/cpp/template-function/main.cpp
+++ b/lldb/test/API/lang/cpp/template-function/main.cpp
@@ -3,6 +3,66 @@ int foo(T t1) {
         return int(t1);
 }
 
+// Some cases to cover ADL, we have two cases:
+//
+// - f which will have a overload in the global namespace if unqualified lookup
+// find f(int) and f(T) is found via ADL.
+//
+// - g which does not have an overload in the global namespace.
+namespace A {
+struct C {};
+
+template <typename T> int f(T) { return 4; }
+
+template <typename T> int g(T) { return 4; }
+} // namespace A
+
+// Meant to overload A::f(T) which may be found via ADL
+int f(int) { return 1; }
+
+// Regular overloaded functions case h(T) and h(double).
+template <class T> int h(T x) { return x; }
+int h(double d) { return 5; }
+
+template <class... Us> int var(Us... pargs) { return 10; }
+
+// Having the templated overloaded operators in a namespace effects the
+// mangled name generated in the IR e.g. _ZltRK1BS1_ Vs _ZN1AltERKNS_1BES2_
+// One will be in the symbol table but the other won't. This results in a
+// different code path that will result in CPlusPlusNameParser being used.
+// This allows us to cover that code as well.
+namespace A {
+template <typename T> bool operator<(const T &, const T &) { return true; }
+
+template <typename T> bool operator>(const T &, const T &) { return true; }
+
+template <typename T> bool operator<<(const T &, const T &) { return true; }
+
+template <typename T> bool operator>>(const T &, const T &) { return true; }
+
+template <typename T> bool operator==(const T &, const T &) { return true; }
+
+struct B {};
+} // namespace A
+
+struct D {};
+
+// Make sure we cover more straight forward cases as well.
+bool operator<(const D &, const D &) { return true; }
+bool operator>(const D &, const D &) { return true; }
+bool operator>>(const D &, const D &) { return true; }
+bool operator<<(const D &, const D &) { return true; }
+bool operator==(const D &, const D &) { return true; }
+
 int main() {
-        return foo(42);
+  A::B b1;
+  A::B b2;
+  D d1;
+  D d2;
+
+  bool result_b = b1 < b2 && b1 << b2 && b1 == b2 && b1 > b2 && b1 >> b2;
+  bool result_c = d1 < d2 && d1 << d2 && d1 == d2 && d1 > d2 && d1 >> d2;
+
+  return foo(42) + result_b + result_c + f(A::C{}) + g(A::C{}) + h(10) + h(1.) +
+         var(1) + var(1, 2); // break here
 }
diff --git a/lldb/test/API/lang/objc/modules-non-objc-target/Makefile b/lldb/test/API/lang/objc/modules-non-objc-target/Makefile
new file mode 100644
index 0000000000000..10495940055b6
--- /dev/null
+++ b/lldb/test/API/lang/objc/modules-non-objc-target/Makefile
@@ -0,0 +1,3 @@
+C_SOURCES := main.c
+
+include Makefile.rules
diff --git a/lldb/test/API/lang/objc/modules-non-objc-target/TestObjCModulesNonObjCTarget.py b/lldb/test/API/lang/objc/modules-non-objc-target/TestObjCModulesNonObjCTarget.py
new file mode 100644
index 0000000000000..18283f6d2b330
--- /dev/null
+++ b/lldb/test/API/lang/objc/modules-non-objc-target/TestObjCModulesNonObjCTarget.py
@@ -0,0 +1,26 @@
+"""
+Tests that importing ObjC modules in a non-ObjC target doesn't crash LLDB.
+"""
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+class TestCase(TestBase):
+
+    mydir = TestBase.compute_mydir(__file__)
+
+    @skipUnlessDarwin
+    def test(self):
+        self.build()
+        lldbutil.run_to_source_breakpoint(self,"// break here", lldb.SBFileSpec("main.c"))
+
+        # Import foundation to get some ObjC types.
+        self.expect("expr --lang objc -- @import Foundation")
+        # Do something with NSString (which requires special handling when
+        # preparing to run in the target). The expression most likely can't
+        # be prepared to run in the target but it should at least not crash LLDB.
+        self.expect('expr --lang objc -- [NSString stringWithFormat:@"%d", 1];',
+                    error=True,
+                    substrs=["error: The expression could not be prepared to run in the target"])
diff --git a/lldb/test/API/lang/objc/modules-non-objc-target/main.c b/lldb/test/API/lang/objc/modules-non-objc-target/main.c
new file mode 100644
index 0000000000000..ba45ee316cd42
--- /dev/null
+++ b/lldb/test/API/lang/objc/modules-non-objc-target/main.c
@@ -0,0 +1,3 @@
+int main() {
+  return 0; // break here
+}
diff --git a/lldb/test/Shell/SymbolFile/DWARF/debug-types-basic.test b/lldb/test/Shell/SymbolFile/DWARF/debug-types-basic.test
index 24a6a651d5f94..947b43ba6b2ff 100644
--- a/lldb/test/Shell/SymbolFile/DWARF/debug-types-basic.test
+++ b/lldb/test/Shell/SymbolFile/DWARF/debug-types-basic.test
@@ -20,7 +20,7 @@
 
 # And type units+dwo+dwarf5.
 # RUN: %clangxx -target x86_64-pc-linux %S/Inputs/debug-types-basic.cpp \
-# RUN:   -g -gdwarf-5 -fdebug-types-section -c -o %t5dwo.o
+# RUN:   -g -gdwarf-5 -fdebug-types-section -gsplit-dwarf -c -o %t5dwo.o
 # RUN: ld.lld %t5dwo.o -o %t5dwo
 # RUN: %lldb %t5dwo -s %s -o exit | FileCheck %s
 
diff --git a/lldb/test/Shell/SymbolFile/DWARF/debug-types-expressions.test b/lldb/test/Shell/SymbolFile/DWARF/debug-types-expressions.test
index 5964eea40adf8..0442cd8faa3b2 100644
--- a/lldb/test/Shell/SymbolFile/DWARF/debug-types-expressions.test
+++ b/lldb/test/Shell/SymbolFile/DWARF/debug-types-expressions.test
@@ -12,12 +12,16 @@
 
 # Test type units in dwo files.
 # RUN: %clangxx_host %S/Inputs/debug-types-expressions.cpp \
-# RUN:   -g -gdwarf-4 -fdebug-types-section -o %t4dwo
+# RUN:   -g -gdwarf-4 -fdebug-types-section -gsplit-dwarf -o %t4dwo \
+# RUN:   -Xclang -split-dwarf-output -Xclang %t4dwo.dwo \
+# RUN:   -Xclang -split-dwarf-file   -Xclang %t4dwo.dwo
 # RUN: %lldb %t4dwo -s %s -o exit | FileCheck %s
 
 # And type units+dwo+dwarf5.
 # RUN: %clangxx_host %S/Inputs/debug-types-expressions.cpp \
-# RUN:   -g -gdwarf-5 -fdebug-types-section -o %t5dwo
+# RUN:   -g -gdwarf-5 -fdebug-types-section -gsplit-dwarf -o %t5dwo \
+# RUN:   -Xclang -split-dwarf-output -Xclang %t5dwo.dwo \
+# RUN:   -Xclang -split-dwarf-file   -Xclang %t5dwo.dwo
 # RUN: %lldb %t5dwo -s %s -o exit | FileCheck %s
 
 breakpoint set -n foo
diff --git a/lldb/test/Shell/SymbolFile/DWARF/dwo-type-in-main-file.s b/lldb/test/Shell/SymbolFile/DWARF/dwo-type-in-main-file.s
new file mode 100644
index 0000000000000..3b6d52c9042a5
--- /dev/null
+++ b/lldb/test/Shell/SymbolFile/DWARF/dwo-type-in-main-file.s
@@ -0,0 +1,180 @@
+# This tests the scenario where a (split) compile unit contains reference to a
+# type, but that type is defined in another compile unit in the main object
+# file.
+
+# REQUIRES: x86
+
+# RUN: llvm-mc %s -o %t --triple=x86_64-pc-linux --filetype=obj --defsym MAIN=0
+# RUN: llvm-mc %s -o %T/dwo-type-in-main-file-cu2.dwo --triple=x86_64-pc-linux --filetype=obj --defsym DWO=0
+# RUN: cd %T
+# RUN: %lldb %t -o "target var a" -b 2>&1 | FileCheck %s
+
+# CHECK: (A) a = (b = 47)
+
+.ifdef MAIN
+        .type   a,@object               # @a
+        .data
+        .globl  a
+        .quad   0 # padding
+a:
+        .long   47                      # 0x2f
+        .size   a, 4
+
+        .section        .debug_addr,"",@progbits
+.Laddr_table_base0:
+        .quad   a
+
+        .section        .debug_info,"",@progbits
+.Lcu_begin0:
+        .long   .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit
+.Ldebug_info_start0:
+        .short  4                       # DWARF version number
+        .long   .debug_abbrev           # Offset Into Abbrev. Section
+        .byte   8                       # Address Size (in bytes)
+        .byte   1                       # Abbrev [1] 0xb:0x89 DW_TAG_compile_unit
+        .asciz  "Hand-written DWARF"    # DW_AT_producer
+        .asciz  "cu1.cc"                # DW_AT_name
+        .byte   2                       # Abbrev [2] 0x2a:0x2d DW_TAG_structure_type
+        .asciz  "A"                     # DW_AT_name
+        .byte   4                       # DW_AT_byte_size
+        .byte   3                       # Abbrev [3] 0x33:0xc DW_TAG_member
+        .asciz  "b"                     # DW_AT_name
+        .long   .Lint                   # DW_AT_type
+        .byte   0                       # DW_AT_data_member_location
+        .byte   0                       # End Of Children Mark
+.Lint:
+        .byte   7                       # Abbrev [7] 0x57:0x7 DW_TAG_base_type
+        .asciz  "int"                   # DW_AT_name
+        .byte   5                       # DW_AT_encoding
+        .byte   4                       # DW_AT_byte_size
+        .byte   0                       # End Of Children Mark
+.Ldebug_info_end0:
+
+.Lcu_begin1:
+        .long   .Ldebug_info_end1-.Ldebug_info_start1 # Length of Unit
+.Ldebug_info_start1:
+        .short  4                       # DWARF version number
+        .long   .debug_abbrev           # Offset Into Abbrev. Section
+        .byte   8                       # Address Size (in bytes)
+        .byte   8                       # Abbrev DW_TAG_compile_unit
+        .asciz  "dwo-type-in-main-file-cu2.dwo" # DW_AT_GNU_dwo_name
+        .quad   5578312047953902346     # DW_AT_GNU_dwo_id
+        .long   .Laddr_table_base0      # DW_AT_GNU_addr_base
+.Ldebug_info_end1:
+
+        .section        .debug_abbrev,"",@progbits
+        .byte   1                       # Abbreviation Code
+        .byte   17                      # DW_TAG_compile_unit
+        .byte   1                       # DW_CHILDREN_yes
+        .byte   37                      # DW_AT_producer
+        .byte   8                       # DW_FORM_string
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   2                       # Abbreviation Code
+        .byte   19                      # DW_TAG_structure_type
+        .byte   1                       # DW_CHILDREN_yes
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .byte   11                      # DW_AT_byte_size
+        .byte   11                      # DW_FORM_data1
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   3                       # Abbreviation Code
+        .byte   13                      # DW_TAG_member
+        .byte   0                       # DW_CHILDREN_no
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .byte   73                      # DW_AT_type
+        .byte   19                      # DW_FORM_ref4
+        .byte   56                      # DW_AT_data_member_location
+        .byte   11                      # DW_FORM_data1
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   7                       # Abbreviation Code
+        .byte   36                      # DW_TAG_base_type
+        .byte   0                       # DW_CHILDREN_no
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .byte   62                      # DW_AT_encoding
+        .byte   11                      # DW_FORM_data1
+        .byte   11                      # DW_AT_byte_size
+        .byte   11                      # DW_FORM_data1
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   8                       # Abbreviation Code
+        .byte   17                      # DW_TAG_compile_unit
+        .byte   0                       # DW_CHILDREN_no
+        .ascii  "\260B"                 # DW_AT_GNU_dwo_name
+        .byte   8                       # DW_FORM_string
+        .ascii  "\261B"                 # DW_AT_GNU_dwo_id
+        .byte   7                       # DW_FORM_data8
+        .ascii  "\263B"                 # DW_AT_GNU_addr_base
+        .byte   23                      # DW_FORM_sec_offset
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   0                       # EOM(3)
+.endif
+
+.ifdef DWO
+        .section        .debug_info.dwo,"e",@progbits
+        .long   .Ldebug_info_dwo_end0-.Ldebug_info_dwo_start0 # Length of Unit
+.Ldebug_info_dwo_start0:
+        .short  4                       # DWARF version number
+        .long   0                       # Offset Into Abbrev. Section
+        .byte   8                       # Address Size (in bytes)
+        .byte   1                       # Abbrev [1] 0xb:0x1c DW_TAG_compile_unit
+        .asciz  "Hand-written DWARF"    # DW_AT_producer
+        .asciz  "cu2.cc"                # DW_AT_name
+        .asciz  "dwo-type-in-main-file-cu2.dwo" # DW_AT_GNU_dwo_name
+        .quad   5578312047953902346     # DW_AT_GNU_dwo_id
+        .byte   2                       # Abbrev [2] 0x19:0xb DW_TAG_variable
+        .asciz  "a"                     # DW_AT_name
+        .long   .LA_fwd-.debug_info.dwo # DW_AT_type
+        .byte   2                       # DW_AT_location
+        .byte   251
+        .byte   0
+.LA_fwd:
+        .byte   3                       # Abbrev [3] 0x24:0x2 DW_TAG_structure_type
+        .asciz  "A"                     # DW_AT_name
+                                        # DW_AT_declaration
+        .byte   0                       # End Of Children Mark
+.Ldebug_info_dwo_end0:
+
+        .section        .debug_abbrev.dwo,"e",@progbits
+        .byte   1                       # Abbreviation Code
+        .byte   17                      # DW_TAG_compile_unit
+        .byte   1                       # DW_CHILDREN_yes
+        .byte   37                      # DW_AT_producer
+        .byte   8                       # DW_FORM_string
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .ascii  "\260B"                 # DW_AT_GNU_dwo_name
+        .byte   8                       # DW_FORM_string
+        .ascii  "\261B"                 # DW_AT_GNU_dwo_id
+        .byte   7                       # DW_FORM_data8
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   2                       # Abbreviation Code
+        .byte   52                      # DW_TAG_variable
+        .byte   0                       # DW_CHILDREN_no
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .byte   73                      # DW_AT_type
+        .byte   19                      # DW_FORM_ref4
+        .byte   2                       # DW_AT_location
+        .byte   24                      # DW_FORM_exprloc
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   3                       # Abbreviation Code
+        .byte   19                      # DW_TAG_structure_type
+        .byte   0                       # DW_CHILDREN_no
+        .byte   3                       # DW_AT_name
+        .byte   8                       # DW_FORM_string
+        .byte   60                      # DW_AT_declaration
+        .byte   25                      # DW_FORM_flag_present
+        .byte   0                       # EOM(1)
+        .byte   0                       # EOM(2)
+        .byte   0                       # EOM(3)
+.endif
diff --git a/lldb/tools/debugserver/resources/lldb-debugserver-Info.plist b/lldb/tools/debugserver/resources/lldb-debugserver-Info.plist
index 343325c2765cb..ddaf0644f2cf2 100644
--- a/lldb/tools/debugserver/resources/lldb-debugserver-Info.plist
+++ b/lldb/tools/debugserver/resources/lldb-debugserver-Info.plist
@@ -12,10 +12,5 @@
     <string>debugserver</string>
     <key>CFBundleVersion</key>
     <string>2</string>
-	<key>SecTaskAccess</key>
-	<array>
-		<string>allowed</string>
-		<string>debug</string>
-	</array>
 </dict>
 </plist>
diff --git a/lldb/unittests/Platform/PlatformDarwinTest.cpp b/lldb/unittests/Platform/PlatformDarwinTest.cpp
index a329fd5721361..06287c63227b6 100644
--- a/lldb/unittests/Platform/PlatformDarwinTest.cpp
+++ b/lldb/unittests/Platform/PlatformDarwinTest.cpp
@@ -18,6 +18,8 @@ using namespace lldb;
 using namespace lldb_private;
 
 struct PlatformDarwinTester : public PlatformDarwin {
+public:
+  using PlatformDarwin::FindXcodeContentsDirectoryInPath;
   static bool SDKSupportsModules(SDKType desired_type,
                                  const lldb_private::FileSpec &sdk_path) {
     return PlatformDarwin::SDKSupportsModules(desired_type, sdk_path);
@@ -69,3 +71,64 @@ TEST(PlatformDarwinTest, TestParseVersionBuildDir) {
       PlatformDarwin::SDKType::MacOSX,
       FileSpec(base + "MacOSX.platform/Developer/SDKs/MacOSX10.9.sdk")));
 }
+
+TEST(PlatformDarwinTest, FindXcodeContentsDirectoryInPath) {
+  std::string standard =
+      "/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/"
+      "Developer/SDKs/MacOSX.sdk";
+  EXPECT_EQ("/Applications/Xcode.app/Contents",
+            PlatformDarwinTester::FindXcodeContentsDirectoryInPath(standard));
+
+  std::string standard_version =
+      "/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/"
+      "Developer/SDKs/MacOSX10.15.sdk";
+  EXPECT_EQ(
+      "/Applications/Xcode.app/Contents",
+      PlatformDarwinTester::FindXcodeContentsDirectoryInPath(standard_version));
+
+  std::string beta = "/Applications/Xcode-beta.app/Contents/Developer/"
+                     "Platforms/MacOSX.platform/"
+                     "Developer/SDKs/MacOSX10.15.sdk";
+  EXPECT_EQ("/Applications/Xcode-beta.app/Contents",
+            PlatformDarwinTester::FindXcodeContentsDirectoryInPath(beta));
+
+  std::string no_app =
+      "/Applications/Xcode/Contents/Developer/Platforms/MacOSX.platform/"
+      "Developer/SDKs/MacOSX10.15.sdk";
+  EXPECT_EQ("", PlatformDarwinTester::FindXcodeContentsDirectoryInPath(no_app));
+
+  std::string no_contents =
+      "/Applications/Xcode.app/Developer/Platforms/MacOSX.platform/"
+      "Developer/SDKs/MacOSX10.15.sdk";
+  EXPECT_EQ(
+      "", PlatformDarwinTester::FindXcodeContentsDirectoryInPath(no_contents));
+
+  std::string no_capitalization =
+      "/Applications/Xcode.app/contents/Developer/Platforms/MacOSX.platform/"
+      "Developer/SDKs/MacOSX10.15.sdk";
+  EXPECT_EQ("", PlatformDarwinTester::FindXcodeContentsDirectoryInPath(
+                    no_capitalization));
+}
+
+TEST(PlatformDarwinTest, GetSDKNameForType) {
+  EXPECT_EQ("macosx",
+            PlatformDarwin::GetSDKNameForType(PlatformDarwin::SDKType::MacOSX));
+  EXPECT_EQ("iphonesimulator", PlatformDarwin::GetSDKNameForType(
+                                   PlatformDarwin::SDKType::iPhoneSimulator));
+  EXPECT_EQ("iphoneos", PlatformDarwin::GetSDKNameForType(
+                            PlatformDarwin::SDKType::iPhoneOS));
+  EXPECT_EQ("appletvsimulator", PlatformDarwin::GetSDKNameForType(
+                                    PlatformDarwin::SDKType::AppleTVSimulator));
+  EXPECT_EQ("appletvos", PlatformDarwin::GetSDKNameForType(
+                             PlatformDarwin::SDKType::AppleTVOS));
+  EXPECT_EQ("watchsimulator", PlatformDarwin::GetSDKNameForType(
+                                  PlatformDarwin::SDKType::WatchSimulator));
+  EXPECT_EQ("watchos", PlatformDarwin::GetSDKNameForType(
+                           PlatformDarwin::SDKType::watchOS));
+  EXPECT_EQ("linux",
+            PlatformDarwin::GetSDKNameForType(PlatformDarwin::SDKType::Linux));
+  EXPECT_EQ("", PlatformDarwin::GetSDKNameForType(
+                    PlatformDarwin::SDKType::numSDKTypes));
+  EXPECT_EQ(
+      "", PlatformDarwin::GetSDKNameForType(PlatformDarwin::SDKType::unknown));
+}
diff --git a/lldb/unittests/Target/StackFrameRecognizerTest.cpp b/lldb/unittests/Target/StackFrameRecognizerTest.cpp
index f7b7829e2bb8d..067a56a19902b 100644
--- a/lldb/unittests/Target/StackFrameRecognizerTest.cpp
+++ b/lldb/unittests/Target/StackFrameRecognizerTest.cpp
@@ -76,8 +76,7 @@ TEST_F(StackFrameRecognizerTest, NullModuleRegex) {
   bool any_printed = false;
   StackFrameRecognizerManager::ForEach(
       [&any_printed](uint32_t recognizer_id, std::string name,
-                     std::string function, std::string symbol,
-                     std::string alternate_symbol,
+                     std::string function, llvm::ArrayRef<ConstString> symbols,
                      bool regexp) { any_printed = true; });
 
   EXPECT_TRUE(any_printed);
diff --git a/lldb/utils/lldb-dotest/lldb-dotest.in b/lldb/utils/lldb-dotest/lldb-dotest.in
index b5acd9ba29c50..edddaf4cd0c21 100755
--- a/lldb/utils/lldb-dotest/lldb-dotest.in
+++ b/lldb/utils/lldb-dotest/lldb-dotest.in
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!@PYTHON_EXECUTABLE@
 import subprocess
 import sys
 
diff --git a/llvm-spirv/include/LLVMSPIRVExtensions.inc b/llvm-spirv/include/LLVMSPIRVExtensions.inc
index 7e6b8a7a552b0..6071892c8b400 100644
--- a/llvm-spirv/include/LLVMSPIRVExtensions.inc
+++ b/llvm-spirv/include/LLVMSPIRVExtensions.inc
@@ -15,3 +15,4 @@ EXT(SPV_INTEL_blocking_pipes)
 EXT(SPV_INTEL_function_pointers)
 EXT(SPV_INTEL_kernel_attributes)
 EXT(SPV_INTEL_io_pipes)
+EXT(SPV_INTEL_inline_assembly)
diff --git a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp
index 692bb7e0106a7..3283646f305d7 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp
+++ b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp
@@ -38,6 +38,7 @@
 //===----------------------------------------------------------------------===//
 #include "SPIRVReader.h"
 #include "OCLUtil.h"
+#include "SPIRVAsm.h"
 #include "SPIRVBasicBlock.h"
 #include "SPIRVExtInst.h"
 #include "SPIRVFunction.h"
@@ -57,6 +58,7 @@
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/LegacyPassManager.h"
@@ -1516,6 +1518,9 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
   case OpFunction:
     return mapValue(BV, transFunction(static_cast<SPIRVFunction *>(BV)));
 
+  case OpAsmINTEL:
+    return mapValue(BV, transAsmINTEL(static_cast<SPIRVAsmINTEL *>(BV)));
+
   case OpLabel:
     return mapValue(BV, BasicBlock::Create(*Context, BV->getName(), F));
 
@@ -2112,6 +2117,10 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
     return mapValue(BV, Call);
   }
 
+  case OpAsmCallINTEL:
+    return mapValue(
+        BV, transAsmCallINTEL(static_cast<SPIRVAsmCallINTEL *>(BV), F, BB));
+
   case OpFunctionPointerCallINTEL: {
     SPIRVFunctionPointerCallINTEL *BC =
         static_cast<SPIRVFunctionPointerCallINTEL *>(BV);
@@ -2380,6 +2389,24 @@ Function *SPIRVToLLVM::transFunction(SPIRVFunction *BF) {
   return F;
 }
 
+Value *SPIRVToLLVM::transAsmINTEL(SPIRVAsmINTEL *BA) {
+  assert(BA);
+  bool HasSideEffect = BA->hasDecorate(DecorationSideEffectsINTEL);
+  return InlineAsm::get(
+      cast<FunctionType>(transType(BA->getFunctionType())),
+      BA->getInstructions(), BA->getConstraints(), HasSideEffect,
+      /* IsAlignStack */ false, InlineAsm::AsmDialect::AD_ATT);
+}
+
+CallInst *SPIRVToLLVM::transAsmCallINTEL(SPIRVAsmCallINTEL *BI, Function *F,
+                                         BasicBlock *BB) {
+  assert(BI);
+  auto *IA = cast<InlineAsm>(transValue(BI->getAsm(), F, BB));
+  auto Args = transValue(BM->getValues(BI->getArguments()), F, BB);
+  return CallInst::Create(cast<FunctionType>(IA->getFunctionType()), IA, Args,
+                          BI->getName(), BB);
+}
+
 /// LLVM convert builtin functions is translated to two instructions:
 /// y = i32 islessgreater(float x, float z) ->
 ///     y = i32 ZExt(bool LessOrGreater(float x, float z))
diff --git a/llvm-spirv/lib/SPIRV/SPIRVReader.h b/llvm-spirv/lib/SPIRV/SPIRVReader.h
index 89d27c09d4b6d..42ebdcf0721f8 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVReader.h
+++ b/llvm-spirv/lib/SPIRV/SPIRVReader.h
@@ -103,6 +103,9 @@ class SPIRVToLLVM {
   Instruction *transSGSizeQueryBI(SPIRVInstruction *BI, BasicBlock *BB);
   bool transFPContractMetadata();
   bool transKernelMetadata();
+  Value *transAsmINTEL(SPIRVAsmINTEL *BA);
+  CallInst *transAsmCallINTEL(SPIRVAsmCallINTEL *BI, Function *F,
+                              BasicBlock *BB);
   bool transNonTemporalMetadata(Instruction *I);
   bool transSourceLanguage();
   bool transSourceExtension();
diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
index 3eee174dca32a..58c25e59d38d5 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
+++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
@@ -40,6 +40,7 @@
 
 #include "SPIRVWriter.h"
 #include "LLVMToSPIRVDbgTran.h"
+#include "SPIRVAsm.h"
 #include "SPIRVBasicBlock.h"
 #include "SPIRVEntry.h"
 #include "SPIRVEnum.h"
@@ -60,6 +61,7 @@
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Function.h"
+#include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/InstrTypes.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
@@ -208,7 +210,7 @@ static bool recursiveType(const StructType *ST, const Type *Ty) {
   SmallPtrSet<const StructType *, 4> Seen;
 
   std::function<bool(const Type *Ty)> Run = [&](const Type *Ty) {
-    if (!isa<CompositeType>(Ty) && !Ty->isPointerTy())
+    if (!(isa<StructType>(Ty) || isa<SequentialType>(Ty)) && !Ty->isPointerTy())
       return false;
 
     if (auto *StructTy = dyn_cast<StructType>(Ty)) {
@@ -387,7 +389,8 @@ SPIRVType *LLVMToSPIRV::transType(Type *T) {
 
     for (unsigned I = 0, E = T->getStructNumElements(); I != E; ++I) {
       auto *ElemTy = ST->getElementType(I);
-      if ((isa<CompositeType>(ElemTy) || isa<PointerType>(ElemTy)) &&
+      if ((isa<StructType>(ElemTy) || isa<SequentialType>(ElemTy) ||
+           isa<PointerType>(ElemTy)) &&
           recursiveType(ST, ElemTy))
         ForwardRefs.push_back(I);
       else
@@ -1267,6 +1270,10 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V,
     return BV ? mapValue(V, BV) : nullptr;
   }
 
+  if (InlineAsm *IA = dyn_cast<InlineAsm>(V))
+    if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_inline_assembly))
+      return mapValue(V, transAsmINTEL(IA));
+
   if (CallInst *CI = dyn_cast<CallInst>(V))
     return mapValue(V, transCallInst(CI, BB));
 
@@ -1776,6 +1783,11 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
 }
 
 SPIRVValue *LLVMToSPIRV::transCallInst(CallInst *CI, SPIRVBasicBlock *BB) {
+  assert(CI);
+  if (isa<InlineAsm>(CI->getCalledOperand()) &&
+      BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_inline_assembly))
+    return transAsmCallINTEL(CI, BB);
+
   if (CI->isIndirectCall())
     return transIndirectCallInst(CI, BB);
   return transDirectCallInst(CI, BB);
@@ -1829,6 +1841,32 @@ SPIRVValue *LLVMToSPIRV::transIndirectCallInst(CallInst *CI,
       BB);
 }
 
+SPIRVValue *LLVMToSPIRV::transAsmINTEL(InlineAsm *IA) {
+  assert(IA);
+
+  // TODO: intention here is to provide information about actual target
+  //       but in fact spir-64 is substituted as triple when translator works
+  //       eventually we need to fix it (not urgent)
+  StringRef TripleStr(M->getTargetTriple());
+  auto AsmTarget = static_cast<SPIRVAsmTargetINTEL *>(
+      BM->getOrAddAsmTargetINTEL(TripleStr.str()));
+  auto SIA = BM->addAsmINTEL(
+      static_cast<SPIRVTypeFunction *>(transType(IA->getFunctionType())),
+      AsmTarget, IA->getAsmString(), IA->getConstraintString());
+  if (IA->hasSideEffects())
+    SIA->addDecorate(DecorationSideEffectsINTEL);
+  return SIA;
+}
+
+SPIRVValue *LLVMToSPIRV::transAsmCallINTEL(CallInst *CI, SPIRVBasicBlock *BB) {
+  assert(CI);
+  auto IA = cast<InlineAsm>(CI->getCalledOperand());
+  return BM->addAsmCallINTELInst(
+      static_cast<SPIRVAsmINTEL *>(transValue(IA, BB, false)),
+      transArguments(CI, BB, SPIRVEntry::createUnique(OpAsmCallINTEL).get()),
+      BB);
+}
+
 bool LLVMToSPIRV::transAddressingMode() {
   Triple TargetTriple(M->getTargetTriple());
 
diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.h b/llvm-spirv/lib/SPIRV/SPIRVWriter.h
index de4a499f67796..f83cf98abfc90 100644
--- a/llvm-spirv/lib/SPIRV/SPIRVWriter.h
+++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.h
@@ -100,6 +100,8 @@ class LLVMToSPIRV : public ModulePass {
   SPIRVValue *transCallInst(CallInst *Call, SPIRVBasicBlock *BB);
   SPIRVValue *transDirectCallInst(CallInst *Call, SPIRVBasicBlock *BB);
   SPIRVValue *transIndirectCallInst(CallInst *Call, SPIRVBasicBlock *BB);
+  SPIRVValue *transAsmINTEL(InlineAsm *Asm);
+  SPIRVValue *transAsmCallINTEL(CallInst *Call, SPIRVBasicBlock *BB);
   bool transDecoration(Value *V, SPIRVValue *BV);
   SPIRVWord transFunctionControlMask(Function *);
   SPIRVFunction *transFunctionDecl(Function *F);
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVAsm.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVAsm.h
new file mode 100644
index 0000000000000..d1ee9d8cb1253
--- /dev/null
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVAsm.h
@@ -0,0 +1,142 @@
+//===- SPIRVAsm.h -                                           --*- C++ -*-===//
+//
+//                     The LLVM/SPIRV Translator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the inline assembler entries defined in SPIRV spec with op
+/// codes.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef SPIRV_LIBSPIRV_SPIRVASM_H
+#define SPIRV_LIBSPIRV_SPIRVASM_H
+
+#include "SPIRVEntry.h"
+#include "SPIRVInstruction.h"
+#include "SPIRVValue.h"
+
+namespace SPIRV {
+
+class SPIRVAsmTargetINTEL : public SPIRVEntry {
+public:
+  static const SPIRVWord FixedWC = 2;
+  static const Op OC = OpAsmTargetINTEL;
+  // Complete constructor
+  SPIRVAsmTargetINTEL(SPIRVModule *M, SPIRVId TheId,
+                      const std::string &TheTarget)
+      : SPIRVEntry(M, FixedWC + getSizeInWords(TheTarget), OC, TheId),
+        Target(TheTarget) {
+    validate();
+  }
+  // Incomplete constructor
+  SPIRVAsmTargetINTEL() : SPIRVEntry(OC) {}
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityAsmINTEL);
+  }
+  SPIRVExtSet getRequiredExtensions() const override {
+    return getSet(ExtensionID::SPV_INTEL_inline_assembly);
+  }
+  const std::string &getTarget() const { return Target; }
+
+protected:
+  void validate() const override {
+    SPIRVEntry::validate();
+    assert(WordCount > FixedWC);
+    assert(OpCode == OC);
+  }
+  _SPIRV_DEF_ENCDEC2(Id, Target)
+  std::string Target;
+};
+
+class SPIRVAsmINTEL : public SPIRVValue {
+public:
+  static const SPIRVWord FixedWC = 5;
+  static const Op OC = OpAsmINTEL;
+  // Complete constructor
+  SPIRVAsmINTEL(SPIRVModule *M, SPIRVTypeFunction *TheFunctionType,
+                SPIRVId TheId, SPIRVAsmTargetINTEL *TheTarget,
+                const std::string &TheInstructions,
+                const std::string &TheConstraints)
+      : SPIRVValue(M,
+                   FixedWC + getSizeInWords(TheInstructions) +
+                       getSizeInWords(TheConstraints),
+                   OC, TheFunctionType->getReturnType(), TheId),
+        Target(TheTarget), FunctionType(TheFunctionType),
+        Instructions(TheInstructions), Constraints(TheConstraints) {
+    validate();
+  }
+  // Incomplete constructor
+  SPIRVAsmINTEL() : SPIRVValue(OC) {}
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityAsmINTEL);
+  }
+  SPIRVExtSet getRequiredExtensions() const override {
+    return getSet(ExtensionID::SPV_INTEL_inline_assembly);
+  }
+  const std::string &getInstructions() const { return Instructions; }
+  const std::string &getConstraints() const { return Constraints; }
+  SPIRVTypeFunction *getFunctionType() const { return FunctionType; }
+
+protected:
+  _SPIRV_DEF_ENCDEC6(Type, Id, FunctionType, Target, Instructions, Constraints)
+  void validate() const override {
+    SPIRVValue::validate();
+    assert(WordCount > FixedWC);
+    assert(OpCode == OC);
+  }
+  SPIRVAsmTargetINTEL *Target;
+  SPIRVTypeFunction *FunctionType;
+  std::string Instructions;
+  std::string Constraints;
+};
+
+class SPIRVAsmCallINTEL : public SPIRVInstruction {
+public:
+  static const SPIRVWord FixedWC = 4;
+  static const Op OC = OpAsmCallINTEL;
+  // Complete constructor
+  SPIRVAsmCallINTEL(SPIRVId TheId, SPIRVAsmINTEL *TheAsm,
+                    const std::vector<SPIRVWord> &TheArgs,
+                    SPIRVBasicBlock *TheBB)
+      : SPIRVInstruction(FixedWC + TheArgs.size(), OC, TheAsm->getType(), TheId,
+                         TheBB),
+        Asm(TheAsm), Args(TheArgs) {
+    validate();
+  }
+  // Incomplete constructor
+  SPIRVAsmCallINTEL() : SPIRVInstruction(OC) {}
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityAsmINTEL);
+  }
+  SPIRVExtSet getRequiredExtensions() const override {
+    return getSet(ExtensionID::SPV_INTEL_inline_assembly);
+  }
+  bool isOperandLiteral(unsigned int Index) const override { return false; }
+  void setWordCount(SPIRVWord TheWordCount) override {
+    SPIRVEntry::setWordCount(TheWordCount);
+    Args.resize(TheWordCount - FixedWC);
+  }
+  const std::vector<SPIRVWord> &getArguments() const { return Args; }
+
+  SPIRVAsmINTEL *getAsm() const { return Asm; }
+
+protected:
+  _SPIRV_DEF_ENCDEC4(Type, Id, Asm, Args)
+  void validate() const override {
+    SPIRVInstruction::validate();
+    assert(WordCount >= FixedWC);
+    assert(OpCode == OC);
+    assert(getBasicBlock() && "Invalid BB");
+    assert(getBasicBlock()->getModule() == Asm->getModule());
+  }
+  SPIRVAsmINTEL *Asm;
+  std::vector<SPIRVWord> Args;
+};
+
+} // namespace SPIRV
+#endif // SPIRV_LIBSPIRV_SPIRVASM_H
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
index 6bc701bf53a54..28bacfdb46d20 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
@@ -38,6 +38,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "SPIRVEntry.h"
+#include "SPIRVAsm.h"
 #include "SPIRVBasicBlock.h"
 #include "SPIRVDebug.h"
 #include "SPIRVDecorate.h"
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
index 33308a1df8522..eed9a76cc032e 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
@@ -366,6 +366,7 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
   ADD_VEC_INIT(DecorationReferencedIndirectlyINTEL,
                {CapabilityIndirectReferencesINTEL});
   ADD_VEC_INIT(DecorationIOPipeStorageINTEL, {CapabilityIOPipeINTEL});
+  ADD_VEC_INIT(DecorationSideEffectsINTEL, {CapabilityAsmINTEL});
 }
 
 template <> inline void SPIRVMap<BuiltIn, SPIRVCapVec>::init() {
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
index d3ef9d22f7a06..5e59bd704bb07 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
@@ -893,6 +893,9 @@ inline bool isValid(spv::Op V) {
   case OpSubgroupImageBlockWriteINTEL:
   case OpSubgroupImageMediaBlockReadINTEL:
   case OpSubgroupImageMediaBlockWriteINTEL:
+  case OpAsmTargetINTEL:
+  case OpAsmINTEL:
+  case OpAsmCallINTEL:
   case OpVmeImageINTEL:
   case OpTypeVmeImageINTEL:
   case OpTypeAvcImePayloadINTEL:
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
index 0cb669c104f3f..d9cccd2d936ca 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
@@ -38,6 +38,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "SPIRVModule.h"
+#include "SPIRVAsm.h"
 #include "SPIRVDebug.h"
 #include "SPIRVEntry.h"
 #include "SPIRVExtInst.h"
@@ -297,6 +298,12 @@ class SPIRVModuleImpl : public SPIRVModule {
                                         SPIRVBasicBlock *) override;
   SPIRVInstruction *addFunctionPointerINTELInst(SPIRVType *, SPIRVFunction *,
                                                 SPIRVBasicBlock *) override;
+  SPIRVEntry *getOrAddAsmTargetINTEL(const std::string &) override;
+  SPIRVValue *addAsmINTEL(SPIRVTypeFunction *, SPIRVAsmTargetINTEL *,
+                          const std::string &, const std::string &) override;
+  SPIRVInstruction *addAsmCallINTELInst(SPIRVAsmINTEL *,
+                                        const std::vector<SPIRVWord> &,
+                                        SPIRVBasicBlock *) override;
   SPIRVInstruction *addCmpInst(Op, SPIRVType *, SPIRVValue *, SPIRVValue *,
                                SPIRVBasicBlock *) override;
   SPIRVInstruction *addLoadInst(SPIRVValue *, const std::vector<SPIRVWord> &,
@@ -444,6 +451,8 @@ class SPIRVModuleImpl : public SPIRVModule {
   typedef std::vector<SPIRVMemberName *> SPIRVMemberNameVec;
   typedef std::vector<SPIRVDecorationGroup *> SPIRVDecGroupVec;
   typedef std::vector<SPIRVGroupDecorateGeneric *> SPIRVGroupDecVec;
+  typedef std::vector<SPIRVAsmTargetINTEL *> SPIRVAsmTargetVector;
+  typedef std::vector<SPIRVAsmINTEL *> SPIRVAsmVector;
   typedef std::map<SPIRVId, SPIRVExtInstSetKind> SPIRVIdToInstructionSetMap;
   std::map<SPIRVExtInstSetKind, SPIRVId> ExtInstSetIds;
   typedef std::map<SPIRVId, SPIRVExtInstSetKind> SPIRVIdToBuiltinSetMap;
@@ -469,6 +478,8 @@ class SPIRVModuleImpl : public SPIRVModule {
   SPIRVDecorateSet DecorateSet;
   SPIRVDecGroupVec DecGroupVec;
   SPIRVGroupDecVec GroupDecVec;
+  SPIRVAsmTargetVector AsmTargetVec;
+  SPIRVAsmVector AsmVec;
   SPIRVExecModelIdSetMap EntryPointSet;
   SPIRVExecModelIdVecMap EntryPointVec;
   SPIRVStringMap StrMap;
@@ -632,6 +643,14 @@ void SPIRVModuleImpl::layoutEntry(SPIRVEntry *E) {
     }
     break;
   }
+  case OpAsmTargetINTEL: {
+    addTo(AsmTargetVec, E);
+    break;
+  }
+  case OpAsmINTEL: {
+    addTo(AsmVec, E);
+    break;
+  }
   default:
     if (isTypeOpCode(OC))
       TypeVec.push_back(static_cast<SPIRVType *>(E));
@@ -1212,6 +1231,34 @@ SPIRVInstruction *SPIRVModuleImpl::addFunctionPointerINTELInst(
       new SPIRVFunctionPointerINTEL(getId(), TheType, TheFunction, BB), BB);
 }
 
+SPIRVEntry *
+SPIRVModuleImpl::getOrAddAsmTargetINTEL(const std::string &TheTarget) {
+  auto TargetIt = std::find_if(AsmTargetVec.begin(), AsmTargetVec.end(),
+                               [&TheTarget](const SPIRVAsmTargetINTEL *Target) {
+                                 return Target->getTarget() == TheTarget;
+                               });
+  if (TargetIt == AsmTargetVec.end())
+    return add(new SPIRVAsmTargetINTEL(this, getId(), TheTarget));
+  return *TargetIt;
+}
+
+SPIRVValue *SPIRVModuleImpl::addAsmINTEL(SPIRVTypeFunction *TheType,
+                                         SPIRVAsmTargetINTEL *TheTarget,
+                                         const std::string &TheInstructions,
+                                         const std::string &TheConstraints) {
+  auto Asm = new SPIRVAsmINTEL(this, TheType, getId(), TheTarget,
+                               TheInstructions, TheConstraints);
+  return add(Asm);
+}
+
+SPIRVInstruction *
+SPIRVModuleImpl::addAsmCallINTELInst(SPIRVAsmINTEL *TheAsm,
+                                     const std::vector<SPIRVWord> &TheArguments,
+                                     SPIRVBasicBlock *BB) {
+  return addInstruction(
+      new SPIRVAsmCallINTEL(getId(), TheAsm, TheArguments, BB), BB);
+}
+
 SPIRVInstruction *SPIRVModuleImpl::addBinaryInst(Op TheOpCode, SPIRVType *Type,
                                                  SPIRVValue *Op1,
                                                  SPIRVValue *Op2,
@@ -1606,8 +1653,13 @@ spv_ostream &operator<<(spv_ostream &O, SPIRVModule &M) {
   O << MI.MemberNameVec << MI.DecGroupVec << MI.DecorateSet << MI.GroupDecVec
     << MI.ForwardPointerVec
     << TopologicalSort(MI.TypeVec, MI.ConstVec, MI.VariableVec,
-                       MI.ForwardPointerVec)
-    << SPIRVNL() << MI.DebugInstVec << SPIRVNL() << MI.FuncVec;
+                       MI.ForwardPointerVec);
+
+  if (M.isAllowedToUseExtension(ExtensionID::SPV_INTEL_inline_assembly)) {
+    O << SPIRVNL() << MI.AsmTargetVec << MI.AsmVec;
+  }
+
+  O << SPIRVNL() << MI.DebugInstVec << SPIRVNL() << MI.FuncVec;
   return O;
 }
 
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h
index a9a0ed0368f06..d753fbf6238b4 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h
@@ -86,6 +86,9 @@ class SPIRVGroupDecorate;
 class SPIRVGroupMemberDecorate;
 class SPIRVGroupDecorateGeneric;
 class SPIRVInstTemplateBase;
+class SPIRVAsmTargetINTEL;
+class SPIRVAsmINTEL;
+class SPIRVAsmCallINTEL;
 
 typedef SPIRVBasicBlock SPIRVLabel;
 struct SPIRVTypeImageDescriptor;
@@ -303,6 +306,12 @@ class SPIRVModule {
   virtual SPIRVInstruction *addFunctionPointerINTELInst(SPIRVType *,
                                                         SPIRVFunction *,
                                                         SPIRVBasicBlock *) = 0;
+  virtual SPIRVEntry *getOrAddAsmTargetINTEL(const std::string &) = 0;
+  virtual SPIRVValue *addAsmINTEL(SPIRVTypeFunction *, SPIRVAsmTargetINTEL *,
+                                  const std::string &, const std::string &) = 0;
+  virtual SPIRVInstruction *addAsmCallINTELInst(SPIRVAsmINTEL *,
+                                                const std::vector<SPIRVWord> &,
+                                                SPIRVBasicBlock *) = 0;
   virtual SPIRVInstruction *
   addCompositeConstructInst(SPIRVType *, const std::vector<SPIRVId> &,
                             SPIRVBasicBlock *) = 0;
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
index 1e3c6f09b9f48..41c22c5342883 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -335,6 +335,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
   add(DecorationMaxByteOffset, "MaxByteOffset");
   add(DecorationNoSignedWrap, "NoSignedWrap");
   add(DecorationNoUnsignedWrap, "NoUnsignedWrap");
+  add(DecorationSideEffectsINTEL, "SideEffectsINTEL");
   add(DecorationUserSemantic, "UserSemantic");
   add(DecorationRegisterINTEL, "RegisterINTEL");
   add(DecorationMemoryINTEL, "MemoryINTEL");
@@ -488,6 +489,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(CapabilitySubgroupImageBlockIOINTEL, "SubgroupImageBlockIOINTEL");
   add(CapabilitySubgroupImageMediaBlockIOINTEL,
       "SubgroupImageMediaBlockIOINTEL");
+  add(CapabilityAsmINTEL, "AsmINTEL");
   add(CapabilitySubgroupAvcMotionEstimationINTEL,
       "SubgroupAvcMotionEstimationINTEL");
   add(CapabilitySubgroupAvcMotionEstimationIntraINTEL,
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
index 127960329750c..be24e40a5de74 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
@@ -307,6 +307,9 @@ _SPIRV_OP(SubgroupImageMediaBlockReadINTEL, 5580)
 _SPIRV_OP(SubgroupImageMediaBlockWriteINTEL, 5581)
 _SPIRV_OP(FunctionPointerINTEL, 5600)
 _SPIRV_OP(FunctionPointerCallINTEL, 5601)
+_SPIRV_OP(AsmTargetINTEL, 5609)
+_SPIRV_OP(AsmINTEL, 5610)
+_SPIRV_OP(AsmCallINTEL, 5611)
 _SPIRV_OP(VmeImageINTEL, 5699)
 _SPIRV_OP(TypeVmeImageINTEL, 5700)
 _SPIRV_OP(TypeAvcImePayloadINTEL, 5701)
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
index 6cc74c2200242..be25d4754fb25 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
@@ -342,71 +342,72 @@ enum FunctionParameterAttribute {
 };
 
 enum Decoration {
-    DecorationRelaxedPrecision = 0,
-    DecorationSpecId = 1,
-    DecorationBlock = 2,
-    DecorationBufferBlock = 3,
-    DecorationRowMajor = 4,
-    DecorationColMajor = 5,
-    DecorationArrayStride = 6,
-    DecorationMatrixStride = 7,
-    DecorationGLSLShared = 8,
-    DecorationGLSLPacked = 9,
-    DecorationCPacked = 10,
-    DecorationBuiltIn = 11,
-    DecorationNoPerspective = 13,
-    DecorationFlat = 14,
-    DecorationPatch = 15,
-    DecorationCentroid = 16,
-    DecorationSample = 17,
-    DecorationInvariant = 18,
-    DecorationRestrict = 19,
-    DecorationAliased = 20,
-    DecorationVolatile = 21,
-    DecorationConstant = 22,
-    DecorationCoherent = 23,
-    DecorationNonWritable = 24,
-    DecorationNonReadable = 25,
-    DecorationUniform = 26,
-    DecorationSaturatedConversion = 28,
-    DecorationStream = 29,
-    DecorationLocation = 30,
-    DecorationComponent = 31,
-    DecorationIndex = 32,
-    DecorationBinding = 33,
-    DecorationDescriptorSet = 34,
-    DecorationOffset = 35,
-    DecorationXfbBuffer = 36,
-    DecorationXfbStride = 37,
-    DecorationFuncParamAttr = 38,
-    DecorationFPRoundingMode = 39,
-    DecorationFPFastMathMode = 40,
-    DecorationLinkageAttributes = 41,
-    DecorationNoContraction = 42,
-    DecorationInputAttachmentIndex = 43,
-    DecorationAlignment = 44,
-    DecorationMaxByteOffset = 45,
-    DecorationNoSignedWrap = 4469,
-    DecorationNoUnsignedWrap = 4470,
-    DecorationOverrideCoverageNV = 5248,
-    DecorationPassthroughNV = 5250,
-    DecorationViewportRelativeNV = 5252,
-    DecorationSecondaryViewportRelativeNV = 5256,
-    DecorationReferencedIndirectlyINTEL = 5602,
-    DecorationUserSemantic = 5635,
-    DecorationRegisterINTEL = 5825,
-    DecorationMemoryINTEL = 5826,
-    DecorationNumbanksINTEL = 5827,
-    DecorationBankwidthINTEL = 5828,
-    DecorationMaxPrivateCopiesINTEL = 5829,
-    DecorationSinglepumpINTEL = 5830,
-    DecorationDoublepumpINTEL = 5831,
-    DecorationMaxReplicatesINTEL = 5832,
-    DecorationSimpleDualPortINTEL = 5833,
-    DecorationMergeINTEL = 5834,
-    DecorationBankBitsINTEL = 5835,
-    DecorationIOPipeStorageINTEL = 5944,
-    DecorationMax = 0x7fffffff,
+  DecorationRelaxedPrecision = 0,
+  DecorationSpecId = 1,
+  DecorationBlock = 2,
+  DecorationBufferBlock = 3,
+  DecorationRowMajor = 4,
+  DecorationColMajor = 5,
+  DecorationArrayStride = 6,
+  DecorationMatrixStride = 7,
+  DecorationGLSLShared = 8,
+  DecorationGLSLPacked = 9,
+  DecorationCPacked = 10,
+  DecorationBuiltIn = 11,
+  DecorationNoPerspective = 13,
+  DecorationFlat = 14,
+  DecorationPatch = 15,
+  DecorationCentroid = 16,
+  DecorationSample = 17,
+  DecorationInvariant = 18,
+  DecorationRestrict = 19,
+  DecorationAliased = 20,
+  DecorationVolatile = 21,
+  DecorationConstant = 22,
+  DecorationCoherent = 23,
+  DecorationNonWritable = 24,
+  DecorationNonReadable = 25,
+  DecorationUniform = 26,
+  DecorationSaturatedConversion = 28,
+  DecorationStream = 29,
+  DecorationLocation = 30,
+  DecorationComponent = 31,
+  DecorationIndex = 32,
+  DecorationBinding = 33,
+  DecorationDescriptorSet = 34,
+  DecorationOffset = 35,
+  DecorationXfbBuffer = 36,
+  DecorationXfbStride = 37,
+  DecorationFuncParamAttr = 38,
+  DecorationFPRoundingMode = 39,
+  DecorationFPFastMathMode = 40,
+  DecorationLinkageAttributes = 41,
+  DecorationNoContraction = 42,
+  DecorationInputAttachmentIndex = 43,
+  DecorationAlignment = 44,
+  DecorationMaxByteOffset = 45,
+  DecorationNoSignedWrap = 4469,
+  DecorationNoUnsignedWrap = 4470,
+  DecorationOverrideCoverageNV = 5248,
+  DecorationPassthroughNV = 5250,
+  DecorationViewportRelativeNV = 5252,
+  DecorationSecondaryViewportRelativeNV = 5256,
+  DecorationReferencedIndirectlyINTEL = 5602,
+  DecorationSideEffectsINTEL = 5608,
+  DecorationUserSemantic = 5635,
+  DecorationRegisterINTEL = 5825,
+  DecorationMemoryINTEL = 5826,
+  DecorationNumbanksINTEL = 5827,
+  DecorationBankwidthINTEL = 5828,
+  DecorationMaxPrivateCopiesINTEL = 5829,
+  DecorationSinglepumpINTEL = 5830,
+  DecorationDoublepumpINTEL = 5831,
+  DecorationMaxReplicatesINTEL = 5832,
+  DecorationSimpleDualPortINTEL = 5833,
+  DecorationMergeINTEL = 5834,
+  DecorationBankBitsINTEL = 5835,
+  DecorationIOPipeStorageINTEL = 5944,
+  DecorationMax = 0x7fffffff,
 };
 
 enum BuiltIn {
@@ -681,6 +682,7 @@ enum Capability {
   CapabilitySubgroupImageMediaBlockIOINTEL = 5579,
   CapabilityFunctionPointersINTEL = 5603,
   CapabilityIndirectReferencesINTEL = 5604,
+  CapabilityAsmINTEL = 5606,
   CapabilitySubgroupAvcMotionEstimationINTEL = 5696,
   CapabilitySubgroupAvcMotionEstimationIntraINTEL = 5697,
   CapabilitySubgroupAvcMotionEstimationChromaINTEL = 5698,
@@ -689,8 +691,8 @@ enum Capability {
   CapabilityFPGALoopControlsINTEL = 5888,
   CapabilityBlockingPipesINTEL = 5945,
   CapabilityFPGARegINTEL = 5948,
-  CapabilityKernelAttributesINTEL= 5892,
-  CapabilityFPGAKernelAttributesINTEL= 5897,
+  CapabilityKernelAttributesINTEL = 5892,
+  CapabilityFPGAKernelAttributesINTEL = 5897,
   CapabilityIOPipeINTEL = 5943,
   CapabilityMax = 0x7fffffff,
 };
@@ -1019,6 +1021,9 @@ enum Op {
   OpSubgroupImageMediaBlockWriteINTEL = 5581,
   OpFunctionPointerINTEL = 5600,
   OpFunctionPointerCallINTEL = 5601,
+  OpAsmTargetINTEL = 5609,
+  OpAsmINTEL = 5610,
+  OpAsmCallINTEL = 5611,
   OpVmeImageINTEL = 5699,
   OpTypeVmeImageINTEL = 5700,
   OpTypeAvcImePayloadINTEL = 5701,
diff --git a/llvm-spirv/test/DebugInfo/COFF/no-cus.ll b/llvm-spirv/test/DebugInfo/COFF/no-cus.ll
index c9e532f992f8b..3bb9b7b26fcfc 100644
--- a/llvm-spirv/test/DebugInfo/COFF/no-cus.ll
+++ b/llvm-spirv/test/DebugInfo/COFF/no-cus.ll
@@ -3,7 +3,7 @@
 ; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o %t.ll
 
 ; RUN: llc -mtriple=%triple < %t.ll -filetype=obj -o %t.o
-; RUN: llvm-objdump -section-headers %t.o | FileCheck %s
+; RUN: llvm-objdump --section-headers %t.o | FileCheck %s
 
 ; Don't emit debug info in this scenario and don't crash.
 
diff --git a/llvm-spirv/test/inline_asm_basic.cl b/llvm-spirv/test/inline_asm_basic.cl
new file mode 100644
index 0000000000000..745a24fe96ec6
--- /dev/null
+++ b/llvm-spirv/test/inline_asm_basic.cl
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -emit-llvm-bc %s -o %t.bc
+// RUN: llvm-spirv -spirv-ext=+SPV_INTEL_inline_assembly %t.bc -o %t.spv
+// RUN: llvm-spirv %t.spv -to-text -o %t.spt
+// RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+// RUN: llvm-spirv -r %t.spv -o %t.bc
+// RUN: llvm-dis < %t.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+// CHECK-SPIRV: {{[0-9]+}} Capability AsmINTEL
+// CHECK-SPIRV: {{[0-9]+}} Extension "SPV_INTEL_inline_assembly"
+// CHECK-SPIRV: {{[0-9]+}} AsmTargetINTEL
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL
+
+// CHECK-LLVM: call void asm sideeffect
+
+kernel void foo() {
+  __asm__ volatile ("");
+}
diff --git a/llvm-spirv/test/inline_asm_clobbers.cl b/llvm-spirv/test/inline_asm_clobbers.cl
new file mode 100644
index 0000000000000..a640430ec9f50
--- /dev/null
+++ b/llvm-spirv/test/inline_asm_clobbers.cl
@@ -0,0 +1,94 @@
+// RUN: %clang_cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -emit-llvm-bc %s -o %t.bc
+// RUN: llvm-spirv -spirv-ext=+SPV_INTEL_inline_assembly %t.bc -o %t.spv
+// RUN: llvm-spirv %t.spv -to-text -o %t.spt
+// RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+// RUN: llvm-spirv -r %t.spv -o %t.bc
+// RUN: llvm-dis < %t.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+// Excerpt from opencl-c-base.h
+typedef __SIZE_TYPE__ size_t;
+
+// Excerpt from opencl-c.h to speed up compilation.
+#define __ovld __attribute__((overloadable))
+#define __cnfn __attribute__((const))
+size_t __ovld __cnfn get_global_id(unsigned int dimindx);
+
+// CHECK-SPIRV: {{[0-9]+}} Capability AsmINTEL
+// CHECK-SPIRV: {{[0-9]+}} Extension "SPV_INTEL_inline_assembly"
+// CHECK-SPIRV: {{[0-9]+}} AsmTargetINTEL
+
+// XCHECK-LLVM: [[STRUCTYPE:%[a-z0-9]+]] = type { i32, i32 }
+
+// CHECK-LLVM-LABEL: define spir_kernel void @mem_clobber
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} """~{cc},~{memory}"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)**
+// CHECK-LLVM-NEXT: getelementptr inbounds i32, i32 addrspace(1)* [[VALUE]], i64 0
+// CHECK-LLVM-NEXT: store i32 1, i32 addrspace(1)*
+// CHECK-LLVM-NEXT: call void asm sideeffect "", "~{cc},~{memory}"()
+// CHECK-LLVM-NEXT: load i32 addrspace(1)*, i32 addrspace(1)**
+
+kernel void mem_clobber(global int *x) {
+  x[0] = 1;
+  __asm__ ("":::"cc","memory");
+  x[0] += 1;
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @out_clobber
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "earlyclobber_instruction_out $0""=&r"
+// CHECK-LLVM: barrier
+// CHECK-LLVM: store i32 %{{[a-z0-9]+}}, i32* [[VALUE:%[a-z0-9]+]], align 4
+// CHECK-LLVM-NEXT: [[STOREVAL:%[a-z0-9]+]] = call i32 asm "earlyclobber_instruction_out $0", "=&r"()
+// CHECK-LLVM: store i32 [[STOREVAL]], i32* [[VALUE]], align 4
+
+kernel void out_clobber(global int *x) {
+  int i = get_global_id(0);
+  __asm__ ("barrier");
+  int a = x[i];
+  __asm__ ("earlyclobber_instruction_out %0":"=&r"(a));
+  a += 1;
+  x[i] = a;
+}
+
+// TODO: This fails on debug build with assert "function type not legal for constraints"
+//       Probably I am not completely understand what happens
+//       Or bug in clang FE. To investigate later, change xchecks to checks and enable
+
+// XCHECK-LLVM-LABEL: define spir_kernel void @in_clobber
+// XCHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "earlyclobber_instruction_in $0""&r"
+// XCHECK-LLVM: barrier
+// XCHECK-LLVM: getelementptr
+// XCHECK-LLVM: store i32  %{{[a-z0-9]+}}, i32* [[LOADVAL:%[a-z0-9]+]], align 4
+// XCHECK-LLVM-NEXT: [[VALUE:%[a-z0-9]+]] = load i32, i32* [[LOADVAL]], align 4
+// XCHECK-LLVM-NEXT: call void asm sideeffect "earlyclobber_instruction_in $0", "&r"(i32 [[VALUE]])
+// XCHECK-LLVM: %{{[a-z0-9]+}} = load i32, i32* [[LOADVAL]], align 4
+
+#if 0
+kernel void in_clobber(global int *x) {
+  int i = get_global_id(0);
+  __asm__ ("barrier");
+  int a = x[i];
+  __asm__ ("earlyclobber_instruction_in %0"::"&r"(a));
+  a += 1;
+  x[i] = a;
+}
+#endif
+
+// XCHECK-LLVM-LABEL: define spir_kernel void @mixed_clobber
+// XCHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "mixedclobber_instruction $0 $1 $2""=&r,=&r,&r,1,~{cc},~{memory}"
+
+#if 0
+kernel void mixed_clobber(global int *x, global int *y, global int *z) {
+  int i = get_global_id(0);
+  int a = x[i];
+  int b = y[i];
+  int c = z[i];
+  __asm__ ("mixedclobber_instruction %0 %1 %2":"=&r"(a),"+&r"(b):"&r"(c):"cc","memory");
+  a += 1;
+  b += 1;
+  c += 1;
+  x[i] = c;
+  y[i] = a;
+  z[i] = b;
+}
+#endif
+
diff --git a/llvm-spirv/test/inline_asm_constraints.cl b/llvm-spirv/test/inline_asm_constraints.cl
new file mode 100644
index 0000000000000..98bf490642550
--- /dev/null
+++ b/llvm-spirv/test/inline_asm_constraints.cl
@@ -0,0 +1,100 @@
+// RUN: %clang_cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -emit-llvm-bc %s -o %t.bc
+// RUN: llvm-spirv -spirv-ext=+SPV_INTEL_inline_assembly %t.bc -o %t.spv
+// RUN: llvm-spirv %t.spv -to-text -o %t.spt
+// RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+// RUN: llvm-spirv -r %t.spv -o %t.bc
+// RUN: llvm-dis < %t.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+// Excerpt from opencl-c-base.h
+typedef __SIZE_TYPE__ size_t;
+typedef unsigned char uchar;
+typedef unsigned short ushort;
+typedef unsigned int uint;
+typedef unsigned long ulong;
+
+// Excerpt from opencl-c.h to speed up compilation.
+#define __ovld __attribute__((overloadable))
+#define __cnfn __attribute__((const))
+size_t __ovld __cnfn get_global_id(unsigned int dimindx);
+
+// CHECK-SPIRV: {{[0-9]+}} Capability AsmINTEL
+// CHECK-SPIRV: {{[0-9]+}} Extension "SPV_INTEL_inline_assembly"
+// CHECK-SPIRV-COUNT-1: {{[0-9]+}} AsmTargetINTEL
+
+// CHECK-LLVM: [[STRUCTYPE:%[a-z]+]] = type { i32, i8, float }
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_int
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "intcommand $0 $1""=r,r"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = call i32 asm sideeffect "intcommand $0 $1", "=r,r"(i32 %{{[0-9]+}})
+// CHECK-LLVM-NEXT: store i32 [[VALUE]], i32 addrspace(1)*
+
+kernel void test_int(global int *in, global int *out) {
+  int i = get_global_id(0);
+  __asm__ volatile ("intcommand %0 %1" : "=r"(out[i]) : "r"(in[i]));
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_float
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "floatcommand $0 $1""=r,r"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = call float asm sideeffect "floatcommand $0 $1", "=r,r"(float %{{[0-9]+}})
+// CHECK-LLVM-NEXT: store float [[VALUE]], float addrspace(1)*
+
+kernel void test_float(global float *in, global float *out) {
+  int i = get_global_id(0);
+  __asm__ volatile ("floatcommand %0 %1" : "=r"(out[i]) : "r"(in[i]));
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_mixed_integral
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "mixed_integral_command $0 $3 $1 $2""=r,r,r,r"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = call i64 asm sideeffect "mixed_integral_command $0 $3 $1 $2", "=r,r,r,r"(i16 %{{[0-9]+}}, i32 %{{[0-9]+}}, i8 %{{[0-9]+}})
+// CHECK-LLVM-NEXT: store i64 [[VALUE]], i64 addrspace(1)*
+
+kernel void test_mixed_integral(global uchar *A, global ushort *B, global uint *C, global ulong *D) {
+  int wiId = get_global_id(0);
+  __asm__ volatile ("mixed_integral_command %0 %3 %1 %2"
+          : "=r"(D[wiId]) : "r"(B[wiId]), "r"(C[wiId]), "r"(A[wiId]));
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_mixed_floating
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "mixed_floating_command $0 $1 $2""=r,r,r"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = call half asm sideeffect "mixed_floating_command $0 $1 $2", "=r,r,r"(double %{{[0-9]+}}, float %{{[0-9]+}})
+// CHECK-LLVM-NEXT: store half [[VALUE]], half addrspace(1)*
+
+kernel void test_mixed_floating(global float *A, global half *B, global double *C) {
+  int wiId = get_global_id(0);
+  __asm__ volatile ("mixed_floating_command %0 %1 %2"
+          : "=r"(B[wiId]) : "r"(C[wiId]), "r"(A[wiId]));
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_mixed_all
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "mixed_all_command $0 $3 $1 $2""=r,r,r,r"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = call i8 asm sideeffect "mixed_all_command $0 $3 $1 $2", "=r,r,r,r"(float %{{[0-9]+}}, i32 %{{[0-9]+}}, i8 %{{[0-9]+}})
+// CHECK-LLVM-NEXT: store i8 [[VALUE]], i8 addrspace(1)*
+
+kernel void test_mixed_all(global uchar *A, global float *B, global uint *C, global bool *D) {
+  int wiId = get_global_id(0);
+  __asm__ volatile ("mixed_all_command %0 %3 %1 %2"
+          : "=r"(D[wiId]) : "r"(B[wiId]), "r"(C[wiId]), "r"(A[wiId]));
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_multiple
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "multiple_command $0 $0 $1 $1 $2 $2""=r,=r,=r,0,1,2"
+// CHECK-LLVM: [[VALUE:%[0-9]+]] = call [[STRUCTYPE]] asm sideeffect "multiple_command $0 $0 $1 $1 $2 $2", "=r,=r,=r,0,1,2"(i32 %{{[0-9]+}}, i8 %{{[0-9]+}}, float %{{[0-9]+}})
+// CHECK-LLVM-NEXT: extractvalue [[STRUCTYPE]] [[VALUE]], 0
+// CHECK-LLVM-NEXT: extractvalue [[STRUCTYPE]] [[VALUE]], 1
+// CHECK-LLVM-NEXT: extractvalue [[STRUCTYPE]] [[VALUE]], 2
+
+kernel void test_multiple(global uchar *A, global float *B, global uint *C) {
+  int wiId = get_global_id(0);
+  __asm__ volatile ("multiple_command %0 %0 %1 %1 %2 %2"
+          : "+r"(C[wiId]), "+r"(A[wiId]), "+r"(B[wiId]));
+}
+
+// CHECK-LLVM-LABEL: define spir_kernel void @test_constants
+// CHECK-SPIRV: {{[0-9]+}} AsmINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} "constcommand $0 $1""i,i"
+// CHECK-LLVM: call void asm sideeffect "constcommand $0 $1", "i,i"(i32 1, double 2.000000e+00)
+
+kernel void test_constants() {
+  int i = get_global_id(0);
+  __asm__ volatile ("constcommand %0 %1" : : "i"(1), "i"(2.0));
+}
+
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 23f36d5039a7c..3bb037b803dea 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -410,6 +410,17 @@ endif()
 
 option(LLVM_ENABLE_EXPENSIVE_CHECKS "Enable expensive checks" OFF)
 
+# While adding scalable vector support to LLVM, we temporarily want to
+# allow an implicit conversion of TypeSize to uint64_t. This CMake flag
+# enables a more strict conversion where it asserts that the type is not
+# a scalable vector type.
+#
+# Enabling this flag makes it easier to find cases where the compiler makes
+# assumptions on the size being 'fixed size', when building tests for
+# SVE/SVE2 or other scalable vector architectures.
+option(LLVM_ENABLE_STRICT_IMPLICIT_CONVERSION_TYPESIZE
+       "Enable assertions that type is not scalable in implicit conversion from TypeSize to uint64_t" OFF)
+
 set(LLVM_ABI_BREAKING_CHECKS "WITH_ASSERTS" CACHE STRING
   "Enable abi-breaking checks.  Can be WITH_ASSERTS, FORCE_ON or FORCE_OFF.")
 
diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake
index df231eb3308ce..70ad34a41bde8 100644
--- a/llvm/cmake/modules/HandleLLVMOptions.cmake
+++ b/llvm/cmake/modules/HandleLLVMOptions.cmake
@@ -95,6 +95,10 @@ if(LLVM_ENABLE_EXPENSIVE_CHECKS)
   endif()
 endif()
 
+if (LLVM_ENABLE_STRICT_IMPLICIT_CONVERSION_TYPESIZE)
+  add_definitions(-DSTRICT_IMPLICIT_CONVERSION_TYPESIZE)
+endif()
+
 string(TOUPPER "${LLVM_ABI_BREAKING_CHECKS}" uppercase_LLVM_ABI_BREAKING_CHECKS)
 
 if( uppercase_LLVM_ABI_BREAKING_CHECKS STREQUAL "WITH_ASSERTS" )
diff --git a/llvm/docs/CompileCudaWithLLVM.rst b/llvm/docs/CompileCudaWithLLVM.rst
index b4479771f803a..d85cac77982de 100644
--- a/llvm/docs/CompileCudaWithLLVM.rst
+++ b/llvm/docs/CompileCudaWithLLVM.rst
@@ -22,21 +22,22 @@ Compiling CUDA Code
 Prerequisites
 -------------
 
-CUDA is supported since llvm 3.9. Current release of clang (7.0.0) supports CUDA
-7.0 through 9.2. If you need support for CUDA 10, you will need to use clang
-built from r342924 or newer.
+CUDA is supported since llvm 3.9. Clang currently supports CUDA 7.0 through
+10.1. If clang detects a newer CUDA version, it will issue a warning and will
+attempt to use detected CUDA SDK it as if it were CUDA-10.1.
 
-Before you build CUDA code, you'll need to have installed the appropriate driver
-for your nvidia GPU and the CUDA SDK.  See `NVIDIA's CUDA installation guide
+Before you build CUDA code, you'll need to have installed the CUDA SDK.  See
+`NVIDIA's CUDA installation guide
 <https://docs.nvidia.com/cuda/cuda-installation-guide-linux/index.html>`_ for
-details.  Note that clang `does not support
+details.  Note that clang `maynot support
 <https://llvm.org/bugs/show_bug.cgi?id=26966>`_ the CUDA toolkit as installed by
-many Linux package managers; you probably need to install CUDA in a single
-directory from NVIDIA's package.
+some Linux package managers. Clang does attempt to deal with specific details of
+CUDA installation on a handful of common Linux distributions, but in general the
+most reliable way to make it work is to install CUDA in a single directory from
+NVIDIA's `.run` package and specify its location via `--cuda-path=...` argument.
 
 CUDA compilation is supported on Linux. Compilation on MacOS and Windows may or
-may not work and currently have no maintainers. Compilation with CUDA-9.x is
-`currently broken on Windows <https://bugs.llvm.org/show_bug.cgi?id=38811>`_.
+may not work and currently have no maintainers.
 
 Invoking clang
 --------------
diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst
index 10396afd30722..a3014064b80d5 100644
--- a/llvm/docs/GettingStarted.rst
+++ b/llvm/docs/GettingStarted.rst
@@ -404,10 +404,7 @@ The files are as follows, with *x.y* marking the version number:
 Checkout LLVM from Git
 ----------------------
 
-You can also checkout the source code for LLVM from Git. While the LLVM
-project's official source-code repository is Subversion, we are in the process
-of migrating to git. We currently recommend that all developers use Git for
-day-to-day development.
+You can also checkout the source code for LLVM from Git.
 
 .. note::
 
diff --git a/llvm/docs/LoopTerminology.rst b/llvm/docs/LoopTerminology.rst
index 207195ef79e2c..ef0593419a461 100644
--- a/llvm/docs/LoopTerminology.rst
+++ b/llvm/docs/LoopTerminology.rst
@@ -170,4 +170,226 @@ TBD
 "More Canonical" Loops
 ======================
 
-TBD
+.. _loop-terminology-loop-rotate:
+
+Rotated Loops
+-------------
+
+Loops are rotated by the LoopRotate (:ref:`loop-rotate <passes-loop-rotate>`)
+pass, which converts loops into do/while style loops and is
+implemented in
+`LoopRotation.h <http://llvm.org/doxygen/LoopRotation_8h_source.html>`_.  Example:
+
+.. code-block:: C
+
+  void test(int n) {
+    for (int i = 0; i < n; i += 1)
+      // Loop body
+  }
+
+is transformed to:
+
+.. code-block:: C
+
+  void test(int n) {
+    int i = 0;
+    do {
+      // Loop body
+      i += 1;
+    } while (i < n);
+  }
+
+**Warning**: This transformation is valid only if the compiler
+can prove that the loop body will be executed at least once. Otherwise,
+it has to insert a guard which will test it at runtime. In the example
+above, that would be:
+
+.. code-block:: C
+
+  void test(int n) {
+    int i = 0;
+    if (n > 0) {
+      do {
+        // Loop body
+        i += 1;
+      } while (i < n);
+    }
+  }
+
+It's important to understand the effect of loop rotation
+at the LLVM IR level. We follow with the previous examples
+in LLVM IR while also providing a graphical representation
+of the control-flow graphs (CFG). You can get the same graphical
+results by utilizing the :ref:`view-cfg <passes-view-cfg>` pass.
+
+The initial **for** loop could be translated to:
+
+.. code-block:: none
+
+  define void @test(i32 %n) {
+  entry:
+    br label %for.header
+
+  for.header:
+    %i = phi i32 [ 0, %entry ], [ %i.next, %latch ]
+    %cond = icmp slt i32 %i, %n
+    br i1 %cond, label %body, label %exit
+
+  body:
+    ; Loop body
+    br label %latch
+
+  latch:
+    %i.next = add nsw i32 %i, 1
+    br label %for.header
+
+  exit:
+    ret void
+  }
+
+.. image:: ./loop-terminology-initial-loop.png
+  :width: 400 px
+
+Before we explain how LoopRotate will actually
+transform this loop, here's how we could convert
+it (by hand) to a do-while style loop.
+
+.. code-block:: none
+
+  define void @test(i32 %n) {
+  entry:
+    br label %body
+
+  body:
+    %i = phi i32 [ 0, %entry ], [ %i.next, %latch ]
+    ; Loop body
+    br label %latch
+
+  latch:
+    %i.next = add nsw i32 %i, 1
+    %cond = icmp slt i32 %i.next, %n
+    br i1 %cond, label %body, label %exit
+
+  exit:
+    ret void
+  }
+
+.. image:: ./loop-terminology-rotated-loop.png
+  :width: 400 px
+
+Note two things:
+
+* The condition check was moved to the "bottom" of the loop, i.e.
+  the latch. This is something that LoopRotate does by copying the header
+  of the loop to the latch.
+* The compiler in this case can't deduce that the loop will
+  definitely execute at least once so the above transformation
+  is not valid. As mentioned above, a guard has to be inserted,
+  which is something that LoopRotate will do.
+
+This is how LoopRotate transforms this loop:
+
+.. code-block:: none
+
+  define void @test(i32 %n) {
+  entry:
+    %guard_cond = icmp slt i32 0, %n
+    br i1 %guard_cond, label %loop.preheader, label %exit
+
+  loop.preheader:
+    br label %body
+
+  body:
+    %i2 = phi i32 [ 0, %loop.preheader ], [ %i.next, %latch ]
+    br label %latch
+
+  latch:
+    %i.next = add nsw i32 %i2, 1
+    %cond = icmp slt i32 %i.next, %n
+    br i1 %cond, label %body, label %loop.exit
+
+  loop.exit:
+    br label %exit
+
+  exit:
+    ret void
+  }
+
+.. image:: ./loop-terminology-guarded-loop.png
+  :width: 500 px
+
+The result is a little bit more complicated than we may expect
+because LoopRotate ensures that the loop is in
+:ref:`Loop Simplify Form <loop-terminology-loop-simplify>`
+after rotation.
+In this case, it inserted the %loop.preheader basic block so
+that the loop has a preheader and it introduced the %loop.exit
+basic block so that the loop has dedicated exits
+(otherwise, %exit would be jumped from both %latch and %entry,
+but %entry is not contained in the loop).
+Note that a loop has to be in Loop Simplify Form beforehand
+too for LoopRotate to be applied successfully.
+
+The main advantage of this form is that it allows hoisting
+invariant instructions, especially loads, into the preheader.
+That could be done in non-rotated loops as well but with
+some disadvantages.  Let's illustrate them with an example:
+
+.. code-block:: C
+
+  for (int i = 0; i < n; ++i) {
+    auto v = *p;
+    use(v);
+  }
+
+We assume that loading from p is invariant and use(v) is some
+statement that uses v.
+If we wanted to execute the load only once we could move it
+"out" of the loop body, resulting in this:
+
+.. code-block:: C
+
+  auto v = *p;
+  for (int i = 0; i < n; ++i) {
+    use(v);
+  }
+
+However, now, in the case that n <= 0, in the initial form,
+the loop body would never execute, and so, the load would
+never execute.  This is a problem mainly for semantic reasons.
+Consider the case in which n <= 0 and loading from p is invalid.
+In the initial program there would be no error.  However, with this
+transformation we would introduce one, effectively breaking
+the initial semantics.
+
+To avoid both of these problems, we can insert a guard:
+
+.. code-block:: C
+
+  if (n > 0) {  // loop guard
+    auto v = *p;
+    for (int i = 0; i < n; ++i) {
+      use(v);
+    }
+  }
+
+This is certainly better but it could be improved slightly. Notice
+that the check for whether n is bigger than 0 is executed twice (and
+n does not change in between).  Once when we check the guard condition
+and once in the first execution of the loop.  To avoid that, we could
+do an unconditional first execution and insert the loop condition
+in the end. This effectively means transforming the loop into a do-while loop:
+
+.. code-block:: C
+
+  if (0 < n) {
+    auto v = *p;
+    do {
+      use(v);
+      ++i;
+    } while (i < n);
+  }
+
+Note that LoopRotate does not generally do such
+hoisting.  Rather, it is an enabling transformation for other
+passes like Loop-Invariant Code Motion (:ref:`-licm <passes-licm>`).
diff --git a/llvm/docs/Passes.rst b/llvm/docs/Passes.rst
index a13f1e6694cad..39451a915ee4a 100644
--- a/llvm/docs/Passes.rst
+++ b/llvm/docs/Passes.rst
@@ -798,10 +798,14 @@ accomplished by creating a new value to hold the initial value of the array
 access for the first iteration, and then creating a new GEP instruction in the
 loop to increment the value by the appropriate amount.
 
+.. _passes-loop-rotate:
+
 ``-loop-rotate``: Rotate Loops
 ------------------------------
 
-A simple loop rotation transformation.
+A simple loop rotation transformation.  A summary of it can be found in
+:ref:`Loop Terminology for Rotated Loops <loop-terminology-loop-rotate>`.
+
 
 .. _passes-loop-simplify:
 
@@ -1194,6 +1198,8 @@ performing optimizing transformations.
 Note that this does not provide full security verification (like Java), but
 instead just tries to ensure that code is well-formed.
 
+.. _passes-view-cfg:
+
 ``-view-cfg``: View CFG of function
 -----------------------------------
 
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b24659c16f9e..bbfcc6076c018 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -100,7 +100,9 @@ Changes to the AMDGPU Target
 Changes to the AVR Target
 -----------------------------
 
-During this release ...
+* Moved from an experimental backend to an official backend. AVR support is now
+  included by default in all LLVM builds and releases and is available under
+  the "avr-unknown-unknown" target triple.
 
 Changes to the WebAssembly Target
 ---------------------------------
diff --git a/llvm/docs/loop-terminology-guarded-loop.png b/llvm/docs/loop-terminology-guarded-loop.png
new file mode 100644
index 0000000000000..d235b1421189a
Binary files /dev/null and b/llvm/docs/loop-terminology-guarded-loop.png differ
diff --git a/llvm/docs/loop-terminology-initial-loop.png b/llvm/docs/loop-terminology-initial-loop.png
new file mode 100644
index 0000000000000..ad8fc109b6519
Binary files /dev/null and b/llvm/docs/loop-terminology-initial-loop.png differ
diff --git a/llvm/docs/loop-terminology-rotated-loop.png b/llvm/docs/loop-terminology-rotated-loop.png
new file mode 100644
index 0000000000000..b048ff702684a
Binary files /dev/null and b/llvm/docs/loop-terminology-rotated-loop.png differ
diff --git a/llvm/examples/OrcV2Examples/LLJITWithLazyReexports/LLJITWithLazyReexports.cpp b/llvm/examples/OrcV2Examples/LLJITWithLazyReexports/LLJITWithLazyReexports.cpp
index 99c3aead224e4..b75d5610f9e64 100644
--- a/llvm/examples/OrcV2Examples/LLJITWithLazyReexports/LLJITWithLazyReexports.cpp
+++ b/llvm/examples/OrcV2Examples/LLJITWithLazyReexports/LLJITWithLazyReexports.cpp
@@ -107,7 +107,7 @@ int main(int argc, char *argv[]) {
       [](ThreadSafeModule TSM,
          const MaterializationResponsibility &R) -> Expected<ThreadSafeModule> {
         TSM.withModuleDo([](Module &M) { dbgs() << "---Compiling---\n" << M; });
-        return TSM;
+        return std::move(TSM); // Not a redundant move: fix build on gcc-7.5
       });
 
   // (3) Create stubs and call-through managers:
diff --git a/llvm/examples/ThinLtoJIT/ThinLtoJIT.cpp b/llvm/examples/ThinLtoJIT/ThinLtoJIT.cpp
index 7442fbd3c0a53..6bd8f6144db16 100644
--- a/llvm/examples/ThinLtoJIT/ThinLtoJIT.cpp
+++ b/llvm/examples/ThinLtoJIT/ThinLtoJIT.cpp
@@ -191,7 +191,7 @@ Expected<ThreadSafeModule> ThinLtoJIT::setupMainModule(StringRef MainFunction) {
   }
 
   if (auto TSM = GlobalIndex->parseModuleFromFile(*M))
-    return TSM;
+    return std::move(TSM); // Not a redundant move: fix build on gcc-7.5
 
   return createStringError(inconvertibleErrorCode(),
                            "Failed to parse main module");
diff --git a/llvm/examples/ThinLtoJIT/ThinLtoModuleIndex.cpp b/llvm/examples/ThinLtoJIT/ThinLtoModuleIndex.cpp
index 596c9356826d6..42ee43f1091ba 100644
--- a/llvm/examples/ThinLtoJIT/ThinLtoModuleIndex.cpp
+++ b/llvm/examples/ThinLtoJIT/ThinLtoModuleIndex.cpp
@@ -205,7 +205,7 @@ void ThinLtoModuleIndex::updatePathRank(StringRef Path, unsigned Distance) {
   Entry.Count += 1;
   Entry.MinDist = std::min(Entry.MinDist, Distance);
   assert(Entry.MinDist > 0 && "We want it as a divisor");
-};
+}
 
 // TODO: The size of a ThreadPool's task queue is not accessible. It would
 // be great to know in order to estimate how many modules we schedule. The
diff --git a/llvm/include/llvm-c/DebugInfo.h b/llvm/include/llvm-c/DebugInfo.h
index 61702253f69b8..cdf5f5a0cca86 100644
--- a/llvm/include/llvm-c/DebugInfo.h
+++ b/llvm/include/llvm-c/DebugInfo.h
@@ -296,7 +296,7 @@ LLVMDIBuilderCreateModule(LLVMDIBuilderRef Builder, LLVMMetadataRef ParentScope,
                           const char *Name, size_t NameLen,
                           const char *ConfigMacros, size_t ConfigMacrosLen,
                           const char *IncludePath, size_t IncludePathLen,
-                          const char *APINotestFile, size_t APINotestFileLen);
+                          const char *APINotesFile, size_t APINotesFileLen);
 
 /**
  * Creates a new descriptor for a namespace with the specified parent scope.
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h
index dd576e039151d..446041119c807 100644
--- a/llvm/include/llvm/Analysis/MemoryLocation.h
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h
@@ -89,6 +89,11 @@ class LocationSize {
       : Value(Raw > MaxValue ? Unknown : Raw) {}
 
   static LocationSize precise(uint64_t Value) { return LocationSize(Value); }
+  static LocationSize precise(TypeSize Value) {
+    if (Value.isScalable())
+      return unknown();
+    return precise(Value.getFixedSize());
+  }
 
   static LocationSize upperBound(uint64_t Value) {
     // You can't go lower than 0, so give a precise result.
@@ -98,6 +103,11 @@ class LocationSize {
       return unknown();
     return LocationSize(Value | ImpreciseBit, Direct);
   }
+  static LocationSize upperBound(TypeSize Value) {
+    if (Value.isScalable())
+      return unknown();
+    return upperBound(Value.getFixedSize());
+  }
 
   constexpr static LocationSize unknown() {
     return LocationSize(Unknown, Direct);
diff --git a/llvm/include/llvm/Analysis/ScalarEvolutionExpander.h b/llvm/include/llvm/Analysis/ScalarEvolutionExpander.h
index 7a94f6320a569..0c88f9f79e766 100644
--- a/llvm/include/llvm/Analysis/ScalarEvolutionExpander.h
+++ b/llvm/include/llvm/Analysis/ScalarEvolutionExpander.h
@@ -16,6 +16,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
 #include "llvm/Analysis/ScalarEvolutionNormalization.h"
 #include "llvm/Analysis/TargetFolder.h"
@@ -186,10 +187,18 @@ namespace llvm {
       assert(At && "This function requires At instruction to be provided.");
       if (!TTI)      // In assert-less builds, avoid crashing
         return true; // by always claiming to be high-cost.
+      SmallVector<const SCEV *, 8> Worklist;
       SmallPtrSet<const SCEV *, 8> Processed;
       int BudgetRemaining = Budget * TargetTransformInfo::TCC_Basic;
-      return isHighCostExpansionHelper(Expr, L, *At, BudgetRemaining, *TTI,
-                                       Processed);
+      Worklist.emplace_back(Expr);
+      while (!Worklist.empty()) {
+        const SCEV *S = Worklist.pop_back_val();
+        if (isHighCostExpansionHelper(S, L, *At, BudgetRemaining, *TTI,
+                                      Processed, Worklist))
+          return true;
+      }
+      assert(BudgetRemaining >= 0 && "Should have returned from inner loop.");
+      return false;
     }
 
     /// This method returns the canonical induction variable of the specified
@@ -334,7 +343,8 @@ namespace llvm {
     bool isHighCostExpansionHelper(const SCEV *S, Loop *L,
                                    const Instruction &At, int &BudgetRemaining,
                                    const TargetTransformInfo &TTI,
-                                   SmallPtrSetImpl<const SCEV *> &Processed);
+                                   SmallPtrSetImpl<const SCEV *> &Processed,
+                                   SmallVectorImpl<const SCEV *> &Worklist);
 
     /// Insert the specified binary operator, doing a small amount of work to
     /// avoid inserting an obviously redundant operation, and hoisting to an
diff --git a/llvm/include/llvm/Analysis/StackSafetyAnalysis.h b/llvm/include/llvm/Analysis/StackSafetyAnalysis.h
index f9d8b08ac1425..c797d498b5dd8 100644
--- a/llvm/include/llvm/Analysis/StackSafetyAnalysis.h
+++ b/llvm/include/llvm/Analysis/StackSafetyAnalysis.h
@@ -33,6 +33,8 @@ class StackSafetyInfo {
   StackSafetyInfo &operator=(StackSafetyInfo &&);
   ~StackSafetyInfo();
 
+  FunctionInfo *getInfo() const { return Info.get(); }
+
   // TODO: Add useful for client methods.
   void print(raw_ostream &O) const;
 };
@@ -96,17 +98,26 @@ class StackSafetyGlobalPrinterPass
   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
 };
 
+class StackSafetyGlobalAnnotatorPass
+    : public PassInfoMixin<StackSafetyGlobalAnnotatorPass> {
+
+public:
+  explicit StackSafetyGlobalAnnotatorPass() {}
+  PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
+};
+
 /// This pass performs the global (interprocedural) stack safety analysis
 /// (legacy pass manager).
 class StackSafetyGlobalInfoWrapperPass : public ModulePass {
-  StackSafetyGlobalInfo SSI;
+  StackSafetyGlobalInfo SSGI;
+  bool SetMetadata;
 
 public:
   static char ID;
 
-  StackSafetyGlobalInfoWrapperPass();
+  StackSafetyGlobalInfoWrapperPass(bool SetMetadata = false);
 
-  const StackSafetyGlobalInfo &getResult() const { return SSI; }
+  const StackSafetyGlobalInfo &getResult() const { return SSGI; }
 
   void print(raw_ostream &O, const Module *M) const override;
   void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -114,6 +125,8 @@ class StackSafetyGlobalInfoWrapperPass : public ModulePass {
   bool runOnModule(Module &M) override;
 };
 
+ModulePass *createStackSafetyGlobalInfoWrapperPass(bool SetMetadata);
+
 } // end namespace llvm
 
 #endif // LLVM_ANALYSIS_STACKSAFETYANALYSIS_H
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 1387b90307f7f..ca6892b14ef3b 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1069,6 +1069,7 @@ class TargetTransformInfo {
 
   /// \returns The type to use in a loop expansion of a memcpy call.
   Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
+                                  unsigned SrcAddrSpace, unsigned DestAddrSpace,
                                   unsigned SrcAlign, unsigned DestAlign) const;
 
   /// \param[out] OpsOut The operand types to copy RemainingBytes of memory.
@@ -1080,6 +1081,8 @@ class TargetTransformInfo {
   void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
                                          LLVMContext &Context,
                                          unsigned RemainingBytes,
+                                         unsigned SrcAddrSpace,
+                                         unsigned DestAddrSpace,
                                          unsigned SrcAlign,
                                          unsigned DestAlign) const;
 
@@ -1382,11 +1385,15 @@ class TargetTransformInfo::Concept {
   virtual Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
                                                    Type *ExpectedType) = 0;
   virtual Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
+                                          unsigned SrcAddrSpace,
+                                          unsigned DestAddrSpace,
                                           unsigned SrcAlign,
                                           unsigned DestAlign) const = 0;
   virtual void getMemcpyLoopResidualLoweringType(
       SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
-      unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const = 0;
+      unsigned RemainingBytes,
+      unsigned SrcAddrSpace, unsigned DestAddrSpace,
+      unsigned SrcAlign, unsigned DestAlign) const = 0;
   virtual bool areInlineCompatible(const Function *Caller,
                                    const Function *Callee) const = 0;
   virtual bool
@@ -1830,16 +1837,22 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
     return Impl.getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
   }
   Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
+                                  unsigned SrcAddrSpace, unsigned DestAddrSpace,
                                   unsigned SrcAlign,
                                   unsigned DestAlign) const override {
-    return Impl.getMemcpyLoopLoweringType(Context, Length, SrcAlign, DestAlign);
+    return Impl.getMemcpyLoopLoweringType(Context, Length,
+                                          SrcAddrSpace, DestAddrSpace,
+                                          SrcAlign, DestAlign);
   }
   void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
                                          LLVMContext &Context,
                                          unsigned RemainingBytes,
+                                         unsigned SrcAddrSpace,
+                                         unsigned DestAddrSpace,
                                          unsigned SrcAlign,
                                          unsigned DestAlign) const override {
     Impl.getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
+                                           SrcAddrSpace, DestAddrSpace,
                                            SrcAlign, DestAlign);
   }
   bool areInlineCompatible(const Function *Caller,
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 60065731784a3..2acb88a6a83d1 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -543,6 +543,7 @@ class TargetTransformInfoImplBase {
   }
 
   Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
+                                  unsigned SrcAddrSpace, unsigned DestAddrSpace,
                                   unsigned SrcAlign, unsigned DestAlign) const {
     return Type::getInt8Ty(Context);
   }
@@ -550,6 +551,8 @@ class TargetTransformInfoImplBase {
   void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
                                          LLVMContext &Context,
                                          unsigned RemainingBytes,
+                                         unsigned SrcAddrSpace,
+                                         unsigned DestAddrSpace,
                                          unsigned SrcAlign,
                                          unsigned DestAlign) const {
     for (unsigned i = 0; i != RemainingBytes; ++i)
@@ -882,33 +885,32 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
       if (A->isStaticAlloca())
         return TTI::TCC_Free;
 
-    if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
-      return static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
-                                                GEP->getPointerOperand(),
-                                                Operands.drop_front());
-    }
+    auto *TargetTTI = static_cast<T *>(this);
+
+    if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U))
+      return TargetTTI->getGEPCost(GEP->getSourceElementType(),
+                                   GEP->getPointerOperand(),
+                                   Operands.drop_front());
 
     if (auto CS = ImmutableCallSite(U)) {
       const Function *F = CS.getCalledFunction();
       if (!F) {
         // Just use the called value type.
         Type *FTy = CS.getCalledValue()->getType()->getPointerElementType();
-        return static_cast<T *>(this)
-            ->getCallCost(cast<FunctionType>(FTy), CS.arg_size(), U);
+        return TargetTTI->getCallCost(cast<FunctionType>(FTy),
+                                      CS.arg_size(), U);
       }
 
       SmallVector<const Value *, 8> Arguments(CS.arg_begin(), CS.arg_end());
-      return static_cast<T *>(this)->getCallCost(F, Arguments, U);
+      return TargetTTI->getCallCost(F, Arguments, U);
     }
 
     if (isa<SExtInst>(U) || isa<ZExtInst>(U) || isa<FPExtInst>(U))
       // The old behaviour of generally treating extensions of icmp to be free
       // has been removed. A target that needs it should override getUserCost().
-      return static_cast<T *>(this)->getExtCost(cast<Instruction>(U),
-                                                Operands.back());
+      return TargetTTI->getExtCost(cast<Instruction>(U), Operands.back());
 
-    return static_cast<T *>(this)->getOperationCost(
-        Operator::getOpcode(U), U->getType(),
+    return TargetTTI->getOperationCost(Operator::getOpcode(U), U->getType(),
         U->getNumOperands() == 1 ? U->getOperand(0)->getType() : nullptr);
   }
 
diff --git a/llvm/include/llvm/Analysis/ValueLattice.h b/llvm/include/llvm/Analysis/ValueLattice.h
index a467a715fca82..2810ba5a3fc3a 100644
--- a/llvm/include/llvm/Analysis/ValueLattice.h
+++ b/llvm/include/llvm/Analysis/ValueLattice.h
@@ -29,27 +29,49 @@ class ValueLatticeElement {
     /// producing instruction is dead.  Caution: We use this as the starting
     /// state in our local meet rules.  In this usage, it's taken to mean
     /// "nothing known yet".
+    /// Transition to any other state allowed.
     unknown,
 
     /// This Value is an UndefValue constant or produces undef. Undefined values
     /// can be merged with constants (or single element constant ranges),
     /// assuming all uses of the result will be replaced.
+    /// Transition allowed to the following states:
+    ///  constant
+    ///  singlecrfromundef
+    ///  overdefined
     undef,
 
-    /// This Value has a specific constant value.  (For constant integers,
-    /// constantrange is used instead.  Integer typed constantexprs can appear
-    /// as constant.)
+    /// This Value has a specific constant value.  The constant cannot be undef.
+    /// (For constant integers, constantrange is used instead. Integer typed
+    /// constantexprs can appear as constant.) Note that the constant state
+    /// can be reached by merging undef & constant states.
+    /// Transition allowed to the following states:
+    ///  overdefined
     constant,
 
-    /// This Value is known to not have the specified value.  (For constant
+    /// This Value is known to not have the specified value. (For constant
     /// integers, constantrange is used instead.  As above, integer typed
     /// constantexprs can appear here.)
+    /// Transition allowed to the following states:
+    ///  overdefined
     notconstant,
 
     /// The Value falls within this range. (Used only for integer typed values.)
+    /// Transition allowed to the following states:
+    ///  constantrange (new range must be a superset of the existing range)
+    ///  singlecrfromundef (range must stay a single element range)
+    ///  overdefined
     constantrange,
 
+    /// This Value contains a single element constant range that was merged with
+    /// an Undef value. Merging it with other constant ranges results in
+    /// overdefined, unless they match the single element constant range.
+    /// Transition allowed to the following states:
+    ///  overdefined
+    singlecrfromundef,
+
     /// We can not precisely model the dynamic values this value might take.
+    /// No transitions are allowed after reaching overdefined.
     overdefined
   };
 
@@ -75,6 +97,7 @@ class ValueLatticeElement {
     case unknown:
     case undef:
     case constant:
+    case singlecrfromundef:
     case notconstant:
       break;
     case constantrange:
@@ -105,6 +128,7 @@ class ValueLatticeElement {
 
     switch (Other.Tag) {
     case constantrange:
+    case singlecrfromundef:
       if (!isConstantRange())
         new (&Range) ConstantRange(Other.Range);
       else
@@ -155,8 +179,11 @@ class ValueLatticeElement {
   bool isUnknown() const { return Tag == unknown; }
   bool isUnknownOrUndef() const { return Tag == unknown || Tag == undef; }
   bool isConstant() const { return Tag == constant; }
+  bool isSingleCRFromUndef() const { return Tag == singlecrfromundef; }
   bool isNotConstant() const { return Tag == notconstant; }
-  bool isConstantRange() const { return Tag == constantrange; }
+  bool isConstantRange() const {
+    return Tag == constantrange || Tag == singlecrfromundef;
+  }
   bool isOverdefined() const { return Tag == overdefined; }
 
   Constant *getConstant() const {
@@ -251,6 +278,8 @@ class ValueLatticeElement {
       if (getConstantRange() == NewR)
         return false;
 
+      assert(!isSingleCRFromUndef());
+
       if (NewR.isEmptySet())
         return markOverdefined();
 
@@ -260,11 +289,11 @@ class ValueLatticeElement {
       return true;
     }
 
-    assert(isUnknown() || isUndef());
+    assert(isUnknown() || (isUndef() && NewR.isSingleElement()));
     if (NewR.isEmptySet())
       return markOverdefined();
 
-    Tag = constantrange;
+    Tag = isUnknown() ? constantrange : singlecrfromundef;
     new (&Range) ConstantRange(std::move(NewR));
     return true;
   }
@@ -322,7 +351,17 @@ class ValueLatticeElement {
       markOverdefined();
       return true;
     }
+
     ConstantRange NewR = getConstantRange().unionWith(RHS.getConstantRange());
+
+    if (isSingleCRFromUndef() || RHS.isSingleCRFromUndef()) {
+      if (NewR.isSingleElement()) {
+        assert(getConstantRange() == NewR);
+        return false;
+      }
+      markOverdefined();
+      return true;
+    }
     if (NewR.isFullSet())
       return markOverdefined();
     else if (NewR == getConstantRange())
diff --git a/llvm/include/llvm/BinaryFormat/COFF.h b/llvm/include/llvm/BinaryFormat/COFF.h
index 626e0a431e93a..1919d7f0dece9 100644
--- a/llvm/include/llvm/BinaryFormat/COFF.h
+++ b/llvm/include/llvm/BinaryFormat/COFF.h
@@ -642,6 +642,11 @@ enum DLLCharacteristics : unsigned {
   IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE = 0x8000
 };
 
+enum ExtendedDLLCharacteristics : unsigned {
+  /// Image is CET compatible
+  IMAGE_DLL_CHARACTERISTICS_EX_CET_COMPAT = 0x0001
+};
+
 enum DebugType : unsigned {
   IMAGE_DEBUG_TYPE_UNKNOWN = 0,
   IMAGE_DEBUG_TYPE_COFF = 1,
@@ -660,6 +665,7 @@ enum DebugType : unsigned {
   IMAGE_DEBUG_TYPE_ILTCG = 14,
   IMAGE_DEBUG_TYPE_MPX = 15,
   IMAGE_DEBUG_TYPE_REPRO = 16,
+  IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS = 20,
 };
 
 enum BaseRelocationType : unsigned {
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index f3dd322940d33..3b1658929c34f 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -704,28 +704,33 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
     std::pair<unsigned, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, Src);
     std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(DL, Dst);
 
-    // Check for NOOP conversions.
-    if (SrcLT.first == DstLT.first &&
-        SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
+    unsigned SrcSize = SrcLT.second.getSizeInBits();
+    unsigned DstSize = DstLT.second.getSizeInBits();
 
+    switch (Opcode) {
+    default:
+      break;
+    case Instruction::Trunc:
+      // Check for NOOP conversions.
+      if (TLI->isTruncateFree(SrcLT.second, DstLT.second))
+        return 0;
+      LLVM_FALLTHROUGH;
+    case Instruction::BitCast:
       // Bitcast between types that are legalized to the same type are free.
-      if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
+      if (SrcLT.first == DstLT.first && SrcSize == DstSize)
+        return 0;
+      break;
+    case Instruction::ZExt:
+      if (TLI->isZExtFree(SrcLT.second, DstLT.second))
+        return 0;
+      break;
+    case Instruction::AddrSpaceCast:
+      if (TLI->isFreeAddrSpaceCast(Src->getPointerAddressSpace(),
+                                   Dst->getPointerAddressSpace()))
         return 0;
+      break;
     }
 
-    if (Opcode == Instruction::Trunc &&
-        TLI->isTruncateFree(SrcLT.second, DstLT.second))
-      return 0;
-
-    if (Opcode == Instruction::ZExt &&
-        TLI->isZExtFree(SrcLT.second, DstLT.second))
-      return 0;
-
-    if (Opcode == Instruction::AddrSpaceCast &&
-        TLI->isFreeAddrSpaceCast(Src->getPointerAddressSpace(),
-                                 Dst->getPointerAddressSpace()))
-      return 0;
-
     // If this is a zext/sext of a load, return 0 if the corresponding
     // extending load exists on target.
     if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h
new file mode 100644
index 0000000000000..cdec26879f732
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/CommandFlags.h
@@ -0,0 +1,149 @@
+//===-- CommandFlags.h - Command Line Flags Interface -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains codegen-specific flags that are shared between different
+// command line tools. The tools "llc" and "opt" both use this file to prevent
+// flag duplication.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Module.h"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
+#include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/CodeGen.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include <string>
+
+namespace llvm {
+
+namespace codegen {
+
+std::string getMArch();
+
+std::string getMCPU();
+
+std::vector<std::string> getMAttrs();
+
+Reloc::Model getRelocModel();
+Optional<Reloc::Model> getExplicitRelocModel();
+
+ThreadModel::Model getThreadModel();
+
+CodeModel::Model getCodeModel();
+Optional<CodeModel::Model> getExplicitCodeModel();
+
+llvm::ExceptionHandling getExceptionModel();
+
+CodeGenFileType getFileType();
+Optional<CodeGenFileType> getExplicitFileType();
+
+CodeGenFileType getFileType();
+
+llvm::FramePointer::FP getFramePointerUsage();
+
+bool getEnableUnsafeFPMath();
+
+bool getEnableNoInfsFPMath();
+
+bool getEnableNoNaNsFPMath();
+
+bool getEnableNoSignedZerosFPMath();
+
+bool getEnableNoTrappingFPMath();
+
+llvm::FPDenormal::DenormalMode getDenormalFPMath();
+
+bool getEnableHonorSignDependentRoundingFPMath();
+
+llvm::FloatABI::ABIType getFloatABIForCalls();
+
+llvm::FPOpFusion::FPOpFusionMode getFuseFPOps();
+
+bool getDontPlaceZerosInBSS();
+
+bool getEnableGuaranteedTailCallOpt();
+
+bool getDisableTailCalls();
+
+bool getStackSymbolOrdering();
+
+unsigned getOverrideStackAlignment();
+
+bool getStackRealign();
+
+std::string getTrapFuncName();
+
+bool getUseCtors();
+
+bool getRelaxELFRelocations();
+
+bool getDataSections();
+Optional<bool> getExplicitDataSections();
+
+bool getFunctionSections();
+Optional<bool> getExplicitFunctionSections();
+
+std::string getBBSections();
+
+unsigned getTLSSize();
+
+bool getEmulatedTLS();
+
+bool getUniqueSectionNames();
+
+bool getUniqueBBSectionNames();
+
+llvm::EABI getEABIVersion();
+
+llvm::DebuggerKind getDebuggerTuningOpt();
+
+bool getEnableStackSizeSection();
+
+bool getEnableAddrsig();
+
+bool getEmitCallSiteInfo();
+
+bool getEnableDebugEntryValues();
+
+bool getForceDwarfFrameSection();
+
+/// Create this object with static storage to register codegen-related command
+/// line options.
+struct RegisterCodeGenFlags {
+  RegisterCodeGenFlags();
+};
+
+llvm::BasicBlockSection getBBSectionsMode(llvm::TargetOptions &Options);
+
+// Common utility function tightly tied to the options listed here. Initializes
+// a TargetOptions object with CodeGen flags and returns it.
+TargetOptions InitTargetOptionsFromCodeGenFlags();
+
+std::string getCPUStr();
+
+std::string getFeaturesStr();
+
+std::vector<std::string> getFeatureList();
+
+void renderBoolStringAttr(AttrBuilder &B, StringRef Name, bool Val);
+
+/// Set function attributes of function \p F based on CPU, Features, and command
+/// line flags.
+void setFunctionAttributes(StringRef CPU, StringRef Features, Function &F);
+
+/// Set function attributes of functions in Module M based on CPU,
+/// Features, and command line flags.
+void setFunctionAttributes(StringRef CPU, StringRef Features, Module &M);
+} // namespace codegen
+} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/CommandFlags.inc b/llvm/include/llvm/CodeGen/CommandFlags.inc
deleted file mode 100644
index 8ed0d370ca6d8..0000000000000
--- a/llvm/include/llvm/CodeGen/CommandFlags.inc
+++ /dev/null
@@ -1,496 +0,0 @@
-//===-- CommandFlags.h - Command Line Flags Interface -----------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains codegen-specific flags that are shared between different
-// command line tools. The tools "llc" and "opt" both use this file to prevent
-// flag duplication.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/IR/Intrinsics.h"
-#include "llvm/IR/Module.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
-#include "llvm/MC/SubtargetFeature.h"
-#include "llvm/Support/CodeGen.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Host.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
-#include <string>
-using namespace llvm;
-
-static cl::opt<std::string>
-    MArch("march",
-          cl::desc("Architecture to generate code for (see --version)"));
-
-static cl::opt<std::string>
-    MCPU("mcpu",
-         cl::desc("Target a specific cpu type (-mcpu=help for details)"),
-         cl::value_desc("cpu-name"), cl::init(""));
-
-static cl::list<std::string>
-    MAttrs("mattr", cl::CommaSeparated,
-           cl::desc("Target specific attributes (-mattr=help for details)"),
-           cl::value_desc("a1,+a2,-a3,..."));
-
-static cl::opt<Reloc::Model> RelocModel(
-    "relocation-model", cl::desc("Choose relocation model"),
-    cl::values(
-        clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
-        clEnumValN(Reloc::PIC_, "pic",
-                   "Fully relocatable, position independent code"),
-        clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
-                   "Relocatable external references, non-relocatable code"),
-        clEnumValN(Reloc::ROPI, "ropi",
-                   "Code and read-only data relocatable, accessed PC-relative"),
-        clEnumValN(
-            Reloc::RWPI, "rwpi",
-            "Read-write data relocatable, accessed relative to static base"),
-        clEnumValN(Reloc::ROPI_RWPI, "ropi-rwpi",
-                   "Combination of ropi and rwpi")));
-
-LLVM_ATTRIBUTE_UNUSED static Optional<Reloc::Model> getRelocModel() {
-  if (RelocModel.getNumOccurrences()) {
-    Reloc::Model R = RelocModel;
-    return R;
-  }
-  return None;
-}
-
-static cl::opt<ThreadModel::Model> TMModel(
-    "thread-model", cl::desc("Choose threading model"),
-    cl::init(ThreadModel::POSIX),
-    cl::values(clEnumValN(ThreadModel::POSIX, "posix", "POSIX thread model"),
-               clEnumValN(ThreadModel::Single, "single",
-                          "Single thread model")));
-
-static cl::opt<llvm::CodeModel::Model> CMModel(
-    "code-model", cl::desc("Choose code model"),
-    cl::values(clEnumValN(CodeModel::Tiny, "tiny", "Tiny code model"),
-               clEnumValN(CodeModel::Small, "small", "Small code model"),
-               clEnumValN(CodeModel::Kernel, "kernel", "Kernel code model"),
-               clEnumValN(CodeModel::Medium, "medium", "Medium code model"),
-               clEnumValN(CodeModel::Large, "large", "Large code model")));
-
-LLVM_ATTRIBUTE_UNUSED static Optional<CodeModel::Model> getCodeModel() {
-  if (CMModel.getNumOccurrences()) {
-    CodeModel::Model M = CMModel;
-    return M;
-  }
-  return None;
-}
-
-static cl::opt<llvm::ExceptionHandling> ExceptionModel(
-    "exception-model", cl::desc("exception model"),
-    cl::init(ExceptionHandling::None),
-    cl::values(
-        clEnumValN(ExceptionHandling::None, "default",
-                   "default exception handling model"),
-        clEnumValN(ExceptionHandling::DwarfCFI, "dwarf",
-                   "DWARF-like CFI based exception handling"),
-        clEnumValN(ExceptionHandling::SjLj, "sjlj", "SjLj exception handling"),
-        clEnumValN(ExceptionHandling::ARM, "arm", "ARM EHABI exceptions"),
-        clEnumValN(ExceptionHandling::WinEH, "wineh",
-                   "Windows exception model"),
-        clEnumValN(ExceptionHandling::Wasm, "wasm",
-                   "WebAssembly exception handling")));
-
-static cl::opt<CodeGenFileType> FileType(
-    "filetype", cl::init(CGFT_AssemblyFile),
-    cl::desc(
-        "Choose a file type (not all types are supported by all targets):"),
-    cl::values(clEnumValN(CGFT_AssemblyFile, "asm",
-                          "Emit an assembly ('.s') file"),
-               clEnumValN(CGFT_ObjectFile, "obj",
-                          "Emit a native object ('.o') file"),
-               clEnumValN(CGFT_Null, "null",
-                          "Emit nothing, for performance testing")));
-
-static cl::opt<llvm::FramePointer::FP> FramePointerUsage(
-    "frame-pointer", cl::desc("Specify frame pointer elimination optimization"),
-    cl::init(llvm::FramePointer::None),
-    cl::values(
-        clEnumValN(llvm::FramePointer::All, "all",
-                   "Disable frame pointer elimination"),
-        clEnumValN(llvm::FramePointer::NonLeaf, "non-leaf",
-                   "Disable frame pointer elimination for non-leaf frame"),
-        clEnumValN(llvm::FramePointer::None, "none",
-                   "Enable frame pointer elimination")));
-
-static cl::opt<bool> EnableUnsafeFPMath(
-    "enable-unsafe-fp-math",
-    cl::desc("Enable optimizations that may decrease FP precision"),
-    cl::init(false));
-
-static cl::opt<bool> EnableNoInfsFPMath(
-    "enable-no-infs-fp-math",
-    cl::desc("Enable FP math optimizations that assume no +-Infs"),
-    cl::init(false));
-
-static cl::opt<bool> EnableNoNaNsFPMath(
-    "enable-no-nans-fp-math",
-    cl::desc("Enable FP math optimizations that assume no NaNs"),
-    cl::init(false));
-
-static cl::opt<bool> EnableNoSignedZerosFPMath(
-    "enable-no-signed-zeros-fp-math",
-    cl::desc("Enable FP math optimizations that assume "
-             "the sign of 0 is insignificant"),
-    cl::init(false));
-
-static cl::opt<bool>
-    EnableNoTrappingFPMath("enable-no-trapping-fp-math",
-                           cl::desc("Enable setting the FP exceptions build "
-                                    "attribute not to use exceptions"),
-                           cl::init(false));
-
-static cl::opt<llvm::FPDenormal::DenormalMode> DenormalFPMath(
-    "denormal-fp-math",
-    cl::desc("Select which denormal numbers the code is permitted to require"),
-    cl::init(FPDenormal::IEEE),
-    cl::values(clEnumValN(FPDenormal::IEEE, "ieee",
-                          "IEEE 754 denormal numbers"),
-               clEnumValN(FPDenormal::PreserveSign, "preserve-sign",
-                          "the sign of a  flushed-to-zero number is preserved "
-                          "in the sign of 0"),
-               clEnumValN(FPDenormal::PositiveZero, "positive-zero",
-                          "denormals are flushed to positive zero")));
-
-static cl::opt<bool> EnableHonorSignDependentRoundingFPMath(
-    "enable-sign-dependent-rounding-fp-math", cl::Hidden,
-    cl::desc("Force codegen to assume rounding mode can change dynamically"),
-    cl::init(false));
-
-static cl::opt<llvm::FloatABI::ABIType> FloatABIForCalls(
-    "float-abi", cl::desc("Choose float ABI type"), cl::init(FloatABI::Default),
-    cl::values(clEnumValN(FloatABI::Default, "default",
-                          "Target default float ABI type"),
-               clEnumValN(FloatABI::Soft, "soft",
-                          "Soft float ABI (implied by -soft-float)"),
-               clEnumValN(FloatABI::Hard, "hard",
-                          "Hard float ABI (uses FP registers)")));
-
-static cl::opt<llvm::FPOpFusion::FPOpFusionMode> FuseFPOps(
-    "fp-contract", cl::desc("Enable aggressive formation of fused FP ops"),
-    cl::init(FPOpFusion::Standard),
-    cl::values(
-        clEnumValN(FPOpFusion::Fast, "fast", "Fuse FP ops whenever profitable"),
-        clEnumValN(FPOpFusion::Standard, "on", "Only fuse 'blessed' FP ops."),
-        clEnumValN(FPOpFusion::Strict, "off",
-                   "Only fuse FP ops when the result won't be affected.")));
-
-static cl::opt<bool> DontPlaceZerosInBSS(
-    "nozero-initialized-in-bss",
-    cl::desc("Don't place zero-initialized symbols into bss section"),
-    cl::init(false));
-
-static cl::opt<bool> EnableGuaranteedTailCallOpt(
-    "tailcallopt",
-    cl::desc(
-        "Turn fastcc calls into tail calls by (potentially) changing ABI."),
-    cl::init(false));
-
-static cl::opt<bool> DisableTailCalls("disable-tail-calls",
-                                      cl::desc("Never emit tail calls"),
-                                      cl::init(false));
-
-static cl::opt<bool> StackSymbolOrdering("stack-symbol-ordering",
-                                         cl::desc("Order local stack symbols."),
-                                         cl::init(true));
-
-static cl::opt<unsigned>
-    OverrideStackAlignment("stack-alignment",
-                           cl::desc("Override default stack alignment"),
-                           cl::init(0));
-
-static cl::opt<bool>
-    StackRealign("stackrealign",
-                 cl::desc("Force align the stack to the minimum alignment"),
-                 cl::init(false));
-
-static cl::opt<std::string> TrapFuncName(
-    "trap-func", cl::Hidden,
-    cl::desc("Emit a call to trap function rather than a trap instruction"),
-    cl::init(""));
-
-static cl::opt<bool> UseCtors("use-ctors",
-                              cl::desc("Use .ctors instead of .init_array."),
-                              cl::init(false));
-
-static cl::opt<bool> RelaxELFRelocations(
-    "relax-elf-relocations",
-    cl::desc("Emit GOTPCRELX/REX_GOTPCRELX instead of GOTPCREL on x86-64 ELF"),
-    cl::init(false));
-
-static cl::opt<bool> DataSections("data-sections",
-                                  cl::desc("Emit data into separate sections"),
-                                  cl::init(false));
-
-static cl::opt<bool>
-    FunctionSections("function-sections",
-                     cl::desc("Emit functions into separate sections"),
-                     cl::init(false));
-
-static cl::opt<std::string>
-    BBSections("basicblock-sections",
-               cl::desc("Emit basic blocks into separate sections"),
-               cl::value_desc("all | <function list (file)> | labels | none"),
-               cl::init("none"));
-
-static cl::opt<unsigned> TLSSize("tls-size",
-                                 cl::desc("Bit size of immediate TLS offsets"),
-                                 cl::init(0));
-
-static cl::opt<bool> EmulatedTLS("emulated-tls",
-                                 cl::desc("Use emulated TLS model"),
-                                 cl::init(false));
-
-static cl::opt<bool>
-    UniqueSectionNames("unique-section-names",
-                       cl::desc("Give unique names to every section"),
-                       cl::init(true));
-
-static cl::opt<bool> UniqueBBSectionNames(
-    "unique-bb-section-names",
-    cl::desc("Give unique names to every basic block section"),
-    cl::init(false));
-
-static cl::opt<llvm::EABI>
-    EABIVersion("meabi", cl::desc("Set EABI type (default depends on triple):"),
-                cl::init(EABI::Default),
-                cl::values(clEnumValN(EABI::Default, "default",
-                                      "Triple default EABI version"),
-                           clEnumValN(EABI::EABI4, "4", "EABI version 4"),
-                           clEnumValN(EABI::EABI5, "5", "EABI version 5"),
-                           clEnumValN(EABI::GNU, "gnu", "EABI GNU")));
-
-static cl::opt<DebuggerKind> DebuggerTuningOpt(
-    "debugger-tune", cl::desc("Tune debug info for a particular debugger"),
-    cl::init(DebuggerKind::Default),
-    cl::values(clEnumValN(DebuggerKind::GDB, "gdb", "gdb"),
-               clEnumValN(DebuggerKind::LLDB, "lldb", "lldb"),
-               clEnumValN(DebuggerKind::SCE, "sce", "SCE targets (e.g. PS4)")));
-
-static cl::opt<bool> EnableStackSizeSection(
-    "stack-size-section",
-    cl::desc("Emit a section containing stack size metadata"), cl::init(false));
-
-static cl::opt<bool>
-    EnableAddrsig("addrsig", cl::desc("Emit an address-significance table"),
-                  cl::init(false));
-
-static cl::opt<bool> EmitCallSiteInfo(
-    "emit-call-site-info",
-    cl::desc(
-        "Emit call site debug information, if debug information is enabled."),
-    cl::init(false));
-
-static cl::opt<bool>
-    EnableDebugEntryValues("debug-entry-values",
-                           cl::desc("Emit debug info about parameter's entry values"),
-                           cl::init(false));
-
-static cl::opt<bool>
-    ForceDwarfFrameSection("force-dwarf-frame-section",
-                           cl::desc("Always emit a debug frame section."),
-                           cl::init(false));
-
-static llvm::BasicBlockSection
-getBBSectionsMode(llvm::TargetOptions &Options) {
-  if (BBSections == "all")
-    return BasicBlockSection::All;
-  else if (BBSections == "labels")
-    return BasicBlockSection::Labels;
-  else if (BBSections == "none")
-    return BasicBlockSection::None;
-  else {
-    ErrorOr<std::unique_ptr<MemoryBuffer>> MBOrErr =
-        MemoryBuffer::getFile(BBSections);
-    if (!MBOrErr) {
-      errs() << "Error loading basic block sections function list file: "
-             << MBOrErr.getError().message() << "\n";
-    } else {
-      Options.BBSectionsFuncListBuf = std::move(*MBOrErr);
-    }
-    return BasicBlockSection::List;
-  }
-}
-
-// Common utility function tightly tied to the options listed here. Initializes
-// a TargetOptions object with CodeGen flags and returns it.
-static TargetOptions InitTargetOptionsFromCodeGenFlags() {
-  TargetOptions Options;
-  Options.AllowFPOpFusion = FuseFPOps;
-  Options.UnsafeFPMath = EnableUnsafeFPMath;
-  Options.NoInfsFPMath = EnableNoInfsFPMath;
-  Options.NoNaNsFPMath = EnableNoNaNsFPMath;
-  Options.NoSignedZerosFPMath = EnableNoSignedZerosFPMath;
-  Options.NoTrappingFPMath = EnableNoTrappingFPMath;
-  Options.FPDenormalMode = DenormalFPMath;
-  Options.HonorSignDependentRoundingFPMathOption =
-      EnableHonorSignDependentRoundingFPMath;
-  if (FloatABIForCalls != FloatABI::Default)
-    Options.FloatABIType = FloatABIForCalls;
-  Options.NoZerosInBSS = DontPlaceZerosInBSS;
-  Options.GuaranteedTailCallOpt = EnableGuaranteedTailCallOpt;
-  Options.StackAlignmentOverride = OverrideStackAlignment;
-  Options.StackSymbolOrdering = StackSymbolOrdering;
-  Options.UseInitArray = !UseCtors;
-  Options.RelaxELFRelocations = RelaxELFRelocations;
-  Options.DataSections = DataSections;
-  Options.FunctionSections = FunctionSections;
-  Options.BBSections = getBBSectionsMode(Options);
-  Options.UniqueSectionNames = UniqueSectionNames;
-  Options.UniqueBBSectionNames = UniqueBBSectionNames;
-  Options.TLSSize = TLSSize;
-  Options.EmulatedTLS = EmulatedTLS;
-  Options.ExplicitEmulatedTLS = EmulatedTLS.getNumOccurrences() > 0;
-  Options.ExceptionModel = ExceptionModel;
-  Options.EmitStackSizeSection = EnableStackSizeSection;
-  Options.EmitAddrsig = EnableAddrsig;
-  Options.EmitCallSiteInfo = EmitCallSiteInfo;
-  Options.EnableDebugEntryValues = EnableDebugEntryValues;
-  Options.ForceDwarfFrameSection = ForceDwarfFrameSection;
-
-  Options.MCOptions = InitMCTargetOptionsFromFlags();
-
-  Options.ThreadModel = TMModel;
-  Options.EABIVersion = EABIVersion;
-  Options.DebuggerTuning = DebuggerTuningOpt;
-
-  return Options;
-}
-
-LLVM_ATTRIBUTE_UNUSED static std::string getCPUStr() {
-  // If user asked for the 'native' CPU, autodetect here. If autodection fails,
-  // this will set the CPU to an empty string which tells the target to
-  // pick a basic default.
-  if (MCPU == "native") return std::string(sys::getHostCPUName());
-
-  return MCPU;
-}
-
-LLVM_ATTRIBUTE_UNUSED static std::string getFeaturesStr() {
-  SubtargetFeatures Features;
-
-  // If user asked for the 'native' CPU, we need to autodetect features.
-  // This is necessary for x86 where the CPU might not support all the
-  // features the autodetected CPU name lists in the target. For example,
-  // not all Sandybridge processors support AVX.
-  if (MCPU == "native") {
-    StringMap<bool> HostFeatures;
-    if (sys::getHostCPUFeatures(HostFeatures))
-      for (auto &F : HostFeatures)
-        Features.AddFeature(F.first(), F.second);
-  }
-
-  for (unsigned i = 0; i != MAttrs.size(); ++i)
-    Features.AddFeature(MAttrs[i]);
-
-  return Features.getString();
-}
-
-LLVM_ATTRIBUTE_UNUSED static std::vector<std::string> getFeatureList() {
-  SubtargetFeatures Features;
-
-  // If user asked for the 'native' CPU, we need to autodetect features.
-  // This is necessary for x86 where the CPU might not support all the
-  // features the autodetected CPU name lists in the target. For example,
-  // not all Sandybridge processors support AVX.
-  if (MCPU == "native") {
-    StringMap<bool> HostFeatures;
-    if (sys::getHostCPUFeatures(HostFeatures))
-      for (auto &F : HostFeatures)
-        Features.AddFeature(F.first(), F.second);
-  }
-
-  for (unsigned i = 0; i != MAttrs.size(); ++i)
-    Features.AddFeature(MAttrs[i]);
-
-  return Features.getFeatures();
-}
-
-static void renderBoolStringAttr(AttrBuilder &B, StringRef Name, bool Val) {
-  B.addAttribute(Name, Val ? "true" : "false");
-}
-
-#define HANDLE_BOOL_ATTR(CL, AttrName)                              \
-  do {                                                              \
-    if (CL.getNumOccurrences() > 0 && !F.hasFnAttribute(AttrName))  \
-      renderBoolStringAttr(NewAttrs, AttrName, CL);                 \
-  } while (0)
-
-
-/// Set function attributes of function \p F based on CPU, Features, and command
-/// line flags.
-LLVM_ATTRIBUTE_UNUSED static void
-setFunctionAttributes(StringRef CPU, StringRef Features, Function &F) {
-  auto &Ctx = F.getContext();
-  AttributeList Attrs = F.getAttributes();
-  AttrBuilder NewAttrs;
-
-  if (!CPU.empty() && !F.hasFnAttribute("target-cpu"))
-    NewAttrs.addAttribute("target-cpu", CPU);
-  if (!Features.empty()) {
-    // Append the command line features to any that are already on the function.
-    StringRef OldFeatures
-      = F.getFnAttribute("target-features").getValueAsString();
-    if (OldFeatures.empty())
-      NewAttrs.addAttribute("target-features", Features);
-    else {
-      SmallString<256> Appended(OldFeatures);
-      Appended.push_back(',');
-      Appended.append(Features);
-      NewAttrs.addAttribute("target-features", Appended);
-    }
-  }
-  if (FramePointerUsage.getNumOccurrences() > 0 &&
-      !F.hasFnAttribute("frame-pointer")) {
-    if (FramePointerUsage == llvm::FramePointer::All)
-      NewAttrs.addAttribute("frame-pointer", "all");
-    else if (FramePointerUsage == llvm::FramePointer::NonLeaf)
-      NewAttrs.addAttribute("frame-pointer", "non-leaf");
-    else if (FramePointerUsage == llvm::FramePointer::None)
-      NewAttrs.addAttribute("frame-pointer", "none");
-  }
-  if (DisableTailCalls.getNumOccurrences() > 0)
-    NewAttrs.addAttribute("disable-tail-calls",
-                          toStringRef(DisableTailCalls));
-  if (StackRealign)
-    NewAttrs.addAttribute("stackrealign");
-
-  HANDLE_BOOL_ATTR(EnableUnsafeFPMath, "unsafe-fp-math");
-  HANDLE_BOOL_ATTR(EnableNoInfsFPMath, "no-infs-fp-math");
-  HANDLE_BOOL_ATTR(EnableNoNaNsFPMath, "no-nans-fp-math");
-  HANDLE_BOOL_ATTR(EnableNoSignedZerosFPMath, "no-signed-zeros-fp-math");
-
-  if (TrapFuncName.getNumOccurrences() > 0)
-    for (auto &B : F)
-      for (auto &I : B)
-        if (auto *Call = dyn_cast<CallInst>(&I))
-          if (const auto *F = Call->getCalledFunction())
-            if (F->getIntrinsicID() == Intrinsic::debugtrap ||
-                F->getIntrinsicID() == Intrinsic::trap)
-              Call->addAttribute(
-                llvm::AttributeList::FunctionIndex,
-                Attribute::get(Ctx, "trap-func-name", TrapFuncName));
-
-  // Let NewAttrs override Attrs.
-  F.setAttributes(
-    Attrs.addAttributes(Ctx, AttributeList::FunctionIndex, NewAttrs));
-}
-
-/// Set function attributes of functions in Module M based on CPU,
-/// Features, and command line flags.
-LLVM_ATTRIBUTE_UNUSED static void
-setFunctionAttributes(StringRef CPU, StringRef Features, Module &M) {
-  for (Function &F : M)
-    setFunctionAttributes(CPU, Features, F);
-}
diff --git a/llvm/include/llvm/CodeGen/DIE.h b/llvm/include/llvm/CodeGen/DIE.h
index cf01d456f1f84..c7baaf6aef3dd 100644
--- a/llvm/include/llvm/CodeGen/DIE.h
+++ b/llvm/include/llvm/CodeGen/DIE.h
@@ -551,10 +551,21 @@ template <class T> class IntrusiveBackList : IntrusiveBackListBase {
   }
 
   void takeNodes(IntrusiveBackList<T> &Other) {
-    for (auto &N : Other) {
-      N.Next.setPointerAndInt(&N, true);
-      push_back(N);
-    }
+    if (Other.empty())
+      return;
+
+    T *FirstNode = static_cast<T *>(Other.Last->Next.getPointer());
+    T *IterNode = FirstNode;
+    do {
+      // Keep a pointer to the node and increment the iterator.
+      T *TmpNode = IterNode;
+      IterNode = static_cast<T *>(IterNode->Next.getPointer());
+
+      // Unlink the node and push it back to this list.
+      TmpNode->Next.setPointerAndInt(TmpNode, true);
+      push_back(*TmpNode);
+    } while (IterNode != FirstNode);
+
     Other.Last = nullptr;
   }
 
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 1d144688a006e..d47dddf88f516 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -190,6 +190,19 @@ class CombinerHelper {
   bool applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
   bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
 
+  /// Return true if any explicit use operand on \p MI is defined by a
+  /// G_IMPLICIT_DEF.
+  bool matchAnyExplicitUseIsUndef(MachineInstr &MI);
+
+  /// Replace an instruction with a G_FCONSTANT with value \p C.
+  bool replaceInstWithFConstant(MachineInstr &MI, double C);
+
+  /// Replace an instruction with a G_CONSTANT with value \p C.
+  bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
+
+  /// Replace an instruction with a G_IMPLICIT_DEF.
+  bool replaceInstWithUndef(MachineInstr &MI);
+
   /// Try to transform \p MI by using all of the above
   /// combine functions. Returns true if changed.
   bool tryCombine(MachineInstr &MI);
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index af8129b98a2b8..41577a86b2122 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -167,7 +167,8 @@ class LegalizationArtifactCombiner {
 
   bool tryCombineTrunc(MachineInstr &MI,
                        SmallVectorImpl<MachineInstr *> &DeadInsts,
-                       SmallVectorImpl<Register> &UpdatedDefs) {
+                       SmallVectorImpl<Register> &UpdatedDefs,
+                       GISelObserverWrapper &Observer) {
     assert(MI.getOpcode() == TargetOpcode::G_TRUNC);
 
     Builder.setInstr(MI);
@@ -189,6 +190,66 @@ class LegalizationArtifactCombiner {
       }
     }
 
+    // Try to fold trunc(merge) to directly use the source of the merge.
+    // This gets rid of large, difficult to legalize, merges
+    if (SrcMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) {
+      const Register MergeSrcReg = SrcMI->getOperand(1).getReg();
+      const LLT MergeSrcTy = MRI.getType(MergeSrcReg);
+      const LLT DstTy = MRI.getType(DstReg);
+
+      // We can only fold if the types are scalar
+      const unsigned DstSize = DstTy.getSizeInBits();
+      const unsigned MergeSrcSize = MergeSrcTy.getSizeInBits();
+      if (!DstTy.isScalar() || !MergeSrcTy.isScalar())
+        return false;
+
+      if (DstSize < MergeSrcSize) {
+        // When the merge source is larger than the destination, we can just
+        // truncate the merge source directly
+        if (isInstUnsupported({TargetOpcode::G_TRUNC, {DstTy, MergeSrcTy}}))
+          return false;
+
+        LLVM_DEBUG(dbgs() << "Combining G_TRUNC(G_MERGE_VALUES) to G_TRUNC: "
+                          << MI);
+
+        Builder.buildTrunc(DstReg, MergeSrcReg);
+        UpdatedDefs.push_back(DstReg);
+      } else if (DstSize == MergeSrcSize) {
+        // If the sizes match we can simply try to replace the register
+        LLVM_DEBUG(
+            dbgs() << "Replacing G_TRUNC(G_MERGE_VALUES) with merge input: "
+                   << MI);
+        replaceRegOrBuildCopy(DstReg, MergeSrcReg, MRI, Builder, UpdatedDefs,
+                              Observer);
+      } else if (DstSize % MergeSrcSize == 0) {
+        // If the trunc size is a multiple of the merge source size we can use
+        // a smaller merge instead
+        if (isInstUnsupported(
+                {TargetOpcode::G_MERGE_VALUES, {DstTy, MergeSrcTy}}))
+          return false;
+
+        LLVM_DEBUG(
+            dbgs() << "Combining G_TRUNC(G_MERGE_VALUES) to G_MERGE_VALUES: "
+                   << MI);
+
+        const unsigned NumSrcs = DstSize / MergeSrcSize;
+        assert(NumSrcs < SrcMI->getNumOperands() - 1 &&
+               "trunc(merge) should require less inputs than merge");
+        SmallVector<Register, 2> SrcRegs(NumSrcs);
+        for (unsigned i = 0; i < NumSrcs; ++i)
+          SrcRegs[i] = SrcMI->getOperand(i + 1).getReg();
+
+        Builder.buildMerge(DstReg, SrcRegs);
+        UpdatedDefs.push_back(DstReg);
+      } else {
+        // Unable to combine
+        return false;
+      }
+
+      markInstAndDefDead(MI, *SrcMI, DeadInsts);
+      return true;
+    }
+
     return false;
   }
 
@@ -533,7 +594,7 @@ class LegalizationArtifactCombiner {
       Changed = tryCombineExtract(MI, DeadInsts, UpdatedDefs);
       break;
     case TargetOpcode::G_TRUNC:
-      Changed = tryCombineTrunc(MI, DeadInsts, UpdatedDefs);
+      Changed = tryCombineTrunc(MI, DeadInsts, UpdatedDefs, WrapperObserver);
       if (!Changed) {
         // Try to combine truncates away even if they are legal. As all artifact
         // combines at the moment look only "up" the def-use chains, we achieve
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index 6f35718902518..08d12a57adff0 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -275,6 +275,7 @@ class LegalizerHelper {
   LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
   LegalizeResult lowerFMad(MachineInstr &MI);
   LegalizeResult lowerIntrinsicRound(MachineInstr &MI);
+  LegalizeResult lowerFFloor(MachineInstr &MI);
   LegalizeResult lowerUnmergeValues(MachineInstr &MI);
   LegalizeResult lowerShuffleVector(MachineInstr &MI);
   LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index da7258b60f2f5..59c2aa898d4fd 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1446,6 +1446,11 @@ class MachineIRBuilder {
     return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
   }
 
+  /// Build and insert \p Dst = G_BSWAP \p Src0
+  MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
+    return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
+  }
+
   /// Build and insert \p Res = G_FADD \p Op0, \p Op1
   MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
                                 const SrcOp &Src1,
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
index f528d1a460128..8a8d3ce200409 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
@@ -29,18 +29,23 @@ class RegisterBank {
 private:
   unsigned ID;
   const char *Name;
-  unsigned Size;
+  const unsigned *Sizes;
   BitVector ContainedRegClasses;
 
-  /// Sentinel value used to recognize register bank not properly
+  /// HwMode of the target. Not initialized by the constructor, initialized
+  /// within generated RegisterBankInfo class constructor.
+  unsigned HwMode;
+
+  /// Sentinel values used to recognize register bank not properly
   /// initialized yet.
   static const unsigned InvalidID;
+  static const unsigned InvalidHwMode;
 
   /// Only the RegisterBankInfo can initialize RegisterBank properly.
   friend RegisterBankInfo;
 
 public:
-  RegisterBank(unsigned ID, const char *Name, unsigned Size,
+  RegisterBank(unsigned ID, const char *Name, const unsigned *Sizes,
                const uint32_t *CoveredClasses, unsigned NumRegClasses);
 
   /// Get the identifier of this register bank.
@@ -51,7 +56,7 @@ class RegisterBank {
   const char *getName() const { return Name; }
 
   /// Get the maximal size in bits that fits in this register bank.
-  unsigned getSize() const { return Size; }
+  unsigned getSize() const { return Sizes[HwMode]; }
 
   /// Check whether this instance is ready to be used.
   bool isValid() const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index 8725d96efd821..b86d2d10322f0 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -415,7 +415,8 @@ class RegisterBankInfo {
 
   /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
   /// RegisterBank instances.
-  RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
+  RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks,
+                   unsigned HwMode);
 
   /// This constructor is meaningless.
   /// It just provides a default constructor that can be used at link time
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 8f2f4bb34a332..cd33a37149089 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -46,6 +46,19 @@ class raw_ostream;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 
+enum MachineBasicBlockSection : unsigned {
+  ///  This is also the order of sections in a function.  Basic blocks that are
+  ///  part of the original function section (entry block) come first, followed
+  ///  by exception handling basic blocks, cold basic blocks and finally basic
+  //   blocks that need unique sections.
+  MBBS_Entry,
+  MBBS_Exception,
+  MBBS_Cold,
+  MBBS_Unique,
+  ///  None implies no sections for any basic block, the default.
+  MBBS_None,
+};
+
 template <> struct ilist_traits<MachineInstr> {
 private:
   friend class MachineBasicBlock; // Set by the owning MachineBasicBlock.
@@ -130,6 +143,9 @@ class MachineBasicBlock
   /// Indicate that this basic block is the entry block of a cleanup funclet.
   bool IsCleanupFuncletEntry = false;
 
+  /// Stores the Section type of the basic block with basic block sections.
+  MachineBasicBlockSection SectionType = MBBS_None;
+
   /// Default target of the callbr of a basic block.
   bool InlineAsmBrDefaultTarget = false;
 
@@ -140,6 +156,9 @@ class MachineBasicBlock
   /// is only computed once and is cached.
   mutable MCSymbol *CachedMCSymbol = nullptr;
 
+  /// Used during basic block sections to mark the end of a basic block.
+  MCSymbol *EndMCSymbol = nullptr;
+
   // Intrusive list support
   MachineBasicBlock() = default;
 
@@ -415,6 +434,18 @@ class MachineBasicBlock
   /// Indicates if this is the entry block of a cleanup funclet.
   void setIsCleanupFuncletEntry(bool V = true) { IsCleanupFuncletEntry = V; }
 
+  /// Returns true if this block begins any section.
+  bool isBeginSection() const;
+
+  /// Returns true if this block ends any section.
+  bool isEndSection() const;
+
+  /// Returns the type of section this basic block belongs to.
+  MachineBasicBlockSection getSectionType() const { return SectionType; }
+
+  /// Indicate that the basic block belongs to a Section Type.
+  void setSectionType(MachineBasicBlockSection V) { SectionType = V; }
+
   /// Returns true if this is the indirect dest of an INLINEASM_BR.
   bool isInlineAsmBrIndirectTarget(const MachineBasicBlock *Tgt) const {
     return InlineAsmBrIndirectTargets.count(Tgt);
@@ -453,6 +484,12 @@ class MachineBasicBlock
   void moveBefore(MachineBasicBlock *NewAfter);
   void moveAfter(MachineBasicBlock *NewBefore);
 
+  /// Returns true if this and MBB belong to the same section.
+  bool sameSection(const MachineBasicBlock *MBB) const;
+
+  /// Returns the basic block that ends the section which contains this one.
+  const MachineBasicBlock *getSectionEndMBB() const;
+
   /// Update the terminator instructions in block to account for changes to the
   /// layout. If the block previously used a fallthrough, it may now need a
   /// branch, and if it previously used branching it may now be able to use a
@@ -839,6 +876,12 @@ class MachineBasicBlock
   /// Return the MCSymbol for this basic block.
   MCSymbol *getSymbol() const;
 
+  /// Sets the MCSymbol corresponding to the end of this basic block.
+  void setEndMCSymbol(MCSymbol *Sym) { EndMCSymbol = Sym; }
+
+  /// Returns the MCSymbol corresponding to the end of this basic block.
+  MCSymbol *getEndMCSymbol() const { return EndMCSymbol; }
+
   Optional<uint64_t> getIrrLoopHeaderWeight() const {
     return IrrLoopHeaderWeight;
   }
diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
index 755e8d8b6f76e..384b206fc2202 100644
--- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
@@ -583,7 +583,13 @@ class MachineFrameInfo {
 
   /// Return the alignment in bytes that this function must be aligned to,
   /// which is greater than the default stack alignment provided by the target.
-  unsigned getMaxAlignment() const { return MaxAlignment.value(); }
+  LLVM_ATTRIBUTE_DEPRECATED(unsigned getMaxAlignment() const,
+                            "Use getMaxAlign instead") {
+    return MaxAlignment.value();
+  }
+  /// Return the alignment in bytes that this function must be aligned to,
+  /// which is greater than the default stack alignment provided by the target.
+  Align getMaxAlign() const { return MaxAlignment; }
 
   /// Make sure the function is at least Align bytes aligned.
   void ensureMaxAlignment(Align Alignment);
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 33cefea76ab2e..7b767ff7c7a53 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -37,6 +37,7 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Recycler.h"
+#include "llvm/Target/TargetOptions.h"
 #include <cassert>
 #include <cstdint>
 #include <memory>
@@ -64,6 +65,7 @@ class MachineRegisterInfo;
 class MCContext;
 class MCInstrDesc;
 class MCSymbol;
+class MCSection;
 class Pass;
 class PseudoSourceValueManager;
 class raw_ostream;
@@ -244,6 +246,9 @@ class MachineFunction {
   // Keep track of jump tables for switch instructions
   MachineJumpTableInfo *JumpTableInfo;
 
+  // Keep track of the function section.
+  MCSection *Section = nullptr;
+
   // Keeps track of Wasm exception handling related data. This will be null for
   // functions that aren't using a wasm EH personality.
   WasmEHFuncInfo *WasmEHInfo = nullptr;
@@ -257,6 +262,12 @@ class MachineFunction {
   // numbered and this vector keeps track of the mapping from ID's to MBB's.
   std::vector<MachineBasicBlock*> MBBNumbering;
 
+  // Unary encoding of basic block symbols is used to reduce size of ".strtab".
+  // Basic block number 'i' gets a prefix of length 'i'.  The ith character also
+  // denotes the type of basic block number 'i'.  Return blocks are marked with
+  // 'r', landing pads with 'l' and regular blocks with 'a'.
+  std::vector<char> BBSectionsSymbolPrefix;
+
   // Pool-allocate MachineFunction-lifetime and IR objects.
   BumpPtrAllocator Allocator;
 
@@ -332,6 +343,14 @@ class MachineFunction {
   bool HasEHScopes = false;
   bool HasEHFunclets = false;
 
+  /// Section Type for basic blocks, only relevant with basic block sections.
+  BasicBlockSection BBSectionsType = BasicBlockSection::None;
+
+  /// With Basic Block Sections, this stores the bb ranges of cold and
+  /// exception sections.
+  std::pair<int, int> ColdSectionRange = {-1, -1};
+  std::pair<int, int> ExceptionSectionRange = {-1, -1};
+
   /// List of C++ TypeInfo used.
   std::vector<const GlobalValue *> TypeInfos;
 
@@ -453,6 +472,12 @@ class MachineFunction {
   MachineModuleInfo &getMMI() const { return MMI; }
   MCContext &getContext() const { return Ctx; }
 
+  /// Returns the Section this function belongs to.
+  MCSection *getSection() const { return Section; }
+
+  /// Indicates the Section this function belongs to.
+  void setSection(MCSection *S) { Section = S; }
+
   PseudoSourceValueManager &getPSVManager() const { return *PSVManager; }
 
   /// Return the DataLayout attached to the Module associated to this MF.
@@ -467,6 +492,35 @@ class MachineFunction {
   /// getFunctionNumber - Return a unique ID for the current function.
   unsigned getFunctionNumber() const { return FunctionNumber; }
 
+  /// Returns true if this function has basic block sections enabled.
+  bool hasBBSections() const {
+    return (BBSectionsType == BasicBlockSection::All ||
+            BBSectionsType == BasicBlockSection::List);
+  }
+
+  /// Returns true if basic block labels are to be generated for this function.
+  bool hasBBLabels() const {
+    return BBSectionsType == BasicBlockSection::Labels;
+  }
+
+  void setBBSectionsType(BasicBlockSection V) { BBSectionsType = V; }
+
+  void setSectionRange();
+
+  /// Returns true if this basic block number starts a cold or exception
+  /// section.
+  bool isSectionStartMBB(int N) const {
+    return (N == ColdSectionRange.first || N == ExceptionSectionRange.first);
+  }
+
+  /// Returns true if this basic block ends a cold or exception section.
+  bool isSectionEndMBB(int N) const {
+    return (N == ColdSectionRange.second || N == ExceptionSectionRange.second);
+  }
+
+  /// Creates basic block Labels for this function.
+  void createBBLabels();
+
   /// getTarget - Return the target machine this machine code is compiled with
   const LLVMTargetMachine &getTarget() const { return Target; }
 
@@ -1014,6 +1068,11 @@ class MachineFunction {
   /// of the instruction stream.
   void copyCallSiteInfo(const MachineInstr *Old,
                         const MachineInstr *New);
+
+  const std::vector<char> &getBBSectionsSymbolPrefix() const {
+    return BBSectionsSymbolPrefix;
+  }
+
   /// Move the call site info from \p Old to \New call site info. This function
   /// is used when we are replacing one call instruction with another one to
   /// the same callee.
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index c5a90b0c46e36..064b6075c095d 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -91,6 +91,8 @@ class MachineRegisterInfo {
   /// all registers that were disabled are removed from the list.
   SmallVector<MCPhysReg, 16> UpdatedCSRs;
 
+  void initUpdatedCSRs();
+
   /// RegAllocHints - This vector records register allocation hints for
   /// virtual registers. For each virtual register, it keeps a pair of hint
   /// type and hints vector making up the allocation hints. Only the first
@@ -231,12 +233,17 @@ class MachineRegisterInfo {
 
   /// Disables the register from the list of CSRs.
   /// I.e. the register will not appear as part of the CSR mask.
-  /// \see UpdatedCalleeSavedRegs.
-  void disableCalleeSavedRegister(unsigned Reg);
+  /// \see UpdatedCSRs.
+  void disableCalleeSavedRegister(Register Reg);
+
+  /// Enables the register from the list of CSRs.
+  /// I.e. the register will appear as part of the CSR mask.
+  /// \see UpdatedCSRs.
+  void enableCalleeSavedRegister(Register Reg);
 
   /// Returns list of callee saved registers.
   /// The function returns the updated CSR list (after taking into account
-  /// registers that are disabled from the CSR list).
+  /// registers that are enabled/disabled from the CSR list).
   const MCPhysReg *getCalleeSavedRegs() const;
 
   /// Sets the updated Callee Saved Registers list.
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 72c7e8b1b6bb7..997f36eb6aede 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -22,6 +22,7 @@ namespace llvm {
 class FunctionPass;
 class MachineFunction;
 class MachineFunctionPass;
+class MemoryBuffer;
 class ModulePass;
 class Pass;
 class TargetMachine;
@@ -42,6 +43,12 @@ namespace llvm {
   /// the entry block.
   FunctionPass *createUnreachableBlockEliminationPass();
 
+  /// createBBSectionsPrepare Pass - This pass assigns sections to machine basic
+  /// blocks and is enabled with -fbasicblock-sections.
+  /// Buf is a memory buffer that contains the list of functions and basic
+  /// block ids to selectively enable basic block sections.
+  MachineFunctionPass *createBBSectionsPreparePass(const MemoryBuffer *Buf);
+
   /// MachineFunctionPrinter pass - This pass prints out the machine function to
   /// the given stream as a debugging tool.
   MachineFunctionPass *
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.h b/llvm/include/llvm/CodeGen/RDFGraph.h
similarity index 100%
rename from llvm/lib/Target/Hexagon/RDFGraph.h
rename to llvm/include/llvm/CodeGen/RDFGraph.h
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.h b/llvm/include/llvm/CodeGen/RDFLiveness.h
similarity index 100%
rename from llvm/lib/Target/Hexagon/RDFLiveness.h
rename to llvm/include/llvm/CodeGen/RDFLiveness.h
diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.h b/llvm/include/llvm/CodeGen/RDFRegisters.h
similarity index 100%
rename from llvm/lib/Target/Hexagon/RDFRegisters.h
rename to llvm/include/llvm/CodeGen/RDFRegisters.h
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 993a3c8bbf95f..3cf7b6a346805 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -935,7 +935,7 @@ class SelectionDAG {
   SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,
                   ArrayRef<SDValue> Ops);
   SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
-                  ArrayRef<SDValue> Ops);
+                  ArrayRef<SDValue> Ops, const SDNodeFlags Flags = SDNodeFlags());
 
   // Specialize based on number of operands.
   SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h
index d2ab79cb235e8..f6513e8d4ea0c 100644
--- a/llvm/include/llvm/CodeGen/StackProtector.h
+++ b/llvm/include/llvm/CodeGen/StackProtector.h
@@ -95,7 +95,7 @@ class StackProtector : public FunctionPass {
                                 bool InStruct = false) const;
 
   /// Check whether a stack allocation has its address taken.
-  bool HasAddressTaken(const Instruction *AI);
+  bool HasAddressTaken(const Instruction *AI, uint64_t AllocSize);
 
   /// RequiresStackProtector - Check whether or not this function needs a
   /// stack protector based upon the stack protector level.
diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
index 7ccdd6326a908..177510d48db21 100644
--- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -93,6 +93,11 @@ class TargetFrameLowering {
   /// is the largest alignment for any data object in the target.
   ///
   unsigned getStackAlignment() const { return StackAlignment.value(); }
+  /// getStackAlignment - This method returns the number of bytes to which the
+  /// stack pointer must be aligned on entry to a function.  Typically, this
+  /// is the largest alignment for any data object in the target.
+  ///
+  Align getStackAlign() const { return StackAlignment; }
 
   /// alignSPAdjust - This method aligns the stack adjustment to the correct
   /// alignment.
@@ -110,9 +115,15 @@ class TargetFrameLowering {
   /// which the stack pointer must be aligned at all times, even between
   /// calls.
   ///
-  unsigned getTransientStackAlignment() const {
+  LLVM_ATTRIBUTE_DEPRECATED(unsigned getTransientStackAlignment() const,
+                            "Use getTransientStackAlign instead") {
     return TransientStackAlignment.value();
   }
+  /// getTransientStackAlignment - This method returns the number of bytes to
+  /// which the stack pointer must be aligned at all times, even between
+  /// calls.
+  ///
+  Align getTransientStackAlign() const { return TransientStackAlignment; }
 
   /// isStackRealignable - This method returns whether the stack can be
   /// realigned.
diff --git a/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h b/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
index 790e16ffa9eb9..2a1123e27dada 100644
--- a/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+++ b/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
@@ -65,6 +65,15 @@ class TargetLoweringObjectFileELF : public TargetLoweringObjectFile {
   MCSection *getSectionForJumpTable(const Function &F,
                                     const TargetMachine &TM) const override;
 
+  MCSection *
+  getSectionForMachineBasicBlock(const Function &F,
+                                 const MachineBasicBlock &MBB,
+                                 const TargetMachine &TM) const override;
+
+  MCSection *getNamedSectionForMachineBasicBlock(
+      const Function &F, const MachineBasicBlock &MBB, const TargetMachine &TM,
+      const char *Suffix) const override;
+
   bool shouldPutJumpTableInFunctionSection(bool UsesLabelDifference,
                                            const Function &F) const override;
 
diff --git a/llvm/include/llvm/IR/Constants.h b/llvm/include/llvm/IR/Constants.h
index e6d8c0eb4d925..d0ea1adbbf183 100644
--- a/llvm/include/llvm/IR/Constants.h
+++ b/llvm/include/llvm/IR/Constants.h
@@ -392,7 +392,7 @@ class ConstantAggregateZero final : public ConstantData {
 /// use operands.
 class ConstantAggregate : public Constant {
 protected:
-  ConstantAggregate(CompositeType *T, ValueTy VT, ArrayRef<Constant *> V);
+  ConstantAggregate(Type *T, ValueTy VT, ArrayRef<Constant *> V);
 
 public:
   /// Transparently provide more efficient getOperand methods.
diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h
index 3b56da680c6e2..ac3abe3c32dc6 100644
--- a/llvm/include/llvm/IR/DerivedTypes.h
+++ b/llvm/include/llvm/IR/DerivedTypes.h
@@ -195,26 +195,6 @@ class FunctionCallee {
   Value *Callee = nullptr;
 };
 
-/// Common super class of ArrayType, StructType and VectorType.
-class CompositeType : public Type {
-protected:
-  explicit CompositeType(LLVMContext &C, TypeID tid) : Type(C, tid) {}
-
-public:
-  /// Given an index value into the type, return the type of the element.
-  Type *getTypeAtIndex(const Value *V) const;
-  Type *getTypeAtIndex(unsigned Idx) const;
-  bool indexValid(const Value *V) const;
-  bool indexValid(unsigned Idx) const;
-
-  /// Methods for support type inquiry through isa, cast, and dyn_cast.
-  static bool classof(const Type *T) {
-    return T->getTypeID() == ArrayTyID ||
-           T->getTypeID() == StructTyID ||
-           T->getTypeID() == VectorTyID;
-  }
-};
-
 /// Class to represent struct types. There are two different kinds of struct
 /// types: Literal structs and Identified structs.
 ///
@@ -235,8 +215,8 @@ class CompositeType : public Type {
 /// elements as defined by DataLayout (which is required to match what the code
 /// generator for a target expects).
 ///
-class StructType : public CompositeType {
-  StructType(LLVMContext &C) : CompositeType(C, StructTyID) {}
+class StructType : public Type {
+  StructType(LLVMContext &C) : Type(C, StructTyID) {}
 
   enum {
     /// This is the contents of the SubClassData field.
@@ -350,6 +330,11 @@ class StructType : public CompositeType {
     assert(N < NumContainedTys && "Element number out of range!");
     return ContainedTys[N];
   }
+  /// Given an index value into the type, return the type of the element.
+  Type *getTypeAtIndex(const Value *V) const;
+  Type *getTypeAtIndex(unsigned N) const { return getElementType(N); }
+  bool indexValid(const Value *V) const;
+  bool indexValid(unsigned Idx) const { return Idx < getNumElements(); }
 
   /// Methods for support type inquiry through isa, cast, and dyn_cast.
   static bool classof(const Type *T) {
@@ -375,14 +360,14 @@ Type *Type::getStructElementType(unsigned N) const {
 /// for use of SIMD instructions. SequentialType holds the common features of
 /// both, which stem from the fact that both lay their components out in memory
 /// identically.
-class SequentialType : public CompositeType {
+class SequentialType : public Type {
   Type *ContainedType;               ///< Storage for the single contained type.
   uint64_t NumElements;
 
 protected:
   SequentialType(TypeID TID, Type *ElType, uint64_t NumElements)
-    : CompositeType(ElType->getContext(), TID), ContainedType(ElType),
-      NumElements(NumElements) {
+      : Type(ElType->getContext(), TID), ContainedType(ElType),
+        NumElements(NumElements) {
     ContainedTys = &ContainedType;
     NumContainedTys = 1;
   }
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index e558d4317efc3..713624d13bef0 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -1008,16 +1008,23 @@ class GetElementPtrInst : public Instruction {
     return getPointerAddressSpace();
   }
 
-  /// Returns the type of the element that would be loaded with
-  /// a load instruction with the specified parameters.
+  /// Returns the result type of a getelementptr with the given source
+  /// element type and indexes.
   ///
   /// Null is returned if the indices are invalid for the specified
-  /// pointer type.
-  ///
+  /// source element type.
   static Type *getIndexedType(Type *Ty, ArrayRef<Value *> IdxList);
   static Type *getIndexedType(Type *Ty, ArrayRef<Constant *> IdxList);
   static Type *getIndexedType(Type *Ty, ArrayRef<uint64_t> IdxList);
 
+  /// Return the type of the element at the given index of an indexable
+  /// type.  This is equivalent to "getIndexedType(Agg, {Zero, Idx})".
+  ///
+  /// Returns null if the type can't be indexed, or the given index is not
+  /// legal for the given type.
+  static Type *getTypeAtIndex(Type *Ty, Value *Idx);
+  static Type *getTypeAtIndex(Type *Ty, uint64_t Idx);
+
   inline op_iterator       idx_begin()       { return op_begin()+1; }
   inline const_op_iterator idx_begin() const { return op_begin()+1; }
   inline op_iterator       idx_end()         { return op_end(); }
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 3a205de4e368e..a6de3f949199e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -778,12 +778,6 @@ def llvm_nxv2f64_ty : LLVMType<nxv2f64>;
 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 
   class AdvSIMD_1Vec_PredLoad_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
-                 LLVMPointerTo<0>],
-                [IntrReadMem, IntrArgMemOnly]>;
-
-  class AdvSIMD_1Vec_PredFaultingLoad_Intrinsic
     : Intrinsic<[llvm_anyvector_ty],
                 [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                  LLVMPointerToElt<0>],
@@ -793,7 +787,7 @@ let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
     : Intrinsic<[],
                 [llvm_anyvector_ty,
                  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
-                 LLVMPointerTo<0>],
+                 LLVMPointerToElt<0>],
                 [IntrArgMemOnly, NoCapture<2>]>;
 
   class AdvSIMD_SVE_Index_Intrinsic
@@ -1263,14 +1257,34 @@ class AdvSIMD_ScatterStore_VS_Intrinsic
                ],
                [IntrWriteMem, IntrArgMemOnly]>;
 
+
+class SVE_gather_prf_scalar_base_vector_offset_scaled
+    : Intrinsic<[],
+                [
+                  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate
+                  llvm_ptr_ty, // Base address
+                  llvm_anyvector_ty, // Offsets
+                  llvm_i32_ty // Prfop
+                ],
+                [IntrInaccessibleMemOrArgMemOnly, NoCapture<1>, ImmArg<3>]>;
+
+class SVE_gather_prf_vector_base_scalar_offset
+    : Intrinsic<[],
+                [
+                  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate
+                  llvm_anyvector_ty, // Base addresses
+                  llvm_i64_ty, // Scalar offset
+                  llvm_i32_ty // Prfop
+                ],
+                [IntrInaccessibleMemOrArgMemOnly, ImmArg<3>]>;
+
 //
 // Loads
 //
 
 def int_aarch64_sve_ldnt1 : AdvSIMD_1Vec_PredLoad_Intrinsic;
-
-def int_aarch64_sve_ldnf1 : AdvSIMD_1Vec_PredFaultingLoad_Intrinsic;
-def int_aarch64_sve_ldff1 : AdvSIMD_1Vec_PredFaultingLoad_Intrinsic;
+def int_aarch64_sve_ldnf1 : AdvSIMD_1Vec_PredLoad_Intrinsic;
+def int_aarch64_sve_ldff1 : AdvSIMD_1Vec_PredLoad_Intrinsic;
 
 //
 // Stores
@@ -1279,13 +1293,39 @@ def int_aarch64_sve_ldff1 : AdvSIMD_1Vec_PredFaultingLoad_Intrinsic;
 def int_aarch64_sve_stnt1 : AdvSIMD_1Vec_PredStore_Intrinsic;
 
 //
-// Prefetch
+// Prefetches
 //
 
 def int_aarch64_sve_prf
   : Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i32_ty],
                   [IntrArgMemOnly, ImmArg<2>]>;
 
+// Scalar + 32-bit scaled offset vector, zero extend, packed and
+// unpacked.
+def int_aarch64_sve_gather_prfb_scaled_uxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfh_scaled_uxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfw_scaled_uxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfd_scaled_uxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+
+// Scalar + 32-bit scaled offset vector, sign extend, packed and
+// unpacked.
+def int_aarch64_sve_gather_prfb_scaled_sxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfw_scaled_sxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfh_scaled_sxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfd_scaled_sxtw : SVE_gather_prf_scalar_base_vector_offset_scaled;
+
+// Scalar + 64-bit scaled offset vector.
+def int_aarch64_sve_gather_prfb_scaled : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfh_scaled : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfw_scaled : SVE_gather_prf_scalar_base_vector_offset_scaled;
+def int_aarch64_sve_gather_prfd_scaled : SVE_gather_prf_scalar_base_vector_offset_scaled;
+
+// Vector + scalar.
+def int_aarch64_sve_gather_prfb : SVE_gather_prf_vector_base_scalar_offset;
+def int_aarch64_sve_gather_prfh : SVE_gather_prf_vector_base_scalar_offset;
+def int_aarch64_sve_gather_prfw : SVE_gather_prf_vector_base_scalar_offset;
+def int_aarch64_sve_gather_prfd : SVE_gather_prf_vector_base_scalar_offset;
+
 //
 // Scalar to vector operations
 //
diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td
index b35e1b7c44736..80ed0792a209c 100644
--- a/llvm/include/llvm/IR/IntrinsicsARM.td
+++ b/llvm/include/llvm/IR/IntrinsicsARM.td
@@ -1246,6 +1246,32 @@ def int_arm_mve_vqmovn_predicated: Intrinsic<[llvm_anyvector_ty],
 def int_arm_mve_fma_predicated: Intrinsic<[llvm_anyvector_ty],
    [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
     LLVMMatchType<0> /* addend */, llvm_anyvector_ty /* pred */], [IntrNoMem]>;
+def int_arm_mve_vmla_n_predicated: Intrinsic<[llvm_anyvector_ty],
+   [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
+    llvm_i32_ty /* mult op #2 (scalar) */, llvm_anyvector_ty /* pred */],
+   [IntrNoMem]>;
+def int_arm_mve_vmlas_n_predicated: Intrinsic<[llvm_anyvector_ty],
+   [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
+    llvm_i32_ty /* addend (scalar) */, llvm_anyvector_ty /* pred */],
+   [IntrNoMem]>;
+
+defm int_arm_mve_vqdmlah: MVEPredicated<[llvm_anyvector_ty],
+  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
+   llvm_i32_ty /* mult op #2 (scalar) */]>;
+defm int_arm_mve_vqrdmlah: MVEPredicated<[llvm_anyvector_ty],
+  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
+   llvm_i32_ty /* mult op #2 (scalar) */]>;
+defm int_arm_mve_vqdmlash: MVEPredicated<[llvm_anyvector_ty],
+  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
+   llvm_i32_ty /* addend (scalar) */]>;
+defm int_arm_mve_vqrdmlash: MVEPredicated<[llvm_anyvector_ty],
+  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
+   llvm_i32_ty /* addend (scalar) */]>;
+
+defm int_arm_mve_vqdmlad: MVEPredicated<[llvm_anyvector_ty],
+  [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
+   llvm_i32_ty /* exchange */, llvm_i32_ty /* round */,
+   llvm_i32_ty /* subtract */]>;
 
 // CDE (Custom Datapath Extension)
 
diff --git a/llvm/include/llvm/IR/KnowledgeRetention.h b/llvm/include/llvm/IR/KnowledgeRetention.h
index e5997bf3d28d2..f5c2d554c2305 100644
--- a/llvm/include/llvm/IR/KnowledgeRetention.h
+++ b/llvm/include/llvm/IR/KnowledgeRetention.h
@@ -115,6 +115,16 @@ inline RetainedKnowledge getKnowledgeFromUseInAssume(const Use *U) {
                                          U->getOperandNo());
 }
 
+/// Return true iff the operand bundles of the provided llvm.assume doesn't
+/// contain any valuable information. This is true when:
+///  - The operand bundle is empty
+///  - The operand bundle only contains information about dropped values or
+///    constant folded values.
+///
+/// the argument to the call of llvm.assume may still be useful even if the
+/// function returned true.
+bool isAssumeWithEmptyBundle(CallInst &Assume);
+
 //===----------------------------------------------------------------------===//
 // Utilities for testing
 //===----------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 6de57384fa3e4..fece1583da057 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -77,6 +77,7 @@ void initializeAssumptionCacheTrackerPass(PassRegistry&);
 void initializeAtomicExpandPass(PassRegistry&);
 void initializeAttributorLegacyPassPass(PassRegistry&);
 void initializeAttributorCGSCCLegacyPassPass(PassRegistry &);
+void initializeBBSectionsPreparePass(PassRegistry &);
 void initializeBDCELegacyPassPass(PassRegistry&);
 void initializeBarrierNoopPass(PassRegistry&);
 void initializeBasicAAWrapperPassPass(PassRegistry&);
diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h
index bf41420f2a5a6..f859d0c418a37 100644
--- a/llvm/include/llvm/MC/MCAsmBackend.h
+++ b/llvm/include/llvm/MC/MCAsmBackend.h
@@ -51,10 +51,10 @@ class MCAsmBackend {
   virtual bool allowAutoPadding() const { return false; }
 
   /// Give the target a chance to manipulate state related to instruction
-  /// alignment (e.g. padding for optimization) before and after actually
-  /// emitting the instruction.
-  virtual void alignBranchesBegin(MCObjectStreamer &OS, const MCInst &Inst) {}
-  virtual void alignBranchesEnd(MCObjectStreamer &OS, const MCInst &Inst) {}
+  /// alignment (e.g. padding for optimization), instruction relaxablility, etc.
+  /// before and after actually emitting the instruction.
+  virtual void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst) {}
+  virtual void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst) {}
 
   /// lifetime management
   virtual void reset() {}
diff --git a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
new file mode 100644
index 0000000000000..7a5edf78fdcc1
--- /dev/null
+++ b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
@@ -0,0 +1,54 @@
+//===-- MCTargetOptionsCommandFlags.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains machine code-specific flags that are shared between
+// different command line tools.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCTARGETOPTIONSCOMMANDFLAGS_H
+#define LLVM_MC_MCTARGETOPTIONSCOMMANDFLAGS_H
+
+#include "llvm/ADT/Optional.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/Support/CommandLine.h"
+
+namespace llvm {
+
+namespace mc {
+
+bool getRelaxAll();
+Optional<bool> getExplicitRelaxAll();
+
+bool getIncrementalLinkerCompatible();
+
+int getDwarfVersion();
+
+bool getShowMCInst();
+
+bool getFatalWarnings();
+
+bool getNoWarn();
+
+bool getNoDeprecatedWarn();
+
+std::string getABIName();
+
+/// Create this object with static storage to register mc-related command
+/// line options.
+struct RegisterMCTargetOptionsFlags {
+  RegisterMCTargetOptionsFlags();
+};
+
+MCTargetOptions InitMCTargetOptionsFromFlags();
+
+} // namespace mc
+
+} // namespace llvm
+
+#endif
diff --git a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.inc b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.inc
deleted file mode 100644
index 93e21b626eacc..0000000000000
--- a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.inc
+++ /dev/null
@@ -1,65 +0,0 @@
-//===-- MCTargetOptionsCommandFlags.h --------------------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains machine code-specific flags that are shared between
-// different command line tools.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_MC_MCTARGETOPTIONSCOMMANDFLAGS_H
-#define LLVM_MC_MCTARGETOPTIONSCOMMANDFLAGS_H
-
-#include "llvm/MC/MCTargetOptions.h"
-#include "llvm/Support/CommandLine.h"
-using namespace llvm;
-
-static cl::opt<bool> RelaxAll("mc-relax-all",
-                       cl::desc("When used with filetype=obj, "
-                                "relax all fixups in the emitted object file"));
-
-static cl::opt<bool> IncrementalLinkerCompatible(
-    "incremental-linker-compatible",
-    cl::desc(
-        "When used with filetype=obj, "
-        "emit an object file which can be used with an incremental linker"));
-
-static cl::opt<int> DwarfVersion("dwarf-version", cl::desc("Dwarf version"),
-                          cl::init(0));
-
-static cl::opt<bool> ShowMCInst("asm-show-inst",
-                         cl::desc("Emit internal instruction representation to "
-                                  "assembly file"));
-
-static cl::opt<bool> FatalWarnings("fatal-warnings",
-                            cl::desc("Treat warnings as errors"));
-
-static cl::opt<bool> NoWarn("no-warn", cl::desc("Suppress all warnings"));
-static cl::alias NoWarnW("W", cl::desc("Alias for --no-warn"), cl::aliasopt(NoWarn));
-
-static cl::opt<bool> NoDeprecatedWarn("no-deprecated-warn",
-                               cl::desc("Suppress all deprecated warnings"));
-
-static cl::opt<std::string>
-ABIName("target-abi", cl::Hidden,
-        cl::desc("The name of the ABI to be targeted from the backend."),
-        cl::init(""));
-
-static MCTargetOptions InitMCTargetOptionsFromFlags() {
-  MCTargetOptions Options;
-  Options.MCRelaxAll = RelaxAll;
-  Options.MCIncrementalLinkerCompatible = IncrementalLinkerCompatible;
-  Options.DwarfVersion = DwarfVersion;
-  Options.ShowMCInst = ShowMCInst;
-  Options.ABIName = ABIName;
-  Options.MCFatalWarnings = FatalWarnings;
-  Options.MCNoWarn = NoWarn;
-  Options.MCNoDeprecatedWarn = NoDeprecatedWarn;
-  return Options;
-}
-
-#endif
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h
index 59b99d0889217..e2c9b42e04b42 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -1060,59 +1060,59 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
   case ELF::ELFCLASS32:
     switch (EF.getHeader()->e_machine) {
     case ELF::EM_386:
-      return "ELF32-i386";
+      return "elf32-i386";
     case ELF::EM_IAMCU:
-      return "ELF32-iamcu";
+      return "elf32-iamcu";
     case ELF::EM_X86_64:
-      return "ELF32-x86-64";
+      return "elf32-x86-64";
     case ELF::EM_ARM:
-      return (IsLittleEndian ? "ELF32-arm-little" : "ELF32-arm-big");
+      return (IsLittleEndian ? "elf32-littlearm" : "elf32-bigarm");
     case ELF::EM_AVR:
-      return "ELF32-avr";
+      return "elf32-avr";
     case ELF::EM_HEXAGON:
-      return "ELF32-hexagon";
+      return "elf32-hexagon";
     case ELF::EM_LANAI:
-      return "ELF32-lanai";
+      return "elf32-lanai";
     case ELF::EM_MIPS:
-      return "ELF32-mips";
+      return "elf32-mips";
     case ELF::EM_MSP430:
-      return "ELF32-msp430";
+      return "elf32-msp430";
     case ELF::EM_PPC:
-      return "ELF32-ppc";
+      return "elf32-powerpc";
     case ELF::EM_RISCV:
-      return "ELF32-riscv";
+      return "elf32-littleriscv";
     case ELF::EM_SPARC:
     case ELF::EM_SPARC32PLUS:
-      return "ELF32-sparc";
+      return "elf32-sparc";
     case ELF::EM_AMDGPU:
-      return "ELF32-amdgpu";
+      return "elf32-amdgpu";
     default:
-      return "ELF32-unknown";
+      return "elf32-unknown";
     }
   case ELF::ELFCLASS64:
     switch (EF.getHeader()->e_machine) {
     case ELF::EM_386:
-      return "ELF64-i386";
+      return "elf64-i386";
     case ELF::EM_X86_64:
-      return "ELF64-x86-64";
+      return "elf64-x86-64";
     case ELF::EM_AARCH64:
-      return (IsLittleEndian ? "ELF64-aarch64-little" : "ELF64-aarch64-big");
+      return (IsLittleEndian ? "elf64-littleaarch64" : "elf64-bigaarch64");
     case ELF::EM_PPC64:
-      return "ELF64-ppc64";
+      return "elf64-powerpc";
     case ELF::EM_RISCV:
-      return "ELF64-riscv";
+      return "elf64-littleriscv";
     case ELF::EM_S390:
-      return "ELF64-s390";
+      return "elf64-s390";
     case ELF::EM_SPARCV9:
-      return "ELF64-sparc";
+      return "elf64-sparc";
     case ELF::EM_MIPS:
-      return "ELF64-mips";
+      return "elf64-mips";
     case ELF::EM_AMDGPU:
-      return "ELF64-amdgpu";
+      return "elf64-amdgpu";
     case ELF::EM_BPF:
-      return "ELF64-BPF";
+      return "elf64-bpf";
     default:
-      return "ELF64-unknown";
+      return "elf64-unknown";
     }
   default:
     // FIXME: Proper error handling.
diff --git a/llvm/include/llvm/ObjectYAML/ELFYAML.h b/llvm/include/llvm/ObjectYAML/ELFYAML.h
index 60bb2375901bd..44f5d7cd069ed 100644
--- a/llvm/include/llvm/ObjectYAML/ELFYAML.h
+++ b/llvm/include/llvm/ObjectYAML/ELFYAML.h
@@ -65,6 +65,7 @@ LLVM_YAML_STRONG_TYPEDEF(uint32_t, MIPS_AFL_FLAGS1)
 LLVM_YAML_STRONG_TYPEDEF(uint32_t, MIPS_ISA)
 
 LLVM_YAML_STRONG_TYPEDEF(StringRef, YAMLFlowString)
+LLVM_YAML_STRONG_TYPEDEF(int64_t, YAMLIntUInt)
 
 // For now, hardcode 64 bits everywhere that 32 or 64 would be needed
 // since 64-bit can hold 32-bit values too.
@@ -439,7 +440,7 @@ struct Group : Section {
 
 struct Relocation {
   llvm::yaml::Hex64 Offset;
-  int64_t Addend;
+  YAMLIntUInt Addend;
   ELF_REL Type;
   Optional<StringRef> Symbol;
 };
@@ -542,6 +543,14 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::SectionName)
 namespace llvm {
 namespace yaml {
 
+template <> struct ScalarTraits<ELFYAML::YAMLIntUInt> {
+  static void output(const ELFYAML::YAMLIntUInt &Val, void *Ctx,
+                     raw_ostream &Out);
+  static StringRef input(StringRef Scalar, void *Ctx,
+                         ELFYAML::YAMLIntUInt &Val);
+  static QuotingType mustQuote(StringRef) { return QuotingType::None; }
+};
+
 template <>
 struct ScalarEnumerationTraits<ELFYAML::ELF_ET> {
   static void enumeration(IO &IO, ELFYAML::ELF_ET &Value);
diff --git a/llvm/include/llvm/Support/Alignment.h b/llvm/include/llvm/Support/Alignment.h
index 05cf82f0def12..cf5f151b51997 100644
--- a/llvm/include/llvm/Support/Alignment.h
+++ b/llvm/include/llvm/Support/Alignment.h
@@ -164,17 +164,34 @@ inline bool isAddrAligned(Align Lhs, const void *Addr) {
 
 /// Returns a multiple of A needed to store `Size` bytes.
 inline uint64_t alignTo(uint64_t Size, Align A) {
-  const uint64_t value = A.value();
-  // The following line is equivalent to `(Size + value - 1) / value * value`.
+  const uint64_t Value = A.value();
+  // The following line is equivalent to `(Size + Value - 1) / Value * Value`.
 
   // The division followed by a multiplication can be thought of as a right
   // shift followed by a left shift which zeros out the extra bits produced in
-  // the bump; `~(value - 1)` is a mask where all those bits being zeroed out
+  // the bump; `~(Value - 1)` is a mask where all those bits being zeroed out
   // are just zero.
 
   // Most compilers can generate this code but the pattern may be missed when
   // multiple functions gets inlined.
-  return (Size + value - 1) & ~(value - 1);
+  return (Size + Value - 1) & ~(Value - 1U);
+}
+
+/// If non-zero \p Skew is specified, the return value will be a minimal integer
+/// that is greater than or equal to \p Size and equal to \p A * N + \p Skew for
+/// some integer N. If \p Skew is larger than \p A, its value is adjusted to '\p
+/// Skew mod \p A'.
+///
+/// Examples:
+/// \code
+///   alignTo(5, Align(8), 7) = 7
+///   alignTo(17, Align(8), 1) = 17
+///   alignTo(~0LL, Align(8), 3) = 3
+/// \endcode
+inline uint64_t alignTo(uint64_t Size, Align A, uint64_t Skew) {
+  const uint64_t Value = A.value();
+  Skew %= Value;
+  return ((Size + Value - 1 - Skew) & ~(Value - 1U)) + Skew;
 }
 
 /// Returns a multiple of A needed to store `Size` bytes.
diff --git a/llvm/include/llvm/Support/GenericDomTreeConstruction.h b/llvm/include/llvm/Support/GenericDomTreeConstruction.h
index 7c0278e8770ee..571550012374c 100644
--- a/llvm/include/llvm/Support/GenericDomTreeConstruction.h
+++ b/llvm/include/llvm/Support/GenericDomTreeConstruction.h
@@ -7,11 +7,11 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// Generic dominator tree construction - This file provides routines to
+/// Generic dominator tree construction - this file provides routines to
 /// construct immediate dominator information for a flow-graph based on the
 /// Semi-NCA algorithm described in this dissertation:
 ///
-///   Linear-Time Algorithms for Dominators and Related Problems
+///   [1] Linear-Time Algorithms for Dominators and Related Problems
 ///   Loukas Georgiadis, Princeton University, November 2005, pp. 21-23:
 ///   ftp://ftp.cs.princeton.edu/reports/2005/737.pdf
 ///
@@ -20,13 +20,15 @@
 ///
 /// O(n^2) worst cases happen when the computation of nearest common ancestors
 /// requires O(n) average time, which is very unlikely in real world. If this
-/// ever turns out to be an issue, consider implementing a hybrid algorithm.
+/// ever turns out to be an issue, consider implementing a hybrid algorithm
+/// that uses SLT to perform full constructions and SemiNCA for incremental
+/// updates.
 ///
 /// The file uses the Depth Based Search algorithm to perform incremental
 /// updates (insertion and deletions). The implemented algorithm is based on
 /// this publication:
 ///
-///   An Experimental Study of Dynamic Dominators
+///   [2] An Experimental Study of Dynamic Dominators
 ///   Loukas Georgiadis, et al., April 12 2016, pp. 5-7, 9-10:
 ///   https://arxiv.org/pdf/1604.02711.pdf
 ///
@@ -732,7 +734,7 @@ struct SemiNCAInfo {
       LLVM_DEBUG(dbgs() << "Roots are different in updated trees\n"
                         << "The entire tree needs to be rebuilt\n");
       // It may be possible to update the tree without recalculating it, but
-      // we do not know yet how to do it, and it happens rarely in practise.
+      // we do not know yet how to do it, and it happens rarely in practice.
       CalculateFromScratch(DT, BUI);
     }
   }
@@ -757,13 +759,13 @@ struct SemiNCAInfo {
     LLVM_DEBUG(dbgs() << "\t\tNCA == " << BlockNamePrinter(NCD) << "\n");
     const unsigned NCDLevel = NCD->getLevel();
 
-    // Based on Lemma 2.5 from the second paper, after insertion of (From,To), v
-    // is affected iff depth(NCD)+1 < depth(v) && a path P from To to v exists
-    // where every w on P s.t. depth(v) <= depth(w)
+    // Based on Lemma 2.5 from [2], after insertion of (From,To), v is affected
+    // iff depth(NCD)+1 < depth(v) && a path P from To to v exists where every
+    // w on P s.t. depth(v) <= depth(w)
     //
     // This reduces to a widest path problem (maximizing the depth of the
     // minimum vertex in the path) which can be solved by a modified version of
-    // Dijkstra with a bucket queue (named depth-based search in the paper).
+    // Dijkstra with a bucket queue (named depth-based search in [2]).
 
     // To is in the path, so depth(NCD)+1 < depth(v) <= depth(To). Nothing
     // affected if this does not hold.
@@ -957,7 +959,7 @@ struct SemiNCAInfo {
                         << BlockNamePrinter(ToIDom) << "\n");
 
       // To remains reachable after deletion.
-      // (Based on the caption under Figure 4. from the second paper.)
+      // (Based on the caption under Figure 4. from [2].)
       if (FromTN != ToIDom || HasProperSupport(DT, BUI, ToTN))
         DeleteReachable(DT, BUI, FromTN, ToTN);
       else
@@ -976,7 +978,7 @@ struct SemiNCAInfo {
     LLVM_DEBUG(dbgs() << "\tRebuilding subtree\n");
 
     // Find the top of the subtree that needs to be rebuilt.
-    // (Based on the lemma 2.6 from the second paper.)
+    // (Based on the lemma 2.6 from [2].)
     const NodePtr ToIDom =
         DT.findNearestCommonDominator(FromTN->getBlock(), ToTN->getBlock());
     assert(ToIDom || DT.isPostDominator());
@@ -1008,7 +1010,7 @@ struct SemiNCAInfo {
   }
 
   // Checks if a node has proper support, as defined on the page 3 and later
-  // explained on the page 7 of the second paper.
+  // explained on the page 7 of [2].
   static bool HasProperSupport(DomTreeT &DT, const BatchUpdatePtr BUI,
                                const TreeNodePtr TN) {
     LLVM_DEBUG(dbgs() << "IsReachableFromIDom " << BlockNamePrinter(TN)
@@ -1033,7 +1035,7 @@ struct SemiNCAInfo {
   }
 
   // Handle deletions that make destination node unreachable.
-  // (Based on the lemma 2.7 from the second paper.)
+  // (Based on the lemma 2.7 from the [2].)
   static void DeleteUnreachable(DomTreeT &DT, const BatchUpdatePtr BUI,
                                 const TreeNodePtr ToTN) {
     LLVM_DEBUG(dbgs() << "Deleting unreachable subtree "
@@ -1493,9 +1495,9 @@ struct SemiNCAInfo {
   // LEFT, and thus, LEFT is really an ancestor (in the dominator tree) of
   // RIGHT, not a sibling.
 
-  // It is possible to verify the parent and sibling properties in
-  // linear time, but the algorithms are complex. Instead, we do it in a
-  // straightforward N^2 and N^3 way below, using direct path reachability.
+  // It is possible to verify the parent and sibling properties in linear time,
+  // but the algorithms are complex. Instead, we do it in a straightforward
+  // N^2 and N^3 way below, using direct path reachability.
 
   // Checks if the tree has the parent property: if for all edges from V to W in
   // the input graph, such that V is reachable, the parent of W in the tree is
@@ -1571,7 +1573,7 @@ struct SemiNCAInfo {
 
   // Check if the given tree is the same as a freshly computed one for the same
   // Parent.
-  // Running time: O(N^2), but faster in practise (same as tree construction).
+  // Running time: O(N^2), but faster in practice (same as tree construction).
   //
   // Note that this does not check if that the tree construction algorithm is
   // correct and should be only used for fast (but possibly unsound)
@@ -1648,12 +1650,12 @@ bool Verify(const DomTreeT &DT, typename DomTreeT::VerificationLevel VL) {
   if (!SNCA.IsSameAsFreshTree(DT))
     return false;
 
-  // Common checks to verify the properties of the tree. O(N log N) at worst
+  // Common checks to verify the properties of the tree. O(N log N) at worst.
   if (!SNCA.verifyRoots(DT) || !SNCA.verifyReachability(DT) ||
       !SNCA.VerifyLevels(DT) || !SNCA.VerifyDFSNumbers(DT))
     return false;
 
-  // Extra checks depending on VerificationLevel. Up to O(N^3)
+  // Extra checks depending on VerificationLevel. Up to O(N^3).
   if (VL == DomTreeT::VerificationLevel::Basic ||
       VL == DomTreeT::VerificationLevel::Full)
     if (!SNCA.verifyParentProperty(DT))
diff --git a/llvm/include/llvm/Support/TypeSize.h b/llvm/include/llvm/Support/TypeSize.h
index 253190c08a04c..d800317204223 100644
--- a/llvm/include/llvm/Support/TypeSize.h
+++ b/llvm/include/llvm/Support/TypeSize.h
@@ -15,6 +15,8 @@
 #ifndef LLVM_SUPPORT_TYPESIZE_H
 #define LLVM_SUPPORT_TYPESIZE_H
 
+#include "llvm/Support/WithColor.h"
+
 #include <cstdint>
 #include <cassert>
 
@@ -146,10 +148,32 @@ class TypeSize {
 
   // Casts to a uint64_t if this is a fixed-width size.
   //
-  // NOTE: This interface is obsolete and will be removed in a future version
-  // of LLVM in favour of calling getFixedSize() directly.
+  // This interface is deprecated and will be removed in a future version
+  // of LLVM in favour of upgrading uses that rely on this implicit conversion
+  // to uint64_t. Calls to functions that return a TypeSize should use the
+  // proper interfaces to TypeSize.
+  // In practice this is mostly calls to MVT/EVT::getSizeInBits().
+  //
+  // To determine how to upgrade the code:
+  //
+  //   if (<algorithm works for both scalable and fixed-width vectors>)
+  //     use getKnownMinSize()
+  //   else if (<algorithm works only for fixed-width vectors>) {
+  //     if <algorithm can be adapted for both scalable and fixed-width vectors>
+  //       update the algorithm and use getKnownMinSize()
+  //     else
+  //       bail out early for scalable vectors and use getFixedSize()
+  //   }
   operator uint64_t() const {
+#ifdef STRICT_IMPLICIT_CONVERSION_TYPESIZE
     return getFixedSize();
+#else
+    if (isScalable())
+      WithColor::warning() << "Compiler has made implicit assumption that "
+                              "TypeSize is not scalable. This may or may not "
+                              "lead to broken code.\n";
+    return getKnownMinSize();
+#endif
   }
 
   // Additional convenience operators needed to avoid ambiguous parses.
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 6a34e9f9fc15f..baa31d0a09e5f 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -142,7 +142,34 @@ def mul_to_shl : GICombineRule<
          [{ return Helper.matchCombineMulToShl(*${mi}, ${matchinfo}); }]),
   (apply [{ Helper.applyCombineMulToShl(*${mi}, ${matchinfo}); }])>;
 
+// [us]itofp(undef) = 0, because the result value is bounded.
+def undef_to_fp_zero : GICombineRule<
+  (defs root:$root),
+  (match (wip_match_opcode G_UITOFP, G_SITOFP):$root,
+         [{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]),
+  (apply [{ Helper.replaceInstWithFConstant(*${root}, 0.0); }])>;
+
+def undef_to_int_zero: GICombineRule<
+  (defs root:$root),
+  (match (wip_match_opcode G_AND, G_MUL):$root,
+         [{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]),
+  (apply [{ Helper.replaceInstWithConstant(*${root}, 0); }])>;
+
+def undef_to_negative_one: GICombineRule<
+  (defs root:$root),
+  (match (wip_match_opcode G_OR):$root,
+         [{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]),
+  (apply [{ Helper.replaceInstWithConstant(*${root}, -1); }])>;
+
+def propagate_undef: GICombineRule<
+  (defs root:$root),
+  (match (wip_match_opcode G_ADD, G_FPTOSI, G_FPTOUI, G_SUB, G_XOR):$root,
+         [{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]),
+  (apply [{ Helper.replaceInstWithUndef(*${root}); }])>;
+
+def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
+                                     undef_to_negative_one, propagate_undef]>;
+
 def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl]>;
 def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain,
-    combines_for_extload, combine_indexed_load_store]>;
-
+    combines_for_extload, combine_indexed_load_store, undef_combines]>;
diff --git a/llvm/include/llvm/Target/TargetLoweringObjectFile.h b/llvm/include/llvm/Target/TargetLoweringObjectFile.h
index a13b09682a3a6..2a5ac9a4de9a0 100644
--- a/llvm/include/llvm/Target/TargetLoweringObjectFile.h
+++ b/llvm/include/llvm/Target/TargetLoweringObjectFile.h
@@ -24,6 +24,7 @@
 namespace llvm {
 
 class GlobalValue;
+class MachineBasicBlock;
 class MachineModuleInfo;
 class Mangler;
 class MCContext;
@@ -90,6 +91,15 @@ class TargetLoweringObjectFile : public MCObjectFileInfo {
                                            const Constant *C,
                                            unsigned &Align) const;
 
+  virtual MCSection *
+  getSectionForMachineBasicBlock(const Function &F,
+                                 const MachineBasicBlock &MBB,
+                                 const TargetMachine &TM) const;
+
+  virtual MCSection *getNamedSectionForMachineBasicBlock(
+      const Function &F, const MachineBasicBlock &MBB, const TargetMachine &TM,
+      const char *Suffix) const;
+
   /// Classify the specified global variable into a set of target independent
   /// categories embodied in SectionKind.
   static SectionKind getKindForGlobal(const GlobalObject *GO,
diff --git a/llvm/include/llvm/module.modulemap b/llvm/include/llvm/module.modulemap
index c099b78b169cd..3c8639992fdd4 100644
--- a/llvm/include/llvm/module.modulemap
+++ b/llvm/include/llvm/module.modulemap
@@ -29,7 +29,6 @@ module LLVM_Backend {
     exclude header "CodeGen/LinkAllCodegenComponents.h"
 
     // These are intended for (repeated) textual inclusion.
-    textual header "CodeGen/CommandFlags.inc"
     textual header "CodeGen/DIEValue.def"
   }
 }
@@ -317,8 +316,6 @@ module LLVM_MC {
 
   umbrella "MC"
   module * { export * }
-
-  textual header "MC/MCTargetOptionsCommandFlags.inc"
 }
 
 // Used by llvm-tblgen
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index bc9ae5ebffb01..1e4d7f7117851 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4081,13 +4081,16 @@ static Value *SimplifyGEPInst(Type *SrcTy, ArrayRef<Value *> Ops,
   if (isa<UndefValue>(Ops[0]))
     return UndefValue::get(GEPTy);
 
+  bool IsScalableVec =
+      SrcTy->isVectorTy() ? SrcTy->getVectorIsScalable() : false;
+
   if (Ops.size() == 2) {
     // getelementptr P, 0 -> P.
     if (match(Ops[1], m_Zero()) && Ops[0]->getType() == GEPTy)
       return Ops[0];
 
     Type *Ty = SrcTy;
-    if (Ty->isSized()) {
+    if (!IsScalableVec && Ty->isSized()) {
       Value *P;
       uint64_t C;
       uint64_t TyAllocSize = Q.DL.getTypeAllocSize(Ty);
@@ -4135,7 +4138,7 @@ static Value *SimplifyGEPInst(Type *SrcTy, ArrayRef<Value *> Ops,
     }
   }
 
-  if (Q.DL.getTypeAllocSize(LastType) == 1 &&
+  if (!IsScalableVec && Q.DL.getTypeAllocSize(LastType) == 1 &&
       all_of(Ops.slice(1).drop_back(1),
              [](Value *Idx) { return match(Idx, m_Zero()); })) {
     unsigned IdxWidth =
@@ -5358,9 +5361,6 @@ Value *llvm::SimplifyCall(CallBase *Call, const SimplifyQuery &Q) {
     if (Value *Ret = simplifyIntrinsic(Call, Q))
       return Ret;
 
-  if (Value *ReturnedArg = Call->getReturnedArgOperand())
-    return ReturnedArg;
-
   if (!canConstantFoldCallTo(Call, F))
     return nullptr;
 
diff --git a/llvm/lib/Analysis/MemoryBuiltins.cpp b/llvm/lib/Analysis/MemoryBuiltins.cpp
index 427e6fd3ace24..be0feeb9237e9 100644
--- a/llvm/lib/Analysis/MemoryBuiltins.cpp
+++ b/llvm/lib/Analysis/MemoryBuiltins.cpp
@@ -633,6 +633,10 @@ SizeOffsetType ObjectSizeOffsetVisitor::visitAllocaInst(AllocaInst &I) {
   if (!I.getAllocatedType()->isSized())
     return unknown();
 
+  if (I.getAllocatedType()->isVectorTy() &&
+      I.getAllocatedType()->getVectorIsScalable())
+    return unknown();
+
   APInt Size(IntTyBits, DL.getTypeAllocSize(I.getAllocatedType()));
   if (!I.isArrayAllocation())
     return std::make_pair(align(Size, I.getAlignment()), Zero);
diff --git a/llvm/lib/Analysis/ScalarEvolutionExpander.cpp b/llvm/lib/Analysis/ScalarEvolutionExpander.cpp
index 67d0a026064ca..5ffdb0b10d447 100644
--- a/llvm/lib/Analysis/ScalarEvolutionExpander.cpp
+++ b/llvm/lib/Analysis/ScalarEvolutionExpander.cpp
@@ -2137,7 +2137,8 @@ SCEVExpander::getRelatedExistingExpansion(const SCEV *S, const Instruction *At,
 
 bool SCEVExpander::isHighCostExpansionHelper(
     const SCEV *S, Loop *L, const Instruction &At, int &BudgetRemaining,
-    const TargetTransformInfo &TTI, SmallPtrSetImpl<const SCEV *> &Processed) {
+    const TargetTransformInfo &TTI, SmallPtrSetImpl<const SCEV *> &Processed,
+    SmallVectorImpl<const SCEV *> &Worklist) {
   if (BudgetRemaining < 0)
     return true; // Already run out of budget, give up.
 
@@ -2172,13 +2173,12 @@ bool SCEVExpander::isHighCostExpansionHelper(
       llvm_unreachable("There are no other cast types.");
     }
     const SCEV *Op = CastExpr->getOperand();
-    BudgetRemaining -=
-        TTI.getCastInstrCost(Opcode, S->getType(), Op->getType());
-    return isHighCostExpansionHelper(Op, L, At, BudgetRemaining, TTI,
-                                     Processed);
+    BudgetRemaining -= TTI.getCastInstrCost(Opcode, /*Dst=*/S->getType(),
+                                            /*Src=*/Op->getType());
+    Worklist.emplace_back(Op);
+    return false; // Will answer upon next entry into this function.
   }
 
-
   if (auto *UDivExpr = dyn_cast<SCEVUDivExpr>(S)) {
     // If the divisor is a power of two count this as a logical right-shift.
     if (auto *SC = dyn_cast<SCEVConstant>(UDivExpr->getRHS())) {
@@ -2188,8 +2188,8 @@ bool SCEVExpander::isHighCostExpansionHelper(
         // Note that we don't count the cost of RHS, because it is a constant,
         // and we consider those to be free. But if that changes, we would need
         // to log2() it first before calling isHighCostExpansionHelper().
-        return isHighCostExpansionHelper(UDivExpr->getLHS(), L, At,
-                                         BudgetRemaining, TTI, Processed);
+        Worklist.emplace_back(UDivExpr->getLHS());
+        return false; // Will answer upon next entry into this function.
       }
     }
 
@@ -2208,10 +2208,8 @@ bool SCEVExpander::isHighCostExpansionHelper(
     // Need to count the cost of this UDiv.
     BudgetRemaining -=
         TTI.getArithmeticInstrCost(Instruction::UDiv, S->getType());
-    return isHighCostExpansionHelper(UDivExpr->getLHS(), L, At, BudgetRemaining,
-                                     TTI, Processed) ||
-           isHighCostExpansionHelper(UDivExpr->getRHS(), L, At, BudgetRemaining,
-                                     TTI, Processed);
+    Worklist.insert(Worklist.end(), {UDivExpr->getLHS(), UDivExpr->getRHS()});
+    return false; // Will answer upon next entry into this function.
   }
 
   if (const auto *NAry = dyn_cast<SCEVAddRecExpr>(S)) {
@@ -2264,12 +2262,9 @@ bool SCEVExpander::isHighCostExpansionHelper(
       return true;
 
     // And finally, the operands themselves should fit within the budget.
-    for (const SCEV *Op : NAry->operands()) {
-      if (isHighCostExpansionHelper(Op, L, At, BudgetRemaining, TTI, Processed))
-        return true;
-    }
-
-    return BudgetRemaining < 0;
+    Worklist.insert(Worklist.end(), NAry->operands().begin(),
+                    NAry->operands().end());
+    return false; // So far so good, though ops may be too costly?
   }
 
   if (const SCEVNAryExpr *NAry = dyn_cast<SCEVNAryExpr>(S)) {
@@ -2301,15 +2296,16 @@ bool SCEVExpander::isHighCostExpansionHelper(
 
     assert(NAry->getNumOperands() > 1 &&
            "Nary expr should have more than 1 operand.");
-    for (const SCEV *Op : NAry->operands()) {
-      if (isHighCostExpansionHelper(Op, L, At, BudgetRemaining, TTI, Processed))
-        return true;
-      if (Op == *NAry->op_begin())
-        continue;
-      BudgetRemaining -= PairCost;
-    }
+    // The simple nary expr will require one less op (or pair of ops)
+    // than the number of it's terms.
+    BudgetRemaining -= PairCost * (NAry->getNumOperands() - 1);
+    if (BudgetRemaining < 0)
+      return true;
 
-    return BudgetRemaining < 0;
+    // And finally, the operands themselves should fit within the budget.
+    Worklist.insert(Worklist.end(), NAry->operands().begin(),
+                    NAry->operands().end());
+    return false; // So far so good, though ops may be too costly?
   }
 
   llvm_unreachable("No other scev expressions possible.");
diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp
index 33a326e4a86fc..3af1cec9d0182 100644
--- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp
+++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp
@@ -99,11 +99,11 @@ raw_ostream &operator<<(raw_ostream &OS, const UseInfo &U) {
 }
 
 struct AllocaInfo {
-  const AllocaInst *AI = nullptr;
+  AllocaInst *AI = nullptr;
   uint64_t Size = 0;
   UseInfo Use;
 
-  AllocaInfo(unsigned PointerSize, const AllocaInst *AI, uint64_t Size)
+  AllocaInfo(unsigned PointerSize, AllocaInst *AI, uint64_t Size)
       : AI(AI), Size(Size), Use(PointerSize) {}
 
   StringRef getName() const { return AI->getName(); }
@@ -205,7 +205,7 @@ StackSafetyInfo::FunctionInfo::FunctionInfo(const GlobalAlias *A) : GV(A) {
 namespace {
 
 class StackSafetyLocalAnalysis {
-  const Function &F;
+  Function &F;
   const DataLayout &DL;
   ScalarEvolution &SE;
   unsigned PointerSize = 0;
@@ -227,7 +227,7 @@ class StackSafetyLocalAnalysis {
   }
 
 public:
-  StackSafetyLocalAnalysis(const Function &F, ScalarEvolution &SE)
+  StackSafetyLocalAnalysis(Function &F, ScalarEvolution &SE)
       : F(F), DL(F.getParent()->getDataLayout()), SE(SE),
         PointerSize(DL.getPointerSizeInBits()),
         UnknownRange(PointerSize, true) {}
@@ -653,17 +653,47 @@ PreservedAnalyses StackSafetyGlobalPrinterPass::run(Module &M,
   return PreservedAnalyses::all();
 }
 
+static bool SetStackSafetyMetadata(Module &M,
+                                   const StackSafetyGlobalInfo &SSGI) {
+  bool Changed = false;
+  unsigned Width = M.getDataLayout().getPointerSizeInBits();
+  for (auto &F : M.functions()) {
+    if (F.isDeclaration() || F.hasOptNone())
+      continue;
+    auto Iter = SSGI.find(&F);
+    if (Iter == SSGI.end())
+      continue;
+    StackSafetyInfo::FunctionInfo *Summary = Iter->second.getInfo();
+    for (auto &AS : Summary->Allocas) {
+      ConstantRange AllocaRange{APInt(Width, 0), APInt(Width, AS.Size)};
+      if (AllocaRange.contains(AS.Use.Range)) {
+        AS.AI->setMetadata(M.getMDKindID("stack-safe"),
+                           MDNode::get(M.getContext(), None));
+        Changed = true;
+      }
+    }
+  }
+  return Changed;
+}
+
+PreservedAnalyses
+StackSafetyGlobalAnnotatorPass::run(Module &M, ModuleAnalysisManager &AM) {
+  auto &SSGI = AM.getResult<StackSafetyGlobalAnalysis>(M);
+  (void)SetStackSafetyMetadata(M, SSGI);
+  return PreservedAnalyses::all();
+}
+
 char StackSafetyGlobalInfoWrapperPass::ID = 0;
 
-StackSafetyGlobalInfoWrapperPass::StackSafetyGlobalInfoWrapperPass()
-    : ModulePass(ID) {
+StackSafetyGlobalInfoWrapperPass::StackSafetyGlobalInfoWrapperPass(bool SetMetadata)
+    : ModulePass(ID), SetMetadata(SetMetadata) {
   initializeStackSafetyGlobalInfoWrapperPassPass(
       *PassRegistry::getPassRegistry());
 }
 
 void StackSafetyGlobalInfoWrapperPass::print(raw_ostream &O,
                                              const Module *M) const {
-  ::print(SSI, O, *M);
+  ::print(SSGI, O, *M);
 }
 
 void StackSafetyGlobalInfoWrapperPass::getAnalysisUsage(
@@ -676,8 +706,12 @@ bool StackSafetyGlobalInfoWrapperPass::runOnModule(Module &M) {
       M, [this](Function &F) -> const StackSafetyInfo & {
         return getAnalysis<StackSafetyInfoWrapperPass>(F).getResult();
       });
-  SSI = SSDFA.run();
-  return false;
+  SSGI = SSDFA.run();
+  return SetMetadata ? SetStackSafetyMetadata(M, SSGI) : false;
+}
+
+ModulePass *llvm::createStackSafetyGlobalInfoWrapperPass(bool SetMetadata) {
+  return new StackSafetyGlobalInfoWrapperPass(SetMetadata);
 }
 
 static const char LocalPassArg[] = "stack-safety-local";
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index a1b30fc8f12b1..89b1783a9a007 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -776,16 +776,23 @@ Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
 
 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
                                                      Value *Length,
+                                                     unsigned SrcAddrSpace,
+                                                     unsigned DestAddrSpace,
                                                      unsigned SrcAlign,
                                                      unsigned DestAlign) const {
-  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
+  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
+                                            DestAddrSpace, SrcAlign,
                                             DestAlign);
 }
 
 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
-    unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
+    unsigned RemainingBytes,
+    unsigned SrcAddrSpace,
+    unsigned DestAddrSpace,
+    unsigned SrcAlign, unsigned DestAlign) const {
   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
+                                             SrcAddrSpace, DestAddrSpace,
                                              SrcAlign, DestAlign);
 }
 
diff --git a/llvm/lib/Analysis/ValueLattice.cpp b/llvm/lib/Analysis/ValueLattice.cpp
index eaf8885cc14ec..1a15605ce1e13 100644
--- a/llvm/lib/Analysis/ValueLattice.cpp
+++ b/llvm/lib/Analysis/ValueLattice.cpp
@@ -19,6 +19,12 @@ raw_ostream &operator<<(raw_ostream &OS, const ValueLatticeElement &Val) {
 
   if (Val.isNotConstant())
     return OS << "notconstant<" << *Val.getNotConstant() << ">";
+
+  if (Val.isSingleCRFromUndef())
+    return OS << "constantrange (from undef)<"
+              << Val.getConstantRange().getLower() << ", "
+              << Val.getConstantRange().getUpper() << ">";
+
   if (Val.isConstantRange())
     return OS << "constantrange<" << Val.getConstantRange().getLower() << ", "
               << Val.getConstantRange().getUpper() << ">";
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 1a2253050152d..f1adc037d17f0 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -1104,8 +1104,8 @@ static void computeKnownBitsFromOperator(const Operator *I,
     break;
   case Instruction::And: {
     // If either the LHS or the RHS are Zero, the result is zero.
-    computeKnownBits(I->getOperand(1), Known, Depth + 1, Q);
-    computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q);
+    computeKnownBits(I->getOperand(1), DemandedElts, Known, Depth + 1, Q);
+    computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
 
     // Output known-1 bits are only known if set in both the LHS & RHS.
     Known.One &= Known2.One;
@@ -1128,8 +1128,8 @@ static void computeKnownBitsFromOperator(const Operator *I,
     break;
   }
   case Instruction::Or:
-    computeKnownBits(I->getOperand(1), Known, Depth + 1, Q);
-    computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q);
+    computeKnownBits(I->getOperand(1), DemandedElts, Known, Depth + 1, Q);
+    computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
 
     // Output known-0 bits are only known if clear in both the LHS & RHS.
     Known.Zero &= Known2.Zero;
@@ -1137,8 +1137,8 @@ static void computeKnownBitsFromOperator(const Operator *I,
     Known.One |= Known2.One;
     break;
   case Instruction::Xor: {
-    computeKnownBits(I->getOperand(1), Known, Depth + 1, Q);
-    computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q);
+    computeKnownBits(I->getOperand(1), DemandedElts, Known, Depth + 1, Q);
+    computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
 
     // Output known-0 bits are known if clear or set in both the LHS & RHS.
     APInt KnownZeroOut = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
@@ -1605,12 +1605,12 @@ static void computeKnownBitsFromOperator(const Operator *I,
       switch (II->getIntrinsicID()) {
       default: break;
       case Intrinsic::bitreverse:
-        computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q);
+        computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
         Known.Zero |= Known2.Zero.reverseBits();
         Known.One |= Known2.One.reverseBits();
         break;
       case Intrinsic::bswap:
-        computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q);
+        computeKnownBits(I->getOperand(0), DemandedElts, Known2, Depth + 1, Q);
         Known.Zero |= Known2.Zero.byteSwap();
         Known.One |= Known2.One.byteSwap();
         break;
@@ -1762,13 +1762,20 @@ static void computeKnownBitsFromOperator(const Operator *I,
     }
     break;
   }
-  case Instruction::ExtractElement:
-    // Look through extract element. At the moment we keep this simple and skip
-    // tracking the specific element. But at least we might find information
-    // valid for all elements of the vector (for example if vector is sign
-    // extended, shifted, etc).
-    computeKnownBits(I->getOperand(0), Known, Depth + 1, Q);
+  case Instruction::ExtractElement: {
+    // Look through extract element. If the index is non-constant or
+    // out-of-range demand all elements, otherwise just the extracted element.
+    auto* EEI = cast<ExtractElementInst>(I);
+    const Value* Vec = EEI->getVectorOperand();
+    const Value* Idx = EEI->getIndexOperand();
+    auto *CIdx = dyn_cast<ConstantInt>(Idx);
+    unsigned NumElts = Vec->getType()->getVectorNumElements();
+    APInt DemandedVecElts = APInt::getAllOnesValue(NumElts);
+    if (CIdx && CIdx->getValue().ult(NumElts))
+      DemandedVecElts = APInt::getOneBitSet(NumElts, CIdx->getZExtValue());
+    computeKnownBits(Vec, DemandedVecElts, Known, Depth + 1, Q);
     break;
+  }
   case Instruction::ExtractValue:
     if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I->getOperand(0))) {
       const ExtractValueInst *EVI = cast<ExtractValueInst>(I);
@@ -2084,7 +2091,7 @@ static bool isGEPKnownNonNull(const GEPOperator *GEP, unsigned Depth,
     }
 
     // If we have a zero-sized type, the index doesn't matter. Keep looping.
-    if (Q.DL.getTypeAllocSize(GTI.getIndexedType()) == 0)
+    if (Q.DL.getTypeAllocSize(GTI.getIndexedType()).getKnownMinSize() == 0)
       continue;
 
     // Fast path the constant operand case both for efficiency and so we don't
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index 1632895fe5fa3..2a99592265408 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -395,7 +395,7 @@ static bool slotOnlyDiscardsData(const Value *RetVal, const Value *CallVal,
 
 /// For an aggregate type, determine whether a given index is within bounds or
 /// not.
-static bool indexReallyValid(CompositeType *T, unsigned Idx) {
+static bool indexReallyValid(Type *T, unsigned Idx) {
   if (ArrayType *AT = dyn_cast<ArrayType>(T))
     return Idx < AT->getNumElements();
 
@@ -419,7 +419,7 @@ static bool indexReallyValid(CompositeType *T, unsigned Idx) {
 /// function again on a finished iterator will repeatedly return
 /// false. SubTypes.back()->getTypeAtIndex(Path.back()) is either an empty
 /// aggregate or a non-aggregate
-static bool advanceToNextLeafType(SmallVectorImpl<CompositeType *> &SubTypes,
+static bool advanceToNextLeafType(SmallVectorImpl<Type *> &SubTypes,
                                   SmallVectorImpl<unsigned> &Path) {
   // First march back up the tree until we can successfully increment one of the
   // coordinates in Path.
@@ -435,16 +435,16 @@ static bool advanceToNextLeafType(SmallVectorImpl<CompositeType *> &SubTypes,
   // We know there's *some* valid leaf now, so march back down the tree picking
   // out the left-most element at each node.
   ++Path.back();
-  Type *DeeperType = SubTypes.back()->getTypeAtIndex(Path.back());
+  Type *DeeperType =
+      ExtractValueInst::getIndexedType(SubTypes.back(), Path.back());
   while (DeeperType->isAggregateType()) {
-    CompositeType *CT = cast<CompositeType>(DeeperType);
-    if (!indexReallyValid(CT, 0))
+    if (!indexReallyValid(DeeperType, 0))
       return true;
 
-    SubTypes.push_back(CT);
+    SubTypes.push_back(DeeperType);
     Path.push_back(0);
 
-    DeeperType = CT->getTypeAtIndex(0U);
+    DeeperType = ExtractValueInst::getIndexedType(DeeperType, 0);
   }
 
   return true;
@@ -460,17 +460,15 @@ static bool advanceToNextLeafType(SmallVectorImpl<CompositeType *> &SubTypes,
 /// For example, if Next was {[0 x i64], {{}, i32, {}}, i32} then we would setup
 /// Path as [1, 1] and SubTypes as [Next, {{}, i32, {}}] to represent the first
 /// i32 in that type.
-static bool firstRealType(Type *Next,
-                          SmallVectorImpl<CompositeType *> &SubTypes,
+static bool firstRealType(Type *Next, SmallVectorImpl<Type *> &SubTypes,
                           SmallVectorImpl<unsigned> &Path) {
   // First initialise the iterator components to the first "leaf" node
   // (i.e. node with no valid sub-type at any index, so {} does count as a leaf
   // despite nominally being an aggregate).
-  while (Next->isAggregateType() &&
-         indexReallyValid(cast<CompositeType>(Next), 0)) {
-    SubTypes.push_back(cast<CompositeType>(Next));
+  while (Type *FirstInner = ExtractValueInst::getIndexedType(Next, 0)) {
+    SubTypes.push_back(Next);
     Path.push_back(0);
-    Next = cast<CompositeType>(Next)->getTypeAtIndex(0U);
+    Next = FirstInner;
   }
 
   // If there's no Path now, Next was originally scalar already (or empty
@@ -480,7 +478,8 @@ static bool firstRealType(Type *Next,
 
   // Otherwise, use normal iteration to keep looking through the tree until we
   // find a non-aggregate type.
-  while (SubTypes.back()->getTypeAtIndex(Path.back())->isAggregateType()) {
+  while (ExtractValueInst::getIndexedType(SubTypes.back(), Path.back())
+             ->isAggregateType()) {
     if (!advanceToNextLeafType(SubTypes, Path))
       return false;
   }
@@ -490,14 +489,15 @@ static bool firstRealType(Type *Next,
 
 /// Set the iterator data-structures to the next non-empty, non-aggregate
 /// subtype.
-static bool nextRealType(SmallVectorImpl<CompositeType *> &SubTypes,
+static bool nextRealType(SmallVectorImpl<Type *> &SubTypes,
                          SmallVectorImpl<unsigned> &Path) {
   do {
     if (!advanceToNextLeafType(SubTypes, Path))
       return false;
 
     assert(!Path.empty() && "found a leaf but didn't set the path?");
-  } while (SubTypes.back()->getTypeAtIndex(Path.back())->isAggregateType());
+  } while (ExtractValueInst::getIndexedType(SubTypes.back(), Path.back())
+               ->isAggregateType());
 
   return true;
 }
@@ -669,7 +669,7 @@ bool llvm::returnTypeIsEligibleForTailCall(const Function *F,
   }
 
   SmallVector<unsigned, 4> RetPath, CallPath;
-  SmallVector<CompositeType *, 4> RetSubTypes, CallSubTypes;
+  SmallVector<Type *, 4> RetSubTypes, CallSubTypes;
 
   bool RetEmpty = !firstRealType(RetVal->getType(), RetSubTypes, RetPath);
   bool CallEmpty = !firstRealType(CallVal->getType(), CallSubTypes, CallPath);
@@ -692,7 +692,8 @@ bool llvm::returnTypeIsEligibleForTailCall(const Function *F,
       // We've exhausted the values produced by the tail call instruction, the
       // rest are essentially undef. The type doesn't really matter, but we need
       // *something*.
-      Type *SlotType = RetSubTypes.back()->getTypeAtIndex(RetPath.back());
+      Type *SlotType =
+          ExtractValueInst::getIndexedType(RetSubTypes.back(), RetPath.back());
       CallVal = UndefValue::get(SlotType);
     }
 
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 31b53d726556a..7d0050ff8eaac 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -682,7 +682,9 @@ void AsmPrinter::emitFunctionHeader() {
   emitConstantPool();
 
   // Print the 'header' of function.
-  OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(&F, TM));
+  MF->setSection(getObjFileLowering().SectionForGlobal(&F, TM));
+  OutStreamer->SwitchSection(MF->getSection());
+
   emitVisibility(CurrentFnSym, F.getVisibility());
 
   if (MAI->needsFunctionDescriptors() &&
@@ -1095,6 +1097,15 @@ void AsmPrinter::emitFunctionBody() {
   // Print out code for the function.
   bool HasAnyRealCode = false;
   int NumInstsInFunction = 0;
+  bool emitBBSections = MF->hasBBSections();
+  MachineBasicBlock *EndOfRegularSectionMBB = nullptr;
+  if (emitBBSections) {
+    EndOfRegularSectionMBB =
+        const_cast<MachineBasicBlock *>(MF->front().getSectionEndMBB());
+    assert(EndOfRegularSectionMBB->isEndSection() &&
+           "The MBB at the end of the regular section must end a section");
+  }
+
   for (auto &MBB : *MF) {
     // Print a label for the basic block.
     emitBasicBlockStart(MBB);
@@ -1174,7 +1185,18 @@ void AsmPrinter::emitFunctionBody() {
         }
       }
     }
-
+    if (&MBB != EndOfRegularSectionMBB &&
+        (MF->hasBBLabels() || MBB.isEndSection())) {
+      // Emit size directive for the size of this basic block.  Create a symbol
+      // for the end of the basic block.
+      MCSymbol *CurrentBBEnd = OutContext.createTempSymbol();
+      const MCExpr *SizeExp = MCBinaryExpr::createSub(
+          MCSymbolRefExpr::create(CurrentBBEnd, OutContext),
+          MCSymbolRefExpr::create(MBB.getSymbol(), OutContext), OutContext);
+      OutStreamer->emitLabel(CurrentBBEnd);
+      MBB.setEndMCSymbol(CurrentBBEnd);
+      OutStreamer->emitELFSize(MBB.getSymbol(), SizeExp);
+    }
     emitBasicBlockEnd(MBB);
   }
 
@@ -1208,6 +1230,10 @@ void AsmPrinter::emitFunctionBody() {
     }
   }
 
+  // Switch to the original section if basic block sections was used.
+  if (emitBBSections)
+    OutStreamer->SwitchSection(MF->getSection());
+
   const Function &F = MF->getFunction();
   for (const auto &BB : F) {
     if (!BB.hasAddressTaken())
@@ -1223,7 +1249,7 @@ void AsmPrinter::emitFunctionBody() {
   emitFunctionBodyEnd();
 
   if (needFuncLabelsForEHOrDebugInfo(*MF, MMI) ||
-      MAI->hasDotTypeDotSizeDirective()) {
+      MAI->hasDotTypeDotSizeDirective() || emitBBSections) {
     // Create a symbol for the end of function.
     CurrentFnEnd = createTempSymbol("func_end");
     OutStreamer->emitLabel(CurrentFnEnd);
@@ -1246,6 +1272,9 @@ void AsmPrinter::emitFunctionBody() {
     HI.Handler->markFunctionEnd();
   }
 
+  if (emitBBSections)
+    EndOfRegularSectionMBB->setEndMCSymbol(CurrentFnEnd);
+
   // Print out jump tables referenced by the function.
   emitJumpTableInfo();
 
@@ -2973,10 +3002,11 @@ static void emitBasicBlockLoopComments(const MachineBasicBlock &MBB,
   PrintChildLoopComment(OS, Loop, AP.getFunctionNumber());
 }
 
-/// EmitBasicBlockStart - This method prints the label for the specified
+/// emitBasicBlockStart - This method prints the label for the specified
 /// MachineBasicBlock, an alignment (if present) and a comment describing
 /// it if appropriate.
 void AsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
+  bool BBSections = MF->hasBBSections();
   // End the previous funclet and start a new one.
   if (MBB.isEHFuncletEntry()) {
     for (const HandlerInfo &HI : Handlers) {
@@ -2986,9 +3016,11 @@ void AsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
   }
 
   // Emit an alignment directive for this block, if needed.
-  const Align Alignment = MBB.getAlignment();
-  if (Alignment != Align(1))
-    emitAlignment(Alignment);
+  if (MBB.pred_empty() || !BBSections) {
+    const Align Alignment = MBB.getAlignment();
+    if (Alignment != Align(1))
+      emitAlignment(Alignment);
+  }
 
   // If the block has its address taken, emit any labels that were used to
   // reference the block.  It is possible that there is more than one label
@@ -3020,18 +3052,37 @@ void AsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
     emitBasicBlockLoopComments(MBB, MLI, *this);
   }
 
-  // Print the main label for the block.
+  bool emitBBLabels = BBSections || MF->hasBBLabels();
   if (MBB.pred_empty() ||
-      (isBlockOnlyReachableByFallthrough(&MBB) && !MBB.isEHFuncletEntry() &&
-       !MBB.hasLabelMustBeEmitted())) {
+      (!emitBBLabels && isBlockOnlyReachableByFallthrough(&MBB) &&
+       !MBB.isEHFuncletEntry() && !MBB.hasLabelMustBeEmitted())) {
     if (isVerbose()) {
       // NOTE: Want this comment at start of line, don't emit with AddComment.
       OutStreamer->emitRawComment(" %bb." + Twine(MBB.getNumber()) + ":",
                                   false);
     }
   } else {
-    if (isVerbose() && MBB.hasLabelMustBeEmitted())
+    if (isVerbose() && MBB.hasLabelMustBeEmitted()) {
       OutStreamer->AddComment("Label of block must be emitted");
+    }
+    // With -fbasicblock-sections, a basic block can start a new section.
+    if (MBB.getSectionType() == MachineBasicBlockSection::MBBS_Exception) {
+      // Create the exception section for this function.
+      OutStreamer->SwitchSection(
+          getObjFileLowering().getNamedSectionForMachineBasicBlock(
+              MF->getFunction(), MBB, TM, ".eh"));
+    } else if (MBB.getSectionType() == MachineBasicBlockSection::MBBS_Cold) {
+      // Create the cold section here.
+      OutStreamer->SwitchSection(
+          getObjFileLowering().getNamedSectionForMachineBasicBlock(
+              MF->getFunction(), MBB, TM, ".unlikely"));
+    } else if (MBB.isBeginSection() && MBB.isEndSection()) {
+      OutStreamer->SwitchSection(
+          getObjFileLowering().getSectionForMachineBasicBlock(MF->getFunction(),
+                                                              MBB, TM));
+    } else if (BBSections) {
+      OutStreamer->SwitchSection(MF->getSection());
+    }
     OutStreamer->emitLabel(MBB.getSymbol());
   }
 }
@@ -3064,6 +3115,10 @@ void AsmPrinter::emitVisibility(MCSymbol *Sym, unsigned Visibility,
 /// the predecessor and this block is a fall-through.
 bool AsmPrinter::
 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
+  // With BasicBlock Sections, no block is a fall through.
+  if (MBB->isBeginSection())
+    return false;
+
   // If this is a landing pad, it isn't a fall through.  If it has no preds,
   // then nothing falls through to it.
   if (MBB->isEHPad() || MBB->pred_empty())
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index bb9d2ec6ef281..7efeb1a3736ad 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -613,12 +613,15 @@ static void addToFwdRegWorklist(FwdRegWorklist &Worklist, unsigned Reg,
     // instructions we may have already created an expression for the
     // parameter when walking through the instructions. Append that to the
     // new expression.
+    std::vector<uint64_t> ParamElts = Param.Expr->getElements().vec();
+    // Avoid multiple DW_OP_stack_values.
+    if (Expr->isImplicit() && Param.Expr->isImplicit())
+      erase_if(ParamElts,
+               [](uint64_t Op) { return Op == dwarf::DW_OP_stack_value; });
     const DIExpression *CombinedExpr =
         (Param.Expr->getNumElements() > 0)
-            ? DIExpression::append(Expr, Param.Expr->getElements())
+            ? DIExpression::append(Expr, ParamElts)
             : Expr;
-    assert(CombinedExpr->isValid() && "Combined debug expression is invalid");
-
     ParamsForFwdReg.push_back({Param.ParamReg, CombinedExpr});
   }
 }
diff --git a/llvm/lib/CodeGen/BBSectionsPrepare.cpp b/llvm/lib/CodeGen/BBSectionsPrepare.cpp
new file mode 100644
index 0000000000000..6e81801abf06d
--- /dev/null
+++ b/llvm/lib/CodeGen/BBSectionsPrepare.cpp
@@ -0,0 +1,315 @@
+//===-- BBSectionsPrepare.cpp ---=========---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// BBSectionsPrepare implementation.
+//
+// The purpose of this pass is to assign sections to basic blocks when
+// -fbasicblock-sections= option is used.  Exception landing pad blocks are
+// specially handled by grouping them in a single section.  Further, with
+// profile information only the subset of basic blocks with profiles are placed
+// in a separate section and the rest are grouped in a cold section.
+//
+// Basic Block Sections
+// ====================
+//
+// With option, -fbasicblock-sections=, each basic block could be placed in a
+// unique ELF text section in the object file along with a symbol labelling the
+// basic block. The linker can then order the basic block sections in any
+// arbitrary sequence which when done correctly can encapsulate block layout,
+// function layout and function splitting optimizations. However, there are a
+// couple of challenges to be addressed for this to be feasible:
+//
+// 1. The compiler must not allow any implicit fall-through between any two
+//    adjacent basic blocks as they could be reordered at link time to be
+//    non-adjacent. In other words, the compiler must make a fall-through
+//    between adjacent basic blocks explicit by retaining the direct jump
+//    instruction that jumps to the next basic block.
+//
+// 2. All inter-basic block branch targets would now need to be resolved by the
+//    linker as they cannot be calculated during compile time. This is done
+//    using static relocations. Further, the compiler tries to use short branch
+//    instructions on some ISAs for small branch offsets. This is not possible
+//    with basic block sections as the offset is not determined at compile time,
+//    and long branch instructions have to be used everywhere.
+//
+// 3. Each additional section bloats object file sizes by tens of bytes.  The
+//    number of basic blocks can be potentially very large compared to the size
+//    of functions and can bloat object sizes significantly. Option
+//    fbasicblock-sections= also takes a file path which can be used to specify
+//    a subset of basic blocks that needs unique sections to keep the bloats
+//    small.
+//
+// 4. Debug Information (DebugInfo) and Call Frame Information (CFI) emission
+//    needs special handling with basic block sections. DebugInfo needs to be
+//    emitted with more relocations as basic block sections can break a
+//    function into potentially several disjoint pieces, and CFI needs to be
+//    emitted per basic block. This also bloats the object file and binary
+//    sizes.
+//
+// Basic Block Labels
+// ==================
+//
+// With -fbasicblock-sections=labels, or when a basic block is placed in a
+// unique section, it is labelled with a symbol.  This allows easy mapping of
+// virtual addresses from PMU profiles back to the corresponding basic blocks.
+// Since the number of basic blocks is large, the labeling bloats the symbol
+// table sizes and the string table sizes significantly. While the binary size
+// does increase, it does not affect performance as the symbol table is not
+// loaded in memory during run-time. The string table size bloat is kept very
+// minimal using a unary naming scheme that uses string suffix compression. The
+// basic blocks for function foo are named "a.BB.foo", "aa.BB.foo", ... This
+// turns out to be very good for string table sizes and the bloat in the string
+// table size for a very large binary is ~8 %.  The naming also allows using
+// the --symbol-ordering-file option in LLD to arbitrarily reorder the
+// sections.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/Support/LineIterator.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Target/TargetMachine.h"
+
+#include <string>
+
+using llvm::SmallSet;
+using llvm::StringMap;
+using llvm::StringRef;
+using namespace llvm;
+
+namespace {
+
+class BBSectionsPrepare : public MachineFunctionPass {
+public:
+  static char ID;
+  StringMap<SmallSet<unsigned, 4>> BBSectionsList;
+  const MemoryBuffer *MBuf = nullptr;
+
+  BBSectionsPrepare() : MachineFunctionPass(ID) {
+    initializeBBSectionsPreparePass(*PassRegistry::getPassRegistry());
+  }
+
+  BBSectionsPrepare(const MemoryBuffer *Buf)
+      : MachineFunctionPass(ID), MBuf(Buf) {
+    initializeBBSectionsPreparePass(*PassRegistry::getPassRegistry());
+  };
+
+  StringRef getPassName() const override {
+    return "Basic Block Sections Analysis";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  /// Read profiles of basic blocks if available here.
+  bool doInitialization(Module &M) override;
+
+  /// Identify basic blocks that need separate sections and prepare to emit them
+  /// accordingly.
+  bool runOnMachineFunction(MachineFunction &MF) override;
+};
+
+} // end anonymous namespace
+
+char BBSectionsPrepare::ID = 0;
+INITIALIZE_PASS(BBSectionsPrepare, "bbsections-prepare",
+                "Determine if a basic block needs a special section", false,
+                false)
+
+// This inserts an unconditional branch at the end of MBB to the next basic
+// block S if and only if the control-flow implicitly falls through from MBB to
+// S and S and MBB belong to different sections.  This is necessary with basic
+// block sections as MBB and S could be potentially reordered.
+static void insertUnconditionalFallthroughBranch(MachineBasicBlock &MBB) {
+  MachineBasicBlock *Fallthrough = MBB.getFallThrough();
+
+  if (Fallthrough == nullptr)
+    return;
+
+  // If this basic block and the Fallthrough basic block are in the same
+  // section then do not insert the jump.
+  if (MBB.sameSection(Fallthrough))
+    return;
+
+  const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
+  SmallVector<MachineOperand, 4> Cond;
+  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
+
+  // If a branch to the fall through block already exists, return.
+  if (!TII->analyzeBranch(MBB, TBB, FBB, Cond) &&
+      (TBB == Fallthrough || FBB == Fallthrough)) {
+    return;
+  }
+
+  Cond.clear();
+  DebugLoc DL = MBB.findBranchDebugLoc();
+  TII->insertBranch(MBB, Fallthrough, nullptr, Cond, DL);
+}
+
+/// This function sorts basic blocks according to the sections in which they are
+/// emitted.  Basic block sections automatically turn on function sections so
+/// the entry block is in the function section.  The other sections that are
+/// created are:
+/// 1) Exception section - basic blocks that are landing pads
+/// 2) Cold section - basic blocks that will not have unique sections.
+/// 3) Unique section - one per basic block that is emitted in a unique section.
+static bool assignSectionsAndSortBasicBlocks(
+    MachineFunction &MF,
+    const StringMap<SmallSet<unsigned, 4>> &BBSectionsList) {
+  SmallSet<unsigned, 4> S = BBSectionsList.lookup(MF.getName());
+
+  bool HasHotEHPads = false;
+
+  for (auto &MBB : MF) {
+    // Entry basic block cannot start another section because the function
+    // starts one already.
+    if (MBB.getNumber() == MF.front().getNumber()) {
+      MBB.setSectionType(MachineBasicBlockSection::MBBS_Entry);
+      continue;
+    }
+    // Check if this BB is a cold basic block.  With the list option, all cold
+    // basic blocks can be clustered in a single cold section.
+    // All Exception landing pads must be in a single section.  If all the
+    // landing pads are cold, it can be kept in the cold section.  Otherwise, we
+    // create a separate exception section.
+    bool isColdBB = ((MF.getTarget().getBBSectionsType() ==
+                      llvm::BasicBlockSection::List) &&
+                     !S.empty() && !S.count(MBB.getNumber()));
+    if (isColdBB) {
+      MBB.setSectionType(MachineBasicBlockSection::MBBS_Cold);
+    } else if (MBB.isEHPad()) {
+      // We handle non-cold basic eh blocks later.
+      HasHotEHPads = true;
+    } else {
+      // Place this MBB in a unique section.  A unique section begins and ends
+      // that section by definition.
+      MBB.setSectionType(MachineBasicBlockSection::MBBS_Unique);
+    }
+  }
+
+  // If some EH Pads are not cold then we move all EH Pads to the exception
+  // section as we require that all EH Pads be in a single section.
+  if (HasHotEHPads) {
+    std::for_each(MF.begin(), MF.end(), [&](MachineBasicBlock &MBB) {
+      if (MBB.isEHPad())
+        MBB.setSectionType(MachineBasicBlockSection::MBBS_Exception);
+    });
+  }
+
+  for (auto &MBB : MF) {
+    // With -fbasicblock-sections, fall through blocks must be made
+    // explicitly reachable.  Do this after sections is set as
+    // unnecessary fallthroughs can be avoided.
+    insertUnconditionalFallthroughBranch(MBB);
+  }
+
+  MF.sort(([&](MachineBasicBlock &X, MachineBasicBlock &Y) {
+    unsigned TypeX = X.getSectionType();
+    unsigned TypeY = Y.getSectionType();
+
+    return (TypeX != TypeY) ? TypeX < TypeY : X.getNumber() < Y.getNumber();
+  }));
+
+  MF.setSectionRange();
+  return true;
+}
+
+bool BBSectionsPrepare::runOnMachineFunction(MachineFunction &MF) {
+  auto BBSectionsType = MF.getTarget().getBBSectionsType();
+  assert(BBSectionsType != BasicBlockSection::None &&
+         "BB Sections not enabled!");
+
+  // Renumber blocks before sorting them for basic block sections.  This is
+  // useful during sorting, basic blocks in the same section will retain the
+  // default order.  This renumbering should also be done for basic block
+  // labels to match the profiles with the correct blocks.
+  MF.RenumberBlocks();
+
+  if (BBSectionsType == BasicBlockSection::Labels) {
+    MF.setBBSectionsType(BBSectionsType);
+    MF.createBBLabels();
+    return true;
+  }
+
+  if (BBSectionsType == BasicBlockSection::List &&
+      BBSectionsList.find(MF.getName()) == BBSectionsList.end())
+    return true;
+
+  MF.setBBSectionsType(BBSectionsType);
+  MF.createBBLabels();
+  assignSectionsAndSortBasicBlocks(MF, BBSectionsList);
+
+  return true;
+}
+
+// Basic Block Sections can be enabled for a subset of machine basic blocks.
+// This is done by passing a file containing names of functions for which basic
+// block sections are desired.  Additionally, machine basic block ids of the
+// functions can also be specified for a finer granularity.
+// A file with basic block sections for all of function main and two blocks for
+// function foo looks like this:
+// ----------------------------
+// list.txt:
+// !main
+// !foo
+// !!2
+// !!4
+static bool getBBSectionsList(const MemoryBuffer *MBuf,
+                              StringMap<SmallSet<unsigned, 4>> &bbMap) {
+  if (!MBuf)
+    return false;
+
+  line_iterator LineIt(*MBuf, /*SkipBlanks=*/true, /*CommentMarker=*/'#');
+
+  StringMap<SmallSet<unsigned, 4>>::iterator fi = bbMap.end();
+
+  for (; !LineIt.is_at_eof(); ++LineIt) {
+    StringRef s(*LineIt);
+    if (s[0] == '@')
+      continue;
+    // Check for the leading "!"
+    if (!s.consume_front("!") || s.empty())
+      break;
+    // Check for second "!" which encodes basic block ids.
+    if (s.consume_front("!")) {
+      if (fi != bbMap.end())
+        fi->second.insert(std::stoi(s.str()));
+      else
+        return false;
+    } else {
+      // Start a new function.
+      auto R = bbMap.try_emplace(s.split('/').first);
+      fi = R.first;
+      assert(R.second);
+    }
+  }
+  return true;
+}
+
+bool BBSectionsPrepare::doInitialization(Module &M) {
+  if (MBuf)
+    getBBSectionsList(MBuf, BBSectionsList);
+  return true;
+}
+
+void BBSectionsPrepare::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.setPreservesAll();
+  AU.addRequired<MachineModuleInfoWrapperPass>();
+}
+
+MachineFunctionPass *
+llvm::createBBSectionsPreparePass(const MemoryBuffer *Buf) {
+  return new BBSectionsPrepare(Buf);
+}
diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt
index 0a299da0f4030..5113b488f2c0c 100644
--- a/llvm/lib/CodeGen/CMakeLists.txt
+++ b/llvm/lib/CodeGen/CMakeLists.txt
@@ -8,12 +8,14 @@ add_llvm_component_library(LLVMCodeGen
   BranchRelaxation.cpp
   BreakFalseDeps.cpp
   BuiltinGCs.cpp
+  BBSectionsPrepare.cpp
   CalcSpillWeights.cpp
   CallingConvLower.cpp
   CFGuardLongjmp.cpp
   CFIInstrInserter.cpp
   CodeGen.cpp
   CodeGenPrepare.cpp
+  CommandFlags.cpp
   CriticalAntiDepBreaker.cpp
   DeadMachineInstructionElim.cpp
   DetectDeadLanes.cpp
@@ -115,6 +117,9 @@ add_llvm_component_library(LLVMCodeGen
   ProcessImplicitDefs.cpp
   PrologEpilogInserter.cpp
   PseudoSourceValue.cpp
+  RDFGraph.cpp
+  RDFLiveness.cpp
+  RDFRegisters.cpp
   ReachingDefAnalysis.cpp
   RegAllocBase.cpp
   RegAllocBasic.cpp
diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp
index bf97aaee36659..5d6ee09c84387 100644
--- a/llvm/lib/CodeGen/CalcSpillWeights.cpp
+++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp
@@ -203,9 +203,10 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
   };
   std::set<CopyHint> CopyHints;
 
-  for (MachineRegisterInfo::reg_instr_iterator
-       I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
-       I != E; ) {
+  for (MachineRegisterInfo::reg_instr_nodbg_iterator
+           I = mri.reg_instr_nodbg_begin(li.reg),
+           E = mri.reg_instr_nodbg_end();
+       I != E;) {
     MachineInstr *mi = &*(I++);
 
     // For local split artifacts, we are interested only in instructions between
@@ -215,7 +216,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
       continue;
 
     numInstr++;
-    if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugInstr())
+    if (mi->isIdentityCopy() || mi->isImplicitDef())
       continue;
     if (!visited.insert(mi).second)
       continue;
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index c74ba71d61708..eefb328c9c607 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -20,6 +20,7 @@ using namespace llvm;
 /// initializeCodeGen - Initialize all passes linked into the CodeGen library.
 void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeAtomicExpandPass(Registry);
+  initializeBBSectionsPreparePass(Registry);
   initializeBranchFolderPassPass(Registry);
   initializeBranchRelaxationPass(Registry);
   initializeCFGuardLongjmpPass(Registry);
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index fd55ef2936b0a..1cccd6fade4ef 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -6140,7 +6140,7 @@ bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
   //    select.end:
   //       %sel = phi i32 [ %c, %select.true ], [ %d, %select.false ]
   //
-  // %cmp should be freezed, otherwise it may introduce undefined behavior.
+  // %cmp should be frozen, otherwise it may introduce undefined behavior.
   // In addition, we may sink instructions that produce %c or %d from
   // the entry block into the destination(s) of the new branch.
   // If the true or false blocks do not contain a sunken instruction, that
diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp
new file mode 100644
index 0000000000000..7acb84df582fa
--- /dev/null
+++ b/llvm/lib/CodeGen/CommandFlags.cpp
@@ -0,0 +1,588 @@
+//===-- CommandFlags.cpp - Command Line Flags Interface ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains codegen-specific flags that are shared between different
+// command line tools. The tools "llc" and "opt" both use this file to prevent
+// flag duplication.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/CommandFlags.h"
+
+using namespace llvm;
+
+#define CGOPT(TY, NAME)                                                        \
+  static cl::opt<TY> *NAME##View;                                              \
+  TY codegen::get##NAME() {                                                    \
+    assert(NAME##View && "RegisterCodeGenFlags not created.");                 \
+    return *NAME##View;                                                        \
+  }
+
+#define CGLIST(TY, NAME)                                                       \
+  static cl::list<TY> *NAME##View;                                             \
+  std::vector<TY> codegen::get##NAME() {                                       \
+    assert(NAME##View && "RegisterCodeGenFlags not created.");                 \
+    return *NAME##View;                                                        \
+  }
+
+#define CGOPT_EXP(TY, NAME)                                                    \
+  CGOPT(TY, NAME)                                                              \
+  Optional<TY> codegen::getExplicit##NAME() {                                  \
+    if (NAME##View->getNumOccurrences()) {                                     \
+      TY res = *NAME##View;                                                    \
+      return res;                                                              \
+    }                                                                          \
+    return None;                                                               \
+  }
+
+CGOPT(std::string, MArch)
+CGOPT(std::string, MCPU)
+CGLIST(std::string, MAttrs)
+CGOPT_EXP(Reloc::Model, RelocModel)
+CGOPT(ThreadModel::Model, ThreadModel)
+CGOPT_EXP(CodeModel::Model, CodeModel)
+CGOPT(ExceptionHandling, ExceptionModel)
+CGOPT_EXP(CodeGenFileType, FileType)
+CGOPT(FramePointer::FP, FramePointerUsage)
+CGOPT(bool, EnableUnsafeFPMath)
+CGOPT(bool, EnableNoInfsFPMath)
+CGOPT(bool, EnableNoNaNsFPMath)
+CGOPT(bool, EnableNoSignedZerosFPMath)
+CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(FPDenormal::DenormalMode, DenormalFPMath)
+CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
+CGOPT(FloatABI::ABIType, FloatABIForCalls)
+CGOPT(FPOpFusion::FPOpFusionMode, FuseFPOps)
+CGOPT(bool, DontPlaceZerosInBSS)
+CGOPT(bool, EnableGuaranteedTailCallOpt)
+CGOPT(bool, DisableTailCalls)
+CGOPT(bool, StackSymbolOrdering)
+CGOPT(unsigned, OverrideStackAlignment)
+CGOPT(bool, StackRealign)
+CGOPT(std::string, TrapFuncName)
+CGOPT(bool, UseCtors)
+CGOPT(bool, RelaxELFRelocations)
+CGOPT_EXP(bool, DataSections)
+CGOPT_EXP(bool, FunctionSections)
+CGOPT(std::string, BBSections)
+CGOPT(unsigned, TLSSize)
+CGOPT(bool, EmulatedTLS)
+CGOPT(bool, UniqueSectionNames)
+CGOPT(bool, UniqueBBSectionNames)
+CGOPT(EABI, EABIVersion)
+CGOPT(DebuggerKind, DebuggerTuningOpt)
+CGOPT(bool, EnableStackSizeSection)
+CGOPT(bool, EnableAddrsig)
+CGOPT(bool, EmitCallSiteInfo)
+CGOPT(bool, EnableDebugEntryValues)
+CGOPT(bool, ForceDwarfFrameSection)
+
+codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
+#define CGBINDOPT(NAME)                                                        \
+  do {                                                                         \
+    NAME##View = std::addressof(NAME);                                         \
+  } while (0)
+
+  static cl::opt<std::string> MArch(
+      "march", cl::desc("Architecture to generate code for (see --version)"));
+  CGBINDOPT(MArch);
+
+  static cl::opt<std::string> MCPU(
+      "mcpu", cl::desc("Target a specific cpu type (-mcpu=help for details)"),
+      cl::value_desc("cpu-name"), cl::init(""));
+  CGBINDOPT(MCPU);
+
+  static cl::list<std::string> MAttrs(
+      "mattr", cl::CommaSeparated,
+      cl::desc("Target specific attributes (-mattr=help for details)"),
+      cl::value_desc("a1,+a2,-a3,..."));
+  CGBINDOPT(MAttrs);
+
+  static cl::opt<Reloc::Model> RelocModel(
+      "relocation-model", cl::desc("Choose relocation model"),
+      cl::values(
+          clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
+          clEnumValN(Reloc::PIC_, "pic",
+                     "Fully relocatable, position independent code"),
+          clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
+                     "Relocatable external references, non-relocatable code"),
+          clEnumValN(
+              Reloc::ROPI, "ropi",
+              "Code and read-only data relocatable, accessed PC-relative"),
+          clEnumValN(
+              Reloc::RWPI, "rwpi",
+              "Read-write data relocatable, accessed relative to static base"),
+          clEnumValN(Reloc::ROPI_RWPI, "ropi-rwpi",
+                     "Combination of ropi and rwpi")));
+  CGBINDOPT(RelocModel);
+
+  static cl::opt<ThreadModel::Model> ThreadModel(
+      "thread-model", cl::desc("Choose threading model"),
+      cl::init(ThreadModel::POSIX),
+      cl::values(
+          clEnumValN(ThreadModel::POSIX, "posix", "POSIX thread model"),
+          clEnumValN(ThreadModel::Single, "single", "Single thread model")));
+  CGBINDOPT(ThreadModel);
+
+  static cl::opt<CodeModel::Model> CodeModel(
+      "code-model", cl::desc("Choose code model"),
+      cl::values(clEnumValN(CodeModel::Tiny, "tiny", "Tiny code model"),
+                 clEnumValN(CodeModel::Small, "small", "Small code model"),
+                 clEnumValN(CodeModel::Kernel, "kernel", "Kernel code model"),
+                 clEnumValN(CodeModel::Medium, "medium", "Medium code model"),
+                 clEnumValN(CodeModel::Large, "large", "Large code model")));
+  CGBINDOPT(CodeModel);
+
+  static cl::opt<ExceptionHandling> ExceptionModel(
+      "exception-model", cl::desc("exception model"),
+      cl::init(ExceptionHandling::None),
+      cl::values(
+          clEnumValN(ExceptionHandling::None, "default",
+                     "default exception handling model"),
+          clEnumValN(ExceptionHandling::DwarfCFI, "dwarf",
+                     "DWARF-like CFI based exception handling"),
+          clEnumValN(ExceptionHandling::SjLj, "sjlj",
+                     "SjLj exception handling"),
+          clEnumValN(ExceptionHandling::ARM, "arm", "ARM EHABI exceptions"),
+          clEnumValN(ExceptionHandling::WinEH, "wineh",
+                     "Windows exception model"),
+          clEnumValN(ExceptionHandling::Wasm, "wasm",
+                     "WebAssembly exception handling")));
+  CGBINDOPT(ExceptionModel);
+
+  static cl::opt<CodeGenFileType> FileType(
+      "filetype", cl::init(CGFT_AssemblyFile),
+      cl::desc(
+          "Choose a file type (not all types are supported by all targets):"),
+      cl::values(
+          clEnumValN(CGFT_AssemblyFile, "asm", "Emit an assembly ('.s') file"),
+          clEnumValN(CGFT_ObjectFile, "obj",
+                     "Emit a native object ('.o') file"),
+          clEnumValN(CGFT_Null, "null",
+                     "Emit nothing, for performance testing")));
+  CGBINDOPT(FileType);
+
+  static cl::opt<FramePointer::FP> FramePointerUsage(
+      "frame-pointer",
+      cl::desc("Specify frame pointer elimination optimization"),
+      cl::init(FramePointer::None),
+      cl::values(
+          clEnumValN(FramePointer::All, "all",
+                     "Disable frame pointer elimination"),
+          clEnumValN(FramePointer::NonLeaf, "non-leaf",
+                     "Disable frame pointer elimination for non-leaf frame"),
+          clEnumValN(FramePointer::None, "none",
+                     "Enable frame pointer elimination")));
+  CGBINDOPT(FramePointerUsage);
+
+  static cl::opt<bool> EnableUnsafeFPMath(
+      "enable-unsafe-fp-math",
+      cl::desc("Enable optimizations that may decrease FP precision"),
+      cl::init(false));
+  CGBINDOPT(EnableUnsafeFPMath);
+
+  static cl::opt<bool> EnableNoInfsFPMath(
+      "enable-no-infs-fp-math",
+      cl::desc("Enable FP math optimizations that assume no +-Infs"),
+      cl::init(false));
+  CGBINDOPT(EnableNoInfsFPMath);
+
+  static cl::opt<bool> EnableNoNaNsFPMath(
+      "enable-no-nans-fp-math",
+      cl::desc("Enable FP math optimizations that assume no NaNs"),
+      cl::init(false));
+  CGBINDOPT(EnableNoNaNsFPMath);
+
+  static cl::opt<bool> EnableNoSignedZerosFPMath(
+      "enable-no-signed-zeros-fp-math",
+      cl::desc("Enable FP math optimizations that assume "
+               "the sign of 0 is insignificant"),
+      cl::init(false));
+  CGBINDOPT(EnableNoSignedZerosFPMath);
+
+  static cl::opt<bool> EnableNoTrappingFPMath(
+      "enable-no-trapping-fp-math",
+      cl::desc("Enable setting the FP exceptions build "
+               "attribute not to use exceptions"),
+      cl::init(false));
+  CGBINDOPT(EnableNoTrappingFPMath);
+
+  static cl::opt<FPDenormal::DenormalMode> DenormalFPMath(
+      "denormal-fp-math",
+      cl::desc(
+          "Select which denormal numbers the code is permitted to require"),
+      cl::init(FPDenormal::IEEE),
+      cl::values(
+          clEnumValN(FPDenormal::IEEE, "ieee", "IEEE 754 denormal numbers"),
+          clEnumValN(FPDenormal::PreserveSign, "preserve-sign",
+                     "the sign of a  flushed-to-zero number is preserved "
+                     "in the sign of 0"),
+          clEnumValN(FPDenormal::PositiveZero, "positive-zero",
+                     "denormals are flushed to positive zero")));
+  CGBINDOPT(DenormalFPMath);
+
+  static cl::opt<bool> EnableHonorSignDependentRoundingFPMath(
+      "enable-sign-dependent-rounding-fp-math", cl::Hidden,
+      cl::desc("Force codegen to assume rounding mode can change dynamically"),
+      cl::init(false));
+  CGBINDOPT(EnableHonorSignDependentRoundingFPMath);
+
+  static cl::opt<FloatABI::ABIType> FloatABIForCalls(
+      "float-abi", cl::desc("Choose float ABI type"),
+      cl::init(FloatABI::Default),
+      cl::values(clEnumValN(FloatABI::Default, "default",
+                            "Target default float ABI type"),
+                 clEnumValN(FloatABI::Soft, "soft",
+                            "Soft float ABI (implied by -soft-float)"),
+                 clEnumValN(FloatABI::Hard, "hard",
+                            "Hard float ABI (uses FP registers)")));
+  CGBINDOPT(FloatABIForCalls);
+
+  static cl::opt<FPOpFusion::FPOpFusionMode> FuseFPOps(
+      "fp-contract", cl::desc("Enable aggressive formation of fused FP ops"),
+      cl::init(FPOpFusion::Standard),
+      cl::values(
+          clEnumValN(FPOpFusion::Fast, "fast",
+                     "Fuse FP ops whenever profitable"),
+          clEnumValN(FPOpFusion::Standard, "on", "Only fuse 'blessed' FP ops."),
+          clEnumValN(FPOpFusion::Strict, "off",
+                     "Only fuse FP ops when the result won't be affected.")));
+  CGBINDOPT(FuseFPOps);
+
+  static cl::opt<bool> DontPlaceZerosInBSS(
+      "nozero-initialized-in-bss",
+      cl::desc("Don't place zero-initialized symbols into bss section"),
+      cl::init(false));
+  CGBINDOPT(DontPlaceZerosInBSS);
+
+  static cl::opt<bool> EnableGuaranteedTailCallOpt(
+      "tailcallopt",
+      cl::desc(
+          "Turn fastcc calls into tail calls by (potentially) changing ABI."),
+      cl::init(false));
+  CGBINDOPT(EnableGuaranteedTailCallOpt);
+
+  static cl::opt<bool> DisableTailCalls(
+      "disable-tail-calls", cl::desc("Never emit tail calls"), cl::init(false));
+  CGBINDOPT(DisableTailCalls);
+
+  static cl::opt<bool> StackSymbolOrdering(
+      "stack-symbol-ordering", cl::desc("Order local stack symbols."),
+      cl::init(true));
+  CGBINDOPT(StackSymbolOrdering);
+
+  static cl::opt<unsigned> OverrideStackAlignment(
+      "stack-alignment", cl::desc("Override default stack alignment"),
+      cl::init(0));
+  CGBINDOPT(OverrideStackAlignment);
+
+  static cl::opt<bool> StackRealign(
+      "stackrealign",
+      cl::desc("Force align the stack to the minimum alignment"),
+      cl::init(false));
+  CGBINDOPT(StackRealign);
+
+  static cl::opt<std::string> TrapFuncName(
+      "trap-func", cl::Hidden,
+      cl::desc("Emit a call to trap function rather than a trap instruction"),
+      cl::init(""));
+  CGBINDOPT(TrapFuncName);
+
+  static cl::opt<bool> UseCtors("use-ctors",
+                                cl::desc("Use .ctors instead of .init_array."),
+                                cl::init(false));
+  CGBINDOPT(UseCtors);
+
+  static cl::opt<bool> RelaxELFRelocations(
+      "relax-elf-relocations",
+      cl::desc(
+          "Emit GOTPCRELX/REX_GOTPCRELX instead of GOTPCREL on x86-64 ELF"),
+      cl::init(false));
+  CGBINDOPT(RelaxELFRelocations);
+
+  static cl::opt<bool> DataSections(
+      "data-sections", cl::desc("Emit data into separate sections"),
+      cl::init(false));
+  CGBINDOPT(DataSections);
+
+  static cl::opt<bool> FunctionSections(
+      "function-sections", cl::desc("Emit functions into separate sections"),
+      cl::init(false));
+  CGBINDOPT(FunctionSections);
+
+  static cl::opt<std::string> BBSections(
+      "basicblock-sections",
+      cl::desc("Emit basic blocks into separate sections"),
+      cl::value_desc("all | <function list (file)> | labels | none"),
+      cl::init("none"));
+  CGBINDOPT(BBSections);
+
+  static cl::opt<unsigned> TLSSize(
+      "tls-size", cl::desc("Bit size of immediate TLS offsets"), cl::init(0));
+  CGBINDOPT(TLSSize);
+
+  static cl::opt<bool> EmulatedTLS(
+      "emulated-tls", cl::desc("Use emulated TLS model"), cl::init(false));
+  CGBINDOPT(EmulatedTLS);
+
+  static cl::opt<bool> UniqueSectionNames(
+      "unique-section-names", cl::desc("Give unique names to every section"),
+      cl::init(true));
+  CGBINDOPT(UniqueSectionNames);
+
+  static cl::opt<bool> UniqueBBSectionNames(
+      "unique-bb-section-names",
+      cl::desc("Give unique names to every basic block section"),
+      cl::init(false));
+  CGBINDOPT(UniqueBBSectionNames);
+
+  static cl::opt<EABI> EABIVersion(
+      "meabi", cl::desc("Set EABI type (default depends on triple):"),
+      cl::init(EABI::Default),
+      cl::values(
+          clEnumValN(EABI::Default, "default", "Triple default EABI version"),
+          clEnumValN(EABI::EABI4, "4", "EABI version 4"),
+          clEnumValN(EABI::EABI5, "5", "EABI version 5"),
+          clEnumValN(EABI::GNU, "gnu", "EABI GNU")));
+  CGBINDOPT(EABIVersion);
+
+  static cl::opt<DebuggerKind> DebuggerTuningOpt(
+      "debugger-tune", cl::desc("Tune debug info for a particular debugger"),
+      cl::init(DebuggerKind::Default),
+      cl::values(
+          clEnumValN(DebuggerKind::GDB, "gdb", "gdb"),
+          clEnumValN(DebuggerKind::LLDB, "lldb", "lldb"),
+          clEnumValN(DebuggerKind::SCE, "sce", "SCE targets (e.g. PS4)")));
+  CGBINDOPT(DebuggerTuningOpt);
+
+  static cl::opt<bool> EnableStackSizeSection(
+      "stack-size-section",
+      cl::desc("Emit a section containing stack size metadata"),
+      cl::init(false));
+  CGBINDOPT(EnableStackSizeSection);
+
+  static cl::opt<bool> EnableAddrsig(
+      "addrsig", cl::desc("Emit an address-significance table"),
+      cl::init(false));
+  CGBINDOPT(EnableAddrsig);
+
+  static cl::opt<bool> EmitCallSiteInfo(
+      "emit-call-site-info",
+      cl::desc(
+          "Emit call site debug information, if debug information is enabled."),
+      cl::init(false));
+  CGBINDOPT(EmitCallSiteInfo);
+
+  static cl::opt<bool> EnableDebugEntryValues(
+      "debug-entry-values",
+      cl::desc("Emit debug info about parameter's entry values"),
+      cl::init(false));
+  CGBINDOPT(EnableDebugEntryValues);
+
+  static cl::opt<bool> ForceDwarfFrameSection(
+      "force-dwarf-frame-section",
+      cl::desc("Always emit a debug frame section."), cl::init(false));
+  CGBINDOPT(ForceDwarfFrameSection);
+
+#undef CGBINDOPT
+
+  mc::RegisterMCTargetOptionsFlags();
+}
+
+llvm::BasicBlockSection
+codegen::getBBSectionsMode(llvm::TargetOptions &Options) {
+  if (getBBSections() == "all")
+    return BasicBlockSection::All;
+  else if (getBBSections() == "labels")
+    return BasicBlockSection::Labels;
+  else if (getBBSections() == "none")
+    return BasicBlockSection::None;
+  else {
+    ErrorOr<std::unique_ptr<MemoryBuffer>> MBOrErr =
+        MemoryBuffer::getFile(getBBSections());
+    if (!MBOrErr) {
+      errs() << "Error loading basic block sections function list file: "
+             << MBOrErr.getError().message() << "\n";
+    } else {
+      Options.BBSectionsFuncListBuf = std::move(*MBOrErr);
+    }
+    return BasicBlockSection::List;
+  }
+}
+
+// Common utility function tightly tied to the options listed here. Initializes
+// a TargetOptions object with CodeGen flags and returns it.
+TargetOptions codegen::InitTargetOptionsFromCodeGenFlags() {
+  TargetOptions Options;
+  Options.AllowFPOpFusion = getFuseFPOps();
+  Options.UnsafeFPMath = getEnableUnsafeFPMath();
+  Options.NoInfsFPMath = getEnableNoInfsFPMath();
+  Options.NoNaNsFPMath = getEnableNoNaNsFPMath();
+  Options.NoSignedZerosFPMath = getEnableNoSignedZerosFPMath();
+  Options.NoTrappingFPMath = getEnableNoTrappingFPMath();
+  Options.FPDenormalMode = getDenormalFPMath();
+  Options.HonorSignDependentRoundingFPMathOption =
+      getEnableHonorSignDependentRoundingFPMath();
+  if (getFloatABIForCalls() != FloatABI::Default)
+    Options.FloatABIType = getFloatABIForCalls();
+  Options.NoZerosInBSS = getDontPlaceZerosInBSS();
+  Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
+  Options.StackAlignmentOverride = getOverrideStackAlignment();
+  Options.StackSymbolOrdering = getStackSymbolOrdering();
+  Options.UseInitArray = !getUseCtors();
+  Options.RelaxELFRelocations = getRelaxELFRelocations();
+  Options.DataSections = getDataSections();
+  Options.FunctionSections = getFunctionSections();
+  Options.BBSections = getBBSectionsMode(Options);
+  Options.UniqueSectionNames = getUniqueSectionNames();
+  Options.UniqueBBSectionNames = getUniqueBBSectionNames();
+  Options.TLSSize = getTLSSize();
+  Options.EmulatedTLS = getEmulatedTLS();
+  Options.ExplicitEmulatedTLS = EmulatedTLSView->getNumOccurrences() > 0;
+  Options.ExceptionModel = getExceptionModel();
+  Options.EmitStackSizeSection = getEnableStackSizeSection();
+  Options.EmitAddrsig = getEnableAddrsig();
+  Options.EmitCallSiteInfo = getEmitCallSiteInfo();
+  Options.EnableDebugEntryValues = getEnableDebugEntryValues();
+  Options.ForceDwarfFrameSection = getForceDwarfFrameSection();
+
+  Options.MCOptions = mc::InitMCTargetOptionsFromFlags();
+
+  Options.ThreadModel = getThreadModel();
+  Options.EABIVersion = getEABIVersion();
+  Options.DebuggerTuning = getDebuggerTuningOpt();
+
+  return Options;
+}
+
+std::string codegen::getCPUStr() {
+  // If user asked for the 'native' CPU, autodetect here. If autodection fails,
+  // this will set the CPU to an empty string which tells the target to
+  // pick a basic default.
+  if (getMCPU() == "native")
+    return std::string(sys::getHostCPUName());
+
+  return getMCPU();
+}
+
+std::string codegen::getFeaturesStr() {
+  SubtargetFeatures Features;
+
+  // If user asked for the 'native' CPU, we need to autodetect features.
+  // This is necessary for x86 where the CPU might not support all the
+  // features the autodetected CPU name lists in the target. For example,
+  // not all Sandybridge processors support AVX.
+  if (getMCPU() == "native") {
+    StringMap<bool> HostFeatures;
+    if (sys::getHostCPUFeatures(HostFeatures))
+      for (auto &F : HostFeatures)
+        Features.AddFeature(F.first(), F.second);
+  }
+
+  for (auto const &MAttr : getMAttrs())
+    Features.AddFeature(MAttr);
+
+  return Features.getString();
+}
+
+std::vector<std::string> codegen::getFeatureList() {
+  SubtargetFeatures Features;
+
+  // If user asked for the 'native' CPU, we need to autodetect features.
+  // This is necessary for x86 where the CPU might not support all the
+  // features the autodetected CPU name lists in the target. For example,
+  // not all Sandybridge processors support AVX.
+  if (getMCPU() == "native") {
+    StringMap<bool> HostFeatures;
+    if (sys::getHostCPUFeatures(HostFeatures))
+      for (auto &F : HostFeatures)
+        Features.AddFeature(F.first(), F.second);
+  }
+
+  for (auto const &MAttr : getMAttrs())
+    Features.AddFeature(MAttr);
+
+  return Features.getFeatures();
+}
+
+void codegen::renderBoolStringAttr(AttrBuilder &B, StringRef Name, bool Val) {
+  B.addAttribute(Name, Val ? "true" : "false");
+}
+
+#define HANDLE_BOOL_ATTR(CL, AttrName)                                         \
+  do {                                                                         \
+    if (CL->getNumOccurrences() > 0 && !F.hasFnAttribute(AttrName))            \
+      renderBoolStringAttr(NewAttrs, AttrName, *CL);                           \
+  } while (0)
+
+/// Set function attributes of function \p F based on CPU, Features, and command
+/// line flags.
+void codegen::setFunctionAttributes(StringRef CPU, StringRef Features,
+                                    Function &F) {
+  auto &Ctx = F.getContext();
+  AttributeList Attrs = F.getAttributes();
+  AttrBuilder NewAttrs;
+
+  if (!CPU.empty() && !F.hasFnAttribute("target-cpu"))
+    NewAttrs.addAttribute("target-cpu", CPU);
+  if (!Features.empty()) {
+    // Append the command line features to any that are already on the function.
+    StringRef OldFeatures =
+        F.getFnAttribute("target-features").getValueAsString();
+    if (OldFeatures.empty())
+      NewAttrs.addAttribute("target-features", Features);
+    else {
+      SmallString<256> Appended(OldFeatures);
+      Appended.push_back(',');
+      Appended.append(Features);
+      NewAttrs.addAttribute("target-features", Appended);
+    }
+  }
+  if (FramePointerUsageView->getNumOccurrences() > 0 &&
+      !F.hasFnAttribute("frame-pointer")) {
+    if (getFramePointerUsage() == FramePointer::All)
+      NewAttrs.addAttribute("frame-pointer", "all");
+    else if (getFramePointerUsage() == FramePointer::NonLeaf)
+      NewAttrs.addAttribute("frame-pointer", "non-leaf");
+    else if (getFramePointerUsage() == FramePointer::None)
+      NewAttrs.addAttribute("frame-pointer", "none");
+  }
+  if (DisableTailCallsView->getNumOccurrences() > 0)
+    NewAttrs.addAttribute("disable-tail-calls",
+                          toStringRef(getDisableTailCalls()));
+  if (getStackRealign())
+    NewAttrs.addAttribute("stackrealign");
+
+  HANDLE_BOOL_ATTR(EnableUnsafeFPMathView, "unsafe-fp-math");
+  HANDLE_BOOL_ATTR(EnableNoInfsFPMathView, "no-infs-fp-math");
+  HANDLE_BOOL_ATTR(EnableNoNaNsFPMathView, "no-nans-fp-math");
+  HANDLE_BOOL_ATTR(EnableNoSignedZerosFPMathView, "no-signed-zeros-fp-math");
+
+  if (TrapFuncNameView->getNumOccurrences() > 0)
+    for (auto &B : F)
+      for (auto &I : B)
+        if (auto *Call = dyn_cast<CallInst>(&I))
+          if (const auto *F = Call->getCalledFunction())
+            if (F->getIntrinsicID() == Intrinsic::debugtrap ||
+                F->getIntrinsicID() == Intrinsic::trap)
+              Call->addAttribute(
+                  AttributeList::FunctionIndex,
+                  Attribute::get(Ctx, "trap-func-name", getTrapFuncName()));
+
+  // Let NewAttrs override Attrs.
+  F.setAttributes(
+      Attrs.addAttributes(Ctx, AttributeList::FunctionIndex, NewAttrs));
+}
+
+/// Set function attributes of functions in Module M based on CPU,
+/// Features, and command line flags.
+void codegen::setFunctionAttributes(StringRef CPU, StringRef Features,
+                                    Module &M) {
+  for (Function &F : M)
+    setFunctionAttributes(CPU, Features, F);
+}
diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp
index 213416d08610e..7cf3f0863e5bf 100644
--- a/llvm/lib/CodeGen/ExpandMemCmp.cpp
+++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp
@@ -273,6 +273,8 @@ MemCmpExpansion::LoadPair MemCmpExpansion::getLoadPair(Type *LoadSizeType,
   // Get the memory source at offset `OffsetBytes`.
   Value *LhsSource = CI->getArgOperand(0);
   Value *RhsSource = CI->getArgOperand(1);
+  Align LhsAlign = LhsSource->getPointerAlignment(DL).valueOrOne();
+  Align RhsAlign = RhsSource->getPointerAlignment(DL).valueOrOne();
   if (OffsetBytes > 0) {
     auto *ByteType = Type::getInt8Ty(CI->getContext());
     LhsSource = Builder.CreateConstGEP1_64(
@@ -281,6 +283,8 @@ MemCmpExpansion::LoadPair MemCmpExpansion::getLoadPair(Type *LoadSizeType,
     RhsSource = Builder.CreateConstGEP1_64(
         ByteType, Builder.CreateBitCast(RhsSource, ByteType->getPointerTo()),
         OffsetBytes);
+    LhsAlign = commonAlignment(LhsAlign, OffsetBytes);
+    RhsAlign = commonAlignment(RhsAlign, OffsetBytes);
   }
   LhsSource = Builder.CreateBitCast(LhsSource, LoadSizeType->getPointerTo());
   RhsSource = Builder.CreateBitCast(RhsSource, LoadSizeType->getPointerTo());
@@ -290,13 +294,13 @@ MemCmpExpansion::LoadPair MemCmpExpansion::getLoadPair(Type *LoadSizeType,
   if (auto *C = dyn_cast<Constant>(LhsSource))
     Lhs = ConstantFoldLoadFromConstPtr(C, LoadSizeType, DL);
   if (!Lhs)
-    Lhs = Builder.CreateLoad(LoadSizeType, LhsSource);
+    Lhs = Builder.CreateAlignedLoad(LoadSizeType, LhsSource, LhsAlign);
 
   Value *Rhs = nullptr;
   if (auto *C = dyn_cast<Constant>(RhsSource))
     Rhs = ConstantFoldLoadFromConstPtr(C, LoadSizeType, DL);
   if (!Rhs)
-    Rhs = Builder.CreateLoad(LoadSizeType, RhsSource);
+    Rhs = Builder.CreateAlignedLoad(LoadSizeType, RhsSource, RhsAlign);
 
   // Swap bytes if required.
   if (NeedsBSwap) {
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 4e0daadead30d..ecb46f401fb44 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1483,6 +1483,37 @@ bool CombinerHelper::tryCombineShiftToUnmerge(MachineInstr &MI,
   return false;
 }
 
+bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) {
+  return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
+    return MO.isReg() &&
+           getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
+  });
+}
+
+bool CombinerHelper::replaceInstWithFConstant(MachineInstr &MI, double C) {
+  assert(MI.getNumDefs() == 1 && "Expected only one def?");
+  Builder.setInstr(MI);
+  Builder.buildFConstant(MI.getOperand(0), C);
+  MI.eraseFromParent();
+  return true;
+}
+
+bool CombinerHelper::replaceInstWithConstant(MachineInstr &MI, int64_t C) {
+  assert(MI.getNumDefs() == 1 && "Expected only one def?");
+  Builder.setInstr(MI);
+  Builder.buildConstant(MI.getOperand(0), C);
+  MI.eraseFromParent();
+  return true;
+}
+
+bool CombinerHelper::replaceInstWithUndef(MachineInstr &MI) {
+  assert(MI.getNumDefs() == 1 && "Expected only one def?");
+  Builder.setInstr(MI);
+  Builder.buildUndef(MI.getOperand(0));
+  MI.eraseFromParent();
+  return true;
+}
+
 bool CombinerHelper::tryCombine(MachineInstr &MI) {
   if (tryCombineCopy(MI))
     return true;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index d0a51ed03f000..d7cbdbc3c9046 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2194,6 +2194,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   }
   case TargetOpcode::G_FMAD:
     return lowerFMad(MI);
+  case TargetOpcode::G_FFLOOR:
+    return lowerFFloor(MI);
   case TargetOpcode::G_INTRINSIC_ROUND:
     return lowerIntrinsicRound(MI);
   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
@@ -4646,6 +4648,39 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
+  Register DstReg = MI.getOperand(0).getReg();
+  Register X = MI.getOperand(1).getReg();
+  const unsigned Flags = MI.getFlags();
+  const LLT Ty = MRI.getType(DstReg);
+  const LLT CondTy = Ty.changeElementSize(1);
+
+  // round(x) =>
+  //  t = trunc(x);
+  //  d = fabs(x - t);
+  //  o = copysign(1.0f, x);
+  //  return t + (d >= 0.5 ? o : 0.0);
+
+  auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags);
+
+  auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags);
+  auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags);
+  auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
+  auto One = MIRBuilder.buildFConstant(Ty, 1.0);
+  auto Half = MIRBuilder.buildFConstant(Ty, 0.5);
+  auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X);
+
+  auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half,
+                                  Flags);
+  auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags);
+
+  MIRBuilder.buildFAdd(DstReg, T, Sel, Flags);
+
+  MI.eraseFromParent();
+  return Legalized;
+}
+
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerFFloor(MachineInstr &MI) {
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
   unsigned Flags = MI.getFlags();
@@ -4656,8 +4691,8 @@ LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
   // if (src < 0.0 && src != result)
   //   result += -1.0.
 
-  auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
+  auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
 
   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
                                   SrcReg, Zero, Flags);
@@ -4666,7 +4701,7 @@ LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
 
-  MIRBuilder.buildFAdd(DstReg, Trunc, AddVal);
+  MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags);
   MI.eraseFromParent();
   return Legalized;
 }
@@ -4837,35 +4872,47 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
   LLT DstTy = MRI.getType(Src);
   LLT InsertTy = MRI.getType(InsertSrc);
 
-  if (InsertTy.isScalar() &&
-      (DstTy.isScalar() ||
-       (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
-    LLT IntDstTy = DstTy;
-    if (!DstTy.isScalar()) {
-      IntDstTy = LLT::scalar(DstTy.getSizeInBits());
-      Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
-    }
+  if (InsertTy.isVector() ||
+      (DstTy.isVector() && DstTy.getElementType() != InsertTy))
+    return UnableToLegalize;
 
-    Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
-    if (Offset != 0) {
-      auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
-      ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
-    }
+  const DataLayout &DL = MIRBuilder.getDataLayout();
+  if ((DstTy.isPointer() &&
+       DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) ||
+      (InsertTy.isPointer() &&
+       DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) {
+    LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
+    return UnableToLegalize;
+  }
 
-    APInt MaskVal = APInt::getBitsSetWithWrap(DstTy.getSizeInBits(),
-                                              Offset + InsertTy.getSizeInBits(),
-                                              Offset);
+  LLT IntDstTy = DstTy;
 
-    auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
-    auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
-    auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
+  if (!DstTy.isScalar()) {
+    IntDstTy = LLT::scalar(DstTy.getSizeInBits());
+    Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0);
+  }
 
-    MIRBuilder.buildBitcast(Dst, Or);
-    MI.eraseFromParent();
-    return Legalized;
+  if (!InsertTy.isScalar()) {
+    const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits());
+    InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0);
   }
 
-  return UnableToLegalize;
+  Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
+  if (Offset != 0) {
+    auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
+    ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
+  }
+
+  APInt MaskVal = APInt::getBitsSetWithWrap(
+      DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset);
+
+  auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
+  auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
+  auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
+
+  MIRBuilder.buildCast(Dst, Or);
+  MI.eraseFromParent();
+  return Legalized;
 }
 
 LegalizerHelper::LegalizeResult
@@ -4909,7 +4956,7 @@ LegalizerHelper::lowerBswap(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();
   Register Src = MI.getOperand(1).getReg();
   const LLT Ty = MRI.getType(Src);
-  unsigned SizeInBytes = Ty.getSizeInBytes();
+  unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8;
   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
 
   // Swap most and least significant byte, set remaining bytes in Res to zero.
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
index fc9c802693abd..54e5d48edf276 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
@@ -19,11 +19,12 @@
 using namespace llvm;
 
 const unsigned RegisterBank::InvalidID = UINT_MAX;
+const unsigned RegisterBank::InvalidHwMode = UINT_MAX;
 
 RegisterBank::RegisterBank(
-    unsigned ID, const char *Name, unsigned Size,
+    unsigned ID, const char *Name, const unsigned *Sizes,
     const uint32_t *CoveredClasses, unsigned NumRegClasses)
-    : ID(ID), Name(Name), Size(Size) {
+    : ID(ID), Name(Name), Sizes(Sizes), HwMode(InvalidHwMode) {
   ContainedRegClasses.resize(NumRegClasses);
   ContainedRegClasses.setBitsInMask(CoveredClasses);
 }
@@ -63,7 +64,8 @@ bool RegisterBank::covers(const TargetRegisterClass &RC) const {
 }
 
 bool RegisterBank::isValid() const {
-  return ID != InvalidID && Name != nullptr && Size != 0 &&
+  return ID != InvalidID && Name != nullptr && Sizes != nullptr &&
+         HwMode != InvalidID &&
          // A register bank that does not cover anything is useless.
          !ContainedRegClasses.empty();
 }
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 255ea693b5c4a..3a8d0a9d3c4fc 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -56,8 +56,11 @@ const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
 // RegisterBankInfo implementation.
 //------------------------------------------------------------------------------
 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
-                                   unsigned NumRegBanks)
+                                   unsigned NumRegBanks, unsigned HwMode)
     : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
+  // Initialize HwMode for all RegBanks
+  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx)
+    RegBanks[Idx]->HwMode = HwMode;
 #ifndef NDEBUG
   for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
     assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 827f53aa54f68..36a027c987e1f 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -268,6 +268,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
       .Case("pre-instr-symbol", MIToken::kw_pre_instr_symbol)
       .Case("post-instr-symbol", MIToken::kw_post_instr_symbol)
       .Case("heap-alloc-marker", MIToken::kw_heap_alloc_marker)
+      .Case("bbsections", MIToken::kw_bbsections)
       .Case("unknown-size", MIToken::kw_unknown_size)
       .Default(MIToken::Identifier);
 }
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index aaffe4a4c91bb..e76f6a7e21a39 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -122,6 +122,7 @@ struct MIToken {
     kw_pre_instr_symbol,
     kw_post_instr_symbol,
     kw_heap_alloc_marker,
+    kw_bbsections,
     kw_unknown_size,
 
     // Named metadata keywords
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index c20c1552377dc..93af409ec8552 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -495,6 +495,7 @@ class MIParser {
   bool parseOffset(int64_t &Offset);
   bool parseAlignment(unsigned &Alignment);
   bool parseAddrspace(unsigned &Addrspace);
+  bool parseMBBS(MachineBasicBlockSection &T);
   bool parseOperandsOffset(MachineOperand &Op);
   bool parseIRValue(const Value *&V);
   bool parseMemoryOperandFlag(MachineMemOperand::Flags &Flags);
@@ -619,6 +620,25 @@ bool MIParser::consumeIfPresent(MIToken::TokenKind TokenKind) {
   return true;
 }
 
+// Parse Machine Basic Block Section Type.
+bool MIParser::parseMBBS(MachineBasicBlockSection &T) {
+  assert(Token.is(MIToken::kw_bbsections));
+  lex();
+  const StringRef &S = Token.stringValue();
+  if (S == "Entry")
+    T = MBBS_Entry;
+  else if (S == "Exception")
+    T = MBBS_Exception;
+  else if (S == "Cold")
+    T = MBBS_Cold;
+  else if (S == "Unique")
+    T = MBBS_Unique;
+  else
+    return error("Unknown Section Type");
+  lex();
+  return false;
+}
+
 bool MIParser::parseBasicBlockDefinition(
     DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {
   assert(Token.is(MIToken::MachineBasicBlockLabel));
@@ -630,6 +650,7 @@ bool MIParser::parseBasicBlockDefinition(
   lex();
   bool HasAddressTaken = false;
   bool IsLandingPad = false;
+  MachineBasicBlockSection SectionType = MBBS_None;
   unsigned Alignment = 0;
   BasicBlock *BB = nullptr;
   if (consumeIfPresent(MIToken::lparen)) {
@@ -654,6 +675,10 @@ bool MIParser::parseBasicBlockDefinition(
           return true;
         lex();
         break;
+      case MIToken::kw_bbsections:
+        if (parseMBBS(SectionType))
+          return true;
+        break;
       default:
         break;
       }
@@ -683,6 +708,10 @@ bool MIParser::parseBasicBlockDefinition(
   if (HasAddressTaken)
     MBB->setHasAddressTaken();
   MBB->setIsEHPad(IsLandingPad);
+  if (SectionType != MBBS_None) {
+    MBB->setSectionType(SectionType);
+    MF.setBBSectionsType(BasicBlockSection::List);
+  }
   return false;
 }
 
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f955bdc6186a7..199d077ac66ee 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -438,6 +438,14 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
         diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));
     return true;
   }
+  // Check Basic Block Section Flags.
+  if (MF.getTarget().getBBSectionsType() == BasicBlockSection::Labels) {
+    MF.createBBLabels();
+    MF.setBBSectionsType(BasicBlockSection::Labels);
+  } else if (MF.hasBBSections()) {
+    MF.setSectionRange();
+    MF.createBBLabels();
+  }
   PFS.SM = &SM;
 
   // Initialize the frame information after creating all the MBBs so that the
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index ece4f96325ca0..2a150b1368df2 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -334,7 +334,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
   YamlMFI.StackSize = MFI.getStackSize();
   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
-  YamlMFI.MaxAlignment = MFI.getMaxAlignment();
+  YamlMFI.MaxAlignment = MFI.getMaxAlign().value();
   YamlMFI.AdjustsStack = MFI.adjustsStack();
   YamlMFI.HasCalls = MFI.hasCalls();
   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
@@ -635,6 +635,27 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
     OS << "align " << MBB.getAlignment().value();
     HasAttributes = true;
   }
+  if (MBB.getSectionType() != MBBS_None) {
+    OS << (HasAttributes ? ", " : " (");
+    OS << "bbsections ";
+    switch (MBB.getSectionType()) {
+    case MBBS_Entry:
+      OS << "Entry";
+      break;
+    case MBBS_Exception:
+      OS << "Exception";
+      break;
+    case MBBS_Cold:
+      OS << "Cold";
+      break;
+    case MBBS_Unique:
+      OS << "Unique";
+      break;
+    default:
+      llvm_unreachable("No such section type");
+    }
+    HasAttributes = true;
+  }
   if (HasAttributes)
     OS << ")";
   OS << ":\n";
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index c2f459e313ccd..b273da862fa3a 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -61,12 +61,31 @@ MCSymbol *MachineBasicBlock::getSymbol() const {
     const MachineFunction *MF = getParent();
     MCContext &Ctx = MF->getContext();
     auto Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
+
+    bool BasicBlockSymbols = MF->hasBBSections() || MF->hasBBLabels();
+    auto Delimiter = BasicBlockSymbols ? "." : "_";
     assert(getNumber() >= 0 && "cannot get label for unreachable MBB");
-    CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
-                                           Twine(MF->getFunctionNumber()) +
-                                           "_" + Twine(getNumber()));
-  }
 
+    // With Basic Block Sections, we emit a symbol for every basic block. To
+    // keep the size of strtab small, we choose a unary encoding which can
+    // compress the symbol names significantly.  The basic blocks for function
+    // foo are named a.BB.foo, aa.BB.foo, and so on.
+    if (BasicBlockSymbols) {
+      auto Iter = MF->getBBSectionsSymbolPrefix().begin();
+      if (getNumber() < 0 ||
+          getNumber() >= (int)MF->getBBSectionsSymbolPrefix().size())
+        report_fatal_error("Unreachable MBB: " + Twine(getNumber()));
+      std::string Prefix(Iter + 1, Iter + getNumber() + 1);
+      std::reverse(Prefix.begin(), Prefix.end());
+      CachedMCSymbol =
+          Ctx.getOrCreateSymbol(Prefix + Twine(Delimiter) + "BB" +
+                                Twine(Delimiter) + Twine(MF->getName()));
+    } else {
+      CachedMCSymbol = Ctx.getOrCreateSymbol(
+          Twine(Prefix) + "BB" + Twine(MF->getFunctionNumber()) +
+          Twine(Delimiter) + Twine(getNumber()));
+    }
+  }
   return CachedMCSymbol;
 }
 
@@ -529,6 +548,48 @@ void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
   getParent()->splice(++NewBefore->getIterator(), getIterator());
 }
 
+// Returns true if this basic block and the Other are in the same section.
+bool MachineBasicBlock::sameSection(const MachineBasicBlock *Other) const {
+  if (this == Other)
+    return true;
+
+  if (this->getSectionType() != Other->getSectionType())
+    return false;
+
+  // If either is in a unique section, return false.
+  if (this->getSectionType() == llvm::MachineBasicBlockSection::MBBS_Unique ||
+      Other->getSectionType() == llvm::MachineBasicBlockSection::MBBS_Unique)
+    return false;
+
+  return true;
+}
+
+const MachineBasicBlock *MachineBasicBlock::getSectionEndMBB() const {
+  if (this->isEndSection())
+    return this;
+  auto I = std::next(this->getIterator());
+  const MachineFunction *MF = getParent();
+  while (I != MF->end()) {
+    const MachineBasicBlock &MBB = *I;
+    if (MBB.isEndSection())
+      return &MBB;
+    I = std::next(I);
+  }
+  llvm_unreachable("No End Basic Block for this section.");
+}
+
+// Returns true if this block begins any section.
+bool MachineBasicBlock::isBeginSection() const {
+  return (SectionType == MBBS_Entry || SectionType == MBBS_Unique ||
+          getParent()->isSectionStartMBB(getNumber()));
+}
+
+// Returns true if this block begins any section.
+bool MachineBasicBlock::isEndSection() const {
+  return (SectionType == MBBS_Entry || SectionType == MBBS_Unique ||
+          getParent()->isSectionEndMBB(getNumber()));
+}
+
 void MachineBasicBlock::updateTerminator() {
   const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
   // A block with no successors has no concerns with fall-through edges.
diff --git a/llvm/lib/CodeGen/MachineFrameInfo.cpp b/llvm/lib/CodeGen/MachineFrameInfo.cpp
index e5f35aea98cca..7690505dabe39 100644
--- a/llvm/lib/CodeGen/MachineFrameInfo.cpp
+++ b/llvm/lib/CodeGen/MachineFrameInfo.cpp
@@ -136,7 +136,7 @@ BitVector MachineFrameInfo::getPristineRegs(const MachineFunction &MF) const {
 uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
-  unsigned MaxAlign = getMaxAlignment();
+  Align MaxAlign = getMaxAlign();
   int64_t Offset = 0;
 
   // This code is very, very similar to PEI::calculateFrameObjectOffsets().
@@ -155,11 +155,11 @@ uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
     if (isDeadObjectIndex(i) || getStackID(i) != TargetStackID::Default)
       continue;
     Offset += getObjectSize(i);
-    unsigned Align = getObjectAlignment(i);
+    Align Alignment = getObjectAlign(i);
     // Adjust to alignment boundary
-    Offset = (Offset+Align-1)/Align*Align;
+    Offset = alignTo(Offset, Alignment);
 
-    MaxAlign = std::max(Align, MaxAlign);
+    MaxAlign = std::max(Alignment, MaxAlign);
   }
 
   if (adjustsStack() && TFI->hasReservedCallFrame(MF))
@@ -170,20 +170,17 @@ uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
   // ensure that the callee's frame or the alloca data is suitably aligned;
   // otherwise, for leaf functions, align to the TransientStackAlignment
   // value.
-  unsigned StackAlign;
+  Align StackAlign;
   if (adjustsStack() || hasVarSizedObjects() ||
       (RegInfo->needsStackRealignment(MF) && getObjectIndexEnd() != 0))
-    StackAlign = TFI->getStackAlignment();
+    StackAlign = TFI->getStackAlign();
   else
-    StackAlign = TFI->getTransientStackAlignment();
+    StackAlign = TFI->getTransientStackAlign();
 
   // If the frame pointer is eliminated, all frame offsets will be relative to
   // SP not FP. Align to MaxAlign so this works.
   StackAlign = std::max(StackAlign, MaxAlign);
-  unsigned AlignMask = StackAlign - 1;
-  Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
-
-  return (uint64_t)Offset;
+  return alignTo(Offset, StackAlign);
 }
 
 void MachineFrameInfo::computeMaxCallFrameSize(const MachineFunction &MF) {
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index b00907f63d4ea..76a1bd9f75afb 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -33,6 +33,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
@@ -71,6 +72,7 @@
 #include <cstdint>
 #include <iterator>
 #include <string>
+#include <type_traits>
 #include <utility>
 #include <vector>
 
@@ -339,6 +341,59 @@ void MachineFunction::RenumberBlocks(MachineBasicBlock *MBB) {
   MBBNumbering.resize(BlockNo);
 }
 
+/// This sets the section ranges of cold or exception section with basic block
+/// sections.
+void MachineFunction::setSectionRange() {
+  // Compute the Section Range of cold and exception basic blocks.  Find the
+  // first and last block of each range.
+  auto SectionRange =
+      ([&](llvm::MachineBasicBlockSection S) -> std::pair<int, int> {
+        auto MBBP =
+            std::find_if(begin(), end(), [&](MachineBasicBlock &MBB) -> bool {
+              return MBB.getSectionType() == S;
+            });
+        if (MBBP == end())
+          return std::make_pair(-1, -1);
+
+        auto MBBQ =
+            std::find_if(rbegin(), rend(), [&](MachineBasicBlock &MBB) -> bool {
+              return MBB.getSectionType() == S;
+            });
+        assert(MBBQ != rend() && "Section end not found!");
+        return std::make_pair(MBBP->getNumber(), MBBQ->getNumber());
+      });
+
+  ExceptionSectionRange = SectionRange(MBBS_Exception);
+  ColdSectionRange = SectionRange(llvm::MBBS_Cold);
+}
+
+/// This is used with -fbasicblock-sections or -fbasicblock-labels option.
+/// A unary encoding of basic block labels is done to keep ".strtab" sizes
+/// small.
+void MachineFunction::createBBLabels() {
+  const TargetInstrInfo *TII = getSubtarget().getInstrInfo();
+  this->BBSectionsSymbolPrefix.resize(getNumBlockIDs(), 'a');
+  for (auto MBBI = begin(), E = end(); MBBI != E; ++MBBI) {
+    assert(
+        (MBBI->getNumber() >= 0 && MBBI->getNumber() < (int)getNumBlockIDs()) &&
+        "BasicBlock number was out of range!");
+    // 'a' - Normal block.
+    // 'r' - Return block.
+    // 'l' - Landing Pad.
+    // 'L' - Return and landing pad.
+    bool isEHPad = MBBI->isEHPad();
+    bool isRetBlock = MBBI->isReturnBlock() && !TII->isTailCall(MBBI->back());
+    char type = 'a';
+    if (isEHPad && isRetBlock)
+      type = 'L';
+    else if (isEHPad)
+      type = 'l';
+    else if (isRetBlock)
+      type = 'r';
+    BBSectionsSymbolPrefix[MBBI->getNumber()] = type;
+  }
+}
+
 /// Allocate a new MachineInstr. Use this instead of `new MachineInstr'.
 MachineInstr *MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
                                                   const DebugLoc &DL,
diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp
index 19bcb09530f7c..d63f194f7e662 100644
--- a/llvm/lib/CodeGen/MachineOutliner.cpp
+++ b/llvm/lib/CodeGen/MachineOutliner.cpp
@@ -97,6 +97,13 @@ static cl::opt<bool> EnableLinkOnceODROutlining(
     cl::desc("Enable the machine outliner on linkonceodr functions"),
     cl::init(false));
 
+// Set the number of times to repeatedly apply outlining.
+// Defaults to 1, but more repetitions can save additional size.
+static cl::opt<unsigned>
+    NumRepeat("machine-outline-runs", cl::Hidden,
+              cl::desc("The number of times to apply machine outlining"),
+              cl::init(1));
+
 namespace {
 
 /// Represents an undefined index in the suffix tree.
@@ -842,6 +849,9 @@ struct MachineOutliner : public ModulePass {
   /// linkonceodr linkage.
   bool OutlineFromLinkOnceODRs = false;
 
+  /// The current repeat number of machine outlining.
+  unsigned OutlineRepeatedNum = 0;
+
   /// Set to true if the outliner should run on all functions in the module
   /// considered safe for outlining.
   /// Set to true by default for compatibility with llc's -run-pass option.
@@ -900,9 +910,12 @@ struct MachineOutliner : public ModulePass {
                                           InstructionMapper &Mapper,
                                           unsigned Name);
 
-  /// Calls 'doOutline()'.
+  /// Calls runOnceOnModule NumRepeat times
   bool runOnModule(Module &M) override;
 
+  /// Calls 'doOutline()'.
+  bool runOnceOnModule(Module &M, unsigned Iter);
+
   /// Construct a suffix tree on the instructions in \p M and outline repeated
   /// strings from that tree.
   bool doOutline(Module &M, unsigned &OutlinedFunctionNum);
@@ -1099,7 +1112,13 @@ MachineFunction *MachineOutliner::createOutlinedFunction(
   // Create the function name. This should be unique.
   // FIXME: We should have a better naming scheme. This should be stable,
   // regardless of changes to the outliner's cost model/traversal order.
-  std::string FunctionName = ("OUTLINED_FUNCTION_" + Twine(Name)).str();
+  std::string FunctionName;
+  if (OutlineRepeatedNum > 0)
+    FunctionName = ("OUTLINED_FUNCTION_" + Twine(OutlineRepeatedNum + 1) + "_" +
+                    Twine(Name))
+                       .str();
+  else
+    FunctionName = ("OUTLINED_FUNCTION_" + Twine(Name)).str();
 
   // Create the function using an IR-level function.
   LLVMContext &C = M.getContext();
@@ -1438,12 +1457,14 @@ void MachineOutliner::emitInstrCountChangedRemark(
   }
 }
 
-bool MachineOutliner::runOnModule(Module &M) {
+bool MachineOutliner::runOnceOnModule(Module &M, unsigned Iter) {
   // Check if there's anything in the module. If it's empty, then there's
   // nothing to outline.
   if (M.empty())
     return false;
 
+  OutlineRepeatedNum = Iter;
+
   // Number to append to the current outlined function.
   unsigned OutlinedFunctionNum = 0;
 
@@ -1507,3 +1528,23 @@ bool MachineOutliner::doOutline(Module &M, unsigned &OutlinedFunctionNum) {
 
   return OutlinedSomething;
 }
+
+// Apply machine outlining for NumRepeat times.
+bool MachineOutliner::runOnModule(Module &M) {
+  if (NumRepeat < 1)
+    report_fatal_error("Expect NumRepeat for machine outlining "
+                       "to be greater than or equal to 1!\n");
+
+  bool Changed = false;
+  for (unsigned I = 0; I < NumRepeat; I++) {
+    if (!runOnceOnModule(M, I)) {
+      LLVM_DEBUG(dbgs() << "Stopped outlining at iteration " << I
+                        << " because no changes were found.\n";);
+      return Changed;
+    }
+    Changed = true;
+  }
+  LLVM_DEBUG(dbgs() << "Stopped outlining because iteration is "
+                       "equal to " << NumRepeat << "\n";);
+  return Changed;
+}
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 270ba125df005..12f1bafe1fb2c 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -610,30 +610,54 @@ bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const {
   return false;
 }
 
-void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
+void MachineRegisterInfo::initUpdatedCSRs() {
+  if (IsUpdatedCSRsInitialized)
+    return;
 
   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
-  assert(Reg && (Reg < TRI->getNumRegs()) &&
-         "Trying to disable an invalid register");
+  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
+  for (const MCPhysReg *I = CSR; *I; ++I)
+    UpdatedCSRs.push_back(*I);
 
-  if (!IsUpdatedCSRsInitialized) {
-    const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
-    for (const MCPhysReg *I = CSR; *I; ++I)
-      UpdatedCSRs.push_back(*I);
+  // Zero value represents the end of the register list
+  // (no more registers should be pushed).
+  UpdatedCSRs.push_back(0);
 
-    // Zero value represents the end of the register list
-    // (no more registers should be pushed).
-    UpdatedCSRs.push_back(0);
+  IsUpdatedCSRsInitialized = true;
+}
 
-    IsUpdatedCSRsInitialized = true;
-  }
+void MachineRegisterInfo::disableCalleeSavedRegister(Register Reg) {
+  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
+  assert(Reg && (Reg < TRI->getNumRegs()) &&
+         "Trying to disable an invalid register");
+
+  initUpdatedCSRs();
 
-  // Remove the register (and its aliases from the list).
+  // Remove the register (and its aliases) from the CSR list.
   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
                       UpdatedCSRs.end());
 }
 
+void MachineRegisterInfo::enableCalleeSavedRegister(Register Reg) {
+  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
+  assert(Reg && (Reg < TRI->getNumRegs()) &&
+         "Trying to disable an invalid register");
+
+  initUpdatedCSRs();
+
+  // Remove the null terminator from the end of the list.
+  assert(UpdatedCSRs.back() == 0);
+  UpdatedCSRs.pop_back();
+
+  // Add the register (and its sub-registers) to the CSR list.
+  for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI)
+    UpdatedCSRs.push_back(*SRI);
+
+  // Put the null terminator back.
+  UpdatedCSRs.push_back(0);
+}
+
 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
   if (IsUpdatedCSRsInitialized)
     return UpdatedCSRs.data();
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 889d0261c7cee..b12ccc40eb61f 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -453,6 +453,8 @@ static void assignCalleeSavedSpillSlots(MachineFunction &F,
         FrameIdx = MFI.CreateFixedSpillStackObject(Size, FixedSlot->Offset);
       }
 
+      LLVM_DEBUG(dbgs() << "Assigned " << RegInfo->getName(Reg)
+                        << " to spill slot " << FrameIdx << "\n");
       CS.setFrameIdx(FrameIdx);
     }
   }
@@ -635,22 +637,21 @@ void PEI::spillCalleeSavedRegs(MachineFunction &MF) {
 }
 
 /// AdjustStackOffset - Helper function used to adjust the stack frame offset.
-static inline void
-AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx,
-                  bool StackGrowsDown, int64_t &Offset,
-                  unsigned &MaxAlign, unsigned Skew) {
+static inline void AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx,
+                                     bool StackGrowsDown, int64_t &Offset,
+                                     Align &MaxAlign, unsigned Skew) {
   // If the stack grows down, add the object size to find the lowest address.
   if (StackGrowsDown)
     Offset += MFI.getObjectSize(FrameIdx);
 
-  unsigned Align = MFI.getObjectAlignment(FrameIdx);
+  Align Alignment = MFI.getObjectAlign(FrameIdx);
 
   // If the alignment of this object is greater than that of the stack, then
   // increase the stack alignment to match.
-  MaxAlign = std::max(MaxAlign, Align);
+  MaxAlign = std::max(MaxAlign, Alignment);
 
   // Adjust to alignment boundary.
-  Offset = alignTo(Offset, Align, Skew);
+  Offset = alignTo(Offset, Alignment, Skew);
 
   if (StackGrowsDown) {
     LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset
@@ -710,7 +711,7 @@ computeFreeStackSlots(MachineFrameInfo &MFI, bool StackGrowsDown,
 /// Assign frame object to an unused portion of the stack in the fixed stack
 /// object range.  Return true if the allocation was successful.
 static inline bool scavengeStackSlot(MachineFrameInfo &MFI, int FrameIdx,
-                                     bool StackGrowsDown, unsigned MaxAlign,
+                                     bool StackGrowsDown, Align MaxAlign,
                                      BitVector &StackBytesFree) {
   if (MFI.isVariableSizedObjectIndex(FrameIdx))
     return false;
@@ -722,7 +723,7 @@ static inline bool scavengeStackSlot(MachineFrameInfo &MFI, int FrameIdx,
     return false;
   }
 
-  unsigned ObjAlign = MFI.getObjectAlignment(FrameIdx);
+  Align ObjAlign = MFI.getObjectAlign(FrameIdx);
   if (ObjAlign > MaxAlign)
     return false;
 
@@ -769,11 +770,11 @@ static inline bool scavengeStackSlot(MachineFrameInfo &MFI, int FrameIdx,
 
 /// AssignProtectedObjSet - Helper function to assign large stack objects (i.e.,
 /// those required to be close to the Stack Protector) to stack offsets.
-static void
-AssignProtectedObjSet(const StackObjSet &UnassignedObjs,
-                      SmallSet<int, 16> &ProtectedObjs,
-                      MachineFrameInfo &MFI, bool StackGrowsDown,
-                      int64_t &Offset, unsigned &MaxAlign, unsigned Skew) {
+static void AssignProtectedObjSet(const StackObjSet &UnassignedObjs,
+                                  SmallSet<int, 16> &ProtectedObjs,
+                                  MachineFrameInfo &MFI, bool StackGrowsDown,
+                                  int64_t &Offset, Align &MaxAlign,
+                                  unsigned Skew) {
 
   for (StackObjSet::const_iterator I = UnassignedObjs.begin(),
         E = UnassignedObjs.end(); I != E; ++I) {
@@ -811,7 +812,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
   for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i)
     if (!MFI.isDeadObjectIndex(i) &&
         MFI.getStackID(i) == TargetStackID::Default)
-      assert(MFI.getObjectAlignment(i) <= MFI.getMaxAlignment() &&
+      assert(MFI.getObjectAlign(i) <= MFI.getMaxAlign() &&
              "MaxAlignment is invalid");
 #endif
 
@@ -850,9 +851,8 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
       // address of the object.
       Offset += MFI.getObjectSize(i);
 
-      unsigned Align = MFI.getObjectAlignment(i);
       // Adjust to alignment boundary
-      Offset = alignTo(Offset, Align, Skew);
+      Offset = alignTo(Offset, MFI.getObjectAlign(i), Skew);
 
       LLVM_DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << -Offset << "]\n");
       MFI.setObjectOffset(i, -Offset);        // Set the computed offset
@@ -867,9 +867,8 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
       if (MFI.isDeadObjectIndex(i))
         continue;
 
-      unsigned Align = MFI.getObjectAlignment(i);
       // Adjust to alignment boundary
-      Offset = alignTo(Offset, Align, Skew);
+      Offset = alignTo(Offset, MFI.getObjectAlign(i), Skew);
 
       LLVM_DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << Offset << "]\n");
       MFI.setObjectOffset(i, Offset);
@@ -880,7 +879,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
   // FixedCSEnd is the stack offset to the end of the fixed and callee-save
   // stack area.
   int64_t FixedCSEnd = Offset;
-  unsigned MaxAlign = MFI.getMaxAlignment();
+  Align MaxAlign = MFI.getMaxAlign();
 
   // Make sure the special register scavenging spill slot is closest to the
   // incoming stack pointer if a frame pointer is required and is closer
@@ -903,10 +902,10 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
   // frame index registers. Functions which don't want/need this optimization
   // will continue to use the existing code path.
   if (MFI.getUseLocalStackAllocationBlock()) {
-    unsigned Align = MFI.getLocalFrameMaxAlign().value();
+    Align Alignment = MFI.getLocalFrameMaxAlign();
 
     // Adjust to alignment boundary.
-    Offset = alignTo(Offset, Align, Skew);
+    Offset = alignTo(Offset, Alignment, Skew);
 
     LLVM_DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n");
 
@@ -921,7 +920,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
     // Allocate the local block
     Offset += MFI.getLocalFrameSize();
 
-    MaxAlign = std::max(Align, MaxAlign);
+    MaxAlign = std::max(Alignment, MaxAlign);
   }
 
   // Retrieve the Exception Handler registration node.
@@ -1072,12 +1071,12 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
     // ensure that the callee's frame or the alloca data is suitably aligned;
     // otherwise, for leaf functions, align to the TransientStackAlignment
     // value.
-    unsigned StackAlign;
+    Align StackAlign;
     if (MFI.adjustsStack() || MFI.hasVarSizedObjects() ||
         (RegInfo->needsStackRealignment(MF) && MFI.getObjectIndexEnd() != 0))
-      StackAlign = TFI.getStackAlignment();
+      StackAlign = TFI.getStackAlign();
     else
-      StackAlign = TFI.getTransientStackAlignment();
+      StackAlign = TFI.getTransientStackAlign();
 
     // If the frame pointer is eliminated, all frame offsets will be relative to
     // SP not FP. Align to MaxAlign so this works.
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/CodeGen/RDFGraph.cpp
similarity index 99%
rename from llvm/lib/Target/Hexagon/RDFGraph.cpp
rename to llvm/lib/CodeGen/RDFGraph.cpp
index 0cb35dc988196..437a6b0300967 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/CodeGen/RDFGraph.cpp
@@ -8,8 +8,6 @@
 //
 // Target-independent, SSA-based data flow graph for register data flow (RDF).
 //
-#include "RDFGraph.h"
-#include "RDFRegisters.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
@@ -20,6 +18,8 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -753,8 +753,10 @@ RegisterSet DataFlowGraph::getLandingPadLiveIns() const {
   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
   if (RegisterId R = TLI.getExceptionPointerRegister(PF))
     LR.insert(RegisterRef(R));
-  if (RegisterId R = TLI.getExceptionSelectorRegister(PF))
-    LR.insert(RegisterRef(R));
+  if (!isFuncletEHPersonality(classifyEHPersonality(PF))) {
+    if (RegisterId R = TLI.getExceptionSelectorRegister(PF))
+      LR.insert(RegisterRef(R));
+  }
   return LR;
 }
 
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/CodeGen/RDFLiveness.cpp
similarity index 99%
rename from llvm/lib/Target/Hexagon/RDFLiveness.cpp
rename to llvm/lib/CodeGen/RDFLiveness.cpp
index e2c007c9d01af..0bcd27f8ea452 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/CodeGen/RDFLiveness.cpp
@@ -22,9 +22,6 @@
 // and Embedded Architectures and Compilers", 8 (4),
 // <10.1145/2086696.2086706>. <hal-00647369>
 //
-#include "RDFLiveness.h"
-#include "RDFGraph.h"
-#include "RDFRegisters.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
@@ -33,6 +30,9 @@
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/RDFLiveness.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/MC/LaneBitmask.h"
 #include "llvm/MC/MCRegisterInfo.h"
diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
similarity index 99%
rename from llvm/lib/Target/Hexagon/RDFRegisters.cpp
rename to llvm/lib/CodeGen/RDFRegisters.cpp
index b5675784e34b8..bd8661816e718 100644
--- a/llvm/lib/Target/Hexagon/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -6,11 +6,11 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "RDFRegisters.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/MC/LaneBitmask.h"
 #include "llvm/MC/MCRegisterInfo.h"
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 36fc540fe3163..254669b364708 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -555,6 +555,10 @@ namespace {
                               SDValue InnerPos, SDValue InnerNeg,
                               unsigned PosOpcode, unsigned NegOpcode,
                               const SDLoc &DL);
+    SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
+                              SDValue InnerPos, SDValue InnerNeg,
+                              unsigned PosOpcode, unsigned NegOpcode,
+                              const SDLoc &DL);
     SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
     SDValue MatchLoadCombine(SDNode *N);
     SDValue MatchStoreCombine(StoreSDNode *N);
@@ -6265,8 +6269,12 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
   //              EltSize & Mask == NegC & Mask
   //
   // (because "x & Mask" is a truncation and distributes through subtraction).
+  //
+  // We also need to account for a potential truncation of NegOp1 if the amount
+  // has already been legalized to a shift amount type.
   APInt Width;
-  if (Pos == NegOp1)
+  if ((Pos == NegOp1) ||
+      (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0)))
     Width = NegC->getAPIntValue();
 
   // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
@@ -6319,6 +6327,33 @@ SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
   return SDValue();
 }
 
+// A subroutine of MatchRotate used once we have found an OR of two opposite
+// shifts of N0 + N1.  If Neg == <operand size> - Pos then the OR reduces
+// to both (PosOpcode N0, N1, Pos) and (NegOpcode N0, N1, Neg), with the
+// former being preferred if supported.  InnerPos and InnerNeg are Pos and
+// Neg with outer conversions stripped away.
+// TODO: Merge with MatchRotatePosNeg.
+SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos,
+                                       SDValue Neg, SDValue InnerPos,
+                                       SDValue InnerNeg, unsigned PosOpcode,
+                                       unsigned NegOpcode, const SDLoc &DL) {
+  // fold (or (shl x0, (*ext y)),
+  //          (srl x1, (*ext (sub 32, y)))) ->
+  //   (fshl x0, x1, y) or (fshr x0, x1, (sub 32, y))
+  //
+  // fold (or (shl x0, (*ext (sub 32, y))),
+  //          (srl x1, (*ext y))) ->
+  //   (fshr x0, x1, y) or (fshl x0, x1, (sub 32, y))
+  EVT VT = N0.getValueType();
+  if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits(), DAG)) {
+    bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
+    return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, N0, N1,
+                       HasPos ? Pos : Neg);
+  }
+
+  return SDValue();
+}
+
 // MatchRotate - Handle an 'or' of two operands.  If this is one of the many
 // idioms for rotate, and if the target supports rotation instructions, generate
 // a rot[lr]. This also matches funnel shift patterns, similar to rotation but
@@ -6444,10 +6479,6 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
     return Res;
   }
 
-  // TODO: Handle variable funnel shifts.
-  if (!IsRotate)
-    return SDValue();
-
   // If there is a mask here, and we have a variable shift, we can't be sure
   // that we're masking out the right stuff.
   if (LHSMask.getNode() || RHSMask.getNode())
@@ -6468,13 +6499,29 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
     RExtOp0 = RHSShiftAmt.getOperand(0);
   }
 
-  SDValue TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
-                                   LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
+  if (IsRotate && (HasROTL || HasROTR)) {
+    SDValue TryL =
+        MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt, LExtOp0,
+                          RExtOp0, ISD::ROTL, ISD::ROTR, DL);
+    if (TryL)
+      return TryL;
+
+    SDValue TryR =
+        MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt, RExtOp0,
+                          LExtOp0, ISD::ROTR, ISD::ROTL, DL);
+    if (TryR)
+      return TryR;
+  }
+
+  SDValue TryL =
+      MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, LHSShiftAmt, RHSShiftAmt,
+                        LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL);
   if (TryL)
     return TryL;
 
-  SDValue TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
-                                   RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
+  SDValue TryR =
+      MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
+                        RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL);
   if (TryR)
     return TryR;
 
@@ -11936,13 +11983,24 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
     return SDValue();
   };
 
-  // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
-  if (SDValue V = tryToFoldXYSubZ(N0, N1))
-    return V;
-
-  // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
-  if (SDValue V = tryToFoldXSubYZ(N0, N1))
-    return V;
+  // If we have two choices trying to fold (fsub (fmul u, v), (fmul x, y)),
+  // prefer to fold the multiply with fewer uses.
+  if (isContractableFMUL(N0) && isContractableFMUL(N1) &&
+      (N0.getNode()->use_size() > N1.getNode()->use_size())) {
+    // fold (fsub (fmul a, b), (fmul c, d)) -> (fma (fneg c), d, (fmul a, b))
+    if (SDValue V = tryToFoldXSubYZ(N0, N1))
+      return V;
+    // fold (fsub (fmul a, b), (fmul c, d)) -> (fma a, b, (fneg (fmul c, d)))
+    if (SDValue V = tryToFoldXYSubZ(N0, N1))
+      return V;
+  } else {
+    // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
+    if (SDValue V = tryToFoldXYSubZ(N0, N1))
+      return V;
+    // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
+    if (SDValue V = tryToFoldXSubYZ(N0, N1))
+      return V;
+  }
 
   // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
   if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) &&
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index dcd072d7631f5..5b673486af153 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7435,7 +7435,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
-                              ArrayRef<SDValue> Ops) {
+                              ArrayRef<SDValue> Ops, const SDNodeFlags Flags) {
   if (VTList.NumVTs == 1)
     return getNode(Opcode, DL, VTList.VTs[0], Ops);
 
@@ -7504,6 +7504,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
       return SDValue(E, 0);
 
     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTList);
+    N->setFlags(Flags);
     createOperands(N, Ops);
     CSEMap.InsertNode(N, IP);
   } else {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index fed02b47cf2c3..29f15095af583 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1113,29 +1113,23 @@ void SelectionDAGBuilder::visit(const Instruction &I) {
   visit(I.getOpcode(), I);
 
   if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) {
-    // Propagate the fast-math-flags of this IR instruction to the DAG node that
-    // maps to this instruction.
-    // TODO: We could handle all flags (nsw, etc) here.
-    // TODO: If an IR instruction maps to >1 node, only the final node will have
-    //       flags set.
-    if (SDNode *Node = getNodeForIRValue(&I)) {
-      SDNodeFlags IncomingFlags;
-      IncomingFlags.copyFMF(*FPMO);
-      if (!Node->getFlags().isDefined())
-        Node->setFlags(IncomingFlags);
-      else
-        Node->intersectFlagsWith(IncomingFlags);
-    }
-  }
-  // Constrained FP intrinsics with fpexcept.ignore should also get
-  // the NoFPExcept flag.
-  if (auto *FPI = dyn_cast<ConstrainedFPIntrinsic>(&I))
-    if (FPI->getExceptionBehavior() == fp::ExceptionBehavior::ebIgnore)
+    // ConstrainedFPIntrinsics handle their own FMF.
+    if (!isa<ConstrainedFPIntrinsic>(&I)) {
+      // Propagate the fast-math-flags of this IR instruction to the DAG node that
+      // maps to this instruction.
+      // TODO: We could handle all flags (nsw, etc) here.
+      // TODO: If an IR instruction maps to >1 node, only the final node will have
+      //       flags set.
       if (SDNode *Node = getNodeForIRValue(&I)) {
-        SDNodeFlags Flags = Node->getFlags();
-        Flags.setNoFPExcept(true);
-        Node->setFlags(Flags);
+        SDNodeFlags IncomingFlags;
+        IncomingFlags.copyFMF(*FPMO);
+        if (!Node->getFlags().isDefined())
+          Node->setFlags(IncomingFlags);
+        else
+          Node->intersectFlagsWith(IncomingFlags);
       }
+    }
+  }
 
   if (!I.isTerminator() && !HasTailCall &&
       !isStatepoint(&I)) // statepoints handle their exports internally
@@ -4377,7 +4371,7 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
 // are looking for. If first operand of the GEP is a splat vector - we
 // extract the splat value and use it as a uniform base.
 // In all other cases the function returns 'false'.
-static bool getUniformBase(const Value *&Ptr, SDValue &Base, SDValue &Index,
+static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index,
                            ISD::MemIndexType &IndexType, SDValue &Scale,
                            SelectionDAGBuilder *SDB) {
   SelectionDAG& DAG = SDB->DAG;
@@ -4388,11 +4382,12 @@ static bool getUniformBase(const Value *&Ptr, SDValue &Base, SDValue &Index,
   if (!GEP)
     return false;
 
-  const Value *GEPPtr = GEP->getPointerOperand();
-  if (!GEPPtr->getType()->isVectorTy())
-    Ptr = GEPPtr;
-  else if (!(Ptr = getSplatValue(GEPPtr)))
-    return false;
+  const Value *BasePtr = GEP->getPointerOperand();
+  if (BasePtr->getType()->isVectorTy()) {
+    BasePtr = getSplatValue(BasePtr);
+    if (!BasePtr)
+      return false;
+  }
 
   unsigned FinalIndex = GEP->getNumOperands() - 1;
   Value *IndexVal = GEP->getOperand(FinalIndex);
@@ -4412,7 +4407,7 @@ static bool getUniformBase(const Value *&Ptr, SDValue &Base, SDValue &Index,
 
   // The operands of the GEP may be defined in another basic block.
   // In this case we'll not find nodes for the operands.
-  if (!SDB->findValue(Ptr))
+  if (!SDB->findValue(BasePtr))
     return false;
   Constant *C = dyn_cast<Constant>(IndexVal);
   if (!C && !SDB->findValue(IndexVal))
@@ -4434,7 +4429,7 @@ static bool getUniformBase(const Value *&Ptr, SDValue &Base, SDValue &Index,
                 SDB->getCurSDLoc(), TLI.getPointerTy(DL));
     Index = SDB->getValue(IndexVal);
   }
-  Base = SDB->getValue(Ptr);
+  Base = SDB->getValue(BasePtr);
   IndexType = ISD::SIGNED_SCALED;
 
   if (STy || !Index.getValueType().isVector()) {
@@ -4465,17 +4460,15 @@ void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
   SDValue Index;
   ISD::MemIndexType IndexType;
   SDValue Scale;
-  const Value *BasePtr = Ptr;
-  bool UniformBase = getUniformBase(BasePtr, Base, Index, IndexType, Scale,
-                                    this);
+  bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this);
 
-  const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
+  unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
   MachineMemOperand *MMO = DAG.getMachineFunction().
-    getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
+    getMachineMemOperand(MachinePointerInfo(AS),
                          MachineMemOperand::MOStore,
                          // TODO: Make MachineMemOperands aware of scalable
                          // vectors.
-                         VT.getStoreSize().getKnownMinSize(),
+                         MemoryLocation::UnknownSize,
                          Alignment, AAInfo);
   if (!UniformBase) {
     Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
@@ -4582,28 +4575,15 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
   SDValue Index;
   ISD::MemIndexType IndexType;
   SDValue Scale;
-  const Value *BasePtr = Ptr;
-  bool UniformBase = getUniformBase(BasePtr, Base, Index, IndexType, Scale,
-                                    this);
-  bool ConstantMemory = false;
-  if (UniformBase && AA &&
-      AA->pointsToConstantMemory(
-          MemoryLocation(BasePtr,
-                         LocationSize::precise(
-                             DAG.getDataLayout().getTypeStoreSize(I.getType())),
-                         AAInfo))) {
-    // Do not serialize (non-volatile) loads of constant memory with anything.
-    Root = DAG.getEntryNode();
-    ConstantMemory = true;
-  }
-
+  bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this);
+  unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
   MachineMemOperand *MMO =
     DAG.getMachineFunction().
-    getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
+    getMachineMemOperand(MachinePointerInfo(AS),
                          MachineMemOperand::MOLoad,
                          // TODO: Make MachineMemOperands aware of scalable
                          // vectors.
-                         VT.getStoreSize().getKnownMinSize(),
+                         MemoryLocation::UnknownSize,
                          Alignment, AAInfo, Ranges);
 
   if (!UniformBase) {
@@ -4616,9 +4596,7 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
   SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
                                        Ops, MMO, IndexType);
 
-  SDValue OutChain = Gather.getValue(1);
-  if (!ConstantMemory)
-    PendingLoads.push_back(OutChain);
+  PendingLoads.push_back(Gather.getValue(1));
   setValue(&I, Gather);
 }
 
@@ -7080,6 +7058,13 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
   SDVTList VTs = DAG.getVTList(ValueVTs);
   fp::ExceptionBehavior EB = FPI.getExceptionBehavior().getValue();
 
+  SDNodeFlags Flags;
+  if (EB == fp::ExceptionBehavior::ebIgnore)
+    Flags.setNoFPExcept(true);
+
+  if (auto *FPOp = dyn_cast<FPMathOperator>(&FPI))
+    Flags.copyFMF(*FPOp);
+
   unsigned Opcode;
   switch (FPI.getIntrinsicID()) {
   default: llvm_unreachable("Impossible intrinsic");  // Can't reach here.
@@ -7095,7 +7080,7 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
         !TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(),
                                         ValueVTs[0])) {
       Opers.pop_back();
-      SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, sdl, VTs, Opers);
+      SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, sdl, VTs, Opers, Flags);
       pushOutChain(Mul, EB);
       Opcode = ISD::STRICT_FADD;
       Opers.clear();
@@ -7123,7 +7108,7 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
   }
   }
 
-  SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers);
+  SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers, Flags);
   pushOutChain(Result, EB);
 
   SDValue FPResult = Result.getValue(0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7b27eccbfc6ca..6148b24e3e000 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1634,15 +1634,32 @@ bool TargetLowering::SimplifyDemandedBits(
       Known.One |= Known2.One;
       Known.Zero |= Known2.Zero;
     }
+
+    // For pow-2 bitwidths we only demand the bottom modulo amt bits.
+    if (isPowerOf2_32(BitWidth)) {
+      APInt DemandedAmtBits(Op2.getScalarValueSizeInBits(), BitWidth - 1);
+      if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts,
+                               Known2, TLO, Depth + 1))
+        return true;
+    }
     break;
   }
   case ISD::ROTL:
   case ISD::ROTR: {
     SDValue Op0 = Op.getOperand(0);
+    SDValue Op1 = Op.getOperand(1);
 
     // If we're rotating an 0/-1 value, then it stays an 0/-1 value.
     if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1))
       return TLO.CombineTo(Op, Op0);
+
+    // For pow-2 bitwidths we only demand the bottom modulo amt bits.
+    if (isPowerOf2_32(BitWidth)) {
+      APInt DemandedAmtBits(Op1.getScalarValueSizeInBits(), BitWidth - 1);
+      if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO,
+                               Depth + 1))
+        return true;
+    }
     break;
   }
   case ISD::BITREVERSE: {
diff --git a/llvm/lib/CodeGen/StackProtector.cpp b/llvm/lib/CodeGen/StackProtector.cpp
index 4e2189884bb19..a343791807e64 100644
--- a/llvm/lib/CodeGen/StackProtector.cpp
+++ b/llvm/lib/CodeGen/StackProtector.cpp
@@ -18,6 +18,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/BranchProbabilityInfo.h"
 #include "llvm/Analysis/EHPersonalities.h"
+#include "llvm/Analysis/MemoryLocation.h"
 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLowering.h"
@@ -161,9 +162,16 @@ bool StackProtector::ContainsProtectableArray(Type *Ty, bool &IsLarge,
   return NeedsProtector;
 }
 
-bool StackProtector::HasAddressTaken(const Instruction *AI) {
+bool StackProtector::HasAddressTaken(const Instruction *AI,
+                                     uint64_t AllocSize) {
+  const DataLayout &DL = M->getDataLayout();
   for (const User *U : AI->users()) {
     const auto *I = cast<Instruction>(U);
+    // If this instruction accesses memory make sure it doesn't access beyond
+    // the bounds of the allocated object.
+    Optional<MemoryLocation> MemLoc = MemoryLocation::getOrNone(I);
+    if (MemLoc.hasValue() && MemLoc->Size.getValue() > AllocSize)
+      return true;
     switch (I->getOpcode()) {
     case Instruction::Store:
       if (AI == cast<StoreInst>(I)->getValueOperand())
@@ -189,11 +197,26 @@ bool StackProtector::HasAddressTaken(const Instruction *AI) {
     }
     case Instruction::Invoke:
       return true;
+    case Instruction::GetElementPtr: {
+      // If the GEP offset is out-of-bounds, or is non-constant and so has to be
+      // assumed to be potentially out-of-bounds, then any memory access that
+      // would use it could also be out-of-bounds meaning stack protection is
+      // required.
+      const GetElementPtrInst *GEP = cast<GetElementPtrInst>(I);
+      unsigned TypeSize = DL.getIndexTypeSizeInBits(I->getType());
+      APInt Offset(TypeSize, 0);
+      APInt MaxOffset(TypeSize, AllocSize);
+      if (!GEP->accumulateConstantOffset(DL, Offset) || Offset.ugt(MaxOffset))
+        return true;
+      // Adjust AllocSize to be the space remaining after this offset.
+      if (HasAddressTaken(I, AllocSize - Offset.getLimitedValue()))
+        return true;
+      break;
+    }
     case Instruction::BitCast:
-    case Instruction::GetElementPtr:
     case Instruction::Select:
     case Instruction::AddrSpaceCast:
-      if (HasAddressTaken(I))
+      if (HasAddressTaken(I, AllocSize))
         return true;
       break;
     case Instruction::PHI: {
@@ -201,7 +224,7 @@ bool StackProtector::HasAddressTaken(const Instruction *AI) {
       // they are only visited once.
       const auto *PN = cast<PHINode>(I);
       if (VisitedPHIs.insert(PN).second)
-        if (HasAddressTaken(PN))
+        if (HasAddressTaken(PN, AllocSize))
           return true;
       break;
     }
@@ -330,7 +353,8 @@ bool StackProtector::RequiresStackProtector() {
           continue;
         }
 
-        if (Strong && HasAddressTaken(AI)) {
+        if (Strong && HasAddressTaken(AI, M->getDataLayout().getTypeAllocSize(
+                                              AI->getAllocatedType()))) {
           ++NumAddrTaken;
           Layout.insert(std::make_pair(AI, MachineFrameInfo::SSPLK_AddrOf));
           ORE.emit([&]() {
@@ -342,6 +366,9 @@ bool StackProtector::RequiresStackProtector() {
           });
           NeedsProtector = true;
         }
+        // Clear any PHIs that we visited, to make sure we examine all uses of
+        // any subsequent allocas that we look at.
+        VisitedPHIs.clear();
       }
     }
   }
diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
index 2ce285c85672c..8f1c342202d6d 100644
--- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
@@ -21,6 +21,8 @@
 #include "llvm/BinaryFormat/Dwarf.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/BinaryFormat/MachO.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
 #include "llvm/IR/Comdat.h"
@@ -52,8 +54,8 @@
 #include "llvm/ProfileData/InstrProf.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CodeGen.h"
-#include "llvm/Support/Format.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include <cassert>
@@ -762,6 +764,56 @@ MCSection *TargetLoweringObjectFileELF::getSectionForConstant(
   return DataRelROSection;
 }
 
+/// Returns a unique section for the given machine basic block.
+MCSection *TargetLoweringObjectFileELF::getSectionForMachineBasicBlock(
+    const Function &F, const MachineBasicBlock &MBB,
+    const TargetMachine &TM) const {
+  SmallString<128> Name;
+  Name = (static_cast<MCSectionELF *>(MBB.getParent()->getSection()))
+             ->getSectionName();
+  if (TM.getUniqueBBSectionNames()) {
+    Name += ".";
+    Name += MBB.getSymbol()->getName();
+  }
+  unsigned UniqueID = NextUniqueID++;
+  unsigned Flags = ELF::SHF_ALLOC | ELF::SHF_EXECINSTR;
+  std::string GroupName = "";
+  if (F.hasComdat()) {
+    Flags |= ELF::SHF_GROUP;
+    GroupName = F.getComdat()->getName().str();
+  }
+  return getContext().getELFSection(Name, ELF::SHT_PROGBITS, Flags,
+                                    0 /* Entry Size */, GroupName, UniqueID,
+                                    nullptr);
+}
+
+MCSection *TargetLoweringObjectFileELF::getNamedSectionForMachineBasicBlock(
+    const Function &F, const MachineBasicBlock &MBB, const TargetMachine &TM,
+    const char *Suffix) const {
+  SmallString<128> Name;
+  Name = (static_cast<MCSectionELF *>(MBB.getParent()->getSection()))
+             ->getSectionName();
+
+  // If unique section names is off, explicity add the function name to the
+  // section name to make sure named sections for functions are unique
+  // across the module.
+  if (!TM.getUniqueSectionNames()) {
+    Name += ".";
+    Name += MBB.getParent()->getName();
+  }
+
+  Name += Suffix;
+
+  unsigned Flags = ELF::SHF_ALLOC | ELF::SHF_EXECINSTR;
+  std::string GroupName = "";
+  if (F.hasComdat()) {
+    Flags |= ELF::SHF_GROUP;
+    GroupName = F.getComdat()->getName().str();
+  }
+  return getContext().getELFSection(Name, ELF::SHT_PROGBITS, Flags,
+                                    0 /* Entry Size */, GroupName);
+}
+
 static MCSectionELF *getStaticStructorSection(MCContext &Ctx, bool UseInitArray,
                                               bool IsCtor, unsigned Priority,
                                               const MCSymbol *KeySym) {
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 4485d5ee4f951..a351efc6659d5 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -983,6 +983,9 @@ void TargetPassConfig::addMachinePasses() {
       addPass(createMachineOutlinerPass(RunOnAllFunctions));
   }
 
+  if (TM->getBBSectionsType() != llvm::BasicBlockSection::None)
+    addPass(llvm::createBBSectionsPreparePass(TM->getBBSectionsFuncListBuf()));
+
   // Add passes that directly emit MI after all other MI passes.
   addPreEmitPass2();
 
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 1c582ff06560a..34d1f7e611ab2 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -468,8 +468,8 @@ bool TargetRegisterInfo::needsStackRealignment(
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
   const Function &F = MF.getFunction();
-  unsigned StackAlign = TFI->getStackAlignment();
-  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
+  Align StackAlign = TFI->getStackAlign();
+  bool requiresRealignment = ((MFI.getMaxAlign() > StackAlign) ||
                               F.hasFnAttribute(Attribute::StackAlignment));
   if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
     if (canRealignStack(MF))
diff --git a/llvm/lib/DWARFLinker/DWARFLinker.cpp b/llvm/lib/DWARFLinker/DWARFLinker.cpp
index 66da6265ca531..8464c04f801ec 100644
--- a/llvm/lib/DWARFLinker/DWARFLinker.cpp
+++ b/llvm/lib/DWARFLinker/DWARFLinker.cpp
@@ -923,15 +923,20 @@ void DWARFLinker::DIECloner::cloneExpression(
         OutputBuffer.push_back(Op.getRawOperand(0));
         RefOffset = Op.getRawOperand(1);
       }
-      auto RefDie = Unit.getOrigUnit().getDIEForOffset(RefOffset);
-      uint32_t RefIdx = Unit.getOrigUnit().getDIEIndex(RefDie);
-      CompileUnit::DIEInfo &Info = Unit.getInfo(RefIdx);
       uint32_t Offset = 0;
-      if (DIE *Clone = Info.Clone)
-        Offset = Clone->getOffset();
-      else
-        Linker.reportWarning("base type ref doesn't point to DW_TAG_base_type.",
-                             File);
+      // Look up the base type. For DW_OP_convert, the operand may be 0 to
+      // instead indicate the generic type. The same holds for
+      // DW_OP_reinterpret, which is currently not supported.
+      if (RefOffset > 0 || Op.getCode() != dwarf::DW_OP_convert) {
+        auto RefDie = Unit.getOrigUnit().getDIEForOffset(RefOffset);
+        uint32_t RefIdx = Unit.getOrigUnit().getDIEIndex(RefDie);
+        CompileUnit::DIEInfo &Info = Unit.getInfo(RefIdx);
+        if (DIE *Clone = Info.Clone)
+          Offset = Clone->getOffset();
+        else
+          Linker.reportWarning(
+              "base type ref doesn't point to DW_TAG_base_type.", File);
+      }
       uint8_t ULEB[16];
       unsigned RealSize = encodeULEB128(Offset, ULEB, ULEBsize);
       if (RealSize > ULEBsize) {
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp b/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
index e9463fd53d9aa..0a658034b67b8 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
@@ -266,7 +266,13 @@ bool DWARFExpression::Operation::print(raw_ostream &OS,
       break;
 
     if (Size == Operation::BaseTypeRef && U) {
-      prettyPrintBaseTypeRef(U, OS, Operands, Operand);
+      // For DW_OP_convert the operand may be 0 to indicate that conversion to
+      // the generic type should be done. The same holds for DW_OP_reinterpret,
+      // which is currently not supported.
+      if (Opcode == DW_OP_convert && Operands[Operand] == 0)
+        OS << " 0x0";
+      else
+        prettyPrintBaseTypeRef(U, OS, Operands, Operand);
     } else if (Size == Operation::SizeBlock) {
       uint64_t Offset = Operands[Operand];
       for (unsigned i = 0; i < Operands[Operand - 1]; ++i)
@@ -320,6 +326,12 @@ bool DWARFExpression::Operation::verify(DWARFUnit *U) {
       break;
 
     if (Size == Operation::BaseTypeRef) {
+      // For DW_OP_convert the operand may be 0 to indicate that conversion to
+      // the generic type should be done, so don't look up a base type in that
+      // case. The same holds for DW_OP_reinterpret, which is currently not
+      // supported.
+      if (Opcode == DW_OP_convert && Operands[Operand] == 0)
+        continue;
       auto Die = U->getDIEForOffset(U->getOffset() + Operands[Operand]);
       if (!Die || Die.getTag() != dwarf::DW_TAG_base_type) {
         Error = true;
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
index 440ab4174a565..e869547964acb 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -554,7 +554,7 @@ void RuntimeDyldELF::setMipsABI(const ObjectFile &Obj) {
     IsMipsO32ABI = AbiVariant & ELF::EF_MIPS_ABI_O32;
     IsMipsN32ABI = AbiVariant & ELF::EF_MIPS_ABI2;
   }
-  IsMipsN64ABI = Obj.getFileFormatName().equals("ELF64-mips");
+  IsMipsN64ABI = Obj.getFileFormatName().equals("elf64-mips");
 }
 
 // Return the .TOC. section and offset.
diff --git a/llvm/lib/FuzzMutate/Operations.cpp b/llvm/lib/FuzzMutate/Operations.cpp
index cf55d09caf7e6..43255e16140ad 100644
--- a/llvm/lib/FuzzMutate/Operations.cpp
+++ b/llvm/lib/FuzzMutate/Operations.cpp
@@ -244,20 +244,24 @@ static SourcePred matchScalarInAggregate() {
 
 static SourcePred validInsertValueIndex() {
   auto Pred = [](ArrayRef<Value *> Cur, const Value *V) {
-    auto *CTy = cast<CompositeType>(Cur[0]->getType());
     if (auto *CI = dyn_cast<ConstantInt>(V))
-      if (CI->getBitWidth() == 32 &&
-          CTy->getTypeAtIndex(CI->getZExtValue()) == Cur[1]->getType())
-        return true;
+      if (CI->getBitWidth() == 32) {
+        Type *Indexed = ExtractValueInst::getIndexedType(Cur[0]->getType(),
+                                                         CI->getZExtValue());
+        return Indexed == Cur[1]->getType();
+      }
     return false;
   };
   auto Make = [](ArrayRef<Value *> Cur, ArrayRef<Type *> Ts) {
     std::vector<Constant *> Result;
     auto *Int32Ty = Type::getInt32Ty(Cur[0]->getContext());
-    auto *CTy = cast<CompositeType>(Cur[0]->getType());
-    for (int I = 0, E = getAggregateNumElements(CTy); I < E; ++I)
-      if (CTy->getTypeAtIndex(I) == Cur[1]->getType())
+    auto *BaseTy = Cur[0]->getType();
+    int I = 0;
+    while (Type *Indexed = ExtractValueInst::getIndexedType(BaseTy, I)) {
+      if (Indexed == Cur[1]->getType())
         Result.push_back(ConstantInt::get(Int32Ty, I));
+      ++I;
+    }
     return Result;
   };
   return {Pred, Make};
diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp
index dc78c5537befc..3e2e74c31fc0a 100644
--- a/llvm/lib/IR/ConstantFold.cpp
+++ b/llvm/lib/IR/ConstantFold.cpp
@@ -2389,10 +2389,11 @@ Constant *llvm::ConstantFoldGetElementPtr(Type *PointeeTy, Constant *C,
   SmallVector<Constant *, 8> NewIdxs;
   Type *Ty = PointeeTy;
   Type *Prev = C->getType();
+  auto GEPIter = gep_type_begin(PointeeTy, Idxs);
   bool Unknown =
       !isa<ConstantInt>(Idxs[0]) && !isa<ConstantDataVector>(Idxs[0]);
   for (unsigned i = 1, e = Idxs.size(); i != e;
-       Prev = Ty, Ty = cast<CompositeType>(Ty)->getTypeAtIndex(Idxs[i]), ++i) {
+       Prev = Ty, Ty = (++GEPIter).getIndexedType(), ++i) {
     if (!isa<ConstantInt>(Idxs[i]) && !isa<ConstantDataVector>(Idxs[i])) {
       // We don't know if it's in range or not.
       Unknown = true;
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index c68b461f17199..bde4c07e15a31 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -1047,19 +1047,20 @@ static Constant *getSequenceIfElementsMatch(Constant *C,
   return nullptr;
 }
 
-ConstantAggregate::ConstantAggregate(CompositeType *T, ValueTy VT,
+ConstantAggregate::ConstantAggregate(Type *T, ValueTy VT,
                                      ArrayRef<Constant *> V)
     : Constant(T, VT, OperandTraits<ConstantAggregate>::op_end(this) - V.size(),
                V.size()) {
   llvm::copy(V, op_begin());
 
   // Check that types match, unless this is an opaque struct.
-  if (auto *ST = dyn_cast<StructType>(T))
+  if (auto *ST = dyn_cast<StructType>(T)) {
     if (ST->isOpaque())
       return;
-  for (unsigned I = 0, E = V.size(); I != E; ++I)
-    assert(V[I]->getType() == T->getTypeAtIndex(I) &&
-           "Initializer for composite element doesn't match!");
+    for (unsigned I = 0, E = V.size(); I != E; ++I)
+      assert(V[I]->getType() == ST->getTypeAtIndex(I) &&
+             "Initializer for struct element doesn't match!");
+  }
 }
 
 ConstantArray::ConstantArray(ArrayType *T, ArrayRef<Constant *> V)
diff --git a/llvm/lib/IR/DebugInfoMetadata.cpp b/llvm/lib/IR/DebugInfoMetadata.cpp
index 289d4159683bd..740c4bfbbe039 100644
--- a/llvm/lib/IR/DebugInfoMetadata.cpp
+++ b/llvm/lib/IR/DebugInfoMetadata.cpp
@@ -1112,7 +1112,9 @@ DIExpression *DIExpression::append(const DIExpression *Expr,
   }
 
   NewOps.append(Ops.begin(), Ops.end());
-  return DIExpression::get(Expr->getContext(), NewOps);
+  auto *result = DIExpression::get(Expr->getContext(), NewOps);
+  assert(result->isValid() && "concatenated expression is not valid");
+  return result;
 }
 
 DIExpression *DIExpression::appendToStack(const DIExpression *Expr,
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 68eed612e4bfd..0884a24a709e5 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -1659,35 +1659,44 @@ GetElementPtrInst::GetElementPtrInst(const GetElementPtrInst &GEPI)
   SubclassOptionalData = GEPI.SubclassOptionalData;
 }
 
-/// getIndexedType - Returns the type of the element that would be accessed with
-/// a gep instruction with the specified parameters.
-///
-/// The Idxs pointer should point to a continuous piece of memory containing the
-/// indices, either as Value* or uint64_t.
-///
-/// A null type is returned if the indices are invalid for the specified
-/// pointer type.
-///
-template <typename IndexTy>
-static Type *getIndexedTypeInternal(Type *Agg, ArrayRef<IndexTy> IdxList) {
-  // Handle the special case of the empty set index set, which is always valid.
-  if (IdxList.empty())
-    return Agg;
-
-  // If there is at least one index, the top level type must be sized, otherwise
-  // it cannot be 'stepped over'.
-  if (!Agg->isSized())
+Type *GetElementPtrInst::getTypeAtIndex(Type *Ty, Value *Idx) {
+  if (auto Struct = dyn_cast<StructType>(Ty)) {
+    if (!Struct->indexValid(Idx))
+      return nullptr;
+    return Struct->getTypeAtIndex(Idx);
+  }
+  if (!Idx->getType()->isIntOrIntVectorTy())
     return nullptr;
+  if (auto Array = dyn_cast<ArrayType>(Ty))
+    return Array->getElementType();
+  if (auto Vector = dyn_cast<VectorType>(Ty))
+    return Vector->getElementType();
+  return nullptr;
+}
 
-  unsigned CurIdx = 1;
-  for (; CurIdx != IdxList.size(); ++CurIdx) {
-    CompositeType *CT = dyn_cast<CompositeType>(Agg);
-    if (!CT || CT->isPointerTy()) return nullptr;
-    IndexTy Index = IdxList[CurIdx];
-    if (!CT->indexValid(Index)) return nullptr;
-    Agg = CT->getTypeAtIndex(Index);
+Type *GetElementPtrInst::getTypeAtIndex(Type *Ty, uint64_t Idx) {
+  if (auto Struct = dyn_cast<StructType>(Ty)) {
+    if (Idx >= Struct->getNumElements())
+      return nullptr;
+    return Struct->getElementType(Idx);
   }
-  return CurIdx == IdxList.size() ? Agg : nullptr;
+  if (auto Array = dyn_cast<ArrayType>(Ty))
+    return Array->getElementType();
+  if (auto Vector = dyn_cast<VectorType>(Ty))
+    return Vector->getElementType();
+  return nullptr;
+}
+
+template <typename IndexTy>
+static Type *getIndexedTypeInternal(Type *Ty, ArrayRef<IndexTy> IdxList) {
+  if (IdxList.empty())
+    return Ty;
+  for (IndexTy V : IdxList.slice(1)) {
+    Ty = GetElementPtrInst::getTypeAtIndex(Ty, V);
+    if (!Ty)
+      return Ty;
+  }
+  return Ty;
 }
 
 Type *GetElementPtrInst::getIndexedType(Type *Ty, ArrayRef<Value *> IdxList) {
@@ -2220,15 +2229,15 @@ Type *ExtractValueInst::getIndexedType(Type *Agg,
     if (ArrayType *AT = dyn_cast<ArrayType>(Agg)) {
       if (Index >= AT->getNumElements())
         return nullptr;
+      Agg = AT->getElementType();
     } else if (StructType *ST = dyn_cast<StructType>(Agg)) {
       if (Index >= ST->getNumElements())
         return nullptr;
+      Agg = ST->getElementType(Index);
     } else {
       // Not a valid type to index into.
       return nullptr;
     }
-
-    Agg = cast<CompositeType>(Agg)->getTypeAtIndex(Index);
   }
   return const_cast<Type*>(Agg);
 }
diff --git a/llvm/lib/IR/KnowledgeRetention.cpp b/llvm/lib/IR/KnowledgeRetention.cpp
index ba3644f08aa1d..ec6f5712cee54 100644
--- a/llvm/lib/IR/KnowledgeRetention.cpp
+++ b/llvm/lib/IR/KnowledgeRetention.cpp
@@ -286,6 +286,16 @@ RetainedKnowledge llvm::getKnowledgeFromOperandInAssume(CallInst &AssumeCI,
   return Result;
 }
 
+bool llvm::isAssumeWithEmptyBundle(CallInst &CI) {
+  IntrinsicInst &Assume = cast<IntrinsicInst>(CI);
+  assert(Assume.getIntrinsicID() == Intrinsic::assume &&
+         "this function is intended to be used on llvm.assume");
+  return none_of(Assume.bundle_op_infos(),
+                 [](const CallBase::BundleOpInfo &BOI) {
+                   return BOI.Tag->getKey() != "ignore";
+                 });
+}
+
 PreservedAnalyses AssumeBuilderPass::run(Function &F,
                                          FunctionAnalysisManager &AM) {
   for (Instruction &I : instructions(F))
diff --git a/llvm/lib/IR/Operator.cpp b/llvm/lib/IR/Operator.cpp
index 8ba68674d50ed..54b7d56e6353a 100644
--- a/llvm/lib/IR/Operator.cpp
+++ b/llvm/lib/IR/Operator.cpp
@@ -45,6 +45,11 @@ bool GEPOperator::accumulateConstantOffset(const DataLayout &DL,
     if (OpC->isZero())
       continue;
 
+    // Scalable vectors have are multiplied by a runtime constant.
+    if (auto *VecTy = dyn_cast<VectorType>(GTI.getIndexedType()))
+      if (VecTy->isScalable())
+        return false;
+
     // Handle a struct index, which adds its field offset to the pointer.
     if (StructType *STy = GTI.getStructTypeOrNull()) {
       unsigned ElementIdx = OpC->getZExtValue();
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index 3eab5042b5424..e91bc8aa7e708 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -529,52 +529,22 @@ StructType *Module::getTypeByName(StringRef Name) const {
   return getContext().pImpl->NamedStructTypes.lookup(Name);
 }
 
-//===----------------------------------------------------------------------===//
-//                       CompositeType Implementation
-//===----------------------------------------------------------------------===//
-
-Type *CompositeType::getTypeAtIndex(const Value *V) const {
-  if (auto *STy = dyn_cast<StructType>(this)) {
-    unsigned Idx =
-      (unsigned)cast<Constant>(V)->getUniqueInteger().getZExtValue();
-    assert(indexValid(Idx) && "Invalid structure index!");
-    return STy->getElementType(Idx);
-  }
-
-  return cast<SequentialType>(this)->getElementType();
+Type *StructType::getTypeAtIndex(const Value *V) const {
+  unsigned Idx = (unsigned)cast<Constant>(V)->getUniqueInteger().getZExtValue();
+  assert(indexValid(Idx) && "Invalid structure index!");
+  return getElementType(Idx);
 }
 
-Type *CompositeType::getTypeAtIndex(unsigned Idx) const{
-  if (auto *STy = dyn_cast<StructType>(this)) {
-    assert(indexValid(Idx) && "Invalid structure index!");
-    return STy->getElementType(Idx);
-  }
-
-  return cast<SequentialType>(this)->getElementType();
-}
-
-bool CompositeType::indexValid(const Value *V) const {
-  if (auto *STy = dyn_cast<StructType>(this)) {
-    // Structure indexes require (vectors of) 32-bit integer constants.  In the
-    // vector case all of the indices must be equal.
-    if (!V->getType()->isIntOrIntVectorTy(32))
-      return false;
-    const Constant *C = dyn_cast<Constant>(V);
-    if (C && V->getType()->isVectorTy())
-      C = C->getSplatValue();
-    const ConstantInt *CU = dyn_cast_or_null<ConstantInt>(C);
-    return CU && CU->getZExtValue() < STy->getNumElements();
-  }
-
-  // Sequential types can be indexed by any integer.
-  return V->getType()->isIntOrIntVectorTy();
-}
-
-bool CompositeType::indexValid(unsigned Idx) const {
-  if (auto *STy = dyn_cast<StructType>(this))
-    return Idx < STy->getNumElements();
-  // Sequential types can be indexed by any integer.
-  return true;
+bool StructType::indexValid(const Value *V) const {
+  // Structure indexes require (vectors of) 32-bit integer constants.  In the
+  // vector case all of the indices must be equal.
+  if (!V->getType()->isIntOrIntVectorTy(32))
+    return false;
+  const Constant *C = dyn_cast<Constant>(V);
+  if (C && V->getType()->isVectorTy())
+    C = C->getSplatValue();
+  const ConstantInt *CU = dyn_cast_or_null<ConstantInt>(C);
+  return CU && CU->getZExtValue() < getNumElements();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp
index 8cd589759eab4..962e67437280e 100644
--- a/llvm/lib/IR/Value.cpp
+++ b/llvm/lib/IR/Value.cpp
@@ -666,7 +666,7 @@ uint64_t Value::getPointerDereferenceableBytes(const DataLayout &DL,
     if (DerefBytes == 0 && (A->hasByValAttr() || A->hasStructRetAttr())) {
       Type *PT = cast<PointerType>(A->getType())->getElementType();
       if (PT->isSized())
-        DerefBytes = DL.getTypeStoreSize(PT);
+        DerefBytes = DL.getTypeStoreSize(PT).getKnownMinSize();
     }
     if (DerefBytes == 0) {
       DerefBytes = A->getDereferenceableOrNullBytes();
@@ -707,14 +707,15 @@ uint64_t Value::getPointerDereferenceableBytes(const DataLayout &DL,
     }
   } else if (auto *AI = dyn_cast<AllocaInst>(this)) {
     if (!AI->isArrayAllocation()) {
-      DerefBytes = DL.getTypeStoreSize(AI->getAllocatedType());
+      DerefBytes =
+          DL.getTypeStoreSize(AI->getAllocatedType()).getKnownMinSize();
       CanBeNull = false;
     }
   } else if (auto *GV = dyn_cast<GlobalVariable>(this)) {
     if (GV->getValueType()->isSized() && !GV->hasExternalWeakLinkage()) {
       // TODO: Don't outright reject hasExternalWeakLinkage but set the
       // CanBeNull flag.
-      DerefBytes = DL.getTypeStoreSize(GV->getValueType());
+      DerefBytes = DL.getTypeStoreSize(GV->getValueType()).getFixedSize();
       CanBeNull = false;
     }
   }
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 1053304995c98..68c920d4e54f4 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -2385,11 +2385,14 @@ void Verifier::visitFunction(const Function &F) {
     AssertDI(Parent && isa<DILocalScope>(Parent),
              "DILocation's scope must be a DILocalScope", N, &F, &I, DL,
              Parent);
+
     DILocalScope *Scope = DL->getInlinedAtScope();
-    if (Scope && !Seen.insert(Scope).second)
+    Assert(Scope, "Failed to find DILocalScope", DL);
+
+    if (!Seen.insert(Scope).second)
       return;
 
-    DISubprogram *SP = Scope ? Scope->getSubprogram() : nullptr;
+    DISubprogram *SP = Scope->getSubprogram();
 
     // Scope and SP could be the same MDNode and we don't want to skip
     // validation in that case
@@ -4412,15 +4415,6 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
            "must be a power of 2",
            Call);
 
-    if (auto *LengthCI = dyn_cast<ConstantInt>(AMI->getLength())) {
-      uint64_t Length = LengthCI->getZExtValue();
-      uint64_t ElementSize = AMI->getElementSizeInBytes();
-      Assert((Length % ElementSize) == 0,
-             "constant length must be a multiple of the element size in the "
-             "element-wise atomic memory intrinsic",
-             Call);
-    }
-
     auto IsValidAlignment = [&](uint64_t Alignment) {
       return isPowerOf2_64(Alignment) && ElementSizeVal.ule(Alignment);
     };
diff --git a/llvm/lib/MC/CMakeLists.txt b/llvm/lib/MC/CMakeLists.txt
index de2e47d8d9b28..ab809daf5273d 100644
--- a/llvm/lib/MC/CMakeLists.txt
+++ b/llvm/lib/MC/CMakeLists.txt
@@ -44,6 +44,7 @@ add_llvm_component_library(LLVMMC
   MCSymbol.cpp
   MCSymbolELF.cpp
   MCTargetOptions.cpp
+  MCTargetOptionsCommandFlags.cpp
   MCValue.cpp
   MCWasmObjectTargetWriter.cpp
   MCWasmStreamer.cpp
diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp
index 83f0d62bac2ad..97fb13bdb8856 100644
--- a/llvm/lib/MC/MCAssembler.cpp
+++ b/llvm/lib/MC/MCAssembler.cpp
@@ -785,9 +785,15 @@ void MCAssembler::layout(MCAsmLayout &Layout) {
   }
 
   // Layout until everything fits.
-  while (layoutOnce(Layout))
+  while (layoutOnce(Layout)) {
     if (getContext().hadError())
       return;
+    // Size of fragments in one section can depend on the size of fragments in
+    // another. If any fragment has changed size, we have to re-layout (and
+    // as a result possibly further relax) all.
+    for (MCSection &Sec : *this)
+      Layout.invalidateFragmentsFrom(&*Sec.begin());
+  }
 
   DEBUG_WITH_TYPE("mc-dump", {
       errs() << "assembler backend - post-relaxation\n--\n";
diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp
index a36cdc4c1abba..70c9201e8a170 100644
--- a/llvm/lib/MC/MCObjectStreamer.cpp
+++ b/llvm/lib/MC/MCObjectStreamer.cpp
@@ -367,9 +367,9 @@ bool MCObjectStreamer::mayHaveInstructions(MCSection &Sec) const {
 
 void MCObjectStreamer::emitInstruction(const MCInst &Inst,
                                        const MCSubtargetInfo &STI) {
-  getAssembler().getBackend().alignBranchesBegin(*this, Inst);
+  getAssembler().getBackend().emitInstructionBegin(*this, Inst);
   emitInstructionImpl(Inst, STI);
-  getAssembler().getBackend().alignBranchesEnd(*this, Inst);
+  getAssembler().getBackend().emitInstructionEnd(*this, Inst);
 }
 
 void MCObjectStreamer::emitInstructionImpl(const MCInst &Inst,
diff --git a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
new file mode 100644
index 0000000000000..3ca34061241a8
--- /dev/null
+++ b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
@@ -0,0 +1,105 @@
+//===-- MCTargetOptionsCommandFlags.cpp --------------------------*- C++
+//-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains machine code-specific flags that are shared between
+// different command line tools.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
+
+using namespace llvm;
+
+#define MCOPT(TY, NAME)                                                        \
+  static cl::opt<TY> *NAME##View;                                              \
+  TY llvm::mc::get##NAME() {                                                   \
+    assert(NAME##View && "RegisterMCTargetOptionsFlags not created.");         \
+    return *NAME##View;                                                        \
+  }
+
+#define MCOPT_EXP(TY, NAME)                                                    \
+  MCOPT(TY, NAME)                                                              \
+  Optional<TY> llvm::mc::getExplicit##NAME() {                                 \
+    if (NAME##View->getNumOccurrences()) {                                     \
+      TY res = *NAME##View;                                                    \
+      return res;                                                              \
+    }                                                                          \
+    return None;                                                               \
+  }
+
+MCOPT_EXP(bool, RelaxAll)
+MCOPT(bool, IncrementalLinkerCompatible)
+MCOPT(int, DwarfVersion)
+MCOPT(bool, ShowMCInst)
+MCOPT(bool, FatalWarnings)
+MCOPT(bool, NoWarn)
+MCOPT(bool, NoDeprecatedWarn)
+MCOPT(std::string, ABIName)
+
+llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
+#define MCBINDOPT(NAME)                                                        \
+  do {                                                                         \
+    NAME##View = std::addressof(NAME);                                         \
+  } while (0)
+
+  static cl::opt<bool> RelaxAll(
+      "mc-relax-all", cl::desc("When used with filetype=obj, relax all fixups "
+                               "in the emitted object file"));
+  MCBINDOPT(RelaxAll);
+
+  static cl::opt<bool> IncrementalLinkerCompatible(
+      "incremental-linker-compatible",
+      cl::desc(
+          "When used with filetype=obj, "
+          "emit an object file which can be used with an incremental linker"));
+  MCBINDOPT(IncrementalLinkerCompatible);
+
+  static cl::opt<int> DwarfVersion("dwarf-version", cl::desc("Dwarf version"),
+                                   cl::init(0));
+  MCBINDOPT(DwarfVersion);
+
+  static cl::opt<bool> ShowMCInst(
+      "asm-show-inst",
+      cl::desc("Emit internal instruction representation to assembly file"));
+  MCBINDOPT(ShowMCInst);
+
+  static cl::opt<bool> FatalWarnings("fatal-warnings",
+                                     cl::desc("Treat warnings as errors"));
+  MCBINDOPT(FatalWarnings);
+
+  static cl::opt<bool> NoWarn("no-warn", cl::desc("Suppress all warnings"));
+  static cl::alias NoWarnW("W", cl::desc("Alias for --no-warn"),
+                           cl::aliasopt(NoWarn));
+  MCBINDOPT(NoWarn);
+
+  static cl::opt<bool> NoDeprecatedWarn(
+      "no-deprecated-warn", cl::desc("Suppress all deprecated warnings"));
+  MCBINDOPT(NoDeprecatedWarn);
+
+  static cl::opt<std::string> ABIName(
+      "target-abi", cl::Hidden,
+      cl::desc("The name of the ABI to be targeted from the backend."),
+      cl::init(""));
+  MCBINDOPT(ABIName);
+
+#undef MCBINDOPT
+}
+
+MCTargetOptions llvm::mc::InitMCTargetOptionsFromFlags() {
+  MCTargetOptions Options;
+  Options.MCRelaxAll = getRelaxAll();
+  Options.MCIncrementalLinkerCompatible = getIncrementalLinkerCompatible();
+  Options.DwarfVersion = getDwarfVersion();
+  Options.ShowMCInst = getShowMCInst();
+  Options.ABIName = getABIName();
+  Options.MCFatalWarnings = getFatalWarnings();
+  Options.MCNoWarn = getNoWarn();
+  Options.MCNoDeprecatedWarn = getNoDeprecatedWarn();
+  return Options;
+}
diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp
index d567153af4c22..e9977b4899eeb 100644
--- a/llvm/lib/ObjectYAML/ELFYAML.cpp
+++ b/llvm/lib/ObjectYAML/ELFYAML.cpp
@@ -982,6 +982,38 @@ struct NormalizedOther {
 
 } // end anonymous namespace
 
+void ScalarTraits<ELFYAML::YAMLIntUInt>::output(const ELFYAML::YAMLIntUInt &Val,
+                                                void *Ctx, raw_ostream &Out) {
+  Out << Val;
+}
+
+StringRef ScalarTraits<ELFYAML::YAMLIntUInt>::input(StringRef Scalar, void *Ctx,
+                                                    ELFYAML::YAMLIntUInt &Val) {
+  const bool Is64 = static_cast<ELFYAML::Object *>(Ctx)->Header.Class ==
+                    ELFYAML::ELF_ELFCLASS(ELF::ELFCLASS64);
+  StringRef ErrMsg = "invalid number";
+  // We do not accept negative hex numbers because their meaning is ambiguous.
+  // For example, would -0xfffffffff mean 1 or INT32_MIN?
+  if (Scalar.empty() || Scalar.startswith("-0x"))
+    return ErrMsg;
+
+  if (Scalar.startswith("-")) {
+    const int64_t MinVal = Is64 ? INT64_MIN : INT32_MIN;
+    long long Int;
+    if (getAsSignedInteger(Scalar, /*Radix=*/0, Int) || (Int < MinVal))
+      return ErrMsg;
+    Val = Int;
+    return "";
+  }
+
+  const uint64_t MaxVal = Is64 ? UINT64_MAX : UINT32_MAX;
+  unsigned long long UInt;
+  if (getAsUnsignedInteger(Scalar, /*Radix=*/0, UInt) || (UInt > MaxVal))
+    return ErrMsg;
+  Val = UInt;
+  return "";
+}
+
 void MappingTraits<ELFYAML::Symbol>::mapping(IO &IO, ELFYAML::Symbol &Symbol) {
   IO.mapOptional("Name", Symbol.Name, StringRef());
   IO.mapOptional("StName", Symbol.StName);
@@ -1582,7 +1614,7 @@ void MappingTraits<ELFYAML::Relocation>::mapping(IO &IO,
   } else
     IO.mapRequired("Type", Rel.Type);
 
-  IO.mapOptional("Addend", Rel.Addend, (int64_t)0);
+  IO.mapOptional("Addend", Rel.Addend, (ELFYAML::YAMLIntUInt)0);
 }
 
 void MappingTraits<ELFYAML::Object>::mapping(IO &IO, ELFYAML::Object &Object) {
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index 056e8833ab83e..56af6d3bd7c21 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -92,6 +92,7 @@ MODULE_PASS("tsan-module", ThreadSanitizerPass())
 MODULE_PASS("kasan-module", ModuleAddressSanitizerPass(/*CompileKernel=*/true, false, true, false))
 MODULE_PASS("sancov-module", ModuleSanitizerCoveragePass())
 MODULE_PASS("poison-checking", PoisonCheckingPass())
+MODULE_PASS("stack-safety-annotator", StackSafetyGlobalAnnotatorPass())
 #undef MODULE_PASS
 
 #ifndef CGSCC_ANALYSIS
diff --git a/llvm/lib/Support/raw_ostream.cpp b/llvm/lib/Support/raw_ostream.cpp
index 13b0203ac953e..7e9428e5dbc92 100644
--- a/llvm/lib/Support/raw_ostream.cpp
+++ b/llvm/lib/Support/raw_ostream.cpp
@@ -792,7 +792,7 @@ size_t raw_fd_ostream::preferred_buffer_size() const {
   // If this is a terminal, don't use buffering. Line buffering
   // would be a more traditional thing to do, but it's not worth
   // the complexity.
-  if (S_ISCHR(statbuf.st_mode) && isatty(FD))
+  if (S_ISCHR(statbuf.st_mode) && is_displayed())
     return 0;
   // Return the preferred block size.
   return statbuf.st_blksize;
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 91a8bca993975..9f17d7d0762bc 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1217,8 +1217,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
                       false, NeedsWinCFI, &HasWinCFI);
 
     if (NeedsRealignment) {
-      const unsigned Alignment = MFI.getMaxAlignment();
-      const unsigned NrBitsToZero = countTrailingZeros(Alignment);
+      const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
       assert(NrBitsToZero > 1);
       assert(scratchSPReg != AArch64::SP);
 
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 05675503c96f5..bae5c7f4eef8d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4509,6 +4509,16 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
     return cast<MemSDNode>(Root)->getMemoryVT();
 
   const unsigned Opcode = Root->getOpcode();
+  // For custom ISD nodes, we have to look at them individually to extract the
+  // type of the data moved to/from memory.
+  switch (Opcode) {
+  case AArch64ISD::LDNF1:
+  case AArch64ISD::LDNF1S:
+    return cast<VTSDNode>(Root->getOperand(3))->getVT();
+  default:
+    break;
+  }
+
   if (Opcode != ISD::INTRINSIC_VOID)
     return EVT();
 
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 23df49790b5e1..7b189dac4abab 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8981,7 +8981,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::aarch64_sve_ldnt1: {
     PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
     Info.opc = ISD::INTRINSIC_W_CHAIN;
-    Info.memVT = MVT::getVT(PtrTy->getElementType());
+    Info.memVT = MVT::getVT(I.getType());
     Info.ptrVal = I.getArgOperand(1);
     Info.offset = 0;
     Info.align = MaybeAlign(DL.getABITypeAlignment(PtrTy->getElementType()));
@@ -8991,7 +8991,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::aarch64_sve_stnt1: {
     PointerType *PtrTy = cast<PointerType>(I.getArgOperand(2)->getType());
     Info.opc = ISD::INTRINSIC_W_CHAIN;
-    Info.memVT = MVT::getVT(PtrTy->getElementType());
+    Info.memVT = MVT::getVT(I.getOperand(0)->getType());
     Info.ptrVal = I.getArgOperand(2);
     Info.offset = 0;
     Info.align = MaybeAlign(DL.getABITypeAlignment(PtrTy->getElementType()));
@@ -12646,6 +12646,41 @@ static SDValue getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset,
   return DAG.getNode(ISD::SHL, DL, MVT::nxv2i64, Offset, SplatShift);
 }
 
+/// Check if the value of \p OffsetInBytes can be used as an immediate for
+/// the gather load/prefetch and scatter store instructions with vector base and
+/// immediate offset addressing mode:
+///
+///      [<Zn>.[S|D]{, #<imm>}]
+///
+/// where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
+
+inline static bool isValidImmForSVEVecImmAddrMode(unsigned OffsetInBytes,
+                                                  unsigned ScalarSizeInBytes) {
+  // The immediate is not a multiple of the scalar size.
+  if (OffsetInBytes % ScalarSizeInBytes)
+    return false;
+
+  // The immediate is out of range.
+  if (OffsetInBytes / ScalarSizeInBytes > 31)
+    return false;
+
+  return true;
+}
+
+/// Check if the value of \p Offset represents a valid immediate for the SVE
+/// gather load/prefetch and scatter store instructiona with vector base and
+/// immediate offset addressing mode:
+///
+///      [<Zn>.[S|D]{, #<imm>}]
+///
+/// where <imm> = sizeof(<T>) * k, for k = 0, 1, ..., 31.
+static bool isValidImmForSVEVecImmAddrMode(SDValue Offset,
+                                           unsigned ScalarSizeInBytes) {
+  ConstantSDNode *OffsetConst = dyn_cast<ConstantSDNode>(Offset.getNode());
+  return OffsetConst && isValidImmForSVEVecImmAddrMode(
+                            OffsetConst->getZExtValue(), ScalarSizeInBytes);
+}
+
 static SDValue performScatterStoreCombine(SDNode *N, SelectionDAG &DAG,
                                           unsigned Opcode,
                                           bool OnlyPackedOffsets = true) {
@@ -12697,13 +12732,8 @@ static SDValue performScatterStoreCombine(SDNode *N, SelectionDAG &DAG,
   // immediates outside that range and non-immediate scalar offsets use SST1 or
   // SST1_UXTW instead.
   if (Opcode == AArch64ISD::SST1_IMM) {
-    uint64_t MaxIndex = 31;
-    uint64_t SrcElSize = SrcElVT.getStoreSize().getKnownMinSize();
-
-    ConstantSDNode *OffsetConst = dyn_cast<ConstantSDNode>(Offset.getNode());
-    if (nullptr == OffsetConst ||
-        OffsetConst->getZExtValue() > MaxIndex * SrcElSize ||
-        OffsetConst->getZExtValue() % SrcElSize) {
+    if (!isValidImmForSVEVecImmAddrMode(Offset,
+                                        SrcVT.getScalarSizeInBits() / 8)) {
       if (MVT::nxv4i32 == Base.getValueType().getSimpleVT().SimpleTy)
         Opcode = AArch64ISD::SST1_UXTW;
       else
@@ -12763,7 +12793,6 @@ static SDValue performGatherLoadCombine(SDNode *N, SelectionDAG &DAG,
          "Gather loads are only possible for SVE vectors");
 
   SDLoc DL(N);
-  MVT RetElVT = RetVT.getVectorElementType().getSimpleVT();
 
   // Make sure that the loaded data will fit into an SVE register
   if (RetVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock)
@@ -12780,8 +12809,8 @@ static SDValue performGatherLoadCombine(SDNode *N, SelectionDAG &DAG,
   // applies to non-temporal gathers because there's no instruction that takes
   // indicies.
   if (Opcode == AArch64ISD::GLDNT1_INDEX) {
-    Offset =
-        getScaledOffsetForBitWidth(DAG, Offset, DL, RetElVT.getSizeInBits());
+    Offset = getScaledOffsetForBitWidth(DAG, Offset, DL,
+                                        RetVT.getScalarSizeInBits());
     Opcode = AArch64ISD::GLDNT1;
   }
 
@@ -12800,13 +12829,8 @@ static SDValue performGatherLoadCombine(SDNode *N, SelectionDAG &DAG,
   // immediates outside that range and non-immediate scalar offsets use GLD1 or
   // GLD1_UXTW instead.
   if (Opcode == AArch64ISD::GLD1_IMM || Opcode == AArch64ISD::GLDFF1_IMM) {
-    uint64_t MaxIndex = 31;
-    uint64_t RetElSize = RetElVT.getStoreSize().getKnownMinSize();
-
-    ConstantSDNode *OffsetConst = dyn_cast<ConstantSDNode>(Offset.getNode());
-    if (nullptr == OffsetConst ||
-        OffsetConst->getZExtValue() > MaxIndex * RetElSize ||
-        OffsetConst->getZExtValue() % RetElSize) {
+    if (!isValidImmForSVEVecImmAddrMode(Offset,
+                                        RetVT.getScalarSizeInBits() / 8)) {
       if (MVT::nxv4i32 == Base.getValueType().getSimpleVT().SimpleTy)
         Opcode = (Opcode == AArch64ISD::GLD1_IMM) ? AArch64ISD::GLD1_UXTW
                                                   : AArch64ISD::GLDFF1_UXTW;
@@ -12950,6 +12974,51 @@ performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return SDValue(N, 0);
 }
 
+/// Legalize the gather prefetch (scalar + vector addressing mode) when the
+/// offset vector is an unpacked 32-bit scalable vector. The other cases (Offset
+/// != nxv2i32) do not need legalization.
+static SDValue legalizeSVEGatherPrefetchOffsVec(SDNode *N, SelectionDAG &DAG) {
+  const unsigned OffsetPos = 4;
+  SDValue Offset = N->getOperand(OffsetPos);
+
+  // Not an unpacked vector, bail out.
+  if (Offset.getValueType().getSimpleVT().SimpleTy != MVT::nxv2i32)
+    return SDValue();
+
+  // Extend the unpacked offset vector to 64-bit lanes.
+  SDLoc DL(N);
+  Offset = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::nxv2i64, Offset);
+  SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
+  // Replace the offset operand with the 64-bit one.
+  Ops[OffsetPos] = Offset;
+
+  return DAG.getNode(N->getOpcode(), DL, DAG.getVTList(MVT::Other), Ops);
+}
+
+/// Combines a node carrying the intrinsic `aarch64_sve_gather_prf<T>` into a
+/// node that uses `aarch64_sve_gather_prf<T>_scaled_uxtw` when the scalar
+/// offset passed to `aarch64_sve_gather_prf<T>` is not a valid immediate for
+/// the sve gather prefetch instruction with vector plus immediate addressing
+/// mode.
+static SDValue combineSVEPrefetchVecBaseImmOff(SDNode *N, SelectionDAG &DAG,
+                                               unsigned NewIID,
+                                               unsigned ScalarSizeInBytes) {
+  const unsigned ImmPos = 4, OffsetPos = 3;
+  // No need to combine the node if the immediate is valid...
+  if (isValidImmForSVEVecImmAddrMode(N->getOperand(ImmPos), ScalarSizeInBytes))
+    return SDValue();
+
+  // ...otherwise swap the offset base with the offset...
+  SmallVector<SDValue, 5> Ops(N->op_begin(), N->op_end());
+  std::swap(Ops[ImmPos], Ops[OffsetPos]);
+  // ...and remap the intrinsic `aarch64_sve_gather_prf<T>` to
+  // `aarch64_sve_gather_prf<T>_scaled_uxtw`.
+  SDLoc DL(N);
+  Ops[1] = DAG.getConstant(NewIID, DL, MVT::i64);
+
+  return DAG.getNode(N->getOpcode(), DL, DAG.getVTList(MVT::Other), Ops);
+}
+
 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
                                                  DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
@@ -13014,6 +13083,31 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN:
     switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+    case Intrinsic::aarch64_sve_gather_prfb:
+      return combineSVEPrefetchVecBaseImmOff(
+          N, DAG, Intrinsic::aarch64_sve_gather_prfb_scaled_uxtw,
+          1 /*=ScalarSizeInBytes*/);
+    case Intrinsic::aarch64_sve_gather_prfh:
+      return combineSVEPrefetchVecBaseImmOff(
+          N, DAG, Intrinsic::aarch64_sve_gather_prfh_scaled_uxtw,
+          2 /*=ScalarSizeInBytes*/);
+    case Intrinsic::aarch64_sve_gather_prfw:
+      return combineSVEPrefetchVecBaseImmOff(
+          N, DAG, Intrinsic::aarch64_sve_gather_prfw_scaled_uxtw,
+          4 /*=ScalarSizeInBytes*/);
+    case Intrinsic::aarch64_sve_gather_prfd:
+      return combineSVEPrefetchVecBaseImmOff(
+          N, DAG, Intrinsic::aarch64_sve_gather_prfd_scaled_uxtw,
+          8 /*=ScalarSizeInBytes*/);
+    case Intrinsic::aarch64_sve_gather_prfb_scaled_uxtw:
+    case Intrinsic::aarch64_sve_gather_prfb_scaled_sxtw:
+    case Intrinsic::aarch64_sve_gather_prfh_scaled_uxtw:
+    case Intrinsic::aarch64_sve_gather_prfh_scaled_sxtw:
+    case Intrinsic::aarch64_sve_gather_prfw_scaled_uxtw:
+    case Intrinsic::aarch64_sve_gather_prfw_scaled_sxtw:
+    case Intrinsic::aarch64_sve_gather_prfd_scaled_uxtw:
+    case Intrinsic::aarch64_sve_gather_prfd_scaled_sxtw:
+      return legalizeSVEGatherPrefetchOffsVec(N, DAG);
     case Intrinsic::aarch64_neon_ld2:
     case Intrinsic::aarch64_neon_ld3:
     case Intrinsic::aarch64_neon_ld4:
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 833aee041aa51..d3a541d0246b5 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -880,37 +880,37 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
 
   // Gather prefetch using scaled 32-bit offsets, e.g.
   //    prfh pldl1keep, p0, [x0, z0.s, uxtw #1]
-  defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only,  ZPR32ExtUXTW8Only>;
-  defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
-  defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
-  defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64, ZPR32ExtUXTW64>;
+  defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only,  ZPR32ExtUXTW8Only, int_aarch64_sve_gather_prfb_scaled_sxtw, int_aarch64_sve_gather_prfb_scaled_uxtw>;
+  defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16,     ZPR32ExtUXTW16,    int_aarch64_sve_gather_prfh_scaled_sxtw, int_aarch64_sve_gather_prfh_scaled_uxtw>;
+  defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32,     ZPR32ExtUXTW32,    int_aarch64_sve_gather_prfw_scaled_sxtw, int_aarch64_sve_gather_prfw_scaled_uxtw>;
+  defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64,     ZPR32ExtUXTW64,    int_aarch64_sve_gather_prfd_scaled_sxtw, int_aarch64_sve_gather_prfd_scaled_uxtw>;
 
   // Gather prefetch using unpacked, scaled 32-bit offsets, e.g.
   //    prfh pldl1keep, p0, [x0, z0.d, uxtw #1]
-  defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
-  defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
-  defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
-  defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
+  defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only, int_aarch64_sve_gather_prfb_scaled_sxtw, int_aarch64_sve_gather_prfb_scaled_uxtw>;
+  defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16,    ZPR64ExtUXTW16,    int_aarch64_sve_gather_prfh_scaled_sxtw, int_aarch64_sve_gather_prfh_scaled_uxtw>;
+  defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32,    ZPR64ExtUXTW32,    int_aarch64_sve_gather_prfw_scaled_sxtw, int_aarch64_sve_gather_prfw_scaled_uxtw>;
+  defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64,    ZPR64ExtUXTW64,    int_aarch64_sve_gather_prfd_scaled_sxtw, int_aarch64_sve_gather_prfd_scaled_uxtw>;
 
   // Gather prefetch using scaled 64-bit offsets, e.g.
   //    prfh pldl1keep, p0, [x0, z0.d, lsl #1]
-  defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8>;
-  defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16>;
-  defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32>;
-  defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64>;
+  defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8,  int_aarch64_sve_gather_prfb_scaled>;
+  defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16, int_aarch64_sve_gather_prfh_scaled>;
+  defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32, int_aarch64_sve_gather_prfw_scaled>;
+  defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64, int_aarch64_sve_gather_prfd_scaled>;
 
   // Gather prefetch using 32/64-bit pointers with offset, e.g.
   //    prfh pldl1keep, p0, [z0.s, #16]
   //    prfh pldl1keep, p0, [z0.d, #16]
-  defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31>;
-  defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2>;
-  defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4>;
-  defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8>;
+  defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31, int_aarch64_sve_gather_prfb>;
+  defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2, int_aarch64_sve_gather_prfh>;
+  defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4, int_aarch64_sve_gather_prfw>;
+  defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8, int_aarch64_sve_gather_prfd>;
 
-  defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31>;
-  defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2>;
-  defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>;
-  defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>;
+  defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31, int_aarch64_sve_gather_prfb>;
+  defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2, int_aarch64_sve_gather_prfh>;
+  defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4, int_aarch64_sve_gather_prfw>;
+  defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8, int_aarch64_sve_gather_prfd>;
 
   defm ADR_SXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_sxtw<0b00, "adr">;
   defm ADR_UXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_uxtw<0b01, "adr">;
@@ -1538,6 +1538,12 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
   defm Pat_Load_P2  : unpred_load_predicate<nxv2i1, LDR_PXI>;
 
   multiclass ldnf1<Instruction I, ValueType Ty, SDPatternOperator Load, ValueType PredTy, ValueType MemVT> {
+    // scalar + immediate (mul vl)
+    let AddedComplexity = 1 in {
+      def : Pat<(Ty (Load  (PredTy PPR:$gp), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), MemVT)),
+                (I PPR:$gp, GPR64sp:$base, simm4s1:$offset)>;
+    }
+
     // base
     def : Pat<(Ty (Load  (PredTy PPR:$gp), GPR64:$base, MemVT)),
               (I PPR:$gp, GPR64sp:$base, (i64 0))>;
@@ -1570,40 +1576,45 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
   // 16-element contiguous non-faulting loads
   defm : ldnf1<LDNF1B_IMM,    nxv16i8, AArch64ldnf1, nxv16i1, nxv16i8>;
 
-  multiclass ldff1<Instruction I, ValueType Ty, SDPatternOperator Load, ValueType PredTy, ValueType MemVT> {
-    // Add more complex addressing modes here as required.
+  multiclass ldff1<Instruction I, ValueType Ty, SDPatternOperator Load, ValueType PredTy, ValueType MemVT, ComplexPattern AddrCP> {
+    // reg + reg
+    let AddedComplexity = 1 in {
+      def : Pat<(Ty (Load  (PredTy PPR:$gp), (AddrCP GPR64:$base, GPR64:$offset), MemVT)),
+                (I PPR:$gp, GPR64sp:$base, GPR64:$offset)>;
+    }
+
     // Base
     def : Pat<(Ty (Load  (PredTy PPR:$gp), GPR64:$base, MemVT)),
               (I PPR:$gp, GPR64sp:$base, XZR)>;
   }
 
   // 2-element contiguous first faulting loads
-  defm : ldff1<LDFF1B_D,  nxv2i64, AArch64ldff1,  nxv2i1, nxv2i8>;
-  defm : ldff1<LDFF1SB_D, nxv2i64, AArch64ldff1s, nxv2i1, nxv2i8>;
-  defm : ldff1<LDFF1H_D,  nxv2i64, AArch64ldff1,  nxv2i1, nxv2i16>;
-  defm : ldff1<LDFF1SH_D, nxv2i64, AArch64ldff1s, nxv2i1, nxv2i16>;
-  defm : ldff1<LDFF1W_D,  nxv2i64, AArch64ldff1,  nxv2i1, nxv2i32>;
-  defm : ldff1<LDFF1SW_D, nxv2i64, AArch64ldff1s, nxv2i1, nxv2i32>;
-  defm : ldff1<LDFF1D,    nxv2i64, AArch64ldff1,  nxv2i1, nxv2i64>;
-  defm : ldff1<LDFF1W_D,  nxv2f32, AArch64ldff1,  nxv2i1, nxv2f32>;
-  defm : ldff1<LDFF1D,    nxv2f64, AArch64ldff1,  nxv2i1, nxv2f64>;
+  defm : ldff1<LDFF1B_D,  nxv2i64, AArch64ldff1,  nxv2i1, nxv2i8,  am_sve_regreg_lsl0>;
+  defm : ldff1<LDFF1SB_D, nxv2i64, AArch64ldff1s, nxv2i1, nxv2i8,  am_sve_regreg_lsl0>;
+  defm : ldff1<LDFF1H_D,  nxv2i64, AArch64ldff1,  nxv2i1, nxv2i16, am_sve_regreg_lsl1>;
+  defm : ldff1<LDFF1SH_D, nxv2i64, AArch64ldff1s, nxv2i1, nxv2i16, am_sve_regreg_lsl1>;
+  defm : ldff1<LDFF1W_D,  nxv2i64, AArch64ldff1,  nxv2i1, nxv2i32, am_sve_regreg_lsl2>;
+  defm : ldff1<LDFF1SW_D, nxv2i64, AArch64ldff1s, nxv2i1, nxv2i32, am_sve_regreg_lsl2>;
+  defm : ldff1<LDFF1D,    nxv2i64, AArch64ldff1,  nxv2i1, nxv2i64, am_sve_regreg_lsl3>;
+  defm : ldff1<LDFF1W_D,  nxv2f32, AArch64ldff1,  nxv2i1, nxv2f32, am_sve_regreg_lsl2>;
+  defm : ldff1<LDFF1D,    nxv2f64, AArch64ldff1,  nxv2i1, nxv2f64, am_sve_regreg_lsl3>;
 
   // 4-element contiguous first faulting loads
-  defm : ldff1<LDFF1B_S,  nxv4i32, AArch64ldff1,  nxv4i1, nxv4i8>;
-  defm : ldff1<LDFF1SB_S, nxv4i32, AArch64ldff1s, nxv4i1, nxv4i8>;
-  defm : ldff1<LDFF1H_S,  nxv4i32, AArch64ldff1,  nxv4i1, nxv4i16>;
-  defm : ldff1<LDFF1SH_S, nxv4i32, AArch64ldff1s, nxv4i1, nxv4i16>;
-  defm : ldff1<LDFF1W,    nxv4i32, AArch64ldff1,  nxv4i1, nxv4i32>;
-  defm : ldff1<LDFF1W,    nxv4f32, AArch64ldff1,  nxv4i1, nxv4f32>;
+  defm : ldff1<LDFF1B_S,  nxv4i32, AArch64ldff1,  nxv4i1, nxv4i8,  am_sve_regreg_lsl0>;
+  defm : ldff1<LDFF1SB_S, nxv4i32, AArch64ldff1s, nxv4i1, nxv4i8,  am_sve_regreg_lsl0>;
+  defm : ldff1<LDFF1H_S,  nxv4i32, AArch64ldff1,  nxv4i1, nxv4i16, am_sve_regreg_lsl1>;
+  defm : ldff1<LDFF1SH_S, nxv4i32, AArch64ldff1s, nxv4i1, nxv4i16, am_sve_regreg_lsl1>;
+  defm : ldff1<LDFF1W,    nxv4i32, AArch64ldff1,  nxv4i1, nxv4i32, am_sve_regreg_lsl2>;
+  defm : ldff1<LDFF1W,    nxv4f32, AArch64ldff1,  nxv4i1, nxv4f32, am_sve_regreg_lsl2>;
 
   // 8-element contiguous first faulting loads
-  defm : ldff1<LDFF1B_H,  nxv8i16, AArch64ldff1,  nxv8i1, nxv8i8>;
-  defm : ldff1<LDFF1SB_H, nxv8i16, AArch64ldff1s, nxv8i1, nxv8i8>;
-  defm : ldff1<LDFF1H,    nxv8i16, AArch64ldff1,  nxv8i1, nxv8i16>;
-  defm : ldff1<LDFF1H,    nxv8f16, AArch64ldff1,  nxv8i1, nxv8f16>;
+  defm : ldff1<LDFF1B_H,  nxv8i16, AArch64ldff1,  nxv8i1, nxv8i8,  am_sve_regreg_lsl0>;
+  defm : ldff1<LDFF1SB_H, nxv8i16, AArch64ldff1s, nxv8i1, nxv8i8,  am_sve_regreg_lsl0>;
+  defm : ldff1<LDFF1H,    nxv8i16, AArch64ldff1,  nxv8i1, nxv8i16, am_sve_regreg_lsl1>;
+  defm : ldff1<LDFF1H,    nxv8f16, AArch64ldff1,  nxv8i1, nxv8f16, am_sve_regreg_lsl1>;
 
   // 16-element contiguous first faulting loads
-  defm : ldff1<LDFF1B, nxv16i8, AArch64ldff1, nxv16i1, nxv16i8>;
+  defm : ldff1<LDFF1B, nxv16i8, AArch64ldff1, nxv16i1, nxv16i8, am_sve_regreg_lsl0>;
 }
 
 let Predicates = [HasSVE2] in {
diff --git a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
index 975502818fcd2..8169c49285d1d 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
@@ -400,7 +400,9 @@ bool AArch64StackTagging::isInterestingAlloca(const AllocaInst &AI) {
       // dynamic alloca instrumentation for them as well.
       !AI.isUsedWithInAlloca() &&
       // swifterror allocas are register promoted by ISel
-      !AI.isSwiftError();
+      !AI.isSwiftError() &&
+      // safe allocas are not interesting
+      !AI.getMetadata("stack-safe");
   return IsInteresting;
 }
 
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 6a9d3acff8fb2..3937d6390c4da 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -6455,9 +6455,17 @@ class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
 
 multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm,
                                       RegisterOperand sxtw_opnd,
-                                      RegisterOperand uxtw_opnd> {
+                                      RegisterOperand uxtw_opnd,
+                                      PatFrag op_sxtw,
+                                      PatFrag op_uxtw> {
   def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
+
+  def : Pat<(op_uxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+
+  def : Pat<(op_sxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
 }
 
 class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
@@ -6480,11 +6488,14 @@ class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
   let Inst{3-0}   = prfop;
 }
 
-multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
+multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty, SDPatternOperator op> {
   def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
                   (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+
+  def : Pat<(op (nxv4i1 PPR_3b:$Pg), (nxv4i32 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_3b:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
 }
 
 class sve_mem_z_fill<string asm>
@@ -6798,14 +6809,27 @@ class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
 
 multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm,
                                           RegisterOperand sxtw_opnd,
-                                          RegisterOperand uxtw_opnd> {
+                                          RegisterOperand uxtw_opnd,
+                                          PatFrag op_sxtw,
+                                          PatFrag op_uxtw> {
   def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
+
+  def : Pat<(op_uxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+
+  def : Pat<(op_sxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+
 }
 
 multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm,
-                                          RegisterOperand zprext> {
+                                          RegisterOperand zprext, PatFrag frag> {
   def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
+
+  def : Pat<(frag (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 zprext:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
+
 }
 
 
@@ -6831,11 +6855,14 @@ class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
   let hasSideEffects = 1;
 }
 
-multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
+multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty, SDPatternOperator op> {
   def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
                   (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+
+  def : Pat<(op (nxv2i1 PPR_3b:$Pg), (nxv2i64 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_3b:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
index d3135593bf1f5..112934fd133e1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
@@ -159,13 +159,14 @@ struct AMDGPUFunctionArgInfo {
 
 class AMDGPUArgumentUsageInfo : public ImmutablePass {
 private:
-  static const AMDGPUFunctionArgInfo ExternFunctionInfo;
-  static const AMDGPUFunctionArgInfo FixedABIFunctionInfo;
   DenseMap<const Function *, AMDGPUFunctionArgInfo> ArgInfoMap;
 
 public:
   static char ID;
 
+  static const AMDGPUFunctionArgInfo ExternFunctionInfo;
+  static const AMDGPUFunctionArgInfo FixedABIFunctionInfo;
+
   AMDGPUArgumentUsageInfo() : ImmutablePass(ID) { }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 1a56f382ca80f..63f7590217dfc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -601,6 +601,15 @@ int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumVGPRs(
   return std::max(NumVGPR, NumAGPR);
 }
 
+static const Function *getCalleeFunction(const MachineOperand &Op) {
+  if (Op.isImm()) {
+    assert(Op.getImm() == 0);
+    return nullptr;
+  }
+
+  return cast<Function>(Op.getGlobal());
+}
+
 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
   const MachineFunction &MF) const {
   SIFunctionResourceInfo Info;
@@ -631,8 +640,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
   Info.PrivateSegmentSize = FrameInfo.getStackSize();
   if (MFI->isStackRealigned())
-    Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
-
+    Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
 
   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
@@ -854,8 +862,9 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
 
         const MachineOperand *CalleeOp
           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
-        const Function *Callee = cast<Function>(CalleeOp->getGlobal());
-        if (Callee->isDeclaration()) {
+
+        const Function *Callee = getCalleeFunction(*CalleeOp);
+        if (!Callee || Callee->isDeclaration()) {
           // If this is a call to an external function, we can't do much. Make
           // conservative guesses.
 
@@ -898,7 +907,8 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
           Info.HasRecursion |= I->second.HasRecursion;
         }
 
-        if (!Callee->doesNotRecurse())
+        // FIXME: Call site could have norecurse on it
+        if (!Callee || !Callee->doesNotRecurse())
           Info.HasRecursion = true;
       }
     }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 7d30178b57ed5..e7e5e132ecbd3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -572,8 +572,20 @@ static void packSplitRegsToOrigType(MachineIRBuilder &B,
                                     ArrayRef<Register> Regs,
                                     LLT LLTy,
                                     LLT PartLLT) {
+  MachineRegisterInfo &MRI = *B.getMRI();
+
   if (!LLTy.isVector() && !PartLLT.isVector()) {
-    B.buildMerge(OrigRegs[0], Regs);
+    assert(OrigRegs.size() == 1);
+    LLT OrigTy = MRI.getType(OrigRegs[0]);
+
+    unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();
+    if (SrcSize == OrigTy.getSizeInBits())
+      B.buildMerge(OrigRegs[0], Regs);
+    else {
+      auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
+      B.buildTrunc(OrigRegs[0], Widened);
+    }
+
     return;
   }
 
@@ -584,8 +596,6 @@ static void packSplitRegsToOrigType(MachineIRBuilder &B,
     return;
   }
 
-  MachineRegisterInfo &MRI = *B.getMRI();
-
   assert(LLTy.isVector() && !PartLLT.isVector());
 
   LLT DstEltTy = LLTy.getElementType();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index be02054742ec8..bee0605bd556d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2220,8 +2220,7 @@ SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) con
 // Don't handle v2f16. The extra instructions to scalarize and repack around the
 // compare and vselect end up producing worse code than scalarizing the whole
 // operation.
-SDValue AMDGPUTargetLowering::LowerFROUND_LegalFTRUNC(SDValue Op,
-                                                      SelectionDAG &DAG) const {
+SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
   SDLoc SL(Op);
   SDValue X = Op.getOperand(0);
   EVT VT = Op.getValueType();
@@ -2250,75 +2249,6 @@ SDValue AMDGPUTargetLowering::LowerFROUND_LegalFTRUNC(SDValue Op,
   return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
 }
 
-SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
-  SDLoc SL(Op);
-  SDValue X = Op.getOperand(0);
-
-  SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
-
-  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
-  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
-  const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
-  const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
-  EVT SetCCVT =
-      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
-
-  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
-
-  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
-
-  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
-
-  const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
-                                       MVT::i64);
-
-  SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
-  SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
-                          DAG.getConstant(INT64_C(0x0008000000000000), SL,
-                                          MVT::i64),
-                          Exp);
-
-  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
-  SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
-                              DAG.getConstant(0, SL, MVT::i64), Tmp0,
-                              ISD::SETNE);
-
-  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
-                             D, DAG.getConstant(0, SL, MVT::i64));
-  SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
-
-  K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
-  K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
-
-  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
-  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
-  SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
-
-  SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
-                            ExpEqNegOne,
-                            DAG.getConstantFP(1.0, SL, MVT::f64),
-                            DAG.getConstantFP(0.0, SL, MVT::f64));
-
-  SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
-
-  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
-  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
-
-  return K;
-}
-
-SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
-  EVT VT = Op.getValueType();
-
-  if (isOperationLegal(ISD::FTRUNC, VT))
-    return LowerFROUND_LegalFTRUNC(Op, DAG);
-
-  if (VT == MVT::f64)
-    return LowerFROUND64(Op, DAG);
-
-  llvm_unreachable("unhandled type");
-}
-
 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
   SDLoc SL(Op);
   SDValue Src = Op.getOperand(0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index a8d5f55f1b7af..54747b57f6f4d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -52,8 +52,6 @@ class AMDGPUTargetLowering : public TargetLowering {
   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
 
-  SDValue LowerFROUND_LegalFTRUNC(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 4bf92904e1ab8..47866501776d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -24,6 +24,7 @@
 #include "AMDGPUGlobalISelUtils.h"
 #include "AMDGPUTargetMachine.h"
 #include "SIMachineFunctionInfo.h"
+#include "llvm/ADT/ScopeExit.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
@@ -217,6 +218,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   const LLT S64 = LLT::scalar(64);
   const LLT S128 = LLT::scalar(128);
   const LLT S256 = LLT::scalar(256);
+  const LLT S512 = LLT::scalar(512);
   const LLT S1024 = LLT::scalar(1024);
 
   const LLT V2S16 = LLT::vector(2, 16);
@@ -1205,10 +1207,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
     unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
 
     auto notValidElt = [=](const LegalityQuery &Query, unsigned TypeIdx) {
-      const LLT &Ty = Query.Types[TypeIdx];
+      const LLT Ty = Query.Types[TypeIdx];
       if (Ty.isVector()) {
         const LLT &EltTy = Ty.getElementType();
-        if (EltTy.getSizeInBits() < 8 || EltTy.getSizeInBits() > 64)
+        if (EltTy.getSizeInBits() < 8 || EltTy.getSizeInBits() > 512)
           return true;
         if (!isPowerOf2_32(EltTy.getSizeInBits()))
           return true;
@@ -1230,14 +1232,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
       // Clamp the little scalar to s8-s256 and make it a power of 2. It's not
       // worth considering the multiples of 64 since 2*192 and 2*384 are not
       // valid.
-      .clampScalar(LitTyIdx, S32, S256)
+      .clampScalar(LitTyIdx, S32, S512)
       .widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)
       // Break up vectors with weird elements into scalars
       .fewerElementsIf(
-        [=](const LegalityQuery &Query) { return notValidElt(Query, 0); },
+        [=](const LegalityQuery &Query) { return notValidElt(Query, LitTyIdx); },
         scalarize(0))
       .fewerElementsIf(
-        [=](const LegalityQuery &Query) { return notValidElt(Query, 1); },
+        [=](const LegalityQuery &Query) { return notValidElt(Query, BigTyIdx); },
         scalarize(1))
       .clampScalar(BigTyIdx, S32, S1024);
 
@@ -3372,96 +3374,215 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI,
   return true;
 }
 
-// Produce a vector of s16 elements from s32 pieces.
-static void truncToS16Vector(MachineIRBuilder &B, Register DstReg,
-                             ArrayRef<Register> UnmergeParts) {
+/// Turn a set of s16 typed registers in \p A16AddrRegs into a dword sized
+/// vector with s16 typed elements.
+static void packImageA16AddressToDwords(MachineIRBuilder &B, MachineInstr &MI,
+                                        SmallVectorImpl<Register> &PackedAddrs,
+                                        int AddrIdx, int DimIdx, int NumVAddrs,
+                                        int NumGradients) {
   const LLT S16 = LLT::scalar(16);
-
-  SmallVector<Register, 4> RemergeParts(UnmergeParts.size());
-  for (int I = 0, E = UnmergeParts.size(); I != E; ++I)
-    RemergeParts[I] = B.buildTrunc(S16, UnmergeParts[I]).getReg(0);
-
-  B.buildBuildVector(DstReg, RemergeParts);
-}
-
-/// Convert a set of s32 registers to a result vector with s16 elements.
-static void bitcastToS16Vector(MachineIRBuilder &B, Register DstReg,
-                               ArrayRef<Register> UnmergeParts) {
-  MachineRegisterInfo &MRI = *B.getMRI();
   const LLT V2S16 = LLT::vector(2, 16);
-  LLT TargetTy = MRI.getType(DstReg);
-  int NumElts = UnmergeParts.size();
-
-  if (NumElts == 1) {
-    assert(TargetTy == V2S16);
-    B.buildBitcast(DstReg, UnmergeParts[0]);
-    return;
-  }
 
-  SmallVector<Register, 4> RemergeParts(NumElts);
-  for (int I = 0; I != NumElts; ++I)
-    RemergeParts[I] = B.buildBitcast(V2S16, UnmergeParts[I]).getReg(0);
+  for (int I = AddrIdx; I < AddrIdx + NumVAddrs; ++I) {
+    Register AddrReg = MI.getOperand(I).getReg();
 
-  if (TargetTy.getSizeInBits() == 32u * NumElts) {
-    B.buildConcatVectors(DstReg, RemergeParts);
-    return;
+    if (I < DimIdx) {
+      AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0);
+      PackedAddrs.push_back(AddrReg);
+    } else {
+      // Dz/dh, dz/dv and the last odd coord are packed with undef. Also, in 1D,
+      // derivatives dx/dh and dx/dv are packed with undef.
+      if (((I + 1) >= (AddrIdx + NumVAddrs)) ||
+          ((NumGradients / 2) % 2 == 1 &&
+           (I == DimIdx + (NumGradients / 2) - 1 ||
+            I == DimIdx + NumGradients - 1))) {
+        PackedAddrs.push_back(
+            B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
+                .getReg(0));
+      } else {
+        PackedAddrs.push_back(
+            B.buildBuildVector(V2S16, {AddrReg, MI.getOperand(I + 1).getReg()})
+                .getReg(0));
+        ++I;
+      }
+    }
   }
-
-  const LLT V3S16 = LLT::vector(3, 16);
-  const LLT V6S16 = LLT::vector(6, 16);
-
-  // Widen to v6s16 and unpack v3 parts.
-  assert(TargetTy == V3S16);
-
-  RemergeParts.push_back(B.buildUndef(V2S16).getReg(0));
-  auto Concat = B.buildConcatVectors(V6S16, RemergeParts);
-  B.buildUnmerge({DstReg, MRI.createGenericVirtualRegister(V3S16)}, Concat);
-}
-
-// FIXME: Just vector trunc should be sufficent, but legalization currently
-// broken.
-static void repackUnpackedD16Load(MachineIRBuilder &B, Register DstReg,
-                                  Register WideDstReg) {
-  const LLT S32 = LLT::scalar(32);
-  const LLT S16 = LLT::scalar(16);
-
-  auto Unmerge = B.buildUnmerge(S32, WideDstReg);
-
-  int NumOps = Unmerge->getNumOperands() - 1;
-  SmallVector<Register, 4> RemergeParts(NumOps);
-  for (int I = 0; I != NumOps; ++I)
-    RemergeParts[I] = B.buildTrunc(S16, Unmerge.getReg(I)).getReg(0);
-
-  B.buildBuildVector(DstReg, RemergeParts);
 }
 
+/// Convert from separate vaddr components to a single vector address register,
+/// and replace the remaining operands with $noreg.
+static void convertImageAddrToPacked(MachineIRBuilder &B, MachineInstr &MI,
+                                     int DimIdx, int NumVAddrs) {
+  SmallVector<Register, 8> AddrRegs(NumVAddrs);
+  for (int I = 0; I != NumVAddrs; ++I) {
+    AddrRegs[I] = MI.getOperand(DimIdx + I).getReg();
+    assert(B.getMRI()->getType(AddrRegs[I]) == LLT::scalar(32));
+  }
+
+  auto VAddr = B.buildBuildVector(LLT::vector(NumVAddrs, 32), AddrRegs);
+  MI.getOperand(DimIdx).setReg(VAddr.getReg(0));
+  for (int I = 1; I != NumVAddrs; ++I)
+    MI.getOperand(DimIdx + I).setReg(AMDGPU::NoRegister);
+}
+
+/// Return number of address arguments, and the number of gradients
+static std::pair<int, int>
+getImageNumVAddr(const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr,
+                 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode) {
+  const AMDGPU::MIMGDimInfo *DimInfo
+    = AMDGPU::getMIMGDimInfo(ImageDimIntr->Dim);
+
+  int NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0;
+  int NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0;
+  int NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0;
+  int NumVAddr = BaseOpcode->NumExtraArgs + NumGradients + NumCoords + NumLCM;
+  return {NumVAddr, NumGradients};
+}
+
+static int getDMaskIdx(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
+                       int NumDefs) {
+  assert(!BaseOpcode->Atomic);
+  return NumDefs + 1 + (BaseOpcode->Store ? 1 : 0);
+}
+
+/// Return first address operand index in an image intrinsic.
+static int getImageVAddrIdxBegin(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
+                                 int NumDefs) {
+  if (BaseOpcode->Atomic)
+    return NumDefs + 1 + (BaseOpcode->AtomicX2 ? 2 : 1);
+  return getDMaskIdx(BaseOpcode, NumDefs) + 1;
+}
+
+/// Rewrite image intrinsics to use register layouts expected by the subtarget.
+///
+/// Depending on the subtarget, load/store with 16-bit element data need to be
+/// rewritten to use the low half of 32-bit registers, or directly use a packed
+/// layout. 16-bit addresses should also sometimes be packed into 32-bit
+/// registers.
+///
+/// We don't want to directly select image instructions just yet, but also want
+/// to exposes all register repacking to the legalizer/combiners. We also don't
+/// want a selected instrution entering RegBankSelect. In order to avoid
+/// defining a multitude of intermediate image instructions, directly hack on
+/// the intrinsic's arguments. In cases like a16 addreses, this requires padding
+/// now unnecessary arguments with $noreg.
 bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
     MachineInstr &MI, MachineIRBuilder &B,
     GISelChangeObserver &Observer,
     const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const {
-  bool IsTFE = MI.getNumExplicitDefs() == 2;
+  B.setInstr(MI);
 
+  const int NumDefs = MI.getNumExplicitDefs();
+  bool IsTFE = NumDefs == 2;
   // We are only processing the operands of d16 image operations on subtargets
   // that use the unpacked register layout, or need to repack the TFE result.
 
-  // TODO: Need to handle a16 images too
   // TODO: Do we need to guard against already legalized intrinsics?
-  if (!IsTFE && !ST.hasUnpackedD16VMem())
-    return true;
-
   const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
     AMDGPU::getMIMGBaseOpcodeInfo(ImageDimIntr->BaseOpcode);
 
-  if (BaseOpcode->Atomic) // No d16 atomics, or TFE.
-    return true;
-
-  B.setInstr(MI);
-
   MachineRegisterInfo *MRI = B.getMRI();
   const LLT S32 = LLT::scalar(32);
   const LLT S16 = LLT::scalar(16);
+  const LLT V2S16 = LLT::vector(2, 16);
+
+  // Index of first address argument
+  const int AddrIdx = getImageVAddrIdxBegin(BaseOpcode, NumDefs);
+
+  // Check for 16 bit addresses and pack if true.
+  int DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;
+  LLT AddrTy = MRI->getType(MI.getOperand(DimIdx).getReg());
+  const bool IsA16 = AddrTy == S16;
+
+  int NumVAddrs, NumGradients;
+  std::tie(NumVAddrs, NumGradients) = getImageNumVAddr(ImageDimIntr, BaseOpcode);
+  const int DMaskIdx = BaseOpcode->Atomic ? -1 :
+    getDMaskIdx(BaseOpcode, NumDefs);
+  unsigned DMask = 0;
+
+  int DMaskLanes = 0;
+  if (!BaseOpcode->Atomic) {
+    DMask = MI.getOperand(DMaskIdx).getImm();
+    if (BaseOpcode->Gather4) {
+      DMaskLanes = 4;
+    } else if (DMask != 0) {
+      DMaskLanes = countPopulation(DMask);
+    } else if (!IsTFE && !BaseOpcode->Store) {
+      // If dmask is 0, this is a no-op load. This can be eliminated.
+      B.buildUndef(MI.getOperand(0));
+      MI.eraseFromParent();
+      return true;
+    }
+  }
+
+  Observer.changingInstr(MI);
+  auto ChangedInstr = make_scope_exit([&] { Observer.changedInstr(MI); });
+
+  unsigned NewOpcode = NumDefs == 0 ?
+    AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE : AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD;
+
+  // Track that we legalized this
+  MI.setDesc(B.getTII().get(NewOpcode));
+
+  // Expecting to get an error flag since TFC is on - and dmask is 0 Force
+  // dmask to be at least 1 otherwise the instruction will fail
+  if (IsTFE && DMask == 0) {
+    DMask = 0x1;
+    DMaskLanes = 1;
+    MI.getOperand(DMaskIdx).setImm(DMask);
+  }
+
+  // If the register allocator cannot place the address registers contiguously
+  // without introducing moves, then using the non-sequential address encoding
+  // is always preferable, since it saves VALU instructions and is usually a
+  // wash in terms of code size or even better.
+  //
+  // However, we currently have no way of hinting to the register allocator
+  // that MIMG addresses should be placed contiguously when it is possible to
+  // do so, so force non-NSA for the common 2-address case as a heuristic.
+  //
+  // SIShrinkInstructions will convert NSA encodings to non-NSA after register
+  // allocation when possible.
+  const bool UseNSA = NumVAddrs >= 3 &&
+                      ST.hasFeature(AMDGPU::FeatureNSAEncoding);
+
+  // Rewrite the addressing register layout before doing anything else.
+  if (IsA16) {
+#if 0
+    // FIXME: this feature is missing from gfx10. When that is fixed, this check
+    // should be introduced.
+    if (!ST.hasFeature(AMDGPU::FeatureR128A16))
+      return false;
+#endif
+
+    if (NumVAddrs > 1) {
+      SmallVector<Register, 4> PackedRegs;
+      packImageA16AddressToDwords(B, MI, PackedRegs, AddrIdx, DimIdx, NumVAddrs,
+                                  NumGradients);
+
+      if (!UseNSA && PackedRegs.size() > 1) {
+        LLT PackedAddrTy = LLT::vector(2 * PackedRegs.size(), 16);
+        auto Concat = B.buildConcatVectors(PackedAddrTy, PackedRegs);
+        PackedRegs[0] = Concat.getReg(0);
+        PackedRegs.resize(1);
+      }
+
+      const int NumPacked = PackedRegs.size();
+      for (int I = 0; I != NumVAddrs; ++I) {
+        assert(MI.getOperand(AddrIdx + I).getReg() != AMDGPU::NoRegister);
+
+        if (I < NumPacked)
+          MI.getOperand(AddrIdx + I).setReg(PackedRegs[I]);
+        else
+          MI.getOperand(AddrIdx + I).setReg(AMDGPU::NoRegister);
+      }
+    }
+  } else if (!UseNSA && NumVAddrs > 1) {
+    convertImageAddrToPacked(B, MI, AddrIdx, NumVAddrs);
+  }
 
   if (BaseOpcode->Store) { // No TFE for stores?
+    // TODO: Handle dmask trim
     Register VData = MI.getOperand(1).getReg();
     LLT Ty = MRI->getType(VData);
     if (!Ty.isVector() || Ty.getElementType() != S16)
@@ -3469,9 +3590,11 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
 
     B.setInstr(MI);
 
-    Observer.changingInstr(MI);
-    MI.getOperand(1).setReg(handleD16VData(B, *MRI, VData));
-    Observer.changedInstr(MI);
+    Register RepackedReg = handleD16VData(B, *MRI, VData);
+    if (RepackedReg != VData) {
+      MI.getOperand(1).setReg(RepackedReg);
+    }
+
     return true;
   }
 
@@ -3479,96 +3602,162 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   LLT Ty = MRI->getType(DstReg);
   const LLT EltTy = Ty.getScalarType();
   const bool IsD16 = Ty.getScalarType() == S16;
-  const unsigned NumElts = Ty.isVector() ? Ty.getNumElements() : 1;
+  const int NumElts = Ty.isVector() ? Ty.getNumElements() : 1;
 
-  if (IsTFE) {
-    // In the IR, TFE is supposed to be used with a 2 element struct return
-    // type. The intruction really returns these two values in one contiguous
-    // register, with one additional dword beyond the loaded data. Rewrite the
-    // return type to use a single register result.
-    Register Dst1Reg = MI.getOperand(1).getReg();
-    if (MRI->getType(Dst1Reg) != S32)
-      return false;
+  // Confirm that the return type is large enough for the dmask specified
+  if (NumElts < DMaskLanes)
+    return false;
 
-    // TODO: Make sure the TFE operand bit is set.
+  if (NumElts > 4 || DMaskLanes > 4)
+    return false;
 
-    // The raw dword aligned data component of the load. The only legal cases
-    // where this matters should be when using the packed D16 format, for
-    // s16 -> <2 x s16>, and <3 x s16> -> <4 x s16>,
-    LLT RoundedTy;
-    LLT TFETy;
+  const unsigned AdjustedNumElts = DMaskLanes == 0 ? 1 : DMaskLanes;
+  const LLT AdjustedTy = Ty.changeNumElements(AdjustedNumElts);
 
-    if (IsD16 && ST.hasUnpackedD16VMem()) {
-      RoundedTy = LLT::scalarOrVector(NumElts, 32);
-      TFETy = LLT::vector(NumElts + 1, 32);
-    } else {
-      unsigned EltSize = Ty.getScalarSizeInBits();
-      unsigned RoundedElts = (Ty.getSizeInBits() + 31) / 32;
-      unsigned RoundedSize = 32 * RoundedElts;
-      RoundedTy = LLT::scalarOrVector(RoundedSize / EltSize, EltSize);
-      TFETy = LLT::vector(RoundedSize / 32 + 1, S32);
-    }
+  // The raw dword aligned data component of the load. The only legal cases
+  // where this matters should be when using the packed D16 format, for
+  // s16 -> <2 x s16>, and <3 x s16> -> <4 x s16>,
+  LLT RoundedTy;
 
-    Register TFEReg = MRI->createGenericVirtualRegister(TFETy);
-    Observer.changingInstr(MI);
+  // S32 vector to to cover all data, plus TFE result element.
+  LLT TFETy;
 
-    MI.getOperand(0).setReg(TFEReg);
-    MI.RemoveOperand(1);
+  // Register type to use for each loaded component. Will be S32 or V2S16.
+  LLT RegTy;
 
-    Observer.changedInstr(MI);
+  if (IsD16 && ST.hasUnpackedD16VMem()) {
+    RoundedTy = LLT::scalarOrVector(AdjustedNumElts, 32);
+    TFETy = LLT::vector(AdjustedNumElts + 1, 32);
+    RegTy = S32;
+  } else {
+    unsigned EltSize = EltTy.getSizeInBits();
+    unsigned RoundedElts = (AdjustedTy.getSizeInBits() + 31) / 32;
+    unsigned RoundedSize = 32 * RoundedElts;
+    RoundedTy = LLT::scalarOrVector(RoundedSize / EltSize, EltSize);
+    TFETy = LLT::vector(RoundedSize / 32 + 1, S32);
+    RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
+  }
 
-    // Insert after the instruction.
-    B.setInsertPt(*MI.getParent(), ++MI.getIterator());
+  // The return type does not need adjustment.
+  // TODO: Should we change s16 case to s32 or <2 x s16>?
+  if (!IsTFE && (RoundedTy == Ty || !Ty.isVector()))
+    return true;
+
+  Register Dst1Reg;
+
+  // Insert after the instruction.
+  B.setInsertPt(*MI.getParent(), ++MI.getIterator());
 
-    // Now figure out how to copy the new result register back into the old
-    // result.
+  // TODO: For TFE with d16, if we used a TFE type that was a multiple of <2 x
+  // s16> instead of s32, we would only need 1 bitcast instead of multiple.
+  const LLT LoadResultTy = IsTFE ? TFETy : RoundedTy;
+  const int ResultNumRegs = LoadResultTy.getSizeInBits() / 32;
 
-    SmallVector<Register, 5> UnmergeResults(TFETy.getNumElements(), Dst1Reg);
-    int NumDataElts = TFETy.getNumElements() - 1;
+  Register NewResultReg = MRI->createGenericVirtualRegister(LoadResultTy);
 
-    if (!Ty.isVector()) {
-      // Simplest case is a trivial unmerge (plus a truncate for d16).
-      UnmergeResults[0] = Ty == S32 ?
-        DstReg : MRI->createGenericVirtualRegister(S32);
+  MI.getOperand(0).setReg(NewResultReg);
 
-      B.buildUnmerge(UnmergeResults, TFEReg);
-      if (Ty != S32)
-        B.buildTrunc(DstReg, UnmergeResults[0]);
+  // In the IR, TFE is supposed to be used with a 2 element struct return
+  // type. The intruction really returns these two values in one contiguous
+  // register, with one additional dword beyond the loaded data. Rewrite the
+  // return type to use a single register result.
+
+  if (IsTFE) {
+    Dst1Reg = MI.getOperand(1).getReg();
+    if (MRI->getType(Dst1Reg) != S32)
+      return false;
+
+    // TODO: Make sure the TFE operand bit is set.
+    MI.RemoveOperand(1);
+
+    // Handle the easy case that requires no repack instructions.
+    if (Ty == S32) {
+      B.buildUnmerge({DstReg, Dst1Reg}, NewResultReg);
       return true;
     }
+  }
 
-    // We have to repack into a new vector of some kind.
-    for (int I = 0; I != NumDataElts; ++I)
-      UnmergeResults[I] = MRI->createGenericVirtualRegister(S32);
-    B.buildUnmerge(UnmergeResults, TFEReg);
+  // Now figure out how to copy the new result register back into the old
+  // result.
+  SmallVector<Register, 5> ResultRegs(ResultNumRegs, Dst1Reg);
 
-    // Drop the final TFE element.
-    ArrayRef<Register> DataPart(UnmergeResults.data(), NumDataElts);
+  const int NumDataRegs = IsTFE ? ResultNumRegs - 1  : ResultNumRegs;
 
-    if (EltTy == S32)
-      B.buildBuildVector(DstReg, DataPart);
-    else if (ST.hasUnpackedD16VMem())
-      truncToS16Vector(B, DstReg, DataPart);
-    else
-      bitcastToS16Vector(B, DstReg, DataPart);
+  if (ResultNumRegs == 1) {
+    assert(!IsTFE);
+    ResultRegs[0] = NewResultReg;
+  } else {
+    // We have to repack into a new vector of some kind.
+    for (int I = 0; I != NumDataRegs; ++I)
+      ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy);
+    B.buildUnmerge(ResultRegs, NewResultReg);
 
+    // Drop the final TFE element to get the data part. The TFE result is
+    // directly written to the right place already.
+    if (IsTFE)
+      ResultRegs.resize(NumDataRegs);
+  }
+
+  // For an s16 scalar result, we form an s32 result with a truncate regardless
+  // of packed vs. unpacked.
+  if (IsD16 && !Ty.isVector()) {
+    B.buildTrunc(DstReg, ResultRegs[0]);
     return true;
   }
 
-  // Must be an image load.
-  if (!Ty.isVector() || Ty.getElementType() != S16)
+  // Avoid a build/concat_vector of 1 entry.
+  if (Ty == V2S16 && NumDataRegs == 1 && !ST.hasUnpackedD16VMem()) {
+    B.buildBitcast(DstReg, ResultRegs[0]);
     return true;
+  }
 
-  B.setInsertPt(*MI.getParent(), ++MI.getIterator());
+  assert(Ty.isVector());
 
-  LLT WidenedTy = Ty.changeElementType(S32);
-  Register WideDstReg = MRI->createGenericVirtualRegister(WidenedTy);
+  if (IsD16) {
+    // For packed D16 results with TFE enabled, all the data components are
+    // S32. Cast back to the expected type.
+    //
+    // TODO: We don't really need to use load s32 elements. We would only need one
+    // cast for the TFE result if a multiple of v2s16 was used.
+    if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) {
+      for (Register &Reg : ResultRegs)
+        Reg = B.buildBitcast(V2S16, Reg).getReg(0);
+    } else if (ST.hasUnpackedD16VMem()) {
+      for (Register &Reg : ResultRegs)
+        Reg = B.buildTrunc(S16, Reg).getReg(0);
+    }
+  }
 
-  Observer.changingInstr(MI);
-  MI.getOperand(0).setReg(WideDstReg);
-  Observer.changedInstr(MI);
+  auto padWithUndef = [&](LLT Ty, int NumElts) {
+    if (NumElts == 0)
+      return;
+    Register Undef = B.buildUndef(Ty).getReg(0);
+    for (int I = 0; I != NumElts; ++I)
+      ResultRegs.push_back(Undef);
+  };
+
+  // Pad out any elements eliminated due to the dmask.
+  LLT ResTy = MRI->getType(ResultRegs[0]);
+  if (!ResTy.isVector()) {
+    padWithUndef(ResTy, NumElts - ResultRegs.size());
+    B.buildBuildVector(DstReg, ResultRegs);
+    return true;
+  }
+
+  assert(!ST.hasUnpackedD16VMem() && ResTy == V2S16);
+  const int RegsToCover = (Ty.getSizeInBits() + 31) / 32;
+
+  // Deal with the one annoying legal case.
+  const LLT V3S16 = LLT::vector(3, 16);
+  if (Ty == V3S16) {
+    padWithUndef(ResTy, RegsToCover - ResultRegs.size() + 1);
+    auto Concat = B.buildConcatVectors(LLT::vector(6, 16), ResultRegs);
+    B.buildUnmerge({DstReg, MRI->createGenericVirtualRegister(V3S16)}, Concat);
+    return true;
+  }
 
-  repackUnpackedD16Load(B, DstReg, WideDstReg);
+  padWithUndef(ResTy, RegsToCover - ResultRegs.size());
+  B.buildConcatVectors(DstReg, ResultRegs);
   return true;
 }
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
index 1f14eb3a6fad3..06f2ff39844df 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
@@ -14,6 +14,7 @@
 #include "AMDGPULibFunc.h"
 #include <llvm/ADT/SmallString.h>
 #include <llvm/ADT/SmallVector.h>
+#include "llvm/ADT/StringExtras.h"
 #include <llvm/ADT/StringSwitch.h>
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/DerivedTypes.h"
@@ -479,8 +480,6 @@ static bool eatTerm(StringRef& mangledName, const char (&str)[N]) {
   return false;
 }
 
-static inline bool isDigit(char c) { return c >= '0' && c <= '9'; }
-
 static int eatNumber(StringRef& s) {
   size_t const savedSize = s.size();
   int n = 0;
@@ -605,7 +604,7 @@ bool ItaniumParamParser::parseItaniumParam(StringRef& param,
 
   // parse type
   char const TC = param.front();
-  if (::isDigit(TC)) {
+  if (isDigit(TC)) {
     res.ArgType = StringSwitch<AMDGPULibFunc::EType>
       (eatLengthPrefixedName(param))
       .Case("ocl_image1darray" , AMDGPULibFunc::IMG1DA)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index da0f6b08264ca..7f498e606a70c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -220,7 +220,7 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
                                           unsigned Size) const {
   // TODO: Should there be a UniformVGPRRegBank which can use readfirstlane?
   if (Dst.getID() == AMDGPU::SGPRRegBankID &&
-      isVectorRegisterBank(Src)) {
+      (isVectorRegisterBank(Src) || Src.getID() == AMDGPU::VCCRegBankID)) {
     return std::numeric_limits<unsigned>::max();
   }
 
@@ -238,9 +238,6 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
        Src.getID() == AMDGPU::VCCRegBankID))
     return std::numeric_limits<unsigned>::max();
 
-  if (Src.getID() == AMDGPU::VCCRegBankID)
-    return std::numeric_limits<unsigned>::max();
-
   // There is no direct copy between AGPRs.
   if (Dst.getID() == AMDGPU::AGPRRegBankID &&
       Src.getID() == AMDGPU::AGPRRegBankID)
@@ -2252,10 +2249,13 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
     return;
   }
   case AMDGPU::G_SEXT:
-  case AMDGPU::G_ZEXT: {
+  case AMDGPU::G_ZEXT:
+  case AMDGPU::G_ANYEXT: {
     Register SrcReg = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(SrcReg);
-    bool Signed = Opc == AMDGPU::G_SEXT;
+    const bool Signed = Opc == AMDGPU::G_SEXT;
+
+    assert(empty(OpdMapper.getVRegs(1)));
 
     MachineIRBuilder B(MI);
     const RegisterBank *SrcBank =
@@ -2282,9 +2282,12 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
         auto ShiftAmt = B.buildConstant(S32, 31);
         MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);
         B.buildAShr(DefRegs[1], DefRegs[0], ShiftAmt);
-      } else {
+      } else if (Opc == AMDGPU::G_ZEXT) {
         B.buildZExtOrTrunc(DefRegs[0], SrcReg);
         B.buildConstant(DefRegs[1], 0);
+      } else {
+        B.buildAnyExtOrTrunc(DefRegs[0], SrcReg);
+        B.buildUndef(DefRegs[1]);
       }
 
       MRI.setRegBank(DstReg, *SrcBank);
@@ -2295,6 +2298,9 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
     if (SrcTy != LLT::scalar(1))
       return;
 
+    // It is not legal to have a legalization artifact with a VCC source. Rather
+    // than introducing a copy, insert the selcet we would have to select the
+    // copy to.
     if (SrcBank == &AMDGPU::VCCRegBank) {
       SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
 
@@ -2329,24 +2335,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
       return;
     }
 
-    // Fixup the case with an s1 src that isn't a condition register. Use shifts
-    // instead of introducing a compare to avoid an unnecessary condition
-    // register (and since there's no scalar 16-bit compares).
-    auto Ext = B.buildAnyExt(DstTy, SrcReg);
-    auto ShiftAmt = B.buildConstant(LLT::scalar(32), DstTy.getSizeInBits() - 1);
-    auto Shl = B.buildShl(DstTy, Ext, ShiftAmt);
-
-    if (MI.getOpcode() == AMDGPU::G_SEXT)
-      B.buildAShr(DstReg, Shl, ShiftAmt);
-    else
-      B.buildLShr(DstReg, Shl, ShiftAmt);
-
-    MRI.setRegBank(DstReg, *SrcBank);
-    MRI.setRegBank(Ext.getReg(0), *SrcBank);
-    MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);
-    MRI.setRegBank(Shl.getReg(0), *SrcBank);
-    MI.eraseFromParent();
-    return;
+    break;
   }
   case AMDGPU::G_BUILD_VECTOR:
   case AMDGPU::G_BUILD_VECTOR_TRUNC: {
@@ -2758,6 +2747,17 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
     }
     break;
   }
+  case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD:
+  case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: {
+    const AMDGPU::RsrcIntrinsic *RSrcIntrin
+      = AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID());
+    assert(RSrcIntrin && RSrcIntrin->IsImage);
+    // Non-images can have complications from operands that allow both SGPR
+    // and VGPR. For now it's too complicated to figure out the final opcode
+    // to derive the register bank from the MCInstrDesc.
+    applyMappingImage(MI, OpdMapper, MRI, RSrcIntrin->RsrcArg);
+    return;
+  }
   case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
     auto IntrID = MI.getIntrinsicID();
     switch (IntrID) {
@@ -3423,17 +3423,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       break;
     }
 
-    // TODO: Should anyext be split into 32-bit part as well?
-    if (MI.getOpcode() == AMDGPU::G_ANYEXT) {
-      OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);
-      OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank->getID(), SrcSize);
-    } else {
-      // Scalar extend can use 64-bit BFE, but VGPRs require extending to
-      // 32-bits, and then to 64.
-      OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);
-      OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(),
-                                                         SrcSize);
-    }
+    // Scalar extend can use 64-bit BFE, but VGPRs require extending to
+    // 32-bits, and then to 64.
+    OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);
+    OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(),
+                                                       SrcSize);
     break;
   }
   case AMDGPU::G_FCMP: {
@@ -3873,6 +3867,17 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     }
     break;
   }
+  case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD:
+  case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: {
+    auto IntrID = MI.getIntrinsicID();
+    const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID);
+    assert(RSrcIntrin && "missing RsrcIntrinsic for image intrinsic");
+    // Non-images can have complications from operands that allow both SGPR
+    // and VGPR. For now it's too complicated to figure out the final opcode
+    // to derive the register bank from the MCInstrDesc.
+    assert(RSrcIntrin->IsImage);
+    return getImageMapping(MRI, MI, RSrcIntrin->RsrcArg);
+  }
   case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
     auto IntrID = MI.getIntrinsicID();
     switch (IntrID) {
@@ -4005,15 +4010,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       break;
     }
     default:
-      if (const AMDGPU::RsrcIntrinsic *RSrcIntrin =
-              AMDGPU::lookupRsrcIntrinsic(IntrID)) {
-        // Non-images can have complications from operands that allow both SGPR
-        // and VGPR. For now it's too complicated to figure out the final opcode
-        // to derive the register bank from the MCInstrDesc.
-        if (RSrcIntrin->IsImage)
-          return getImageMapping(MRI, MI, RSrcIntrin->RsrcArg);
-      }
-
       return getInvalidInstructionMapping();
     }
     break;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
index 2569589c7d5fe..223e36e995862 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
@@ -208,6 +208,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
   // Loop over all of the blocks in a function, tracking all of the blocks that
   // return.
   SmallVector<BasicBlock *, 4> ReturningBlocks;
+  SmallVector<BasicBlock *, 4> UniformlyReachedRetBlocks;
   SmallVector<BasicBlock *, 4> UnreachableBlocks;
 
   // Dummy return block for infinite loop.
@@ -219,6 +220,8 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
     if (isa<ReturnInst>(BB->getTerminator())) {
       if (!isUniformlyReached(DA, *BB))
         ReturningBlocks.push_back(BB);
+      else
+        UniformlyReachedRetBlocks.push_back(BB);
     } else if (isa<UnreachableInst>(BB->getTerminator())) {
       if (!isUniformlyReached(DA, *BB))
         UnreachableBlocks.push_back(BB);
@@ -332,6 +335,18 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
   const TargetTransformInfo &TTI
     = getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
 
-  unifyReturnBlockSet(F, ReturningBlocks, InsertExport, TTI, "UnifiedReturnBlock");
+  // Unify returning blocks. If we are going to insert the export it is also
+  // necessary to include blocks that are uniformly reached, because in addition
+  // to inserting the export the "done" bits on existing exports will be cleared
+  // and we do not want to end up with the normal export in a non-unified,
+  // uniformly reached block with the "done" bit cleared.
+  auto BlocksToUnify = std::move(ReturningBlocks);
+  if (InsertExport) {
+    BlocksToUnify.insert(BlocksToUnify.end(), UniformlyReachedRetBlocks.begin(),
+                         UniformlyReachedRetBlocks.end());
+  }
+
+  unifyReturnBlockSet(F, BlocksToUnify, InsertExport, TTI,
+                      "UnifiedReturnBlock");
   return true;
 }
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 9d5d2db4bd6c0..df843f4034efc 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -27,7 +27,19 @@ using namespace llvm;
 using namespace llvm::AMDGPU;
 
 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << getRegisterName(RegNo);
+  // FIXME: The current implementation of
+  // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
+  // as an integer or we provide a name which represents a physical register.
+  // For CFI instructions we really want to emit a name for the DWARF register
+  // instead, because there may be multiple DWARF registers corresponding to a
+  // single physical register. One case where this problem manifests is with
+  // wave32/wave64 where using the physical register name is ambiguous: if we
+  // write e.g. `.cfi_undefined v0` we lose information about the wavefront
+  // size which we need to encode the register in the final DWARF. Ideally we
+  // would extend MC to support parsing DWARF register names so we could do
+  // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
+  // non-pretty DWARF register names in assembly text.
+  OS << RegNo;
 }
 
 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
index 9644e66fda4e5..9ac1b1badee1c 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
@@ -43,6 +43,7 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
   WeakRefDirective = ".weakref\t";
   //===--- Dwarf Emission Directives -----------------------------------===//
   SupportsDebugInformation = true;
+  DwarfRegNumForCFI = true;
 }
 
 bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index d0c713d07d87b..60b35981de9c9 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -768,7 +768,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
 
   if (TRI.needsStackRealignment(MF)) {
     HasFP = true;
-    const unsigned Alignment = MFI.getMaxAlignment();
+    const unsigned Alignment = MFI.getMaxAlign().value();
 
     RoundedSize += Alignment;
     if (LiveRegs.empty()) {
@@ -834,8 +834,9 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
 
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   uint32_t NumBytes = MFI.getStackSize();
-  uint32_t RoundedSize = FuncInfo->isStackRealigned() ?
-    NumBytes + MFI.getMaxAlignment() : NumBytes;
+  uint32_t RoundedSize = FuncInfo->isStackRealigned()
+                             ? NumBytes + MFI.getMaxAlign().value()
+                             : NumBytes;
 
   if (RoundedSize != 0 && hasFP(MF)) {
     const unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 991e0161e7fc6..34fe290ade617 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2445,21 +2445,20 @@ void SITargetLowering::passSpecialInputs(
   if (!CLI.CS)
     return;
 
-  const Function *CalleeFunc = CLI.CS.getCalledFunction();
-  assert(CalleeFunc);
-
   SelectionDAG &DAG = CLI.DAG;
   const SDLoc &DL = CLI.DL;
 
   const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
-
-  auto &ArgUsageInfo =
-    DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
-  const AMDGPUFunctionArgInfo &CalleeArgInfo
-    = ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
-
   const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
 
+  const AMDGPUFunctionArgInfo *CalleeArgInfo
+    = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
+  if (const Function *CalleeFunc = CLI.CS.getCalledFunction()) {
+    auto &ArgUsageInfo =
+      DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
+    CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
+  }
+
   // TODO: Unify with private memory register handling. This is complicated by
   // the fact that at least in kernels, the input argument is not necessarily
   // in the same location as the input.
@@ -2477,7 +2476,7 @@ void SITargetLowering::passSpecialInputs(
     const ArgDescriptor *OutgoingArg;
     const TargetRegisterClass *ArgRC;
 
-    std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
+    std::tie(OutgoingArg, ArgRC) = CalleeArgInfo->getPreloadedValue(InputID);
     if (!OutgoingArg)
       continue;
 
@@ -2518,13 +2517,13 @@ void SITargetLowering::passSpecialInputs(
   const TargetRegisterClass *ArgRC;
 
   std::tie(OutgoingArg, ArgRC) =
-    CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
+    CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
   if (!OutgoingArg)
     std::tie(OutgoingArg, ArgRC) =
-      CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
+      CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
   if (!OutgoingArg)
     std::tie(OutgoingArg, ArgRC) =
-      CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
+      CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
   if (!OutgoingArg)
     return;
 
@@ -2539,10 +2538,10 @@ void SITargetLowering::passSpecialInputs(
   SDLoc SL;
 
   // If incoming ids are not packed we need to pack them.
-  if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo.WorkItemIDX)
+  if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX)
     InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
 
-  if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo.WorkItemIDY) {
+  if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY) {
     SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
     Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
                     DAG.getShiftAmountConstant(10, MVT::i32, SL));
@@ -2550,7 +2549,7 @@ void SITargetLowering::passSpecialInputs(
                  DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
   }
 
-  if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo.WorkItemIDZ) {
+  if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ) {
     SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
     Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
                     DAG.getShiftAmountConstant(20, MVT::i32, SL));
@@ -2708,7 +2707,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
   if (!CLI.CS.getInstruction())
     report_fatal_error("unsupported libcall legalization");
 
-  if (!CLI.CS.getCalledFunction()) {
+  if (!AMDGPUTargetMachine::EnableFixedFunctionABI && !CLI.CS.getCalledFunction()) {
     return lowerUnhandledCall(CLI, InVals,
                               "unsupported indirect call to function ");
   }
@@ -2937,9 +2936,12 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
   Ops.push_back(Callee);
   // Add a redundant copy of the callee global which will not be legalized, as
   // we need direct access to the callee later.
-  GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Callee);
-  const GlobalValue *GV = GSD->getGlobal();
-  Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
+  if (GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(Callee)) {
+    const GlobalValue *GV = GSD->getGlobal();
+    Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
+  } else {
+    Ops.push_back(DAG.getTargetConstant(0, DL, MVT::i64));
+  }
 
   if (IsTailCall) {
     // Each tail call may have to adjust the stack by a different amount, so
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 49bd9cbfe3809..49849576dc26c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -445,8 +445,8 @@ def SI_RETURN : SPseudoInstSI <
 
 // Return for returning function calls without output register.
 //
-// This version is only needed so we can fill in the output regiter in
-// the custom inserter.
+// This version is only needed so we can fill in the output register
+// in the custom inserter.
 def SI_CALL_ISEL : SPseudoInstSI <
   (outs), (ins SSrc_b64:$src0, unknown:$callee),
   [(AMDGPUcall i64:$src0, tglobaladdr:$callee)]> {
@@ -458,6 +458,11 @@ def SI_CALL_ISEL : SPseudoInstSI <
   let isConvergent = 1;
 }
 
+def : GCNPat<
+  (AMDGPUcall i64:$src0, (i64 0)),
+  (SI_CALL_ISEL $src0, (i64 0))
+>;
+
 // Wrapper around s_swappc_b64 with extra $callee parameter to track
 // the called function after regalloc.
 def SI_CALL : SPseudoInstSI <
@@ -2354,3 +2359,24 @@ def G_AMDGPU_S_BUFFER_LOAD : AMDGPUGenericInstruction {
   let mayLoad = 1;
   let mayStore = 0;
 }
+
+// This is equivalent to the G_INTRINSIC*, but the operands may have
+// been legalized depending on the subtarget requirements.
+def G_AMDGPU_INTRIN_IMAGE_LOAD : AMDGPUGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins unknown:$intrin, variable_ops);
+  let hasSideEffects = 0;
+  let mayLoad = 1;
+
+  // FIXME: Use separate opcode for atomics.
+  let mayStore = 1;
+}
+
+// This is equivalent to the G_INTRINSIC*, but the operands may have
+// been legalized depending on the subtarget requirements.
+def G_AMDGPU_INTRIN_IMAGE_STORE : AMDGPUGenericInstruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins unknown:$intrin, variable_ops);
+  let hasSideEffects = 0;
+  let mayStore = 1;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 2f33bc8467be8..6b2b54d896fa3 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -171,8 +171,6 @@ class SIWholeQuadMode : public MachineFunctionPass {
   void propagateBlock(MachineBasicBlock &MBB, std::vector<WorkItem> &Worklist);
   char analyzeFunction(MachineFunction &MF);
 
-  bool requiresCorrectState(const MachineInstr &MI) const;
-
   MachineBasicBlock::iterator saveSCC(MachineBasicBlock &MBB,
                                       MachineBasicBlock::iterator Before);
   MachineBasicBlock::iterator
@@ -526,36 +524,6 @@ char SIWholeQuadMode::analyzeFunction(MachineFunction &MF) {
   return GlobalFlags;
 }
 
-/// Whether \p MI really requires the exec state computed during analysis.
-///
-/// Scalar instructions must occasionally be marked WQM for correct propagation
-/// (e.g. thread masks leading up to branches), but when it comes to actual
-/// execution, they don't care about EXEC.
-bool SIWholeQuadMode::requiresCorrectState(const MachineInstr &MI) const {
-  if (MI.isTerminator())
-    return true;
-
-  // Skip instructions that are not affected by EXEC
-  if (TII->isScalarUnit(MI))
-    return false;
-
-  // Generic instructions such as COPY will either disappear by register
-  // coalescing or be lowered to SALU or VALU instructions.
-  if (MI.isTransient()) {
-    if (MI.getNumExplicitOperands() >= 1) {
-      const MachineOperand &Op = MI.getOperand(0);
-      if (Op.isReg()) {
-        if (TRI->isSGPRReg(*MRI, Op.getReg())) {
-          // SGPR instructions are not affected by EXEC
-          return false;
-        }
-      }
-    }
-  }
-
-  return true;
-}
-
 MachineBasicBlock::iterator
 SIWholeQuadMode::saveSCC(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator Before) {
@@ -742,7 +710,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
     if (II != IE) {
       MachineInstr &MI = *II;
 
-      if (requiresCorrectState(MI)) {
+      if (MI.isTerminator() || TII->mayReadEXEC(*MRI, MI)) {
         auto III = Instructions.find(&MI);
         if (III != Instructions.end()) {
           if (III->second.Needs & StateWWM)
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 054ce02b14d2c..95233a0a0f34d 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1256,7 +1256,7 @@ def : GCNPat <
 
 // Same as a 32-bit inreg
 def : GCNPat<
-  (i32 (sext i16:$src)),
+  (i32 (UniformUnaryFrag<sext> i16:$src)),
   (S_SEXT_I32_I16 $src)
 >;
 
@@ -1283,7 +1283,7 @@ def : GCNPat<
 >;
 
 def : GCNPat <
-  (i64 (sext i16:$src)),
+  (i64 (UniformUnaryFrag<sext> i16:$src)),
     (REG_SEQUENCE SReg_64, (i32 (S_SEXT_I32_I16 $src)), sub0,
     (i32 (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1)
 >;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index a33cd3b8014d4..30345f82fae6e 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -402,6 +402,20 @@ def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, as
 } // End SubtargetPredicate = isGFX8Plus
 } // End SchedRW = [Write64Bit]
 
+def : GCNPat<
+  (i64 (getDivergentFrag<sext>.ret i16:$src)),
+    (REG_SEQUENCE VReg_64,
+      (i32 (V_BFE_I32 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0,
+      (i32 (COPY_TO_REGCLASS
+         (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
+      ), VGPR_32)), sub1)
+>;
+
+def : GCNPat<
+  (i32 (getDivergentFrag<sext>.ret i16:$src)),
+  (i32 (V_BFE_I32 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
+>;
+
 let SubtargetPredicate = isGFX6GFX7GFX10 in {
 def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
 } // End SubtargetPredicate = isGFX6GFX7GFX10
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 4dcb1f62577a6..9fc566761c5c8 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1360,17 +1360,18 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
         // If there's dynamic realignment, adjust for it.
         if (RI.needsStackRealignment(MF)) {
           MachineFrameInfo &MFI = MF.getFrameInfo();
-          unsigned MaxAlign = MFI.getMaxAlignment();
+          Align MaxAlign = MFI.getMaxAlign();
           assert (!AFI->isThumb1OnlyFunction());
           // Emit bic r6, r6, MaxAlign
-          assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
-                                    "immediates larger than 256 with all lower "
-                                    "bits set.");
+          assert(MaxAlign <= Align(256) &&
+                 "The BIC instruction cannot encode "
+                 "immediates larger than 256 with all lower "
+                 "bits set.");
           unsigned bicOpc = AFI->isThumbFunction() ?
             ARM::t2BICri : ARM::BICri;
           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
               .addReg(ARM::R6, RegState::Kill)
-              .addImm(MaxAlign - 1)
+              .addImm(MaxAlign.value() - 1)
               .add(predOps(ARMCC::AL))
               .add(condCodeOp());
         }
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index b8434735451c3..0822a1c062439 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -71,6 +71,14 @@ static cl::opt<bool>
 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
                      cl::desc("Align ARM NEON spills in prolog and epilog"));
 
+static cl::opt<bool> EnableExtraSpills(
+    "arm-extra-spills", cl::Hidden, cl::init(false),
+    cl::desc("Preserve extra registers when useful for IPRA"));
+
+// Testing option to bypass some profitability checks.
+static cl::opt<bool> ForceExtraSpills("arm-extra-spills-force", cl::Hidden,
+                                      cl::init(false));
+
 static MachineBasicBlock::iterator
 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
                         unsigned NumAlignedDPRCS2Regs);
@@ -142,27 +150,6 @@ ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
   return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects();
 }
 
-static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII,
-                        const MCPhysReg *CSRegs) {
-  // Integer spill area is handled with "pop".
-  if (isPopOpcode(MI.getOpcode())) {
-    // The first two operands are predicates. The last two are
-    // imp-def and imp-use of SP. Check everything in between.
-    for (int i = 5, e = MI.getNumOperands(); i != e; ++i)
-      if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
-        return false;
-    return true;
-  }
-  if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
-       MI.getOpcode() == ARM::LDR_POST_REG ||
-       MI.getOpcode() == ARM::t2LDR_POST) &&
-      isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
-      MI.getOperand(1).getReg() == ARM::SP)
-    return true;
-
-  return false;
-}
-
 static void emitRegPlusImmediate(
     bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
     const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
@@ -281,13 +268,13 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MBBI,
                                      const DebugLoc &DL, const unsigned Reg,
-                                     const unsigned Alignment,
+                                     const Align Alignment,
                                      const bool MustBeSingleInstruction) {
   const ARMSubtarget &AST =
       static_cast<const ARMSubtarget &>(MF.getSubtarget());
   const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
-  const unsigned AlignMask = Alignment - 1;
-  const unsigned NrBitsToZero = countTrailingZeros(Alignment);
+  const unsigned AlignMask = Alignment.value() - 1U;
+  const unsigned NrBitsToZero = Log2(Alignment);
   assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
   if (!AFI->isThumbFunction()) {
     // if the BFC instruction is available, use that to zero the lower
@@ -367,7 +354,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   assert(!AFI->isThumb1OnlyFunction() &&
          "This emitPrologue does not support Thumb1!");
   bool isARM = !AFI->isThumbFunction();
-  unsigned Align = STI.getFrameLowering()->getStackAlignment();
+  Align Alignment = STI.getFrameLowering()->getStackAlign();
   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
   unsigned NumBytes = MFI.getStackSize();
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
@@ -458,8 +445,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   // Determine starting offsets of spill areas.
   unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
   unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
-  unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
-  unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
+  Align DPRAlign = DPRCSSize ? std::min(Align(8), Alignment) : Align(4);
+  unsigned DPRGapSize =
+      (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign.value();
   unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
   int FramePtrOffsetInPush = 0;
   if (HasFP) {
@@ -717,7 +705,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   // If aligned NEON registers were spilled, the stack has already been
   // realigned.
   if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
-    unsigned MaxAlign = MFI.getMaxAlignment();
+    Align MaxAlign = MFI.getMaxAlign();
     assert(!AFI->isThumb1OnlyFunction());
     if (!AFI->isThumbFunction()) {
       emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
@@ -793,15 +781,16 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
 
   if (!AFI->hasStackFrame()) {
     if (NumBytes - ArgRegsSaveSize != 0)
-      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
+      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize,
+                   MachineInstr::FrameDestroy);
   } else {
     // Unwind MBBI to point to first LDR / VLDRD.
-    const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
     if (MBBI != MBB.begin()) {
       do {
         --MBBI;
-      } while (MBBI != MBB.begin() && isCSRestore(*MBBI, TII, CSRegs));
-      if (!isCSRestore(*MBBI, TII, CSRegs))
+      } while (MBBI != MBB.begin() &&
+               MBBI->getFlag(MachineInstr::FrameDestroy));
+      if (!MBBI->getFlag(MachineInstr::FrameDestroy))
         ++MBBI;
     }
 
@@ -819,7 +808,8 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
       if (NumBytes) {
         if (isARM)
           emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
-                                  ARMCC::AL, 0, TII);
+                                  ARMCC::AL, 0, TII,
+                                  MachineInstr::FrameDestroy);
         else {
           // It's not possible to restore SP from FP in a single instruction.
           // For iOS, this looks like:
@@ -831,10 +821,11 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
           assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
                  "No scratch register to restore SP from FP!");
           emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
-                                 ARMCC::AL, 0, TII);
+                                 ARMCC::AL, 0, TII, MachineInstr::FrameDestroy);
           BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
               .addReg(ARM::R4)
-              .add(predOps(ARMCC::AL));
+              .add(predOps(ARMCC::AL))
+              .setMIFlag(MachineInstr::FrameDestroy);
         }
       } else {
         // Thumb2 or ARM.
@@ -842,15 +833,18 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
           BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
               .addReg(FramePtr)
               .add(predOps(ARMCC::AL))
-              .add(condCodeOp());
+              .add(condCodeOp())
+              .setMIFlag(MachineInstr::FrameDestroy);
         else
           BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
               .addReg(FramePtr)
-              .add(predOps(ARMCC::AL));
+              .add(predOps(ARMCC::AL))
+              .setMIFlag(MachineInstr::FrameDestroy);
       }
     } else if (NumBytes &&
                !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
-      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
+      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes,
+                   MachineInstr::FrameDestroy);
 
     // Increment past our save areas.
     if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
@@ -863,7 +857,8 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
     if (AFI->getDPRCalleeSavedGapSize()) {
       assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
              "unexpected DPR alignment gap");
-      emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
+      emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(),
+                   MachineInstr::FrameDestroy);
     }
 
     if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
@@ -871,7 +866,8 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
   }
 
   if (ArgRegsSaveSize)
-    emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
+    emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize,
+                 MachineInstr::FrameDestroy);
 }
 
 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
@@ -1118,7 +1114,8 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
     if (Regs.size() > 1 || LdrOpc == 0) {
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
                                     .addReg(ARM::SP)
-                                    .add(predOps(ARMCC::AL));
+                                    .add(predOps(ARMCC::AL))
+                                    .setMIFlags(MachineInstr::FrameDestroy);
       for (unsigned i = 0, e = Regs.size(); i < e; ++i)
         MIB.addReg(Regs[i], getDefRegState(true));
       if (DeleteRet) {
@@ -1136,7 +1133,8 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
       MachineInstrBuilder MIB =
         BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
           .addReg(ARM::SP, RegState::Define)
-          .addReg(ARM::SP);
+          .addReg(ARM::SP)
+          .setMIFlags(MachineInstr::FrameDestroy);
       // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
       // that refactoring is complete (eventually).
       if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
@@ -1179,7 +1177,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
     int FI = CSI[i].getFrameIdx();
     // The even-numbered registers will be 16-byte aligned, the odd-numbered
     // registers will be 8-byte aligned.
-    MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
+    MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16));
 
     // The stack slot for D8 needs to be maximally aligned because this is
     // actually the point where we align the stack pointer.  MachineFrameInfo
@@ -1188,7 +1186,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
     // over-alignment is not realized because the code inserted below adjusts
     // the stack pointer by numregs * 8 before aligning the stack pointer.
     if (DNum == 0)
-      MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
+      MFI.setObjectAlignment(FI, MFI.getMaxAlign());
   }
 
   // Move the stack pointer to the d8 spill slot, and align it at the same
@@ -1211,7 +1209,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
 
-  unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
+  Align MaxAlign = MF.getFrameInfo().getMaxAlign();
   // We must set parameter MustBeSingleInstruction to true, since
   // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
   // stack alignment.  Luckily, this can always be done since all ARM
@@ -1627,6 +1625,251 @@ checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
   SavedRegs.set(ARM::R4);
 }
 
+// Compute the set of registers which cannot be preserved, because they are
+// either modified outside the PUSH/POP instructions, or are live at the point
+// where the POP will be inserted. This only considers r0-r3, which are
+// currently the only registers we voluntatrily save when the PCS doesn't
+// require it.
+void ARMFrameLowering::findRegDefsOutsideSaveRestore(
+    MachineFunction &MF, BitVector &UnsaveableRegs) const {
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  SmallSet<MachineBasicBlock *, 2> SaveBlocks;
+  SmallSet<MachineBasicBlock *, 2> RestoreBlocks;
+
+  if (MFI.getSavePoint()) {
+    SaveBlocks.insert(MFI.getSavePoint());
+    RestoreBlocks.insert(MFI.getRestorePoint());
+  } else {
+    SaveBlocks.insert(&MF.front());
+    for (MachineBasicBlock &MBB : MF)
+      if (MBB.isReturnBlock())
+        RestoreBlocks.insert(&MBB);
+  }
+
+  // Walk blocks from the function entry and exits (following control flow both
+  // ways), stopping when we get to a save/restore block. Check for
+  // instructions which modify any of the registers we care about.
+  SmallVector<MachineBasicBlock *, 4> WorkList;
+  SmallSet<MachineBasicBlock *, 4> VisitedBlocks;
+  LLVM_DEBUG(dbgs() << "Entry block: " << MF.front().getName() << "\n");
+  WorkList.push_back(&MF.front());
+  for (MachineBasicBlock &MBB : MF) {
+    if (MBB.isReturnBlock()) {
+      LLVM_DEBUG(dbgs() << "Return block: " << MBB.getName() << "\n");
+      WorkList.push_back(&MBB);
+    }
+  }
+
+  auto CheckOutsideInst = [&UnsaveableRegs, TRI](MachineInstr &MI) {
+    for (Register Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
+      if (MI.modifiesRegister(Reg, TRI)) {
+        UnsaveableRegs.set(Reg);
+        LLVM_DEBUG(dbgs() << "Register " << TRI->getName(Reg)
+                          << " modified by instruction " << MI << "\n");
+      }
+    }
+  };
+
+  while (!WorkList.empty()) {
+    MachineBasicBlock *MBB = WorkList.pop_back_val();
+
+    if (VisitedBlocks.count(MBB))
+      continue;
+    VisitedBlocks.insert(MBB);
+
+    bool IsSave = SaveBlocks.count(MBB);
+    bool IsRestore = RestoreBlocks.count(MBB);
+
+    LLVM_DEBUG(dbgs() << "Visiting block " << MBB->getName() << ", IsSave="
+                      << IsSave << ", IsRestore=" << IsRestore << "\n");
+
+    // If this is a restore block, the POP instruction will be inserted just
+    // before the terminator, so we need to consider any terminator
+    // instructions to be outside the preserved region. We also need to check
+    // for registers which are live at the POP insertion point, because these
+    // can't be restored without changing their value.
+    if (IsRestore) {
+      LivePhysRegs LPR(*TRI);
+      LPR.addLiveOuts(*MBB);
+      for (auto &Term : reverse(MBB->terminators())) {
+        LPR.stepBackward(Term);
+        CheckOutsideInst(Term);
+      }
+
+      for (Register Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
+        if (LPR.contains(Reg)) {
+          UnsaveableRegs.set(Reg);
+          LLVM_DEBUG(dbgs() << "Register " << TRI->getName(Reg)
+                            << " live-out of restore block " << MBB->getName()
+                            << "\n");
+        }
+      }
+    }
+
+    // If this block is completely outside the save/restore region, then any
+    // modified registers can't be preserved. A save block counts as being
+    // inside the saved region, with the possible exception of the last few
+    // instructions if it's also a restore block, handled above. We don't visit
+    // blocks which are completely inside the saved region and don't have any
+    // save/restore instructions, so don't need to check that here.
+    if (!IsSave && !IsRestore)
+      for (auto &MI : *MBB)
+        CheckOutsideInst(MI);
+
+    // Walk the control flow graph in both directions, except for blocks which
+    // are inside the PUSH/POP region.
+    if (IsSave || !IsRestore)
+      for (auto Pred : MBB->predecessors())
+        WorkList.push_back(Pred);
+    if (!IsSave || IsRestore)
+      for (auto Succ : MBB->successors())
+        WorkList.push_back(Succ);
+  }
+}
+
+bool ARMFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
+  // Shrink wrapping is detrimental to code size because it prevents merging
+  // the CSR restore and function return into one POP instruction. It also
+  // conflicts with saving extra registers for IPRA, because it makes more
+  // registers live at the PUSH/POP.
+  if (MF.getFunction().hasMinSize())
+    return false;
+
+  return true;
+}
+
+// When doing inter-procedural register allocation, saving extra registers in
+// [r0,r3] will allow us to keep live values in them in any callers. The extra
+// saves and restores don't cost us any code-size if we are already emitting
+// PUSH and POP instructions.
+unsigned ARMFrameLowering::spillExtraRegsForIPRA(MachineFunction &MF,
+                                                 BitVector &SavedRegs,
+                                                 bool HasFPRegSaves) const {
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  LLVM_DEBUG(dbgs() << "Extra spills for " << MF.getName() << ": ");
+
+  if (!EnableExtraSpills) {
+    LLVM_DEBUG(dbgs() << "optimisation not enabled\n");
+    return 0;
+  }
+
+  // If IPRA is not enabled, nothing will be able to take advantage of the
+  // extra saved registers.
+  if (!MF.getTarget().Options.EnableIPRA) {
+    LLVM_DEBUG(dbgs() << "IPRA disabled\n");
+    return 0;
+  }
+
+  // These registers will take extra time to save and restore, and will often
+  // go unused, so only to this at -Oz.
+  if (!MF.getFunction().hasMinSize()) {
+    LLVM_DEBUG(dbgs() << "not minsize\n");
+    return 0;
+  }
+
+  // If we are not currently spilling any registers, we'd need to add an extra
+  // PUSH/POP pair, so this isn't worth it.
+  if (!SavedRegs.any()) {
+    LLVM_DEBUG(dbgs() << "no existing push/pop\n");
+    return 0;
+  }
+
+  // If we can't guarantee that this definition of the function is the one
+  // which will be picked by the linker, then IPRA can't make use of any extra
+  // saved registers.
+  if (!MF.getFunction().isDefinitionExact()) {
+    LLVM_DEBUG(dbgs() << "inexact definition\n");
+    return 0;
+  }
+
+  int NumVisibleCallers = 0;
+  for (const User *U : MF.getFunction().users()) {
+    if (const CallBase *Call = dyn_cast<CallBase>(U)) {
+      if (Call->getCalledOperand() == &MF.getFunction()) {
+        ++NumVisibleCallers;
+      }
+    }
+  }
+
+  // If we don't have any direct callers in the current translation unit,
+  // nothing will be able to take advantage of the extra saved registers.
+  if (NumVisibleCallers == 0 && !ForceExtraSpills) {
+    LLVM_DEBUG(dbgs() << "no visible callers\n");
+    return 0;
+  }
+
+  // If we need to emit unwind tables, these will be longer if we need to
+  // preserve r0-r3, so we need a lot of visible calls to make this worthwhile.
+  if (MF.getFunction().needsUnwindTableEntry() && NumVisibleCallers <= 8 &&
+      !ForceExtraSpills) {
+    LLVM_DEBUG(dbgs() << "needs unwind table\n");
+    return 0;
+  }
+
+  // Ok, we've decided we are going to try the optimisation.
+  LLVM_DEBUG(dbgs() << "enabled\n");
+
+  // Compute the registers which can't be preserved because they are either
+  // modified before the PUSH or after the POP, or are live at the point where
+  // the POP will be inserted.
+  BitVector NonPreserveableRegisters;
+  NonPreserveableRegisters.resize(TRI->getNumRegs());
+  findRegDefsOutsideSaveRestore(MF, NonPreserveableRegisters);
+
+  unsigned NumExtraRegs = 0;
+
+  // We'd also like to leave some registers free so that we can use them to
+  // fold a small SP update into the PUSH/POP. We can't know exactly what this
+  // optimisation can do, because stack layout isn't finalised, but we can make
+  // a good enough estimate.
+  unsigned StackSize = MFI.estimateStackSize(MF);
+
+  // If the stack space is large, we probably won't be able to fold the SP
+  // update into the push/pop, so we should use all the registers we want. If
+  // we have FP register saves, then the SP update will be folded into the
+  // VPUSH/VPOP instead, and we can use the GPRs freely.
+  if (StackSize > 16 || HasFPRegSaves)
+    StackSize = 0;
+
+  LLVM_DEBUG(dbgs() << "Estimated " << StackSize
+                    << " bytes of SP update being folded into push/pop\n");
+
+  for (Register Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
+    if (StackSize) {
+      StackSize -= 4;
+      LLVM_DEBUG(dbgs() << "not saving " << TRI->getName(Reg)
+                        << ", wanted for SP update\n");
+      continue;
+    }
+
+    // If we don't modify the register anywhere in this function, IPRA will
+    // already know that it is preserved, and there's no point in saving it.
+    if (!MRI.isPhysRegModified(Reg)) {
+      LLVM_DEBUG(dbgs() << "not saving " << TRI->getName(Reg)
+                        << ", not modified\n");
+      continue;
+    }
+
+    if (NonPreserveableRegisters[Reg]) {
+      LLVM_DEBUG(dbgs() << "not saving " << TRI->getName(Reg)
+                        << ", modified outide save region\n");
+      continue;
+    }
+
+    LLVM_DEBUG(dbgs() << "also saving " << TRI->getName(Reg) << " for IPRA\n");
+    SavedRegs.set(Reg);
+    MRI.enableCalleeSavedRegister(Reg);
+    ++NumExtraRegs;
+  }
+
+  return NumExtraRegs;
+}
+
 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                             BitVector &SavedRegs,
                                             RegScavenger *RS) const {
@@ -2017,6 +2260,14 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
                         << "\n");
     }
 
+    // When using IPRA, we might want to preserve some of r0-r3, to reduce
+    // register pressure in our callers.
+    unsigned ExtraIPRASpills =
+        spillExtraRegsForIPRA(MF, SavedRegs, NumFPRSpills != 0);
+    NumGPRSpills += ExtraIPRASpills;
+    if (ExtraIPRASpills)
+      CS1Spilled = true;
+
     // Avoid spilling LR in Thumb1 if there's a tail call: it's expensive to
     // restore LR in that case.
     bool ExpensiveLRRestore = AFI->isThumb1OnlyFunction() && MFI.hasTailCall();
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h
index f30f3895d9721..e03e2d0e1cdb9 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.h
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.h
@@ -56,6 +56,10 @@ class ARMFrameLowering : public TargetFrameLowering {
 
   void getCalleeSaves(const MachineFunction &MF,
                       BitVector &SavedRegs) const override;
+  void findRegDefsOutsideSaveRestore(MachineFunction &MF,
+                                     BitVector &Regs) const;
+  unsigned spillExtraRegsForIPRA(MachineFunction &MF, BitVector &SavedRegs,
+                                 bool HasFPRegSaves) const;
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
 
@@ -63,9 +67,8 @@ class ARMFrameLowering : public TargetFrameLowering {
                                 MachineBasicBlock &MBB) const override;
 
   /// Returns true if the target will correctly handle shrink wrapping.
-  bool enableShrinkWrapping(const MachineFunction &MF) const override {
-    return true;
-  }
+  bool enableShrinkWrapping(const MachineFunction &MF) const override;
+
   bool isProfitableForNoCSROpt(const Function &F) const override {
     // The no-CSR optimisation is bad for code size on ARM, because we can save
     // many registers with a single PUSH/POP pair.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 858ea8843162b..2e6bcb550999d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -911,7 +911,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::FMA, MVT::v4f32, Expand);
     }
 
-    setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
     setTargetDAGCombine(ISD::SHL);
     setTargetDAGCombine(ISD::SRL);
     setTargetDAGCombine(ISD::SRA);
@@ -939,6 +938,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setTargetDAGCombine(ISD::SIGN_EXTEND);
     setTargetDAGCombine(ISD::ZERO_EXTEND);
     setTargetDAGCombine(ISD::ANY_EXTEND);
+    setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
     setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
     setTargetDAGCombine(ISD::INTRINSIC_VOID);
     setTargetDAGCombine(ISD::VECREDUCE_ADD);
@@ -2458,26 +2458,25 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                                   RegsToPass[i].second.getValueType()));
 
   // Add a register mask operand representing the call-preserved registers.
-  if (!isTailCall) {
-    const uint32_t *Mask;
-    const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
-    if (isThisReturn) {
-      // For 'this' returns, use the R0-preserving mask if applicable
-      Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
-      if (!Mask) {
-        // Set isThisReturn to false if the calling convention is not one that
-        // allows 'returned' to be modeled in this way, so LowerCallResult does
-        // not try to pass 'this' straight through
-        isThisReturn = false;
-        Mask = ARI->getCallPreservedMask(MF, CallConv);
-      }
-    } else
+  const uint32_t *Mask;
+  const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
+  if (isThisReturn) {
+    // For 'this' returns, use the R0-preserving mask if applicable
+    Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
+    if (!Mask) {
+      // Set isThisReturn to false if the calling convention is not one that
+      // allows 'returned' to be modeled in this way, so LowerCallResult does
+      // not try to pass 'this' straight through
+      isThisReturn = false;
       Mask = ARI->getCallPreservedMask(MF, CallConv);
-
-    assert(Mask && "Missing call preserved mask for calling convention");
-    Ops.push_back(DAG.getRegisterMask(Mask));
+    }
+  } else {
+    Mask = ARI->getCallPreservedMask(MF, CallConv);
   }
 
+  assert(Mask && "Missing call preserved mask for calling convention");
+  Ops.push_back(DAG.getRegisterMask(Mask));
+
   if (InFlag.getNode())
     Ops.push_back(InFlag);
 
@@ -14173,7 +14172,9 @@ static SDValue PerformLongShiftCombine(SDNode *N, SelectionDAG &DAG) {
 }
 
 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
-static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
+SDValue ARMTargetLowering::PerformIntrinsicCombine(SDNode *N,
+                                                   DAGCombinerInfo &DCI) const {
+  SelectionDAG &DAG = DCI.DAG;
   unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
   switch (IntNo) {
   default:
@@ -14322,6 +14323,27 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
   case Intrinsic::arm_neon_vqrshiftu:
     // No immediate versions of these to check for.
     break;
+
+  case Intrinsic::arm_mve_vqdmlah:
+  case Intrinsic::arm_mve_vqdmlash:
+  case Intrinsic::arm_mve_vqrdmlah:
+  case Intrinsic::arm_mve_vqrdmlash:
+  case Intrinsic::arm_mve_vmla_n_predicated:
+  case Intrinsic::arm_mve_vmlas_n_predicated:
+  case Intrinsic::arm_mve_vqdmlah_predicated:
+  case Intrinsic::arm_mve_vqdmlash_predicated:
+  case Intrinsic::arm_mve_vqrdmlah_predicated:
+  case Intrinsic::arm_mve_vqrdmlash_predicated: {
+    // These intrinsics all take an i32 scalar operand which is narrowed to the
+    // size of a single lane of the vector type they return. So we don't need
+    // any bits of that operand above that point, which allows us to eliminate
+    // uxth/sxth.
+    unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
+    APInt DemandedMask = APInt::getLowBitsSet(32, BitWidth);
+    if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI))
+      return SDValue();
+    break;
+  }
   }
 
   return SDValue();
@@ -15041,7 +15063,8 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
     return PerformVCVTCombine(N, DCI.DAG, Subtarget);
   case ISD::FDIV:
     return PerformVDIVCombine(N, DCI.DAG, Subtarget);
-  case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
+  case ISD::INTRINSIC_WO_CHAIN:
+    return PerformIntrinsicCombine(N, DCI);
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
@@ -17056,7 +17079,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::arm_mve_vld4q: {
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     // Conservatively set memVT to the entire set of vectors loaded.
-    Type *VecTy = cast<CompositeType>(I.getType())->getTypeAtIndex(1);
+    Type *VecTy = cast<StructType>(I.getType())->getElementType(1);
     unsigned Factor = Intrinsic == Intrinsic::arm_mve_vld2q ? 2 : 4;
     Info.memVT = EVT::getVectorVT(VecTy->getContext(), MVT::i64, Factor * 2);
     Info.ptrVal = I.getArgOperand(0);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 99694cd9e0303..d95e4278e958e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -352,6 +352,7 @@ class VectorType;
     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
+    SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
     bool SimplifyDemandedBitsForTargetNode(SDValue Op,
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 20856ccdb4118..58164e57ab818 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4210,11 +4210,32 @@ class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
   let Inst{0} = round;
 }
 
+multiclass MVE_VQxDMLxDH_p<string iname, bit exch, bit round, bit subtract,
+                           MVEVectorVTInfo VTI> {
+  def "": MVE_VQxDMLxDH<iname, exch, round, subtract, VTI.Suffix, VTI.Size,
+                        !if(!eq(VTI.LaneBits, 32), ",@earlyclobber $Qd", "")>;
+  defvar Inst = !cast<Instruction>(NAME);
+  defvar ConstParams = (? (i32 exch), (i32 round), (i32 subtract));
+  defvar unpred_intr = int_arm_mve_vqdmlad;
+  defvar pred_intr = int_arm_mve_vqdmlad_predicated;
+
+  def : Pat<(VTI.Vec !con((unpred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
+                                       (VTI.Vec MQPR:$c)), ConstParams)),
+            (VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
+                           (VTI.Vec MQPR:$c)))>;
+  def : Pat<(VTI.Vec !con((pred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
+                                     (VTI.Vec MQPR:$c)), ConstParams,
+                          (? (VTI.Pred VCCR:$pred)))),
+            (VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
+                           (VTI.Vec MQPR:$c),
+                           ARMVCCThen, (VTI.Pred VCCR:$pred)))>;
+}
+
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
                                bit round, bit subtract> {
-  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00>;
-  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
-  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10, ",@earlyclobber $Qd">;
+  defm s8  : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v16s8>;
+  defm s16 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v8s16>;
+  defm s32 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v4s32>;
 }
 
 defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;
@@ -5152,48 +5173,49 @@ class MVE_VFMAMLA_qr<string iname, string suffix,
   let validForTailPredication = 1;
 }
 
-def MVE_VMLA_qr_s8     : MVE_VFMAMLA_qr<"vmla",  "s8",  0b0, 0b00, 0b0>;
-def MVE_VMLA_qr_s16    : MVE_VFMAMLA_qr<"vmla",  "s16", 0b0, 0b01, 0b0>;
-def MVE_VMLA_qr_s32    : MVE_VFMAMLA_qr<"vmla",  "s32", 0b0, 0b10, 0b0>;
-def MVE_VMLA_qr_u8     : MVE_VFMAMLA_qr<"vmla",  "u8",  0b1, 0b00, 0b0>;
-def MVE_VMLA_qr_u16    : MVE_VFMAMLA_qr<"vmla",  "u16", 0b1, 0b01, 0b0>;
-def MVE_VMLA_qr_u32    : MVE_VFMAMLA_qr<"vmla",  "u32", 0b1, 0b10, 0b0>;
+multiclass MVE_VMLA_qr_multi<string iname, MVEVectorVTInfo VTI,
+                             bit scalar_addend> {
+  def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
+                         scalar_addend>;
+  defvar Inst = !cast<Instruction>(NAME);
+  defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_n_predicated");
+  defvar v1   = (VTI.Vec MQPR:$v1);
+  defvar v2   = (VTI.Vec MQPR:$v2);
+  defvar vs   = (VTI.Vec (ARMvdup rGPR:$s));
+  defvar s    = (i32 rGPR:$s);
+  defvar pred = (VTI.Pred VCCR:$pred);
 
-def MVE_VMLAS_qr_s8    : MVE_VFMAMLA_qr<"vmlas", "s8",  0b0, 0b00, 0b1>;
-def MVE_VMLAS_qr_s16   : MVE_VFMAMLA_qr<"vmlas", "s16", 0b0, 0b01, 0b1>;
-def MVE_VMLAS_qr_s32   : MVE_VFMAMLA_qr<"vmlas", "s32", 0b0, 0b10, 0b1>;
-def MVE_VMLAS_qr_u8    : MVE_VFMAMLA_qr<"vmlas", "u8",  0b1, 0b00, 0b1>;
-def MVE_VMLAS_qr_u16   : MVE_VFMAMLA_qr<"vmlas", "u16", 0b1, 0b01, 0b1>;
-def MVE_VMLAS_qr_u32   : MVE_VFMAMLA_qr<"vmlas", "u32", 0b1, 0b10, 0b1>;
+  // The signed and unsigned variants of this instruction have different
+  // encodings, but they're functionally identical. For the sake of
+  // determinism, we generate only the unsigned variant.
+  if VTI.Unsigned then let Predicates = [HasMVEInt] in {
+    if scalar_addend then {
+      def : Pat<(VTI.Vec (add (mul v1, v2), vs)),
+                (VTI.Vec (Inst v1, v2, s))>;
+    } else {
+      def : Pat<(VTI.Vec (add (mul v2, vs), v1)),
+                (VTI.Vec (Inst v1, v2, s))>;
+    }
 
-let Predicates = [HasMVEInt] in {
-  def : Pat<(v4i32 (add (v4i32 MQPR:$src1),
-                        (v4i32 (mul (v4i32 MQPR:$src2),
-                                    (v4i32 (ARMvdup (i32 rGPR:$x))))))),
-            (v4i32 (MVE_VMLA_qr_u32 $src1, $src2, $x))>;
-  def : Pat<(v8i16 (add (v8i16 MQPR:$src1),
-                        (v8i16 (mul (v8i16 MQPR:$src2),
-                                    (v8i16 (ARMvdup (i32 rGPR:$x))))))),
-            (v8i16 (MVE_VMLA_qr_u16 $src1, $src2, $x))>;
-  def : Pat<(v16i8 (add (v16i8 MQPR:$src1),
-                        (v16i8 (mul (v16i8 MQPR:$src2),
-                                    (v16i8 (ARMvdup (i32 rGPR:$x))))))),
-            (v16i8 (MVE_VMLA_qr_u8 $src1, $src2, $x))>;
-
-  def : Pat<(v4i32 (add (v4i32 (ARMvdup (i32 rGPR:$x))),
-                        (v4i32 (mul (v4i32 MQPR:$src1),
-                                    (v4i32 MQPR:$src2))))),
-            (v4i32 (MVE_VMLAS_qr_u32 $src1, $src2, $x))>;
-  def : Pat<(v8i16 (add (v8i16 (ARMvdup (i32 rGPR:$x))),
-                        (v8i16 (mul (v8i16 MQPR:$src1),
-                                    (v8i16 MQPR:$src2))))),
-            (v8i16 (MVE_VMLAS_qr_u16 $src1, $src2, $x))>;
-  def : Pat<(v16i8 (add (v16i8 (ARMvdup (i32 rGPR:$x))),
-                        (v16i8 (mul (v16i8 MQPR:$src1),
-                                    (v16i8 MQPR:$src2))))),
-            (v16i8 (MVE_VMLAS_qr_u8 $src1, $src2, $x))>;
+    def : Pat<(VTI.Vec (pred_int v1, v2, s, pred)),
+              (VTI.Vec (Inst v1, v2, s, ARMVCCThen, pred))>;
+  }
 }
 
+defm MVE_VMLA_qr_s8   : MVE_VMLA_qr_multi<"vmla", MVE_v16s8, 0b0>;
+defm MVE_VMLA_qr_s16  : MVE_VMLA_qr_multi<"vmla", MVE_v8s16, 0b0>;
+defm MVE_VMLA_qr_s32  : MVE_VMLA_qr_multi<"vmla", MVE_v4s32, 0b0>;
+defm MVE_VMLA_qr_u8   : MVE_VMLA_qr_multi<"vmla", MVE_v16u8, 0b0>;
+defm MVE_VMLA_qr_u16  : MVE_VMLA_qr_multi<"vmla", MVE_v8u16, 0b0>;
+defm MVE_VMLA_qr_u32  : MVE_VMLA_qr_multi<"vmla", MVE_v4u32, 0b0>;
+
+defm MVE_VMLAS_qr_s8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16s8, 0b1>;
+defm MVE_VMLAS_qr_s16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8s16, 0b1>;
+defm MVE_VMLAS_qr_s32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4s32, 0b1>;
+defm MVE_VMLAS_qr_u8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16u8, 0b1>;
+defm MVE_VMLAS_qr_u16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8u16, 0b1>;
+defm MVE_VMLAS_qr_u32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4u32, 0b1>;
+
 multiclass MVE_VFMA_qr_multi<string iname, MVEVectorVTInfo VTI,
                              bit scalar_addend> {
   def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Size{0}, 0b11, scalar_addend>;
@@ -5241,10 +5263,30 @@ class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
   let Inst{5} = bit_5;
 }
 
+multiclass MVE_VQDMLAH_qr_multi<string iname, MVEVectorVTInfo VTI,
+                                bit bit_5, bit bit_12> {
+  def "": MVE_VQDMLAH_qr<iname, VTI.Suffix, 0b0, VTI.Size, bit_5, bit_12>;
+  defvar Inst = !cast<Instruction>(NAME);
+  defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # iname);
+  defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_predicated");
+
+  let Predicates = [HasMVEInt] in {
+    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
+                                   (i32 rGPR:$s))),
+              (VTI.Vec (Inst       (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
+                                   (i32 rGPR:$s)))>;
+    def : Pat<(VTI.Vec (pred_int   (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
+                                   (i32 rGPR:$s), (VTI.Pred VCCR:$pred))),
+              (VTI.Vec (Inst       (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
+                                   (i32 rGPR:$s), ARMVCCThen,
+                                   (VTI.Pred VCCR:$pred)))>;
+  }
+}
+
 multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
-  def s8  : MVE_VQDMLAH_qr<iname, "s8",  0b0, 0b00, bit_5, bit_12>;
-  def s16 : MVE_VQDMLAH_qr<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
-  def s32 : MVE_VQDMLAH_qr<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
+  defm s8  : MVE_VQDMLAH_qr_multi<iname, MVE_v16s8, bit_5, bit_12>;
+  defm s16 : MVE_VQDMLAH_qr_multi<iname, MVE_v8s16, bit_5, bit_12>;
+  defm s32 : MVE_VQDMLAH_qr_multi<iname, MVE_v4s32, bit_5, bit_12>;
 }
 
 defm MVE_VQDMLAH_qr   : MVE_VQDMLAH_qr_types<"vqdmlah",   0b1, 0b0>;
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 12dddd29ca847..a0e7a6f2b6ff4 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -991,7 +991,7 @@ static bool mayCombineMisaligned(const TargetSubtargetInfo &STI,
   // Stack pointer alignment is out of the programmers control so we can trust
   // SP-relative loads/stores.
   if (getLoadStoreBaseOp(MI).getReg() == ARM::SP &&
-      STI.getFrameLowering()->getTransientStackAlignment() >= 4)
+      STI.getFrameLowering()->getTransientStackAlign() >= Align(4))
     return true;
   return false;
 }
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index c0632016ccf05..0e024437667e8 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -216,6 +216,10 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
         break;
       }
       LLVM_FALLTHROUGH;
+    case ARM::R0:
+    case ARM::R1:
+    case ARM::R2:
+    case ARM::R3:
     case ARM::R4:
     case ARM::R5:
     case ARM::R6:
@@ -402,7 +406,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 
   if (RegInfo->needsStackRealignment(MF)) {
-    const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
+    const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
     // Emit the following sequence, using R4 as a temporary, since we cannot use
     // SP as a source or destination register for the shifts:
     // mov  r4, sp
@@ -848,7 +852,8 @@ bool Thumb1FrameLowering::spillCalleeSavedRegisters(
   if (!LoRegsToSave.none()) {
     MachineInstrBuilder MIB =
         BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
-    for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
+    for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5,
+                         ARM::R6, ARM::R7, ARM::LR}) {
       if (LoRegsToSave[Reg]) {
         bool isKill = !MRI.isLiveIn(Reg);
         if (isKill && !MRI.isReserved(Reg))
@@ -956,6 +961,9 @@ bool Thumb1FrameLowering::restoreCalleeSavedRegisters(
       llvm_unreachable("callee-saved register of unexpected class");
     }
 
+    if (Reg == ARM::LR)
+      I.setRestored(false);
+
     // If this is a low register not used as the frame pointer, we may want to
     // use it for restoring the high registers.
     if ((ARM::tGPRRegClass.contains(Reg)) &&
@@ -980,6 +988,9 @@ bool Thumb1FrameLowering::restoreCalleeSavedRegisters(
   static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
                                          ARM::R4, ARM::R5, ARM::R6, ARM::R7};
   static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
+  static const unsigned AllLoRegs[] = {ARM::R0, ARM::R1, ARM::R2,
+                                       ARM::R3, ARM::R4, ARM::R5,
+                                       ARM::R6, ARM::R7, ARM::LR};
 
   const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
   const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
@@ -1018,16 +1029,10 @@ bool Thumb1FrameLowering::restoreCalleeSavedRegisters(
       BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
 
   bool NeedsPop = false;
-  for (unsigned i = CSI.size(); i != 0; --i) {
-    CalleeSavedInfo &Info = CSI[i-1];
-    unsigned Reg = Info.getReg();
-
-    // High registers (excluding lr) have already been dealt with
-    if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
+  for (unsigned Reg : AllLoRegs) {
+    if (!LoRegsToRestore[Reg])
       continue;
-
     if (Reg == ARM::LR) {
-      Info.setRestored(false);
       if (!MBB.succ_empty() ||
           MI->getOpcode() == ARM::TCRETURNdi ||
           MI->getOpcode() == ARM::TCRETURNri)
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index e31a61ce5d8ca..1c77b68a9012f 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -284,6 +284,8 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
   const SDNode *N = Op.getNode();
   EVT VT = Op.getValueType();
   SDLoc dl(N);
+  assert(isPowerOf2_32(VT.getSizeInBits()) &&
+         "Expected power-of-2 shift amount");
 
   // Expand non-constant shifts to loops.
   if (!isa<ConstantSDNode>(N->getOperand(1))) {
@@ -296,12 +298,20 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
     case ISD::SRL:
       return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
                          N->getOperand(1));
-    case ISD::ROTL:
-      return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
-                         N->getOperand(1));
-    case ISD::ROTR:
-      return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
-                         N->getOperand(1));
+    case ISD::ROTL: {
+      SDValue Amt = N->getOperand(1);
+      EVT AmtVT = Amt.getValueType();
+      Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
+                        DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
+      return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
+    }
+    case ISD::ROTR: {
+      SDValue Amt = N->getOperand(1);
+      EVT AmtVT = Amt.getValueType();
+      Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
+                        DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
+      return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
+    }
     case ISD::SRA:
       return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
                          N->getOperand(1));
@@ -317,9 +327,11 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
     break;
   case ISD::ROTL:
     Opc8 = AVRISD::ROL;
+    ShiftAmount = ShiftAmount % VT.getSizeInBits();
     break;
   case ISD::ROTR:
     Opc8 = AVRISD::ROR;
+    ShiftAmount = ShiftAmount % VT.getSizeInBits();
     break;
   case ISD::SRL:
     Opc8 = AVRISD::LSR;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
index 1a741c9077507..cf2cb3c47a620 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
@@ -34,8 +34,9 @@ namespace adjust {
 
 using namespace llvm;
 
-void signed_width(unsigned Width, uint64_t Value, std::string Description,
-                  const MCFixup &Fixup, MCContext *Ctx = nullptr) {
+static void signed_width(unsigned Width, uint64_t Value,
+                         std::string Description, const MCFixup &Fixup,
+                         MCContext *Ctx = nullptr) {
   if (!isIntN(Width, Value)) {
     std::string Diagnostic = "out of range " + Description;
 
@@ -53,8 +54,9 @@ void signed_width(unsigned Width, uint64_t Value, std::string Description,
   }
 }
 
-void unsigned_width(unsigned Width, uint64_t Value, std::string Description,
-                    const MCFixup &Fixup, MCContext *Ctx = nullptr) {
+static void unsigned_width(unsigned Width, uint64_t Value,
+                           std::string Description, const MCFixup &Fixup,
+                           MCContext *Ctx = nullptr) {
   if (!isUIntN(Width, Value)) {
     std::string Diagnostic = "out of range " + Description;
 
@@ -72,8 +74,8 @@ void unsigned_width(unsigned Width, uint64_t Value, std::string Description,
 }
 
 /// Adjusts the value of a branch target before fixup application.
-void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-                  MCContext *Ctx = nullptr) {
+static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                         MCContext *Ctx = nullptr) {
   // We have one extra bit of precision because the value is rightshifted by
   // one.
   unsigned_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
@@ -83,8 +85,8 @@ void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
 }
 
 /// Adjusts the value of a relative branch target before fixup application.
-void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-                          MCContext *Ctx = nullptr) {
+static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
+                                 uint64_t &Value, MCContext *Ctx = nullptr) {
   // We have one extra bit of precision because the value is rightshifted by
   // one.
   signed_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
@@ -101,8 +103,8 @@ void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
 /// 1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
 ///
 /// Offset of 0 (so the result is left shifted by 3 bits before application).
-void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-                MCContext *Ctx = nullptr) {
+static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                       MCContext *Ctx = nullptr) {
   adjustBranch(Size, Fixup, Value, Ctx);
 
   auto top = Value & (0xf00000 << 6);   // the top four bits
@@ -117,8 +119,8 @@ void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
 /// Resolves to:
 /// 0000 00kk kkkk k000
 /// Offset of 0 (so the result is left shifted by 3 bits before application).
-void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-                   MCContext *Ctx = nullptr) {
+static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                          MCContext *Ctx = nullptr) {
   adjustRelativeBranch(Size, Fixup, Value, Ctx);
 
   // Because the value may be negative, we must mask out the sign bits
@@ -131,8 +133,8 @@ void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
 /// Resolves to:
 /// 0000 kkkk kkkk kkkk
 /// Offset of 0 (so the result isn't left-shifted before application).
-void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-                    MCContext *Ctx = nullptr) {
+static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                           MCContext *Ctx = nullptr) {
   adjustRelativeBranch(Size, Fixup, Value, Ctx);
 
   // Because the value may be negative, we must mask out the sign bits
@@ -144,8 +146,8 @@ void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
 ///
 /// Resolves to:
 /// 0000 0000 kk00 kkkk
-void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
-                  MCContext *Ctx = nullptr) {
+static void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
+                         MCContext *Ctx = nullptr) {
   unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
 
   Value = ((Value & 0x30) << 2) | (Value & 0x0f);
@@ -155,8 +157,8 @@ void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
 ///
 /// Resolves to:
 /// 0000 0000 AAAA A000
-void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
-                 MCContext *Ctx = nullptr) {
+static void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
+                        MCContext *Ctx = nullptr) {
   unsigned_width(5, Value, std::string("port number"), Fixup, Ctx);
 
   Value &= 0x1f;
@@ -168,8 +170,8 @@ void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
 ///
 /// Resolves to:
 /// 1011 0AAd dddd AAAA
-void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
-                 MCContext *Ctx = nullptr) {
+static void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
+                        MCContext *Ctx = nullptr) {
   unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
 
   Value = ((Value & 0x30) << 5) | (Value & 0x0f);
@@ -177,9 +179,7 @@ void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
 
 /// Adjusts a program memory address.
 /// This is a simple right-shift.
-void pm(uint64_t &Value) {
-  Value >>= 1;
-}
+static void pm(uint64_t &Value) { Value >>= 1; }
 
 /// Fixups relating to the LDI instruction.
 namespace ldi {
@@ -189,36 +189,36 @@ namespace ldi {
 /// Resolves to:
 /// 0000 KKKK 0000 KKKK
 /// Offset of 0 (so the result isn't left-shifted before application).
-void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-           MCContext *Ctx = nullptr) {
+static void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                  MCContext *Ctx = nullptr) {
   uint64_t upper = Value & 0xf0;
   uint64_t lower = Value & 0x0f;
 
   Value = (upper << 4) | lower;
 }
 
-void neg(uint64_t &Value) { Value *= -1; }
+static void neg(uint64_t &Value) { Value *= -1; }
 
-void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-         MCContext *Ctx = nullptr) {
+static void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                MCContext *Ctx = nullptr) {
   Value &= 0xff;
   ldi::fixup(Size, Fixup, Value, Ctx);
 }
 
-void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-         MCContext *Ctx = nullptr) {
+static void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                MCContext *Ctx = nullptr) {
   Value = (Value & 0xff00) >> 8;
   ldi::fixup(Size, Fixup, Value, Ctx);
 }
 
-void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-         MCContext *Ctx = nullptr) {
+static void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                MCContext *Ctx = nullptr) {
   Value = (Value & 0xff0000) >> 16;
   ldi::fixup(Size, Fixup, Value, Ctx);
 }
 
-void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
-         MCContext *Ctx = nullptr) {
+static void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
+                MCContext *Ctx = nullptr) {
   Value = (Value & 0xff000000) >> 24;
   ldi::fixup(Size, Fixup, Value, Ctx);
 }
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt
index 3536aa81fb215..747f14e0ceca0 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -64,9 +64,6 @@ add_llvm_target(HexagonCodeGen
   HexagonVLIWPacketizer.cpp
   RDFCopy.cpp
   RDFDeadCode.cpp
-  RDFGraph.cpp
-  RDFLiveness.cpp
-  RDFRegisters.cpp
 )
 
 add_subdirectory(AsmParser)
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 1a2d92719c5e7..1601d5600cc29 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -591,7 +591,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
   auto &HII = *HST.getInstrInfo();
   auto &HRI = *HST.getRegisterInfo();
 
-  unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment());
+  Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
 
   // Calculate the total stack frame size.
   // Get the number of bytes to allocate from the FrameInfo.
@@ -603,7 +603,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
   FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
   MFI.setStackSize(FrameSize);
 
-  bool AlignStack = (MaxAlign > getStackAlignment());
+  bool AlignStack = (MaxAlign > getStackAlign());
 
   // Get the number of bytes to allocate from the FrameInfo.
   unsigned NumBytes = MFI.getStackSize();
@@ -742,7 +742,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
     if (AlignStack) {
       BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
           .addReg(SP)
-          .addImm(-int64_t(MaxAlign));
+          .addImm(-int64_t(MaxAlign.value()));
     }
     // If the stack-checking is enabled, and we spilled the callee-saved
     // registers inline (i.e. did not use a spill function), then call
@@ -1507,7 +1507,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
   // via AP, which may not be available at the particular place in the program.
   MachineFrameInfo &MFI = MF.getFrameInfo();
   bool HasAlloca = MFI.hasVarSizedObjects();
-  bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment());
+  bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
 
   if (!HasAlloca || !NeedsAlign)
     return;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index e220a0765e2d5..388c5feb0e11b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -734,8 +734,8 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
   MachineFrameInfo &MFI = MF->getFrameInfo();
   const HexagonFrameLowering *HFI = HST->getFrameLowering();
   int FX = cast<FrameIndexSDNode>(N)->getIndex();
-  unsigned StkA = HFI->getStackAlignment();
-  unsigned MaxA = MFI.getMaxAlignment();
+  Align StkA = HFI->getStackAlign();
+  Align MaxA = MFI.getMaxAlign();
   SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
   SDLoc DL(N);
   SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
@@ -1284,9 +1284,9 @@ void HexagonDAGToDAGISel::emitFunctionEntryCode() {
   MachineFrameInfo &MFI = MF->getFrameInfo();
   MachineBasicBlock *EntryBB = &MF->front();
   unsigned AR = FuncInfo->CreateReg(MVT::i32);
-  unsigned EntryMaxA = MFI.getMaxAlignment();
+  Align EntryMaxA = MFI.getMaxAlign();
   BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
-      .addImm(EntryMaxA);
+      .addImm(EntryMaxA.value());
   MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
 }
 
@@ -1296,7 +1296,7 @@ void HexagonDAGToDAGISel::updateAligna() {
     return;
   auto *AlignaI = const_cast<MachineInstr*>(HFI.getAlignaInstr(*MF));
   assert(AlignaI != nullptr);
-  unsigned MaxA = MF->getFrameInfo().getMaxAlignment();
+  unsigned MaxA = MF->getFrameInfo().getMaxAlign().value();
   if (AlignaI->getOperand(1).getImm() < MaxA)
     AlignaI->getOperand(1).setImm(MaxA);
 }
diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index a8c0921ec6151..c718e5f2d9fbe 100644
--- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -12,9 +12,6 @@
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
-#include "RDFGraph.h"
-#include "RDFLiveness.h"
-#include "RDFRegisters.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/StringRef.h"
@@ -27,6 +24,9 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFLiveness.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/MCInstrDesc.h"
diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
index 517ad1c6ee7b4..f26e23befde21 100644
--- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
@@ -11,9 +11,6 @@
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "RDFCopy.h"
 #include "RDFDeadCode.h"
-#include "RDFGraph.h"
-#include "RDFLiveness.h"
-#include "RDFRegisters.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
@@ -24,6 +21,9 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFLiveness.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
diff --git a/llvm/lib/Target/Hexagon/RDFCopy.cpp b/llvm/lib/Target/Hexagon/RDFCopy.cpp
index a9d39fd4b2dcb..34d58f0a7a230 100644
--- a/llvm/lib/Target/Hexagon/RDFCopy.cpp
+++ b/llvm/lib/Target/Hexagon/RDFCopy.cpp
@@ -11,13 +11,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "RDFCopy.h"
-#include "RDFGraph.h"
-#include "RDFLiveness.h"
-#include "RDFRegisters.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFLiveness.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
diff --git a/llvm/lib/Target/Hexagon/RDFCopy.h b/llvm/lib/Target/Hexagon/RDFCopy.h
index 1450ab8848492..99b18a75d8c2b 100644
--- a/llvm/lib/Target/Hexagon/RDFCopy.h
+++ b/llvm/lib/Target/Hexagon/RDFCopy.h
@@ -9,9 +9,9 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFCOPY_H
 #define LLVM_LIB_TARGET_HEXAGON_RDFCOPY_H
 
-#include "RDFGraph.h"
-#include "RDFLiveness.h"
-#include "RDFRegisters.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFLiveness.h"
+#include "llvm/CodeGen/RDFRegisters.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include <map>
 #include <vector>
diff --git a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp
index af86c7b1956bc..5a98debd3c000 100644
--- a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp
+++ b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp
@@ -9,13 +9,13 @@
 // RDF-based generic dead code elimination.
 
 #include "RDFDeadCode.h"
-#include "RDFGraph.h"
-#include "RDFLiveness.h"
 
 #include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFLiveness.h"
 #include "llvm/Support/Debug.h"
 
 #include <queue>
diff --git a/llvm/lib/Target/Hexagon/RDFDeadCode.h b/llvm/lib/Target/Hexagon/RDFDeadCode.h
index 7f91977e1d6cd..859c8161d355c 100644
--- a/llvm/lib/Target/Hexagon/RDFDeadCode.h
+++ b/llvm/lib/Target/Hexagon/RDFDeadCode.h
@@ -23,8 +23,8 @@
 #ifndef RDF_DEADCODE_H
 #define RDF_DEADCODE_H
 
-#include "RDFGraph.h"
-#include "RDFLiveness.h"
+#include "llvm/CodeGen/RDFGraph.h"
+#include "llvm/CodeGen/RDFLiveness.h"
 #include "llvm/ADT/SetVector.h"
 
 namespace llvm {
diff --git a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
index eddc2b8e61f7d..3c84ed057fd19 100644
--- a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
@@ -32,8 +32,8 @@ void LanaiFrameLowering::determineFrameLayout(MachineFunction &MF) const {
   unsigned FrameSize = MFI.getStackSize();
 
   // Get the alignment.
-  unsigned StackAlign = LRI->needsStackRealignment(MF) ? MFI.getMaxAlignment()
-                                                       : getStackAlignment();
+  Align StackAlign =
+      LRI->needsStackRealignment(MF) ? MFI.getMaxAlign() : getStackAlign();
 
   // Get the maximum call frame size of all the calls.
   unsigned MaxCallFrameSize = MFI.getMaxCallFrameSize();
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 7046f03cf082b..df1d2d0832326 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -368,6 +368,7 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool parseSetMsaDirective();
   bool parseSetNoMsaDirective();
   bool parseSetNoDspDirective();
+  bool parseSetNoMips3DDirective();
   bool parseSetReorderDirective();
   bool parseSetNoReorderDirective();
   bool parseSetMips16Directive();
@@ -6985,6 +6986,21 @@ bool MipsAsmParser::parseSetNoDspDirective() {
   return false;
 }
 
+bool MipsAsmParser::parseSetNoMips3DDirective() {
+  MCAsmParser &Parser = getParser();
+  Parser.Lex(); // Eat "nomips3d".
+
+  // If this is not the end of the statement, report an error.
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    reportParseError("unexpected token, expected end of statement");
+    return false;
+  }
+
+  clearFeatureBits(Mips::FeatureMips3D, "mips3d");
+  getTargetStreamer().emitDirectiveSetNoMips3D();
+  return false;
+}
+
 bool MipsAsmParser::parseSetMips16Directive() {
   MCAsmParser &Parser = getParser();
   Parser.Lex(); // Eat "mips16".
@@ -7317,6 +7333,10 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
   switch (Feature) {
   default:
     llvm_unreachable("Unimplemented feature");
+  case Mips::FeatureMips3D:
+    setFeatureBits(Mips::FeatureMips3D, "mips3d");
+    getTargetStreamer().emitDirectiveSetMips3D();
+    break;
   case Mips::FeatureDSP:
     setFeatureBits(Mips::FeatureDSP, "dsp");
     getTargetStreamer().emitDirectiveSetDsp();
@@ -7732,6 +7752,10 @@ bool MipsAsmParser::parseDirectiveSet() {
     return parseSetFeature(Mips::FeatureDSPR2);
   if (IdVal == "nodsp")
     return parseSetNoDspDirective();
+  if (IdVal == "mips3d")
+    return parseSetFeature(Mips::FeatureMips3D);
+  if (IdVal == "nomips3d")
+    return parseSetNoMips3DDirective();
   if (IdVal == "msa")
     return parseSetMsaDirective();
   if (IdVal == "nomsa")
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 1fcc537207f52..579273004f1d7 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -109,6 +109,8 @@ void MipsTargetStreamer::emitDirectiveSetHardFloat() {
 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
 void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
   // .cplocal $reg
@@ -609,6 +611,16 @@ void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
   MipsTargetStreamer::emitDirectiveSetNoDsp();
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips3D() {
+  OS << "\t.set\tmips3d\n";
+  MipsTargetStreamer::emitDirectiveSetMips3D();
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() {
+  OS << "\t.set\tnomips3d\n";
+  MipsTargetStreamer::emitDirectiveSetNoMips3D();
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
   OS << "\t.set\tpop\n";
   MipsTargetStreamer::emitDirectiveSetPop();
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index bed66e8075815..7fe750249c588 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -161,6 +161,8 @@ def FeatureDSPR3
     : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
                        [ FeatureDSP, FeatureDSPR2 ]>;
 
+def FeatureMips3D : SubtargetFeature<"mips3d", "Has3D", "true", "Mips 3D ASE">;
+
 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 
 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 4ad0665d18236..37a0aefc9636e 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -72,6 +72,8 @@ def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
                        AssemblerPredicate<(all_of (not FeatureSingleFloat))>;
 def IsNotSoftFloat   : Predicate<"!Subtarget->useSoftFloat()">,
                        AssemblerPredicate<(all_of (not FeatureSoftFloat))>;
+def Mips3D           : Predicate<"Subtarget->has3D()">,
+                       AssemblerPredicate<(all_of FeatureMips3D)>;
 
 //===----------------------------------------------------------------------===//
 // Mips FGR size adjectives.
@@ -456,6 +458,12 @@ let DecoderNamespace = "MipsFP64" in {
     def PLU_PS64    : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
                       ADDS_FM<0x2D, 22>,
                       ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def PUL_PS64    : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,
+                      ADDS_FM<0x2E, 22>,
+                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def PUU_PS64    : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
+                      ADDS_FM<0x2F, 22>,
+                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
 
     def CVT_S_PU64  : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
                       ABSS_FM<0x20, 22>,
@@ -470,6 +478,21 @@ let DecoderNamespace = "MipsFP64" in {
   }
 }
 
+let DecoderNamespace = "MipsFP64" in {
+  let AdditionalPredicates = [Mips3D] in {
+    def ADDR_PS64   : ADDS_FT<"addr.ps", FGR64Opnd, II_ADDR_PS, 0>,
+                      ADDS_FM<0x18, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def MULR_PS64   : ADDS_FT<"mulr.ps", FGR64Opnd, II_MULR_PS, 0>,
+                      ADDS_FM<0x1a, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd, II_CVT>,
+                      ABSS_FM<0x26, 20>,
+                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+    def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd, II_CVT>,
+                      ABSS_FM<0x24, 22>,
+                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
+  }
+}
+
 let DecoderNamespace = "MipsFP64" in {
   let AdditionalPredicates = [NotInMicroMips] in {
     def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index d5a44801dcf27..e0f4f9eab9dad 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -539,11 +539,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
       // addiu $Reg, $zero, -MaxAlignment
       // andi $sp, $sp, $Reg
       Register VR = MF.getRegInfo().createVirtualRegister(RC);
-      assert(isInt<16>(MFI.getMaxAlignment()) &&
+      assert((Log2(MFI.getMaxAlign()) < 16) &&
              "Function's alignment size requirement is not supported.");
-      int MaxAlign = -(int)MFI.getMaxAlignment();
+      int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value();
 
-      BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
+      BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign);
       BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
 
       if (hasBP(MF)) {
diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td
index 0c0ddeab22c49..568c85af655d5 100644
--- a/llvm/lib/Target/Mips/MipsSchedule.td
+++ b/llvm/lib/Target/Mips/MipsSchedule.td
@@ -27,6 +27,7 @@ def II_ADD              : InstrItinClass;
 def II_ADDU             : InstrItinClass;
 def II_ADD_D            : InstrItinClass;
 def II_ADD_S            : InstrItinClass;
+def II_ADDR_PS          : InstrItinClass;
 def II_ALIGN            : InstrItinClass;
 def II_AND              : InstrItinClass;
 def II_ANDI             : InstrItinClass;
@@ -278,6 +279,7 @@ def II_MUL              : InstrItinClass;
 def II_MUH              : InstrItinClass;
 def II_MUHU             : InstrItinClass;
 def II_MULU             : InstrItinClass;
+def II_MULR_PS          : InstrItinClass;
 def II_MULT             : InstrItinClass;
 def II_MULTU            : InstrItinClass;
 def II_MUL_D            : InstrItinClass;
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index faccb37c2361f..3888ca4e82f56 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -822,17 +822,19 @@ def : InstRW<[GenericWriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, FADD_D32,
 // madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw],
 // cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds,
 // trunc.w.[ds], trunc.w.ps,
-def : InstRW<[GenericWriteFPUL], (instrs CEIL_L_D64, CEIL_L_S, CEIL_W_D32,
+def : InstRW<[GenericWriteFPUL], (instrs ADDR_PS64,
+                                  CEIL_L_D64, CEIL_L_S, CEIL_W_D32,
                                   CEIL_W_D64, CEIL_W_S, CVT_D32_S, CVT_D32_W,
                                   CVT_D64_L, CVT_D64_S, CVT_D64_W, CVT_L_D64,
                                   CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L,
                                   CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S,
                                   CVT_PS_S64, CVT_S_PL64, CVT_S_PU64,
+                                  CVT_PS_PW64, CVT_PW_PS64,
                                   FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32,
                                   FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,
-                                  MADD_D32, MADD_D64, MSUB_D32, MSUB_D64,
+                                  MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, MULR_PS64,
                                   NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,
-                                  PLL_PS64, PLU_PS64,
+                                  PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64,
                                   ROUND_L_D64, ROUND_L_S, ROUND_W_D32,
                                   ROUND_W_D64, ROUND_W_S, TRUNC_L_D64,
                                   TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64,
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index 7331917baa256..872ff59f5041f 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -457,7 +457,9 @@ def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>;
 def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>;
 def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>;
 def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>;
-def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>;
+def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64)>;
+def : InstRW<[P5600WriteFPUL], (instrs ADDR_PS64, MULR_PS64)>;
+def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_PW64, CVT_PW_PS64)>;
 
 // div.[ds], div.ps
 def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 5a1dfec41a472..9303832e38a9f 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -149,6 +149,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
   // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
   bool HasDSP, HasDSPR2, HasDSPR3;
 
+  // Has3D -- Supports Mips3D ASE.
+  bool Has3D;
+
   // Allow mixed Mips16 and Mips32 in one source file
   bool AllowMixed16_32;
 
diff --git a/llvm/lib/Target/Mips/MipsTargetStreamer.h b/llvm/lib/Target/Mips/MipsTargetStreamer.h
index b389ba8938c4b..e383d749d1d11 100644
--- a/llvm/lib/Target/Mips/MipsTargetStreamer.h
+++ b/llvm/lib/Target/Mips/MipsTargetStreamer.h
@@ -84,6 +84,8 @@ class MipsTargetStreamer : public MCTargetStreamer {
   virtual void emitDirectiveSetDsp();
   virtual void emitDirectiveSetDspr2();
   virtual void emitDirectiveSetNoDsp();
+  virtual void emitDirectiveSetMips3D();
+  virtual void emitDirectiveSetNoMips3D();
   virtual void emitDirectiveSetPop();
   virtual void emitDirectiveSetPush();
   virtual void emitDirectiveSetSoftFloat();
@@ -263,6 +265,8 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer {
   void emitDirectiveSetDsp() override;
   void emitDirectiveSetDspr2() override;
   void emitDirectiveSetNoDsp() override;
+  void emitDirectiveSetMips3D() override;
+  void emitDirectiveSetNoMips3D() override;
   void emitDirectiveSetPop() override;
   void emitDirectiveSetPush() override;
   void emitDirectiveSetSoftFloat() override;
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index 76fe78ee0bfbd..6fcadfb5a1605 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -1634,8 +1634,8 @@ void NVPTXAsmPrinter::setAndEmitFunctionVirtualRegisters(
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   int NumBytes = (int) MFI.getStackSize();
   if (NumBytes) {
-    O << "\t.local .align " << MFI.getMaxAlignment() << " .b8 \t" << DEPOTNAME
-      << getFunctionNumber() << "[" << NumBytes << "];\n";
+    O << "\t.local .align " << MFI.getMaxAlign().value() << " .b8 \t"
+      << DEPOTNAME << getFunctionNumber() << "[" << NumBytes << "];\n";
     if (static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit()) {
       O << "\t.reg .b64 \t%SP;\n";
       O << "\t.reg .b64 \t%SPL;\n";
diff --git a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
index a7127b0e9a99d..0ace17619525c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
@@ -97,22 +97,21 @@ bool NVPTXPrologEpilogPass::runOnMachineFunction(MachineFunction &MF) {
 }
 
 /// AdjustStackOffset - Helper function used to adjust the stack frame offset.
-static inline void
-AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx,
-                  bool StackGrowsDown, int64_t &Offset,
-                  unsigned &MaxAlign) {
+static inline void AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx,
+                                     bool StackGrowsDown, int64_t &Offset,
+                                     Align &MaxAlign) {
   // If the stack grows down, add the object size to find the lowest address.
   if (StackGrowsDown)
     Offset += MFI.getObjectSize(FrameIdx);
 
-  unsigned Align = MFI.getObjectAlignment(FrameIdx);
+  Align Alignment = MFI.getObjectAlign(FrameIdx);
 
   // If the alignment of this object is greater than that of the stack, then
   // increase the stack alignment to match.
-  MaxAlign = std::max(MaxAlign, Align);
+  MaxAlign = std::max(MaxAlign, Alignment);
 
   // Adjust to alignment boundary.
-  Offset = (Offset + Align - 1) / Align * Align;
+  Offset = alignTo(Offset, Alignment);
 
   if (StackGrowsDown) {
     LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset
@@ -169,7 +168,7 @@ NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
 
   // NOTE: We do not have a call stack
 
-  unsigned MaxAlign = MFI.getMaxAlignment();
+  Align MaxAlign = MFI.getMaxAlign();
 
   // No scavenger
 
@@ -178,10 +177,10 @@ NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
   // frame index registers. Functions which don't want/need this optimization
   // will continue to use the existing code path.
   if (MFI.getUseLocalStackAllocationBlock()) {
-    unsigned Align = MFI.getLocalFrameMaxAlign().value();
+    Align Alignment = MFI.getLocalFrameMaxAlign();
 
     // Adjust to alignment boundary.
-    Offset = (Offset + Align - 1) / Align * Align;
+    Offset = alignTo(Offset, Alignment);
 
     LLVM_DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n");
 
@@ -196,7 +195,7 @@ NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
     // Allocate the local block
     Offset += MFI.getLocalFrameSize();
 
-    MaxAlign = std::max(Align, MaxAlign);
+    MaxAlign = std::max(Alignment, MaxAlign);
   }
 
   // No stack protector
@@ -227,18 +226,16 @@ NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
     // ensure that the callee's frame or the alloca data is suitably aligned;
     // otherwise, for leaf functions, align to the TransientStackAlignment
     // value.
-    unsigned StackAlign;
+    Align StackAlign;
     if (MFI.adjustsStack() || MFI.hasVarSizedObjects() ||
         (RegInfo->needsStackRealignment(Fn) && MFI.getObjectIndexEnd() != 0))
-      StackAlign = TFI.getStackAlignment();
+      StackAlign = TFI.getStackAlign();
     else
-      StackAlign = TFI.getTransientStackAlignment();
+      StackAlign = TFI.getTransientStackAlign();
 
     // If the frame pointer is eliminated, all frame offsets will be relative to
     // SP not FP. Align to MaxAlign so this works.
-    StackAlign = std::max(StackAlign, MaxAlign);
-    unsigned AlignMask = StackAlign - 1;
-    Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
+    Offset = alignTo(Offset, std::max(StackAlign, MaxAlign));
   }
 
   // Update frame info to pretend that this is part of the stack...
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 4b91ca8368db3..93695a854c246 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -437,9 +437,9 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
     UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
 
   // Get stack alignments. The frame must be aligned to the greatest of these:
-  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
-  unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
-  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
+  Align TargetAlign = getStackAlign(); // alignment required per the ABI
+  Align MaxAlign = MFI.getMaxAlign();  // algmt required by data in frame
+  Align Alignment = std::max(TargetAlign, MaxAlign);
 
   const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
 
@@ -471,7 +471,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
   // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
   // that allocations will be aligned.
   if (MFI.hasVarSizedObjects())
-    maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
+    maxCallFrameSize = alignTo(maxCallFrameSize, Alignment);
 
   // Update the new max call frame size if the caller passes in a valid pointer.
   if (NewMaxCallFrameSize)
@@ -481,7 +481,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
   FrameSize += maxCallFrameSize;
 
   // Make sure the frame is aligned.
-  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
+  FrameSize = alignTo(FrameSize, Alignment);
 
   return FrameSize;
 }
@@ -667,7 +667,7 @@ PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
   int NegFrameSize = -FrameSize;
   bool IsLargeFrame = !isInt<16>(NegFrameSize);
   MachineFrameInfo &MFI = MF.getFrameInfo();
-  unsigned MaxAlign = MFI.getMaxAlignment();
+  Align MaxAlign = MFI.getMaxAlign();
   bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
 
   return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
@@ -867,10 +867,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   }
 
   // Get stack alignments.
-  unsigned MaxAlign = MFI.getMaxAlignment();
+  Align MaxAlign = MFI.getMaxAlign();
   if (HasBP && MaxAlign > 1)
-    assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
-           "Invalid alignment!");
+    assert(Log2(MaxAlign) < 16 && "Invalid alignment!");
 
   // Frames of 32KB & larger require special handling because they cannot be
   // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
@@ -1007,15 +1006,15 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   if (HasBP && MaxAlign > 1) {
     if (isPPC64)
       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
-        .addReg(SPReg)
-        .addImm(0)
-        .addImm(64 - Log2_32(MaxAlign));
+          .addReg(SPReg)
+          .addImm(0)
+          .addImm(64 - Log2(MaxAlign));
     else // PPC32...
       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
-        .addReg(SPReg)
-        .addImm(0)
-        .addImm(32 - Log2_32(MaxAlign))
-        .addImm(31);
+          .addReg(SPReg)
+          .addImm(0)
+          .addImm(32 - Log2(MaxAlign))
+          .addImm(31);
     if (!isLargeFrame) {
       BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
         .addReg(ScratchReg, RegState::Kill)
@@ -2058,8 +2057,8 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
     RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
 
     // Might we have over-aligned allocas?
-    bool HasAlVars = MFI.hasVarSizedObjects() &&
-                     MFI.getMaxAlignment() > getStackAlignment();
+    bool HasAlVars =
+        MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign();
 
     // These kinds of spills might need two registers.
     if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8ac965d614bac..2d718011059ab 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6841,9 +6841,6 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
   if (ValVT == MVT::f128)
     report_fatal_error("f128 is unimplemented on AIX.");
 
-  if (ArgFlags.isByVal())
-    report_fatal_error("Passing structure by value is unimplemented.");
-
   if (ArgFlags.isNest())
     report_fatal_error("Nest arguments are unimplemented.");
 
@@ -6857,6 +6854,29 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
                                      PPC::X3, PPC::X4, PPC::X5, PPC::X6,
                                      PPC::X7, PPC::X8, PPC::X9, PPC::X10};
 
+  if (ArgFlags.isByVal()) {
+    if (ArgFlags.getNonZeroByValAlign() > PtrByteSize)
+      report_fatal_error("Pass-by-value arguments with alignment greater than "
+                         "register width are not supported.");
+
+    const unsigned ByValSize = ArgFlags.getByValSize();
+
+    // An empty aggregate parameter takes up no storage and no registers.
+    if (ByValSize == 0)
+      return false;
+
+    if (ByValSize <= PtrByteSize) {
+      State.AllocateStack(PtrByteSize, PtrByteSize);
+      if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) {
+        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
+        return false;
+      }
+    }
+
+    report_fatal_error(
+        "Pass-by-value arguments are only supported in a single register.");
+  }
+
   // Arguments always reserve parameter save area.
   switch (ValVT.SimpleTy) {
   default:
@@ -7130,9 +7150,59 @@ SDValue PPCTargetLowering::LowerCall_AIX(
     CCValAssign &VA = ArgLocs[I++];
 
     SDValue Arg = OutVals[VA.getValNo()];
+    ISD::ArgFlagsTy Flags = Outs[VA.getValNo()].Flags;
+    const MVT LocVT = VA.getLocVT();
+    const MVT ValVT = VA.getValVT();
+
+    if (Flags.isByVal()) {
+      const unsigned ByValSize = Flags.getByValSize();
+      assert(
+          VA.isRegLoc() && ByValSize > 0 && ByValSize <= PtrByteSize &&
+          "Pass-by-value arguments are only supported in a single register.");
+
+      // Loads must be a power-of-2 size and cannot be larger than the
+      // ByValSize. For example: a 7 byte by-val arg requires 4, 2 and 1 byte
+      // loads.
+      SDValue RegVal;
+      for (unsigned Bytes = 0; Bytes != ByValSize;) {
+        unsigned N = PowerOf2Floor(ByValSize - Bytes);
+        const MVT VT =
+            N == 1 ? MVT::i8
+                   : ((N == 2) ? MVT::i16 : (N == 4 ? MVT::i32 : MVT::i64));
+
+        SDValue LoadAddr = Arg;
+        if (Bytes != 0) {
+          // Adjust the load offset by the number of bytes read so far.
+          SDNodeFlags Flags;
+          Flags.setNoUnsignedWrap(true);
+          LoadAddr = DAG.getNode(ISD::ADD, dl, LocVT, Arg,
+                                 DAG.getConstant(Bytes, dl, LocVT), Flags);
+        }
+        SDValue Load = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, LoadAddr,
+                                      MachinePointerInfo(), VT);
+        MemOpChains.push_back(Load.getValue(1));
+
+        Bytes += N;
+        assert(LocVT.getSizeInBits() >= (Bytes * 8));
+        if (unsigned NumSHLBits = LocVT.getSizeInBits() - (Bytes * 8)) {
+          // By-val arguments are passed left-justfied in register.
+          EVT ShiftAmountTy =
+              getShiftAmountTy(Load->getValueType(0), DAG.getDataLayout());
+          SDValue SHLAmt = DAG.getConstant(NumSHLBits, dl, ShiftAmountTy);
+          SDValue ShiftedLoad =
+              DAG.getNode(ISD::SHL, dl, Load.getValueType(), Load, SHLAmt);
+          RegVal = RegVal ? DAG.getNode(ISD::OR, dl, LocVT, RegVal, ShiftedLoad)
+                          : ShiftedLoad;
+        } else {
+          assert(!RegVal && Bytes == ByValSize &&
+                 "Pass-by-value argument handling unexpectedly incomplete.");
+          RegVal = Load;
+        }
+      }
 
-    if (!VA.isRegLoc() && !VA.isMemLoc())
-      report_fatal_error("Unexpected location for function call argument.");
+      RegsToPass.push_back(std::make_pair(VA.getLocReg(), RegVal));
+      continue;
+    }
 
     switch (VA.getLocInfo()) {
     default:
@@ -7165,20 +7235,20 @@ SDValue PPCTargetLowering::LowerCall_AIX(
     // Custom handling is used for GPR initializations for vararg float
     // arguments.
     assert(VA.isRegLoc() && VA.needsCustom() && CFlags.IsVarArg &&
-           VA.getValVT().isFloatingPoint() && VA.getLocVT().isInteger() &&
+           ValVT.isFloatingPoint() && LocVT.isInteger() &&
            "Unexpected register handling for calling convention.");
 
     SDValue ArgAsInt =
-        DAG.getBitcast(MVT::getIntegerVT(VA.getValVT().getSizeInBits()), Arg);
+        DAG.getBitcast(MVT::getIntegerVT(ValVT.getSizeInBits()), Arg);
 
-    if (Arg.getValueType().getStoreSize() == VA.getLocVT().getStoreSize())
+    if (Arg.getValueType().getStoreSize() == LocVT.getStoreSize())
       // f32 in 32-bit GPR
       // f64 in 64-bit GPR
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgAsInt));
-    else if (Arg.getValueType().getSizeInBits() < VA.getLocVT().getSizeInBits())
+    else if (Arg.getValueType().getSizeInBits() < LocVT.getSizeInBits())
       // f32 in 64-bit GPR.
       RegsToPass.push_back(std::make_pair(
-          VA.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, VA.getLocVT())));
+          VA.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, LocVT)));
     else {
       // f64 in two 32-bit GPRs
       // The 2 GPRs are marked custom and expected to be adjacent in ArgLocs.
@@ -7592,15 +7662,6 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
       !Op.getOperand(2).getValueType().isFloatingPoint())
     return Op;
 
-  bool HasNoInfs = DAG.getTarget().Options.NoInfsFPMath;
-  bool HasNoNaNs = DAG.getTarget().Options.NoNaNsFPMath;
-  // We might be able to do better than this under some circumstances, but in
-  // general, fsel-based lowering of select is a finite-math-only optimization.
-  // For more information, see section F.3 of the 2.06 ISA specification.
-  // With ISA 3.0, we have xsmaxcdp/xsmincdp which are OK to emit even in the
-  // presence of infinities.
-  if (!Subtarget.hasP9Vector() && (!HasNoInfs || !HasNoNaNs))
-    return Op;
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
 
   EVT ResVT = Op.getValueType();
@@ -7609,13 +7670,12 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
   SDValue TV  = Op.getOperand(2), FV  = Op.getOperand(3);
   SDLoc dl(Op);
 
+  // We have xsmaxcdp/xsmincdp which are OK to emit even in the
+  // presence of infinities.
   if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) {
     switch (CC) {
     default:
-      // Not a min/max but with finite math, we may still be able to use fsel.
-      if (HasNoInfs && HasNoNaNs)
-        break;
-      return Op;
+      break;
     case ISD::SETOGT:
     case ISD::SETGT:
       return DAG.getNode(PPCISD::XSMAXCDP, dl, Op.getValueType(), LHS, RHS);
@@ -7623,7 +7683,14 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
     case ISD::SETLT:
       return DAG.getNode(PPCISD::XSMINCDP, dl, Op.getValueType(), LHS, RHS);
     }
-  } else if (!HasNoInfs || !HasNoNaNs)
+  }
+
+  // We might be able to do better than this under some circumstances, but in
+  // general, fsel-based lowering of select is a finite-math-only optimization.
+  // For more information, see section F.3 of the 2.06 ISA specification.
+  // With ISA 3.0
+  if (!DAG.getTarget().Options.NoInfsFPMath ||
+      !DAG.getTarget().Options.NoNaNsFPMath)
     return Op;
 
   // TODO: Propagate flags from the select rather than global settings.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 1b3c52b4edf0c..f7a68dd162297 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2879,7 +2879,7 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
     APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
                 SExtImm, true);
     InVal = InVal.rotl(SH);
-    uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
+    uint64_t Mask = MB == 0 ? -1LLU : (1LLU << (63 - MB + 1)) - 1;
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use
diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
index bde3f5918a239..815dfd1402f47 100644
--- a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
@@ -113,7 +113,7 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
     if (!SI.isImm())
       return true;
     int64_t Imm = SI.getImm();
-    if (((Imm & 0xFFF0) != 0) || ((Imm & 0xFFF0) != 0xFFF0)) 
+    if (((Imm & 0xFFF0) != 0) && ((Imm & 0xFFF0) != 0xFFF0))
       return false;
 
     // If si = 1111111111110000 and the msb of the d/ds field of the load equals 
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index caa9d7b6b8697..35d3c420c3c3e 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -499,7 +499,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
   // Get stack alignments.
   const PPCFrameLowering *TFI = getFrameLowering(MF);
   unsigned TargetAlign = TFI->getStackAlignment();
-  unsigned MaxAlign = MFI.getMaxAlignment();
+  unsigned MaxAlign = MFI.getMaxAlign().value();
   assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
          "Maximum call-frame size not sufficiently aligned");
 
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 072f0d902cc34..927e8534ece87 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -142,10 +142,10 @@ void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
   uint64_t FrameSize = MFI.getStackSize();
 
   // Get the alignment.
-  unsigned StackAlign = getStackAlignment();
+  Align StackAlign = getStackAlign();
   if (RI->needsStackRealignment(MF)) {
-    unsigned MaxStackAlign = std::max(StackAlign, MFI.getMaxAlignment());
-    FrameSize += (MaxStackAlign - StackAlign);
+    Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
+    FrameSize += (MaxStackAlign.value() - StackAlign.value());
     StackAlign = MaxStackAlign;
   }
 
@@ -359,15 +359,15 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
     // Realign Stack
     const RISCVRegisterInfo *RI = STI.getRegisterInfo();
     if (RI->needsStackRealignment(MF)) {
-      unsigned MaxAlignment = MFI.getMaxAlignment();
+      Align MaxAlignment = MFI.getMaxAlign();
 
       const RISCVInstrInfo *TII = STI.getInstrInfo();
-      if (isInt<12>(-(int)MaxAlignment)) {
+      if (isInt<12>(-(int)MaxAlignment.value())) {
         BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
             .addReg(SPReg)
-            .addImm(-(int)MaxAlignment);
+            .addImm(-(int)MaxAlignment.value());
       } else {
-        unsigned ShiftAmount = countTrailingZeros(MaxAlignment);
+        unsigned ShiftAmount = Log2(MaxAlignment);
         Register VR =
             MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
index bd3b95a98b9f7..9db3107da0733 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
@@ -22,5 +22,5 @@
 
 using namespace llvm;
 
-RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI)
-    : RISCVGenRegisterBankInfo() {}
+RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
+    : RISCVGenRegisterBankInfo(HwMode) {}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
index 05fac992734d9..71dddd28380de 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
@@ -31,7 +31,7 @@ class RISCVGenRegisterBankInfo : public RegisterBankInfo {
 /// This class provides the information for the target register banks.
 class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
 public:
-  RISCVRegisterBankInfo(const TargetRegisterInfo &TRI);
+  RISCVRegisterBankInfo(unsigned HwMode);
 };
 } // end namespace llvm
 #endif
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 47a48c820a290..9815a78526890 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -56,7 +56,7 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
-  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
+  auto *RBI = new RISCVRegisterBankInfo(getHwMode());
   RegBankInfo.reset(RBI);
   InstSelector.reset(createRISCVInstructionSelector(
       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
index 0f74f2bb344c4..6bb3a51df0c3f 100644
--- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
@@ -104,7 +104,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
   // rather than reporting an error, as would be sensible. This is
   // poor, but fixing that bogosity is going to be a large project.
   // For now, just see if it's lied, and report an error here.
-  if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())
+  if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign())
     report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
                        "stack re-alignment, but LLVM couldn't handle it "
                        "(probably because it has a dynamic alloca).");
@@ -146,9 +146,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
 
   // Finally, ensure that the size is sufficiently aligned for the
   // data on the stack.
-  if (MFI.getMaxAlignment() > 0) {
-    NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
-  }
+  NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
 
   // Update stack size with corrected value.
   MFI.setStackSize(NumBytes);
@@ -189,9 +187,10 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF,
       regUnbiased = SP::O6;
 
     // andn %regUnbiased, MaxAlign-1, %regUnbiased
-    int MaxAlign = MFI.getMaxAlignment();
+    Align MaxAlign = MFI.getMaxAlign();
     BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
-      .addReg(regUnbiased).addImm(MaxAlign - 1);
+        .addReg(regUnbiased)
+        .addImm(MaxAlign.value() - 1U);
 
     if (Bias) {
       // add %g1, -BIAS, %o6
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index ddced5a421033..66da118dd8250 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -641,6 +641,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
   setTargetDAGCombine(ISD::FP_ROUND);
   setTargetDAGCombine(ISD::STRICT_FP_ROUND);
   setTargetDAGCombine(ISD::FP_EXTEND);
+  setTargetDAGCombine(ISD::SINT_TO_FP);
+  setTargetDAGCombine(ISD::UINT_TO_FP);
   setTargetDAGCombine(ISD::STRICT_FP_EXTEND);
   setTargetDAGCombine(ISD::BSWAP);
   setTargetDAGCombine(ISD::SDIV);
@@ -6081,6 +6083,32 @@ SDValue SystemZTargetLowering::combineFP_EXTEND(
   return SDValue();
 }
 
+SDValue SystemZTargetLowering::combineINT_TO_FP(
+    SDNode *N, DAGCombinerInfo &DCI) const {
+  if (DCI.Level != BeforeLegalizeTypes)
+    return SDValue();
+  unsigned Opcode = N->getOpcode();
+  EVT OutVT = N->getValueType(0);
+  SelectionDAG &DAG = DCI.DAG;
+  SDValue Op = N->getOperand(0);
+  unsigned OutScalarBits = OutVT.getScalarSizeInBits();
+  unsigned InScalarBits = Op->getValueType(0).getScalarSizeInBits();
+
+  // Insert an extension before type-legalization to avoid scalarization, e.g.:
+  // v2f64 = uint_to_fp v2i16
+  // =>
+  // v2f64 = uint_to_fp (v2i64 zero_extend v2i16)
+  if (OutVT.isVector() && OutScalarBits > InScalarBits) {
+    MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(OutVT.getScalarSizeInBits()),
+                                 OutVT.getVectorNumElements());
+    unsigned ExtOpcode =
+      (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND);
+    SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op);
+    return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp);
+  }
+  return SDValue();
+}
+
 SDValue SystemZTargetLowering::combineBSWAP(
     SDNode *N, DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
@@ -6408,6 +6436,8 @@ SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::FP_ROUND:           return combineFP_ROUND(N, DCI);
   case ISD::STRICT_FP_EXTEND:
   case ISD::FP_EXTEND:          return combineFP_EXTEND(N, DCI);
+  case ISD::SINT_TO_FP:
+  case ISD::UINT_TO_FP:         return combineINT_TO_FP(N, DCI);
   case ISD::BSWAP:              return combineBSWAP(N, DCI);
   case SystemZISD::BR_CCMASK:   return combineBR_CCMASK(N, DCI);
   case SystemZISD::SELECT_CCMASK: return combineSELECT_CCMASK(N, DCI);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 739377ed0f952..f482b7baa19f2 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -642,6 +642,7 @@ class SystemZTargetLowering : public TargetLowering {
   SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
+  SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
diff --git a/llvm/lib/Target/TargetLoweringObjectFile.cpp b/llvm/lib/Target/TargetLoweringObjectFile.cpp
index cfdb67537f0e2..9f464c0201eb6 100644
--- a/llvm/lib/Target/TargetLoweringObjectFile.cpp
+++ b/llvm/lib/Target/TargetLoweringObjectFile.cpp
@@ -149,6 +149,10 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalObject *GO,
   if (isa<Function>(GO))
     return SectionKind::getText();
 
+  // Basic blocks are classified as text sections.
+  if (isa<BasicBlock>(GO))
+    return SectionKind::getText();
+
   // Global variables require more detailed analysis.
   const auto *GVar = cast<GlobalVariable>(GO);
 
@@ -302,6 +306,18 @@ MCSection *TargetLoweringObjectFile::getSectionForConstant(
   return DataSection;
 }
 
+MCSection *TargetLoweringObjectFile::getSectionForMachineBasicBlock(
+    const Function &F, const MachineBasicBlock &MBB,
+    const TargetMachine &TM) const {
+  return nullptr;
+}
+
+MCSection *TargetLoweringObjectFile::getNamedSectionForMachineBasicBlock(
+    const Function &F, const MachineBasicBlock &MBB, const TargetMachine &TM,
+    const char *Suffix) const {
+  return nullptr;
+}
+
 /// getTTypeGlobalReference - Return an MCExpr to use for a
 /// reference to the specified global variable from exception
 /// handling information.
diff --git a/llvm/lib/Target/VE/CMakeLists.txt b/llvm/lib/Target/VE/CMakeLists.txt
index 5b32fd50e5834..89c946d87e198 100644
--- a/llvm/lib/Target/VE/CMakeLists.txt
+++ b/llvm/lib/Target/VE/CMakeLists.txt
@@ -21,6 +21,5 @@ add_llvm_target(VECodeGen
   VETargetMachine.cpp
   )
 
-add_subdirectory(InstPrinter)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
diff --git a/llvm/lib/Target/VE/InstPrinter/CMakeLists.txt b/llvm/lib/Target/VE/InstPrinter/CMakeLists.txt
deleted file mode 100644
index 7ddeebb9a7df6..0000000000000
--- a/llvm/lib/Target/VE/InstPrinter/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-add_llvm_component_library(LLVMVEAsmPrinter
-  VEInstPrinter.cpp
-  )
diff --git a/llvm/lib/Target/VE/InstPrinter/LLVMBuild.txt b/llvm/lib/Target/VE/InstPrinter/LLVMBuild.txt
deleted file mode 100644
index 8cfaea7634e65..0000000000000
--- a/llvm/lib/Target/VE/InstPrinter/LLVMBuild.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-;===- ./lib/Target/VE/InstPrinter/LLVMBuild.txt ----------------*- Conf -*--===;
-;
-; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-; See https://llvm.org/LICENSE.txt for license information.
-; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-;   http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = VEAsmPrinter
-parent = VE
-required_libraries = MC Support
-add_to_library_groups = VE
diff --git a/llvm/lib/Target/VE/LLVMBuild.txt b/llvm/lib/Target/VE/LLVMBuild.txt
index 4e1a5ed898ca2..eb74a9a387b02 100644
--- a/llvm/lib/Target/VE/LLVMBuild.txt
+++ b/llvm/lib/Target/VE/LLVMBuild.txt
@@ -15,7 +15,7 @@
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = InstPrinter MCTargetDesc TargetInfo
+subdirectories = MCTargetDesc TargetInfo
 
 [component_0]
 type = TargetGroup
@@ -29,6 +29,5 @@ type = Library
 name = VECodeGen
 parent = VE
 required_libraries = Analysis AsmPrinter CodeGen Core
-                     MC SelectionDAG VEAsmPrinter
-                     VEDesc VEInfo Support Target
+                     MC SelectionDAG VEDesc VEInfo Support Target
 add_to_library_groups = VE
diff --git a/llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt
index 5ef74c18461cb..9bca0ceeb69bf 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt
@@ -1,4 +1,5 @@
 add_llvm_component_library(LLVMVEDesc
+  VEInstPrinter.cpp
   VEMCAsmInfo.cpp
   VEMCExpr.cpp
   VEMCTargetDesc.cpp
diff --git a/llvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt b/llvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt
index 3fddd5268bee6..e585042e60bba 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt
+++ b/llvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt
@@ -18,5 +18,5 @@
 type = Library
 name = VEDesc
 parent = VE
-required_libraries = MC VEAsmPrinter VEInfo Support
+required_libraries = MC VEInfo Support
 add_to_library_groups = VE
diff --git a/llvm/lib/Target/VE/InstPrinter/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
similarity index 100%
rename from llvm/lib/Target/VE/InstPrinter/VEInstPrinter.cpp
rename to llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
diff --git a/llvm/lib/Target/VE/InstPrinter/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
similarity index 100%
rename from llvm/lib/Target/VE/InstPrinter/VEInstPrinter.h
rename to llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
index b228617058a6a..3cd09299fc70f 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
@@ -11,7 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "VEMCTargetDesc.h"
-#include "InstPrinter/VEInstPrinter.h"
+#include "VEInstPrinter.h"
 #include "VEMCAsmInfo.h"
 #include "VETargetStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.cpp b/llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.cpp
index dfe94bbaaa4bf..29f5afb67ac14 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.cpp
@@ -11,7 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "VETargetStreamer.h"
-#include "InstPrinter/VEInstPrinter.h"
+#include "VEInstPrinter.h"
 #include "llvm/Support/FormattedStream.h"
 
 using namespace llvm;
diff --git a/llvm/lib/Target/VE/VEAsmPrinter.cpp b/llvm/lib/Target/VE/VEAsmPrinter.cpp
index 99bbe441608d3..19a01f4f07498 100644
--- a/llvm/lib/Target/VE/VEAsmPrinter.cpp
+++ b/llvm/lib/Target/VE/VEAsmPrinter.cpp
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "InstPrinter/VEInstPrinter.h"
+#include "MCTargetDesc/VEInstPrinter.h"
 #include "MCTargetDesc/VEMCExpr.h"
 #include "MCTargetDesc/VETargetStreamer.h"
 #include "VE.h"
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
index 21b81d8cd0edc..036c2aee00508 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
@@ -201,11 +201,9 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF,
   }
   if (HasBP) {
     Register BitmaskReg = MRI.createVirtualRegister(PtrRC);
-    unsigned Alignment = MFI.getMaxAlignment();
-    assert((1u << countTrailingZeros(Alignment)) == Alignment &&
-           "Alignment must be a power of 2");
+    Align Alignment = MFI.getMaxAlign();
     BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), BitmaskReg)
-        .addImm((int)~(Alignment - 1));
+        .addImm((int)~(Alignment.value() - 1));
     BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::AND_I32),
             WebAssembly::SP32)
         .addReg(WebAssembly::SP32)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index b4a86ea65fa3c..e3d8b7715f5a4 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -105,6 +105,10 @@ cl::opt<bool> X86AlignBranchWithin32BBoundaries(
         "assumptions about labels corresponding to particular instructions, "
         "and should be used with caution."));
 
+cl::opt<unsigned> X86PadMaxPrefixSize(
+    "x86-pad-max-prefix-size", cl::init(0),
+    cl::desc("Maximum number of prefixes to use for padding"));
+
 cl::opt<bool> X86PadForAlign(
     "x86-pad-for-align", cl::init(true), cl::Hidden,
     cl::desc("Pad previous instructions to implement align directives"));
@@ -134,6 +138,7 @@ class X86AsmBackend : public MCAsmBackend {
   bool needAlignInst(const MCInst &Inst) const;
   MCInst PrevInst;
   MCBoundaryAlignFragment *PendingBoundaryAlign = nullptr;
+  std::pair<MCFragment *, size_t> PrevInstPosition;
 
 public:
   X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
@@ -157,8 +162,8 @@ class X86AsmBackend : public MCAsmBackend {
   }
 
   bool allowAutoPadding() const override;
-  void alignBranchesBegin(MCObjectStreamer &OS, const MCInst &Inst) override;
-  void alignBranchesEnd(MCObjectStreamer &OS, const MCInst &Inst) override;
+  void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst) override;
+  void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst) override;
 
   unsigned getNumFixupKinds() const override {
     return X86::NumTargetFixupKinds;
@@ -167,7 +172,7 @@ class X86AsmBackend : public MCAsmBackend {
   Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
-  
+
   bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                              const MCValue &Target) override;
 
@@ -186,8 +191,16 @@ class X86AsmBackend : public MCAsmBackend {
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
+  bool padInstructionViaRelaxation(MCRelaxableFragment &RF,
+                                   MCCodeEmitter &Emitter,
+                                   unsigned &RemainingSize) const;
+
+  bool padInstructionViaPrefix(MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
+                               unsigned &RemainingSize) const;
+
   bool padInstructionEncoding(MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
                               unsigned &RemainingSize) const;
+
   void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const override;
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
@@ -479,6 +492,52 @@ static bool hasInterruptDelaySlot(const MCInst &Inst) {
   return false;
 }
 
+/// Check if the instruction to be emitted is right after any data.
+static bool
+isRightAfterData(MCFragment *CurrentFragment,
+                 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
+  MCFragment *F = CurrentFragment;
+  // Empty data fragments may be created to prevent further data being
+  // added into the previous fragment, we need to skip them since they
+  // have no contents.
+  for (; isa_and_nonnull<MCDataFragment>(F); F = F->getPrevNode())
+    if (cast<MCDataFragment>(F)->getContents().size() != 0)
+      break;
+
+  // Since data is always emitted into a DataFragment, our check strategy is
+  // simple here.
+  //   - If the fragment is a DataFragment
+  //     - If it's not the fragment where the previous instruction is,
+  //       returns true.
+  //     - If it's the fragment holding the previous instruction but its
+  //       size changed since the the previous instruction was emitted into
+  //       it, returns true.
+  //     - Otherwise returns false.
+  //   - If the fragment is not a DataFragment, returns false.
+  if (auto *DF = dyn_cast_or_null<MCDataFragment>(F))
+    return DF != PrevInstPosition.first ||
+           DF->getContents().size() != PrevInstPosition.second;
+
+  return false;
+}
+
+/// \returns the fragment size if it has instructions, otherwise returns 0.
+static size_t getSizeForInstFragment(const MCFragment *F) {
+  if (!F || !F->hasInstructions())
+    return 0;
+  // MCEncodedFragmentWithContents being templated makes this tricky.
+  switch (F->getKind()) {
+  default:
+    llvm_unreachable("Unknown fragment with instructions!");
+  case MCFragment::FT_Data:
+    return cast<MCDataFragment>(*F).getContents().size();
+  case MCFragment::FT_Relaxable:
+    return cast<MCRelaxableFragment>(*F).getContents().size();
+  case MCFragment::FT_CompactEncodedInst:
+    return cast<MCCompactEncodedInstFragment>(*F).getContents().size();
+  }
+}
+
 /// Check if the instruction operand needs to be aligned. Padding is disabled
 /// before intruction which may be rewritten by linker(e.g. TLSCALL).
 bool X86AsmBackend::needAlignInst(const MCInst &Inst) const {
@@ -500,7 +559,7 @@ bool X86AsmBackend::needAlignInst(const MCInst &Inst) const {
 }
 
 /// Insert BoundaryAlignFragment before instructions to align branches.
-void X86AsmBackend::alignBranchesBegin(MCObjectStreamer &OS,
+void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
                                        const MCInst &Inst) {
   if (!needAlign(OS))
     return;
@@ -515,6 +574,11 @@ void X86AsmBackend::alignBranchesBegin(MCObjectStreamer &OS,
     // semantic.
     return;
 
+  if (isRightAfterData(OS.getCurrentFragment(), PrevInstPosition))
+    // If this instruction follows any data, there is no clear
+    // instruction boundary, inserting a nop would change semantic.
+    return;
+
   if (!isMacroFused(PrevInst, Inst))
     // Macro fusion doesn't happen indeed, clear the pending.
     PendingBoundaryAlign = nullptr;
@@ -526,7 +590,7 @@ void X86AsmBackend::alignBranchesBegin(MCObjectStreamer &OS,
     //
     // Do nothing here since we already inserted a BoudaryAlign fragment when
     // we met the first instruction in the fused pair and we'll tie them
-    // together in alignBranchesEnd.
+    // together in emitInstructionEnd.
     //
     // Note: When there is at least one fragment, such as MCAlignFragment,
     // inserted after the previous instruction, e.g.
@@ -552,24 +616,26 @@ void X86AsmBackend::alignBranchesBegin(MCObjectStreamer &OS,
 }
 
 /// Set the last fragment to be aligned for the BoundaryAlignFragment.
-void X86AsmBackend::alignBranchesEnd(MCObjectStreamer &OS, const MCInst &Inst) {
+void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst) {
   if (!needAlign(OS))
     return;
 
   PrevInst = Inst;
+  MCFragment *CF = OS.getCurrentFragment();
+  PrevInstPosition = std::make_pair(CF, getSizeForInstFragment(CF));
 
   if (!needAlignInst(Inst) || !PendingBoundaryAlign)
     return;
 
   // Tie the aligned instructions into a a pending BoundaryAlign.
-  PendingBoundaryAlign->setLastFragment(OS.getCurrentFragment());
+  PendingBoundaryAlign->setLastFragment(CF);
   PendingBoundaryAlign = nullptr;
 
   // We need to ensure that further data isn't added to the current
   // DataFragment, so that we can get the size of instructions later in
   // MCAssembler::relaxBoundaryAlign. The easiest way is to insert a new empty
   // DataFragment.
-  if (isa_and_nonnull<MCDataFragment>(OS.getCurrentFragment()))
+  if (isa_and_nonnull<MCDataFragment>(CF))
     OS.insert(new MCDataFragment());
 
   // Update the maximum alignment on the current section if necessary.
@@ -734,19 +800,86 @@ void X86AsmBackend::relaxInstruction(const MCInst &Inst,
   Res.setOpcode(RelaxedOp);
 }
 
-static bool canBeRelaxedForPadding(const MCRelaxableFragment &RF) {
-  // TODO: There are lots of other tricks we could apply for increasing
-  // encoding size without impacting performance.
+/// Return true if this instruction has been fully relaxed into it's most
+/// general available form.
+static bool isFullyRelaxed(const MCRelaxableFragment &RF) {
   auto &Inst = RF.getInst();
   auto &STI = *RF.getSubtargetInfo();
   bool Is16BitMode = STI.getFeatureBits()[X86::Mode16Bit];
-  return getRelaxedOpcode(Inst, Is16BitMode) != Inst.getOpcode();
+  return getRelaxedOpcode(Inst, Is16BitMode) == Inst.getOpcode();
 }
 
-bool X86AsmBackend::padInstructionEncoding(MCRelaxableFragment &RF,
-                                           MCCodeEmitter &Emitter,
-                                           unsigned &RemainingSize) const {
-  if (!canBeRelaxedForPadding(RF))
+
+static bool shouldAddPrefix(const MCInst &Inst, const MCInstrInfo &MCII) {
+  // Linker may rewrite the instruction with variant symbol operand.
+  return !hasVariantSymbol(Inst);
+}
+
+static unsigned getRemainingPrefixSize(const MCInst &Inst,
+                                       const MCSubtargetInfo &STI,
+                                       MCCodeEmitter &Emitter) {
+  SmallString<256> Code;
+  raw_svector_ostream VecOS(Code);
+  Emitter.emitPrefix(Inst, VecOS, STI);
+  assert(Code.size() < 15 && "The number of prefixes must be less than 15.");
+
+  // TODO: It turns out we need a decent amount of plumbing for the target
+  // specific bits to determine number of prefixes its safe to add.  Various
+  // targets (older chips mostly, but also Atom family) encounter decoder
+  // stalls with too many prefixes.  For testing purposes, we set the value
+  // externally for the moment.
+  unsigned ExistingPrefixSize = Code.size();
+  unsigned TargetPrefixMax = X86PadMaxPrefixSize;
+  if (TargetPrefixMax <= ExistingPrefixSize)
+    return 0;
+  return TargetPrefixMax - ExistingPrefixSize;
+}
+
+bool X86AsmBackend::padInstructionViaPrefix(MCRelaxableFragment &RF,
+                                            MCCodeEmitter &Emitter,
+                                            unsigned &RemainingSize) const {
+  if (!shouldAddPrefix(RF.getInst(), *MCII))
+    return false;
+  // If the instruction isn't fully relaxed, shifting it around might require a
+  // larger value for one of the fixups then can be encoded.  The outer loop
+  // will also catch this before moving to the next instruction, but we need to
+  // prevent padding this single instruction as well.
+  if (!isFullyRelaxed(RF))
+    return false;
+
+  const unsigned OldSize = RF.getContents().size();
+  if (OldSize == 15)
+    return false;
+
+  const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
+  const unsigned PrefixBytesToAdd =
+    std::min(MaxPossiblePad,
+             getRemainingPrefixSize(RF.getInst(), STI, Emitter));
+  if (PrefixBytesToAdd == 0)
+    return false;
+
+  const uint8_t Prefix = determinePaddingPrefix(RF.getInst());
+
+  SmallString<256> Code;
+  Code.append(PrefixBytesToAdd, Prefix);
+  Code.append(RF.getContents().begin(), RF.getContents().end());
+  RF.getContents() = Code;
+
+  // Adjust the fixups for the change in offsets
+  for (auto &F : RF.getFixups()) {
+    F.setOffset(F.getOffset() + PrefixBytesToAdd);
+  }
+
+  RemainingSize -= PrefixBytesToAdd;
+  return true;
+}
+
+bool X86AsmBackend::padInstructionViaRelaxation(MCRelaxableFragment &RF,
+                                                MCCodeEmitter &Emitter,
+                                                unsigned &RemainingSize) const {
+  if (isFullyRelaxed(RF))
+    // TODO: There are lots of other tricks we could apply for increasing
+    // encoding size without impacting performance.
     return false;
 
   MCInst Relaxed;
@@ -769,6 +902,17 @@ bool X86AsmBackend::padInstructionEncoding(MCRelaxableFragment &RF,
   return true;
 }
 
+bool X86AsmBackend::padInstructionEncoding(MCRelaxableFragment &RF,
+                                           MCCodeEmitter &Emitter,
+                                           unsigned &RemainingSize) const {
+  bool Changed = false;
+  if (RemainingSize != 0)
+    Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);
+  if (RemainingSize != 0)
+    Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);
+  return Changed;
+}
+
 void X86AsmBackend::finishLayout(MCAssembler const &Asm,
                                  MCAsmLayout &Layout) const {
   // See if we can further relax some instructions to cut down on the number of
@@ -851,7 +995,7 @@ void X86AsmBackend::finishLayout(MCAssembler const &Asm,
         // We don't need to worry about larger positive offsets as none of the
         // possible offsets between this and our align are visible, and the
         // ones afterwards aren't changing.
-        if (mayNeedRelaxation(RF.getInst(), *RF.getSubtargetInfo()))
+        if (!isFullyRelaxed(RF))
           break;
       }
       Relaxable.clear();
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 027e2c2d45afb..c25785b9000dd 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -3289,7 +3289,8 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
       ResultReg =
         fastEmit_ri(VT, VT, ISD::AND, ResultReg, hasTrivialKill(PrevVal), 1);
     } else {
-      if (!isTypeLegal(Val->getType(), VT))
+      if (!isTypeLegal(Val->getType(), VT) ||
+          (VT.isVector() && VT.getVectorElementType() == MVT::i1))
         return false;
       ResultReg = getRegForValue(Val);
     }
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index bc88401797c9d..1661497849d15 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -1042,15 +1042,15 @@ static unsigned calculateSetFPREG(uint64_t SPAdjust) {
 // go with the minimum SlotSize.
 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
-  uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
-  unsigned StackAlign = getStackAlignment();
+  Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.
+  Align StackAlign = getStackAlign();
   if (MF.getFunction().hasFnAttribute("stackrealign")) {
     if (MFI.hasCalls())
       MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
     else if (MaxAlign < SlotSize)
-      MaxAlign = SlotSize;
+      MaxAlign = Align(SlotSize);
   }
-  return MaxAlign;
+  return MaxAlign.value();
 }
 
 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
@@ -3009,12 +3009,6 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
   I = MBB.erase(I);
   auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
 
-  // Try to avoid emitting dead SP adjustments if the block end is unreachable,
-  // typically because the function is marked noreturn (abort, throw,
-  // assert_fail, etc).
-  if (isDestroy && blockEndIsUnreachable(MBB, I))
-    return I;
-
   if (!reserveCallFrame) {
     // If the stack pointer can be changed after prologue, turn the
     // adjcallstackup instruction into a 'sub ESP, <amt>' and the
@@ -3097,7 +3091,13 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
     return I;
   }
 
-  if (InternalAmt) {
+  if (isDestroy && InternalAmt && !blockEndIsUnreachable(MBB, I)) {
+    // If we are performing frame pointer elimination and if the callee pops
+    // something off the stack pointer, add it back.  We do this until we have
+    // more advanced stack pointer tracking ability.
+    // We are not tracking the stack pointer adjustment by the callee, so make
+    // sure we restore the stack pointer immediately after the call, there may
+    // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
     MachineBasicBlock::iterator CI = I;
     MachineBasicBlock::iterator B = MBB.begin();
     while (CI != B && !std::prev(CI)->isCall())
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cd3fa5c5372bf..e4bf4ab685388 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4366,6 +4366,12 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   else
     NumBytesForCalleeToPop = 0;  // Callee pops nothing.
 
+  if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
+    // No need to reset the stack after the call if the call doesn't return. To
+    // make the MI verify, we'll pretend the callee does it for us.
+    NumBytesForCalleeToPop = NumBytes;
+  }
+
   // Returns a flag for retval copy to use.
   if (!IsSibcall) {
     Chain = DAG.getCALLSEQ_END(Chain,
@@ -6528,11 +6534,12 @@ static bool getTargetConstantBitsFromNode(SDValue Op, unsigned EltSizeInBits,
 
 namespace llvm {
 namespace X86 {
-bool isConstantSplat(SDValue Op, APInt &SplatVal) {
+bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs) {
   APInt UndefElts;
   SmallVector<APInt, 16> EltBits;
   if (getTargetConstantBitsFromNode(Op, Op.getScalarValueSizeInBits(),
-                                    UndefElts, EltBits, true, false)) {
+                                    UndefElts, EltBits, true,
+                                    AllowPartialUndefs)) {
     int SplatIndex = -1;
     for (int i = 0, e = EltBits.size(); i != e; ++i) {
       if (UndefElts[i])
@@ -20963,9 +20970,12 @@ static SDValue getSETCC(X86::CondCode Cond, SDValue EFLAGS, const SDLoc &dl,
 }
 
 /// Helper for matching OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1),...))
-/// style scalarized (associative) reduction patterns.
+/// style scalarized (associative) reduction patterns. Partial reductions
+/// are supported when the pointer SrcMask is non-null.
+/// TODO - move this to SelectionDAG?
 static bool matchScalarReduction(SDValue Op, ISD::NodeType BinOp,
-                                 SmallVectorImpl<SDValue> &SrcOps) {
+                                 SmallVectorImpl<SDValue> &SrcOps,
+                                 SmallVectorImpl<APInt> *SrcMask = nullptr) {
   SmallVector<SDValue, 8> Opnds;
   DenseMap<SDValue, APInt> SrcOpMap;
   EVT VT = MVT::Other;
@@ -21017,12 +21027,18 @@ static bool matchScalarReduction(SDValue Op, ISD::NodeType BinOp,
     M->second.setBit(CIdx);
   }
 
-  // Quit if not all elements are used.
-  for (DenseMap<SDValue, APInt>::const_iterator I = SrcOpMap.begin(),
-                                                E = SrcOpMap.end();
-       I != E; ++I) {
-    if (!I->second.isAllOnesValue())
-      return false;
+  if (SrcMask) {
+    // Collect the source partial masks.
+    for (SDValue &SrcOp : SrcOps)
+      SrcMask->push_back(SrcOpMap[SrcOp]);
+  } else {
+    // Quit if not all elements are used.
+    for (DenseMap<SDValue, APInt>::const_iterator I = SrcOpMap.begin(),
+                                                  E = SrcOpMap.end();
+         I != E; ++I) {
+      if (!I->second.isAllOnesValue())
+        return false;
+    }
   }
 
   return true;
@@ -27359,30 +27375,19 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
   int NumElts = VT.getVectorNumElements();
 
   // Check for constant splat rotation amount.
-  APInt UndefElts;
-  SmallVector<APInt, 32> EltBits;
-  int CstSplatIndex = -1;
-  if (getTargetConstantBitsFromNode(Amt, EltSizeInBits, UndefElts, EltBits))
-    for (int i = 0; i != NumElts; ++i)
-      if (!UndefElts[i]) {
-        if (CstSplatIndex < 0 || EltBits[i] == EltBits[CstSplatIndex]) {
-          CstSplatIndex = i;
-          continue;
-        }
-        CstSplatIndex = -1;
-        break;
-      }
+  APInt CstSplatValue;
+  bool IsCstSplat = X86::isConstantSplat(Amt, CstSplatValue);
 
   // Check for splat rotate by zero.
-  if (0 <= CstSplatIndex && EltBits[CstSplatIndex].urem(EltSizeInBits) == 0)
+  if (IsCstSplat && CstSplatValue.urem(EltSizeInBits) == 0)
     return R;
 
   // AVX512 implicitly uses modulo rotation amounts.
   if (Subtarget.hasAVX512() && 32 <= EltSizeInBits) {
     // Attempt to rotate by immediate.
-    if (0 <= CstSplatIndex) {
+    if (IsCstSplat) {
       unsigned RotOpc = (Opcode == ISD::ROTL ? X86ISD::VROTLI : X86ISD::VROTRI);
-      uint64_t RotAmt = EltBits[CstSplatIndex].urem(EltSizeInBits);
+      uint64_t RotAmt = CstSplatValue.urem(EltSizeInBits);
       return DAG.getNode(RotOpc, DL, VT, R,
                          DAG.getTargetConstant(RotAmt, DL, MVT::i8));
     }
@@ -27402,10 +27407,10 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
     assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
 
     // Attempt to rotate by immediate.
-    if (0 <= CstSplatIndex) {
-      uint64_t RotateAmt = EltBits[CstSplatIndex].urem(EltSizeInBits);
+    if (IsCstSplat) {
+      uint64_t RotAmt = CstSplatValue.urem(EltSizeInBits);
       return DAG.getNode(X86ISD::VROTLI, DL, VT, R,
-                         DAG.getTargetConstant(RotateAmt, DL, MVT::i8));
+                         DAG.getTargetConstant(RotAmt, DL, MVT::i8));
     }
 
     // Use general rotate by variable (per-element).
@@ -27422,7 +27427,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
          "Only vXi32/vXi16/vXi8 vector rotates supported");
 
   // Rotate by an uniform constant - expand back to shifts.
-  if (0 <= CstSplatIndex)
+  if (IsCstSplat)
     return SDValue();
 
   bool IsSplatAmt = DAG.isSplatValue(Amt);
@@ -41220,7 +41225,8 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
   // TODO: Support multiple SrcOps.
   if (VT == MVT::i1) {
     SmallVector<SDValue, 2> SrcOps;
-    if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
+    SmallVector<APInt, 2> SrcPartials;
+    if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps, &SrcPartials) &&
         SrcOps.size() == 1) {
       SDLoc dl(N);
       const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -41230,9 +41236,11 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
       if (!Mask && TLI.isTypeLegal(SrcOps[0].getValueType()))
         Mask = DAG.getBitcast(MaskVT, SrcOps[0]);
       if (Mask) {
-        APInt AllBits = APInt::getAllOnesValue(NumElts);
-        return DAG.getSetCC(dl, MVT::i1, Mask,
-                            DAG.getConstant(AllBits, dl, MaskVT), ISD::SETEQ);
+        assert(SrcPartials[0].getBitWidth() == NumElts &&
+               "Unexpected partial reduction mask");
+        SDValue PartialBits = DAG.getConstant(SrcPartials[0], dl, MaskVT);
+        Mask = DAG.getNode(ISD::AND, dl, MaskVT, Mask, PartialBits);
+        return DAG.getSetCC(dl, MVT::i1, Mask, PartialBits, ISD::SETEQ);
       }
     }
   }
@@ -41627,30 +41635,9 @@ static SDValue combineOrShiftToFunnelShift(SDNode *N, SelectionDAG &DAG,
                        DAG.getNode(ISD::TRUNCATE, DL, ShiftVT, Amt));
   };
 
-  // OR( SHL( X, C ), SRL( Y, 32 - C ) ) -> FSHL( X, Y, C )
-  // OR( SRL( X, C ), SHL( Y, 32 - C ) ) -> FSHR( Y, X, C )
   // OR( SHL( X, C ), SRL( SRL( Y, 1 ), XOR( C, 31 ) ) ) -> FSHL( X, Y, C )
   // OR( SRL( X, C ), SHL( SHL( Y, 1 ), XOR( C, 31 ) ) ) -> FSHR( Y, X, C )
-  // OR( SHL( X, AND( C, 31 ) ), SRL( Y, AND( 0 - C, 31 ) ) ) -> FSHL( X, Y, C )
-  // OR( SRL( X, AND( C, 31 ) ), SHL( Y, AND( 0 - C, 31 ) ) ) -> FSHR( Y, X, C )
-  if (ShAmt1.getOpcode() == ISD::SUB) {
-    SDValue Sum = ShAmt1.getOperand(0);
-    if (auto *SumC = dyn_cast<ConstantSDNode>(Sum)) {
-      SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
-      if (ShAmt1Op1.getOpcode() == ISD::AND &&
-          isa<ConstantSDNode>(ShAmt1Op1.getOperand(1)) &&
-          ShAmt1Op1.getConstantOperandAPInt(1) == (Bits - 1)) {
-        ShMsk1 = ShAmt1Op1;
-        ShAmt1Op1 = ShAmt1Op1.getOperand(0);
-      }
-      if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
-        ShAmt1Op1 = ShAmt1Op1.getOperand(0);
-      if ((SumC->getAPIntValue() == Bits ||
-           (SumC->getAPIntValue() == 0 && ShMsk1)) &&
-          ShAmt1Op1 == ShAmt0)
-        return GetFunnelShift(Op0, Op1, ShAmt0);
-    }
-  } else if (ShAmt1.getOpcode() == ISD::XOR) {
+  if (ShAmt1.getOpcode() == ISD::XOR) {
     SDValue Mask = ShAmt1.getOperand(1);
     if (auto *MaskC = dyn_cast<ConstantSDNode>(Mask)) {
       unsigned InnerShift = (ISD::FSHL == Opc ? ISD::SRL : ISD::SHL);
@@ -41695,7 +41682,8 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
   // TODO: Support multiple SrcOps.
   if (VT == MVT::i1) {
     SmallVector<SDValue, 2> SrcOps;
-    if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps) &&
+    SmallVector<APInt, 2> SrcPartials;
+    if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps, &SrcPartials) &&
         SrcOps.size() == 1) {
       SDLoc dl(N);
       const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -41705,9 +41693,12 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
       if (!Mask && TLI.isTypeLegal(SrcOps[0].getValueType()))
         Mask = DAG.getBitcast(MaskVT, SrcOps[0]);
       if (Mask) {
-        APInt AllBits = APInt::getNullValue(NumElts);
-        return DAG.getSetCC(dl, MVT::i1, Mask,
-                            DAG.getConstant(AllBits, dl, MaskVT), ISD::SETNE);
+        assert(SrcPartials[0].getBitWidth() == NumElts &&
+               "Unexpected partial reduction mask");
+        SDValue ZeroBits = DAG.getConstant(0, dl, MaskVT);
+        SDValue PartialBits = DAG.getConstant(SrcPartials[0], dl, MaskVT);
+        Mask = DAG.getNode(ISD::AND, dl, MaskVT, Mask, PartialBits);
+        return DAG.getSetCC(dl, MVT::i1, Mask, ZeroBits, ISD::SETNE);
       }
     }
   }
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 0da22acc99de5..825ddedad1768 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -722,7 +722,10 @@ namespace llvm {
 
     /// If Op is a constant whose elements are all the same constant or
     /// undefined, return true and return the constant value in \p SplatVal.
-    bool isConstantSplat(SDValue Op, APInt &SplatVal);
+    /// If we have undef bits that don't cover an entire element, we treat these
+    /// as zero if AllowPartialUndefs is set, else we fail and return false.
+    bool isConstantSplat(SDValue Op, APInt &SplatVal,
+                         bool AllowPartialUndefs = true);
   } // end namespace X86
 
   //===--------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp b/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp
index 48d0d8a35704e..743df41a00ffb 100644
--- a/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp
+++ b/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp
@@ -127,11 +127,18 @@ bool X86IndirectBranchTrackingPass::runOnMachineFunction(MachineFunction &MF) {
     if (MBB.hasAddressTaken())
       Changed |= addENDBR(MBB, MBB.begin());
 
+    // Exception handle may indirectly jump to catch pad, So we should add
+    // ENDBR before catch pad instructions.
+    bool EHPadIBTNeeded = MBB.isEHPad();
+
     for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
-      if (!I->isCall())
-        continue;
-      if (IsCallReturnTwice(I->getOperand(0)))
+      if (I->isCall() && IsCallReturnTwice(I->getOperand(0)))
         Changed |= addENDBR(MBB, std::next(I));
+
+      if (EHPadIBTNeeded && I->isEHLabel()) {
+          Changed |= addENDBR(MBB, std::next(I));
+          EHPadIBTNeeded = false;
+      }
     }
   }
   return Changed;
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 8ed20cdabf7ac..b23050ef61aca 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -12235,6 +12235,7 @@ multiclass avx512_binop_all2<bits<8> opc, string OpcodeStr,
   }
 }
 
+let ExeDomain = SSEPackedSingle in
 defm VCVTNE2PS2BF16 : avx512_binop_all2<0x72, "vcvtne2ps2bf16",
                                         SchedWriteCvtPD2PS, //FIXME: Shoulod be SchedWriteCvtPS2BF
                                         avx512vl_f32_info, avx512vl_i16_info,
@@ -12243,6 +12244,7 @@ defm VCVTNE2PS2BF16 : avx512_binop_all2<0x72, "vcvtne2ps2bf16",
 // Truncate Float to BFloat16
 multiclass avx512_cvtps2bf16<bits<8> opc, string OpcodeStr,
                              X86SchedWriteWidths sched> {
+  let ExeDomain = SSEPackedSingle in {
   let Predicates = [HasBF16], Uses = []<Register>, mayRaiseFPException = 0 in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i16x_info, v16f32_info,
                             X86cvtneps2bf16, X86cvtneps2bf16, sched.ZMM>, EVEX_V512;
@@ -12256,20 +12258,21 @@ multiclass avx512_cvtps2bf16<bits<8> opc, string OpcodeStr,
                                X86cvtneps2bf16, X86cvtneps2bf16,
                                sched.YMM, "{1to8}", "{y}">, EVEX_V256;
     }
+  } // Predicates = [HasBF16, HasVLX]
+  } // ExeDomain = SSEPackedSingle
 
-    def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
-                    (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
-                    VR128X:$src), 0>;
-    def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
-                    (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst,
-                    f128mem:$src), 0, "intel">;
-    def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
-                    (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
-                    VR256X:$src), 0>;
-    def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
-                    (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst,
-                    f256mem:$src), 0, "intel">;
-  }
+  def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
+                  (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
+                  VR128X:$src), 0>;
+  def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
+                  (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst,
+                  f128mem:$src), 0, "intel">;
+  def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
+                  (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
+                  VR256X:$src), 0>;
+  def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
+                  (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst,
+                  f256mem:$src), 0, "intel">;
 }
 
 defm VCVTNEPS2BF16 : avx512_cvtps2bf16<0x72, "vcvtneps2bf16",
@@ -12352,6 +12355,7 @@ multiclass avx512_dpbf16ps_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
   }
 }
 
+let ExeDomain = SSEPackedSingle in
 defm VDPBF16PS : avx512_dpbf16ps_sizes<0x52, "vdpbf16ps", X86dpbf16ps, SchedWriteFMA,
                                        avx512vl_f32_info, avx512vl_i32_info,
                                        HasBF16>, T8XS, EVEX_CD8<32, CD8VF>;
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 7187156fc276e..a03c75bb7dda2 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1297,6 +1297,8 @@ int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
     { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1, 2 },
     { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
     { ISD::ZERO_EXTEND, MVT::v64i8,  MVT::v64i1, 2 },
+
+    { ISD::TRUNCATE,    MVT::v32i8,  MVT::v32i16, 1 },
   };
 
   static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
index 7516c633d4068..753ada0b8000b 100644
--- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
@@ -233,9 +233,9 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF,
   // to determine the end of the prologue.
   DebugLoc dl;
 
-  if (MFI.getMaxAlignment() > getStackAlignment())
-    report_fatal_error("emitPrologue unsupported alignment: "
-                       + Twine(MFI.getMaxAlignment()));
+  if (MFI.getMaxAlign() > getStackAlign())
+    report_fatal_error("emitPrologue unsupported alignment: " +
+                       Twine(MFI.getMaxAlign().value()));
 
   const AttributeList &PAL = MF.getFunction().getAttributes();
   if (PAL.hasAttrSomewhere(Attribute::Nest))
@@ -490,8 +490,7 @@ MachineBasicBlock::iterator XCoreFrameLowering::eliminateCallFramePseudoInstr(
       // We need to keep the stack aligned properly.  To do this, we round the
       // amount of space needed for the outgoing arguments up to the next
       // alignment boundary.
-      unsigned Align = getStackAlignment();
-      Amount = (Amount+Align-1)/Align*Align;
+      Amount = alignTo(Amount, getStackAlign());
 
       assert(Amount%4 == 0);
       Amount /= 4;
diff --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
index 3be31bcd172be..d718574a81c8c 100644
--- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
@@ -295,7 +295,7 @@ doPromotion(Function *F, SmallPtrSetImpl<Argument *> &ArgsToPromote,
               if (auto *ElPTy = dyn_cast<PointerType>(ElTy))
                 ElTy = ElPTy->getElementType();
               else
-                ElTy = cast<CompositeType>(ElTy)->getTypeAtIndex(II);
+                ElTy = GetElementPtrInst::getTypeAtIndex(ElTy, II);
             }
             // And create a GEP to extract those indices.
             V = IRB.CreateGEP(ArgIndex.first, V, Ops, V->getName() + ".idx");
@@ -784,7 +784,7 @@ bool ArgumentPromotionPass::isDenselyPacked(Type *type, const DataLayout &DL) {
   if (DL.getTypeSizeInBits(type) != DL.getTypeAllocSizeInBits(type))
     return false;
 
-  if (!isa<CompositeType>(type))
+  if (!isa<StructType>(type) && !isa<SequentialType>(type))
     return true;
 
   // For homogenous sequential types, check for padding within members.
diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index ff746ad0cbb3a..3b234ca0be7d3 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -142,7 +142,7 @@ static bool isLeakCheckerRoot(GlobalVariable *GV) {
                  E = STy->element_end(); I != E; ++I) {
           Type *InnerTy = *I;
           if (isa<PointerType>(InnerTy)) return true;
-          if (isa<CompositeType>(InnerTy))
+          if (isa<StructType>(InnerTy) || isa<SequentialType>(InnerTy))
             Types.push_back(InnerTy);
         }
         break;
diff --git a/llvm/lib/Transforms/IPO/StripSymbols.cpp b/llvm/lib/Transforms/IPO/StripSymbols.cpp
index 6ce00714523b3..088091df770f9 100644
--- a/llvm/lib/Transforms/IPO/StripSymbols.cpp
+++ b/llvm/lib/Transforms/IPO/StripSymbols.cpp
@@ -147,10 +147,12 @@ static void RemoveDeadConstant(Constant *C) {
   if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) {
     if (!GV->hasLocalLinkage()) return;   // Don't delete non-static globals.
     GV->eraseFromParent();
-  }
-  else if (!isa<Function>(C))
-    if (isa<CompositeType>(C->getType()))
+  } else if (!isa<Function>(C)) {
+    // FIXME: Why does the type of the constant matter here?
+    if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType()) ||
+        isa<VectorType>(C->getType()))
       C->destroyConstant();
+  }
 
   // If the constant referenced anything, see if we can delete it as well.
   for (Constant *O : Operands)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 494626519c064..2138017606b79 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -48,6 +48,7 @@
 #include "llvm/IR/IntrinsicsNVPTX.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsPowerPC.h"
+#include "llvm/IR/KnowledgeRetention.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/IR/PatternMatch.h"
@@ -471,17 +472,29 @@ static Value *simplifyX86varShift(const IntrinsicInst &II,
   }
   assert((LogicalShift || !ShiftLeft) && "Only logical shifts can shift left");
 
-  // Simplify if all shift amounts are constant/undef.
-  auto *CShift = dyn_cast<Constant>(II.getArgOperand(1));
-  if (!CShift)
-    return nullptr;
-
   auto Vec = II.getArgOperand(0);
+  auto Amt = II.getArgOperand(1);
   auto VT = cast<VectorType>(II.getType());
   auto SVT = VT->getVectorElementType();
   int NumElts = VT->getNumElements();
   int BitWidth = SVT->getIntegerBitWidth();
 
+  // If the shift amount is guaranteed to be in-range we can replace it with a
+  // generic shift.
+  APInt UpperBits =
+      APInt::getHighBitsSet(BitWidth, BitWidth - Log2_32(BitWidth));
+  if (llvm::MaskedValueIsZero(Amt, UpperBits,
+                              II.getModule()->getDataLayout())) {
+    return (LogicalShift ? (ShiftLeft ? Builder.CreateShl(Vec, Amt)
+                                      : Builder.CreateLShr(Vec, Amt))
+                         : Builder.CreateAShr(Vec, Amt));
+  }
+
+  // Simplify if all shift amounts are constant/undef.
+  auto *CShift = dyn_cast<Constant>(Amt);
+  if (!CShift)
+    return nullptr;
+
   // Collect each element's shift amount.
   // We also collect special cases: UNDEF = -1, OUT-OF-RANGE = BitWidth.
   bool AnyOutOfRange = false;
@@ -1806,6 +1819,18 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
   IntrinsicInst *II = dyn_cast<IntrinsicInst>(&CI);
   if (!II) return visitCallBase(CI);
 
+  // For atomic unordered mem intrinsics if len is not a positive or
+  // not a multiple of element size then behavior is undefined.
+  if (auto *AMI = dyn_cast<AtomicMemIntrinsic>(II))
+    if (ConstantInt *NumBytes = dyn_cast<ConstantInt>(AMI->getLength()))
+      if (NumBytes->getSExtValue() < 0 ||
+          (NumBytes->getZExtValue() % AMI->getElementSizeInBytes() != 0)) {
+        CreateNonTerminatorUnreachable(AMI);
+        assert(AMI->getType()->isVoidTy() &&
+               "non void atomic unordered mem intrinsic");
+        return eraseInstFromFunction(*AMI);
+      }
+
   // Intrinsics cannot occur in an invoke or a callbr, so handle them here
   // instead of in visitCallBase.
   if (auto *MI = dyn_cast<AnyMemIntrinsic>(II)) {
@@ -4081,7 +4106,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
     // then this one is redundant, and should be removed.
     KnownBits Known(1);
     computeKnownBits(IIOperand, Known, 0, II);
-    if (Known.isAllOnes())
+    if (Known.isAllOnes() && isAssumeWithEmptyBundle(*II))
       return eraseInstFromFunction(*II);
 
     // Update the cache of affected values for this assumption (we might be
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index 0b1d9e8df0392..afdddad10cea2 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -2421,10 +2421,8 @@ Instruction *InstCombiner::visitBitCast(BitCastInst &CI) {
     // to a getelementptr X, 0, 0, 0...  turn it into the appropriate gep.
     // This can enhance SROA and other transforms that want type-safe pointers.
     unsigned NumZeros = 0;
-    while (SrcElTy != DstElTy &&
-           isa<CompositeType>(SrcElTy) && !SrcElTy->isPointerTy() &&
-           SrcElTy->getNumContainedTypes() /* not "{}" */) {
-      SrcElTy = cast<CompositeType>(SrcElTy)->getTypeAtIndex(0U);
+    while (SrcElTy && SrcElTy != DstElTy) {
+      SrcElTy = GetElementPtrInst::getTypeAtIndex(SrcElTy, (uint64_t)0);
       ++NumZeros;
     }
 
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 59ed96a0257a0..aa5d33ce8ac8f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -456,22 +456,39 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
   case Instruction::Add:
     if ((DemandedMask & 1) == 0) {
       // If we do not need the low bit, try to convert bool math to logic:
-      //   add iN (zext i1 X), (sext i1 Y) --> sext (~X & Y) to iN
-      // Truth table for inputs and output signbits:
-      //       X:0 | X:1
-      //      ----------
-      // Y:0  |  0 | 0 |
-      // Y:1  | -1 | 0 |
-      //      ----------
+      // add iN (zext i1 X), (sext i1 Y) --> sext (~X & Y) to iN
       Value *X, *Y;
       if (match(I, m_c_Add(m_OneUse(m_ZExt(m_Value(X))),
                            m_OneUse(m_SExt(m_Value(Y))))) &&
           X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
+        // Truth table for inputs and output signbits:
+        //       X:0 | X:1
+        //      ----------
+        // Y:0  |  0 | 0 |
+        // Y:1  | -1 | 0 |
+        //      ----------
         IRBuilderBase::InsertPointGuard Guard(Builder);
         Builder.SetInsertPoint(I);
         Value *AndNot = Builder.CreateAnd(Builder.CreateNot(X), Y);
         return Builder.CreateSExt(AndNot, VTy);
       }
+
+      // add iN (sext i1 X), (sext i1 Y) --> sext (X | Y) to iN
+      // TODO: Relax the one-use checks because we are removing an instruction?
+      if (match(I, m_Add(m_OneUse(m_SExt(m_Value(X))),
+                         m_OneUse(m_SExt(m_Value(Y))))) &&
+          X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
+        // Truth table for inputs and output signbits:
+        //       X:0 | X:1
+        //      -----------
+        // Y:0  | -1 | -1 |
+        // Y:1  | -1 |  0 |
+        //      -----------
+        IRBuilderBase::InsertPointGuard Guard(Builder);
+        Builder.SetInsertPoint(I);
+        Value *Or = Builder.CreateOr(X, Y);
+        return Builder.CreateSExt(Or, VTy);
+      }
     }
     LLVM_FALLTHROUGH;
   case Instruction::Sub: {
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index e0063eb24515f..9d17e92eca203 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1961,10 +1961,9 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
         if (J > 0) {
           if (J == 1) {
             CurTy = Op1->getSourceElementType();
-          } else if (auto *CT = dyn_cast<CompositeType>(CurTy)) {
-            CurTy = CT->getTypeAtIndex(Op1->getOperand(J));
           } else {
-            CurTy = nullptr;
+            CurTy =
+                GetElementPtrInst::getTypeAtIndex(CurTy, Op1->getOperand(J));
           }
         }
       }
diff --git a/llvm/lib/Transforms/Scalar/SCCP.cpp b/llvm/lib/Transforms/Scalar/SCCP.cpp
index dcdc3483a9088..c17c35b7e3232 100644
--- a/llvm/lib/Transforms/Scalar/SCCP.cpp
+++ b/llvm/lib/Transforms/Scalar/SCCP.cpp
@@ -352,7 +352,7 @@ class SCCPSolver : public InstVisitor<SCCPSolver> {
 
   // pushToWorkList - Helper for markConstant/markOverdefined
   void pushToWorkList(LatticeVal &IV, Value *V) {
-    if (isOverdefined(IV))
+    if (IV.isOverdefined())
       return OverdefinedInstWorkList.push_back(V);
     InstWorkList.push_back(V);
   }
@@ -361,7 +361,7 @@ class SCCPSolver : public InstVisitor<SCCPSolver> {
   // prints a debug message with the updated value.
   void pushToWorkListMsg(LatticeVal &IV, Value *V) {
     LLVM_DEBUG(dbgs() << "updated " << IV << ": " << *V << '\n');
-    if (isOverdefined(IV))
+    if (IV.isOverdefined())
       return OverdefinedInstWorkList.push_back(V);
     InstWorkList.push_back(V);
   }
@@ -529,9 +529,20 @@ class SCCPSolver : public InstVisitor<SCCPSolver> {
 
   // Mark I's users as changed, including AdditionalUsers.
   void markUsersAsChanged(Value *I) {
-    for (User *U : I->users())
-      if (auto *UI = dyn_cast<Instruction>(U))
-        OperandChangedState(UI);
+    // Functions include their arguments in the use-list. Changed function
+    // values mean that the result of the function changed. We only need to
+    // update the call sites with the new function result and do not have to
+    // propagate the call arguments.
+    if (isa<Function>(I)) {
+      for (User *U : I->users()) {
+        if (auto CS = CallSite(U))
+          handleCallResult(CS);
+      }
+    } else {
+      for (User *U : I->users())
+        if (auto *UI = dyn_cast<Instruction>(U))
+          OperandChangedState(UI);
+    }
 
     auto Iter = AdditionalUsers.find(I);
     if (Iter != AdditionalUsers.end()) {
@@ -540,6 +551,9 @@ class SCCPSolver : public InstVisitor<SCCPSolver> {
           OperandChangedState(UI);
     }
   }
+  void handleCallOverdefined(CallSite CS);
+  void handleCallResult(CallSite CS);
+  void handleCallArguments(CallSite CS);
 
 private:
   friend class InstVisitor<SCCPSolver>;
@@ -779,7 +793,7 @@ void SCCPSolver::visitReturnInst(ReturnInst &I) {
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
   if (isOverdefined(ValueState[&I]))
-    return;
+    return (void)markOverdefined(&I);
 
   Function *F = I.getParent()->getParent();
   Value *ResultOp = I.getOperand(0);
@@ -820,7 +834,7 @@ void SCCPSolver::visitCastInst(CastInst &I) {
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
   if (isOverdefined(ValueState[&I]))
-    return;
+    return (void)markOverdefined(&I);
 
   LatticeVal OpSt = getValueState(I.getOperand(0));
   if (Constant *OpC = getConstant(OpSt)) {
@@ -838,7 +852,7 @@ void SCCPSolver::visitExtractValueInst(ExtractValueInst &EVI) {
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
   if (isOverdefined(ValueState[&EVI]))
-    return;
+    return (void)markOverdefined(&EVI);
 
   // If this returns a struct, mark all elements over defined, we don't track
   // structs in structs.
@@ -868,7 +882,7 @@ void SCCPSolver::visitInsertValueInst(InsertValueInst &IVI) {
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
   if (isOverdefined(ValueState[&IVI]))
-    return;
+    return (void)markOverdefined(&IVI);
 
   // If this has more than one index, we can't handle it, drive all results to
   // undef.
@@ -906,8 +920,8 @@ void SCCPSolver::visitSelectInst(SelectInst &I) {
 
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
-  if (isOverdefined(ValueState[&I]))
-    return;
+  if (ValueState[&I].isOverdefined())
+    return (void)markOverdefined(&I);
 
   LatticeVal CondValue = getValueState(I.getCondition());
   if (CondValue.isUnknownOrUndef())
@@ -925,16 +939,10 @@ void SCCPSolver::visitSelectInst(SelectInst &I) {
   LatticeVal TVal = getValueState(I.getTrueValue());
   LatticeVal FVal = getValueState(I.getFalseValue());
 
-  // select ?, C, C -> C.
-  if (isConstant(TVal) && isConstant(FVal) &&
-      getConstant(TVal) == getConstant(FVal))
-    return (void)markConstant(&I, getConstant(FVal));
-
-  if (TVal.isUnknownOrUndef())   // select ?, undef, X -> X.
-    return (void)mergeInValue(&I, FVal);
-  if (FVal.isUnknownOrUndef())   // select ?, X, undef -> X.
-    return (void)mergeInValue(&I, TVal);
-  markOverdefined(&I);
+  bool Changed = ValueState[&I].mergeIn(TVal, DL);
+  Changed |= ValueState[&I].mergeIn(FVal, DL);
+  if (Changed)
+    pushToWorkListMsg(ValueState[&I], &I);
 }
 
 // Handle Unary Operators.
@@ -944,7 +952,8 @@ void SCCPSolver::visitUnaryOperator(Instruction &I) {
   LatticeVal &IV = ValueState[&I];
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
-  if (isOverdefined(IV)) return;
+  if (isOverdefined(IV))
+    return (void)markOverdefined(&I);
 
   if (isConstant(V0State)) {
     Constant *C = ConstantExpr::get(I.getOpcode(), getConstant(V0State));
@@ -968,10 +977,8 @@ void SCCPSolver::visitBinaryOperator(Instruction &I) {
   LatticeVal V2State = getValueState(I.getOperand(1));
 
   LatticeVal &IV = ValueState[&I];
-  if (isOverdefined(IV)) {
-    markOverdefined(&I);
-    return;
-  }
+  if (isOverdefined(IV))
+    return (void)markOverdefined(&I);
 
   if (isConstant(V1State) && isConstant(V2State)) {
     Constant *C = ConstantExpr::get(I.getOpcode(), getConstant(V1State),
@@ -1032,10 +1039,8 @@ void SCCPSolver::visitBinaryOperator(Instruction &I) {
 void SCCPSolver::visitCmpInst(CmpInst &I) {
   // Do not cache this lookup, getValueState calls later in the function might
   // invalidate the reference.
-  if (isOverdefined(ValueState[&I])) {
-    markOverdefined(&I);
-    return;
-  }
+  if (isOverdefined(ValueState[&I]))
+    return (void)markOverdefined(&I);
 
   Value *Op1 = I.getOperand(0);
   Value *Op2 = I.getOperand(1);
@@ -1066,7 +1071,8 @@ void SCCPSolver::visitCmpInst(CmpInst &I) {
 // Handle getelementptr instructions.  If all operands are constants then we
 // can turn this into a getelementptr ConstantExpr.
 void SCCPSolver::visitGetElementPtrInst(GetElementPtrInst &I) {
-  if (isOverdefined(ValueState[&I])) return;
+  if (isOverdefined(ValueState[&I]))
+    return (void)markOverdefined(&I);
 
   SmallVector<Constant*, 8> Operands;
   Operands.reserve(I.getNumOperands());
@@ -1107,7 +1113,7 @@ void SCCPSolver::visitStoreInst(StoreInst &SI) {
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
   if (isOverdefined(ValueState[&SI]))
-    return;
+    return (void)markOverdefined(&SI);
 
   GlobalVariable *GV = cast<GlobalVariable>(SI.getOperand(1));
   DenseMap<GlobalVariable*, LatticeVal>::iterator I = TrackedGlobals.find(GV);
@@ -1130,7 +1136,7 @@ void SCCPSolver::visitLoadInst(LoadInst &I) {
   // ResolvedUndefsIn might mark I as overdefined. Bail out, even if we would
   // discover a concrete value later.
   if (isOverdefined(ValueState[&I]))
-    return;
+    return (void)markOverdefined(&I);
 
   LatticeVal PtrVal = getValueState(I.getOperand(0));
   if (PtrVal.isUnknownOrUndef())
@@ -1177,6 +1183,87 @@ void SCCPSolver::visitLoadInst(LoadInst &I) {
 }
 
 void SCCPSolver::visitCallSite(CallSite CS) {
+  handleCallResult(CS);
+  handleCallArguments(CS);
+}
+
+void SCCPSolver::handleCallOverdefined(CallSite CS) {
+  Function *F = CS.getCalledFunction();
+  Instruction *I = CS.getInstruction();
+
+  // Void return and not tracking callee, just bail.
+  if (I->getType()->isVoidTy())
+    return;
+
+  // Otherwise, if we have a single return value case, and if the function is
+  // a declaration, maybe we can constant fold it.
+  if (F && F->isDeclaration() && !I->getType()->isStructTy() &&
+      canConstantFoldCallTo(cast<CallBase>(CS.getInstruction()), F)) {
+    SmallVector<Constant *, 8> Operands;
+    for (CallSite::arg_iterator AI = CS.arg_begin(), E = CS.arg_end(); AI != E;
+         ++AI) {
+      if (AI->get()->getType()->isStructTy())
+        return markOverdefined(I); // Can't handle struct args.
+      LatticeVal State = getValueState(*AI);
+
+      if (State.isUnknownOrUndef())
+        return; // Operands are not resolved yet.
+      if (isOverdefined(State))
+        return (void)markOverdefined(I);
+      assert(isConstant(State) && "Unknown state!");
+      Operands.push_back(getConstant(State));
+    }
+
+    if (isOverdefined(getValueState(I)))
+      return (void)markOverdefined(I);
+
+    // If we can constant fold this, mark the result of the call as a
+    // constant.
+    if (Constant *C = ConstantFoldCall(cast<CallBase>(CS.getInstruction()), F,
+                                       Operands, &GetTLI(*F))) {
+      // call -> undef.
+      if (isa<UndefValue>(C))
+        return;
+      return (void)markConstant(I, C);
+    }
+  }
+
+  // Otherwise, we don't know anything about this call, mark it overdefined.
+  return (void)markOverdefined(I);
+}
+
+void SCCPSolver::handleCallArguments(CallSite CS) {
+  Function *F = CS.getCalledFunction();
+  // If this is a local function that doesn't have its address taken, mark its
+  // entry block executable and merge in the actual arguments to the call into
+  // the formal arguments of the function.
+  if (!TrackingIncomingArguments.empty() &&
+      TrackingIncomingArguments.count(F)) {
+    MarkBlockExecutable(&F->front());
+
+    // Propagate information from this call site into the callee.
+    CallSite::arg_iterator CAI = CS.arg_begin();
+    for (Function::arg_iterator AI = F->arg_begin(), E = F->arg_end(); AI != E;
+         ++AI, ++CAI) {
+      // If this argument is byval, and if the function is not readonly, there
+      // will be an implicit copy formed of the input aggregate.
+      if (AI->hasByValAttr() && !F->onlyReadsMemory()) {
+        markOverdefined(&*AI);
+        continue;
+      }
+
+      if (auto *STy = dyn_cast<StructType>(AI->getType())) {
+        for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
+          LatticeVal CallArg = getStructValueState(*CAI, i);
+          mergeInValue(getStructValueState(&*AI, i), &*AI, CallArg);
+        }
+      } else
+        mergeInValue(&*AI, getValueState(*CAI), false);
+    }
+  }
+}
+
+void SCCPSolver::handleCallResult(CallSite CS) {
   Function *F = CS.getCalledFunction();
   Instruction *I = CS.getInstruction();
 
@@ -1242,79 +1329,13 @@ void SCCPSolver::visitCallSite(CallSite CS) {
   // The common case is that we aren't tracking the callee, either because we
   // are not doing interprocedural analysis or the callee is indirect, or is
   // external.  Handle these cases first.
-  if (!F || F->isDeclaration()) {
-CallOverdefined:
-    // Void return and not tracking callee, just bail.
-    if (I->getType()->isVoidTy()) return;
-
-    // Otherwise, if we have a single return value case, and if the function is
-    // a declaration, maybe we can constant fold it.
-    if (F && F->isDeclaration() && !I->getType()->isStructTy() &&
-        canConstantFoldCallTo(cast<CallBase>(CS.getInstruction()), F)) {
-      SmallVector<Constant*, 8> Operands;
-      for (CallSite::arg_iterator AI = CS.arg_begin(), E = CS.arg_end();
-           AI != E; ++AI) {
-        if (AI->get()->getType()->isStructTy())
-          return markOverdefined(I); // Can't handle struct args.
-        LatticeVal State = getValueState(*AI);
-
-        if (State.isUnknownOrUndef())
-          return;  // Operands are not resolved yet.
-        if (isOverdefined(State))
-          return (void)markOverdefined(I);
-        assert(isConstant(State) && "Unknown state!");
-        Operands.push_back(getConstant(State));
-      }
-
-      if (isOverdefined(getValueState(I)))
-        return;
-
-      // If we can constant fold this, mark the result of the call as a
-      // constant.
-      if (Constant *C = ConstantFoldCall(cast<CallBase>(CS.getInstruction()), F,
-                                         Operands, &GetTLI(*F))) {
-        // call -> undef.
-        if (isa<UndefValue>(C))
-          return;
-        return (void)markConstant(I, C);
-      }
-    }
-
-    // Otherwise, we don't know anything about this call, mark it overdefined.
-    return (void)markOverdefined(I);
-  }
-
-  // If this is a local function that doesn't have its address taken, mark its
-  // entry block executable and merge in the actual arguments to the call into
-  // the formal arguments of the function.
-  if (!TrackingIncomingArguments.empty() && TrackingIncomingArguments.count(F)){
-    MarkBlockExecutable(&F->front());
-
-    // Propagate information from this call site into the callee.
-    CallSite::arg_iterator CAI = CS.arg_begin();
-    for (Function::arg_iterator AI = F->arg_begin(), E = F->arg_end();
-         AI != E; ++AI, ++CAI) {
-      // If this argument is byval, and if the function is not readonly, there
-      // will be an implicit copy formed of the input aggregate.
-      if (AI->hasByValAttr() && !F->onlyReadsMemory()) {
-        markOverdefined(&*AI);
-        continue;
-      }
-
-      if (auto *STy = dyn_cast<StructType>(AI->getType())) {
-        for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
-          LatticeVal CallArg = getStructValueState(*CAI, i);
-          mergeInValue(getStructValueState(&*AI, i), &*AI, CallArg, false);
-        }
-      } else
-        mergeInValue(&*AI, getValueState(*CAI), false);
-    }
-  }
+  if (!F || F->isDeclaration())
+    return handleCallOverdefined(CS);
 
   // If this is a single/zero retval case, see if we're tracking the function.
   if (auto *STy = dyn_cast<StructType>(F->getReturnType())) {
     if (!MRVFunctionsTracked.count(F))
-      goto CallOverdefined;  // Not tracking this callee.
+      return handleCallOverdefined(CS); // Not tracking this callee.
 
     // If we are tracking this callee, propagate the result of the function
     // into this call site.
@@ -1324,7 +1345,7 @@ void SCCPSolver::visitCallSite(CallSite CS) {
   } else {
     MapVector<Function*, LatticeVal>::iterator TFRVI = TrackedRetVals.find(F);
     if (TFRVI == TrackedRetVals.end())
-      goto CallOverdefined;  // Not tracking this callee.
+      return handleCallOverdefined(CS); // Not tracking this callee.
 
     // If so, propagate the return value of the callee into this call result.
     mergeInValue(I, TFRVI->second);
@@ -1365,7 +1386,7 @@ void SCCPSolver::Solve() {
       // since all of its users will have already been marked as overdefined.
       // Update all of the users of this instruction's value.
       //
-      if (I->getType()->isStructTy() || !isOverdefined(getValueState(I)))
+      if (I->getType()->isStructTy() || !getValueState(I).isOverdefined())
         markUsersAsChanged(I);
     }
 
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index d64ba1db95a65..1267226dfeb2b 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -59,6 +59,7 @@
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/KnowledgeRetention.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/MDBuilder.h"
 #include "llvm/IR/Metadata.h"
@@ -411,7 +412,8 @@ bool llvm::wouldInstructionBeTriviallyDead(Instruction *I,
     // true are operationally no-ops.  In the future we can consider more
     // sophisticated tradeoffs for guards considering potential for check
     // widening, but for now we keep things simple.
-    if (II->getIntrinsicID() == Intrinsic::assume ||
+    if ((II->getIntrinsicID() == Intrinsic::assume &&
+         isAssumeWithEmptyBundle(*II)) ||
         II->getIntrinsicID() == Intrinsic::experimental_guard) {
       if (ConstantInt *Cond = dyn_cast<ConstantInt>(II->getArgOperand(0)))
         return !Cond->isZero();
diff --git a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
index 39be3d3831f00..8804bba975b6a 100644
--- a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
+++ b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
@@ -314,8 +314,14 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) {
                    L->dump());
         return Rotated;
       }
-      if (Metrics.NumInsts > MaxHeaderSize)
+      if (Metrics.NumInsts > MaxHeaderSize) {
+        LLVM_DEBUG(dbgs() << "LoopRotation: NOT rotating - contains "
+                          << Metrics.NumInsts
+                          << " instructions, which is more than the threshold ("
+                          << MaxHeaderSize << " instructions): ";
+                   L->dump());
         return Rotated;
+      }
     }
 
     // Now, this loop is suitable for rotation.
diff --git a/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp b/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
index 0cc085dc366c6..0bb2746eed2d0 100644
--- a/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
+++ b/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
@@ -14,17 +14,9 @@
 
 using namespace llvm;
 
-static unsigned getLoopOperandSizeInBytes(Type *Type) {
-  if (VectorType *VTy = dyn_cast<VectorType>(Type)) {
-    return VTy->getBitWidth() / 8;
-  }
-
-  return Type->getPrimitiveSizeInBits() / 8;
-}
-
 void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
                                      Value *DstAddr, ConstantInt *CopyLen,
-                                     unsigned SrcAlign, unsigned DestAlign,
+                                     unsigned SrcAlign, unsigned DstAlign,
                                      bool SrcIsVolatile, bool DstIsVolatile,
                                      const TargetTransformInfo &TTI) {
   // No need to expand zero length copies.
@@ -35,17 +27,18 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
   BasicBlock *PostLoopBB = nullptr;
   Function *ParentFunc = PreLoopBB->getParent();
   LLVMContext &Ctx = PreLoopBB->getContext();
+  const DataLayout &DL = ParentFunc->getParent()->getDataLayout();
+
+  unsigned SrcAS = cast<PointerType>(SrcAddr->getType())->getAddressSpace();
+  unsigned DstAS = cast<PointerType>(DstAddr->getType())->getAddressSpace();
 
   Type *TypeOfCopyLen = CopyLen->getType();
-  Type *LoopOpType =
-      TTI.getMemcpyLoopLoweringType(Ctx, CopyLen, SrcAlign, DestAlign);
+  Type *LoopOpType = TTI.getMemcpyLoopLoweringType(Ctx, CopyLen, SrcAS, DstAS,
+                                                   SrcAlign, DstAlign);
 
-  unsigned LoopOpSize = getLoopOperandSizeInBytes(LoopOpType);
+  unsigned LoopOpSize = DL.getTypeStoreSize(LoopOpType);
   uint64_t LoopEndCount = CopyLen->getZExtValue() / LoopOpSize;
 
-  unsigned SrcAS = cast<PointerType>(SrcAddr->getType())->getAddressSpace();
-  unsigned DstAS = cast<PointerType>(DstAddr->getType())->getAddressSpace();
-
   if (LoopEndCount != 0) {
     // Split
     PostLoopBB = PreLoopBB->splitBasicBlock(InsertBefore, "memcpy-split");
@@ -66,16 +59,20 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
       DstAddr = PLBuilder.CreateBitCast(DstAddr, DstOpType);
     }
 
+    Align PartDstAlign(MinAlign(DstAlign, LoopOpSize));
+    Align PartSrcAlign(MinAlign(SrcAlign, LoopOpSize));
+
     IRBuilder<> LoopBuilder(LoopBB);
     PHINode *LoopIndex = LoopBuilder.CreatePHI(TypeOfCopyLen, 2, "loop-index");
     LoopIndex->addIncoming(ConstantInt::get(TypeOfCopyLen, 0U), PreLoopBB);
     // Loop Body
     Value *SrcGEP =
         LoopBuilder.CreateInBoundsGEP(LoopOpType, SrcAddr, LoopIndex);
-    Value *Load = LoopBuilder.CreateLoad(LoopOpType, SrcGEP, SrcIsVolatile);
+    Value *Load = LoopBuilder.CreateAlignedLoad(LoopOpType, SrcGEP,
+                                                PartSrcAlign, SrcIsVolatile);
     Value *DstGEP =
         LoopBuilder.CreateInBoundsGEP(LoopOpType, DstAddr, LoopIndex);
-    LoopBuilder.CreateStore(Load, DstGEP, DstIsVolatile);
+    LoopBuilder.CreateAlignedStore(Load, DstGEP, PartDstAlign, DstIsVolatile);
 
     Value *NewIndex =
         LoopBuilder.CreateAdd(LoopIndex, ConstantInt::get(TypeOfCopyLen, 1U));
@@ -93,17 +90,16 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
     IRBuilder<> RBuilder(PostLoopBB ? PostLoopBB->getFirstNonPHI()
                                     : InsertBefore);
 
-    // Update the alignment based on the copy size used in the loop body.
-    SrcAlign = std::min(SrcAlign, LoopOpSize);
-    DestAlign = std::min(DestAlign, LoopOpSize);
-
     SmallVector<Type *, 5> RemainingOps;
     TTI.getMemcpyLoopResidualLoweringType(RemainingOps, Ctx, RemainingBytes,
-                                          SrcAlign, DestAlign);
+                                          SrcAS, DstAS, SrcAlign, DstAlign);
 
     for (auto OpTy : RemainingOps) {
+      Align PartSrcAlign(MinAlign(SrcAlign, BytesCopied));
+      Align PartDstAlign(MinAlign(DstAlign, BytesCopied));
+
       // Calaculate the new index
-      unsigned OperandSize = getLoopOperandSizeInBytes(OpTy);
+      unsigned OperandSize = DL.getTypeStoreSize(OpTy);
       uint64_t GepIndex = BytesCopied / OperandSize;
       assert(GepIndex * OperandSize == BytesCopied &&
              "Division should have no Remainder!");
@@ -114,7 +110,8 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
                              : RBuilder.CreateBitCast(SrcAddr, SrcPtrType);
       Value *SrcGEP = RBuilder.CreateInBoundsGEP(
           OpTy, CastedSrc, ConstantInt::get(TypeOfCopyLen, GepIndex));
-      Value *Load = RBuilder.CreateLoad(OpTy, SrcGEP, SrcIsVolatile);
+      Value *Load =
+          RBuilder.CreateAlignedLoad(OpTy, SrcGEP, PartSrcAlign, SrcIsVolatile);
 
       // Cast destination to operand type and store.
       PointerType *DstPtrType = PointerType::get(OpTy, DstAS);
@@ -123,7 +120,7 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
                              : RBuilder.CreateBitCast(DstAddr, DstPtrType);
       Value *DstGEP = RBuilder.CreateInBoundsGEP(
           OpTy, CastedDst, ConstantInt::get(TypeOfCopyLen, GepIndex));
-      RBuilder.CreateStore(Load, DstGEP, DstIsVolatile);
+      RBuilder.CreateAlignedStore(Load, DstGEP, PartDstAlign, DstIsVolatile);
 
       BytesCopied += OperandSize;
     }
@@ -135,7 +132,7 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr,
 void llvm::createMemCpyLoopUnknownSize(Instruction *InsertBefore,
                                        Value *SrcAddr, Value *DstAddr,
                                        Value *CopyLen, unsigned SrcAlign,
-                                       unsigned DestAlign, bool SrcIsVolatile,
+                                       unsigned DstAlign, bool SrcIsVolatile,
                                        bool DstIsVolatile,
                                        const TargetTransformInfo &TTI) {
   BasicBlock *PreLoopBB = InsertBefore->getParent();
@@ -143,16 +140,17 @@ void llvm::createMemCpyLoopUnknownSize(Instruction *InsertBefore,
       PreLoopBB->splitBasicBlock(InsertBefore, "post-loop-memcpy-expansion");
 
   Function *ParentFunc = PreLoopBB->getParent();
+  const DataLayout &DL = ParentFunc->getParent()->getDataLayout();
   LLVMContext &Ctx = PreLoopBB->getContext();
+  unsigned SrcAS = cast<PointerType>(SrcAddr->getType())->getAddressSpace();
+  unsigned DstAS = cast<PointerType>(DstAddr->getType())->getAddressSpace();
 
-  Type *LoopOpType =
-      TTI.getMemcpyLoopLoweringType(Ctx, CopyLen, SrcAlign, DestAlign);
-  unsigned LoopOpSize = getLoopOperandSizeInBytes(LoopOpType);
+  Type *LoopOpType = TTI.getMemcpyLoopLoweringType(Ctx, CopyLen, SrcAS, DstAS,
+                                                   SrcAlign, DstAlign);
+  unsigned LoopOpSize = DL.getTypeStoreSize(LoopOpType);
 
   IRBuilder<> PLBuilder(PreLoopBB->getTerminator());
 
-  unsigned SrcAS = cast<PointerType>(SrcAddr->getType())->getAddressSpace();
-  unsigned DstAS = cast<PointerType>(DstAddr->getType())->getAddressSpace();
   PointerType *SrcOpType = PointerType::get(LoopOpType, SrcAS);
   PointerType *DstOpType = PointerType::get(LoopOpType, DstAS);
   if (SrcAddr->getType() != SrcOpType) {
@@ -177,13 +175,17 @@ void llvm::createMemCpyLoopUnknownSize(Instruction *InsertBefore,
       BasicBlock::Create(Ctx, "loop-memcpy-expansion", ParentFunc, PostLoopBB);
   IRBuilder<> LoopBuilder(LoopBB);
 
+  Align PartSrcAlign(MinAlign(SrcAlign, LoopOpSize));
+  Align PartDstAlign(MinAlign(DstAlign, LoopOpSize));
+
   PHINode *LoopIndex = LoopBuilder.CreatePHI(CopyLenType, 2, "loop-index");
   LoopIndex->addIncoming(ConstantInt::get(CopyLenType, 0U), PreLoopBB);
 
   Value *SrcGEP = LoopBuilder.CreateInBoundsGEP(LoopOpType, SrcAddr, LoopIndex);
-  Value *Load = LoopBuilder.CreateLoad(LoopOpType, SrcGEP, SrcIsVolatile);
+  Value *Load = LoopBuilder.CreateAlignedLoad(LoopOpType, SrcGEP, PartSrcAlign,
+                                              SrcIsVolatile);
   Value *DstGEP = LoopBuilder.CreateInBoundsGEP(LoopOpType, DstAddr, LoopIndex);
-  LoopBuilder.CreateStore(Load, DstGEP, DstIsVolatile);
+  LoopBuilder.CreateAlignedStore(Load, DstGEP, PartDstAlign, DstIsVolatile);
 
   Value *NewIndex =
       LoopBuilder.CreateAdd(LoopIndex, ConstantInt::get(CopyLenType, 1U));
@@ -234,10 +236,11 @@ void llvm::createMemCpyLoopUnknownSize(Instruction *InsertBefore,
     Value *FullOffset = ResBuilder.CreateAdd(RuntimeBytesCopied, ResidualIndex);
     Value *SrcGEP =
         ResBuilder.CreateInBoundsGEP(Int8Type, SrcAsInt8, FullOffset);
-    Value *Load = ResBuilder.CreateLoad(Int8Type, SrcGEP, SrcIsVolatile);
+    Value *Load = ResBuilder.CreateAlignedLoad(Int8Type, SrcGEP, PartSrcAlign,
+                                               SrcIsVolatile);
     Value *DstGEP =
         ResBuilder.CreateInBoundsGEP(Int8Type, DstAsInt8, FullOffset);
-    ResBuilder.CreateStore(Load, DstGEP, DstIsVolatile);
+    ResBuilder.CreateAlignedStore(Load, DstGEP, PartDstAlign, DstIsVolatile);
 
     Value *ResNewIndex =
         ResBuilder.CreateAdd(ResidualIndex, ConstantInt::get(CopyLenType, 1U));
@@ -284,13 +287,14 @@ void llvm::createMemCpyLoopUnknownSize(Instruction *InsertBefore,
 //   }
 //   return dst;
 // }
-static void createMemMoveLoop(Instruction *InsertBefore,
-                              Value *SrcAddr, Value *DstAddr, Value *CopyLen,
-                              unsigned SrcAlign, unsigned DestAlign,
-                              bool SrcIsVolatile, bool DstIsVolatile) {
+static void createMemMoveLoop(Instruction *InsertBefore, Value *SrcAddr,
+                              Value *DstAddr, Value *CopyLen, unsigned SrcAlign,
+                              unsigned DstAlign, bool SrcIsVolatile,
+                              bool DstIsVolatile) {
   Type *TypeOfCopyLen = CopyLen->getType();
   BasicBlock *OrigBB = InsertBefore->getParent();
   Function *F = OrigBB->getParent();
+  const DataLayout &DL = F->getParent()->getDataLayout();
 
   Type *EltTy = cast<PointerType>(SrcAddr->getType())->getElementType();
 
@@ -318,6 +322,10 @@ static void createMemMoveLoop(Instruction *InsertBefore,
   BasicBlock *ExitBB = InsertBefore->getParent();
   ExitBB->setName("memmove_done");
 
+  unsigned PartSize = DL.getTypeStoreSize(EltTy);
+  Align PartSrcAlign(MinAlign(SrcAlign, PartSize));
+  Align PartDstAlign(MinAlign(DstAlign, PartSize));
+
   // Initial comparison of n == 0 that lets us skip the loops altogether. Shared
   // between both backwards and forward copy clauses.
   ICmpInst *CompareN =
@@ -331,11 +339,12 @@ static void createMemMoveLoop(Instruction *InsertBefore,
   PHINode *LoopPhi = LoopBuilder.CreatePHI(TypeOfCopyLen, 0);
   Value *IndexPtr = LoopBuilder.CreateSub(
       LoopPhi, ConstantInt::get(TypeOfCopyLen, 1), "index_ptr");
-  Value *Element = LoopBuilder.CreateLoad(
+  Value *Element = LoopBuilder.CreateAlignedLoad(
       EltTy, LoopBuilder.CreateInBoundsGEP(EltTy, SrcAddr, IndexPtr),
-      "element");
-  LoopBuilder.CreateStore(
-      Element, LoopBuilder.CreateInBoundsGEP(EltTy, DstAddr, IndexPtr));
+      PartSrcAlign, "element");
+  LoopBuilder.CreateAlignedStore(
+      Element, LoopBuilder.CreateInBoundsGEP(EltTy, DstAddr, IndexPtr),
+      PartDstAlign);
   LoopBuilder.CreateCondBr(
       LoopBuilder.CreateICmpEQ(IndexPtr, ConstantInt::get(TypeOfCopyLen, 0)),
       ExitBB, LoopBB);
@@ -349,11 +358,11 @@ static void createMemMoveLoop(Instruction *InsertBefore,
     BasicBlock::Create(F->getContext(), "copy_forward_loop", F, ExitBB);
   IRBuilder<> FwdLoopBuilder(FwdLoopBB);
   PHINode *FwdCopyPhi = FwdLoopBuilder.CreatePHI(TypeOfCopyLen, 0, "index_ptr");
-  Value *FwdElement = FwdLoopBuilder.CreateLoad(
-      EltTy, FwdLoopBuilder.CreateInBoundsGEP(EltTy, SrcAddr, FwdCopyPhi),
-      "element");
-  FwdLoopBuilder.CreateStore(
-      FwdElement, FwdLoopBuilder.CreateInBoundsGEP(EltTy, DstAddr, FwdCopyPhi));
+  Value *SrcGEP = FwdLoopBuilder.CreateInBoundsGEP(EltTy, SrcAddr, FwdCopyPhi);
+  Value *FwdElement =
+      FwdLoopBuilder.CreateAlignedLoad(EltTy, SrcGEP, PartSrcAlign, "element");
+  Value *DstGEP = FwdLoopBuilder.CreateInBoundsGEP(EltTy, DstAddr, FwdCopyPhi);
+  FwdLoopBuilder.CreateAlignedStore(FwdElement, DstGEP, PartDstAlign);
   Value *FwdIndexPtr = FwdLoopBuilder.CreateAdd(
       FwdCopyPhi, ConstantInt::get(TypeOfCopyLen, 1), "index_increment");
   FwdLoopBuilder.CreateCondBr(FwdLoopBuilder.CreateICmpEQ(FwdIndexPtr, CopyLen),
@@ -365,12 +374,13 @@ static void createMemMoveLoop(Instruction *InsertBefore,
   ElseTerm->eraseFromParent();
 }
 
-static void createMemSetLoop(Instruction *InsertBefore,
-                             Value *DstAddr, Value *CopyLen, Value *SetValue,
-                             unsigned Align, bool IsVolatile) {
+static void createMemSetLoop(Instruction *InsertBefore, Value *DstAddr,
+                             Value *CopyLen, Value *SetValue, unsigned DstAlign,
+                             bool IsVolatile) {
   Type *TypeOfCopyLen = CopyLen->getType();
   BasicBlock *OrigBB = InsertBefore->getParent();
   Function *F = OrigBB->getParent();
+  const DataLayout &DL = F->getParent()->getDataLayout();
   BasicBlock *NewBB =
       OrigBB->splitBasicBlock(InsertBefore, "split");
   BasicBlock *LoopBB
@@ -388,14 +398,17 @@ static void createMemSetLoop(Instruction *InsertBefore,
       LoopBB);
   OrigBB->getTerminator()->eraseFromParent();
 
+  unsigned PartSize = DL.getTypeStoreSize(SetValue->getType());
+  Align PartAlign(MinAlign(DstAlign, PartSize));
+
   IRBuilder<> LoopBuilder(LoopBB);
   PHINode *LoopIndex = LoopBuilder.CreatePHI(TypeOfCopyLen, 0);
   LoopIndex->addIncoming(ConstantInt::get(TypeOfCopyLen, 0), OrigBB);
 
-  LoopBuilder.CreateStore(
+  LoopBuilder.CreateAlignedStore(
       SetValue,
       LoopBuilder.CreateInBoundsGEP(SetValue->getType(), DstAddr, LoopIndex),
-      IsVolatile);
+      PartAlign, IsVolatile);
 
   Value *NewIndex =
       LoopBuilder.CreateAdd(LoopIndex, ConstantInt::get(TypeOfCopyLen, 1));
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index e411c4ece83d9..377aa78730b04 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -3131,7 +3131,7 @@ unsigned BoUpSLP::canMapToVector(Type *T, const DataLayout &DL) const {
   unsigned N = 1;
   Type *EltTy = T;
 
-  while (isa<CompositeType>(EltTy)) {
+  while (isa<StructType>(EltTy) || isa<SequentialType>(EltTy)) {
     if (auto *ST = dyn_cast<StructType>(EltTy)) {
       // Check that struct is homogeneous.
       for (const auto *Ty : ST->elements())
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 45be91baec8d9..19841edb1eeb7 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -404,8 +404,10 @@ void VPInstruction::print(raw_ostream &O) const {
 }
 
 void VPInstruction::print(raw_ostream &O, VPSlotTracker &SlotTracker) const {
-  printAsOperand(O, SlotTracker);
-  O << " = ";
+  if (hasResult()) {
+    printAsOperand(O, SlotTracker);
+    O << " = ";
+  }
 
   switch (getOpcode()) {
   case VPInstruction::Not:
@@ -814,11 +816,18 @@ void VPValue::replaceAllUsesWith(VPValue *New) {
 }
 
 void VPValue::printAsOperand(raw_ostream &OS, VPSlotTracker &Tracker) const {
+  if (const Value *UV = getUnderlyingValue()) {
+    OS << "ir<";
+    UV->printAsOperand(OS, false);
+    OS << ">";
+    return;
+  }
+
   unsigned Slot = Tracker.getSlot(this);
   if (Slot == unsigned(-1))
     OS << "<badref>";
   else
-    OS << "%vp" << Tracker.getSlot(this);
+    OS << "vp<%" << Tracker.getSlot(this) << ">";
 }
 
 void VPInterleavedAccessInfo::visitRegion(VPRegionBlock *Region,
@@ -869,6 +878,13 @@ VPInterleavedAccessInfo::VPInterleavedAccessInfo(VPlan &Plan,
 
 void VPSlotTracker::assignSlot(const VPValue *V) {
   assert(Slots.find(V) == Slots.end() && "VPValue already has a slot!");
+  const Value *UV = V->getUnderlyingValue();
+  if (UV)
+    return;
+  const auto *VPI = dyn_cast<VPInstruction>(V);
+  if (VPI && !VPI->hasResult())
+    return;
+
   Slots[V] = NextSlot++;
 }
 
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index 3cd4464c1efe5..17218e469af7f 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -735,6 +735,26 @@ class VPInstruction : public VPUser, public VPRecipeBase {
     return Opcode == Instruction::Store || Opcode == Instruction::Call ||
            Opcode == Instruction::Invoke || Opcode == SLPStore;
   }
+
+  bool hasResult() const {
+    // CallInst may or may not have a result, depending on the called function.
+    // Conservatively return calls have results for now.
+    switch (getOpcode()) {
+    case Instruction::Ret:
+    case Instruction::Br:
+    case Instruction::Store:
+    case Instruction::Switch:
+    case Instruction::IndirectBr:
+    case Instruction::Resume:
+    case Instruction::CatchRet:
+    case Instruction::Unreachable:
+    case Instruction::Fence:
+    case Instruction::AtomicRMW:
+      return false;
+    default:
+      return true;
+    }
+  }
 };
 
 /// VPWidenRecipe is a recipe for producing a copy of vector type for each
diff --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h b/llvm/lib/Transforms/Vectorize/VPlanValue.h
index 9004650fac84f..abaf4dc43015c 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanValue.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h
@@ -42,6 +42,7 @@ class VPValue {
   friend class VPlanTransforms;
   friend class VPBasicBlock;
   friend class VPInterleavedAccessInfo;
+  friend class VPSlotTracker;
 
 private:
   const unsigned char SubclassID; ///< Subclass identifier (for isa/dyn_cast).
@@ -64,6 +65,7 @@ class VPValue {
 
   /// Return the underlying Value attached to this VPValue.
   Value *getUnderlyingValue() { return UnderlyingVal; }
+  const Value *getUnderlyingValue() const { return UnderlyingVal; }
 
   // Set \p Val as the underlying Value of this VPValue.
   void setUnderlyingValue(Value *Val) {
diff --git a/llvm/test/Analysis/CostModel/ARM/select.ll b/llvm/test/Analysis/CostModel/ARM/select.ll
index c514581f86027..7851bdf2e4851 100644
--- a/llvm/test/Analysis/CostModel/ARM/select.ll
+++ b/llvm/test/Analysis/CostModel/ARM/select.ll
@@ -1,9 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
 ; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE
 ; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON
+; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1
 
-define void @casts() {
-; CHECK-MVE-LABEL: 'casts'
+define void @selects() {
+; CHECK-MVE-LABEL: 'selects'
 ; CHECK-MVE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef
 ; CHECK-MVE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef
 ; CHECK-MVE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef
@@ -34,7 +35,7 @@ define void @casts() {
 ; CHECK-MVE-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef
 ; CHECK-MVE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
-; CHECK-NEON-LABEL: 'casts'
+; CHECK-NEON-LABEL: 'selects'
 ; CHECK-NEON-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef
 ; CHECK-NEON-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef
 ; CHECK-NEON-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef
@@ -64,6 +65,37 @@ define void @casts() {
 ; CHECK-NEON-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef
 ; CHECK-NEON-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef
 ; CHECK-NEON-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-THUMB1-LABEL: 'selects'
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4 = select i1 undef, i64 undef, i64 undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v5 = select i1 undef, float undef, float undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v6 = select i1 undef, double undef, double undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef
+; CHECK-THUMB1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
   ; Scalar values
   %v1 = select i1 undef, i8 undef, i8 undef
diff --git a/llvm/test/Analysis/CostModel/X86/arith-fix.ll b/llvm/test/Analysis/CostModel/X86/arith-fix.ll
index 0f2917826f32e..c07ff0927e495 100644
--- a/llvm/test/Analysis/CostModel/X86/arith-fix.ll
+++ b/llvm/test/Analysis/CostModel/X86/arith-fix.ll
@@ -142,8 +142,8 @@ define i32 @smul(i32 %arg) {
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V32I16 = call <32 x i16> @llvm.smul.fix.v32i16(<32 x i16> undef, <32 x i16> undef, i32 3)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %I8 = call i8 @llvm.smul.fix.i8(i8 undef, i8 undef, i32 3)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V16I8 = call <16 x i8> @llvm.smul.fix.v16i8(<16 x i8> undef, <16 x i8> undef, i32 3)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call <32 x i8> @llvm.smul.fix.v32i8(<32 x i8> undef, <32 x i8> undef, i32 3)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %V64I8 = call <64 x i8> @llvm.smul.fix.v64i8(<64 x i8> undef, <64 x i8> undef, i32 3)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V32I8 = call <32 x i8> @llvm.smul.fix.v32i8(<32 x i8> undef, <32 x i8> undef, i32 3)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 19 for instruction: %V64I8 = call <64 x i8> @llvm.smul.fix.v64i8(<64 x i8> undef, <64 x i8> undef, i32 3)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
 ;
 ; AVX512DQ-LABEL: 'smul'
@@ -376,8 +376,8 @@ define i32 @umul(i32 %arg) {
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V32I16 = call <32 x i16> @llvm.umul.fix.v32i16(<32 x i16> undef, <32 x i16> undef, i32 3)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %I8 = call i8 @llvm.umul.fix.i8(i8 undef, i8 undef, i32 3)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V16I8 = call <16 x i8> @llvm.umul.fix.v16i8(<16 x i8> undef, <16 x i8> undef, i32 3)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call <32 x i8> @llvm.umul.fix.v32i8(<32 x i8> undef, <32 x i8> undef, i32 3)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %V64I8 = call <64 x i8> @llvm.umul.fix.v64i8(<64 x i8> undef, <64 x i8> undef, i32 3)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V32I8 = call <32 x i8> @llvm.umul.fix.v32i8(<32 x i8> undef, <32 x i8> undef, i32 3)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 19 for instruction: %V64I8 = call <64 x i8> @llvm.umul.fix.v64i8(<64 x i8> undef, <64 x i8> undef, i32 3)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
 ;
 ; AVX512DQ-LABEL: 'umul'
diff --git a/llvm/test/Analysis/CostModel/X86/arith-overflow.ll b/llvm/test/Analysis/CostModel/X86/arith-overflow.ll
index 6e1a0c256473f..a003f38171f82 100644
--- a/llvm/test/Analysis/CostModel/X86/arith-overflow.ll
+++ b/llvm/test/Analysis/CostModel/X86/arith-overflow.ll
@@ -1098,8 +1098,8 @@ define i32 @smul(i32 %arg) {
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 21 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
 ;
 ; AVX512DQ-LABEL: 'smul'
@@ -1336,8 +1336,8 @@ define i32 @umul(i32 %arg) {
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef)
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 13 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef)
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef)
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
 ;
 ; AVX512DQ-LABEL: 'umul'
diff --git a/llvm/test/Analysis/CostModel/X86/trunc.ll b/llvm/test/Analysis/CostModel/X86/trunc.ll
index 219ee007efb92..d91c817fd8373 100644
--- a/llvm/test/Analysis/CostModel/X86/trunc.ll
+++ b/llvm/test/Analysis/CostModel/X86/trunc.ll
@@ -317,8 +317,8 @@ define i32 @trunc_vXi8() {
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i8>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i8>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i8>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i8>
-; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i8>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i8>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i8>
 ; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
 ;
 ; BTVER2-LABEL: 'trunc_vXi8'
diff --git a/llvm/test/Analysis/MemorySSA/scalable-vec.ll b/llvm/test/Analysis/MemorySSA/scalable-vec.ll
new file mode 100644
index 0000000000000..23072876a2d72
--- /dev/null
+++ b/llvm/test/Analysis/MemorySSA/scalable-vec.ll
@@ -0,0 +1,25 @@
+; RUN: opt -basicaa -print-memoryssa -verify-memoryssa -analyze < %s 2>&1 | FileCheck %s
+; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>' -verify-memoryssa -disable-output < %s 2>&1 | FileCheck %s
+
+; CHECK-LABEL: define <vscale x 4 x i32> @f(
+; CHECK: 1 = MemoryDef(liveOnEntry)
+; CHECK: MemoryUse(1) MustAlias
+define <vscale x 4 x i32> @f(<vscale x 4 x i32> %z) {
+  %a = alloca <vscale x 4 x i32>
+  store <vscale x 4 x i32> %z, <vscale x 4 x i32>* %a
+  %zz = load <vscale x 4 x i32>, <vscale x 4 x i32>* %a
+  ret <vscale x 4 x i32> %zz
+}
+
+; CHECK-LABEL: define i32 @g(
+; CHECK: 1 = MemoryDef(liveOnEntry)
+; CHECK: MemoryUse(1) MayAlias
+declare i32* @gg(<vscale x 4 x i32>* %a)
+define i32 @g(i32 %z, i32 *%bb) {
+  %a = alloca <vscale x 4 x i32>
+  %aa = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i32 0, i32 0
+  store i32 %z, i32* %aa
+  %bbb = call i32* @gg(<vscale x 4 x i32>* %a) readnone
+  %zz = load i32, i32* %bbb
+  ret i32 %zz
+}
diff --git a/llvm/test/Analysis/StackSafetyAnalysis/ipa-attr.ll b/llvm/test/Analysis/StackSafetyAnalysis/ipa-attr.ll
new file mode 100644
index 0000000000000..0b2dbff53f006
--- /dev/null
+++ b/llvm/test/Analysis/StackSafetyAnalysis/ipa-attr.ll
@@ -0,0 +1,34 @@
+; RUN: llvm-as %s -o %t0.bc
+; RUN: llvm-as %S/Inputs/ipa.ll -o %t1.bc
+; RUN: llvm-link -disable-lazy-loading %t0.bc %t1.bc -o %t.combined.bc
+; RUN: opt -S -passes="stack-safety-annotator" %t.combined.bc -o - 2>&1 | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare void @Write1(i8* %p)
+declare void @Write8(i8* %p)
+
+; Basic out-of-bounds.
+define void @f1() {
+; CHECK-LABEL: define void @f1() {
+; CHECK: alloca i32, align 4{{$}}
+entry:
+  %x = alloca i32, align 4
+  %x1 = bitcast i32* %x to i8*
+  call void @Write8(i8* %x1)
+  ret void
+}
+
+; Basic in-bounds.
+define void @f2() {
+; CHECK-LABEL: define void @f2() {
+; CHECK: alloca i32, align 4, !stack-safe ![[A:[0-9]+]]{{$}}
+entry:
+  %x = alloca i32, align 4
+  %x1 = bitcast i32* %x to i8*
+  call void @Write1(i8* %x1)
+  ret void
+}
+
+; CHECK: ![[A]] = !{}
diff --git a/llvm/test/Analysis/ValueTracking/known-nonnull-at.ll b/llvm/test/Analysis/ValueTracking/known-nonnull-at.ll
index 06f4811837818..9df8c28551329 100644
--- a/llvm/test/Analysis/ValueTracking/known-nonnull-at.ll
+++ b/llvm/test/Analysis/ValueTracking/known-nonnull-at.ll
@@ -117,7 +117,7 @@ define i1 @nonnullReturnTest(i8* nonnull %x) {
 define i1 @unknownReturnTest(i8* %x) {
 ; CHECK-LABEL: @unknownReturnTest(
 ; CHECK-NEXT:    [[X2:%.*]] = call i8* @returningPtr(i8* [[X:%.*]])
-; CHECK-NEXT:    [[NULL_CHECK:%.*]] = icmp eq i8* [[X]], null
+; CHECK-NEXT:    [[NULL_CHECK:%.*]] = icmp eq i8* [[X2]], null
 ; CHECK-NEXT:    ret i1 [[NULL_CHECK]]
 ;
   %x2 = call i8* @returningPtr(i8* %x)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 661bd0d121e0b..418d09d01fd33 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -167,16 +167,6 @@ define void @nonpow2_load_narrowing() {
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:gpr64(s64), %{{[0-9]+}}:gpr(s1) = G_UADDE %{{[0-9]+}}:gpr, %{{[0-9]+}}:gpr, %{{[0-9]+}}:gpr (in function: nonpow2_store_narrowing)
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_store_narrowing
-; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_store_narrowing:
-define void @nonpow2_store_narrowing(i96* %c) {
-  %a = add i128 undef, undef
-  %b = trunc i128 %a to i96
-  store i96 %b, i96* %c
-  ret void
-}
-
 ; Currently can't handle vector lengths that aren't an exact multiple of
 ; natively supported vector lengths. Test that the fall-back works for those.
 ; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: <unknown>:0:0: unable to legalize instruction: %1:_(<7 x s64>) = G_ADD %0, %0 (in function: nonpow2_vector_add_fewerelements
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
index f384ad45ed27c..ba62b60ef7bde 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
@@ -8,9 +8,7 @@ body: |
 
     ; CHECK-LABEL: name: test_implicit_def
     ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF]](s64)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[MV]](s128)
-    ; CHECK: $x0 = COPY [[TRUNC]](s64)
+    ; CHECK: $x0 = COPY [[DEF]](s64)
     %0:_(s128) = G_IMPLICIT_DEF
     %1:_(s64) = G_TRUNC %0(s128)
     $x0 = COPY %1(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
new file mode 100644
index 0000000000000..2c5f12ac9d8dd
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
@@ -0,0 +1,168 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+name:            uitofp_to_zero
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: uitofp_to_zero
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK: $s0 = COPY [[C]](s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(s32) = G_IMPLICIT_DEF
+    %1:_(s32) = G_UITOFP %0(s32)
+    $s0 = COPY %1(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            sitofp_to_zero
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: sitofp_to_zero
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; CHECK: $s0 = COPY [[C]](s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(s32) = G_IMPLICIT_DEF
+    %1:_(s32) = G_SITOFP %0(s32)
+    $s0 = COPY %1(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            and_to_zero
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: and_to_zero
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: $w0 = COPY [[C]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_CONSTANT i32 10
+    %1:_(s32) = G_IMPLICIT_DEF
+    %2:_(s32) = G_AND %0, %1
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            mul_to_zero
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: mul_to_zero
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: $w0 = COPY [[C]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_CONSTANT i32 10
+    %1:_(s32) = G_IMPLICIT_DEF
+    %2:_(s32) = G_MUL %0, %1
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            or_to_negative_one
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: or_to_negative_one
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: $w0 = COPY [[C]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_CONSTANT i32 10
+    %1:_(s32) = G_IMPLICIT_DEF
+    %2:_(s32) = G_OR %0, %1
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            xor_to_undef
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: xor_to_undef
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $w0 = COPY [[DEF]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_CONSTANT i32 10
+    %1:_(s32) = G_IMPLICIT_DEF
+    %2:_(s32) = G_XOR %0, %1
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            add_to_undef
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: add_to_undef
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $w0 = COPY [[DEF]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_CONSTANT i32 10
+    %1:_(s32) = G_IMPLICIT_DEF
+    %2:_(s32) = G_ADD %0, %1
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            sub_to_undef
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: sub_to_undef
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $w0 = COPY [[DEF]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_CONSTANT i32 10
+    %1:_(s32) = G_IMPLICIT_DEF
+    %2:_(s32) = G_SUB %0, %1
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            fptoui_to_undef
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: fptoui_to_undef
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $w0 = COPY [[DEF]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_IMPLICIT_DEF
+    %1:_(s32) = G_FPTOUI %0(s32)
+    $w0 = COPY %1(s32)
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            fptosi_to_undef
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: fptosi_to_undef
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $w0 = COPY [[DEF]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(s32) = G_IMPLICIT_DEF
+    %1:_(s32) = G_FPTOSI %0(s32)
+    $w0 = COPY %1(s32)
+    RET_ReallyLR implicit $w0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/arm64-elf-calls.ll b/llvm/test/CodeGen/AArch64/arm64-elf-calls.ll
index 8c4020327b919..eb6655951878b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-elf-calls.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-elf-calls.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
+; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj -o - %s | llvm-objdump --triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
 
 declare void @callee()
 
diff --git a/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll b/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
index aa47aeb9db5b3..be52469ec55d9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -fast-isel-sink-local-values -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
 ; RUN: llc -fast-isel-sink-local-values -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST
 ; RUN: llc -fast-isel-sink-local-values -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -filetype=obj -o %t %s
-; RUN: llvm-objdump -triple arm64-apple-darwin -d %t | FileCheck %s --check-prefix CHECK-ENCODING
+; RUN: llvm-objdump --triple=arm64-apple-darwin -d %t | FileCheck %s --check-prefix=CHECK-ENCODING
 
 ; CHECK-ENCODING-NOT: <unknown>
 ; CHECK-ENCODING: mov x16, #281470681743360
diff --git a/llvm/test/CodeGen/AArch64/arm64-simplest-elf.ll b/llvm/test/CodeGen/AArch64/arm64-simplest-elf.ll
index 2d6863d129d08..be8f53f47dd89 100644
--- a/llvm/test/CodeGen/AArch64/arm64-simplest-elf.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-simplest-elf.ll
@@ -11,7 +11,7 @@ define void @foo() nounwind {
 
   ; Similarly make sure ELF output works and is vaguely sane: aarch64 target
   ; machine with correct section & symbol names.
-; CHECK-ELF: file format elf64-aarch64
+; CHECK-ELF: file format elf64-littleaarch64
 
 ; CHECK-ELF: Disassembly of section .text
 ; CHECK-ELF-LABEL: <foo>:
diff --git a/llvm/test/CodeGen/AArch64/arm64_32.ll b/llvm/test/CodeGen/AArch64/arm64_32.ll
index c30f651f926f4..f129c463b126b 100644
--- a/llvm/test/CodeGen/AArch64/arm64_32.ll
+++ b/llvm/test/CodeGen/AArch64/arm64_32.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -filetype=obj -o - -disable-post-ra -frame-pointer=non-leaf | \
-; RUN:     llvm-objdump -private-headers - | \
+; RUN:     llvm-objdump --private-headers - | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-MACHO
 ; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -o - -aarch64-enable-atomic-cfg-tidy=0 -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OPT
 ; RUN: llc -mtriple=arm64_32-apple-ios7.0 %s -o - -fast-isel -aarch64-enable-atomic-cfg-tidy=0 -disable-post-ra -frame-pointer=non-leaf | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FAST
diff --git a/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll b/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
index da42b1d6863cd..a7d08565c4c4c 100644
--- a/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
+++ b/llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
@@ -4,13 +4,28 @@
 declare i32 @bcmp(i8*, i8*, i64) nounwind readonly
 declare i32 @memcmp(i8*, i8*, i64) nounwind readonly
 
-define i1 @bcmp_b2(i8* %s1, i8* %s2) {
+define i1 @test_b2(i8* %s1, i8* %s2) {
 entry:
   %bcmp = call i32 @bcmp(i8* %s1, i8* %s2, i64 15)
   %ret = icmp eq i32 %bcmp, 0
   ret i1 %ret
 
-; CHECK-LABEL: bcmp_b2:
+; CHECK-LABEL: test_b2:
+; CHECK-NOT:   bl bcmp
+; CHECKN:      ldr  x
+; CHECKN-NEXT: ldr  x
+; CHECKN-NEXT: ldur x
+; CHECKN-NEXT: ldur x
+; CHECKS-COUNT-30: ldrb w
+}
+
+define i1 @test_b2_align8(i8* align 8 %s1, i8* align 8 %s2) {
+entry:
+  %bcmp = call i32 @bcmp(i8* %s1, i8* %s2, i64 15)
+  %ret = icmp eq i32 %bcmp, 0
+  ret i1 %ret
+
+; CHECK-LABEL: test_b2_align8:
 ; CHECK-NOT:   bl bcmp
 ; CHECKN:      ldr  x
 ; CHECKN-NEXT: ldr  x
@@ -20,19 +35,19 @@ entry:
 ; CHECKS-NEXT: ldr  x
 ; CHECKS-NEXT: ldr  w
 ; CHECKS-NEXT: ldr  w
-; CHECKS-NEXT: ldrh w
-; CHECKS-NEXT: ldrh w
-; CHECKS-NEXT: ldrb w
-; CHECKS-NEXT: ldrb w
+; CHECKS-NEXT: ldrh  w
+; CHECKS-NEXT: ldrh  w
+; CHECKS-NEXT: ldrb  w
+; CHECKS-NEXT: ldrb  w
 }
 
-define i1 @bcmp_bs(i8* %s1, i8* %s2) optsize {
+define i1 @test_bs(i8* %s1, i8* %s2) optsize {
 entry:
   %memcmp = call i32 @memcmp(i8* %s1, i8* %s2, i64 31)
   %ret = icmp eq i32 %memcmp, 0
   ret i1 %ret
 
-; CHECK-LABEL: bcmp_bs:
+; CHECK-LABEL: test_bs:
 ; CHECKN-NOT:  bl memcmp
 ; CHECKN:      ldp  x
 ; CHECKN-NEXT: ldp  x
diff --git a/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll b/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
index 21f3895154c74..94e40052f9c9c 100644
--- a/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -disassemble - | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
 
 ; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one
 ; point, in the edge case where lsb = 0. Just make sure.
diff --git a/llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll b/llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
index 13ca2f7571769..c3395033c7fd9 100644
--- a/llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
+++ b/llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -filetype=obj -o - \
-; RUN:  | llvm-objdump -triple aarch64-unknown-linux-gnu -d - \
+; RUN:  | llvm-objdump --triple=aarch64-unknown-linux-gnu -d - \
 ; RUN:  | FileCheck %s
 
 %struct.c = type { i1 (...)* }
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll b/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
index 4d238282a6722..6777fecbb5d5a 100644
--- a/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
@@ -65,7 +65,7 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
 define i64 @rotl_i64(i64 %x, i64 %z) {
 ; CHECK-LABEL: rotl_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    neg x8, x1
+; CHECK-NEXT:    neg w8, w1
 ; CHECK-NEXT:    ror x0, x0, x8
 ; CHECK-NEXT:    ret
   %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
diff --git a/llvm/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll b/llvm/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll
index afd367b22f6ed..0fa051f3027b6 100644
--- a/llvm/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll
+++ b/llvm/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll
@@ -2,7 +2,7 @@
 ; assembly, the current code path will bypass the parser and just write the
 ; raw text out to the Streamer. We need to actually parse the inlineasm to
 ; demonstrate the bug. Going the asm->obj route does not show the issue.
-; RUN: llc -mtriple=aarch64   < %s -filetype=obj | llvm-objdump -arch=aarch64 -d - | FileCheck %s
+; RUN: llc -mtriple=aarch64   < %s -filetype=obj | llvm-objdump --arch=aarch64 -d - | FileCheck %s
 
 ; CHECK-LABEL: <foo>:
 ; CHECK:       a0 79 95 d2   mov x0, #43981
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-iterative.mir b/llvm/test/CodeGen/AArch64/machine-outliner-iterative.mir
new file mode 100644
index 0000000000000..08aa043f5c683
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-iterative.mir
@@ -0,0 +1,149 @@
+# RUN: llc -mtriple=aarch64 -run-pass=machine-outliner -machine-outline-runs=2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix TWO-RUNS
+# RUN: llc -mtriple=aarch64 -run-pass=machine-outliner -machine-outline-runs=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix ONE-RUN
+# RUN: llc -mtriple=aarch64 -run-pass=machine-outliner -machine-outline-runs=4 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix FOUR-RUNS
+
+# Example of Repeated Instruction Sequence - Iterative Machine Outlining
+#
+#; define void @"$s12"(...) {         define i64 @"$s5” (...) {             define void @"$s13"(...) {
+#   ...                                ...                                   ...
+#   %8 = load i1, i1* %7                                                     %8 = load i1, i1* %7
+#   %9 = load i4, i4*, %6              %9 = load i4, i4*, %6                 %9 = load i4, i4*, %6
+#   store i4 %9, i4* %5                store i4 %9, i4* %5                   store i4 %9, i4* %5
+#   ...                                ...                                   ...
+# }                                  }                                     }
+#
+# After machine outliner (1st time)
+#
+# define void @"$s12"(...) {         define i64 @"$s5” (...) {             define void @"$s13"(...) {
+#   ...                                ...                                   ...
+#   %8 = load i1, i1* %7                                                     %8 = load i1, i1* %7
+#   call void @outlined_function_1_1   call void @outlined_function_1_1      call void @outlined_function_1_1
+#   ...                                ...                                   ...
+# }                                  }                                     }
+#
+# After machine outliner (2nd time)
+#
+# define void @"$s12"(...) {         define i64 @"$s5” (...) {             define void @"$s13"(...) {
+#   ...                                ...                                   ...
+#   call void @outlined_function_2_1   call void @outlined_function_1_1      call void @outlined_function_2_1
+#   ...                                ...                                   ...
+# }                                  }                                     }
+#
+# Check whether machine outliner can further find the outlining opportunity after machine
+# outlining has performed.
+#
+--- |
+  declare void @foo() local_unnamed_addr
+
+  declare void @widget() local_unnamed_addr
+
+  ; Function Attrs: minsize noredzone optsize
+  define void @baz.14() #0 {
+    ret void
+  }
+
+  ; Function Attrs: minsize noredzone optsize
+  define void @baz.15() #0 {
+    ret void
+  }
+
+  ; Function Attrs: minsize noredzone optsize
+  define void @baz.16() #0 {
+    ret void
+  }
+
+  attributes #0 = { minsize noredzone optsize }
+...
+---
+name:            baz.14
+tracksRegLiveness: true
+stack:
+  - { id: 0, offset: -8, size: 8 }
+  - { id: 1, offset: -16, size: 8 }
+body:             |
+  bb.0:
+    liveins: $x0, $x19, $lr
+
+    early-clobber $sp = frame-setup STPXpre killed $lr, killed $x19, $sp, -2 :: (store 8 into %stack.1), (store 8 into %stack.0)
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup CFI_INSTRUCTION offset $w19, -8
+    frame-setup CFI_INSTRUCTION offset $w30, -16
+    renamable $x19 = COPY $x0
+    renamable $x0 = nuw ADDXri $x0, 48, 0
+    $x1 = ADDXri $sp, 0, 0
+    dead $w2 = MOVi32imm 33, implicit-def $x2
+    $x3 = COPY $xzr
+    BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit killed $x2, implicit killed $x3, implicit-def $sp
+    $x0 = COPY killed renamable $x19
+    BL @widget, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+    early-clobber $sp, $lr, $x19 = frame-destroy LDPXpost $sp, 2 :: (load 8 from %stack.1), (load 8 from %stack.0)
+    RET_ReallyLR
+
+...
+---
+name:            baz.15
+tracksRegLiveness: true
+stack:
+  - { id: 0, offset: -8, size: 8 }
+  - { id: 1, offset: -16, size: 8 }
+body:             |
+  bb.0:
+    liveins: $x0, $x19, $lr
+
+    early-clobber $sp = frame-setup STPXpre killed $lr, killed $x19, $sp, -2 :: (store 8 into %stack.1), (store 8 into %stack.0)
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup CFI_INSTRUCTION offset $w19, -8
+    frame-setup CFI_INSTRUCTION offset $w30, -16
+    renamable $x19 = COPY $x0
+    renamable $x0 = nuw ADDXri killed renamable $x0, 16, 0
+    $x1 = ADDXri $sp, 0, 0
+    dead $w2 = MOVi32imm 33, implicit-def $x2
+    $x3 = COPY $xzr
+    BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $x1, implicit killed $x2, implicit killed $x3, implicit-def $sp
+    $x0 = COPY killed renamable $x19
+    BL @widget, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+    early-clobber $sp, $lr, $x19 = frame-destroy LDPXpost $sp, 2 :: (load 8 from %stack.1), (load 8 from %stack.0)
+    RET_ReallyLR
+
+...
+---
+name:            baz.16
+tracksRegLiveness: true
+stack:
+  - { id: 0, offset: -8, size: 8 }
+  - { id: 1, offset: -16, size: 8 }
+body:             |
+  bb.0:
+    liveins: $x0, $x19, $lr
+
+    early-clobber $sp = frame-setup STPXpre killed $lr, killed $x19, $sp, -2 :: (store 8 into %stack.1), (store 8 into %stack.0)
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup CFI_INSTRUCTION offset $w19, -8
+    frame-setup CFI_INSTRUCTION offset $w30, -16
+    renamable $x19 = COPY $x0
+    renamable $x0 = nuw ADDXri $x0, 48, 0
+    $x1 = ADDXri $sp, 0, 0
+    dead $w2 = MOVi32imm 33, implicit-def $x2
+    $x3 = COPY $xzr
+    BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit killed $x2, implicit killed $x3, implicit-def $sp
+    $x0 = COPY killed renamable $x19
+    BL @widget, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+    early-clobber $sp, $lr, $x19 = frame-destroy LDPXpost $sp, 2 :: (load 8 from %stack.1), (load 8 from %stack.0)
+    RET_ReallyLR
+
+...
+
+# TWO-RUNS: name:            OUTLINED_FUNCTION_2_0
+# TWO-RUNS-DAG: bb.0:
+# TWO-RUNS-DAG: renamable $x19 = COPY $x0
+# TWO-RUNS-NEXT: renamable $x0 = nuw ADDXri $x0, 48, 0
+# TWO-RUNS-NEXT: TCRETURNdi @OUTLINED_FUNCTION_0, 0, implicit $sp
+#
+# The machine outliner is expected to stop at the 1st iteration for case ONE-RUN
+# since machine-outline-runs is specified as 1.
+# ONE-RUN-NOT: [[OUTLINED:OUTLINED_FUNCTION_2_[0-9]+]]
+#
+# The machine outliner is expected to stop at the 3rd iteration for case FOUR-RUNS
+# since the MIR has no change at the 3rd iteration.
+# FOUR-RUNS-NOT: [[OUTLINED:OUTLINED_FUNCTION_3_[0-9]+]]
+# FOUR-RUNS-NOT: [[OUTLINED:OUTLINED_FUNCTION_4_[0-9]+]]
diff --git a/llvm/test/CodeGen/AArch64/simple-macho.ll b/llvm/test/CodeGen/AArch64/simple-macho.ll
index 2c2ad8a7a698d..e89f529884d13 100644
--- a/llvm/test/CodeGen/AArch64/simple-macho.ll
+++ b/llvm/test/CodeGen/AArch64/simple-macho.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=arm64-macho -o - %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-macho -filetype=obj -o %t %s
-; RUN: llvm-objdump -triple=arm64-macho -d %t | FileCheck --check-prefix=CHECK-OBJ %s
+; RUN: llvm-objdump --triple=arm64-macho -d %t | FileCheck --check-prefix=CHECK-OBJ %s
 
 define void @foo() {
 ; CHECK-LABEL: _foo:
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging.ll b/llvm/test/CodeGen/AArch64/stack-tagging.ll
index 244a0a1edbb25..feaa5de24c524 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging.ll
@@ -33,6 +33,7 @@ entry:
   %x1 = alloca i32, align 4
   %x2 = alloca i8, align 4
   %x3 = alloca i32, i32 11, align 4
+  %x4 = alloca i32, align 4, !stack-safe !0
   call void @use32(i32* %x1)
   call void @use8(i8* %x2)
   call void @use32(i32* %x3)
@@ -49,6 +50,9 @@ entry:
 ; CHECK:  alloca { [11 x i32], [4 x i8] }, align 16
 ; CHECK:  call { [11 x i32], [4 x i8] }* @llvm.aarch64.tagp.{{.*}}({ [11 x i32], [4 x i8] }* {{.*}}, i64 2)
 ; CHECK:  call void @llvm.aarch64.settag(i8* {{.*}}, i64 48)
+; CHECK:  alloca i32, align 4
+; CHECK-NOT: @llvm.aarch64.tagp
+; CHECK-NOT: @llvm.aarch64.settag
 
 ; CHECK:  call void @use32(
 ; CHECK:  call void @use8(
@@ -185,3 +189,5 @@ another_bb:
 ; CHECK: call void @llvm.aarch64.settag(
 ; CHECK: call void @llvm.aarch64.settag(
 ; CHECK: ret void
+
+!0 = !{}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scaled-offset.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scaled-offset.ll
new file mode 100644
index 0000000000000..78251707a0105
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scaled-offset.ll
@@ -0,0 +1,200 @@
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s | FileCheck %s
+
+; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]    -> 32-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfb_scaled_uxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_scaled_uxtw_nx4vi32:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x0, z0.s, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfb_scaled_sxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_scaled_sxtw_nx4vi32:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x0, z0.s, sxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]    -> 32-bit unpacked scaled offset
+
+define void @llvm_aarch64_sve_gather_prfb_scaled_uxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_scaled_uxtw_nx2vi64:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x0, z0.d, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfb_scaled_sxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_scaled_sxtw_nx2vi64:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x0, z0.d, sxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]           -> 64-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfb_scaled_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_scaled_nx2vi64:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x0, z0.d]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 1)
+  ret void
+ }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]    -> 32-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfh_scaled_uxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_scaled_uxtw_nx4vi32:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x0, z0.s, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfh_scaled_sxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_scaled_sxtw_nx4vi32:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x0, z0.s, sxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1] -> 32-bit unpacked scaled offset
+define void @llvm_aarch64_sve_gather_prfh_scaled_uxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_scaled_uxtw_nx2vi64:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x0, z0.d, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfh_scaled_sxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_scaled_sxtw_nx2vi64:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x0, z0.d, sxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]           -> 64-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfh_scaled_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_scaled_nx2vi64:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x0, z0.d, lsl #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 1)
+  ret void
+ }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]    -> 32-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfw_scaled_uxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_scaled_uxtw_nx4vi32:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x0, z0.s, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfw_scaled_sxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_scaled_sxtw_nx4vi32:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x0, z0.s, sxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2] -> 32-bit unpacked scaled offset
+define void @llvm_aarch64_sve_gather_prfw_scaled_uxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_scaled_uxtw_nx2vi64:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x0, z0.d, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfw_scaled_sxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_scaled_sxtw_nx2vi64:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x0, z0.d, sxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]           -> 64-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfw_scaled_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_scaled_nx2vi64:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x0, z0.d, lsl #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 1)
+  ret void
+ }
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]    -> 32-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfd_scaled_uxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_scaled_uxtw_nx4vi32:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x0, z0.s, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfd_scaled_sxtw_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_scaled_sxtw_nx4vi32:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x0, z0.s, sxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3] -> 32-bit unpacked scaled offset
+define void @llvm_aarch64_sve_gather_prfd_scaled_uxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_scaled_uxtw_nx2vi64:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x0, z0.d, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+define void @llvm_aarch64_sve_gather_prfd_scaled_sxtw_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_scaled_sxtw_nx2vi64:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x0, z0.d, sxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 1)
+  ret void
+ }
+
+; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]           -> 64-bit          scaled offset
+define void @llvm_aarch64_sve_gather_prfd_scaled_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_scaled_nx2vi64:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x0, z0.d, lsl #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 1)
+  ret void
+ }
+
+declare void @llvm.aarch64.sve.gather.prfb.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfb.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfb.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfb.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfb.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.scaled.uxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.scaled.sxtw.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vscale x 4 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.scaled.uxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.scaled.sxtw.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i32> %offset, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.scaled.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vscale x 2 x i64> %offset, i32 %prfop)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll
new file mode 100644
index 0000000000000..481302ce59720
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll
@@ -0,0 +1,82 @@
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s | FileCheck %s
+
+; PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
+define void @llvm_aarch64_sve_gather_prfb_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx4vi32:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [z0.s, #7]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 7, i32 1)
+  ret void
+}
+
+; PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
+define void @llvm_aarch64_sve_gather_prfb_nx2vi64(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx2vi64:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [z0.d, #7]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 7, i32 1)
+  ret void
+}
+
+; PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
+define void @llvm_aarch64_sve_gather_prfh_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx4vi32:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [z0.s, #6]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 6, i32 1)
+  ret void
+}
+
+; PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
+define void @llvm_aarch64_sve_gather_prfh_nx2vi64(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx2vi64:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [z0.d, #6]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 6, i32 1)
+  ret void
+}
+
+; PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
+define void @llvm_aarch64_sve_gather_prfw_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx4vi32:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [z0.s, #12]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 12, i32 1)
+  ret void
+}
+
+; PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
+define void @llvm_aarch64_sve_gather_prfw_nx2vi64(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx2vi64:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [z0.d, #12]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 12, i32 1)
+  ret void
+}
+
+; PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
+define void @llvm_aarch64_sve_gather_prfd_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx4vi32:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [z0.s, #16]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 16, i32 1)
+  ret void
+}
+
+; PRFD <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
+define void @llvm_aarch64_sve_gather_prfd_nx2vi64(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx2vi64:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [z0.d, #16]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 16, i32 1)
+  ret void
+}
+
+declare void @llvm.aarch64.sve.gather.prfb.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfb.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll
new file mode 100644
index 0000000000000..4b0b42eb73b98
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll
@@ -0,0 +1,286 @@
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s | FileCheck %s
+
+; PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 1, ..., 31
+define void @llvm_aarch64_sve_gather_prfb_nx4vi32_runtime_offset(<vscale x 4 x i32> %bases, i64 %imm, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx4vi32_runtime_offset:
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x0, z0.s, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfb_nx4vi32_invalid_immediate_offset_upper_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx4vi32_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #32
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x[[N]], z0.s, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 32, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfb_nx4vi32_invalid_immediate_offset_lower_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx4vi32_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 -1, i32 1)
+  ret void
+}
+
+; PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 1, ..., 31
+define void @llvm_aarch64_sve_gather_prfb_nx2vi64_runtime_offset(<vscale x 2 x i64> %bases, i64 %imm, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx2vi64_runtime_offset:
+; CHECK-NEXT:   prfb pldl1strm, p0, [x0, z0.d, uxtw]
+; CHECK-NEXT:   ret
+  call void @llvm.aarch64.sve.gather.prfb.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfb_nx2vi64_invalid_immediate_offset_upper_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx2vi64_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #32
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x[[N]], z0.d, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 32, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfb_nx2vi64_invalid_immediate_offset_lower_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfb_nx2vi64_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfb  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfb.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 -1, i32 1)
+  ret void
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 2, ..., 62
+define void @llvm_aarch64_sve_gather_prfh_nx4vi32_runtime_offset(<vscale x 4 x i32> %bases, i64 %imm, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx4vi32_runtime_offset:
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x0, z0.s, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfh_nx4vi32_invalid_immediate_offset_upper_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx4vi32_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #63
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x[[N]], z0.s, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 63, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfh_nx4vi32_invalid_immediate_offset_lower_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx4vi32_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 -1, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfh_nx4vi32_invalid_immediate_offset_inbound_not_multiple_of_2(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx4vi32_invalid_immediate_offset_inbound_not_multiple_of_2:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #33
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 33, i32 1)
+  ret void
+}
+
+; PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 2, ..., 62
+define void @llvm_aarch64_sve_gather_prfh_nx2vi64_runtime_offset(<vscale x 2 x i64> %bases, i64 %imm, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx2vi64_runtime_offset:
+; CHECK-NEXT:   prfh pldl1strm, p0, [x0, z0.d, uxtw #1]
+; CHECK-NEXT:   ret
+  call void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfh_nx2vi64_invalid_immediate_offset_upper_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx2vi64_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #63
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x[[N]], z0.d, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 63, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfh_nx2vi64_invalid_immediate_offset_lower_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx2vi64_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 -1, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfh_nx2vi64_invalid_immediate_offset_inbound_not_multiple_of_2(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfh_nx2vi64_invalid_immediate_offset_inbound_not_multiple_of_2:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #33
+; CHECK-NEXT:  prfh  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw #1]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 33, i32 1)
+  ret void
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 4, ..., 124
+define void @llvm_aarch64_sve_gather_prfw_nx4vi32_runtime_offset(<vscale x 4 x i32> %bases, i64 %imm, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx4vi32_runtime_offset:
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x0, z0.s, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfw_nx4vi32_invalid_immediate_offset_upper_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx4vi32_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #125
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x[[N]], z0.s, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 125, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfw_nx4vi32_invalid_immediate_offset_lower_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx4vi32_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 -1, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfw_nx4vi32_invalid_immediate_offset_inbound_not_multiple_of_4(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx4vi32_invalid_immediate_offset_inbound_not_multiple_of_4:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #33
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 33, i32 1)
+  ret void
+}
+
+; PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 4, ..., 124
+define void @llvm_aarch64_sve_gather_prfw_nx2vi64_runtime_offset(<vscale x 2 x i64> %bases, i64 %imm, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx2vi64_runtime_offset:
+; CHECK-NEXT:   prfw pldl1strm, p0, [x0, z0.d, uxtw #2]
+; CHECK-NEXT:   ret
+  call void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfw_nx2vi64_invalid_immediate_offset_upper_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx2vi64_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #125
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x[[N]], z0.d, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 125, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfw_nx2vi64_invalid_immediate_offset_lower_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx2vi64_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 -1, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfw_nx2vi64_invalid_immediate_offset_inbound_not_multiple_of_4(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfw_nx2vi64_invalid_immediate_offset_inbound_not_multiple_of_4:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #33
+; CHECK-NEXT:  prfw  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw #2]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 33, i32 1)
+  ret void
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 8, ..., 248
+define void @llvm_aarch64_sve_gather_prfd_nx4vi32_runtime_offset(<vscale x 4 x i32> %bases, i64 %imm, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx4vi32_runtime_offset:
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x0, z0.s, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfd_nx4vi32_invalid_immediate_offset_upper_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx4vi32_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #125
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x[[N]], z0.s, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 125, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfd_nx4vi32_invalid_immediate_offset_lower_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx4vi32_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 -1, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfd_nx4vi32_invalid_immediate_offset_inbound_not_multiple_of_8(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx4vi32_invalid_immediate_offset_inbound_not_multiple_of_8:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #33
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x[[N:[0-9]+]], z0.s, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 33, i32 1)
+  ret void
+}
+
+; PRFD <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 4, ..., 248
+define void @llvm_aarch64_sve_gather_prfd_nx2vi64_runtime_offset(<vscale x 2 x i64> %bases, i64 %imm, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx2vi64_runtime_offset:
+; CHECK-NEXT:   prfd pldl1strm, p0, [x0, z0.d, uxtw #3]
+; CHECK-NEXT:   ret
+  call void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfd_nx2vi64_invalid_immediate_offset_upper_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx2vi64_invalid_immediate_offset_upper_bound:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #125
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x[[N]], z0.d, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 125, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfd_nx2vi64_invalid_immediate_offset_lower_bound(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx2vi64_invalid_immediate_offset_lower_bound:
+; CHECK-NEXT:  mov   x[[N:[0-9]+]], #-1
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 -1, i32 1)
+  ret void
+}
+
+define void @llvm_aarch64_sve_gather_prfd_nx2vi64_invalid_immediate_offset_inbound_not_multiple_of_8(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
+; CHECK-LABEL: llvm_aarch64_sve_gather_prfd_nx2vi64_invalid_immediate_offset_inbound_not_multiple_of_8:
+; CHECK-NEXT:  mov   w[[N:[0-9]+]], #33
+; CHECK-NEXT:  prfd  pldl1strm, p0, [x[[N:[0-9]+]], z0.d, uxtw #3]
+; CHECK-NEXT:  ret
+  call void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 33, i32 1)
+  ret void
+}
+
+declare void @llvm.aarch64.sve.gather.prfb.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfb.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfh.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfw.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> %bases, i64 %imm, i32 %prfop)
+declare void @llvm.aarch64.sve.gather.prfd.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> %bases, i64 %imm, i32 %prfop)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
index 801cf42962824..a27faf3a7220b 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
@@ -12,6 +12,15 @@ define <vscale x 16 x i8> @ldff1b(<vscale x 16 x i1> %pg, i8* %a) {
   ret <vscale x 16 x i8> %load
 }
 
+define <vscale x 16 x i8> @ldff1b_reg(<vscale x 16 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1b_reg:
+; CHECK: ldff1b { z0.b }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
+  ret <vscale x 16 x i8> %load
+}
+
 define <vscale x 8 x i16> @ldff1b_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldff1b_h:
 ; CHECK: ldff1b { z0.h }, p0/z, [x0]
@@ -21,6 +30,16 @@ define <vscale x 8 x i16> @ldff1b_h(<vscale x 8 x i1> %pg, i8* %a) {
   ret <vscale x 8 x i16> %res
 }
 
+define <vscale x 8 x i16> @ldff1b_h_reg(<vscale x 8 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1b_h_reg:
+; CHECK: ldff1b { z0.h }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8(<vscale x 8 x i1> %pg, i8* %base)
+  %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %res
+}
+
 define <vscale x 4 x i32> @ldff1b_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldff1b_s:
 ; CHECK: ldff1b { z0.s }, p0/z, [x0]
@@ -30,6 +49,16 @@ define <vscale x 4 x i32> @ldff1b_s(<vscale x 4 x i1> %pg, i8* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldff1b_s_reg(<vscale x 4 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1b_s_reg:
+; CHECK: ldff1b { z0.s }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8(<vscale x 4 x i1> %pg, i8* %base)
+  %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 2 x i64> @ldff1b_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldff1b_d:
 ; CHECK: ldff1b { z0.d }, p0/z, [x0]
@@ -39,6 +68,16 @@ define <vscale x 2 x i64> @ldff1b_d(<vscale x 2 x i1> %pg, i8* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldff1b_d_reg(<vscale x 2 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1b_d_reg:
+; CHECK: ldff1b { z0.d }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8(<vscale x 2 x i1> %pg, i8* %base)
+  %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 ;
 ; LDFF1SB
 ;
@@ -52,6 +91,16 @@ define <vscale x 8 x i16> @ldff1sb_h(<vscale x 8 x i1> %pg, i8* %a) {
   ret <vscale x 8 x i16> %res
 }
 
+define <vscale x 8 x i16> @ldff1sb_h_reg(<vscale x 8 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1sb_h_reg:
+; CHECK: ldff1sb { z0.h }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8(<vscale x 8 x i1> %pg, i8* %base)
+  %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %res
+}
+
 define <vscale x 4 x i32> @ldff1sb_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldff1sb_s:
 ; CHECK: ldff1sb { z0.s }, p0/z, [x0]
@@ -61,6 +110,16 @@ define <vscale x 4 x i32> @ldff1sb_s(<vscale x 4 x i1> %pg, i8* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldff1sb_s_reg(<vscale x 4 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1sb_s_reg:
+; CHECK: ldff1sb { z0.s }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8(<vscale x 4 x i1> %pg, i8* %base)
+  %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 2 x i64> @ldff1sb_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldff1sb_d:
 ; CHECK: ldff1sb { z0.d }, p0/z, [x0]
@@ -70,6 +129,16 @@ define <vscale x 2 x i64> @ldff1sb_d(<vscale x 2 x i1> %pg, i8* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldff1sb_d_reg(<vscale x 2 x i1> %pg, i8* %a, i64 %offset) {
+; CHECK-LABEL: ldff1sb_d_reg:
+; CHECK: ldff1sb { z0.d }, p0/z, [x0, x1]
+; CHECK-NEXT: ret
+  %base = getelementptr i8, i8* %a, i64 %offset
+  %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8(<vscale x 2 x i1> %pg, i8* %base)
+  %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 ;
 ; LDFF1H
 ;
@@ -82,6 +151,15 @@ define <vscale x 8 x i16> @ldff1h(<vscale x 8 x i1> %pg, i16* %a) {
   ret <vscale x 8 x i16> %load
 }
 
+define <vscale x 8 x i16> @ldff1h_reg(<vscale x 8 x i1> %pg, i16* %a, i64 %offset) {
+; CHECK-LABEL: ldff1h_reg:
+; CHECK: ldff1h { z0.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT: ret
+  %base = getelementptr i16, i16* %a, i64 %offset
+  %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16(<vscale x 8 x i1> %pg, i16* %base)
+  ret <vscale x 8 x i16> %load
+}
+
 define <vscale x 4 x i32> @ldff1h_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldff1h_s:
 ; CHECK: ldff1h { z0.s }, p0/z, [x0]
@@ -91,6 +169,16 @@ define <vscale x 4 x i32> @ldff1h_s(<vscale x 4 x i1> %pg, i16* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldff1h_s_reg(<vscale x 4 x i1> %pg, i16* %a, i64 %offset) {
+; CHECK-LABEL: ldff1h_s_reg:
+; CHECK: ldff1h { z0.s }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT: ret
+  %base = getelementptr i16, i16* %a, i64 %offset
+  %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16(<vscale x 4 x i1> %pg, i16* %base)
+  %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 2 x i64> @ldff1h_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldff1h_d:
 ; CHECK: ldff1h { z0.d }, p0/z, [x0]
@@ -100,6 +188,16 @@ define <vscale x 2 x i64> @ldff1h_d(<vscale x 2 x i1> %pg, i16* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldff1h_d_reg(<vscale x 2 x i1> %pg, i16* %a, i64 %offset) {
+; CHECK-LABEL: ldff1h_d_reg:
+; CHECK: ldff1h { z0.d }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT: ret
+  %base = getelementptr i16, i16* %a, i64 %offset
+  %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16(<vscale x 2 x i1> %pg, i16* %base)
+  %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 8 x half> @ldff1h_f16(<vscale x 8 x i1> %pg, half* %a) {
 ; CHECK-LABEL: ldff1h_f16:
 ; CHECK: ldff1h { z0.h }, p0/z, [x0]
@@ -108,6 +206,15 @@ define <vscale x 8 x half> @ldff1h_f16(<vscale x 8 x i1> %pg, half* %a) {
   ret <vscale x 8 x half> %load
 }
 
+define <vscale x 8 x half> @ldff1h_f16_reg(<vscale x 8 x i1> %pg, half* %a, i64 %offset) {
+; CHECK-LABEL: ldff1h_f16_reg:
+; CHECK: ldff1h { z0.h }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT: ret
+  %base = getelementptr half, half* %a, i64 %offset
+  %load = call <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16(<vscale x 8 x i1> %pg, half* %base)
+  ret <vscale x 8 x half> %load
+}
+
 ;
 ; LDFF1SH
 ;
@@ -121,6 +228,16 @@ define <vscale x 4 x i32> @ldff1sh_s(<vscale x 4 x i1> %pg, i16* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldff1sh_s_reg(<vscale x 4 x i1> %pg, i16* %a, i64 %offset) {
+; CHECK-LABEL: ldff1sh_s_reg:
+; CHECK: ldff1sh { z0.s }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT: ret
+  %base = getelementptr i16, i16* %a, i64 %offset
+  %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16(<vscale x 4 x i1> %pg, i16* %base)
+  %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 2 x i64> @ldff1sh_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldff1sh_d:
 ; CHECK: ldff1sh { z0.d }, p0/z, [x0]
@@ -130,6 +247,16 @@ define <vscale x 2 x i64> @ldff1sh_d(<vscale x 2 x i1> %pg, i16* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldff1sh_d_reg(<vscale x 2 x i1> %pg, i16* %a, i64 %offset) {
+; CHECK-LABEL: ldff1sh_d_reg:
+; CHECK: ldff1sh { z0.d }, p0/z, [x0, x1, lsl #1]
+; CHECK-NEXT: ret
+  %base = getelementptr i16, i16* %a, i64 %offset
+  %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16(<vscale x 2 x i1> %pg, i16* %base)
+  %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 ;
 ; LDFF1W
 ;
@@ -142,6 +269,15 @@ define <vscale x 4 x i32> @ldff1w(<vscale x 4 x i1> %pg, i32* %a) {
   ret <vscale x 4 x i32> %load
 }
 
+define <vscale x 4 x i32> @ldff1w_reg(<vscale x 4 x i1> %pg, i32* %a, i64 %offset) {
+; CHECK-LABEL: ldff1w_reg:
+; CHECK: ldff1w { z0.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT: ret
+  %base = getelementptr i32, i32* %a, i64 %offset
+  %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32(<vscale x 4 x i1> %pg, i32* %base)
+  ret <vscale x 4 x i32> %load
+}
+
 define <vscale x 2 x i64> @ldff1w_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldff1w_d:
 ; CHECK: ldff1w { z0.d }, p0/z, [x0]
@@ -151,6 +287,16 @@ define <vscale x 2 x i64> @ldff1w_d(<vscale x 2 x i1> %pg, i32* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldff1w_d_reg(<vscale x 2 x i1> %pg, i32* %a, i64 %offset) {
+; CHECK-LABEL: ldff1w_d_reg:
+; CHECK: ldff1w { z0.d }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT: ret
+  %base = getelementptr i32, i32* %a, i64 %offset
+  %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32(<vscale x 2 x i1> %pg, i32* %base)
+  %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 4 x float> @ldff1w_f32(<vscale x 4 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldff1w_f32:
 ; CHECK: ldff1w { z0.s }, p0/z, [x0]
@@ -159,6 +305,15 @@ define <vscale x 4 x float> @ldff1w_f32(<vscale x 4 x i1> %pg, float* %a) {
   ret <vscale x 4 x float> %load
 }
 
+define <vscale x 4 x float> @ldff1w_f32_reg(<vscale x 4 x i1> %pg, float* %a, i64 %offset) {
+; CHECK-LABEL: ldff1w_f32_reg:
+; CHECK: ldff1w { z0.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT: ret
+  %base = getelementptr float, float* %a, i64 %offset
+  %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32(<vscale x 4 x i1> %pg, float* %base)
+  ret <vscale x 4 x float> %load
+}
+
 define <vscale x 2 x float> @ldff1w_2f32(<vscale x 2 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldff1w_2f32:
 ; CHECK: ldff1w { z0.d }, p0/z, [x0]
@@ -167,6 +322,15 @@ define <vscale x 2 x float> @ldff1w_2f32(<vscale x 2 x i1> %pg, float* %a) {
   ret <vscale x 2 x float> %load
 }
 
+define <vscale x 2 x float> @ldff1w_2f32_reg(<vscale x 2 x i1> %pg, float* %a, i64 %offset) {
+; CHECK-LABEL: ldff1w_2f32_reg:
+; CHECK: ldff1w { z0.d }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT: ret
+  %base = getelementptr float, float* %a, i64 %offset
+  %load = call <vscale x 2 x float> @llvm.aarch64.sve.ldff1.nxv2f32(<vscale x 2 x i1> %pg, float* %base)
+  ret <vscale x 2 x float> %load
+}
+
 ;
 ; LDFF1SW
 ;
@@ -180,6 +344,16 @@ define <vscale x 2 x i64> @ldff1sw_d(<vscale x 2 x i1> %pg, i32* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldff1sw_d_reg(<vscale x 2 x i1> %pg, i32* %a, i64 %offset) {
+; CHECK-LABEL: ldff1sw_d_reg:
+; CHECK: ldff1sw { z0.d }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT: ret
+  %base = getelementptr i32, i32* %a, i64 %offset
+  %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32(<vscale x 2 x i1> %pg, i32* %base)
+  %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 ;
 ; LDFF1D
 ;
@@ -192,6 +366,15 @@ define <vscale x 2 x i64> @ldff1d(<vscale x 2 x i1> %pg, i64* %a) {
   ret <vscale x 2 x i64> %load
 }
 
+define <vscale x 2 x i64> @ldff1d_reg(<vscale x 2 x i1> %pg, i64* %a, i64 %offset) {
+; CHECK-LABEL: ldff1d_reg:
+; CHECK: ldff1d { z0.d }, p0/z, [x0, x1, lsl #3]
+; CHECK-NEXT: ret
+  %base = getelementptr i64, i64* %a, i64 %offset
+  %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64(<vscale x 2 x i1> %pg, i64* %base)
+  ret <vscale x 2 x i64> %load
+}
+
 
 define <vscale x 2 x double> @ldff1d_f64(<vscale x 2 x i1> %pg, double* %a) {
 ; CHECK-LABEL: ldff1d_f64:
@@ -201,6 +384,15 @@ define <vscale x 2 x double> @ldff1d_f64(<vscale x 2 x i1> %pg, double* %a) {
   ret <vscale x 2 x double> %load
 }
 
+define <vscale x 2 x double> @ldff1d_f64_reg(<vscale x 2 x i1> %pg, double* %a, i64 %offset) {
+; CHECK-LABEL: ldff1d_f64_reg:
+; CHECK: ldff1d { z0.d }, p0/z, [x0, x1, lsl #3]
+; CHECK-NEXT: ret
+  %base = getelementptr double, double* %a, i64 %offset
+  %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64(<vscale x 2 x i1> %pg, double* %base)
+  ret <vscale x 2 x double> %load
+}
+
 declare <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8(<vscale x 16 x i1>, i8*)
 
 declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8(<vscale x 8 x i1>, i8*)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
index 162ade5aca4d8..917d7ccab69e5 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
@@ -1,5 +1,9 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
+; Range testing for the immediate in the reg+imm(mulvl) addressing
+; mode is done only for one instruction. The rest of the instrucions
+; test only one immediate value in bound.
+
 define <vscale x 16 x i8> @ldnf1b(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b:
 ; CHECK: ldnf1b { z0.b }, p0/z, [x0]
@@ -8,6 +12,65 @@ define <vscale x 16 x i8> @ldnf1b(<vscale x 16 x i1> %pg, i8* %a) {
   ret <vscale x 16 x i8> %load
 }
 
+define <vscale x 16 x i8> @ldnf1b_out_of_lower_bound(<vscale x 16 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_out_of_lower_bound:
+; CHECK:       rdvl    x[[OFFSET:[0-9]+]], #-9
+; CHECK-NEXT:  add     x[[BASE:[0-9]+]], x0, x[[OFFSET]]
+; CHECK-NEXT:  ldnf1b { z0.b }, p0/z, [x[[BASE]]]
+; CHECK-NEXT:  ret
+  %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
+  %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -9
+  %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
+  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
+  ret <vscale x 16 x i8> %load
+}
+
+define <vscale x 16 x i8> @ldnf1b_lower_bound(<vscale x 16 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_lower_bound:
+; CHECK: ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
+  %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -8
+  %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
+  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
+  ret <vscale x 16 x i8> %load
+}
+
+define <vscale x 16 x i8> @ldnf1b_inbound(<vscale x 16 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_inbound:
+; CHECK: ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
+  %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 1
+  %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
+  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
+  ret <vscale x 16 x i8> %load
+}
+
+define <vscale x 16 x i8> @ldnf1b_upper_bound(<vscale x 16 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_upper_bound:
+; CHECK: ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
+  %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
+  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
+  ret <vscale x 16 x i8> %load
+}
+
+define <vscale x 16 x i8> @ldnf1b_out_of_upper_bound(<vscale x 16 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_out_of_upper_bound:
+; CHECK:       rdvl    x[[OFFSET:[0-9]+]], #8
+; CHECK-NEXT:  add     x[[BASE:[0-9]+]], x0, x[[OFFSET]]
+; CHECK-NEXT:  ldnf1b { z0.b }, p0/z, [x[[BASE]]]
+; CHECK-NEXT:  ret
+  %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
+  %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 8
+  %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
+  %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
+  ret <vscale x 16 x i8> %load
+}
+
 define <vscale x 8 x i16> @ldnf1b_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_h:
 ; CHECK: ldnf1b { z0.h }, p0/z, [x0]
@@ -17,6 +80,18 @@ define <vscale x 8 x i16> @ldnf1b_h(<vscale x 8 x i1> %pg, i8* %a) {
   ret <vscale x 8 x i16> %res
 }
 
+define <vscale x 8 x i16> @ldnf1b_h_inbound(<vscale x 8 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_h_inbound:
+; CHECK: ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 8 x i8>*
+  %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 8 x i8>* %base to i8*
+  %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %base_scalar)
+  %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %res
+}
+
 define <vscale x 8 x i16> @ldnf1sb_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_h:
 ; CHECK: ldnf1sb { z0.h }, p0/z, [x0]
@@ -26,6 +101,18 @@ define <vscale x 8 x i16> @ldnf1sb_h(<vscale x 8 x i1> %pg, i8* %a) {
   ret <vscale x 8 x i16> %res
 }
 
+define <vscale x 8 x i16> @ldnf1sb_h_inbound(<vscale x 8 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1sb_h_inbound:
+; CHECK: ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 8 x i8>*
+  %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 8 x i8>* %base to i8*
+  %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %base_scalar)
+  %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %res
+}
+
 define <vscale x 8 x i16> @ldnf1h(<vscale x 8 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h:
 ; CHECK: ldnf1h { z0.h }, p0/z, [x0]
@@ -34,6 +121,17 @@ define <vscale x 8 x i16> @ldnf1h(<vscale x 8 x i1> %pg, i16* %a) {
   ret <vscale x 8 x i16> %load
 }
 
+define <vscale x 8 x i16> @ldnf1h_inbound(<vscale x 8 x i1> %pg, i16* %a) {
+; CHECK-LABEL: ldnf1h_inbound:
+; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i16* %a to <vscale x 8 x i16>*
+  %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base_scalable, i64 1
+  %base_scalar = bitcast <vscale x 8 x i16>* %base to i16*
+  %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16(<vscale x 8 x i1> %pg, i16* %base_scalar)
+  ret <vscale x 8 x i16> %load
+}
+
 define <vscale x 8 x half> @ldnf1h_f16(<vscale x 8 x i1> %pg, half* %a) {
 ; CHECK-LABEL: ldnf1h_f16:
 ; CHECK: ldnf1h { z0.h }, p0/z, [x0]
@@ -42,6 +140,17 @@ define <vscale x 8 x half> @ldnf1h_f16(<vscale x 8 x i1> %pg, half* %a) {
   ret <vscale x 8 x half> %load
 }
 
+define <vscale x 8 x half> @ldnf1h_f16_inbound(<vscale x 8 x i1> %pg, half* %a) {
+; CHECK-LABEL: ldnf1h_f16_inbound:
+; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast half* %a to <vscale x 8 x half>*
+  %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base_scalable, i64 1
+  %base_scalar = bitcast <vscale x 8 x half>* %base to half*
+  %load = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16(<vscale x 8 x i1> %pg, half* %base_scalar)
+  ret <vscale x 8 x half> %load
+}
+
 define <vscale x 4 x i32> @ldnf1b_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_s:
 ; CHECK: ldnf1b { z0.s }, p0/z, [x0]
@@ -51,6 +160,18 @@ define <vscale x 4 x i32> @ldnf1b_s(<vscale x 4 x i1> %pg, i8* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldnf1b_s_inbound(<vscale x 4 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_s_inbound:
+; CHECK: ldnf1b { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 4 x i8>*
+  %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 4 x i8>* %base to i8*
+  %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %base_scalar)
+  %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 4 x i32> @ldnf1sb_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_s:
 ; CHECK: ldnf1sb { z0.s }, p0/z, [x0]
@@ -60,6 +181,18 @@ define <vscale x 4 x i32> @ldnf1sb_s(<vscale x 4 x i1> %pg, i8* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldnf1sb_s_inbound(<vscale x 4 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1sb_s_inbound:
+; CHECK: ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 4 x i8>*
+  %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 4 x i8>* %base to i8*
+  %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %base_scalar)
+  %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 4 x i32> @ldnf1h_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_s:
 ; CHECK: ldnf1h { z0.s }, p0/z, [x0]
@@ -69,6 +202,18 @@ define <vscale x 4 x i32> @ldnf1h_s(<vscale x 4 x i1> %pg, i16* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldnf1h_s_inbound(<vscale x 4 x i1> %pg, i16* %a) {
+; CHECK-LABEL: ldnf1h_s_inbound:
+; CHECK: ldnf1h { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i16* %a to <vscale x 4 x i16>*
+  %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 4 x i16>* %base to i16*
+  %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %base_scalar)
+  %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 4 x i32> @ldnf1sh_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_s:
 ; CHECK: ldnf1sh { z0.s }, p0/z, [x0]
@@ -78,6 +223,18 @@ define <vscale x 4 x i32> @ldnf1sh_s(<vscale x 4 x i1> %pg, i16* %a) {
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 4 x i32> @ldnf1sh_s_inbound(<vscale x 4 x i1> %pg, i16* %a) {
+; CHECK-LABEL: ldnf1sh_s_inbound:
+; CHECK: ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i16* %a to <vscale x 4 x i16>*
+  %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 4 x i16>* %base to i16*
+  %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %base_scalar)
+  %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %res
+}
+
 define <vscale x 4 x i32> @ldnf1w(<vscale x 4 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w:
 ; CHECK: ldnf1w { z0.s }, p0/z, [x0]
@@ -86,6 +243,17 @@ define <vscale x 4 x i32> @ldnf1w(<vscale x 4 x i1> %pg, i32* %a) {
   ret <vscale x 4 x i32> %load
 }
 
+define <vscale x 4 x i32> @ldnf1w_inbound(<vscale x 4 x i1> %pg, i32* %a) {
+; CHECK-LABEL: ldnf1w_inbound:
+; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i32* %a to <vscale x 4 x i32>*
+  %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 4 x i32>* %base to i32*
+  %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32(<vscale x 4 x i1> %pg, i32* %base_scalar)
+  ret <vscale x 4 x i32> %load
+}
+
 define <vscale x 4 x float> @ldnf1w_f32(<vscale x 4 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldnf1w_f32:
 ; CHECK: ldnf1w { z0.s }, p0/z, [x0]
@@ -94,6 +262,17 @@ define <vscale x 4 x float> @ldnf1w_f32(<vscale x 4 x i1> %pg, float* %a) {
   ret <vscale x 4 x float> %load
 }
 
+define <vscale x 4 x float> @ldnf1w_f32_inbound(<vscale x 4 x i1> %pg, float* %a) {
+; CHECK-LABEL: ldnf1w_f32_inbound:
+; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast float* %a to <vscale x 4 x float>*
+  %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 4 x float>* %base to float*
+  %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32(<vscale x 4 x i1> %pg, float* %base_scalar)
+  ret <vscale x 4 x float> %load
+}
+
 define <vscale x 2 x i64> @ldnf1b_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_d:
 ; CHECK: ldnf1b { z0.d }, p0/z, [x0]
@@ -103,6 +282,18 @@ define <vscale x 2 x i64> @ldnf1b_d(<vscale x 2 x i1> %pg, i8* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldnf1b_d_inbound(<vscale x 2 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1b_d_inbound:
+; CHECK: ldnf1b { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 2 x i8>*
+  %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 2 x i8>* %base to i8*
+  %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %base_scalar)
+  %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 2 x i64> @ldnf1sb_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_d:
 ; CHECK: ldnf1sb { z0.d }, p0/z, [x0]
@@ -112,6 +303,18 @@ define <vscale x 2 x i64> @ldnf1sb_d(<vscale x 2 x i1> %pg, i8* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldnf1sb_d_inbound(<vscale x 2 x i1> %pg, i8* %a) {
+; CHECK-LABEL: ldnf1sb_d_inbound:
+; CHECK: ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i8* %a to <vscale x 2 x i8>*
+  %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 2 x i8>* %base to i8*
+  %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %base_scalar)
+  %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 2 x i64> @ldnf1h_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_d:
 ; CHECK: ldnf1h { z0.d }, p0/z, [x0]
@@ -121,6 +324,18 @@ define <vscale x 2 x i64> @ldnf1h_d(<vscale x 2 x i1> %pg, i16* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldnf1h_d_inbound(<vscale x 2 x i1> %pg, i16* %a) {
+; CHECK-LABEL: ldnf1h_d_inbound:
+; CHECK: ldnf1h { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i16* %a to <vscale x 2 x i16>*
+  %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 2 x i16>* %base to i16*
+  %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %base_scalar)
+  %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 2 x i64> @ldnf1sh_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_d:
 ; CHECK: ldnf1sh { z0.d }, p0/z, [x0]
@@ -130,6 +345,18 @@ define <vscale x 2 x i64> @ldnf1sh_d(<vscale x 2 x i1> %pg, i16* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldnf1sh_d_inbound(<vscale x 2 x i1> %pg, i16* %a) {
+; CHECK-LABEL: ldnf1sh_d_inbound:
+; CHECK: ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i16* %a to <vscale x 2 x i16>*
+  %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 2 x i16>* %base to i16*
+  %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %base_scalar)
+  %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 2 x i64> @ldnf1w_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_d:
 ; CHECK: ldnf1w { z0.d }, p0/z, [x0]
@@ -139,6 +366,18 @@ define <vscale x 2 x i64> @ldnf1w_d(<vscale x 2 x i1> %pg, i32* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldnf1w_d_inbound(<vscale x 2 x i1> %pg, i32* %a) {
+; CHECK-LABEL: ldnf1w_d_inbound:
+; CHECK: ldnf1w { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i32* %a to <vscale x 2 x i32>*
+  %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 2 x i32>* %base to i32*
+  %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %base_scalar)
+  %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 2 x i64> @ldnf1sw_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1sw_d:
 ; CHECK: ldnf1sw { z0.d }, p0/z, [x0]
@@ -148,6 +387,18 @@ define <vscale x 2 x i64> @ldnf1sw_d(<vscale x 2 x i1> %pg, i32* %a) {
   ret <vscale x 2 x i64> %res
 }
 
+define <vscale x 2 x i64> @ldnf1sw_d_inbound(<vscale x 2 x i1> %pg, i32* %a) {
+; CHECK-LABEL: ldnf1sw_d_inbound:
+; CHECK: ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i32* %a to <vscale x 2 x i32>*
+  %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7
+  %base_scalar = bitcast <vscale x 2 x i32>* %base to i32*
+  %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %base_scalar)
+  %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %res
+}
+
 define <vscale x 2 x i64> @ldnf1d(<vscale x 2 x i1> %pg, i64* %a) {
 ; CHECK-LABEL: ldnf1d:
 ; CHECK: ldnf1d { z0.d }, p0/z, [x0]
@@ -156,6 +407,17 @@ define <vscale x 2 x i64> @ldnf1d(<vscale x 2 x i1> %pg, i64* %a) {
   ret <vscale x 2 x i64> %load
 }
 
+define <vscale x 2 x i64> @ldnf1d_inbound(<vscale x 2 x i1> %pg, i64* %a) {
+; CHECK-LABEL: ldnf1d_inbound:
+; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast i64* %a to <vscale x 2 x i64>*
+  %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base_scalable, i64 1
+  %base_scalar = bitcast <vscale x 2 x i64>* %base to i64*
+  %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64(<vscale x 2 x i1> %pg, i64* %base_scalar)
+  ret <vscale x 2 x i64> %load
+}
+
 define <vscale x 2 x double> @ldnf1d_f64(<vscale x 2 x i1> %pg, double* %a) {
 ; CHECK-LABEL: ldnf1d_f64:
 ; CHECK: ldnf1d { z0.d }, p0/z, [x0]
@@ -164,6 +426,17 @@ define <vscale x 2 x double> @ldnf1d_f64(<vscale x 2 x i1> %pg, double* %a) {
   ret <vscale x 2 x double> %load
 }
 
+define <vscale x 2 x double> @ldnf1d_f64_inbound(<vscale x 2 x i1> %pg, double* %a) {
+; CHECK-LABEL: ldnf1d_f64_inbound:
+; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ret
+  %base_scalable = bitcast double* %a to <vscale x 2 x double>*
+  %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base_scalable, i64 1
+  %base_scalar = bitcast <vscale x 2 x double>* %base to double*
+  %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64(<vscale x 2 x i1> %pg, double* %base_scalar)
+  ret <vscale x 2 x double> %load
+}
+
 declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1>, i8*)
 
 declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1>, i8*)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
index b82ae30ba2431..8f180d008306d 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -4,12 +4,12 @@
 ; LDNT1B
 ;
 
-define <vscale x 16 x i8> @ldnt1b_i8(<vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
+define <vscale x 16 x i8> @ldnt1b_i8(<vscale x 16 x i1> %pred, i8* %addr) {
 ; CHECK-LABEL: ldnt1b_i8:
 ; CHECK: ldnt1b { z0.b }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %pred,
-                                                                 <vscale x 16 x i8>* %addr)
+                                                                 i8* %addr)
   ret <vscale x 16 x i8> %res
 }
 
@@ -17,21 +17,21 @@ define <vscale x 16 x i8> @ldnt1b_i8(<vscale x 16 x i1> %pred, <vscale x 16 x i8
 ; LDNT1H
 ;
 
-define <vscale x 8 x i16> @ldnt1h_i16(<vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
+define <vscale x 8 x i16> @ldnt1h_i16(<vscale x 8 x i1> %pred, i16* %addr) {
 ; CHECK-LABEL: ldnt1h_i16:
 ; CHECK: ldnt1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %pred,
-                                                                 <vscale x 8 x i16>* %addr)
+                                                                 i16* %addr)
   ret <vscale x 8 x i16> %res
 }
 
-define <vscale x 8 x half> @ldnt1h_f16(<vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
+define <vscale x 8 x half> @ldnt1h_f16(<vscale x 8 x i1> %pred, half* %addr) {
 ; CHECK-LABEL: ldnt1h_f16:
 ; CHECK: ldnt1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %pred,
-                                                                  <vscale x 8 x half>* %addr)
+                                                                  half* %addr)
   ret <vscale x 8 x half> %res
 }
 
@@ -39,21 +39,21 @@ define <vscale x 8 x half> @ldnt1h_f16(<vscale x 8 x i1> %pred, <vscale x 8 x ha
 ; LDNT1W
 ;
 
-define <vscale x 4 x i32> @ldnt1w_i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
+define <vscale x 4 x i32> @ldnt1w_i32(<vscale x 4 x i1> %pred, i32* %addr) {
 ; CHECK-LABEL: ldnt1w_i32:
 ; CHECK: ldnt1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %pred,
-                                                                 <vscale x 4 x i32>* %addr)
+                                                                 i32* %addr)
   ret <vscale x 4 x i32> %res
 }
 
-define <vscale x 4 x float> @ldnt1w_f32(<vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
+define <vscale x 4 x float> @ldnt1w_f32(<vscale x 4 x i1> %pred, float* %addr) {
 ; CHECK-LABEL: ldnt1w_f32:
 ; CHECK: ldnt1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %pred,
-                                                                   <vscale x 4 x float>* %addr)
+                                                                   float* %addr)
   ret <vscale x 4 x float> %res
 }
 
@@ -61,28 +61,28 @@ define <vscale x 4 x float> @ldnt1w_f32(<vscale x 4 x i1> %pred, <vscale x 4 x f
 ; LDNT1D
 ;
 
-define <vscale x 2 x i64> @ldnt1d_i64(<vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
+define <vscale x 2 x i64> @ldnt1d_i64(<vscale x 2 x i1> %pred, i64* %addr) {
 ; CHECK-LABEL: ldnt1d_i64:
 ; CHECK: ldnt1d { z0.d }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %pred,
-                                                                 <vscale x 2 x i64>* %addr)
+                                                                 i64* %addr)
   ret <vscale x 2 x i64> %res
 }
 
-define <vscale x 2 x double> @ldnt1d_f64(<vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
+define <vscale x 2 x double> @ldnt1d_f64(<vscale x 2 x i1> %pred, double* %addr) {
 ; CHECK-LABEL: ldnt1d_f64:
 ; CHECK: ldnt1d { z0.d }, p0/z, [x0]
 ; CHECK-NEXT: ret
   %res = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %pred,
-                                                                    <vscale x 2 x double>* %addr)
+                                                                    double* %addr)
   ret <vscale x 2 x double> %res
 }
 
-declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*)
-declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*)
-declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*)
-declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*)
-declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*)
+declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, i8*)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, i16*)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, i32*)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, i64*)
+declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, half*)
+declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, float*)
+declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, double*)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
index 29d369ba42a05..772e36888fbe8 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -4,13 +4,13 @@
 ; STNT1B
 ;
 
-define void @stnt1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
+define void @stnt1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, i8* %addr) {
 ; CHECK-LABEL: stnt1b_i8:
 ; CHECK: stnt1b { z0.b }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %data,
                                             <vscale x 16 x i1> %pred,
-                                            <vscale x 16 x i8>* %addr)
+                                            i8* %addr)
   ret void
 }
 
@@ -18,23 +18,23 @@ define void @stnt1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, <vsca
 ; STNT1H
 ;
 
-define void @stnt1h_i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
+define void @stnt1h_i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %pred, i16* %addr) {
 ; CHECK-LABEL: stnt1h_i16:
 ; CHECK: stnt1h { z0.h }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16> %data,
                                             <vscale x 8 x i1> %pred,
-                                            <vscale x 8 x i16>* %addr)
+                                            i16* %addr)
   ret void
 }
 
-define void @stnt1h_f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
+define void @stnt1h_f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %pred, half* %addr) {
 ; CHECK-LABEL: stnt1h_f16:
 ; CHECK: stnt1h { z0.h }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half> %data,
                                             <vscale x 8 x i1> %pred,
-                                            <vscale x 8 x half>* %addr)
+                                            half* %addr)
   ret void
 }
 
@@ -42,23 +42,23 @@ define void @stnt1h_f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %pred, <vsc
 ; STNT1W
 ;
 
-define void @stnt1w_i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
+define void @stnt1w_i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, i32* %addr) {
 ; CHECK-LABEL: stnt1w_i32:
 ; CHECK: stnt1w { z0.s }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32> %data,
                                             <vscale x 4 x i1> %pred,
-                                            <vscale x 4 x i32>* %addr)
+                                            i32* %addr)
   ret void
 }
 
-define void @stnt1w_f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
+define void @stnt1w_f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %pred, float* %addr) {
 ; CHECK-LABEL: stnt1w_f32:
 ; CHECK: stnt1w { z0.s }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float> %data,
                                             <vscale x 4 x i1> %pred,
-                                            <vscale x 4 x float>* %addr)
+                                            float* %addr)
   ret void
 }
 
@@ -66,30 +66,30 @@ define void @stnt1w_f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %pred, <vs
 ; STNT1D
 ;
 
-define void @stnt1d_i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
+define void @stnt1d_i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, i64* %addr) {
 ; CHECK-LABEL: stnt1d_i64:
 ; CHECK: stnt1d { z0.d }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
                                             <vscale x 2 x i1> %pred,
-                                            <vscale x 2 x i64>* %addr)
+                                            i64* %addr)
   ret void
 }
 
-define void @stnt1d_f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
+define void @stnt1d_f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %pred, double* %addr) {
 ; CHECK-LABEL: stnt1d_f64:
 ; CHECK: stnt1d { z0.d }, p0, [x0]
 ; CHECK-NEXT: ret
   call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
                                             <vscale x 2 x i1> %pred,
-                                            <vscale x 2 x double>* %addr)
+                                            double* %addr)
   ret void
 }
 
-declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
-declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
-declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
-declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
-declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
-declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
-declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
+declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
+declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
+declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
+declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
+declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*)
+declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*)
+declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*)
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll b/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
index fc71c79be69c7..32dfecc4507b6 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
@@ -15,12 +15,14 @@ define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mas
 ; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x{{[0-9]+}}]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8
+  %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64*
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
-                                                                  <vscale x 2 x i64>* %base_load)
+                                                                  i64* %base_load_bc)
   %base_store = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64> * %base, i64 -9
+  %base_store_bc = bitcast <vscale x 2 x i64>* %base_store to i64*
   call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
                                             <vscale x 2 x i1> %mask,
-                                            <vscale x 2 x i64>* %base_store)
+                                            i64* %base_store_bc)
   ret void
 }
 
@@ -33,12 +35,14 @@ define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i
 ; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-7, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8
+  %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64*
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
-                                                                  <vscale x 2 x i64>* %base_load)
+                                                                  i64* %base_load_bc)
   %base_store = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64> * %base, i64 -7
+  %base_store_bc = bitcast <vscale x 2 x i64>* %base_store to i64*
   call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
                                             <vscale x 2 x i1> %mask,
-                                            <vscale x 2 x i64>* %base_store)
+                                            i64* %base_store_bc)
   ret void
 }
 
@@ -48,12 +52,14 @@ define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2
 ; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-5, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6
+  %base_load_bc = bitcast <vscale x 2 x double>* %base_load to double*
   %data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask,
-                                                                    <vscale x 2 x double>* %base_load)
+                                                                    double* %base_load_bc)
   %base_store = getelementptr <vscale x 2 x double>, <vscale x 2 x double> * %base, i64 -5
+  %base_store_bc = bitcast <vscale x 2 x double>* %base_store to double*
   call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
                                             <vscale x 2 x i1> %mask,
-                                            <vscale x 2 x double>* %base_store)
+                                            double* %base_store_bc)
   ret void
 }
 
@@ -65,12 +71,14 @@ define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i
 ; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #7, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6
+  %base_load_bc = bitcast <vscale x 4 x i32>* %base_load to i32*
   %data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask,
-                                                                  <vscale x 4 x i32>* %base_load)
+                                                                  i32* %base_load_bc)
   %base_store = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32> * %base, i64 7
+  %base_store_bc = bitcast <vscale x 4 x i32>* %base_store to i32*
   call void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32> %data,
                                             <vscale x 4 x i1> %mask,
-                                            <vscale x 4 x i32>* %base_store)
+                                            i32* %base_store_bc)
   ret void
 }
 
@@ -80,12 +88,14 @@ define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x
 ; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #2, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1
+  %base_load_bc = bitcast <vscale x 4 x float>* %base_load to float*
   %data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask,
-                                                                    <vscale x 4 x float>* %base_load)
+                                                                    float* %base_load_bc)
   %base_store = getelementptr <vscale x 4 x float>, <vscale x 4 x float> * %base, i64 2
+  %base_store_bc = bitcast <vscale x 4 x float>* %base_store to float*
   call void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float> %data,
                                             <vscale x 4 x i1> %mask,
-                                            <vscale x 4 x float>* %base_store)
+                                            float* %base_store_bc)
   ret void
 }
 
@@ -98,12 +108,14 @@ define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i
 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #7, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6
+  %base_load_bc = bitcast <vscale x 8 x i16>* %base_load to i16*
   %data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask,
-                                                                  <vscale x 8 x i16>* %base_load)
+                                                                  i16* %base_load_bc)
   %base_store = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16> * %base, i64 7
+  %base_store_bc = bitcast <vscale x 8 x i16>* %base_store to i16*
   call void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16> %data,
                                             <vscale x 8 x i1> %mask,
-                                            <vscale x 8 x i16>* %base_store)
+                                            i16* %base_store_bc)
   ret void
 }
 
@@ -113,12 +125,14 @@ define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x
 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1
+  %base_load_bc = bitcast <vscale x 8 x half>* %base_load to half*
   %data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask,
-                                                                   <vscale x 8 x half>* %base_load)
+                                                                   half* %base_load_bc)
   %base_store = getelementptr <vscale x 8 x half>, <vscale x 8 x half> * %base, i64 2
+  %base_store_bc = bitcast <vscale x 8 x half>* %base_store to half*
   call void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half> %data,
                                             <vscale x 8 x i1> %mask,
-                                            <vscale x 8 x half>* %base_store)
+                                            half* %base_store_bc)
   ret void
 }
 
@@ -130,42 +144,44 @@ define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x
 ; CHECK-NEXT: stnt1b { z[[DATA]].b }, p0, [x0, #7, mul vl]
 ; CHECK-NEXT: ret
   %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6
+  %base_load_bc = bitcast <vscale x 16 x i8>* %base_load to i8*
   %data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask,
-                                                                  <vscale x 16 x i8>* %base_load)
+                                                                  i8* %base_load_bc)
   %base_store = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8> * %base, i64 7
+  %base_store_bc = bitcast <vscale x 16 x i8>* %base_store to i8*
   call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %data,
                                             <vscale x 16 x i1> %mask,
-                                            <vscale x 16 x i8>* %base_store)
+                                            i8* %base_store_bc)
   ret void
 }
 
 ; 2-element non-temporal loads.
-declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*)
-declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, i64*)
+declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, double*)
 
 ; 4-element non-temporal loads.
-declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*)
-declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, i32*)
+declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, float*)
 
 ; 8-element non-temporal loads.
-declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*)
-declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, i16*)
+declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, half*)
 
 ; 16-element non-temporal loads.
-declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*)
+declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, i8*)
 
 ; 2-element non-temporal stores.
-declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
-declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
+declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
+declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*)
                                                                       
 ; 4-element non-temporal stores.                                        
-declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
-declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
+declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
+declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*)
                                                                       
 ; 8-element non-temporal stores.                                        
-declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
-declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
+declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
+declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*)
 
 ; 16-element non-temporal stores.
-declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
+declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
 
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll b/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
index 663f5659ec00b..eb1d8a326a259 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
@@ -7,13 +7,12 @@ define void @test_masked_ldst_sv2i64(i64* %base, <vscale x 2 x i1> %mask, i64 %o
 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #3]
 ; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, x1, lsl #3]
 ; CHECK-NEXT: ret
-  %base_i64 = getelementptr i64, i64* %base, i64 %offset
-  %base_addr = bitcast i64* %base_i64 to <vscale x 2 x i64>*
+  %gep = getelementptr i64, i64* %base, i64 %offset
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
-                                                                  <vscale x 2 x i64>* %base_addr)
+                                                                  i64* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
                                             <vscale x 2 x i1> %mask,
-                                            <vscale x 2 x i64>* %base_addr)
+                                            i64* %gep)
   ret void
 }
 
@@ -22,13 +21,12 @@ define void @test_masked_ldst_sv2f64(double* %base, <vscale x 2 x i1> %mask, i64
 ; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #3]
 ; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, x1, lsl #3]
 ; CHECK-NEXT: ret
-  %base_double = getelementptr double, double* %base, i64 %offset
-  %base_addr = bitcast double* %base_double to <vscale x 2 x double>*
+  %gep = getelementptr double, double* %base, i64 %offset
   %data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask,
-                                                                    <vscale x 2 x double>* %base_addr)
+                                                                    double* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
                                             <vscale x 2 x i1> %mask,
-                                            <vscale x 2 x double>* %base_addr)
+                                            double* %gep)
   ret void
 }
 
@@ -39,13 +37,12 @@ define void @test_masked_ldst_sv4i32(i32* %base, <vscale x 4 x i1> %mask, i64 %o
 ; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #2]
 ; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, x1, lsl #2]
 ; CHECK-NEXT: ret
-  %base_i32 = getelementptr i32, i32* %base, i64 %offset
-  %base_addr = bitcast i32* %base_i32 to <vscale x 4 x i32>*
+  %gep = getelementptr i32, i32* %base, i64 %offset
   %data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask,
-                                                                  <vscale x 4 x i32>* %base_addr)
+                                                                  i32* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32> %data,
                                             <vscale x 4 x i1> %mask,
-                                            <vscale x 4 x i32>* %base_addr)
+                                            i32* %gep)
   ret void
 }
 
@@ -54,13 +51,12 @@ define void @test_masked_ldst_sv4f32(float* %base, <vscale x 4 x i1> %mask, i64
 ; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #2]
 ; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, x1, lsl #2]
 ; CHECK-NEXT: ret
-  %base_float = getelementptr float, float* %base, i64 %offset
-  %base_addr = bitcast float* %base_float to <vscale x 4 x float>*
+  %gep = getelementptr float, float* %base, i64 %offset
   %data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask,
-                                                                    <vscale x 4 x float>* %base_addr)
+                                                                    float* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float> %data,
                                             <vscale x 4 x i1> %mask,
-                                            <vscale x 4 x float>* %base_addr)
+                                            float* %gep)
   ret void
 }
 
@@ -72,13 +68,12 @@ define void @test_masked_ldst_sv8i16(i16* %base, <vscale x 8 x i1> %mask, i64 %o
 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
 ; CHECK-NEXT: ret
-  %base_i16 = getelementptr i16, i16* %base, i64 %offset
-  %base_addr = bitcast i16* %base_i16 to <vscale x 8 x i16>*
+  %gep = getelementptr i16, i16* %base, i64 %offset
   %data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask,
-                                                                  <vscale x 8 x i16>* %base_addr)
+                                                                  i16* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16> %data,
                                             <vscale x 8 x i1> %mask,
-                                            <vscale x 8 x i16>* %base_addr)
+                                            i16* %gep)
   ret void
 }
 
@@ -87,13 +82,12 @@ define void @test_masked_ldst_sv8f16(half* %base, <vscale x 8 x i1> %mask, i64 %
 ; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
 ; CHECK-NEXT: ret
-  %base_half = getelementptr half, half* %base, i64 %offset
-  %base_addr = bitcast half* %base_half to <vscale x 8 x half>*
+  %gep = getelementptr half, half* %base, i64 %offset
   %data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask,
-                                                                   <vscale x 8 x half>* %base_addr)
+                                                                   half* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half> %data,
                                             <vscale x 8 x i1> %mask,
-                                            <vscale x 8 x half>* %base_addr)
+                                            half* %gep)
   ret void
 }
 
@@ -104,42 +98,41 @@ define void @test_masked_ldst_sv16i8(i8* %base, <vscale x 16 x i1> %mask, i64 %o
 ; CHECK-NEXT: ldnt1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, x1]
 ; CHECK-NEXT: stnt1b { z[[DATA]].b }, p0, [x0, x1]
 ; CHECK-NEXT: ret
-  %base_i8 = getelementptr i8, i8* %base, i64 %offset
-  %base_addr = bitcast i8* %base_i8 to <vscale x 16 x i8>*
+  %gep = getelementptr i8, i8* %base, i64 %offset
   %data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask,
-                                                                  <vscale x 16 x i8>* %base_addr)
+                                                                  i8* %gep)
   call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %data,
                                             <vscale x 16 x i1> %mask,
-                                            <vscale x 16 x i8>* %base_addr)
+                                            i8* %gep)
   ret void
 }
 
 ; 2-element non-temporal loads.
-declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*)
-declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, i64*)
+declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, double*)
 
 ; 4-element non-temporal loads.
-declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*)
-declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, i32*)
+declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, float*)
 
 ; 8-element non-temporal loads.
-declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*)
-declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, i16*)
+declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, half*)
 
 ; 16-element non-temporal loads.
-declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*)
+declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, i8*)
 
 ; 2-element non-temporal stores.
-declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
-declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
+declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
+declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*)
                                                                       
 ; 4-element non-temporal stores.                                        
-declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
-declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
+declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
+declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*)
                                                                       
 ; 8-element non-temporal stores.                                        
-declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
-declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
+declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
+declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*)
 
 ; 16-element non-temporal stores.
-declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
+declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
diff --git a/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir b/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
index 231de4e189664..eb92edf2725ad 100644
--- a/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
+++ b/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
@@ -1,7 +1,7 @@
 # RUN: llc -start-before=prologepilog -filetype=obj -o %t %s
 # RUN: llvm-dwarfdump --name=obj1 %t | FileCheck %s --check-prefix=CHECKDWARF1
 # RUN: llvm-dwarfdump --name=obj2 %t | FileCheck %s --check-prefix=CHECKDWARF2
-# RUN: llvm-objdump --disassemble %t | FileCheck %s --check-prefix=CHECKASM
+# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=CHECKASM
 #
 # Test that the location for obj1 and obj2 in the debug information is
 # the same as the location used by load instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
index a2bac737d3764..3c86dd903a066 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
@@ -1,6 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck %s
-# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
+# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_anyext_trunc_v2s32_to_v2s16_to_v2s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
index beaa2e0cc82be..c0c0b4075062c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
@@ -1,6 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck %s
-# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
+# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
new file mode 100644
index 0000000000000..a42b16ecb5914
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
@@ -0,0 +1,136 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: trunc_s16_merge_s64_s32
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with trunc-size < merge-source-size creates a trunc
+    ; of the merge source
+    ; CHECK-LABEL: name: trunc_s16_merge_s64_s32
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: $vgpr0 = COPY [[C]](s32)
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s64) = G_MERGE_VALUES %0, %1
+    %3:_(s16) = G_TRUNC %2
+    %4:_(s32) = G_ANYEXT %3
+    $vgpr0 = COPY %4
+...
+
+---
+name: trunc_s32_merge_s64_s32
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with trunc-size == merge-source-size is eliminated
+    ; CHECK-LABEL: name: trunc_s32_merge_s64_s32
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: $vgpr0 = COPY [[C]](s32)
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s64) = G_MERGE_VALUES %0, %1
+    %3:_(s32) = G_TRUNC %2
+    $vgpr0 = COPY %3
+...
+
+---
+name: trunc_s64_merge_s128_s32
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with trunc-size > merge-source-size combines to a
+    ; smaller merge
+    ; CHECK-LABEL: name: trunc_s64_merge_s128_s32
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s128) = G_MERGE_VALUES %0, %1, %0, %1
+    %3:_(s64) = G_TRUNC %2
+    $vgpr0_vgpr1 = COPY %3
+...
+
+---
+name: trunc_s32_merge_s128_p0
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with a non-scalar merge source is not combined
+    ; CHECK-LABEL: name: trunc_s32_merge_s128_p0
+    ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+    ; CHECK: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 1
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](p0), [[C1]](p0)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s128)
+    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
+    %0:_(p0) = G_CONSTANT i64 0
+    %1:_(p0) = G_CONSTANT i64 1
+    %2:_(s128) = G_MERGE_VALUES %0, %1
+    %3:_(s32) = G_TRUNC %2
+    $vgpr0 = COPY %3
+...
+
+---
+name: trunc_s64_merge_s128_p0
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with a non-scalar merge source is not combined
+    ; CHECK-LABEL: name: trunc_s64_merge_s128_p0
+    ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+    ; CHECK: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 1
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](p0), [[C1]](p0)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[MV]](s128)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[TRUNC]](s64)
+    %0:_(p0) = G_CONSTANT i64 0
+    %1:_(p0) = G_CONSTANT i64 1
+    %2:_(s128) = G_MERGE_VALUES %0, %1
+    %3:_(s64) = G_TRUNC %2
+    $vgpr0_vgpr1 = COPY %3
+...
+
+---
+name: trunc_s128_merge_s192_p0
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with a non-scalar merge source is not combined
+    ; CHECK-LABEL: name: trunc_s128_merge_s192_p0
+    ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+    ; CHECK: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 1
+    ; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[C]](p0), [[C1]](p0), [[C]](p0)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s128) = G_TRUNC [[MV]](s192)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[TRUNC]](s128)
+    %0:_(p0) = G_CONSTANT i64 0
+    %1:_(p0) = G_CONSTANT i64 1
+    %2:_(s192) = G_MERGE_VALUES %0, %1, %0
+    %3:_(s128) = G_TRUNC %2
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
+...
+
+---
+name: trunc_s68_merge_s128_s32
+
+body: |
+  bb.0:
+    ; Test that trunc(merge) with trunc-size > merge-source-size is not combined
+    ; if trunc-size % merge-source-size != 0
+    ; CHECK-LABEL: name: trunc_s68_merge_s128_s32
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s32), [[C1]](s32), [[C]](s32), [[C1]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s68) = G_TRUNC [[MV]](s128)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s68)
+    ; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s128) = G_MERGE_VALUES %0, %1, %0, %1
+    %3:_(s68) = G_TRUNC %2
+    %4:_(s32) = G_TRUNC %3
+    $vgpr0 = COPY %4
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
index f33d2c21f5a0f..85e7106675d75 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
@@ -1,6 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck %s
-# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
+# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_zext_trunc_v2s32_to_v2s16_to_v2s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
index e7d27af6481b8..611eab6bfa692 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
 
 ---
 name: ffloor_s32_vv
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
index b4ac02a72f613..57ff1d89e8dc6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
@@ -1,6 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=0  -o - %s | FileCheck -check-prefixes=GCN %s
-# XUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null  %s 2>&1 | FileCheck -check-prefixes=ERR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs  -o - %s | FileCheck -check-prefixes=GCN %s
 
 ---
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
index f0bcd376fe4e9..207814ccd8c86 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
@@ -589,3 +589,27 @@ body: |
     %4:sgpr(s1024) = G_MERGE_VALUES %0, %1, %2, %3
     S_ENDPGM 0, implicit %4
 ...
+
+---
+
+name: test_merge_values_s_s1024_s_s512
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+
+    ; GCN-LABEL: name: test_merge_values_s_s1024_s_s512
+    ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    ; GCN: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_512 = COPY $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_1024 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, [[COPY1]], %subreg.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
+    ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY [[REG_SEQUENCE]]
+    %0:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+    %1:sgpr(s512) = COPY $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    %2:sgpr(s1024) = G_MERGE_VALUES %0, %1
+    $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY %2
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
index 30270d22b1af6..f96dd5129e023 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
@@ -257,3 +257,32 @@ body: |
     %1:sgpr(s256), %2:sgpr(s256), %3:sgpr(s256), %4:sgpr(s256) = G_UNMERGE_VALUES %0
     S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4
 ...
+
+---
+
+name: test_unmerge_values_s_s512_s_s1024
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins:  $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_unmerge_s512_s1024
+    ; CHECK: [[COPY:%[0-9]+]]:_(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](s1024)
+    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[UV]](s512)
+    ; CHECK: $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY [[UV1]](s512)
+    ; GCN-LABEL: name: test_unmerge_values_s_s512_s_s1024
+    ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    ; GCN: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_512 = COPY [[COPY]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+    ; GCN: [[COPY2:%[0-9]+]]:sreg_512 = COPY [[COPY]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
+    ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[COPY1]]
+    ; GCN: $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY [[COPY2]]
+    %0:sgpr(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+    %1:sgpr(s512), %2:sgpr(s512) = G_UNMERGE_VALUES %0
+    $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %1
+    $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
index b058c6fe502b2..fdf98d2acb582 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
@@ -229,6 +229,67 @@ define void @void_func_p3i8(i8 addrspace(3)* %arg0) #0 {
   ret void
 }
 
+define void @void_func_i48(i48 %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i48
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (store 6 into `i48 addrspace(1)* undef`, align 8, addrspace 1)
+  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+  ; CHECK:   S_SETPC_B64_return [[COPY3]]
+  store i48 %arg0, i48 addrspace(1)* undef
+  ret void
+}
+
+define void @void_func_i48_zeroext(i48 zeroext %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i48_zeroext
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
+  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ZEXT]], [[C]]
+  ; CHECK:   G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+  ; CHECK:   S_SETPC_B64_return [[COPY3]]
+  %ext = zext i48 %arg0 to i64
+  %add = add i64 %ext, 12
+  store i64 %add, i64 addrspace(1)* undef
+  ret void
+}
+
+define void @void_func_i48_signext(i48 signext %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i48_signext
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
+  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT]], [[C]]
+  ; CHECK:   G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+  ; CHECK:   S_SETPC_B64_return [[COPY3]]
+  %ext = sext i48 %arg0 to i64
+  %add = add i64 %ext, 12
+  store i64 %add, i64 addrspace(1)* undef
+  ret void
+}
+
 define void @void_func_i64(i64 %arg0) #0 {
   ; CHECK-LABEL: name: void_func_i64
   ; CHECK: bb.1 (%ir-block.0):
@@ -245,6 +306,87 @@ define void @void_func_i64(i64 %arg0) #0 {
   ret void
 }
 
+define void @void_func_i95(i95 %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i95
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   G_STORE [[TRUNC]](s95), [[DEF]](p1) :: (store 12 into `i95 addrspace(1)* undef`, align 8, addrspace 1)
+  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+  ; CHECK:   S_SETPC_B64_return [[COPY4]]
+  store i95 %arg0, i95 addrspace(1)* undef
+  ret void
+}
+
+define void @void_func_i95_zeroext(i95 zeroext %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i95_zeroext
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
+  ; CHECK:   [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s96) = G_ZEXT [[TRUNC]](s95)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s96) = G_ADD [[ZEXT]], [[C]]
+  ; CHECK:   G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
+  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+  ; CHECK:   S_SETPC_B64_return [[COPY4]]
+  %ext = zext i95 %arg0 to i96
+  %add = add i96 %ext, 12
+  store i96 %add, i96 addrspace(1)* undef
+  ret void
+}
+
+define void @void_func_i95_signext(i95 signext %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i95_signext
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
+  ; CHECK:   [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   [[SEXT:%[0-9]+]]:_(s96) = G_SEXT [[TRUNC]](s95)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s96) = G_ADD [[SEXT]], [[C]]
+  ; CHECK:   G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
+  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+  ; CHECK:   S_SETPC_B64_return [[COPY4]]
+  %ext = sext i95 %arg0 to i96
+  %add = add i96 %ext, 12
+  store i96 %add, i96 addrspace(1)* undef
+  ret void
+}
+
+define void @void_func_i96(i96 %arg0) #0 {
+  ; CHECK-LABEL: name: void_func_i96
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; CHECK:   [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+  ; CHECK:   [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; CHECK:   G_STORE [[MV]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
+  ; CHECK:   [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+  ; CHECK:   S_SETPC_B64_return [[COPY4]]
+  store i96 %arg0, i96 addrspace(1)* undef
+  ret void
+}
+
 define void @void_func_p0i8(i8* %arg0) #0 {
   ; CHECK-LABEL: name: void_func_p0i8
   ; CHECK: bb.1 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
index dbf456f0c6f60..643bdd3b7d582 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=VI %s
-# RUN: llc -march=amdgcn -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=fiji -O0 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9 %s
 # RUN: llc -march=amdgcn -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=SI %s
 
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
index 06d1c24e8cec2..61cbade272b5c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
@@ -292,19 +292,17 @@ body: |
     ; CHECK-LABEL: name: test_bitcast_s24_to_v3s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
     ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[TRUNC]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
-    ; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
-    ; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
+    ; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
@@ -328,23 +326,21 @@ body: |
     ; CHECK-LABEL: name: test_bitcast_s48_to_v3s16
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
     ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
-    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32)
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
     ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
     ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
     ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
     ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
index b144f80ef2eb1..8ebe61b32561f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
@@ -207,13 +207,8 @@ body: |
     ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
     ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
     ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
-    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
-    ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s33) = G_TRUNC %0
     %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
index 373fe979efede..c65df76bda1a9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
@@ -253,13 +253,8 @@ body: |
     ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
     ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
     ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
-    ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C4]](s64)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
-    ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s33) = G_TRUNC %0
     %2:_(s33) = G_CTLZ %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index eba8a2393e77a..6490e9a603b79 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: extract_vector_elt_0_v2i32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
index 698960ba03eb2..e693766954c98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s  | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9  %s
 
 
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
index bd92234ccdd15..50d846ca2367a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fadd_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
index 0ace2229a69ac..9efb04c35f6e9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer  -global-isel-abort=0  %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer  %s -o - | FileCheck -check-prefix=GFX9  %s
 
 
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
index c701e43381c19..c4f373c588f4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -march=amdgcn -mcpu=hawaii  -run-pass=legalizer -verify-machineinstrs  -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
-# RUN: llc -O0 -march=amdgcn -mcpu=fiji  -run-pass=legalizer -verify-machineinstrs  -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -O0 -march=amdgcn -mcpu=gfx900  -run-pass=legalizer -verify-machineinstrs  -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -O0 -march=amdgcn -mcpu=hawaii  -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -O0 -march=amdgcn -mcpu=fiji  -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -O0 -march=amdgcn -mcpu=gfx900  -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_fcmp_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index 3c74a7f9c20b1..550d89d0584e8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_copysign_s16_s16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
index fdab550397a88..a6b5fc876f7d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s  | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fcos_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
index 9ccd77cb69db2..b1eec4dfee3d3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_ffloor_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
index e37d48787d10f..06f237f7a3050 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fma_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
index 63645cf7b8c26..f6456cd57f01e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fminnum_s32_ieee_mode_on
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
index 63645cf7b8c26..f6456cd57f01e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fminnum_s32_ieee_mode_on
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
index 77c8cf402bb70..45130639f696f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fmul_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
index 8e8653b24645b..75e498b3a2e75 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fneg_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
index 6a2ef8c681736..20ba990e8bdb1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s  | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fsin_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
index bf0f65dd78cfb..9508109707cc1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fsqrt_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
index 197716809e895..7df607de5ed84 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI  %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fsub_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
index 459b6beae18e4..37971d389fe4e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
@@ -1295,8 +1295,8 @@ body: |
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[AND]]
-    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
-    ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s16) = G_TRUNC %1
@@ -1321,8 +1321,8 @@ body: |
     ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -131071
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
-    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
-    ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s16) = G_TRUNC %1
@@ -1347,8 +1347,8 @@ body: |
     ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16776961
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
-    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
-    ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s16) = G_TRUNC %1
@@ -1372,8 +1372,8 @@ body: |
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
-    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[OR]](s32)
-    ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s16) = G_TRUNC %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
index 1677838d4439a..406cbf2c35047 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
@@ -11,35 +11,41 @@ body: |
 
     ; GFX6-LABEL: name: test_intrinsic_round_s32
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX6: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+    ; GFX6: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX6: $vgpr0 = COPY [[FADD]](s32)
     ; GFX8-LABEL: name: test_intrinsic_round_s32
     ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX8: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
+    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX8: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: $vgpr0 = COPY [[FADD]](s32)
     ; GFX9-LABEL: name: test_intrinsic_round_s32
     ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX9: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
+    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX9: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: $vgpr0 = COPY [[FADD]](s32)
     %0:_(s32) = COPY $vgpr0
@@ -55,36 +61,42 @@ body: |
 
     ; GFX6-LABEL: name: test_intrinsic_round_s32_flags
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = nsz G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(one), [[COPY]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX6: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+    ; GFX6: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX6: $vgpr0 = COPY [[FADD]](s32)
     ; GFX8-LABEL: name: test_intrinsic_round_s32_flags
     ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = nsz G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(one), [[COPY]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
+    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: $vgpr0 = COPY [[FADD]](s32)
     ; GFX9-LABEL: name: test_intrinsic_round_s32_flags
     ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = nsz G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(one), [[COPY]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
+    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: $vgpr0 = COPY [[FADD]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = nsz G_INTRINSIC_ROUND %0
@@ -99,57 +111,66 @@ body: |
 
     ; GFX6-LABEL: name: test_intrinsic_round_s64
     ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; GFX6: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
     ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
-    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
-    ; GFX6: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C1]](s32), [[C2]](s32)
-    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
-    ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C3]]
-    ; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
-    ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]
-    ; GFX6: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
-    ; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C6]](s32), [[AND]](s32)
-    ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C5]], [[SUB]](s32)
-    ; GFX6: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
-    ; GFX6: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C7]]
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+    ; GFX6: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
+    ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
+    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+    ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+    ; GFX6: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
+    ; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
+    ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
+    ; GFX6: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+    ; GFX6: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
     ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]
-    ; GFX6: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
-    ; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C6]]
-    ; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C8]]
+    ; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
+    ; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
+    ; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
     ; GFX6: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
     ; GFX6: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s64), [[C]]
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[INTRINSIC_TRUNC]]
-    ; GFX6: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
-    ; GFX6: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C]]
-    ; GFX6: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT1]]
-    ; GFX6: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX6: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
+    ; GFX6: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
+    ; GFX6: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX6: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
+    ; GFX6: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 4607182418800017408
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C10]](s64)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C9]]
+    ; GFX6: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C8]]
+    ; GFX6: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT1]]
+    ; GFX6: $vgpr0_vgpr1 = COPY [[FADD1]](s64)
     ; GFX8-LABEL: name: test_intrinsic_round_s64
     ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s64), [[C]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
-    ; GFX8: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
+    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
+    ; GFX8: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4607182418800017408
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C1]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX8: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: $vgpr0_vgpr1 = COPY [[FADD1]](s64)
     ; GFX9-LABEL: name: test_intrinsic_round_s64
     ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; GFX9: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s64), [[C]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
-    ; GFX9: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+    ; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
+    ; GFX9: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
+    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4607182418800017408
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C1]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX9: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: $vgpr0_vgpr1 = COPY [[FADD1]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s64) = G_INTRINSIC_ROUND %0
     $vgpr0_vgpr1 = COPY %1
@@ -164,57 +185,66 @@ body: |
     ; GFX6-LABEL: name: test_intrinsic_round_v2s32
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
-    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX6: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
+    ; GFX6: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX6: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
-    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
-    ; GFX6: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s32), [[INTRINSIC_TRUNC1]]
-    ; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[C1]], [[C]]
+    ; GFX6: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
+    ; GFX6: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[FSUB1]]
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s32), [[C1]]
+    ; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C]]
     ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
     ; GFX6: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; GFX8-LABEL: name: test_intrinsic_round_v2s32
     ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
-    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX8: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
+    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX8: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
-    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
-    ; GFX8: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s32), [[INTRINSIC_TRUNC1]]
-    ; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[C1]], [[C]]
+    ; GFX8: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
+    ; GFX8: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[FSUB1]]
+    ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s32), [[C1]]
+    ; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C]]
     ; GFX8: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
     ; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; GFX9-LABEL: name: test_intrinsic_round_v2s32
     ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
-    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s32), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX9: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
+    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
+    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX9: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
-    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
-    ; GFX9: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s32), [[INTRINSIC_TRUNC1]]
-    ; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s1), [[C1]], [[C]]
+    ; GFX9: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
+    ; GFX9: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[FSUB1]]
+    ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s32), [[C1]]
+    ; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C]]
     ; GFX9: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
     ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -232,91 +262,106 @@ body: |
     ; GFX6-LABEL: name: test_intrinsic_round_v2s64
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; GFX6: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
-    ; GFX6: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
     ; GFX6: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
-    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
-    ; GFX6: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C1]](s32), [[C2]](s32)
-    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
-    ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C3]]
-    ; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
-    ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C4]]
-    ; GFX6: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
-    ; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C6]](s32), [[AND]](s32)
-    ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C5]], [[SUB]](s32)
-    ; GFX6: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
-    ; GFX6: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C7]]
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+    ; GFX6: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
+    ; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
+    ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
+    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+    ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+    ; GFX6: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
+    ; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
+    ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
+    ; GFX6: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+    ; GFX6: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
     ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]]
-    ; GFX6: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
-    ; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C6]]
-    ; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C8]]
+    ; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
+    ; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
+    ; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
     ; GFX6: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
     ; GFX6: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s64), [[C]]
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[INTRINSIC_TRUNC]]
-    ; GFX6: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
-    ; GFX6: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C]]
-    ; GFX6: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT1]]
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX6: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
+    ; GFX6: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
+    ; GFX6: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX6: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
+    ; GFX6: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 4607182418800017408
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C10]](s64)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C9]]
+    ; GFX6: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C8]]
+    ; GFX6: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT1]]
     ; GFX6: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
-    ; GFX6: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C1]](s32), [[C2]](s32)
-    ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C3]]
-    ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C4]]
-    ; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C6]](s32), [[AND3]](s32)
-    ; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C5]], [[SUB1]](s32)
-    ; GFX6: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C7]]
-    ; GFX6: [[AND4:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]
-    ; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C6]]
-    ; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C8]]
-    ; GFX6: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND4]]
+    ; GFX6: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
+    ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]
+    ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+    ; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND2]](s32)
+    ; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32)
+    ; GFX6: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]]
+    ; GFX6: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]
+    ; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]]
+    ; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]]
+    ; GFX6: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND3]]
     ; GFX6: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT2]]
     ; GFX6: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
-    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s64), [[C]]
-    ; GFX6: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[INTRINSIC_TRUNC1]]
-    ; GFX6: [[AND5:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX6: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s1), [[C9]], [[C]]
-    ; GFX6: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT3]]
-    ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
+    ; GFX6: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX6: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
+    ; GFX6: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[FADD2]]
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C10]](s64)
+    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s64), [[C9]]
+    ; GFX6: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C8]]
+    ; GFX6: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT3]]
+    ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD1]](s64), [[FADD3]](s64)
     ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; GFX8-LABEL: name: test_intrinsic_round_v2s64
     ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; GFX8: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
-    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s64), [[C]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
+    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
+    ; GFX8: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4607182418800017408
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C1]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX8: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
-    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s64), [[C]]
-    ; GFX8: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[INTRINSIC_TRUNC1]]
-    ; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX8: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s1), [[C1]], [[C]]
-    ; GFX8: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
-    ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
+    ; GFX8: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX8: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
+    ; GFX8: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[FADD2]]
+    ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s64), [[C1]]
+    ; GFX8: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C]]
+    ; GFX8: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD1]](s64), [[FADD3]](s64)
     ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; GFX9-LABEL: name: test_intrinsic_round_v2s64
     ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
-    ; GFX9: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s64), [[C]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
+    ; GFX9: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
+    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4607182418800017408
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C1]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX9: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
-    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s64), [[C]]
-    ; GFX9: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[INTRINSIC_TRUNC1]]
-    ; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s1), [[C1]], [[C]]
-    ; GFX9: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
-    ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
+    ; GFX9: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX9: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
+    ; GFX9: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[FADD2]]
+    ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
+    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s64), [[C1]]
+    ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C]]
+    ; GFX9: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD1]](s64), [[FADD3]](s64)
     ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     %1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
@@ -332,50 +377,60 @@ body: |
     ; GFX6-LABEL: name: test_intrinsic_round_s16
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; GFX6: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX6: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
     ; GFX6: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
     ; GFX6: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT1]](s32), [[FPEXT2]]
-    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT3]](s32), [[FPEXT4]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C1]], [[C]]
+    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
+    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
+    ; GFX6: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C2]](s16)
+    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
+    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
     ; GFX6: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
     ; GFX6: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT]](s16)
-    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
-    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
-    ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
+    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
+    ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC2]](s16)
     ; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
     ; GFX8-LABEL: name: test_intrinsic_round_s16
     ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; GFX8: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
-    ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX8: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C2]](s16)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
     ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
     ; GFX9-LABEL: name: test_intrinsic_round_s16
     ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; GFX9: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C1]], [[C]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
-    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
+    ; GFX9: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX9: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C2]](s16)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C]]
+    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
     ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s16) = G_TRUNC %0
@@ -397,40 +452,47 @@ body: |
     ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
-    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX6: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
     ; GFX6: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
     ; GFX6: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT1]](s32), [[FPEXT2]]
-    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT3]](s32), [[FPEXT4]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
+    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
+    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX6: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
+    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
     ; GFX6: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
     ; GFX6: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT]](s16)
-    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
-    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
     ; GFX6: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
     ; GFX6: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
-    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+    ; GFX6: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+    ; GFX6: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC3]]
     ; GFX6: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT8]](s32), [[FPEXT9]]
-    ; GFX6: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
-    ; GFX6: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT10]](s32), [[FPEXT11]]
-    ; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX6: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX6: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
+    ; GFX6: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG1]](s16)
+    ; GFX6: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT8]], [[FPEXT9]]
+    ; GFX6: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
+    ; GFX6: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC4]]
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FABS1]](s16)
+    ; GFX6: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT10]](s32), [[FPEXT11]]
+    ; GFX6: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX6: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC3]](s16)
     ; GFX6: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT1]](s16)
-    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
-    ; GFX6: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
-    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
-    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC3]](s16)
+    ; GFX6: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
+    ; GFX6: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
+    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
+    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC5]](s16)
     ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX6: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -442,22 +504,27 @@ body: |
     ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
-    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C1]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C2]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
+    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
-    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC1]](s16), [[C1]]
-    ; GFX8: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC1]](s16), [[INTRINSIC_TRUNC1]]
-    ; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
-    ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
-    ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FADD1]](s16)
+    ; GFX8: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX8: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[TRUNC1]], [[FNEG1]]
+    ; GFX8: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FADD2]]
+    ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C2]]
+    ; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX8: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD1]](s16)
+    ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FADD3]](s16)
     ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX8: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -469,22 +536,27 @@ body: |
     ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
     ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
-    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C1]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C2]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
+    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
-    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC1]](s16), [[C1]]
-    ; GFX9: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC1]](s16), [[INTRINSIC_TRUNC1]]
-    ; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
-    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
-    ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
+    ; GFX9: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX9: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[TRUNC1]], [[FNEG1]]
+    ; GFX9: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FADD2]]
+    ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C2]]
+    ; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX9: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
+    ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD3]](s16)
     ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
     ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $vgpr0
@@ -512,61 +584,71 @@ body: |
     ; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
     ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
-    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX6: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
     ; GFX6: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
     ; GFX6: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT1]](s32), [[FPEXT2]]
-    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT3]](s32), [[FPEXT4]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
+    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
+    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX6: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
+    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
     ; GFX6: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
     ; GFX6: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT]](s16)
-    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
-    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
     ; GFX6: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
     ; GFX6: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
-    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+    ; GFX6: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+    ; GFX6: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC3]]
     ; GFX6: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT8]](s32), [[FPEXT9]]
-    ; GFX6: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
-    ; GFX6: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT10]](s32), [[FPEXT11]]
-    ; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX6: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX6: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
+    ; GFX6: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG1]](s16)
+    ; GFX6: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT8]], [[FPEXT9]]
+    ; GFX6: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
+    ; GFX6: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC4]]
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FABS1]](s16)
+    ; GFX6: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT10]](s32), [[FPEXT11]]
+    ; GFX6: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX6: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC3]](s16)
     ; GFX6: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT1]](s16)
-    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
-    ; GFX6: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
+    ; GFX6: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
+    ; GFX6: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
     ; GFX6: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
     ; GFX6: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT14]]
-    ; GFX6: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
+    ; GFX6: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
+    ; GFX6: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC6]]
     ; GFX6: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
-    ; GFX6: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT15]](s32), [[FPEXT16]]
-    ; GFX6: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
-    ; GFX6: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC4]](s16)
-    ; GFX6: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT17]](s32), [[FPEXT18]]
-    ; GFX6: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP4]], [[FCMP5]]
-    ; GFX6: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[AND2]](s1), [[C2]], [[C1]]
-    ; GFX6: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC4]](s16)
+    ; GFX6: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG2]](s16)
+    ; GFX6: [[FADD4:%[0-9]+]]:_(s32) = G_FADD [[FPEXT15]], [[FPEXT16]]
+    ; GFX6: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD4]](s32)
+    ; GFX6: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC7]]
+    ; GFX6: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[FABS2]](s16)
+    ; GFX6: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT17]](s32), [[FPEXT18]]
+    ; GFX6: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[COPY3]], [[C1]]
+    ; GFX6: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
     ; GFX6: [[FPEXT20:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT2]](s16)
-    ; GFX6: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT19]], [[FPEXT20]]
-    ; GFX6: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
-    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
-    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC3]](s16)
+    ; GFX6: [[FADD5:%[0-9]+]]:_(s32) = G_FADD [[FPEXT19]], [[FPEXT20]]
+    ; GFX6: [[FPTRUNC8:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD5]](s32)
+    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
+    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC5]](s16)
     ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
-    ; GFX6: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC5]](s16)
-    ; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C]](s32)
+    ; GFX6: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC8]](s16)
+    ; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C]](s32)
     ; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
     ; GFX6: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
     ; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
@@ -587,34 +669,41 @@ body: |
     ; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
     ; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
-    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C1]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C2]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
+    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
-    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC1]](s16), [[C1]]
-    ; GFX8: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC1]](s16), [[INTRINSIC_TRUNC1]]
-    ; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX8: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX8: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[TRUNC1]], [[FNEG1]]
+    ; GFX8: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FADD2]]
+    ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C2]]
+    ; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX8: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX8: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
-    ; GFX8: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC2]](s16), [[C1]]
-    ; GFX8: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC2]](s16), [[INTRINSIC_TRUNC2]]
-    ; GFX8: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP4]], [[FCMP5]]
-    ; GFX8: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[AND2]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
-    ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
-    ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FADD1]](s16)
+    ; GFX8: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC2]]
+    ; GFX8: [[FADD4:%[0-9]+]]:_(s16) = G_FADD [[TRUNC2]], [[FNEG2]]
+    ; GFX8: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FADD4]]
+    ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C2]]
+    ; GFX8: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[COPY3]], [[C1]]
+    ; GFX8: [[FADD5:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
+    ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD1]](s16)
+    ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FADD3]](s16)
     ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
-    ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD2]](s16)
-    ; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C]](s32)
+    ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD5]](s16)
+    ; GFX8: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C]](s32)
     ; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
     ; GFX8: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
     ; GFX8: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
@@ -635,30 +724,37 @@ body: |
     ; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
     ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
-    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C1]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C2]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
+    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
-    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC1]](s16), [[C1]]
-    ; GFX9: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC1]](s16), [[INTRINSIC_TRUNC1]]
-    ; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX9: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX9: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[TRUNC1]], [[FNEG1]]
+    ; GFX9: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FADD2]]
+    ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C2]]
+    ; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX9: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX9: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
-    ; GFX9: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC2]](s16), [[C1]]
-    ; GFX9: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC2]](s16), [[INTRINSIC_TRUNC2]]
-    ; GFX9: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP4]], [[FCMP5]]
-    ; GFX9: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[AND2]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
-    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
-    ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
+    ; GFX9: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC2]]
+    ; GFX9: [[FADD4:%[0-9]+]]:_(s16) = G_FADD [[TRUNC2]], [[FNEG2]]
+    ; GFX9: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FADD4]]
+    ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C2]]
+    ; GFX9: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[COPY3]], [[C1]]
+    ; GFX9: [[FADD5:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
+    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
+    ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD3]](s16)
     ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
-    ; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD2]](s16)
+    ; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD5]](s16)
     ; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
     ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[DEF1]](s32)
     ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
@@ -691,75 +787,88 @@ body: |
     ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
     ; GFX6: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
-    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX6: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
     ; GFX6: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
     ; GFX6: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
+    ; GFX6: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
     ; GFX6: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT1]](s32), [[FPEXT2]]
-    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
-    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
-    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT3]](s32), [[FPEXT4]]
-    ; GFX6: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
+    ; GFX6: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
+    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX6: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX6: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX6: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
+    ; GFX6: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
     ; GFX6: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
     ; GFX6: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT]](s16)
-    ; GFX6: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
-    ; GFX6: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
     ; GFX6: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
     ; GFX6: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
-    ; GFX6: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+    ; GFX6: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
+    ; GFX6: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC3]]
     ; GFX6: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT8]](s32), [[FPEXT9]]
-    ; GFX6: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
-    ; GFX6: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
-    ; GFX6: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT10]](s32), [[FPEXT11]]
-    ; GFX6: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX6: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX6: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
+    ; GFX6: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG1]](s16)
+    ; GFX6: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT8]], [[FPEXT9]]
+    ; GFX6: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
+    ; GFX6: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC4]]
+    ; GFX6: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FABS1]](s16)
+    ; GFX6: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT10]](s32), [[FPEXT11]]
+    ; GFX6: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX6: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC3]](s16)
     ; GFX6: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT1]](s16)
-    ; GFX6: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
-    ; GFX6: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
+    ; GFX6: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
+    ; GFX6: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
     ; GFX6: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
     ; GFX6: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT14]]
-    ; GFX6: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
+    ; GFX6: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
+    ; GFX6: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC6]]
     ; GFX6: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
-    ; GFX6: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT15]](s32), [[FPEXT16]]
-    ; GFX6: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
-    ; GFX6: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC4]](s16)
-    ; GFX6: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT17]](s32), [[FPEXT18]]
-    ; GFX6: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP4]], [[FCMP5]]
-    ; GFX6: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[AND2]](s1), [[C2]], [[C1]]
-    ; GFX6: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC4]](s16)
+    ; GFX6: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG2]](s16)
+    ; GFX6: [[FADD4:%[0-9]+]]:_(s32) = G_FADD [[FPEXT15]], [[FPEXT16]]
+    ; GFX6: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD4]](s32)
+    ; GFX6: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC7]]
+    ; GFX6: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[FABS2]](s16)
+    ; GFX6: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT17]](s32), [[FPEXT18]]
+    ; GFX6: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[COPY3]], [[C1]]
+    ; GFX6: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
     ; GFX6: [[FPEXT20:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT2]](s16)
-    ; GFX6: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT19]], [[FPEXT20]]
-    ; GFX6: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
+    ; GFX6: [[FADD5:%[0-9]+]]:_(s32) = G_FADD [[FPEXT19]], [[FPEXT20]]
+    ; GFX6: [[FPTRUNC8:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD5]](s32)
     ; GFX6: [[FPEXT21:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
     ; GFX6: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT21]]
-    ; GFX6: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC3]](s32)
+    ; GFX6: [[FPTRUNC9:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC3]](s32)
+    ; GFX6: [[FNEG3:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC9]]
     ; GFX6: [[FPEXT22:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
-    ; GFX6: [[FPEXT23:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
-    ; GFX6: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FPEXT22]](s32), [[FPEXT23]]
-    ; GFX6: [[FPEXT24:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
-    ; GFX6: [[FPEXT25:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
-    ; GFX6: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[FPEXT24]](s32), [[FPEXT25]]
-    ; GFX6: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
-    ; GFX6: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[AND3]](s1), [[C2]], [[C1]]
-    ; GFX6: [[FPEXT26:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
+    ; GFX6: [[FPEXT23:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG3]](s16)
+    ; GFX6: [[FADD6:%[0-9]+]]:_(s32) = G_FADD [[FPEXT22]], [[FPEXT23]]
+    ; GFX6: [[FPTRUNC10:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD6]](s32)
+    ; GFX6: [[FABS3:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC10]]
+    ; GFX6: [[COPY4:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX6: [[FPEXT24:%[0-9]+]]:_(s32) = G_FPEXT [[FABS3]](s16)
+    ; GFX6: [[FPEXT25:%[0-9]+]]:_(s32) = G_FPEXT [[C2]](s16)
+    ; GFX6: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FPEXT24]](s32), [[FPEXT25]]
+    ; GFX6: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[FCMP3]](s1), [[COPY4]], [[C1]]
+    ; GFX6: [[FPEXT26:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC9]](s16)
     ; GFX6: [[FPEXT27:%[0-9]+]]:_(s32) = G_FPEXT [[SELECT3]](s16)
-    ; GFX6: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT26]], [[FPEXT27]]
-    ; GFX6: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
-    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC1]](s16)
-    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC3]](s16)
+    ; GFX6: [[FADD7:%[0-9]+]]:_(s32) = G_FADD [[FPEXT26]], [[FPEXT27]]
+    ; GFX6: [[FPTRUNC11:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD7]](s32)
+    ; GFX6: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
+    ; GFX6: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC5]](s16)
     ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
-    ; GFX6: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC5]](s16)
-    ; GFX6: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC7]](s16)
+    ; GFX6: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC8]](s16)
+    ; GFX6: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC11]](s16)
     ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
     ; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
     ; GFX6: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -777,39 +886,48 @@ body: |
     ; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
     ; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
-    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX8: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C1]]
-    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX8: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX8: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX8: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX8: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX8: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C2]]
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
+    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX8: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
-    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC1]](s16), [[C1]]
-    ; GFX8: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC1]](s16), [[INTRINSIC_TRUNC1]]
-    ; GFX8: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX8: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX8: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[TRUNC1]], [[FNEG1]]
+    ; GFX8: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FADD2]]
+    ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C2]]
+    ; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX8: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX8: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
-    ; GFX8: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC2]](s16), [[C1]]
-    ; GFX8: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC2]](s16), [[INTRINSIC_TRUNC2]]
-    ; GFX8: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP4]], [[FCMP5]]
-    ; GFX8: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[AND2]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
+    ; GFX8: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC2]]
+    ; GFX8: [[FADD4:%[0-9]+]]:_(s16) = G_FADD [[TRUNC2]], [[FNEG2]]
+    ; GFX8: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FADD4]]
+    ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C2]]
+    ; GFX8: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[COPY3]], [[C1]]
+    ; GFX8: [[FADD5:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
     ; GFX8: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC3]]
-    ; GFX8: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC3]](s16), [[C1]]
-    ; GFX8: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC3]](s16), [[INTRINSIC_TRUNC3]]
-    ; GFX8: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
-    ; GFX8: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[AND3]](s1), [[C2]], [[C1]]
-    ; GFX8: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC3]], [[SELECT3]]
-    ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
-    ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FADD1]](s16)
+    ; GFX8: [[FNEG3:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC3]]
+    ; GFX8: [[FADD6:%[0-9]+]]:_(s16) = G_FADD [[TRUNC3]], [[FNEG3]]
+    ; GFX8: [[FABS3:%[0-9]+]]:_(s16) = G_FABS [[FADD6]]
+    ; GFX8: [[COPY4:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX8: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS3]](s16), [[C2]]
+    ; GFX8: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[FCMP3]](s1), [[COPY4]], [[C1]]
+    ; GFX8: [[FADD7:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC3]], [[SELECT3]]
+    ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD1]](s16)
+    ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[FADD3]](s16)
     ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
     ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
     ; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
-    ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD2]](s16)
-    ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[FADD3]](s16)
+    ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD5]](s16)
+    ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[FADD7]](s16)
     ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
     ; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
     ; GFX8: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -827,37 +945,46 @@ body: |
     ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
     ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
     ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
-    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
     ; GFX9: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
-    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC]](s16), [[C1]]
-    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC]](s16), [[INTRINSIC_TRUNC]]
-    ; GFX9: [[AND:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[AND]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
+    ; GFX9: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC]]
+    ; GFX9: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[FNEG]]
+    ; GFX9: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FADD]]
+    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3800
+    ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 15360
+    ; GFX9: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C2]]
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[COPY1]], [[C1]]
+    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[SELECT]]
     ; GFX9: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
-    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC1]](s16), [[C1]]
-    ; GFX9: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC1]](s16), [[INTRINSIC_TRUNC1]]
-    ; GFX9: [[AND1:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
-    ; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[AND1]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
+    ; GFX9: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC1]]
+    ; GFX9: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[TRUNC1]], [[FNEG1]]
+    ; GFX9: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FADD2]]
+    ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C2]]
+    ; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](s1), [[COPY2]], [[C1]]
+    ; GFX9: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[SELECT1]]
     ; GFX9: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
-    ; GFX9: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC2]](s16), [[C1]]
-    ; GFX9: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC2]](s16), [[INTRINSIC_TRUNC2]]
-    ; GFX9: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP4]], [[FCMP5]]
-    ; GFX9: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[AND2]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
+    ; GFX9: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC2]]
+    ; GFX9: [[FADD4:%[0-9]+]]:_(s16) = G_FADD [[TRUNC2]], [[FNEG2]]
+    ; GFX9: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FADD4]]
+    ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C2]]
+    ; GFX9: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[COPY3]], [[C1]]
+    ; GFX9: [[FADD5:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[SELECT2]]
     ; GFX9: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC3]]
-    ; GFX9: [[FCMP6:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[TRUNC3]](s16), [[C1]]
-    ; GFX9: [[FCMP7:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[TRUNC3]](s16), [[INTRINSIC_TRUNC3]]
-    ; GFX9: [[AND3:%[0-9]+]]:_(s1) = G_AND [[FCMP6]], [[FCMP7]]
-    ; GFX9: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[AND3]](s1), [[C2]], [[C1]]
-    ; GFX9: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC3]], [[SELECT3]]
-    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
-    ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
+    ; GFX9: [[FNEG3:%[0-9]+]]:_(s16) = G_FNEG [[INTRINSIC_TRUNC3]]
+    ; GFX9: [[FADD6:%[0-9]+]]:_(s16) = G_FADD [[TRUNC3]], [[FNEG3]]
+    ; GFX9: [[FABS3:%[0-9]+]]:_(s16) = G_FABS [[FADD6]]
+    ; GFX9: [[COPY4:%[0-9]+]]:_(s16) = COPY [[C3]](s16)
+    ; GFX9: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS3]](s16), [[C2]]
+    ; GFX9: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[FCMP3]](s1), [[COPY4]], [[C1]]
+    ; GFX9: [[FADD7:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC3]], [[SELECT3]]
+    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
+    ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD3]](s16)
     ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
-    ; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD2]](s16)
-    ; GFX9: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD3]](s16)
+    ; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD5]](s16)
+    ; GFX9: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD7]](s16)
     ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[ANYEXT3]](s32)
     ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
     ; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
new file mode 100644
index 0000000000000..7f40f1c665104
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
@@ -0,0 +1,1201 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
+
+define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_swap_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_swap_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_add_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_sub_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_sub_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_smin_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_smin_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+
+define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_umin_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_umin_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_smax_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_smax_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_umax_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_umax_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_and_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_and_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_or_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_or_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_xor_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_xor_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_inc_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_inc_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_dec_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_dec_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s) {
+  ; GFX9-LABEL: name: atomic_cmpswap_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[COPY8]](s32), [[COPY9]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_cmpswap_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[COPY8]](s32), [[COPY9]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i16(i32 %cmp, i32 %swap, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t) {
+  ; GFX9-LABEL: name: atomic_add_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32 %data, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %r) {
+  ; GFX9-LABEL: name: atomic_add_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i16(i32 %data, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %face) {
+  ; GFX9-LABEL: name: atomic_add_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i16(i32 %data, i16 %s, i16 %t, i16 %face, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %slice) {
+  ; GFX9-LABEL: name: atomic_add_1darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_1darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32 %data, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %slice) {
+  ; GFX9-LABEL: name: atomic_add_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %fragid) {
+  ; GFX9-LABEL: name: atomic_add_2dmsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_2dmsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
+  ; GFX9-LABEL: name: atomic_add_2darraymsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_2darraymsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i16(i32 %data, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
+  ; GFX9-LABEL: name: atomic_add_1d_slc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_add_1d_slc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](s32), [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t) {
+  ; GFX9-LABEL: name: atomic_cmpswap_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_cmpswap_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.2d.i32.i16(i32 %cmp, i32 %swap, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t, i16 %r) {
+  ; GFX9-LABEL: name: atomic_cmpswap_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[COPY8]](s32), [[COPY9]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_cmpswap_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.3d.i32.i16(i32 %cmp, i32 %swap, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
+  ; GFX9-LABEL: name: atomic_cmpswap_2darraymsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[COPY8]](s32), [[COPY9]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: atomic_cmpswap_2darraymsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (volatile dereferenceable load store 4 on custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.2darraymsaa.i32.i16(i32 %cmp, i32 %swap, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  %out = bitcast i32 %v to float
+  ret float %out
+}
+
+declare i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.and.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.or.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i16(i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i16(i32, i32, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.2d.i32.i16(i32, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.3d.i32.i16(i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.cube.i32.i16(i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i16(i32, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i16(i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i16(i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.2d.i32.i16(i32, i32, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.3d.i32.i16(i32, i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.cube.i32.i16(i32, i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.1darray.i32.i16(i32, i32, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.2darray.i32.i16(i32, i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.2dmsaa.i32.i16(i32, i32, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+declare i32 @llvm.amdgcn.image.atomic.cmpswap.2darraymsaa.i32.i16(i32, i32, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
+
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
new file mode 100644
index 0000000000000..aee2404071937
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
@@ -0,0 +1,3281 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+r128-a16 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
+
+define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %t = extractelement <2 x i16> %coords, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %r = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.cube), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_1darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %slice = extractelement <2 x i16> %coords, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_2dmsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2dmsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2dmsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2dmsaa), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %fragid = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_2darraymsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2darraymsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %fragid = extractelement <2 x i16> %coords_hi, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_mip_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_mip_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %mip = extractelement <2 x i16> %coords, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_mip_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_mip_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %mip = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_mip_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_mip_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %r = extractelement <2 x i16> %coords_hi, i32 0
+  %mip = extractelement <2 x i16> %coords_hi, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_mip_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_mip_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %mip = extractelement <2 x i16> %coords_hi, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_mip_1darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_mip_1darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %slice = extractelement <2 x i16> %coords_lo, i32 1
+  %mip = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_mip_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_mip_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %mip = extractelement <2 x i16> %coords_hi, i32 1
+  %v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %t = extractelement <2 x i16> %coords, i32 1
+  call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %r = extractelement <2 x i16> %coords_hi, i32 0
+  call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  call void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %slice = extractelement <2 x i16> %coords, i32 1
+  call void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  call void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_2dmsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2dmsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_2dmsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2dmsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %fragid = extractelement <2 x i16> %coords_hi, i32 0
+  call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_2darraymsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darraymsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_2darraymsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darraymsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %fragid = extractelement <2 x i16> %coords_hi, i32 1
+  call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_mip_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_mip_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %mip = extractelement <2 x i16> %coords, i32 1
+  call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_mip_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_mip_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %mip = extractelement <2 x i16> %coords_hi, i32 0
+  call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_mip_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_mip_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %r = extractelement <2 x i16> %coords_hi, i32 0
+  %mip = extractelement <2 x i16> %coords_hi, i32 1
+  call void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_mip_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_mip_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %mip = extractelement <2 x i16> %coords_hi, i32 1
+  call void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_mip_1darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_mip_1darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %slice = extractelement <2 x i16> %coords_lo, i32 1
+  %mip = extractelement <2 x i16> %coords_hi, i32 0
+  call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: store_mip_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_mip_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %mip = extractelement <2 x i16> %coords_hi, i32 1
+  call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_1d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_1d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_3d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_3d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_1darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_1darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_2dmsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_2dmsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_2darraymsaa
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_2darraymsaa
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d_V1
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GFX9:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: load_1d_V1
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  ret float %v
+}
+
+define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d_V2
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; GFX10NSA-LABEL: name: load_1d_V2
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <2 x float> %v
+}
+
+define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1d_V1
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](s32), 2, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1d_V1
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](s32), 2, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1d_V2
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x s32>), 12, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1d_V2
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x s32>), 12, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d_glc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_1d_glc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d_slc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_1d_slc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d_glc_slc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_1d_glc_slc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1d_glc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1d_glc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 1 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
+  ret void
+}
+
+define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1d_slc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1d_slc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 2 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
+  ret void
+}
+
+define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: store_1d_glc_slc
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX9:   S_ENDPGM 0
+  ; GFX10NSA-LABEL: name: store_1d_glc_slc
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 3 :: (dereferenceable store 16 into custom "TargetCustom8")
+  ; GFX10NSA:   S_ENDPGM 0
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
+  ret void
+}
+
+define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: getresinfo_dmask0
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: getresinfo_dmask0
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %mip = extractelement <2 x i16> %coords, i32 0
+  %r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %r
+}
+
+define amdgpu_ps <4 x float> @load_1d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_1d_tfe
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX9:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_1d_tfe
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX10NSA:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 1, i32 0)
+  %data = extractvalue { <4 x float>, i32 } %v, 0
+  %tfe = extractvalue { <4 x float>, i32 } %v, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %data
+}
+
+define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
+  ; GFX9-LABEL: name: load_2d_tfe
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX9:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2d_tfe
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX10NSA:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords, i32 0
+  %t = extractelement <2 x i16> %coords, i32 1
+  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %data = extractvalue { <4 x float>, i32 } %v, 0
+  %tfe = extractvalue { <4 x float>, i32 } %v, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %data
+}
+
+define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_3d_tfe
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF1]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX9:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_3d_tfe
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF1]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX10NSA:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %r = extractelement <2 x i16> %coords_hi, i32 0
+  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 1, i32 0)
+  %data = extractvalue { <4 x float>, i32 } %v, 0
+  %tfe = extractvalue { <4 x float>, i32 } %v, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %data
+}
+
+define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
+  ; GFX9-LABEL: name: load_2darraymsaa_tfe
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX9:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX9:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX9:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX9:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX9:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2darraymsaa_tfe
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
+  ; GFX10NSA:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; GFX10NSA:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+  ; GFX10NSA:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
+  ; GFX10NSA:   [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX10NSA:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %s = extractelement <2 x i16> %coords_lo, i32 0
+  %t = extractelement <2 x i16> %coords_lo, i32 1
+  %slice = extractelement <2 x i16> %coords_hi, i32 0
+  %fragid = extractelement <2 x i16> %coords_hi, i32 1
+  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
+  %data = extractvalue { <4 x float>, i32 } %v, 0
+  %tfe = extractvalue { <4 x float>, i32 } %v, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %data
+}
+
+declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float>, i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float>, i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float>, i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #3
+declare float @llvm.amdgcn.image.load.1d.f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare float @llvm.amdgcn.image.load.2d.f32.i16(i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare void @llvm.amdgcn.image.store.1d.f32.i16(float, i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float>, i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #2
+declare { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i16(i32 immarg, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i16(i32 immarg, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+attributes #2 = { nounwind writeonly }
+attributes #3 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
index c0338b42a9b38..d9d83883ed011 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
@@ -17,8 +17,9 @@ define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
   ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
-  ; UNPACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
+  ; UNPACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)
   ; UNPACKED:   $vgpr0 = COPY [[ANYEXT]](s32)
   ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
   ; PACKED-LABEL: name: image_load_f16
@@ -35,8 +36,9 @@ define amdgpu_ps half @image_load_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
   ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; PACKED:   [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
-  ; PACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s16) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
+  ; PACKED:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AMDGPU_INTRIN_IMAGE_LOAD]](s16)
   ; PACKED:   $vgpr0 = COPY [[ANYEXT]](s32)
   ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -58,8 +60,9 @@ define amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32
   ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
@@ -85,8 +88,9 @@ define amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32
   ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; PACKED:   [[INT:%[0-9]+]]:_(<2 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
-  ; PACKED:   $vgpr0 = COPY [[INT]](<2 x s16>)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
   ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
   ret <2 x half> %tex
@@ -107,8 +111,9 @@ define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32
   ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
@@ -147,9 +152,14 @@ define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32
   ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; PACKED:   [[INT:%[0-9]+]]:_(<3 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
-  ; PACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[INT]](<3 x s16>), 0
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[UV1]](<2 x s16>), [[DEF]](<2 x s16>)
+  ; PACKED:   [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV2]](<3 x s16>), 0
   ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
   ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
   ; PACKED:   $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
@@ -174,8 +184,9 @@ define amdgpu_ps <4 x half> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32
   ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<4 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
@@ -209,8 +220,9 @@ define amdgpu_ps <4 x half> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32
   ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; PACKED:   [[INT:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
-  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INT]](<4 x s16>)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
   ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)
   ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)
   ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
@@ -234,8 +246,9 @@ define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t)
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
   ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; UNPACKED:   $vgpr0 = COPY [[COPY10]](s32)
@@ -255,8 +268,9 @@ define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t)
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; PACKED:   [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
-  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
   ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; PACKED:   $vgpr0 = COPY [[COPY10]](s32)
@@ -284,8 +298,9 @@ define amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s,
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
@@ -313,8 +328,9 @@ define amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s,
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; PACKED:   [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
-  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
   ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
   ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
@@ -342,8 +358,9 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s,
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<4 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
   ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
@@ -384,8 +401,9 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s,
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; PACKED:   [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
-  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
   ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
   ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
   ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
@@ -422,8 +440,9 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s,
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; UNPACKED:   [[INT:%[0-9]+]]:_(<5 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
-  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<5 x s32>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
   ; UNPACKED:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
@@ -459,8 +478,9 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s,
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; PACKED:   [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
-  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
   ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
   ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
   ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
@@ -474,6 +494,1192 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s,
   ret <4 x half> %tex
 }
 
+define amdgpu_ps half @image_load_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; UNPACKED:   $vgpr0 = COPY [[DEF]](s32)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; PACKED-LABEL: name: image_load_f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; PACKED:   $vgpr0 = COPY [[DEF]](s32)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret half %tex
+}
+
+define amdgpu_ps <2 x half> @image_load_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v2f16_dmask_1000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; PACKED-LABEL: name: image_load_v2f16_dmask_1000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <2 x half> %tex
+}
+
+define amdgpu_ps <2 x half> @image_load_v2f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v2f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   $vgpr0 = COPY [[DEF]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; PACKED-LABEL: name: image_load_v2f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   $vgpr0 = COPY [[DEF]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <2 x half> %tex
+}
+
+define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v3f16_dmask_1100
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
+  ; UNPACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; UNPACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; UNPACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v3f16_dmask_1100
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
+  ; PACKED:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0
+  ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; PACKED:   $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <3 x half> %tex
+}
+
+define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v3f16_dmask_1000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
+  ; UNPACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; UNPACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; UNPACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v3f16_dmask_1000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
+  ; PACKED:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0
+  ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; PACKED:   $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <3 x half> %tex
+}
+
+define amdgpu_ps <3 x half> @image_load_v3f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v3f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
+  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
+  ; UNPACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; UNPACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; UNPACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v3f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
+  ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; PACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; PACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <3 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1110
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
+  ; UNPACKED:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v4f16_dmask_1110
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s16>)
+  ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1100
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v4f16_dmask_1100
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[DEF]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_1000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v4f16_dmask_1000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s16>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[DEF]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_v4f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_v4f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+  ; UNPACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_v4f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+  ; PACKED:   $vgpr0 = COPY [[UV]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[UV1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps half @image_load_tfe_f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[COPY10]](s32)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; PACKED-LABEL: name: image_load_tfe_f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 2 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; PACKED:   $vgpr0 = COPY [[COPY10]](s32)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { half, i32 } %res, 0
+  %tfe = extractvalue { half, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret half %tex
+}
+
+define amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v2f16_dmask_1000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; PACKED-LABEL: name: image_load_tfe_v2f16_dmask_1000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <2 x half>, i32 } %res, 0
+  %tfe = extractvalue { <2 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <2 x half> %tex
+}
+
+define amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v2f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; PACKED-LABEL: name: image_load_tfe_v2f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <2 x half>, i32 } %res, 0
+  %tfe = extractvalue { <2 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <2 x half> %tex
+}
+
+define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v3f16_dmask_1100
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
+  ; UNPACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
+  ; UNPACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; UNPACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; UNPACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v3f16_dmask_1100
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
+  ; PACKED:   [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV2]](<3 x s16>), 0
+  ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; PACKED:   $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <3 x half>, i32 } %res, 0
+  %tfe = extractvalue { <3 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <3 x half> %tex
+}
+
+define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v3f16_dmask_1000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
+  ; UNPACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; UNPACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; UNPACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v3f16_dmask_1000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
+  ; PACKED:   [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV2]](<3 x s16>), 0
+  ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; PACKED:   $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <3 x half>, i32 } %res, 0
+  %tfe = extractvalue { <3 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <3 x half> %tex
+}
+
+define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v3f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
+  ; UNPACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; UNPACKED:   [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; UNPACKED:   $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v3f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 6 from custom "TargetCustom8", align 8)
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
+  ; PACKED:   [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV2]](<3 x s16>), 0
+  ; PACKED:   [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
+  ; PACKED:   [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
+  ; PACKED:   $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <3 x half>, i32 } %res, 0
+  %tfe = extractvalue { <3 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <3 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_1110
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; UNPACKED:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
+  ; UNPACKED:   [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_1110
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
+  ; PACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x half>, i32 } %res, 0
+  %tfe = extractvalue { <4 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_1100
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; UNPACKED:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+  ; UNPACKED:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_1100
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[DEF1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x half>, i32 } %res, 0
+  %tfe = extractvalue { <4 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_1000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_1000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[DEF1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x half>, i32 } %res, 0
+  %tfe = extractvalue { <4 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x half> %tex
+}
+
+define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; UNPACKED-LABEL: name: image_load_tfe_v4f16_dmask_0000
+  ; UNPACKED: bb.1 (%ir-block.0):
+  ; UNPACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; UNPACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; UNPACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; UNPACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; UNPACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; UNPACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; UNPACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; UNPACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; UNPACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; UNPACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; UNPACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; UNPACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+  ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+  ; UNPACKED:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+  ; UNPACKED:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; UNPACKED:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; UNPACKED:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
+  ; UNPACKED:   [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+  ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+  ; UNPACKED:   [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
+  ; UNPACKED:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
+  ; UNPACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; UNPACKED:   $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
+  ; UNPACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  ; PACKED-LABEL: name: image_load_tfe_v4f16_dmask_0000
+  ; PACKED: bb.1 (%ir-block.0):
+  ; PACKED:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; PACKED:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; PACKED:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; PACKED:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; PACKED:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; PACKED:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; PACKED:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; PACKED:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; PACKED:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; PACKED:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; PACKED:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; PACKED:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; PACKED:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
+  ; PACKED:   [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+  ; PACKED:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; PACKED:   $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+  ; PACKED:   $vgpr1 = COPY [[DEF1]](<2 x s16>)
+  ; PACKED:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x half>, i32 } %res, 0
+  %tfe = extractvalue { <4 x half>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x half> %tex
+}
+
 declare half @llvm.amdgcn.image.load.2d.f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
index 9abd7451e6de8..e7a8ca40c02a0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
@@ -16,8 +16,9 @@ define amdgpu_ps float @image_load_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
   ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; GCN:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
-  ; GCN:   $vgpr0 = COPY [[INT]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
   ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
   %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
   ret float %tex
@@ -38,8 +39,9 @@ define amdgpu_ps <2 x float> @image_load_v2f32(<8 x i32> inreg %rsrc, i32 %s, i3
   ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; GCN:   [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   $vgpr1 = COPY [[UV1]](s32)
   ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
@@ -62,8 +64,9 @@ define amdgpu_ps <3 x float> @image_load_v3f32(<8 x i32> inreg %rsrc, i32 %s, i3
   ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; GCN:   [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   $vgpr1 = COPY [[UV1]](s32)
   ; GCN:   $vgpr2 = COPY [[UV2]](s32)
@@ -87,8 +90,9 @@ define amdgpu_ps <4 x float> @image_load_v4f32(<8 x i32> inreg %rsrc, i32 %s, i3
   ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; GCN:   [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<4 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   $vgpr1 = COPY [[UV1]](s32)
   ; GCN:   $vgpr2 = COPY [[UV2]](s32)
@@ -114,8 +118,9 @@ define amdgpu_ps float @image_load_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; GCN:   [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
   ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -142,8 +147,9 @@ define amdgpu_ps <2 x float> @image_load_tfe_v2f32(<8 x i32> inreg %rsrc, i32 %s
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; GCN:   [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
   ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   $vgpr1 = COPY [[UV1]](s32)
@@ -171,8 +177,9 @@ define amdgpu_ps <3 x float> @image_load_tfe_v3f32(<8 x i32> inreg %rsrc, i32 %s
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; GCN:   [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<4 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
   ; GCN:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   $vgpr1 = COPY [[UV1]](s32)
@@ -201,8 +208,9 @@ define amdgpu_ps <4 x float> @image_load_tfe_v4f32(<8 x i32> inreg %rsrc, i32 %s
   ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
-  ; GCN:   [[INT:%[0-9]+]]:_(<5 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
-  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<5 x s32>)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
   ; GCN:   G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
   ; GCN:   $vgpr0 = COPY [[UV]](s32)
   ; GCN:   $vgpr1 = COPY [[UV1]](s32)
@@ -216,6 +224,579 @@ define amdgpu_ps <4 x float> @image_load_tfe_v4f32(<8 x i32> inreg %rsrc, i32 %s
   ret <4 x float> %tex
 }
 
+define amdgpu_ps float @image_load_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret float %tex
+}
+
+define amdgpu_ps <2 x float> @image_load_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v2f32_dmask_1000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <2 x float> %tex
+}
+
+define amdgpu_ps <2 x float> @image_load_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v2f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <2 x float> %tex
+}
+
+define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v3f32_dmask_1100
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
+  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <3 x float> %tex
+}
+
+define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v3f32_dmask_1000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
+  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <3 x float> %tex
+}
+
+define amdgpu_ps <3 x float> @image_load_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v3f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
+  %tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <3 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v4f32_dmask_1110
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v4f32_dmask_1100
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v4f32_dmask_1000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_v4f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
+  ; GCN:   $vgpr3 = COPY [[UV3]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps float @image_load_tfe_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { float, i32 } %res, 0
+  %tfe = extractvalue { float, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret float %tex
+}
+
+define amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v2f32_dmask_1000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <2 x float>, i32 } %res, 0
+  %tfe = extractvalue { <2 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <2 x float> %tex
+}
+
+define amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v2f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
+  %res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <2 x float>, i32 } %res, 0
+  %tfe = extractvalue { <2 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <2 x float> %tex
+}
+
+define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v3f32_dmask_1100
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
+  %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <3 x float>, i32 } %res, 0
+  %tfe = extractvalue { <3 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <3 x float> %tex
+}
+
+define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v3f32_dmask_1000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
+  %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <3 x float>, i32 } %res, 0
+  %tfe = extractvalue { <3 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <3 x float> %tex
+}
+
+define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v3f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
+  %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <3 x float>, i32 } %res, 0
+  %tfe = extractvalue { <3 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <3 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1110
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[UV2]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x float>, i32 } %res, 0
+  %tfe = extractvalue { <4 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1100
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[UV1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x float>, i32 } %res, 0
+  %tfe = extractvalue { <4 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x float>, i32 } %res, 0
+  %tfe = extractvalue { <4 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %tex
+}
+
+define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  ; GCN-LABEL: name: image_load_tfe_v4f32_dmask_0000
+  ; GCN: bb.1 (%ir-block.0):
+  ; GCN:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
+  ; GCN:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GCN:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GCN:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GCN:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GCN:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GCN:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GCN:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GCN:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GCN:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GCN:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GCN:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GCN:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GCN:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; GCN:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GCN:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GCN:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GCN:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GCN:   $vgpr0 = COPY [[UV]](s32)
+  ; GCN:   $vgpr1 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr2 = COPY [[DEF1]](s32)
+  ; GCN:   $vgpr3 = COPY [[DEF1]](s32)
+  ; GCN:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { <4 x float>, i32 } %res, 0
+  %tfe = extractvalue { <4 x float>, i32 } %res, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret <4 x float> %tex
+}
+
 declare float @llvm.amdgcn.image.load.2d.f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
 declare <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
new file mode 100644
index 0000000000000..c2cc48d056cf2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
+
+define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
+  ; GFX6-LABEL: name: load_2darraymsaa
+  ; GFX6: bb.1 (%ir-block.0):
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2darraymsaa
+  ; GFX10NSA: bb.1 (%ir-block.0):
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
+  ; GFX6-LABEL: name: load_2darraymsaa_tfe
+  ; GFX6: bb.1 (%ir-block.0):
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX6:   G_STORE [[UV4]](s32), [[MV]](p1) :: (store 4 into %ir.out, addrspace 1)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: load_2darraymsaa_tfe
+  ; GFX10NSA: bb.1 (%ir-block.0):
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
+  ; GFX10NSA:   G_STORE [[UV4]](s32), [[MV]](p1) :: (store 4 into %ir.out, addrspace 1)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
+  %v.vec = extractvalue { <4 x float>, i32 } %v, 0
+  %v.err = extractvalue { <4 x float>, i32 } %v, 1
+  store i32 %v.err, i32 addrspace(1)* %out, align 4
+  ret <4 x float> %v.vec
+}
+
+declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
+declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
+
+attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
new file mode 100644
index 0000000000000..519dec8e7e540
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
+
+define amdgpu_ps float @image_load_3d_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
+  ; GFX6-LABEL: name: image_load_3d_f32
+  ; GFX6: bb.1 (%ir-block.0):
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[BUILD_VECTOR1]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GFX6:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: image_load_3d_f32
+  ; GFX10NSA: bb.1 (%ir-block.0):
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GFX10NSA:   $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %tex = call float @llvm.amdgcn.image.load.3d.f32.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
+  ret float %tex
+}
+
+define amdgpu_ps float @image_load_3d_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
+  ; GFX6-LABEL: name: image_load_3d_tfe_f32
+  ; GFX6: bb.1 (%ir-block.0):
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[BUILD_VECTOR1]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GFX6:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  ; GFX10NSA-LABEL: name: image_load_3d_tfe_f32
+  ; GFX10NSA: bb.1 (%ir-block.0):
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
+  ; GFX10NSA:   G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0
+  %val = call { float, i32 } @llvm.amdgcn.image.load.3d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0)
+  %tex = extractvalue { float, i32 } %val, 0
+  %tfe = extractvalue { float, i32 } %val, 1
+  store i32 %tfe, i32 addrspace(1)* undef
+  ret float %tex
+}
+
+declare float @llvm.amdgcn.image.load.3d.f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
+declare { float, i32 } @llvm.amdgcn.image.load.3d.sl_f32i32s.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
+
+attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
index 7279a61af6293..fac839d8ea50d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
@@ -19,7 +19,8 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
   ; UNPACKED:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; UNPACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 2 into custom "TargetCustom8")
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 2 into custom "TargetCustom8")
   ; UNPACKED:   S_ENDPGM 0
   ; PACKED-LABEL: name: image_store_f16
   ; PACKED: bb.1 (%ir-block.0):
@@ -37,7 +38,8 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha
   ; PACKED:   [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
   ; PACKED:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32)
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; PACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 2 into custom "TargetCustom8")
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 2 into custom "TargetCustom8")
   ; PACKED:   S_ENDPGM 0
   call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
   ret void
@@ -59,13 +61,14 @@ define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; UNPACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
   ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
   ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
   ; UNPACKED:   [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
   ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY11]](s32), [[COPY12]](s32)
-  ; UNPACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<2 x s32>), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8")
+  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY11]](s32), [[COPY12]](s32)
+  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8")
   ; UNPACKED:   S_ENDPGM 0
   ; PACKED-LABEL: name: image_store_v2f16
   ; PACKED: bb.1 (%ir-block.0):
@@ -82,7 +85,8 @@ define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; PACKED:   [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
   ; PACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
-  ; PACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8")
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8")
   ; PACKED:   S_ENDPGM 0
   call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
   ret void
@@ -108,6 +112,7 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; UNPACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
   ; UNPACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
   ; UNPACKED:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
   ; UNPACKED:   [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
   ; UNPACKED:   [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0
   ; UNPACKED:   [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
@@ -119,8 +124,8 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; UNPACKED:   [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
   ; UNPACKED:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
   ; UNPACKED:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
-  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
-  ; UNPACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<3 x s32>), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
+  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<3 x s32>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
   ; UNPACKED:   S_ENDPGM 0
   ; PACKED-LABEL: name: image_store_v3f16
   ; PACKED: bb.1 (%ir-block.0):
@@ -141,7 +146,8 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; PACKED:   [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
   ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
   ; PACKED:   [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
-  ; PACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[UV]](<3 x s16>), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[UV]](<3 x s16>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
   ; PACKED:   S_ENDPGM 0
   call void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
   ret void
@@ -164,6 +170,7 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; UNPACKED:   [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
   ; UNPACKED:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
   ; UNPACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
   ; UNPACKED:   [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
   ; UNPACKED:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
   ; UNPACKED:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
@@ -173,8 +180,8 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; UNPACKED:   [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
   ; UNPACKED:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
   ; UNPACKED:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
-  ; UNPACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
-  ; UNPACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8")
+  ; UNPACKED:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; UNPACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8")
   ; UNPACKED:   S_ENDPGM 0
   ; PACKED-LABEL: name: image_store_v4f16
   ; PACKED: bb.1 (%ir-block.0):
@@ -193,7 +200,8 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
   ; PACKED:   [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
   ; PACKED:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; PACKED:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)
-  ; PACKED:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8")
+  ; PACKED:   [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
+  ; PACKED:   G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8")
   ; PACKED:   S_ENDPGM 0
   call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
index 3ebf9e49ef844..8dbf083da85d1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
@@ -606,1077 +606,913 @@ body: |
     ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
     ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
     ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY [[C4]](s16)
     ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C5]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C5]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL1]]
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
-    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[TRUNC]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C5]](s32)
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[C4]](s16)
+    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+    ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
     ; CHECK: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
-    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY4]](s32)
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
-    ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
-    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C7]]
-    ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
-    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[COPY2]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY5]], [[COPY4]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[COPY6]](s32)
+    ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY9]], [[COPY8]](s32)
+    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
     ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C7]]
-    ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY10]](s32)
-    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY11]], [[COPY10]](s32)
+    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
     ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C7]]
-    ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY12]](s32)
-    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+    ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[COPY12]](s32)
+    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
     ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C7]]
-    ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY14]](s32)
-    ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY15]], [[COPY14]](s32)
+    ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
     ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C7]]
-    ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY16]](s32)
-    ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[COPY17]], [[COPY16]](s32)
+    ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
     ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C7]]
-    ; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY18]](s32)
-    ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
+    ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[COPY19]], [[COPY18]](s32)
+    ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
     ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C7]]
-    ; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY20]](s32)
-    ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+    ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY21]], [[COPY20]](s32)
+    ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
     ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C7]]
-    ; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY22]](s32)
-    ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+    ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[COPY23]], [[COPY22]](s32)
+    ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
     ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C7]]
-    ; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY24]](s32)
-    ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[COPY25]], [[COPY24]](s32)
+    ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
     ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C7]]
-    ; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY26]](s32)
-    ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+    ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY27]], [[COPY26]](s32)
+    ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
     ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C7]]
-    ; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY28]](s32)
-    ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
+    ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[COPY29]], [[COPY28]](s32)
+    ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
     ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C7]]
-    ; CHECK: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY30]](s32)
-    ; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
-    ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C7]]
-    ; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY32]](s32)
-    ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C7]]
-    ; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY34]](s32)
-    ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C7]]
-    ; CHECK: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY36]](s32)
-    ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C7]]
-    ; CHECK: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY38]](s32)
+    ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[COPY31]], [[COPY30]](s32)
+    ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[COPY33]], [[COPY32]](s32)
+    ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[COPY35]], [[COPY34]](s32)
+    ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[COPY37]], [[COPY36]](s32)
+    ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[COPY39]], [[COPY38]](s32)
     ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C7]]
-    ; CHECK: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY40]](s32)
+    ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[COPY41]], [[COPY40]](s32)
     ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C7]]
-    ; CHECK: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY42]](s32)
+    ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[COPY43]], [[COPY42]](s32)
     ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C7]]
-    ; CHECK: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY44]](s32)
+    ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[COPY45]], [[COPY44]](s32)
     ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C7]]
-    ; CHECK: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY46]](s32)
+    ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[COPY47]], [[COPY46]](s32)
     ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C7]]
-    ; CHECK: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY48]](s32)
+    ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[COPY49]], [[COPY48]](s32)
     ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C7]]
-    ; CHECK: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY50]](s32)
+    ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[COPY51]], [[COPY50]](s32)
     ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C7]]
-    ; CHECK: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY52]](s32)
+    ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[COPY53]], [[COPY52]](s32)
     ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C7]]
-    ; CHECK: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY54]](s32)
+    ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[COPY55]], [[COPY54]](s32)
     ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C7]]
-    ; CHECK: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY56]](s32)
+    ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[COPY57]], [[COPY56]](s32)
     ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C7]]
-    ; CHECK: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY58]](s32)
+    ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[COPY59]], [[COPY58]](s32)
     ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C7]]
-    ; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY60]](s32)
-    ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C7]]
-    ; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY62]](s32)
-    ; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY65]], [[C5]](s32)
-    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY64]], [[SHL2]]
-    ; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY67]], [[C5]](s32)
-    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY66]], [[SHL3]]
-    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MV1]](s64)
-    ; CHECK: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C5]](s32)
-    ; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY69:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY69]], [[C7]]
-    ; CHECK: [[LSHR32:%[0-9]+]]:_(s32) = G_LSHR [[AND30]], [[COPY68]](s32)
-    ; CHECK: [[COPY70:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY71:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY71]], [[C7]]
-    ; CHECK: [[LSHR33:%[0-9]+]]:_(s32) = G_LSHR [[AND31]], [[COPY70]](s32)
-    ; CHECK: [[COPY72:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY73:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY73]], [[C7]]
-    ; CHECK: [[LSHR34:%[0-9]+]]:_(s32) = G_LSHR [[AND32]], [[COPY72]](s32)
-    ; CHECK: [[COPY74:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY75:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY75]], [[C7]]
-    ; CHECK: [[LSHR35:%[0-9]+]]:_(s32) = G_LSHR [[AND33]], [[COPY74]](s32)
-    ; CHECK: [[COPY76:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY77:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY77]], [[C7]]
-    ; CHECK: [[LSHR36:%[0-9]+]]:_(s32) = G_LSHR [[AND34]], [[COPY76]](s32)
-    ; CHECK: [[COPY78:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY79:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY79]], [[C7]]
-    ; CHECK: [[LSHR37:%[0-9]+]]:_(s32) = G_LSHR [[AND35]], [[COPY78]](s32)
-    ; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY81]], [[C7]]
-    ; CHECK: [[LSHR38:%[0-9]+]]:_(s32) = G_LSHR [[AND36]], [[COPY80]](s32)
-    ; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY83]], [[C7]]
-    ; CHECK: [[LSHR39:%[0-9]+]]:_(s32) = G_LSHR [[AND37]], [[COPY82]](s32)
-    ; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY85]], [[C7]]
-    ; CHECK: [[LSHR40:%[0-9]+]]:_(s32) = G_LSHR [[AND38]], [[COPY84]](s32)
-    ; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY87]], [[C7]]
-    ; CHECK: [[LSHR41:%[0-9]+]]:_(s32) = G_LSHR [[AND39]], [[COPY86]](s32)
-    ; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY89:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY89]], [[C7]]
-    ; CHECK: [[LSHR42:%[0-9]+]]:_(s32) = G_LSHR [[AND40]], [[COPY88]](s32)
-    ; CHECK: [[COPY90:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY91:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY91]], [[C7]]
-    ; CHECK: [[LSHR43:%[0-9]+]]:_(s32) = G_LSHR [[AND41]], [[COPY90]](s32)
-    ; CHECK: [[COPY92:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY93:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY93]], [[C7]]
-    ; CHECK: [[LSHR44:%[0-9]+]]:_(s32) = G_LSHR [[AND42]], [[COPY92]](s32)
-    ; CHECK: [[COPY94:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY95:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY95]], [[C7]]
-    ; CHECK: [[LSHR45:%[0-9]+]]:_(s32) = G_LSHR [[AND43]], [[COPY94]](s32)
-    ; CHECK: [[COPY96:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY97:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY97]], [[C7]]
-    ; CHECK: [[LSHR46:%[0-9]+]]:_(s32) = G_LSHR [[AND44]], [[COPY96]](s32)
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR46]](s32)
-    ; CHECK: [[COPY98:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY99:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY99]], [[C7]]
-    ; CHECK: [[LSHR47:%[0-9]+]]:_(s32) = G_LSHR [[AND45]], [[COPY98]](s32)
-    ; CHECK: [[COPY100:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY101:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY101]], [[C7]]
-    ; CHECK: [[LSHR48:%[0-9]+]]:_(s32) = G_LSHR [[AND46]], [[COPY100]](s32)
-    ; CHECK: [[COPY102:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY103:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY103]], [[C7]]
-    ; CHECK: [[LSHR49:%[0-9]+]]:_(s32) = G_LSHR [[AND47]], [[COPY102]](s32)
-    ; CHECK: [[COPY104:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY105:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY105]], [[C7]]
-    ; CHECK: [[LSHR50:%[0-9]+]]:_(s32) = G_LSHR [[AND48]], [[COPY104]](s32)
-    ; CHECK: [[COPY106:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY107:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY107]], [[C7]]
-    ; CHECK: [[LSHR51:%[0-9]+]]:_(s32) = G_LSHR [[AND49]], [[COPY106]](s32)
-    ; CHECK: [[COPY108:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY109:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY109]], [[C7]]
-    ; CHECK: [[LSHR52:%[0-9]+]]:_(s32) = G_LSHR [[AND50]], [[COPY108]](s32)
-    ; CHECK: [[COPY110:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY111:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY111]], [[C7]]
-    ; CHECK: [[LSHR53:%[0-9]+]]:_(s32) = G_LSHR [[AND51]], [[COPY110]](s32)
-    ; CHECK: [[COPY112:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY113:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY113]], [[C7]]
-    ; CHECK: [[LSHR54:%[0-9]+]]:_(s32) = G_LSHR [[AND52]], [[COPY112]](s32)
-    ; CHECK: [[COPY114:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY115:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY115]], [[C7]]
-    ; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[AND53]], [[COPY114]](s32)
-    ; CHECK: [[COPY116:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY117:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY117]], [[C7]]
-    ; CHECK: [[LSHR56:%[0-9]+]]:_(s32) = G_LSHR [[AND54]], [[COPY116]](s32)
-    ; CHECK: [[COPY118:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY119:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY119]], [[C7]]
-    ; CHECK: [[LSHR57:%[0-9]+]]:_(s32) = G_LSHR [[AND55]], [[COPY118]](s32)
-    ; CHECK: [[COPY120:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY121:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY121]], [[C7]]
-    ; CHECK: [[LSHR58:%[0-9]+]]:_(s32) = G_LSHR [[AND56]], [[COPY120]](s32)
-    ; CHECK: [[COPY122:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY123:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY123]], [[C7]]
-    ; CHECK: [[LSHR59:%[0-9]+]]:_(s32) = G_LSHR [[AND57]], [[COPY122]](s32)
-    ; CHECK: [[COPY124:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY125:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY125]], [[C7]]
-    ; CHECK: [[LSHR60:%[0-9]+]]:_(s32) = G_LSHR [[AND58]], [[COPY124]](s32)
-    ; CHECK: [[COPY126:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY127:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY127]], [[C7]]
-    ; CHECK: [[LSHR61:%[0-9]+]]:_(s32) = G_LSHR [[AND59]], [[COPY126]](s32)
-    ; CHECK: [[COPY128:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY129:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY129]], [[C5]](s32)
-    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY128]], [[SHL4]]
-    ; CHECK: [[COPY130:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[COPY131:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY131]], [[C5]](s32)
-    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY130]], [[SHL5]]
-    ; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[MV2]](s64)
-    ; CHECK: [[LSHR62:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C5]](s32)
-    ; CHECK: [[COPY132:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY133:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY133]], [[C7]]
-    ; CHECK: [[LSHR63:%[0-9]+]]:_(s32) = G_LSHR [[AND60]], [[COPY132]](s32)
-    ; CHECK: [[COPY134:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY135:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY135]], [[C7]]
-    ; CHECK: [[LSHR64:%[0-9]+]]:_(s32) = G_LSHR [[AND61]], [[COPY134]](s32)
-    ; CHECK: [[COPY136:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY137:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY137]], [[C7]]
-    ; CHECK: [[LSHR65:%[0-9]+]]:_(s32) = G_LSHR [[AND62]], [[COPY136]](s32)
-    ; CHECK: [[COPY138:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY139:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY139]], [[C7]]
-    ; CHECK: [[LSHR66:%[0-9]+]]:_(s32) = G_LSHR [[AND63]], [[COPY138]](s32)
-    ; CHECK: [[COPY140:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY141:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[COPY141]], [[C7]]
-    ; CHECK: [[LSHR67:%[0-9]+]]:_(s32) = G_LSHR [[AND64]], [[COPY140]](s32)
-    ; CHECK: [[COPY142:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY143:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND65:%[0-9]+]]:_(s32) = G_AND [[COPY143]], [[C7]]
-    ; CHECK: [[LSHR68:%[0-9]+]]:_(s32) = G_LSHR [[AND65]], [[COPY142]](s32)
-    ; CHECK: [[COPY144:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY145:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND66:%[0-9]+]]:_(s32) = G_AND [[COPY145]], [[C7]]
-    ; CHECK: [[LSHR69:%[0-9]+]]:_(s32) = G_LSHR [[AND66]], [[COPY144]](s32)
-    ; CHECK: [[COPY146:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY147:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND67:%[0-9]+]]:_(s32) = G_AND [[COPY147]], [[C7]]
-    ; CHECK: [[LSHR70:%[0-9]+]]:_(s32) = G_LSHR [[AND67]], [[COPY146]](s32)
-    ; CHECK: [[COPY148:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY149:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND68:%[0-9]+]]:_(s32) = G_AND [[COPY149]], [[C7]]
-    ; CHECK: [[LSHR71:%[0-9]+]]:_(s32) = G_LSHR [[AND68]], [[COPY148]](s32)
-    ; CHECK: [[COPY150:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY151:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND69:%[0-9]+]]:_(s32) = G_AND [[COPY151]], [[C7]]
-    ; CHECK: [[LSHR72:%[0-9]+]]:_(s32) = G_LSHR [[AND69]], [[COPY150]](s32)
-    ; CHECK: [[COPY152:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY153:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND70:%[0-9]+]]:_(s32) = G_AND [[COPY153]], [[C7]]
-    ; CHECK: [[LSHR73:%[0-9]+]]:_(s32) = G_LSHR [[AND70]], [[COPY152]](s32)
-    ; CHECK: [[COPY154:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY155:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND71:%[0-9]+]]:_(s32) = G_AND [[COPY155]], [[C7]]
-    ; CHECK: [[LSHR74:%[0-9]+]]:_(s32) = G_LSHR [[AND71]], [[COPY154]](s32)
-    ; CHECK: [[COPY156:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY157:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND72:%[0-9]+]]:_(s32) = G_AND [[COPY157]], [[C7]]
-    ; CHECK: [[LSHR75:%[0-9]+]]:_(s32) = G_LSHR [[AND72]], [[COPY156]](s32)
-    ; CHECK: [[COPY158:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY159:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND73:%[0-9]+]]:_(s32) = G_AND [[COPY159]], [[C7]]
-    ; CHECK: [[LSHR76:%[0-9]+]]:_(s32) = G_LSHR [[AND73]], [[COPY158]](s32)
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR76]](s32)
-    ; CHECK: [[COPY160:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY161:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND74:%[0-9]+]]:_(s32) = G_AND [[COPY161]], [[C7]]
-    ; CHECK: [[LSHR77:%[0-9]+]]:_(s32) = G_LSHR [[AND74]], [[COPY160]](s32)
-    ; CHECK: [[COPY162:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY163:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND75:%[0-9]+]]:_(s32) = G_AND [[COPY163]], [[C7]]
-    ; CHECK: [[LSHR78:%[0-9]+]]:_(s32) = G_LSHR [[AND75]], [[COPY162]](s32)
-    ; CHECK: [[COPY164:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY165:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND76:%[0-9]+]]:_(s32) = G_AND [[COPY165]], [[C7]]
-    ; CHECK: [[LSHR79:%[0-9]+]]:_(s32) = G_LSHR [[AND76]], [[COPY164]](s32)
-    ; CHECK: [[COPY166:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY167:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND77:%[0-9]+]]:_(s32) = G_AND [[COPY167]], [[C7]]
-    ; CHECK: [[LSHR80:%[0-9]+]]:_(s32) = G_LSHR [[AND77]], [[COPY166]](s32)
-    ; CHECK: [[COPY168:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY169:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND78:%[0-9]+]]:_(s32) = G_AND [[COPY169]], [[C7]]
-    ; CHECK: [[LSHR81:%[0-9]+]]:_(s32) = G_LSHR [[AND78]], [[COPY168]](s32)
-    ; CHECK: [[COPY170:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY171:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND79:%[0-9]+]]:_(s32) = G_AND [[COPY171]], [[C7]]
-    ; CHECK: [[LSHR82:%[0-9]+]]:_(s32) = G_LSHR [[AND79]], [[COPY170]](s32)
-    ; CHECK: [[COPY172:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY173:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND80:%[0-9]+]]:_(s32) = G_AND [[COPY173]], [[C7]]
-    ; CHECK: [[LSHR83:%[0-9]+]]:_(s32) = G_LSHR [[AND80]], [[COPY172]](s32)
-    ; CHECK: [[COPY174:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY175:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND81:%[0-9]+]]:_(s32) = G_AND [[COPY175]], [[C7]]
-    ; CHECK: [[LSHR84:%[0-9]+]]:_(s32) = G_LSHR [[AND81]], [[COPY174]](s32)
-    ; CHECK: [[COPY176:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY177:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND82:%[0-9]+]]:_(s32) = G_AND [[COPY177]], [[C7]]
-    ; CHECK: [[LSHR85:%[0-9]+]]:_(s32) = G_LSHR [[AND82]], [[COPY176]](s32)
-    ; CHECK: [[COPY178:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY179:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND83:%[0-9]+]]:_(s32) = G_AND [[COPY179]], [[C7]]
-    ; CHECK: [[LSHR86:%[0-9]+]]:_(s32) = G_LSHR [[AND83]], [[COPY178]](s32)
-    ; CHECK: [[COPY180:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY181:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND84:%[0-9]+]]:_(s32) = G_AND [[COPY181]], [[C7]]
-    ; CHECK: [[LSHR87:%[0-9]+]]:_(s32) = G_LSHR [[AND84]], [[COPY180]](s32)
-    ; CHECK: [[COPY182:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY183:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND85:%[0-9]+]]:_(s32) = G_AND [[COPY183]], [[C7]]
-    ; CHECK: [[LSHR88:%[0-9]+]]:_(s32) = G_LSHR [[AND85]], [[COPY182]](s32)
-    ; CHECK: [[COPY184:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY185:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND86:%[0-9]+]]:_(s32) = G_AND [[COPY185]], [[C7]]
-    ; CHECK: [[LSHR89:%[0-9]+]]:_(s32) = G_LSHR [[AND86]], [[COPY184]](s32)
-    ; CHECK: [[COPY186:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY187:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND87:%[0-9]+]]:_(s32) = G_AND [[COPY187]], [[C7]]
-    ; CHECK: [[LSHR90:%[0-9]+]]:_(s32) = G_LSHR [[AND87]], [[COPY186]](s32)
-    ; CHECK: [[COPY188:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY189:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND88:%[0-9]+]]:_(s32) = G_AND [[COPY189]], [[C7]]
-    ; CHECK: [[LSHR91:%[0-9]+]]:_(s32) = G_LSHR [[AND88]], [[COPY188]](s32)
-    ; CHECK: [[COPY190:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY191:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND89:%[0-9]+]]:_(s32) = G_AND [[COPY191]], [[C7]]
-    ; CHECK: [[LSHR92:%[0-9]+]]:_(s32) = G_LSHR [[AND89]], [[COPY190]](s32)
-    ; CHECK: [[COPY192:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY193:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY193]], [[C5]](s32)
-    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY192]], [[SHL6]]
-    ; CHECK: [[COPY194:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[COPY195:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY195]], [[C5]](s32)
-    ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[COPY194]], [[SHL7]]
-    ; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)
-    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s64)
-    ; CHECK: [[LSHR93:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C5]](s32)
-    ; CHECK: [[COPY196:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY197:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND90:%[0-9]+]]:_(s32) = G_AND [[COPY197]], [[C7]]
-    ; CHECK: [[LSHR94:%[0-9]+]]:_(s32) = G_LSHR [[AND90]], [[COPY196]](s32)
-    ; CHECK: [[COPY198:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY199:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND91:%[0-9]+]]:_(s32) = G_AND [[COPY199]], [[C7]]
-    ; CHECK: [[LSHR95:%[0-9]+]]:_(s32) = G_LSHR [[AND91]], [[COPY198]](s32)
-    ; CHECK: [[COPY200:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY201:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND92:%[0-9]+]]:_(s32) = G_AND [[COPY201]], [[C7]]
-    ; CHECK: [[LSHR96:%[0-9]+]]:_(s32) = G_LSHR [[AND92]], [[COPY200]](s32)
-    ; CHECK: [[COPY202:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY203:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND93:%[0-9]+]]:_(s32) = G_AND [[COPY203]], [[C7]]
-    ; CHECK: [[LSHR97:%[0-9]+]]:_(s32) = G_LSHR [[AND93]], [[COPY202]](s32)
-    ; CHECK: [[COPY204:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY205:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND94:%[0-9]+]]:_(s32) = G_AND [[COPY205]], [[C7]]
-    ; CHECK: [[LSHR98:%[0-9]+]]:_(s32) = G_LSHR [[AND94]], [[COPY204]](s32)
-    ; CHECK: [[COPY206:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY207:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND95:%[0-9]+]]:_(s32) = G_AND [[COPY207]], [[C7]]
-    ; CHECK: [[LSHR99:%[0-9]+]]:_(s32) = G_LSHR [[AND95]], [[COPY206]](s32)
-    ; CHECK: [[COPY208:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY209:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND96:%[0-9]+]]:_(s32) = G_AND [[COPY209]], [[C7]]
-    ; CHECK: [[LSHR100:%[0-9]+]]:_(s32) = G_LSHR [[AND96]], [[COPY208]](s32)
-    ; CHECK: [[COPY210:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY211:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND97:%[0-9]+]]:_(s32) = G_AND [[COPY211]], [[C7]]
-    ; CHECK: [[LSHR101:%[0-9]+]]:_(s32) = G_LSHR [[AND97]], [[COPY210]](s32)
-    ; CHECK: [[COPY212:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY213:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND98:%[0-9]+]]:_(s32) = G_AND [[COPY213]], [[C7]]
-    ; CHECK: [[LSHR102:%[0-9]+]]:_(s32) = G_LSHR [[AND98]], [[COPY212]](s32)
-    ; CHECK: [[COPY214:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY215:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND99:%[0-9]+]]:_(s32) = G_AND [[COPY215]], [[C7]]
-    ; CHECK: [[LSHR103:%[0-9]+]]:_(s32) = G_LSHR [[AND99]], [[COPY214]](s32)
-    ; CHECK: [[COPY216:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY217:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND100:%[0-9]+]]:_(s32) = G_AND [[COPY217]], [[C7]]
-    ; CHECK: [[LSHR104:%[0-9]+]]:_(s32) = G_LSHR [[AND100]], [[COPY216]](s32)
-    ; CHECK: [[COPY218:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY219:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND101:%[0-9]+]]:_(s32) = G_AND [[COPY219]], [[C7]]
-    ; CHECK: [[LSHR105:%[0-9]+]]:_(s32) = G_LSHR [[AND101]], [[COPY218]](s32)
-    ; CHECK: [[COPY220:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY221:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND102:%[0-9]+]]:_(s32) = G_AND [[COPY221]], [[C7]]
-    ; CHECK: [[LSHR106:%[0-9]+]]:_(s32) = G_LSHR [[AND102]], [[COPY220]](s32)
-    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR106]](s32)
-    ; CHECK: [[COPY222:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY223:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND103:%[0-9]+]]:_(s32) = G_AND [[COPY223]], [[C7]]
-    ; CHECK: [[LSHR107:%[0-9]+]]:_(s32) = G_LSHR [[AND103]], [[COPY222]](s32)
-    ; CHECK: [[COPY224:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY225:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND104:%[0-9]+]]:_(s32) = G_AND [[COPY225]], [[C7]]
-    ; CHECK: [[LSHR108:%[0-9]+]]:_(s32) = G_LSHR [[AND104]], [[COPY224]](s32)
-    ; CHECK: [[COPY226:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY227:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND105:%[0-9]+]]:_(s32) = G_AND [[COPY227]], [[C7]]
-    ; CHECK: [[LSHR109:%[0-9]+]]:_(s32) = G_LSHR [[AND105]], [[COPY226]](s32)
-    ; CHECK: [[COPY228:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY229:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND106:%[0-9]+]]:_(s32) = G_AND [[COPY229]], [[C7]]
-    ; CHECK: [[LSHR110:%[0-9]+]]:_(s32) = G_LSHR [[AND106]], [[COPY228]](s32)
-    ; CHECK: [[COPY230:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY231:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND107:%[0-9]+]]:_(s32) = G_AND [[COPY231]], [[C7]]
-    ; CHECK: [[LSHR111:%[0-9]+]]:_(s32) = G_LSHR [[AND107]], [[COPY230]](s32)
-    ; CHECK: [[COPY232:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY233:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND108:%[0-9]+]]:_(s32) = G_AND [[COPY233]], [[C7]]
-    ; CHECK: [[LSHR112:%[0-9]+]]:_(s32) = G_LSHR [[AND108]], [[COPY232]](s32)
-    ; CHECK: [[COPY234:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY235:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND109:%[0-9]+]]:_(s32) = G_AND [[COPY235]], [[C7]]
-    ; CHECK: [[LSHR113:%[0-9]+]]:_(s32) = G_LSHR [[AND109]], [[COPY234]](s32)
-    ; CHECK: [[COPY236:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY237:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND110:%[0-9]+]]:_(s32) = G_AND [[COPY237]], [[C7]]
-    ; CHECK: [[LSHR114:%[0-9]+]]:_(s32) = G_LSHR [[AND110]], [[COPY236]](s32)
-    ; CHECK: [[COPY238:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY239:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND111:%[0-9]+]]:_(s32) = G_AND [[COPY239]], [[C7]]
-    ; CHECK: [[LSHR115:%[0-9]+]]:_(s32) = G_LSHR [[AND111]], [[COPY238]](s32)
-    ; CHECK: [[COPY240:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY241:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND112:%[0-9]+]]:_(s32) = G_AND [[COPY241]], [[C7]]
-    ; CHECK: [[LSHR116:%[0-9]+]]:_(s32) = G_LSHR [[AND112]], [[COPY240]](s32)
-    ; CHECK: [[COPY242:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY243:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND113:%[0-9]+]]:_(s32) = G_AND [[COPY243]], [[C7]]
-    ; CHECK: [[LSHR117:%[0-9]+]]:_(s32) = G_LSHR [[AND113]], [[COPY242]](s32)
-    ; CHECK: [[COPY244:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY245:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND114:%[0-9]+]]:_(s32) = G_AND [[COPY245]], [[C7]]
-    ; CHECK: [[LSHR118:%[0-9]+]]:_(s32) = G_LSHR [[AND114]], [[COPY244]](s32)
-    ; CHECK: [[COPY246:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY247:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND115:%[0-9]+]]:_(s32) = G_AND [[COPY247]], [[C7]]
-    ; CHECK: [[LSHR119:%[0-9]+]]:_(s32) = G_LSHR [[AND115]], [[COPY246]](s32)
-    ; CHECK: [[COPY248:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY249:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND116:%[0-9]+]]:_(s32) = G_AND [[COPY249]], [[C7]]
-    ; CHECK: [[LSHR120:%[0-9]+]]:_(s32) = G_LSHR [[AND116]], [[COPY248]](s32)
-    ; CHECK: [[COPY250:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY251:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND117:%[0-9]+]]:_(s32) = G_AND [[COPY251]], [[C7]]
-    ; CHECK: [[LSHR121:%[0-9]+]]:_(s32) = G_LSHR [[AND117]], [[COPY250]](s32)
-    ; CHECK: [[COPY252:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY253:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND118:%[0-9]+]]:_(s32) = G_AND [[COPY253]], [[C7]]
-    ; CHECK: [[LSHR122:%[0-9]+]]:_(s32) = G_LSHR [[AND118]], [[COPY252]](s32)
-    ; CHECK: [[COPY254:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY255:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND119:%[0-9]+]]:_(s32) = G_AND [[COPY255]], [[C7]]
-    ; CHECK: [[LSHR123:%[0-9]+]]:_(s32) = G_LSHR [[AND119]], [[COPY254]](s32)
-    ; CHECK: [[COPY256:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
-    ; CHECK: [[AND120:%[0-9]+]]:_(s16) = G_AND [[COPY256]], [[C6]]
-    ; CHECK: [[COPY257:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY258:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
-    ; CHECK: [[AND121:%[0-9]+]]:_(s32) = G_AND [[COPY258]], [[C1]]
-    ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND121]], [[COPY257]](s32)
-    ; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
-    ; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND120]], [[TRUNC9]]
-    ; CHECK: [[COPY259:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY260:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
-    ; CHECK: [[AND122:%[0-9]+]]:_(s32) = G_AND [[COPY260]], [[C1]]
-    ; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND122]], [[COPY259]](s32)
-    ; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
-    ; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[OR8]], [[TRUNC10]]
-    ; CHECK: [[COPY261:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY262:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
-    ; CHECK: [[AND123:%[0-9]+]]:_(s32) = G_AND [[COPY262]], [[C1]]
-    ; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND123]], [[COPY261]](s32)
-    ; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL10]](s32)
-    ; CHECK: [[OR10:%[0-9]+]]:_(s16) = G_OR [[OR9]], [[TRUNC11]]
-    ; CHECK: [[COPY263:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY264:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
-    ; CHECK: [[AND124:%[0-9]+]]:_(s32) = G_AND [[COPY264]], [[C1]]
-    ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND124]], [[COPY263]](s32)
-    ; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL11]](s32)
-    ; CHECK: [[OR11:%[0-9]+]]:_(s16) = G_OR [[OR10]], [[TRUNC12]]
-    ; CHECK: [[COPY265:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY266:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
-    ; CHECK: [[AND125:%[0-9]+]]:_(s32) = G_AND [[COPY266]], [[C1]]
-    ; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND125]], [[COPY265]](s32)
-    ; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
-    ; CHECK: [[OR12:%[0-9]+]]:_(s16) = G_OR [[OR11]], [[TRUNC13]]
-    ; CHECK: [[COPY267:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY268:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
-    ; CHECK: [[AND126:%[0-9]+]]:_(s32) = G_AND [[COPY268]], [[C1]]
-    ; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND126]], [[COPY267]](s32)
-    ; CHECK: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
-    ; CHECK: [[OR13:%[0-9]+]]:_(s16) = G_OR [[OR12]], [[TRUNC14]]
-    ; CHECK: [[COPY269:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY270:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
-    ; CHECK: [[AND127:%[0-9]+]]:_(s32) = G_AND [[COPY270]], [[C1]]
-    ; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND127]], [[COPY269]](s32)
-    ; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
-    ; CHECK: [[OR14:%[0-9]+]]:_(s16) = G_OR [[OR13]], [[TRUNC15]]
-    ; CHECK: [[COPY271:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY272:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
-    ; CHECK: [[AND128:%[0-9]+]]:_(s32) = G_AND [[COPY272]], [[C1]]
-    ; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND128]], [[COPY271]](s32)
-    ; CHECK: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
-    ; CHECK: [[OR15:%[0-9]+]]:_(s16) = G_OR [[OR14]], [[TRUNC16]]
-    ; CHECK: [[COPY273:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY274:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
-    ; CHECK: [[AND129:%[0-9]+]]:_(s32) = G_AND [[COPY274]], [[C1]]
-    ; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND129]], [[COPY273]](s32)
-    ; CHECK: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL16]](s32)
-    ; CHECK: [[OR16:%[0-9]+]]:_(s16) = G_OR [[OR15]], [[TRUNC17]]
-    ; CHECK: [[COPY275:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY276:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
-    ; CHECK: [[AND130:%[0-9]+]]:_(s32) = G_AND [[COPY276]], [[C1]]
-    ; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND130]], [[COPY275]](s32)
-    ; CHECK: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[SHL17]](s32)
-    ; CHECK: [[OR17:%[0-9]+]]:_(s16) = G_OR [[OR16]], [[TRUNC18]]
-    ; CHECK: [[COPY277:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY278:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
-    ; CHECK: [[AND131:%[0-9]+]]:_(s32) = G_AND [[COPY278]], [[C1]]
-    ; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND131]], [[COPY277]](s32)
-    ; CHECK: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
-    ; CHECK: [[OR18:%[0-9]+]]:_(s16) = G_OR [[OR17]], [[TRUNC19]]
-    ; CHECK: [[COPY279:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY280:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
-    ; CHECK: [[AND132:%[0-9]+]]:_(s32) = G_AND [[COPY280]], [[C1]]
-    ; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND132]], [[COPY279]](s32)
-    ; CHECK: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
-    ; CHECK: [[OR19:%[0-9]+]]:_(s16) = G_OR [[OR18]], [[TRUNC20]]
-    ; CHECK: [[COPY281:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY282:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
-    ; CHECK: [[AND133:%[0-9]+]]:_(s32) = G_AND [[COPY282]], [[C1]]
-    ; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND133]], [[COPY281]](s32)
-    ; CHECK: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
-    ; CHECK: [[OR20:%[0-9]+]]:_(s16) = G_OR [[OR19]], [[TRUNC21]]
-    ; CHECK: [[COPY283:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY284:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
-    ; CHECK: [[AND134:%[0-9]+]]:_(s32) = G_AND [[COPY284]], [[C1]]
-    ; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND134]], [[COPY283]](s32)
-    ; CHECK: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
-    ; CHECK: [[OR21:%[0-9]+]]:_(s16) = G_OR [[OR20]], [[TRUNC22]]
-    ; CHECK: [[COPY285:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY286:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
-    ; CHECK: [[AND135:%[0-9]+]]:_(s32) = G_AND [[COPY286]], [[C1]]
-    ; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND135]], [[COPY285]](s32)
-    ; CHECK: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL22]](s32)
-    ; CHECK: [[OR22:%[0-9]+]]:_(s16) = G_OR [[OR21]], [[TRUNC23]]
-    ; CHECK: [[COPY287:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
-    ; CHECK: [[AND136:%[0-9]+]]:_(s16) = G_AND [[COPY287]], [[C6]]
-    ; CHECK: [[COPY288:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY289:%[0-9]+]]:_(s32) = COPY [[TRUNC3]](s32)
-    ; CHECK: [[AND137:%[0-9]+]]:_(s32) = G_AND [[COPY289]], [[C1]]
-    ; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND137]], [[COPY288]](s32)
-    ; CHECK: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[SHL23]](s32)
-    ; CHECK: [[OR23:%[0-9]+]]:_(s16) = G_OR [[AND136]], [[TRUNC24]]
-    ; CHECK: [[COPY290:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY291:%[0-9]+]]:_(s32) = COPY [[LSHR32]](s32)
-    ; CHECK: [[AND138:%[0-9]+]]:_(s32) = G_AND [[COPY291]], [[C1]]
-    ; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND138]], [[COPY290]](s32)
-    ; CHECK: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL24]](s32)
-    ; CHECK: [[OR24:%[0-9]+]]:_(s16) = G_OR [[OR23]], [[TRUNC25]]
-    ; CHECK: [[COPY292:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY293:%[0-9]+]]:_(s32) = COPY [[LSHR33]](s32)
-    ; CHECK: [[AND139:%[0-9]+]]:_(s32) = G_AND [[COPY293]], [[C1]]
-    ; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND139]], [[COPY292]](s32)
-    ; CHECK: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[SHL25]](s32)
-    ; CHECK: [[OR25:%[0-9]+]]:_(s16) = G_OR [[OR24]], [[TRUNC26]]
-    ; CHECK: [[COPY294:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY295:%[0-9]+]]:_(s32) = COPY [[LSHR34]](s32)
-    ; CHECK: [[AND140:%[0-9]+]]:_(s32) = G_AND [[COPY295]], [[C1]]
-    ; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND140]], [[COPY294]](s32)
-    ; CHECK: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL26]](s32)
-    ; CHECK: [[OR26:%[0-9]+]]:_(s16) = G_OR [[OR25]], [[TRUNC27]]
-    ; CHECK: [[COPY296:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY297:%[0-9]+]]:_(s32) = COPY [[LSHR35]](s32)
-    ; CHECK: [[AND141:%[0-9]+]]:_(s32) = G_AND [[COPY297]], [[C1]]
-    ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND141]], [[COPY296]](s32)
-    ; CHECK: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[SHL27]](s32)
-    ; CHECK: [[OR27:%[0-9]+]]:_(s16) = G_OR [[OR26]], [[TRUNC28]]
-    ; CHECK: [[COPY298:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY299:%[0-9]+]]:_(s32) = COPY [[LSHR36]](s32)
-    ; CHECK: [[AND142:%[0-9]+]]:_(s32) = G_AND [[COPY299]], [[C1]]
-    ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND142]], [[COPY298]](s32)
-    ; CHECK: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL28]](s32)
-    ; CHECK: [[OR28:%[0-9]+]]:_(s16) = G_OR [[OR27]], [[TRUNC29]]
-    ; CHECK: [[COPY300:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY301:%[0-9]+]]:_(s32) = COPY [[LSHR37]](s32)
-    ; CHECK: [[AND143:%[0-9]+]]:_(s32) = G_AND [[COPY301]], [[C1]]
-    ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND143]], [[COPY300]](s32)
-    ; CHECK: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[SHL29]](s32)
-    ; CHECK: [[OR29:%[0-9]+]]:_(s16) = G_OR [[OR28]], [[TRUNC30]]
-    ; CHECK: [[COPY302:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY303:%[0-9]+]]:_(s32) = COPY [[LSHR38]](s32)
-    ; CHECK: [[AND144:%[0-9]+]]:_(s32) = G_AND [[COPY303]], [[C1]]
-    ; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND144]], [[COPY302]](s32)
-    ; CHECK: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL30]](s32)
-    ; CHECK: [[OR30:%[0-9]+]]:_(s16) = G_OR [[OR29]], [[TRUNC31]]
-    ; CHECK: [[COPY304:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY305:%[0-9]+]]:_(s32) = COPY [[LSHR39]](s32)
-    ; CHECK: [[AND145:%[0-9]+]]:_(s32) = G_AND [[COPY305]], [[C1]]
-    ; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND145]], [[COPY304]](s32)
-    ; CHECK: [[TRUNC32:%[0-9]+]]:_(s16) = G_TRUNC [[SHL31]](s32)
-    ; CHECK: [[OR31:%[0-9]+]]:_(s16) = G_OR [[OR30]], [[TRUNC32]]
-    ; CHECK: [[COPY306:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY307:%[0-9]+]]:_(s32) = COPY [[LSHR40]](s32)
-    ; CHECK: [[AND146:%[0-9]+]]:_(s32) = G_AND [[COPY307]], [[C1]]
-    ; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND146]], [[COPY306]](s32)
-    ; CHECK: [[TRUNC33:%[0-9]+]]:_(s16) = G_TRUNC [[SHL32]](s32)
-    ; CHECK: [[OR32:%[0-9]+]]:_(s16) = G_OR [[OR31]], [[TRUNC33]]
-    ; CHECK: [[COPY308:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY309:%[0-9]+]]:_(s32) = COPY [[LSHR41]](s32)
-    ; CHECK: [[AND147:%[0-9]+]]:_(s32) = G_AND [[COPY309]], [[C1]]
-    ; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND147]], [[COPY308]](s32)
-    ; CHECK: [[TRUNC34:%[0-9]+]]:_(s16) = G_TRUNC [[SHL33]](s32)
-    ; CHECK: [[OR33:%[0-9]+]]:_(s16) = G_OR [[OR32]], [[TRUNC34]]
-    ; CHECK: [[COPY310:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY311:%[0-9]+]]:_(s32) = COPY [[LSHR42]](s32)
-    ; CHECK: [[AND148:%[0-9]+]]:_(s32) = G_AND [[COPY311]], [[C1]]
-    ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND148]], [[COPY310]](s32)
-    ; CHECK: [[TRUNC35:%[0-9]+]]:_(s16) = G_TRUNC [[SHL34]](s32)
-    ; CHECK: [[OR34:%[0-9]+]]:_(s16) = G_OR [[OR33]], [[TRUNC35]]
-    ; CHECK: [[COPY312:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY313:%[0-9]+]]:_(s32) = COPY [[LSHR43]](s32)
-    ; CHECK: [[AND149:%[0-9]+]]:_(s32) = G_AND [[COPY313]], [[C1]]
-    ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND149]], [[COPY312]](s32)
-    ; CHECK: [[TRUNC36:%[0-9]+]]:_(s16) = G_TRUNC [[SHL35]](s32)
-    ; CHECK: [[OR35:%[0-9]+]]:_(s16) = G_OR [[OR34]], [[TRUNC36]]
-    ; CHECK: [[COPY314:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY315:%[0-9]+]]:_(s32) = COPY [[LSHR44]](s32)
-    ; CHECK: [[AND150:%[0-9]+]]:_(s32) = G_AND [[COPY315]], [[C1]]
-    ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND150]], [[COPY314]](s32)
-    ; CHECK: [[TRUNC37:%[0-9]+]]:_(s16) = G_TRUNC [[SHL36]](s32)
-    ; CHECK: [[OR36:%[0-9]+]]:_(s16) = G_OR [[OR35]], [[TRUNC37]]
-    ; CHECK: [[COPY316:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY317:%[0-9]+]]:_(s32) = COPY [[LSHR45]](s32)
-    ; CHECK: [[AND151:%[0-9]+]]:_(s32) = G_AND [[COPY317]], [[C1]]
-    ; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND151]], [[COPY316]](s32)
-    ; CHECK: [[TRUNC38:%[0-9]+]]:_(s16) = G_TRUNC [[SHL37]](s32)
-    ; CHECK: [[OR37:%[0-9]+]]:_(s16) = G_OR [[OR36]], [[TRUNC38]]
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR22]](s16)
-    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR37]](s16)
-    ; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
-    ; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL38]]
-    ; CHECK: [[COPY318:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
-    ; CHECK: [[AND152:%[0-9]+]]:_(s16) = G_AND [[COPY318]], [[C6]]
-    ; CHECK: [[COPY319:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY320:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
-    ; CHECK: [[AND153:%[0-9]+]]:_(s32) = G_AND [[COPY320]], [[C1]]
-    ; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND153]], [[COPY319]](s32)
-    ; CHECK: [[TRUNC39:%[0-9]+]]:_(s16) = G_TRUNC [[SHL39]](s32)
-    ; CHECK: [[OR39:%[0-9]+]]:_(s16) = G_OR [[AND152]], [[TRUNC39]]
-    ; CHECK: [[COPY321:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY322:%[0-9]+]]:_(s32) = COPY [[TRUNC5]](s32)
-    ; CHECK: [[AND154:%[0-9]+]]:_(s32) = G_AND [[COPY322]], [[C1]]
-    ; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND154]], [[COPY321]](s32)
-    ; CHECK: [[TRUNC40:%[0-9]+]]:_(s16) = G_TRUNC [[SHL40]](s32)
-    ; CHECK: [[OR40:%[0-9]+]]:_(s16) = G_OR [[OR39]], [[TRUNC40]]
-    ; CHECK: [[COPY323:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY324:%[0-9]+]]:_(s32) = COPY [[LSHR63]](s32)
-    ; CHECK: [[AND155:%[0-9]+]]:_(s32) = G_AND [[COPY324]], [[C1]]
-    ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND155]], [[COPY323]](s32)
-    ; CHECK: [[TRUNC41:%[0-9]+]]:_(s16) = G_TRUNC [[SHL41]](s32)
-    ; CHECK: [[OR41:%[0-9]+]]:_(s16) = G_OR [[OR40]], [[TRUNC41]]
-    ; CHECK: [[COPY325:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY326:%[0-9]+]]:_(s32) = COPY [[LSHR64]](s32)
-    ; CHECK: [[AND156:%[0-9]+]]:_(s32) = G_AND [[COPY326]], [[C1]]
-    ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND156]], [[COPY325]](s32)
-    ; CHECK: [[TRUNC42:%[0-9]+]]:_(s16) = G_TRUNC [[SHL42]](s32)
-    ; CHECK: [[OR42:%[0-9]+]]:_(s16) = G_OR [[OR41]], [[TRUNC42]]
-    ; CHECK: [[COPY327:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY328:%[0-9]+]]:_(s32) = COPY [[LSHR65]](s32)
-    ; CHECK: [[AND157:%[0-9]+]]:_(s32) = G_AND [[COPY328]], [[C1]]
-    ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND157]], [[COPY327]](s32)
-    ; CHECK: [[TRUNC43:%[0-9]+]]:_(s16) = G_TRUNC [[SHL43]](s32)
-    ; CHECK: [[OR43:%[0-9]+]]:_(s16) = G_OR [[OR42]], [[TRUNC43]]
-    ; CHECK: [[COPY329:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY330:%[0-9]+]]:_(s32) = COPY [[LSHR66]](s32)
-    ; CHECK: [[AND158:%[0-9]+]]:_(s32) = G_AND [[COPY330]], [[C1]]
-    ; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND158]], [[COPY329]](s32)
-    ; CHECK: [[TRUNC44:%[0-9]+]]:_(s16) = G_TRUNC [[SHL44]](s32)
-    ; CHECK: [[OR44:%[0-9]+]]:_(s16) = G_OR [[OR43]], [[TRUNC44]]
-    ; CHECK: [[COPY331:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY332:%[0-9]+]]:_(s32) = COPY [[LSHR67]](s32)
-    ; CHECK: [[AND159:%[0-9]+]]:_(s32) = G_AND [[COPY332]], [[C1]]
-    ; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND159]], [[COPY331]](s32)
-    ; CHECK: [[TRUNC45:%[0-9]+]]:_(s16) = G_TRUNC [[SHL45]](s32)
-    ; CHECK: [[OR45:%[0-9]+]]:_(s16) = G_OR [[OR44]], [[TRUNC45]]
-    ; CHECK: [[COPY333:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY334:%[0-9]+]]:_(s32) = COPY [[LSHR68]](s32)
-    ; CHECK: [[AND160:%[0-9]+]]:_(s32) = G_AND [[COPY334]], [[C1]]
-    ; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND160]], [[COPY333]](s32)
-    ; CHECK: [[TRUNC46:%[0-9]+]]:_(s16) = G_TRUNC [[SHL46]](s32)
-    ; CHECK: [[OR46:%[0-9]+]]:_(s16) = G_OR [[OR45]], [[TRUNC46]]
-    ; CHECK: [[COPY335:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY336:%[0-9]+]]:_(s32) = COPY [[LSHR69]](s32)
-    ; CHECK: [[AND161:%[0-9]+]]:_(s32) = G_AND [[COPY336]], [[C1]]
-    ; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND161]], [[COPY335]](s32)
-    ; CHECK: [[TRUNC47:%[0-9]+]]:_(s16) = G_TRUNC [[SHL47]](s32)
-    ; CHECK: [[OR47:%[0-9]+]]:_(s16) = G_OR [[OR46]], [[TRUNC47]]
-    ; CHECK: [[COPY337:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY338:%[0-9]+]]:_(s32) = COPY [[LSHR70]](s32)
-    ; CHECK: [[AND162:%[0-9]+]]:_(s32) = G_AND [[COPY338]], [[C1]]
-    ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND162]], [[COPY337]](s32)
-    ; CHECK: [[TRUNC48:%[0-9]+]]:_(s16) = G_TRUNC [[SHL48]](s32)
-    ; CHECK: [[OR48:%[0-9]+]]:_(s16) = G_OR [[OR47]], [[TRUNC48]]
-    ; CHECK: [[COPY339:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY340:%[0-9]+]]:_(s32) = COPY [[LSHR71]](s32)
-    ; CHECK: [[AND163:%[0-9]+]]:_(s32) = G_AND [[COPY340]], [[C1]]
-    ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND163]], [[COPY339]](s32)
-    ; CHECK: [[TRUNC49:%[0-9]+]]:_(s16) = G_TRUNC [[SHL49]](s32)
-    ; CHECK: [[OR49:%[0-9]+]]:_(s16) = G_OR [[OR48]], [[TRUNC49]]
-    ; CHECK: [[COPY341:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY342:%[0-9]+]]:_(s32) = COPY [[LSHR72]](s32)
-    ; CHECK: [[AND164:%[0-9]+]]:_(s32) = G_AND [[COPY342]], [[C1]]
-    ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND164]], [[COPY341]](s32)
-    ; CHECK: [[TRUNC50:%[0-9]+]]:_(s16) = G_TRUNC [[SHL50]](s32)
-    ; CHECK: [[OR50:%[0-9]+]]:_(s16) = G_OR [[OR49]], [[TRUNC50]]
-    ; CHECK: [[COPY343:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY344:%[0-9]+]]:_(s32) = COPY [[LSHR73]](s32)
-    ; CHECK: [[AND165:%[0-9]+]]:_(s32) = G_AND [[COPY344]], [[C1]]
-    ; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND165]], [[COPY343]](s32)
-    ; CHECK: [[TRUNC51:%[0-9]+]]:_(s16) = G_TRUNC [[SHL51]](s32)
-    ; CHECK: [[OR51:%[0-9]+]]:_(s16) = G_OR [[OR50]], [[TRUNC51]]
-    ; CHECK: [[COPY345:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY346:%[0-9]+]]:_(s32) = COPY [[LSHR74]](s32)
-    ; CHECK: [[AND166:%[0-9]+]]:_(s32) = G_AND [[COPY346]], [[C1]]
-    ; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND166]], [[COPY345]](s32)
-    ; CHECK: [[TRUNC52:%[0-9]+]]:_(s16) = G_TRUNC [[SHL52]](s32)
-    ; CHECK: [[OR52:%[0-9]+]]:_(s16) = G_OR [[OR51]], [[TRUNC52]]
-    ; CHECK: [[COPY347:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY348:%[0-9]+]]:_(s32) = COPY [[LSHR75]](s32)
-    ; CHECK: [[AND167:%[0-9]+]]:_(s32) = G_AND [[COPY348]], [[C1]]
-    ; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND167]], [[COPY347]](s32)
-    ; CHECK: [[TRUNC53:%[0-9]+]]:_(s16) = G_TRUNC [[SHL53]](s32)
-    ; CHECK: [[OR53:%[0-9]+]]:_(s16) = G_OR [[OR52]], [[TRUNC53]]
-    ; CHECK: [[COPY349:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
-    ; CHECK: [[AND168:%[0-9]+]]:_(s16) = G_AND [[COPY349]], [[C6]]
-    ; CHECK: [[COPY350:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY351:%[0-9]+]]:_(s32) = COPY [[LSHR77]](s32)
-    ; CHECK: [[AND169:%[0-9]+]]:_(s32) = G_AND [[COPY351]], [[C1]]
-    ; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND169]], [[COPY350]](s32)
-    ; CHECK: [[TRUNC54:%[0-9]+]]:_(s16) = G_TRUNC [[SHL54]](s32)
-    ; CHECK: [[OR54:%[0-9]+]]:_(s16) = G_OR [[AND168]], [[TRUNC54]]
-    ; CHECK: [[COPY352:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY353:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
-    ; CHECK: [[AND170:%[0-9]+]]:_(s32) = G_AND [[COPY353]], [[C1]]
-    ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND170]], [[COPY352]](s32)
-    ; CHECK: [[TRUNC55:%[0-9]+]]:_(s16) = G_TRUNC [[SHL55]](s32)
-    ; CHECK: [[OR55:%[0-9]+]]:_(s16) = G_OR [[OR54]], [[TRUNC55]]
-    ; CHECK: [[COPY354:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY355:%[0-9]+]]:_(s32) = COPY [[TRUNC7]](s32)
-    ; CHECK: [[AND171:%[0-9]+]]:_(s32) = G_AND [[COPY355]], [[C1]]
-    ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[AND171]], [[COPY354]](s32)
-    ; CHECK: [[TRUNC56:%[0-9]+]]:_(s16) = G_TRUNC [[SHL56]](s32)
-    ; CHECK: [[OR56:%[0-9]+]]:_(s16) = G_OR [[OR55]], [[TRUNC56]]
-    ; CHECK: [[COPY356:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY357:%[0-9]+]]:_(s32) = COPY [[LSHR94]](s32)
-    ; CHECK: [[AND172:%[0-9]+]]:_(s32) = G_AND [[COPY357]], [[C1]]
-    ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[AND172]], [[COPY356]](s32)
-    ; CHECK: [[TRUNC57:%[0-9]+]]:_(s16) = G_TRUNC [[SHL57]](s32)
-    ; CHECK: [[OR57:%[0-9]+]]:_(s16) = G_OR [[OR56]], [[TRUNC57]]
-    ; CHECK: [[COPY358:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY359:%[0-9]+]]:_(s32) = COPY [[LSHR95]](s32)
-    ; CHECK: [[AND173:%[0-9]+]]:_(s32) = G_AND [[COPY359]], [[C1]]
-    ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[AND173]], [[COPY358]](s32)
-    ; CHECK: [[TRUNC58:%[0-9]+]]:_(s16) = G_TRUNC [[SHL58]](s32)
-    ; CHECK: [[OR58:%[0-9]+]]:_(s16) = G_OR [[OR57]], [[TRUNC58]]
-    ; CHECK: [[COPY360:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY361:%[0-9]+]]:_(s32) = COPY [[LSHR96]](s32)
-    ; CHECK: [[AND174:%[0-9]+]]:_(s32) = G_AND [[COPY361]], [[C1]]
-    ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[AND174]], [[COPY360]](s32)
-    ; CHECK: [[TRUNC59:%[0-9]+]]:_(s16) = G_TRUNC [[SHL59]](s32)
-    ; CHECK: [[OR59:%[0-9]+]]:_(s16) = G_OR [[OR58]], [[TRUNC59]]
-    ; CHECK: [[COPY362:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[COPY363:%[0-9]+]]:_(s32) = COPY [[LSHR97]](s32)
-    ; CHECK: [[AND175:%[0-9]+]]:_(s32) = G_AND [[COPY363]], [[C1]]
-    ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[AND175]], [[COPY362]](s32)
-    ; CHECK: [[TRUNC60:%[0-9]+]]:_(s16) = G_TRUNC [[SHL60]](s32)
-    ; CHECK: [[OR60:%[0-9]+]]:_(s16) = G_OR [[OR59]], [[TRUNC60]]
-    ; CHECK: [[COPY364:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
-    ; CHECK: [[COPY365:%[0-9]+]]:_(s32) = COPY [[LSHR98]](s32)
-    ; CHECK: [[AND176:%[0-9]+]]:_(s32) = G_AND [[COPY365]], [[C1]]
-    ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[AND176]], [[COPY364]](s32)
-    ; CHECK: [[TRUNC61:%[0-9]+]]:_(s16) = G_TRUNC [[SHL61]](s32)
-    ; CHECK: [[OR61:%[0-9]+]]:_(s16) = G_OR [[OR60]], [[TRUNC61]]
-    ; CHECK: [[COPY366:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
-    ; CHECK: [[COPY367:%[0-9]+]]:_(s32) = COPY [[LSHR99]](s32)
-    ; CHECK: [[AND177:%[0-9]+]]:_(s32) = G_AND [[COPY367]], [[C1]]
-    ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[AND177]], [[COPY366]](s32)
-    ; CHECK: [[TRUNC62:%[0-9]+]]:_(s16) = G_TRUNC [[SHL62]](s32)
-    ; CHECK: [[OR62:%[0-9]+]]:_(s16) = G_OR [[OR61]], [[TRUNC62]]
-    ; CHECK: [[COPY368:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
-    ; CHECK: [[COPY369:%[0-9]+]]:_(s32) = COPY [[LSHR100]](s32)
-    ; CHECK: [[AND178:%[0-9]+]]:_(s32) = G_AND [[COPY369]], [[C1]]
-    ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[AND178]], [[COPY368]](s32)
-    ; CHECK: [[TRUNC63:%[0-9]+]]:_(s16) = G_TRUNC [[SHL63]](s32)
-    ; CHECK: [[OR63:%[0-9]+]]:_(s16) = G_OR [[OR62]], [[TRUNC63]]
-    ; CHECK: [[COPY370:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
-    ; CHECK: [[COPY371:%[0-9]+]]:_(s32) = COPY [[LSHR101]](s32)
-    ; CHECK: [[AND179:%[0-9]+]]:_(s32) = G_AND [[COPY371]], [[C1]]
-    ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[AND179]], [[COPY370]](s32)
-    ; CHECK: [[TRUNC64:%[0-9]+]]:_(s16) = G_TRUNC [[SHL64]](s32)
-    ; CHECK: [[OR64:%[0-9]+]]:_(s16) = G_OR [[OR63]], [[TRUNC64]]
-    ; CHECK: [[COPY372:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
-    ; CHECK: [[COPY373:%[0-9]+]]:_(s32) = COPY [[LSHR102]](s32)
-    ; CHECK: [[AND180:%[0-9]+]]:_(s32) = G_AND [[COPY373]], [[C1]]
-    ; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[AND180]], [[COPY372]](s32)
-    ; CHECK: [[TRUNC65:%[0-9]+]]:_(s16) = G_TRUNC [[SHL65]](s32)
-    ; CHECK: [[OR65:%[0-9]+]]:_(s16) = G_OR [[OR64]], [[TRUNC65]]
-    ; CHECK: [[COPY374:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
-    ; CHECK: [[COPY375:%[0-9]+]]:_(s32) = COPY [[LSHR103]](s32)
-    ; CHECK: [[AND181:%[0-9]+]]:_(s32) = G_AND [[COPY375]], [[C1]]
-    ; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[AND181]], [[COPY374]](s32)
-    ; CHECK: [[TRUNC66:%[0-9]+]]:_(s16) = G_TRUNC [[SHL66]](s32)
-    ; CHECK: [[OR66:%[0-9]+]]:_(s16) = G_OR [[OR65]], [[TRUNC66]]
-    ; CHECK: [[COPY376:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
-    ; CHECK: [[COPY377:%[0-9]+]]:_(s32) = COPY [[LSHR104]](s32)
-    ; CHECK: [[AND182:%[0-9]+]]:_(s32) = G_AND [[COPY377]], [[C1]]
-    ; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[AND182]], [[COPY376]](s32)
-    ; CHECK: [[TRUNC67:%[0-9]+]]:_(s16) = G_TRUNC [[SHL67]](s32)
-    ; CHECK: [[OR67:%[0-9]+]]:_(s16) = G_OR [[OR66]], [[TRUNC67]]
-    ; CHECK: [[COPY378:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
-    ; CHECK: [[COPY379:%[0-9]+]]:_(s32) = COPY [[LSHR105]](s32)
-    ; CHECK: [[AND183:%[0-9]+]]:_(s32) = G_AND [[COPY379]], [[C1]]
-    ; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[AND183]], [[COPY378]](s32)
-    ; CHECK: [[TRUNC68:%[0-9]+]]:_(s16) = G_TRUNC [[SHL68]](s32)
-    ; CHECK: [[OR68:%[0-9]+]]:_(s16) = G_OR [[OR67]], [[TRUNC68]]
-    ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR53]](s16)
-    ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR68]](s16)
-    ; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C5]](s32)
-    ; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL69]]
-    ; CHECK: [[COPY380:%[0-9]+]]:_(s16) = COPY [[TRUNC8]](s16)
-    ; CHECK: [[AND184:%[0-9]+]]:_(s16) = G_AND [[COPY380]], [[C6]]
-    ; CHECK: [[COPY381:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[COPY382:%[0-9]+]]:_(s32) = COPY [[LSHR107]](s32)
-    ; CHECK: [[AND185:%[0-9]+]]:_(s32) = G_AND [[COPY382]], [[C1]]
-    ; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[AND185]], [[COPY381]](s32)
-    ; CHECK: [[TRUNC69:%[0-9]+]]:_(s16) = G_TRUNC [[SHL70]](s32)
-    ; CHECK: [[OR70:%[0-9]+]]:_(s16) = G_OR [[AND184]], [[TRUNC69]]
-    ; CHECK: [[COPY383:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[COPY384:%[0-9]+]]:_(s32) = COPY [[LSHR108]](s32)
-    ; CHECK: [[AND186:%[0-9]+]]:_(s32) = G_AND [[COPY384]], [[C1]]
-    ; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[AND186]], [[COPY383]](s32)
-    ; CHECK: [[TRUNC70:%[0-9]+]]:_(s16) = G_TRUNC [[SHL71]](s32)
-    ; CHECK: [[OR71:%[0-9]+]]:_(s16) = G_OR [[OR70]], [[TRUNC70]]
-    ; CHECK: [[COPY385:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY386:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
-    ; CHECK: [[AND187:%[0-9]+]]:_(s32) = G_AND [[COPY386]], [[C1]]
-    ; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[AND187]], [[COPY385]](s32)
-    ; CHECK: [[TRUNC71:%[0-9]+]]:_(s16) = G_TRUNC [[SHL72]](s32)
-    ; CHECK: [[OR72:%[0-9]+]]:_(s16) = G_OR [[OR71]], [[TRUNC71]]
-    ; CHECK: [[COPY387:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY61]], [[COPY60]](s32)
+    ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY63]], [[COPY62]](s32)
+    ; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[COPY65]], [[COPY64]](s32)
+    ; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR32:%[0-9]+]]:_(s32) = G_LSHR [[COPY67]], [[COPY66]](s32)
+    ; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY69:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR33:%[0-9]+]]:_(s32) = G_LSHR [[COPY69]], [[COPY68]](s32)
+    ; CHECK: [[COPY70:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY71:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR34:%[0-9]+]]:_(s32) = G_LSHR [[COPY71]], [[COPY70]](s32)
+    ; CHECK: [[COPY72:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY73:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR35:%[0-9]+]]:_(s32) = G_LSHR [[COPY73]], [[COPY72]](s32)
+    ; CHECK: [[COPY74:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY75:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR36:%[0-9]+]]:_(s32) = G_LSHR [[COPY75]], [[COPY74]](s32)
+    ; CHECK: [[COPY76:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY77:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR37:%[0-9]+]]:_(s32) = G_LSHR [[COPY77]], [[COPY76]](s32)
+    ; CHECK: [[COPY78:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY79:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR38:%[0-9]+]]:_(s32) = G_LSHR [[COPY79]], [[COPY78]](s32)
+    ; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR39:%[0-9]+]]:_(s32) = G_LSHR [[COPY81]], [[COPY80]](s32)
+    ; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR40:%[0-9]+]]:_(s32) = G_LSHR [[COPY83]], [[COPY82]](s32)
+    ; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR41:%[0-9]+]]:_(s32) = G_LSHR [[COPY85]], [[COPY84]](s32)
+    ; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR42:%[0-9]+]]:_(s32) = G_LSHR [[COPY87]], [[COPY86]](s32)
+    ; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY89:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR43:%[0-9]+]]:_(s32) = G_LSHR [[COPY89]], [[COPY88]](s32)
+    ; CHECK: [[COPY90:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY91:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[LSHR44:%[0-9]+]]:_(s32) = G_LSHR [[COPY91]], [[COPY90]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR44]](s32)
+    ; CHECK: [[COPY92:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY93:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR45:%[0-9]+]]:_(s32) = G_LSHR [[COPY93]], [[COPY92]](s32)
+    ; CHECK: [[COPY94:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY95:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR46:%[0-9]+]]:_(s32) = G_LSHR [[COPY95]], [[COPY94]](s32)
+    ; CHECK: [[COPY96:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY97:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR47:%[0-9]+]]:_(s32) = G_LSHR [[COPY97]], [[COPY96]](s32)
+    ; CHECK: [[COPY98:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY99:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR48:%[0-9]+]]:_(s32) = G_LSHR [[COPY99]], [[COPY98]](s32)
+    ; CHECK: [[COPY100:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY101:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR49:%[0-9]+]]:_(s32) = G_LSHR [[COPY101]], [[COPY100]](s32)
+    ; CHECK: [[COPY102:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY103:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR50:%[0-9]+]]:_(s32) = G_LSHR [[COPY103]], [[COPY102]](s32)
+    ; CHECK: [[COPY104:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY105:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR51:%[0-9]+]]:_(s32) = G_LSHR [[COPY105]], [[COPY104]](s32)
+    ; CHECK: [[COPY106:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY107:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR52:%[0-9]+]]:_(s32) = G_LSHR [[COPY107]], [[COPY106]](s32)
+    ; CHECK: [[COPY108:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY109:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR53:%[0-9]+]]:_(s32) = G_LSHR [[COPY109]], [[COPY108]](s32)
+    ; CHECK: [[COPY110:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY111:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR54:%[0-9]+]]:_(s32) = G_LSHR [[COPY111]], [[COPY110]](s32)
+    ; CHECK: [[COPY112:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY113:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[COPY113]], [[COPY112]](s32)
+    ; CHECK: [[COPY114:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY115:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR56:%[0-9]+]]:_(s32) = G_LSHR [[COPY115]], [[COPY114]](s32)
+    ; CHECK: [[COPY116:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY117:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR57:%[0-9]+]]:_(s32) = G_LSHR [[COPY117]], [[COPY116]](s32)
+    ; CHECK: [[COPY118:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY119:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR58:%[0-9]+]]:_(s32) = G_LSHR [[COPY119]], [[COPY118]](s32)
+    ; CHECK: [[COPY120:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY121:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR59:%[0-9]+]]:_(s32) = G_LSHR [[COPY121]], [[COPY120]](s32)
+    ; CHECK: [[COPY122:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY123:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR60:%[0-9]+]]:_(s32) = G_LSHR [[COPY123]], [[COPY122]](s32)
+    ; CHECK: [[COPY124:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY125:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR61:%[0-9]+]]:_(s32) = G_LSHR [[COPY125]], [[COPY124]](s32)
+    ; CHECK: [[COPY126:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY127:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR62:%[0-9]+]]:_(s32) = G_LSHR [[COPY127]], [[COPY126]](s32)
+    ; CHECK: [[COPY128:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY129:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR63:%[0-9]+]]:_(s32) = G_LSHR [[COPY129]], [[COPY128]](s32)
+    ; CHECK: [[COPY130:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY131:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR64:%[0-9]+]]:_(s32) = G_LSHR [[COPY131]], [[COPY130]](s32)
+    ; CHECK: [[COPY132:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY133:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR65:%[0-9]+]]:_(s32) = G_LSHR [[COPY133]], [[COPY132]](s32)
+    ; CHECK: [[COPY134:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY135:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR66:%[0-9]+]]:_(s32) = G_LSHR [[COPY135]], [[COPY134]](s32)
+    ; CHECK: [[COPY136:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY137:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR67:%[0-9]+]]:_(s32) = G_LSHR [[COPY137]], [[COPY136]](s32)
+    ; CHECK: [[COPY138:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY139:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR68:%[0-9]+]]:_(s32) = G_LSHR [[COPY139]], [[COPY138]](s32)
+    ; CHECK: [[COPY140:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY141:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR69:%[0-9]+]]:_(s32) = G_LSHR [[COPY141]], [[COPY140]](s32)
+    ; CHECK: [[COPY142:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY143:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR70:%[0-9]+]]:_(s32) = G_LSHR [[COPY143]], [[COPY142]](s32)
+    ; CHECK: [[COPY144:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY145:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR71:%[0-9]+]]:_(s32) = G_LSHR [[COPY145]], [[COPY144]](s32)
+    ; CHECK: [[COPY146:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY147:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR72:%[0-9]+]]:_(s32) = G_LSHR [[COPY147]], [[COPY146]](s32)
+    ; CHECK: [[COPY148:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY149:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR73:%[0-9]+]]:_(s32) = G_LSHR [[COPY149]], [[COPY148]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR73]](s32)
+    ; CHECK: [[COPY150:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY151:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[LSHR74:%[0-9]+]]:_(s32) = G_LSHR [[COPY151]], [[COPY150]](s32)
+    ; CHECK: [[COPY152:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY153:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR75:%[0-9]+]]:_(s32) = G_LSHR [[COPY153]], [[COPY152]](s32)
+    ; CHECK: [[COPY154:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY155:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR76:%[0-9]+]]:_(s32) = G_LSHR [[COPY155]], [[COPY154]](s32)
+    ; CHECK: [[COPY156:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY157:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR77:%[0-9]+]]:_(s32) = G_LSHR [[COPY157]], [[COPY156]](s32)
+    ; CHECK: [[COPY158:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY159:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR78:%[0-9]+]]:_(s32) = G_LSHR [[COPY159]], [[COPY158]](s32)
+    ; CHECK: [[COPY160:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY161:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR79:%[0-9]+]]:_(s32) = G_LSHR [[COPY161]], [[COPY160]](s32)
+    ; CHECK: [[COPY162:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY163:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR80:%[0-9]+]]:_(s32) = G_LSHR [[COPY163]], [[COPY162]](s32)
+    ; CHECK: [[COPY164:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY165:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR81:%[0-9]+]]:_(s32) = G_LSHR [[COPY165]], [[COPY164]](s32)
+    ; CHECK: [[COPY166:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY167:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR82:%[0-9]+]]:_(s32) = G_LSHR [[COPY167]], [[COPY166]](s32)
+    ; CHECK: [[COPY168:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY169:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR83:%[0-9]+]]:_(s32) = G_LSHR [[COPY169]], [[COPY168]](s32)
+    ; CHECK: [[COPY170:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY171:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR84:%[0-9]+]]:_(s32) = G_LSHR [[COPY171]], [[COPY170]](s32)
+    ; CHECK: [[COPY172:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY173:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR85:%[0-9]+]]:_(s32) = G_LSHR [[COPY173]], [[COPY172]](s32)
+    ; CHECK: [[COPY174:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY175:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR86:%[0-9]+]]:_(s32) = G_LSHR [[COPY175]], [[COPY174]](s32)
+    ; CHECK: [[COPY176:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY177:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR87:%[0-9]+]]:_(s32) = G_LSHR [[COPY177]], [[COPY176]](s32)
+    ; CHECK: [[COPY178:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY179:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR88:%[0-9]+]]:_(s32) = G_LSHR [[COPY179]], [[COPY178]](s32)
+    ; CHECK: [[COPY180:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY181:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR89:%[0-9]+]]:_(s32) = G_LSHR [[COPY181]], [[COPY180]](s32)
+    ; CHECK: [[COPY182:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY183:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR90:%[0-9]+]]:_(s32) = G_LSHR [[COPY183]], [[COPY182]](s32)
+    ; CHECK: [[COPY184:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY185:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR91:%[0-9]+]]:_(s32) = G_LSHR [[COPY185]], [[COPY184]](s32)
+    ; CHECK: [[COPY186:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY187:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR92:%[0-9]+]]:_(s32) = G_LSHR [[COPY187]], [[COPY186]](s32)
+    ; CHECK: [[COPY188:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY189:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR93:%[0-9]+]]:_(s32) = G_LSHR [[COPY189]], [[COPY188]](s32)
+    ; CHECK: [[COPY190:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY191:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR94:%[0-9]+]]:_(s32) = G_LSHR [[COPY191]], [[COPY190]](s32)
+    ; CHECK: [[COPY192:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY193:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR95:%[0-9]+]]:_(s32) = G_LSHR [[COPY193]], [[COPY192]](s32)
+    ; CHECK: [[COPY194:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY195:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR96:%[0-9]+]]:_(s32) = G_LSHR [[COPY195]], [[COPY194]](s32)
+    ; CHECK: [[COPY196:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY197:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR97:%[0-9]+]]:_(s32) = G_LSHR [[COPY197]], [[COPY196]](s32)
+    ; CHECK: [[COPY198:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY199:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR98:%[0-9]+]]:_(s32) = G_LSHR [[COPY199]], [[COPY198]](s32)
+    ; CHECK: [[COPY200:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY201:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR99:%[0-9]+]]:_(s32) = G_LSHR [[COPY201]], [[COPY200]](s32)
+    ; CHECK: [[COPY202:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY203:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR100:%[0-9]+]]:_(s32) = G_LSHR [[COPY203]], [[COPY202]](s32)
+    ; CHECK: [[COPY204:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY205:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR101:%[0-9]+]]:_(s32) = G_LSHR [[COPY205]], [[COPY204]](s32)
+    ; CHECK: [[COPY206:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY207:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR102:%[0-9]+]]:_(s32) = G_LSHR [[COPY207]], [[COPY206]](s32)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR102]](s32)
+    ; CHECK: [[COPY208:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY209:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR103:%[0-9]+]]:_(s32) = G_LSHR [[COPY209]], [[COPY208]](s32)
+    ; CHECK: [[COPY210:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY211:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[LSHR104:%[0-9]+]]:_(s32) = G_LSHR [[COPY211]], [[COPY210]](s32)
+    ; CHECK: [[COPY212:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY213:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR105:%[0-9]+]]:_(s32) = G_LSHR [[COPY213]], [[COPY212]](s32)
+    ; CHECK: [[COPY214:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY215:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR106:%[0-9]+]]:_(s32) = G_LSHR [[COPY215]], [[COPY214]](s32)
+    ; CHECK: [[COPY216:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY217:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR107:%[0-9]+]]:_(s32) = G_LSHR [[COPY217]], [[COPY216]](s32)
+    ; CHECK: [[COPY218:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY219:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR108:%[0-9]+]]:_(s32) = G_LSHR [[COPY219]], [[COPY218]](s32)
+    ; CHECK: [[COPY220:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY221:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR109:%[0-9]+]]:_(s32) = G_LSHR [[COPY221]], [[COPY220]](s32)
+    ; CHECK: [[COPY222:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY223:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR110:%[0-9]+]]:_(s32) = G_LSHR [[COPY223]], [[COPY222]](s32)
+    ; CHECK: [[COPY224:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY225:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR111:%[0-9]+]]:_(s32) = G_LSHR [[COPY225]], [[COPY224]](s32)
+    ; CHECK: [[COPY226:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY227:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR112:%[0-9]+]]:_(s32) = G_LSHR [[COPY227]], [[COPY226]](s32)
+    ; CHECK: [[COPY228:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY229:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR113:%[0-9]+]]:_(s32) = G_LSHR [[COPY229]], [[COPY228]](s32)
+    ; CHECK: [[COPY230:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY231:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR114:%[0-9]+]]:_(s32) = G_LSHR [[COPY231]], [[COPY230]](s32)
+    ; CHECK: [[COPY232:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY233:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR115:%[0-9]+]]:_(s32) = G_LSHR [[COPY233]], [[COPY232]](s32)
+    ; CHECK: [[COPY234:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY235:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR116:%[0-9]+]]:_(s32) = G_LSHR [[COPY235]], [[COPY234]](s32)
+    ; CHECK: [[COPY236:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY237:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR117:%[0-9]+]]:_(s32) = G_LSHR [[COPY237]], [[COPY236]](s32)
+    ; CHECK: [[COPY238:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY239:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR118:%[0-9]+]]:_(s32) = G_LSHR [[COPY239]], [[COPY238]](s32)
+    ; CHECK: [[COPY240:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY241:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[LSHR119:%[0-9]+]]:_(s32) = G_LSHR [[COPY241]], [[COPY240]](s32)
+    ; CHECK: [[COPY242:%[0-9]+]]:_(s16) = COPY [[COPY]](s16)
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY242]], [[C6]]
+    ; CHECK: [[COPY243:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY244:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY244]], [[C1]]
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY243]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC3]]
+    ; CHECK: [[COPY245:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY246:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY246]], [[C1]]
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY245]](s32)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC4]]
+    ; CHECK: [[COPY247:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY248:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY248]], [[C1]]
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY247]](s32)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC5]]
+    ; CHECK: [[COPY249:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY250:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
+    ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY250]], [[C1]]
+    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[COPY249]](s32)
+    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[OR2]], [[TRUNC6]]
+    ; CHECK: [[COPY251:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY252:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY252]], [[C1]]
+    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY251]](s32)
+    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
+    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC7]]
+    ; CHECK: [[COPY253:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY254:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
+    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY254]], [[C1]]
+    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[COPY253]](s32)
+    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
+    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC8]]
+    ; CHECK: [[COPY255:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY256:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY256]], [[C1]]
+    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY255]](s32)
+    ; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
+    ; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[OR5]], [[TRUNC9]]
+    ; CHECK: [[COPY257:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY258:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
+    ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY258]], [[C1]]
+    ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[COPY257]](s32)
+    ; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
+    ; CHECK: [[OR7:%[0-9]+]]:_(s16) = G_OR [[OR6]], [[TRUNC10]]
+    ; CHECK: [[COPY259:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY260:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
+    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY260]], [[C1]]
+    ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY259]](s32)
+    ; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
+    ; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[OR7]], [[TRUNC11]]
+    ; CHECK: [[COPY261:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY262:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
+    ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY262]], [[C1]]
+    ; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[COPY261]](s32)
+    ; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
+    ; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[OR8]], [[TRUNC12]]
+    ; CHECK: [[COPY263:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY264:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
+    ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY264]], [[C1]]
+    ; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY263]](s32)
+    ; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL10]](s32)
+    ; CHECK: [[OR10:%[0-9]+]]:_(s16) = G_OR [[OR9]], [[TRUNC13]]
+    ; CHECK: [[COPY265:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY266:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
+    ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY266]], [[C1]]
+    ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[COPY265]](s32)
+    ; CHECK: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[SHL11]](s32)
+    ; CHECK: [[OR11:%[0-9]+]]:_(s16) = G_OR [[OR10]], [[TRUNC14]]
+    ; CHECK: [[COPY267:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY268:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
+    ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY268]], [[C1]]
+    ; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY267]](s32)
+    ; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
+    ; CHECK: [[OR12:%[0-9]+]]:_(s16) = G_OR [[OR11]], [[TRUNC15]]
+    ; CHECK: [[COPY269:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY270:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
+    ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY270]], [[C1]]
+    ; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[COPY269]](s32)
+    ; CHECK: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
+    ; CHECK: [[OR13:%[0-9]+]]:_(s16) = G_OR [[OR12]], [[TRUNC16]]
+    ; CHECK: [[COPY271:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY272:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
+    ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY272]], [[C1]]
+    ; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY271]](s32)
+    ; CHECK: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
+    ; CHECK: [[OR14:%[0-9]+]]:_(s16) = G_OR [[OR13]], [[TRUNC17]]
+    ; CHECK: [[COPY273:%[0-9]+]]:_(s16) = COPY [[COPY1]](s16)
+    ; CHECK: [[AND16:%[0-9]+]]:_(s16) = G_AND [[COPY273]], [[C6]]
+    ; CHECK: [[COPY274:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY275:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY275]], [[C1]]
+    ; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY274]](s32)
+    ; CHECK: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
+    ; CHECK: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC18]]
+    ; CHECK: [[COPY276:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY277:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
+    ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY277]], [[C1]]
+    ; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[COPY276]](s32)
+    ; CHECK: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL16]](s32)
+    ; CHECK: [[OR16:%[0-9]+]]:_(s16) = G_OR [[OR15]], [[TRUNC19]]
+    ; CHECK: [[COPY278:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY279:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
+    ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY279]], [[C1]]
+    ; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY278]](s32)
+    ; CHECK: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[SHL17]](s32)
+    ; CHECK: [[OR17:%[0-9]+]]:_(s16) = G_OR [[OR16]], [[TRUNC20]]
+    ; CHECK: [[COPY280:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY281:%[0-9]+]]:_(s32) = COPY [[LSHR32]](s32)
+    ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY281]], [[C1]]
+    ; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[COPY280]](s32)
+    ; CHECK: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
+    ; CHECK: [[OR18:%[0-9]+]]:_(s16) = G_OR [[OR17]], [[TRUNC21]]
+    ; CHECK: [[COPY282:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY283:%[0-9]+]]:_(s32) = COPY [[LSHR33]](s32)
+    ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY283]], [[C1]]
+    ; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY282]](s32)
+    ; CHECK: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
+    ; CHECK: [[OR19:%[0-9]+]]:_(s16) = G_OR [[OR18]], [[TRUNC22]]
+    ; CHECK: [[COPY284:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY285:%[0-9]+]]:_(s32) = COPY [[LSHR34]](s32)
+    ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY285]], [[C1]]
+    ; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[COPY284]](s32)
+    ; CHECK: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
+    ; CHECK: [[OR20:%[0-9]+]]:_(s16) = G_OR [[OR19]], [[TRUNC23]]
+    ; CHECK: [[COPY286:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY287:%[0-9]+]]:_(s32) = COPY [[LSHR35]](s32)
+    ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY287]], [[C1]]
+    ; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY286]](s32)
+    ; CHECK: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
+    ; CHECK: [[OR21:%[0-9]+]]:_(s16) = G_OR [[OR20]], [[TRUNC24]]
+    ; CHECK: [[COPY288:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY289:%[0-9]+]]:_(s32) = COPY [[LSHR36]](s32)
+    ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY289]], [[C1]]
+    ; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[COPY288]](s32)
+    ; CHECK: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL22]](s32)
+    ; CHECK: [[OR22:%[0-9]+]]:_(s16) = G_OR [[OR21]], [[TRUNC25]]
+    ; CHECK: [[COPY290:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY291:%[0-9]+]]:_(s32) = COPY [[LSHR37]](s32)
+    ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY291]], [[C1]]
+    ; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY290]](s32)
+    ; CHECK: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[SHL23]](s32)
+    ; CHECK: [[OR23:%[0-9]+]]:_(s16) = G_OR [[OR22]], [[TRUNC26]]
+    ; CHECK: [[COPY292:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY293:%[0-9]+]]:_(s32) = COPY [[LSHR38]](s32)
+    ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY293]], [[C1]]
+    ; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[COPY292]](s32)
+    ; CHECK: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL24]](s32)
+    ; CHECK: [[OR24:%[0-9]+]]:_(s16) = G_OR [[OR23]], [[TRUNC27]]
+    ; CHECK: [[COPY294:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY295:%[0-9]+]]:_(s32) = COPY [[LSHR39]](s32)
+    ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY295]], [[C1]]
+    ; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY294]](s32)
+    ; CHECK: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[SHL25]](s32)
+    ; CHECK: [[OR25:%[0-9]+]]:_(s16) = G_OR [[OR24]], [[TRUNC28]]
+    ; CHECK: [[COPY296:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY297:%[0-9]+]]:_(s32) = COPY [[LSHR40]](s32)
+    ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY297]], [[C1]]
+    ; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[COPY296]](s32)
+    ; CHECK: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL26]](s32)
+    ; CHECK: [[OR26:%[0-9]+]]:_(s16) = G_OR [[OR25]], [[TRUNC29]]
+    ; CHECK: [[COPY298:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY299:%[0-9]+]]:_(s32) = COPY [[LSHR41]](s32)
+    ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY299]], [[C1]]
+    ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY298]](s32)
+    ; CHECK: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[SHL27]](s32)
+    ; CHECK: [[OR27:%[0-9]+]]:_(s16) = G_OR [[OR26]], [[TRUNC30]]
+    ; CHECK: [[COPY300:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY301:%[0-9]+]]:_(s32) = COPY [[LSHR42]](s32)
+    ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY301]], [[C1]]
+    ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[COPY300]](s32)
+    ; CHECK: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL28]](s32)
+    ; CHECK: [[OR28:%[0-9]+]]:_(s16) = G_OR [[OR27]], [[TRUNC31]]
+    ; CHECK: [[COPY302:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY303:%[0-9]+]]:_(s32) = COPY [[LSHR43]](s32)
+    ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY303]], [[C1]]
+    ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY302]](s32)
+    ; CHECK: [[TRUNC32:%[0-9]+]]:_(s16) = G_TRUNC [[SHL29]](s32)
+    ; CHECK: [[OR29:%[0-9]+]]:_(s16) = G_OR [[OR28]], [[TRUNC32]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR14]](s16)
+    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR29]](s16)
+    ; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
+    ; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL30]]
+    ; CHECK: [[COPY304:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
+    ; CHECK: [[AND32:%[0-9]+]]:_(s16) = G_AND [[COPY304]], [[C6]]
+    ; CHECK: [[COPY305:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY306:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY306]], [[C1]]
+    ; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND33]], [[COPY305]](s32)
+    ; CHECK: [[TRUNC33:%[0-9]+]]:_(s16) = G_TRUNC [[SHL31]](s32)
+    ; CHECK: [[OR31:%[0-9]+]]:_(s16) = G_OR [[AND32]], [[TRUNC33]]
+    ; CHECK: [[COPY307:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY308:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY308]], [[C1]]
+    ; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[COPY307]](s32)
+    ; CHECK: [[TRUNC34:%[0-9]+]]:_(s16) = G_TRUNC [[SHL32]](s32)
+    ; CHECK: [[OR32:%[0-9]+]]:_(s16) = G_OR [[OR31]], [[TRUNC34]]
+    ; CHECK: [[COPY309:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY310:%[0-9]+]]:_(s32) = COPY [[LSHR60]](s32)
+    ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY310]], [[C1]]
+    ; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[COPY309]](s32)
+    ; CHECK: [[TRUNC35:%[0-9]+]]:_(s16) = G_TRUNC [[SHL33]](s32)
+    ; CHECK: [[OR33:%[0-9]+]]:_(s16) = G_OR [[OR32]], [[TRUNC35]]
+    ; CHECK: [[COPY311:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY312:%[0-9]+]]:_(s32) = COPY [[LSHR61]](s32)
+    ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY312]], [[C1]]
+    ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[COPY311]](s32)
+    ; CHECK: [[TRUNC36:%[0-9]+]]:_(s16) = G_TRUNC [[SHL34]](s32)
+    ; CHECK: [[OR34:%[0-9]+]]:_(s16) = G_OR [[OR33]], [[TRUNC36]]
+    ; CHECK: [[COPY313:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY314:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
+    ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY314]], [[C1]]
+    ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[COPY313]](s32)
+    ; CHECK: [[TRUNC37:%[0-9]+]]:_(s16) = G_TRUNC [[SHL35]](s32)
+    ; CHECK: [[OR35:%[0-9]+]]:_(s16) = G_OR [[OR34]], [[TRUNC37]]
+    ; CHECK: [[COPY315:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY316:%[0-9]+]]:_(s32) = COPY [[LSHR63]](s32)
+    ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY316]], [[C1]]
+    ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[COPY315]](s32)
+    ; CHECK: [[TRUNC38:%[0-9]+]]:_(s16) = G_TRUNC [[SHL36]](s32)
+    ; CHECK: [[OR36:%[0-9]+]]:_(s16) = G_OR [[OR35]], [[TRUNC38]]
+    ; CHECK: [[COPY317:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY318:%[0-9]+]]:_(s32) = COPY [[LSHR64]](s32)
+    ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY318]], [[C1]]
+    ; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[COPY317]](s32)
+    ; CHECK: [[TRUNC39:%[0-9]+]]:_(s16) = G_TRUNC [[SHL37]](s32)
+    ; CHECK: [[OR37:%[0-9]+]]:_(s16) = G_OR [[OR36]], [[TRUNC39]]
+    ; CHECK: [[COPY319:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY320:%[0-9]+]]:_(s32) = COPY [[LSHR65]](s32)
+    ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY320]], [[C1]]
+    ; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[COPY319]](s32)
+    ; CHECK: [[TRUNC40:%[0-9]+]]:_(s16) = G_TRUNC [[SHL38]](s32)
+    ; CHECK: [[OR38:%[0-9]+]]:_(s16) = G_OR [[OR37]], [[TRUNC40]]
+    ; CHECK: [[COPY321:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY322:%[0-9]+]]:_(s32) = COPY [[LSHR66]](s32)
+    ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY322]], [[C1]]
+    ; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[COPY321]](s32)
+    ; CHECK: [[TRUNC41:%[0-9]+]]:_(s16) = G_TRUNC [[SHL39]](s32)
+    ; CHECK: [[OR39:%[0-9]+]]:_(s16) = G_OR [[OR38]], [[TRUNC41]]
+    ; CHECK: [[COPY323:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY324:%[0-9]+]]:_(s32) = COPY [[LSHR67]](s32)
+    ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY324]], [[C1]]
+    ; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[COPY323]](s32)
+    ; CHECK: [[TRUNC42:%[0-9]+]]:_(s16) = G_TRUNC [[SHL40]](s32)
+    ; CHECK: [[OR40:%[0-9]+]]:_(s16) = G_OR [[OR39]], [[TRUNC42]]
+    ; CHECK: [[COPY325:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY326:%[0-9]+]]:_(s32) = COPY [[LSHR68]](s32)
+    ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY326]], [[C1]]
+    ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[COPY325]](s32)
+    ; CHECK: [[TRUNC43:%[0-9]+]]:_(s16) = G_TRUNC [[SHL41]](s32)
+    ; CHECK: [[OR41:%[0-9]+]]:_(s16) = G_OR [[OR40]], [[TRUNC43]]
+    ; CHECK: [[COPY327:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY328:%[0-9]+]]:_(s32) = COPY [[LSHR69]](s32)
+    ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY328]], [[C1]]
+    ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[COPY327]](s32)
+    ; CHECK: [[TRUNC44:%[0-9]+]]:_(s16) = G_TRUNC [[SHL42]](s32)
+    ; CHECK: [[OR42:%[0-9]+]]:_(s16) = G_OR [[OR41]], [[TRUNC44]]
+    ; CHECK: [[COPY329:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY330:%[0-9]+]]:_(s32) = COPY [[LSHR70]](s32)
+    ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY330]], [[C1]]
+    ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[COPY329]](s32)
+    ; CHECK: [[TRUNC45:%[0-9]+]]:_(s16) = G_TRUNC [[SHL43]](s32)
+    ; CHECK: [[OR43:%[0-9]+]]:_(s16) = G_OR [[OR42]], [[TRUNC45]]
+    ; CHECK: [[COPY331:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY332:%[0-9]+]]:_(s32) = COPY [[LSHR71]](s32)
+    ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY332]], [[C1]]
+    ; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[COPY331]](s32)
+    ; CHECK: [[TRUNC46:%[0-9]+]]:_(s16) = G_TRUNC [[SHL44]](s32)
+    ; CHECK: [[OR44:%[0-9]+]]:_(s16) = G_OR [[OR43]], [[TRUNC46]]
+    ; CHECK: [[COPY333:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY334:%[0-9]+]]:_(s32) = COPY [[LSHR72]](s32)
+    ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY334]], [[C1]]
+    ; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[COPY333]](s32)
+    ; CHECK: [[TRUNC47:%[0-9]+]]:_(s16) = G_TRUNC [[SHL45]](s32)
+    ; CHECK: [[OR45:%[0-9]+]]:_(s16) = G_OR [[OR44]], [[TRUNC47]]
+    ; CHECK: [[COPY335:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
+    ; CHECK: [[AND48:%[0-9]+]]:_(s16) = G_AND [[COPY335]], [[C6]]
+    ; CHECK: [[COPY336:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY337:%[0-9]+]]:_(s32) = COPY [[LSHR74]](s32)
+    ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY337]], [[C1]]
+    ; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND49]], [[COPY336]](s32)
+    ; CHECK: [[TRUNC48:%[0-9]+]]:_(s16) = G_TRUNC [[SHL46]](s32)
+    ; CHECK: [[OR46:%[0-9]+]]:_(s16) = G_OR [[AND48]], [[TRUNC48]]
+    ; CHECK: [[COPY338:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY339:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY339]], [[C1]]
+    ; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[COPY338]](s32)
+    ; CHECK: [[TRUNC49:%[0-9]+]]:_(s16) = G_TRUNC [[SHL47]](s32)
+    ; CHECK: [[OR47:%[0-9]+]]:_(s16) = G_OR [[OR46]], [[TRUNC49]]
+    ; CHECK: [[COPY340:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY341:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY341]], [[C1]]
+    ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[COPY340]](s32)
+    ; CHECK: [[TRUNC50:%[0-9]+]]:_(s16) = G_TRUNC [[SHL48]](s32)
+    ; CHECK: [[OR48:%[0-9]+]]:_(s16) = G_OR [[OR47]], [[TRUNC50]]
+    ; CHECK: [[COPY342:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY343:%[0-9]+]]:_(s32) = COPY [[LSHR90]](s32)
+    ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY343]], [[C1]]
+    ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[COPY342]](s32)
+    ; CHECK: [[TRUNC51:%[0-9]+]]:_(s16) = G_TRUNC [[SHL49]](s32)
+    ; CHECK: [[OR49:%[0-9]+]]:_(s16) = G_OR [[OR48]], [[TRUNC51]]
+    ; CHECK: [[COPY344:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY345:%[0-9]+]]:_(s32) = COPY [[LSHR91]](s32)
+    ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY345]], [[C1]]
+    ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[COPY344]](s32)
+    ; CHECK: [[TRUNC52:%[0-9]+]]:_(s16) = G_TRUNC [[SHL50]](s32)
+    ; CHECK: [[OR50:%[0-9]+]]:_(s16) = G_OR [[OR49]], [[TRUNC52]]
+    ; CHECK: [[COPY346:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY347:%[0-9]+]]:_(s32) = COPY [[LSHR92]](s32)
+    ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY347]], [[C1]]
+    ; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[COPY346]](s32)
+    ; CHECK: [[TRUNC53:%[0-9]+]]:_(s16) = G_TRUNC [[SHL51]](s32)
+    ; CHECK: [[OR51:%[0-9]+]]:_(s16) = G_OR [[OR50]], [[TRUNC53]]
+    ; CHECK: [[COPY348:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY349:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
+    ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY349]], [[C1]]
+    ; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[COPY348]](s32)
+    ; CHECK: [[TRUNC54:%[0-9]+]]:_(s16) = G_TRUNC [[SHL52]](s32)
+    ; CHECK: [[OR52:%[0-9]+]]:_(s16) = G_OR [[OR51]], [[TRUNC54]]
+    ; CHECK: [[COPY350:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY351:%[0-9]+]]:_(s32) = COPY [[LSHR94]](s32)
+    ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY351]], [[C1]]
+    ; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[COPY350]](s32)
+    ; CHECK: [[TRUNC55:%[0-9]+]]:_(s16) = G_TRUNC [[SHL53]](s32)
+    ; CHECK: [[OR53:%[0-9]+]]:_(s16) = G_OR [[OR52]], [[TRUNC55]]
+    ; CHECK: [[COPY352:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY353:%[0-9]+]]:_(s32) = COPY [[LSHR95]](s32)
+    ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY353]], [[C1]]
+    ; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND57]], [[COPY352]](s32)
+    ; CHECK: [[TRUNC56:%[0-9]+]]:_(s16) = G_TRUNC [[SHL54]](s32)
+    ; CHECK: [[OR54:%[0-9]+]]:_(s16) = G_OR [[OR53]], [[TRUNC56]]
+    ; CHECK: [[COPY354:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY355:%[0-9]+]]:_(s32) = COPY [[LSHR96]](s32)
+    ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY355]], [[C1]]
+    ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[COPY354]](s32)
+    ; CHECK: [[TRUNC57:%[0-9]+]]:_(s16) = G_TRUNC [[SHL55]](s32)
+    ; CHECK: [[OR55:%[0-9]+]]:_(s16) = G_OR [[OR54]], [[TRUNC57]]
+    ; CHECK: [[COPY356:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[COPY357:%[0-9]+]]:_(s32) = COPY [[LSHR97]](s32)
+    ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY357]], [[C1]]
+    ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[COPY356]](s32)
+    ; CHECK: [[TRUNC58:%[0-9]+]]:_(s16) = G_TRUNC [[SHL56]](s32)
+    ; CHECK: [[OR56:%[0-9]+]]:_(s16) = G_OR [[OR55]], [[TRUNC58]]
+    ; CHECK: [[COPY358:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[COPY359:%[0-9]+]]:_(s32) = COPY [[LSHR98]](s32)
+    ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY359]], [[C1]]
+    ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[COPY358]](s32)
+    ; CHECK: [[TRUNC59:%[0-9]+]]:_(s16) = G_TRUNC [[SHL57]](s32)
+    ; CHECK: [[OR57:%[0-9]+]]:_(s16) = G_OR [[OR56]], [[TRUNC59]]
+    ; CHECK: [[COPY360:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[COPY361:%[0-9]+]]:_(s32) = COPY [[LSHR99]](s32)
+    ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY361]], [[C1]]
+    ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[COPY360]](s32)
+    ; CHECK: [[TRUNC60:%[0-9]+]]:_(s16) = G_TRUNC [[SHL58]](s32)
+    ; CHECK: [[OR58:%[0-9]+]]:_(s16) = G_OR [[OR57]], [[TRUNC60]]
+    ; CHECK: [[COPY362:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[COPY363:%[0-9]+]]:_(s32) = COPY [[LSHR100]](s32)
+    ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY363]], [[C1]]
+    ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[COPY362]](s32)
+    ; CHECK: [[TRUNC61:%[0-9]+]]:_(s16) = G_TRUNC [[SHL59]](s32)
+    ; CHECK: [[OR59:%[0-9]+]]:_(s16) = G_OR [[OR58]], [[TRUNC61]]
+    ; CHECK: [[COPY364:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[COPY365:%[0-9]+]]:_(s32) = COPY [[LSHR101]](s32)
+    ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY365]], [[C1]]
+    ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[COPY364]](s32)
+    ; CHECK: [[TRUNC62:%[0-9]+]]:_(s16) = G_TRUNC [[SHL60]](s32)
+    ; CHECK: [[OR60:%[0-9]+]]:_(s16) = G_OR [[OR59]], [[TRUNC62]]
+    ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR45]](s16)
+    ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR60]](s16)
+    ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C5]](s32)
+    ; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL61]]
+    ; CHECK: [[COPY366:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
+    ; CHECK: [[AND64:%[0-9]+]]:_(s16) = G_AND [[COPY366]], [[C6]]
+    ; CHECK: [[COPY367:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY368:%[0-9]+]]:_(s32) = COPY [[LSHR103]](s32)
+    ; CHECK: [[AND65:%[0-9]+]]:_(s32) = G_AND [[COPY368]], [[C1]]
+    ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[AND65]], [[COPY367]](s32)
+    ; CHECK: [[TRUNC63:%[0-9]+]]:_(s16) = G_TRUNC [[SHL62]](s32)
+    ; CHECK: [[OR62:%[0-9]+]]:_(s16) = G_OR [[AND64]], [[TRUNC63]]
+    ; CHECK: [[COPY369:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[COPY370:%[0-9]+]]:_(s32) = COPY [[LSHR104]](s32)
+    ; CHECK: [[AND66:%[0-9]+]]:_(s32) = G_AND [[COPY370]], [[C1]]
+    ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[AND66]], [[COPY369]](s32)
+    ; CHECK: [[TRUNC64:%[0-9]+]]:_(s16) = G_TRUNC [[SHL63]](s32)
+    ; CHECK: [[OR63:%[0-9]+]]:_(s16) = G_OR [[OR62]], [[TRUNC64]]
+    ; CHECK: [[COPY371:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY372:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND67:%[0-9]+]]:_(s32) = G_AND [[COPY372]], [[C1]]
+    ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[AND67]], [[COPY371]](s32)
+    ; CHECK: [[TRUNC65:%[0-9]+]]:_(s16) = G_TRUNC [[SHL64]](s32)
+    ; CHECK: [[OR64:%[0-9]+]]:_(s16) = G_OR [[OR63]], [[TRUNC65]]
+    ; CHECK: [[COPY373:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+    ; CHECK: [[COPY374:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY374]], [[COPY373]](s32)
+    ; CHECK: [[TRUNC66:%[0-9]+]]:_(s16) = G_TRUNC [[SHL65]](s32)
+    ; CHECK: [[OR65:%[0-9]+]]:_(s16) = G_OR [[OR64]], [[TRUNC66]]
+    ; CHECK: [[COPY375:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+    ; CHECK: [[COPY376:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY376]], [[COPY375]](s32)
+    ; CHECK: [[TRUNC67:%[0-9]+]]:_(s16) = G_TRUNC [[SHL66]](s32)
+    ; CHECK: [[OR66:%[0-9]+]]:_(s16) = G_OR [[OR65]], [[TRUNC67]]
+    ; CHECK: [[COPY377:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY378:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY378]], [[COPY377]](s32)
+    ; CHECK: [[TRUNC68:%[0-9]+]]:_(s16) = G_TRUNC [[SHL67]](s32)
+    ; CHECK: [[OR67:%[0-9]+]]:_(s16) = G_OR [[OR66]], [[TRUNC68]]
+    ; CHECK: [[COPY379:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY380:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY380]], [[COPY379]](s32)
+    ; CHECK: [[TRUNC69:%[0-9]+]]:_(s16) = G_TRUNC [[SHL68]](s32)
+    ; CHECK: [[OR68:%[0-9]+]]:_(s16) = G_OR [[OR67]], [[TRUNC69]]
+    ; CHECK: [[COPY381:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY382:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY382]], [[COPY381]](s32)
+    ; CHECK: [[TRUNC70:%[0-9]+]]:_(s16) = G_TRUNC [[SHL69]](s32)
+    ; CHECK: [[OR69:%[0-9]+]]:_(s16) = G_OR [[OR68]], [[TRUNC70]]
+    ; CHECK: [[COPY383:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[COPY384:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY384]], [[COPY383]](s32)
+    ; CHECK: [[TRUNC71:%[0-9]+]]:_(s16) = G_TRUNC [[SHL70]](s32)
+    ; CHECK: [[OR70:%[0-9]+]]:_(s16) = G_OR [[OR69]], [[TRUNC71]]
+    ; CHECK: [[COPY385:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[COPY386:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY386]], [[COPY385]](s32)
+    ; CHECK: [[TRUNC72:%[0-9]+]]:_(s16) = G_TRUNC [[SHL71]](s32)
+    ; CHECK: [[OR71:%[0-9]+]]:_(s16) = G_OR [[OR70]], [[TRUNC72]]
+    ; CHECK: [[COPY387:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
     ; CHECK: [[COPY388:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY388]], [[COPY387]](s32)
-    ; CHECK: [[TRUNC72:%[0-9]+]]:_(s16) = G_TRUNC [[SHL73]](s32)
-    ; CHECK: [[OR73:%[0-9]+]]:_(s16) = G_OR [[OR72]], [[TRUNC72]]
-    ; CHECK: [[COPY389:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY388]], [[COPY387]](s32)
+    ; CHECK: [[TRUNC73:%[0-9]+]]:_(s16) = G_TRUNC [[SHL72]](s32)
+    ; CHECK: [[OR72:%[0-9]+]]:_(s16) = G_OR [[OR71]], [[TRUNC73]]
+    ; CHECK: [[COPY389:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
     ; CHECK: [[COPY390:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY390]], [[COPY389]](s32)
-    ; CHECK: [[TRUNC73:%[0-9]+]]:_(s16) = G_TRUNC [[SHL74]](s32)
-    ; CHECK: [[OR74:%[0-9]+]]:_(s16) = G_OR [[OR73]], [[TRUNC73]]
-    ; CHECK: [[COPY391:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY390]], [[COPY389]](s32)
+    ; CHECK: [[TRUNC74:%[0-9]+]]:_(s16) = G_TRUNC [[SHL73]](s32)
+    ; CHECK: [[OR73:%[0-9]+]]:_(s16) = G_OR [[OR72]], [[TRUNC74]]
+    ; CHECK: [[COPY391:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
     ; CHECK: [[COPY392:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY392]], [[COPY391]](s32)
-    ; CHECK: [[TRUNC74:%[0-9]+]]:_(s16) = G_TRUNC [[SHL75]](s32)
-    ; CHECK: [[OR75:%[0-9]+]]:_(s16) = G_OR [[OR74]], [[TRUNC74]]
-    ; CHECK: [[COPY393:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY392]], [[COPY391]](s32)
+    ; CHECK: [[TRUNC75:%[0-9]+]]:_(s16) = G_TRUNC [[SHL74]](s32)
+    ; CHECK: [[OR74:%[0-9]+]]:_(s16) = G_OR [[OR73]], [[TRUNC75]]
+    ; CHECK: [[COPY393:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
     ; CHECK: [[COPY394:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY394]], [[COPY393]](s32)
-    ; CHECK: [[TRUNC75:%[0-9]+]]:_(s16) = G_TRUNC [[SHL76]](s32)
-    ; CHECK: [[OR76:%[0-9]+]]:_(s16) = G_OR [[OR75]], [[TRUNC75]]
-    ; CHECK: [[COPY395:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+    ; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY394]], [[COPY393]](s32)
+    ; CHECK: [[TRUNC76:%[0-9]+]]:_(s16) = G_TRUNC [[SHL75]](s32)
+    ; CHECK: [[OR75:%[0-9]+]]:_(s16) = G_OR [[OR74]], [[TRUNC76]]
+    ; CHECK: [[COPY395:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
     ; CHECK: [[COPY396:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY396]], [[COPY395]](s32)
-    ; CHECK: [[TRUNC76:%[0-9]+]]:_(s16) = G_TRUNC [[SHL77]](s32)
-    ; CHECK: [[OR77:%[0-9]+]]:_(s16) = G_OR [[OR76]], [[TRUNC76]]
-    ; CHECK: [[COPY397:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+    ; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY396]], [[COPY395]](s32)
+    ; CHECK: [[TRUNC77:%[0-9]+]]:_(s16) = G_TRUNC [[SHL76]](s32)
+    ; CHECK: [[OR76:%[0-9]+]]:_(s16) = G_OR [[OR75]], [[TRUNC77]]
+    ; CHECK: [[COPY397:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
     ; CHECK: [[COPY398:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY398]], [[COPY397]](s32)
-    ; CHECK: [[TRUNC77:%[0-9]+]]:_(s16) = G_TRUNC [[SHL78]](s32)
-    ; CHECK: [[OR78:%[0-9]+]]:_(s16) = G_OR [[OR77]], [[TRUNC77]]
-    ; CHECK: [[COPY399:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+    ; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY398]], [[COPY397]](s32)
+    ; CHECK: [[TRUNC78:%[0-9]+]]:_(s16) = G_TRUNC [[SHL77]](s32)
+    ; CHECK: [[OR77:%[0-9]+]]:_(s16) = G_OR [[C4]], [[TRUNC78]]
+    ; CHECK: [[COPY399:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
     ; CHECK: [[COPY400:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY400]], [[COPY399]](s32)
-    ; CHECK: [[TRUNC78:%[0-9]+]]:_(s16) = G_TRUNC [[SHL79]](s32)
-    ; CHECK: [[OR79:%[0-9]+]]:_(s16) = G_OR [[OR78]], [[TRUNC78]]
-    ; CHECK: [[COPY401:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+    ; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY400]], [[COPY399]](s32)
+    ; CHECK: [[TRUNC79:%[0-9]+]]:_(s16) = G_TRUNC [[SHL78]](s32)
+    ; CHECK: [[OR78:%[0-9]+]]:_(s16) = G_OR [[OR77]], [[TRUNC79]]
+    ; CHECK: [[COPY401:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
     ; CHECK: [[COPY402:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY402]], [[COPY401]](s32)
-    ; CHECK: [[TRUNC79:%[0-9]+]]:_(s16) = G_TRUNC [[SHL80]](s32)
-    ; CHECK: [[OR80:%[0-9]+]]:_(s16) = G_OR [[OR79]], [[TRUNC79]]
-    ; CHECK: [[COPY403:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+    ; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY402]], [[COPY401]](s32)
+    ; CHECK: [[TRUNC80:%[0-9]+]]:_(s16) = G_TRUNC [[SHL79]](s32)
+    ; CHECK: [[OR79:%[0-9]+]]:_(s16) = G_OR [[OR78]], [[TRUNC80]]
+    ; CHECK: [[COPY403:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY403]], [[C7]](s32)
+    ; CHECK: [[TRUNC81:%[0-9]+]]:_(s16) = G_TRUNC [[SHL80]](s32)
+    ; CHECK: [[OR80:%[0-9]+]]:_(s16) = G_OR [[OR79]], [[TRUNC81]]
     ; CHECK: [[COPY404:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY404]], [[COPY403]](s32)
-    ; CHECK: [[TRUNC80:%[0-9]+]]:_(s16) = G_TRUNC [[SHL81]](s32)
-    ; CHECK: [[OR81:%[0-9]+]]:_(s16) = G_OR [[OR80]], [[TRUNC80]]
-    ; CHECK: [[COPY405:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+    ; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY404]], [[C8]](s32)
+    ; CHECK: [[TRUNC82:%[0-9]+]]:_(s16) = G_TRUNC [[SHL81]](s32)
+    ; CHECK: [[OR81:%[0-9]+]]:_(s16) = G_OR [[OR80]], [[TRUNC82]]
+    ; CHECK: [[COPY405:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY405]], [[C9]](s32)
+    ; CHECK: [[TRUNC83:%[0-9]+]]:_(s16) = G_TRUNC [[SHL82]](s32)
+    ; CHECK: [[OR82:%[0-9]+]]:_(s16) = G_OR [[OR81]], [[TRUNC83]]
     ; CHECK: [[COPY406:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY406]], [[COPY405]](s32)
-    ; CHECK: [[TRUNC81:%[0-9]+]]:_(s16) = G_TRUNC [[SHL82]](s32)
-    ; CHECK: [[OR82:%[0-9]+]]:_(s16) = G_OR [[OR81]], [[TRUNC81]]
-    ; CHECK: [[COPY407:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+    ; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY406]], [[C10]](s32)
+    ; CHECK: [[TRUNC84:%[0-9]+]]:_(s16) = G_TRUNC [[SHL83]](s32)
+    ; CHECK: [[OR83:%[0-9]+]]:_(s16) = G_OR [[OR82]], [[TRUNC84]]
+    ; CHECK: [[COPY407:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY407]], [[C11]](s32)
+    ; CHECK: [[TRUNC85:%[0-9]+]]:_(s16) = G_TRUNC [[SHL84]](s32)
+    ; CHECK: [[OR84:%[0-9]+]]:_(s16) = G_OR [[OR83]], [[TRUNC85]]
     ; CHECK: [[COPY408:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY408]], [[COPY407]](s32)
-    ; CHECK: [[TRUNC82:%[0-9]+]]:_(s16) = G_TRUNC [[SHL83]](s32)
-    ; CHECK: [[OR83:%[0-9]+]]:_(s16) = G_OR [[OR82]], [[TRUNC82]]
-    ; CHECK: [[COPY409:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
+    ; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY408]], [[C12]](s32)
+    ; CHECK: [[TRUNC86:%[0-9]+]]:_(s16) = G_TRUNC [[SHL85]](s32)
+    ; CHECK: [[OR85:%[0-9]+]]:_(s16) = G_OR [[OR84]], [[TRUNC86]]
+    ; CHECK: [[COPY409:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY409]], [[C13]](s32)
+    ; CHECK: [[TRUNC87:%[0-9]+]]:_(s16) = G_TRUNC [[SHL86]](s32)
+    ; CHECK: [[OR86:%[0-9]+]]:_(s16) = G_OR [[OR85]], [[TRUNC87]]
     ; CHECK: [[COPY410:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY410]], [[COPY409]](s32)
-    ; CHECK: [[TRUNC83:%[0-9]+]]:_(s16) = G_TRUNC [[SHL84]](s32)
-    ; CHECK: [[OR84:%[0-9]+]]:_(s16) = G_OR [[OR83]], [[TRUNC83]]
-    ; CHECK: [[COPY411:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY410]], [[C14]](s32)
+    ; CHECK: [[TRUNC88:%[0-9]+]]:_(s16) = G_TRUNC [[SHL87]](s32)
+    ; CHECK: [[OR87:%[0-9]+]]:_(s16) = G_OR [[OR86]], [[TRUNC88]]
+    ; CHECK: [[COPY411:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY411]], [[C15]](s32)
+    ; CHECK: [[TRUNC89:%[0-9]+]]:_(s16) = G_TRUNC [[SHL88]](s32)
+    ; CHECK: [[OR88:%[0-9]+]]:_(s16) = G_OR [[OR87]], [[TRUNC89]]
     ; CHECK: [[COPY412:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY412]], [[COPY411]](s32)
-    ; CHECK: [[TRUNC84:%[0-9]+]]:_(s16) = G_TRUNC [[SHL85]](s32)
-    ; CHECK: [[OR85:%[0-9]+]]:_(s16) = G_OR [[C4]], [[TRUNC84]]
-    ; CHECK: [[COPY413:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY412]], [[C16]](s32)
+    ; CHECK: [[TRUNC90:%[0-9]+]]:_(s16) = G_TRUNC [[SHL89]](s32)
+    ; CHECK: [[OR89:%[0-9]+]]:_(s16) = G_OR [[OR88]], [[TRUNC90]]
+    ; CHECK: [[COPY413:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY413]], [[C17]](s32)
+    ; CHECK: [[TRUNC91:%[0-9]+]]:_(s16) = G_TRUNC [[SHL90]](s32)
+    ; CHECK: [[OR90:%[0-9]+]]:_(s16) = G_OR [[OR89]], [[TRUNC91]]
     ; CHECK: [[COPY414:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY414]], [[COPY413]](s32)
-    ; CHECK: [[TRUNC85:%[0-9]+]]:_(s16) = G_TRUNC [[SHL86]](s32)
-    ; CHECK: [[OR86:%[0-9]+]]:_(s16) = G_OR [[OR85]], [[TRUNC85]]
-    ; CHECK: [[COPY415:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[COPY416:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY416]], [[COPY415]](s32)
-    ; CHECK: [[TRUNC86:%[0-9]+]]:_(s16) = G_TRUNC [[SHL87]](s32)
-    ; CHECK: [[OR87:%[0-9]+]]:_(s16) = G_OR [[OR86]], [[TRUNC86]]
-    ; CHECK: [[COPY417:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY417]], [[C8]](s32)
-    ; CHECK: [[TRUNC87:%[0-9]+]]:_(s16) = G_TRUNC [[SHL88]](s32)
-    ; CHECK: [[OR88:%[0-9]+]]:_(s16) = G_OR [[OR87]], [[TRUNC87]]
-    ; CHECK: [[COPY418:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY418]], [[C9]](s32)
-    ; CHECK: [[TRUNC88:%[0-9]+]]:_(s16) = G_TRUNC [[SHL89]](s32)
-    ; CHECK: [[OR89:%[0-9]+]]:_(s16) = G_OR [[OR88]], [[TRUNC88]]
-    ; CHECK: [[COPY419:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY419]], [[C10]](s32)
-    ; CHECK: [[TRUNC89:%[0-9]+]]:_(s16) = G_TRUNC [[SHL90]](s32)
-    ; CHECK: [[OR90:%[0-9]+]]:_(s16) = G_OR [[OR89]], [[TRUNC89]]
-    ; CHECK: [[COPY420:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY420]], [[C11]](s32)
-    ; CHECK: [[TRUNC90:%[0-9]+]]:_(s16) = G_TRUNC [[SHL91]](s32)
-    ; CHECK: [[OR91:%[0-9]+]]:_(s16) = G_OR [[OR90]], [[TRUNC90]]
-    ; CHECK: [[COPY421:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY421]], [[C12]](s32)
-    ; CHECK: [[TRUNC91:%[0-9]+]]:_(s16) = G_TRUNC [[SHL92]](s32)
-    ; CHECK: [[OR92:%[0-9]+]]:_(s16) = G_OR [[OR91]], [[TRUNC91]]
-    ; CHECK: [[COPY422:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY422]], [[C13]](s32)
-    ; CHECK: [[TRUNC92:%[0-9]+]]:_(s16) = G_TRUNC [[SHL93]](s32)
-    ; CHECK: [[OR93:%[0-9]+]]:_(s16) = G_OR [[OR92]], [[TRUNC92]]
-    ; CHECK: [[COPY423:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY423]], [[C14]](s32)
-    ; CHECK: [[TRUNC93:%[0-9]+]]:_(s16) = G_TRUNC [[SHL94]](s32)
-    ; CHECK: [[OR94:%[0-9]+]]:_(s16) = G_OR [[OR93]], [[TRUNC93]]
-    ; CHECK: [[COPY424:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY424]], [[C15]](s32)
-    ; CHECK: [[TRUNC94:%[0-9]+]]:_(s16) = G_TRUNC [[SHL95]](s32)
-    ; CHECK: [[OR95:%[0-9]+]]:_(s16) = G_OR [[OR94]], [[TRUNC94]]
-    ; CHECK: [[COPY425:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY425]], [[C16]](s32)
-    ; CHECK: [[TRUNC95:%[0-9]+]]:_(s16) = G_TRUNC [[SHL96]](s32)
-    ; CHECK: [[OR96:%[0-9]+]]:_(s16) = G_OR [[OR95]], [[TRUNC95]]
-    ; CHECK: [[COPY426:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY426]], [[C17]](s32)
-    ; CHECK: [[TRUNC96:%[0-9]+]]:_(s16) = G_TRUNC [[SHL97]](s32)
-    ; CHECK: [[OR97:%[0-9]+]]:_(s16) = G_OR [[OR96]], [[TRUNC96]]
-    ; CHECK: [[COPY427:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY427]], [[C18]](s32)
-    ; CHECK: [[TRUNC97:%[0-9]+]]:_(s16) = G_TRUNC [[SHL98]](s32)
-    ; CHECK: [[OR98:%[0-9]+]]:_(s16) = G_OR [[OR97]], [[TRUNC97]]
-    ; CHECK: [[COPY428:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY428]], [[C19]](s32)
-    ; CHECK: [[TRUNC98:%[0-9]+]]:_(s16) = G_TRUNC [[SHL99]](s32)
-    ; CHECK: [[OR99:%[0-9]+]]:_(s16) = G_OR [[OR98]], [[TRUNC98]]
-    ; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR84]](s16)
-    ; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR99]](s16)
-    ; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C5]](s32)
-    ; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL100]]
-    ; CHECK: [[MV4:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR38]](s32), [[OR69]](s32), [[OR100]](s32)
-    ; CHECK: [[TRUNC99:%[0-9]+]]:_(s68) = G_TRUNC [[MV4]](s96)
-    ; CHECK: S_NOP 0, implicit [[TRUNC99]](s68)
+    ; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY414]], [[C18]](s32)
+    ; CHECK: [[TRUNC92:%[0-9]+]]:_(s16) = G_TRUNC [[SHL91]](s32)
+    ; CHECK: [[OR91:%[0-9]+]]:_(s16) = G_OR [[OR90]], [[TRUNC92]]
+    ; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR76]](s16)
+    ; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR91]](s16)
+    ; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C5]](s32)
+    ; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL92]]
+    ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR30]](s32), [[OR61]](s32), [[OR92]](s32)
+    ; CHECK: [[TRUNC93:%[0-9]+]]:_(s68) = G_TRUNC [[MV]](s96)
+    ; CHECK: S_NOP 0, implicit [[TRUNC93]](s68)
     %0:_(s17) = G_CONSTANT i17 0
     %1:_(s17) = G_CONSTANT i17 1
     %2:_(s17) = G_CONSTANT i17 2
@@ -1766,3 +1602,58 @@ body: |
     %7:_(s64) = G_ANYEXT %6
     $vgpr0_vgpr1 = COPY %7
 ...
+
+---
+
+name: test_merge_s256_s128
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
+
+    ; CHECK-LABEL: name: test_merge_s256_s128
+    ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s128), [[COPY1]](s128)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
+    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(s128) = COPY  $vgpr4_vgpr5_vgpr6_vgpr7
+    %2:_(s256) = G_MERGE_VALUES %0, %1
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
+...
+
+---
+
+name: test_merge_s512_s256
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+
+    ; CHECK-LABEL: name: test_merge_s512_s256
+    ; CHECK: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s256) = COPY $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    ; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s256), [[COPY1]](s256)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512)
+    %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    %1:_(s256) = COPY $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    %2:_(s512) = G_MERGE_VALUES %0, %1
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %2
+...
+
+---
+
+name: test_merge_s1024_s512
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+
+    ; CHECK-LABEL: name: test_merge_s1024_s512
+    ; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s512) = COPY $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+    ; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[COPY]](s512), [[COPY1]](s512)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024)
+    %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    %1:_(s512) = COPY $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+    %2:_(s1024) = G_MERGE_VALUES %0, %1
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
index 41f20c0b83f2b..97232c2a52179 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_phi_s32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
index a4f4888250dd7..6f7c008068023 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
@@ -28,6 +28,35 @@ body: |
     $vgpr1 = COPY %7
 ...
 
+---
+name: test_sadde_v2s32
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+
+    ; CHECK-LABEL: name: test_sadde_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[BUILD_VECTOR]]
+    ; CHECK: [[SADDE:%[0-9]+]]:_(<2 x s32>), [[SADDE1:%[0-9]+]]:_(<2 x s1>) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s32>) = G_ZEXT [[SADDE1]](<2 x s1>)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[SADDE]](<2 x s32>)
+    ; CHECK: $vgpr2_vgpr3 = COPY [[ZEXT]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
+    %2:_(<2 x s32>) = COPY $vgpr4_vgpr5
+    %3:_(s32) = G_CONSTANT i32 0
+    %4:_(<2 x s32>) = G_BUILD_VECTOR %3, %3
+    %5:_(<2 x s1>) = G_ICMP intpred(eq), %2, %4
+    %6:_(<2 x s32>), %7:_(<2 x s1>) = G_SADDE %0, %1, %5
+    %8:_(<2 x s32>) = G_ZEXT %7
+    $vgpr0_vgpr1 = COPY %6
+    $vgpr2_vgpr3 = COPY %8
+...
+
 ---
 name: test_sadde_s16
 body: |
@@ -60,3 +89,30 @@ body: |
     $vgpr0 = COPY %9
     $vgpr1 = COPY %10
 ...
+
+---
+name: test_sadde_s64
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
+
+    ; CHECK-LABEL: name: test_sadde_s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr4
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+    ; CHECK: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SADDE1]](s1)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[SADDE]](s64)
+    ; CHECK: $vgpr2 = COPY [[ZEXT]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = COPY $vgpr2_vgpr3
+    %2:_(s32) = COPY $vgpr4
+    %3:_(s32) = G_CONSTANT i32 0
+    %4:_(s1) = G_ICMP intpred(eq), %2, %3
+    %5:_(s64), %6:_(s1) = G_SADDE %0, %1, %4
+    %7:_(s32) = G_ZEXT %6
+    $vgpr0_vgpr1 = COPY %5
+    $vgpr2 = COPY %7
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
index 3b4769c86a39d..f666c09c0c089 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
@@ -28,6 +28,34 @@ body: |
     $vgpr1 = COPY %7
 ...
 
+---
+name: test_ssube_v2s32
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+
+    ; CHECK-LABEL: name: test_ssube_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
+    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[BUILD_VECTOR]]
+    ; CHECK: [[SSUBE:%[0-9]+]]:_(<2 x s32>), [[SSUBE1:%[0-9]+]]:_(<2 x s1>) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s32>) = G_ZEXT [[SSUBE1]](<2 x s1>)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[SSUBE]](<2 x s32>)
+    ; CHECK: $vgpr2_vgpr3 = COPY [[ZEXT]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
+    %2:_(<2 x s32>) = COPY $vgpr4_vgpr5
+    %3:_(s32) = G_CONSTANT i32 0
+    %4:_(<2 x s32>) = G_BUILD_VECTOR %3, %3
+    %5:_(<2 x s1>) = G_ICMP intpred(eq), %2, %4
+    %6:_(<2 x s32>), %7:_(<2 x s1>) = G_SSUBE %0, %1, %5
+    %8:_(<2 x s32>) = G_ZEXT %7
+    $vgpr0_vgpr1 = COPY %6
+    $vgpr2_vgpr3 = COPY %8
+...
 ---
 name: test_ssube_s16
 body: |
@@ -60,3 +88,30 @@ body: |
     $vgpr0 = COPY %9
     $vgpr1 = COPY %10
 ...
+
+---
+name: test_ssube_s64
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4
+
+    ; CHECK-LABEL: name: test_ssube_s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr4
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+    ; CHECK: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SSUBE1]](s1)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[SSUBE]](s64)
+    ; CHECK: $vgpr2 = COPY [[ZEXT]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = COPY $vgpr2_vgpr3
+    %2:_(s32) = COPY $vgpr4
+    %3:_(s32) = G_CONSTANT i32 0
+    %4:_(s1) = G_ICMP intpred(eq), %2, %3
+    %5:_(s64), %6:_(s1) = G_SSUBE %0, %1, %4
+    %7:_(s32) = G_ZEXT %6
+    $vgpr0_vgpr1 = COPY %5
+    $vgpr2 = COPY %7
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
index 2655b126bfa4d..561fcdf504e9d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
@@ -233,31 +233,29 @@ body: |
     ; CHECK-LABEL: name: test_unmerge_s8_s48
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
     ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
-    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32)
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
     ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
     ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
     ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
     ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
     ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
     ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
     ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C1]](s32)
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
     ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
     ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
-    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
     ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
     ; CHECK: $vgpr1 = COPY [[COPY7]](s32)
@@ -290,16 +288,14 @@ body: |
     ; CHECK-LABEL: name: test_unmerge_s16_s48
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
     ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
-    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
     ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
     ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
@@ -762,3 +758,109 @@ body: |
     $vgpr6 = COPY %16
     $vgpr7 = COPY %17
 ...
+
+---
+
+name: test_unmerge_s128_v2s128
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_unmerge_s128_v2s128
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[UV]](s128)
+    ; CHECK: $vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV1]](s128)
+    %0:_(<2 x s128>) = COPY  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    %1:_(s128), %2:_(s128) = G_UNMERGE_VALUES %0
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+    $vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
+...
+
+---
+
+name: test_unmerge_s128_s256
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_unmerge_s128_s256
+    ; CHECK: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[UV]](s128)
+    ; CHECK: $vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV1]](s128)
+    %0:_(s256) = COPY  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    %1:_(s128), %2:_(s128) = G_UNMERGE_VALUES %0
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+    $vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
+...
+
+---
+
+name: test_unmerge_s256_s512
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+
+    ; CHECK-LABEL: name: test_unmerge_s256_s512
+    ; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    ; CHECK: [[UV:%[0-9]+]]:_(s256), [[UV1:%[0-9]+]]:_(s256) = G_UNMERGE_VALUES [[COPY]](s512)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV]](s256)
+    ; CHECK: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV1]](s256)
+    %0:_(s512) = COPY  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    %1:_(s256), %2:_(s256) = G_UNMERGE_VALUES %0
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
+    $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %2
+...
+
+---
+
+name: test_unmerge_s256_v2s256
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+
+    ; CHECK-LABEL: name: test_unmerge_s256_v2s256
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s256>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    ; CHECK: [[UV:%[0-9]+]]:_(s256), [[UV1:%[0-9]+]]:_(s256) = G_UNMERGE_VALUES [[COPY]](<2 x s256>)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[UV]](s256)
+    ; CHECK: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV1]](s256)
+    %0:_(<2 x s256>) = COPY  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+    %1:_(s256), %2:_(s256) = G_UNMERGE_VALUES %0
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
+    $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %2
+...
+
+---
+
+name: test_unmerge_s512_s1024
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+
+    ; CHECK-LABEL: name: test_unmerge_s512_s1024
+    ; CHECK: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+    ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](s1024)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512)
+    ; CHECK: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512)
+    %0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+    %1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1
+    $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2
+...
+
+---
+
+name: test_unmerge_s512_v2s512
+body: |
+  bb.0:
+    liveins:  $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+
+    ; CHECK-LABEL: name: test_unmerge_s512_v2s512
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+    ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](<2 x s512>)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512)
+    ; CHECK: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512)
+    %0:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+    %1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1
+    $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index 0398945717e8f..bead00534e34e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -692,25 +692,23 @@ body: |
     ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C4]], [[SHL1]]
     ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
     ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[MV1:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s128) = G_TRUNC [[MV1]](s448)
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[TRUNC1]](s128), 0
-    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s48) = G_EXTRACT [[TRUNC1]](s128), 64
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s128) = COPY [[INSERT1]](s128)
-    ; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY5]](s128), 0
-    ; CHECK: [[EXTRACT3:%[0-9]+]]:_(s48) = G_EXTRACT [[COPY5]](s128), 64
-    ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[EXTRACT]], [[EXTRACT2]]
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT1]](s48)
-    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT3]](s48)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s48) = G_EXTRACT [[DEF1]](s64), 0
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s128) = COPY [[INSERT1]](s128)
+    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY6]](s128), 0
+    ; CHECK: [[EXTRACT2:%[0-9]+]]:_(s48) = G_EXTRACT [[COPY6]](s128), 64
+    ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY5]], [[EXTRACT1]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s48)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT2]](s48)
     ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[AND3]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s48) = G_TRUNC [[AND3]](s64)
     ; CHECK: [[DEF2:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s128) = COPY [[DEF2]](s128)
-    ; CHECK: [[INSERT2:%[0-9]+]]:_(s128) = G_INSERT [[COPY6]], [[AND2]](s64), 0
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s128) = COPY [[INSERT2]](s128)
-    ; CHECK: [[INSERT3:%[0-9]+]]:_(s128) = G_INSERT [[COPY7]], [[TRUNC2]](s48), 64
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s112) = G_TRUNC [[INSERT3]](s128)
-    ; CHECK: S_ENDPGM 0, implicit [[TRUNC3]](s112)
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s128) = COPY [[DEF2]](s128)
+    ; CHECK: [[INSERT2:%[0-9]+]]:_(s128) = G_INSERT [[COPY7]], [[AND2]](s64), 0
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s128) = COPY [[INSERT2]](s128)
+    ; CHECK: [[INSERT3:%[0-9]+]]:_(s128) = G_INSERT [[COPY8]], [[TRUNC1]](s48), 64
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s112) = G_TRUNC [[INSERT3]](s128)
+    ; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s112)
     %0:_(s32) = COPY $vgpr0
     %1:_(s2) = G_TRUNC %0
     %2:_(s112) = G_ZEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
new file mode 100644
index 0000000000000..d798e2687fd42
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -0,0 +1,1032 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
+
+define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
+  ; GFX9-LABEL: name: gather4_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {
+  ; GFX9-LABEL: name: gather4_cube
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cube), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cube), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f16(i32 1, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {
+  ; GFX9-LABEL: name: gather4_2darray
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2darray), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2darray), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f16(i32 1, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
+  ; GFX9-LABEL: name: gather4_c_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.2d), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.2d), 1, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {
+  ; GFX9-LABEL: name: gather4_cl_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cl.2d), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cl.2d), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f16(i32 1, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {
+  ; GFX9-LABEL: name: gather4_c_cl_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.cl.2d), 1, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.cl.2d), 1, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t) {
+  ; GFX9-LABEL: name: gather4_b_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.2d), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_b_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.2d), 1, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.f16(i32 1, float %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t) {
+  ; GFX9-LABEL: name: gather4_c_b_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.2d), 1, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_b_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.2d), 1, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f16(i32 1, float %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {
+  ; GFX9-LABEL: name: gather4_b_cl_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.cl.2d), 1, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_b_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.cl.2d), 1, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f16(i32 1, float %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t, half %clamp) {
+  ; GFX9-LABEL: name: gather4_c_b_cl_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
+  ; GFX9:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.cl.2d), 1, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_b_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
+  ; GFX10NSA:   [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.cl.2d), 1, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f16(i32 1, float %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {
+  ; GFX9-LABEL: name: gather4_l_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.l.2d), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_l_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.l.2d), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {
+  ; GFX9-LABEL: name: gather4_c_l_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX9:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX9:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX9:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.l.2d), 1, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_l_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX10NSA:   [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+  ; GFX10NSA:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.l.2d), 1, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
+  ; GFX9-LABEL: name: gather4_lz_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.2d), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_lz_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.2d), 1, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
+  ; GFX9-LABEL: name: gather4_c_lz_2d
+  ; GFX9: bb.1.main_body:
+  ; GFX9:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX9:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX9:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX9:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX9:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX9:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX9:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX9:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX9:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX9:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX9:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX9:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX9:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX9:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX9:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX9:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX9:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX9:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX9:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX9:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX9:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX9:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX9:   [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
+  ; GFX9:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.2d), 1, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX9:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX9:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX9:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX9:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX9:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX9:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_lz_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.2d), 1, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f16(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 immarg, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f16(i32 immarg, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f16(i32 immarg, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f16(i32 immarg, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.f16(i32 immarg, float, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f16(i32 immarg, float, float, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f16(i32 immarg, float, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f16(i32 immarg, float, float, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 immarg, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 immarg, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f16(i32 immarg, float, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f16(i32 immarg, float, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f16(i32 immarg, float, half, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f16(i32 immarg, float, half, half, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+
+attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
new file mode 100644
index 0000000000000..9e9407f005c6d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
@@ -0,0 +1,1064 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s
+
+define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 1, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 1, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %face) {
+  ; GFX6-LABEL: name: gather4_cube
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cube), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_cube
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cube), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f32(i32 1, float %s, float %t, float %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %slice) {
+  ; GFX6-LABEL: name: gather4_2darray
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2darray), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2darray
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2darray), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f32(i32 1, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_c_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_cl_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cl.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cl.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f32(i32 1, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_c_cl_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.cl.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.cl.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_b_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_b_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.f32(i32 1, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_c_b_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_b_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_b_cl_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.cl.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_b_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.cl.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_c_b_cl_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.cl.2d), 1, [[BUILD_VECTOR2]](<5 x s32>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_b_cl_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.cl.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
+  ; GFX6-LABEL: name: gather4_l_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.l.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_l_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.l.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 1, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
+  ; GFX6-LABEL: name: gather4_c_l_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.l.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_l_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.l.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_lz_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.2d), 1, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_lz_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.2d), 1, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_c_lz_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_c_lz_2d
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 1, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_2d_dmask_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_2d_dmask_2
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 2, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2d_dmask_2
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 2, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 2, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_2d_dmask_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_2d_dmask_4
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 4, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2d_dmask_4
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 4, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 4, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_2d_dmask_8(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_2d_dmask_8
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 8, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10NSA-LABEL: name: gather4_2d_dmask_8
+  ; GFX10NSA: bb.1.main_body:
+  ; GFX10NSA:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1
+  ; GFX10NSA:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10NSA:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10NSA:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10NSA:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10NSA:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10NSA:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10NSA:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10NSA:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10NSA:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10NSA:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10NSA:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10NSA:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10NSA:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10NSA:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10NSA:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10NSA:   [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
+  ; GFX10NSA:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.2d), 8, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10NSA:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10NSA:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10NSA:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10NSA:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10NSA:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10NSA:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 8, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 immarg, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+
+attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
new file mode 100644
index 0000000000000..5338f1deb8e2a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
@@ -0,0 +1,782 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+
+define amdgpu_ps <4 x float> @gather4_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.o.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_c_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.o.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_c_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_cl_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cl.o.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_cl_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.cl.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_c_cl_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.cl.o.2d), 1, [[BUILD_VECTOR2]](<5 x s32>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_c_cl_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.cl.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_b_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_b_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.o.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_b_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_b_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_c_b_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.o.2d), 1, [[BUILD_VECTOR2]](<5 x s32>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_c_b_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_b_cl_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.cl.o.2d), 1, [[BUILD_VECTOR2]](<5 x s32>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_b_cl_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.b.cl.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp) {
+  ; GFX6-LABEL: name: gather4_c_b_cl_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX6:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.cl.o.2d), 1, [[BUILD_VECTOR2]](<6 x s32>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_c_b_cl_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10:   [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.b.cl.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
+  ; GFX6-LABEL: name: gather4_l_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.l.o.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_l_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.l.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
+  ; GFX6-LABEL: name: gather4_c_l_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.l.o.2d), 1, [[BUILD_VECTOR2]](<5 x s32>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_c_l_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.l.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_lz_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_lz_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.o.2d), 1, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_lz_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+define amdgpu_ps <4 x float> @gather4_c_lz_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t) {
+  ; GFX6-LABEL: name: gather4_c_lz_o_2d
+  ; GFX6: bb.1.main_body:
+  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX6:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX6:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX6:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX6:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX6:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX6:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX6:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX6:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX6:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX6:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX6:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX6:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX6:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX6:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX6:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX6:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX6:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX6:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX6:   [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+  ; GFX6:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.o.2d), 1, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX6:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX6:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX6:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX6:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX6:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+  ; GFX10-LABEL: name: gather4_c_lz_o_2d
+  ; GFX10: bb.1.main_body:
+  ; GFX10:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  ; GFX10:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
+  ; GFX10:   [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
+  ; GFX10:   [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
+  ; GFX10:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
+  ; GFX10:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
+  ; GFX10:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
+  ; GFX10:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
+  ; GFX10:   [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
+  ; GFX10:   [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10
+  ; GFX10:   [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11
+  ; GFX10:   [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12
+  ; GFX10:   [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13
+  ; GFX10:   [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
+  ; GFX10:   [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
+  ; GFX10:   [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
+  ; GFX10:   [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
+  ; GFX10:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+  ; GFX10:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+  ; GFX10:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.o.2d), 1, [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; GFX10:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
+  ; GFX10:   $vgpr0 = COPY [[UV]](s32)
+  ; GFX10:   $vgpr1 = COPY [[UV1]](s32)
+  ; GFX10:   $vgpr2 = COPY [[UV2]](s32)
+  ; GFX10:   $vgpr3 = COPY [[UV3]](s32)
+  ; GFX10:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
+main_body:
+  %v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x float> %v
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32 immarg, i32, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32(i32 immarg, i32, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.o.2d.v4f32.f32(i32 immarg, i32, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.2d.v4f32.f32(i32 immarg, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.f32(i32 immarg, i32, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.f32(i32 immarg, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.2d.v4f32.f32.f32(i32 immarg, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 immarg, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 immarg, i32, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 immarg, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32 immarg, i32, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32(i32 immarg, i32, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
+
+attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
new file mode 100644
index 0000000000000..f34c481824afd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -0,0 +1,2233 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
+
+define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) {
+; GFX7-LABEL: s_mul_i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_mul_i32 s0, s0, s1
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s2, 0xffff
+; GFX8-NEXT:    s_and_b32 s0, s0, s2
+; GFX8-NEXT:    s_and_b32 s1, s1, s2
+; GFX8-NEXT:    s_mul_i32 s0, s0, s1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, 0xffff
+; GFX9-NEXT:    s_and_b32 s0, s0, s2
+; GFX9-NEXT:    s_and_b32 s1, s1, s2
+; GFX9-NEXT:    s_mul_i32 s0, s0, s1
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i16 %num, %den
+  ret i16 %result
+}
+
+define i16 @v_mul_i16(i16 %num, i16 %den) {
+; GFX7-LABEL: v_mul_i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 s4, 0xffff
+; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i16 %num, %den
+  ret i16 %result
+}
+
+define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inreg zeroext %den) {
+; GFX7-LABEL: s_mul_i16_zeroext:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_mul_i32 s0, s0, s1
+; GFX7-NEXT:    s_and_b32 s0, s0, 0xffff
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i16_zeroext:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s2, 0xffff
+; GFX8-NEXT:    s_and_b32 s0, s0, s2
+; GFX8-NEXT:    s_and_b32 s1, s1, s2
+; GFX8-NEXT:    s_mul_i32 s0, s0, s1
+; GFX8-NEXT:    s_and_b32 s0, s0, s2
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i16_zeroext:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, 0xffff
+; GFX9-NEXT:    s_and_b32 s0, s0, s2
+; GFX9-NEXT:    s_and_b32 s1, s1, s2
+; GFX9-NEXT:    s_mul_i32 s0, s0, s1
+; GFX9-NEXT:    s_and_b32 s0, s0, s2
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i16 %num, %den
+  ret i16 %result
+}
+
+define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) {
+; GFX7-LABEL: v_mul_i16_zeroext:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 s4, 0xffff
+; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i16_zeroext:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i16_zeroext:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i16 %num, %den
+  ret i16 %result
+}
+
+define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inreg signext %den) {
+; GFX7-LABEL: s_mul_i16_signext:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_mul_i32 s0, s0, s1
+; GFX7-NEXT:    s_sext_i32_i16 s0, s0
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i16_signext:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s2, 0xffff
+; GFX8-NEXT:    s_and_b32 s0, s0, s2
+; GFX8-NEXT:    s_and_b32 s1, s1, s2
+; GFX8-NEXT:    s_mul_i32 s0, s0, s1
+; GFX8-NEXT:    s_sext_i32_i16 s0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i16_signext:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, 0xffff
+; GFX9-NEXT:    s_and_b32 s0, s0, s2
+; GFX9-NEXT:    s_and_b32 s1, s1, s2
+; GFX9-NEXT:    s_mul_i32 s0, s0, s1
+; GFX9-NEXT:    s_sext_i32_i16 s0, s0
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i16 %num, %den
+  ret i16 %result
+}
+
+define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) {
+; GFX7-LABEL: v_mul_i16_signext:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 s4, 0xffff
+; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX7-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i16_signext:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
+; GFX8-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i16_signext:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i16 %num, %den
+  ret i16 %result
+}
+
+define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) {
+; GCN-LABEL: s_mul_i32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_mul_i32 s0, s0, s1
+; GCN-NEXT:    ; return to shader part epilog
+  %result = mul i32 %num, %den
+  ret i32 %result
+}
+
+define i32 @v_mul_i32(i32 %num, i32 %den) {
+; GCN-LABEL: v_mul_i32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i32 %num, %den
+  ret i32 %result
+}
+
+define amdgpu_ps <2 x i32> @s_mul_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) {
+; GCN-LABEL: s_mul_v2i32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_mul_i32 s0, s0, s2
+; GCN-NEXT:    s_mul_i32 s1, s1, s3
+; GCN-NEXT:    ; return to shader part epilog
+  %result = mul <2 x i32> %num, %den
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @v_mul_v2i32(<2 x i32> %num, <2 x i32> %den) {
+; GCN-LABEL: v_mul_v2i32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v1, v1, v3
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul <2 x i32> %num, %den
+  ret <2 x i32> %result
+}
+
+define amdgpu_ps i64 @s_mul_i64(i64 inreg %num, i64 inreg %den) {
+; GFX7-LABEL: s_mul_i64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX7-NEXT:    s_mul_i32 s4, s0, s2
+; GFX7-NEXT:    s_mul_i32 s1, s1, s2
+; GFX7-NEXT:    s_mul_i32 s0, s0, s3
+; GFX7-NEXT:    s_add_i32 s1, s1, s0
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s1, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX7-NEXT:    s_mov_b32 s0, s4
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s2
+; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX8-NEXT:    s_mul_i32 s4, s0, s2
+; GFX8-NEXT:    s_mul_i32 s1, s1, s2
+; GFX8-NEXT:    s_mul_i32 s0, s0, s3
+; GFX8-NEXT:    s_add_i32 s1, s1, s0
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s1, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX8-NEXT:    s_mov_b32 s0, s4
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mul_i32 s1, s1, s2
+; GFX9-NEXT:    s_mul_i32 s3, s0, s3
+; GFX9-NEXT:    s_mul_i32 s4, s0, s2
+; GFX9-NEXT:    s_mul_hi_u32 s0, s0, s2
+; GFX9-NEXT:    s_add_i32 s1, s1, s3
+; GFX9-NEXT:    s_add_i32 s1, s1, s0
+; GFX9-NEXT:    s_mov_b32 s0, s4
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i64 %num, %den
+  ret i64 %result
+}
+
+define i64 @v_mul_i64(i64 %num, i64 %den) {
+; GFX7-LABEL: v_mul_i64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mul_lo_u32 v4, v0, v3
+; GFX7-NEXT:    v_mul_lo_u32 v1, v1, v2
+; GFX7-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX7-NEXT:    v_mul_hi_u32 v0, v0, v2
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v0, v3
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u32 v4, v0, v3
+; GFX8-NEXT:    v_mul_lo_u32 v1, v1, v2
+; GFX8-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX8-NEXT:    v_mul_hi_u32 v0, v0, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v4
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v0
+; GFX8-NEXT:    v_mov_b32_e32 v0, v3
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v3
+; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v2
+; GFX9-NEXT:    v_add3_u32 v1, v1, v3, v4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i64 %num, %den
+  ret i64 %result
+}
+
+define amdgpu_ps <3 x i32> @s_mul_i96(i96 inreg %num, i96 inreg %den) {
+; GFX7-LABEL: s_mul_i96:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX7-NEXT:    v_mov_b32_e32 v2, s1
+; GFX7-NEXT:    s_mul_i32 s7, s1, s3
+; GFX7-NEXT:    s_mul_i32 s8, s0, s4
+; GFX7-NEXT:    s_add_u32 s7, s7, s8
+; GFX7-NEXT:    v_mov_b32_e32 v3, s4
+; GFX7-NEXT:    v_mul_hi_u32 v2, v2, s3
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s7, v0
+; GFX7-NEXT:    s_mul_i32 s7, s1, s4
+; GFX7-NEXT:    s_mul_i32 s2, s2, s3
+; GFX7-NEXT:    v_mul_hi_u32 v3, s0, v3
+; GFX7-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX7-NEXT:    s_mul_i32 s6, s0, s3
+; GFX7-NEXT:    s_mul_i32 s5, s0, s5
+; GFX7-NEXT:    s_add_i32 s0, s2, s7
+; GFX7-NEXT:    s_add_i32 s0, s0, s5
+; GFX7-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, s0, v2
+; GFX7-NEXT:    s_and_b32 s8, s8, 1
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX7-NEXT:    s_mov_b32 s0, s6
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i96:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s3
+; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX8-NEXT:    v_mov_b32_e32 v2, s1
+; GFX8-NEXT:    s_mul_i32 s7, s1, s3
+; GFX8-NEXT:    s_mul_i32 s8, s0, s4
+; GFX8-NEXT:    s_add_u32 s7, s7, s8
+; GFX8-NEXT:    v_mov_b32_e32 v3, s4
+; GFX8-NEXT:    v_mul_hi_u32 v2, v2, s3
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s7, v0
+; GFX8-NEXT:    s_mul_i32 s7, s1, s4
+; GFX8-NEXT:    s_mul_i32 s2, s2, s3
+; GFX8-NEXT:    v_mul_hi_u32 v3, s0, v3
+; GFX8-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX8-NEXT:    s_mul_i32 s6, s0, s3
+; GFX8-NEXT:    s_mul_i32 s5, s0, s5
+; GFX8-NEXT:    s_add_i32 s0, s2, s7
+; GFX8-NEXT:    s_add_i32 s0, s0, s5
+; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
+; GFX8-NEXT:    s_and_b32 s8, s8, 1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, s8, v1
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v3
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX8-NEXT:    s_mov_b32 s0, s6
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i96:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mul_i32 s7, s1, s3
+; GFX9-NEXT:    s_mul_i32 s8, s0, s4
+; GFX9-NEXT:    s_add_u32 s7, s7, s8
+; GFX9-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX9-NEXT:    s_mul_hi_u32 s9, s0, s3
+; GFX9-NEXT:    s_and_b32 s8, s8, 1
+; GFX9-NEXT:    s_add_u32 s7, s7, s9
+; GFX9-NEXT:    s_cselect_b32 s9, 1, 0
+; GFX9-NEXT:    s_and_b32 s9, s9, 1
+; GFX9-NEXT:    s_add_i32 s8, s8, s9
+; GFX9-NEXT:    s_mul_i32 s9, s1, s4
+; GFX9-NEXT:    s_mul_i32 s2, s2, s3
+; GFX9-NEXT:    s_mul_i32 s5, s0, s5
+; GFX9-NEXT:    s_add_i32 s2, s2, s9
+; GFX9-NEXT:    s_mul_hi_u32 s1, s1, s3
+; GFX9-NEXT:    s_add_i32 s2, s2, s5
+; GFX9-NEXT:    s_mul_i32 s6, s0, s3
+; GFX9-NEXT:    s_mul_hi_u32 s0, s0, s4
+; GFX9-NEXT:    s_add_i32 s1, s2, s1
+; GFX9-NEXT:    s_add_i32 s0, s1, s0
+; GFX9-NEXT:    s_add_i32 s2, s0, s8
+; GFX9-NEXT:    s_mov_b32 s0, s6
+; GFX9-NEXT:    s_mov_b32 s1, s7
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i96 %num, %den
+  %cast = bitcast i96 %result to <3 x i32>
+  ret <3 x i32> %cast
+}
+
+define i96 @v_mul_i96(i96 %num, i96 %den) {
+; GFX7-LABEL: v_mul_i96:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GFX7-NEXT:    v_mul_lo_u32 v8, v0, v4
+; GFX7-NEXT:    v_mul_hi_u32 v9, v0, v3
+; GFX7-NEXT:    v_mul_lo_u32 v2, v2, v3
+; GFX7-NEXT:    v_mul_lo_u32 v5, v0, v5
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX7-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GFX7-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GFX7-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GFX7-NEXT:    v_mul_hi_u32 v1, v1, v3
+; GFX7-NEXT:    v_mul_lo_u32 v6, v0, v3
+; GFX7-NEXT:    v_mul_hi_u32 v0, v0, v4
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v2, v9
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v0, v8
+; GFX7-NEXT:    v_mov_b32_e32 v0, v6
+; GFX7-NEXT:    v_mov_b32_e32 v1, v7
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i96:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GFX8-NEXT:    v_mul_lo_u32 v8, v0, v4
+; GFX8-NEXT:    v_mul_hi_u32 v9, v0, v3
+; GFX8-NEXT:    v_mul_lo_u32 v2, v2, v3
+; GFX8-NEXT:    v_mul_lo_u32 v5, v0, v5
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v9
+; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v8, v9
+; GFX8-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GFX8-NEXT:    v_mul_hi_u32 v1, v1, v3
+; GFX8-NEXT:    v_mul_lo_u32 v6, v0, v3
+; GFX8-NEXT:    v_mul_hi_u32 v0, v0, v4
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v9
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v5
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v0, v8
+; GFX8-NEXT:    v_mov_b32_e32 v0, v6
+; GFX8-NEXT:    v_mov_b32_e32 v1, v7
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i96:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GFX9-NEXT:    v_mul_lo_u32 v8, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v10, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v3
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v1, v1, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
+; GFX9-NEXT:    v_mul_hi_u32 v0, v0, v4
+; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v9
+; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v10
+; GFX9-NEXT:    v_add_u32_e32 v3, v8, v9
+; GFX9-NEXT:    v_add3_u32 v1, v2, v5, v1
+; GFX9-NEXT:    v_add3_u32 v2, v1, v0, v3
+; GFX9-NEXT:    v_mov_b32_e32 v0, v6
+; GFX9-NEXT:    v_mov_b32_e32 v1, v7
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i96 %num, %den
+  ret i96 %result
+}
+
+define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) {
+; GFX7-LABEL: s_mul_i128:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_mov_b32_e32 v0, s4
+; GFX7-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX7-NEXT:    s_mul_i32 s9, s1, s4
+; GFX7-NEXT:    s_mul_i32 s10, s0, s5
+; GFX7-NEXT:    s_add_u32 s9, s9, s10
+; GFX7-NEXT:    s_cselect_b32 s10, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s9, v0
+; GFX7-NEXT:    s_and_b32 s10, s10, 1
+; GFX7-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
+; GFX7-NEXT:    s_mul_i32 s9, s2, s4
+; GFX7-NEXT:    s_mul_i32 s10, s1, s5
+; GFX7-NEXT:    v_mov_b32_e32 v2, s1
+; GFX7-NEXT:    s_add_u32 s9, s9, s10
+; GFX7-NEXT:    s_cselect_b32 s10, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v2, v2, s4
+; GFX7-NEXT:    s_mul_i32 s11, s0, s6
+; GFX7-NEXT:    s_and_b32 s10, s10, 1
+; GFX7-NEXT:    s_add_u32 s9, s9, s11
+; GFX7-NEXT:    v_mov_b32_e32 v3, s5
+; GFX7-NEXT:    s_cselect_b32 s11, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v4, s0, v3
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, s9, v2
+; GFX7-NEXT:    s_and_b32 s11, s11, 1
+; GFX7-NEXT:    s_add_i32 s10, s10, s11
+; GFX7-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, s10, v5
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX7-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX7-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX7-NEXT:    v_mov_b32_e32 v4, s2
+; GFX7-NEXT:    v_mov_b32_e32 v5, s6
+; GFX7-NEXT:    s_mul_i32 s5, s2, s5
+; GFX7-NEXT:    s_mul_i32 s3, s3, s4
+; GFX7-NEXT:    v_mul_hi_u32 v4, v4, s4
+; GFX7-NEXT:    s_mul_i32 s8, s0, s4
+; GFX7-NEXT:    s_mul_i32 s9, s1, s6
+; GFX7-NEXT:    v_mul_hi_u32 v3, s1, v3
+; GFX7-NEXT:    s_mul_i32 s7, s0, s7
+; GFX7-NEXT:    v_mul_hi_u32 v5, s0, v5
+; GFX7-NEXT:    s_add_i32 s0, s3, s5
+; GFX7-NEXT:    s_add_i32 s0, s0, s9
+; GFX7-NEXT:    s_add_i32 s0, s0, s7
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, s0, v4
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX7-NEXT:    s_mov_b32 s0, s8
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i128:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s4
+; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX8-NEXT:    s_mul_i32 s9, s1, s4
+; GFX8-NEXT:    s_mul_i32 s10, s0, s5
+; GFX8-NEXT:    s_add_u32 s9, s9, s10
+; GFX8-NEXT:    s_cselect_b32 s10, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s9, v0
+; GFX8-NEXT:    s_and_b32 s10, s10, 1
+; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, s10, v1
+; GFX8-NEXT:    s_mul_i32 s9, s2, s4
+; GFX8-NEXT:    s_mul_i32 s10, s1, s5
+; GFX8-NEXT:    v_mov_b32_e32 v2, s1
+; GFX8-NEXT:    s_add_u32 s9, s9, s10
+; GFX8-NEXT:    s_cselect_b32 s10, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v2, v2, s4
+; GFX8-NEXT:    s_mul_i32 s11, s0, s6
+; GFX8-NEXT:    s_and_b32 s10, s10, 1
+; GFX8-NEXT:    s_add_u32 s9, s9, s11
+; GFX8-NEXT:    v_mov_b32_e32 v3, s5
+; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s0, v3
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s9, v2
+; GFX8-NEXT:    s_and_b32 s11, s11, 1
+; GFX8-NEXT:    s_add_i32 s10, s10, s11
+; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, s10, v5
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
+; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v4, v2
+; GFX8-NEXT:    v_mov_b32_e32 v4, s2
+; GFX8-NEXT:    v_mov_b32_e32 v5, s6
+; GFX8-NEXT:    s_mul_i32 s5, s2, s5
+; GFX8-NEXT:    s_mul_i32 s3, s3, s4
+; GFX8-NEXT:    v_mul_hi_u32 v4, v4, s4
+; GFX8-NEXT:    s_mul_i32 s8, s0, s4
+; GFX8-NEXT:    s_mul_i32 s9, s1, s6
+; GFX8-NEXT:    v_mul_hi_u32 v3, s1, v3
+; GFX8-NEXT:    s_mul_i32 s7, s0, s7
+; GFX8-NEXT:    v_mul_hi_u32 v5, s0, v5
+; GFX8-NEXT:    s_add_i32 s0, s3, s5
+; GFX8-NEXT:    s_add_i32 s0, s0, s9
+; GFX8-NEXT:    s_add_i32 s0, s0, s7
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, s0, v4
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v5
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX8-NEXT:    s_mov_b32 s0, s8
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i128:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mul_i32 s9, s1, s4
+; GFX9-NEXT:    s_mul_i32 s10, s0, s5
+; GFX9-NEXT:    s_add_u32 s9, s9, s10
+; GFX9-NEXT:    s_cselect_b32 s10, 1, 0
+; GFX9-NEXT:    s_mul_hi_u32 s11, s0, s4
+; GFX9-NEXT:    s_and_b32 s10, s10, 1
+; GFX9-NEXT:    s_add_u32 s9, s9, s11
+; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
+; GFX9-NEXT:    s_and_b32 s11, s11, 1
+; GFX9-NEXT:    s_add_i32 s10, s10, s11
+; GFX9-NEXT:    s_mul_i32 s11, s2, s4
+; GFX9-NEXT:    s_mul_i32 s12, s1, s5
+; GFX9-NEXT:    s_add_u32 s11, s11, s12
+; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
+; GFX9-NEXT:    s_mul_i32 s13, s0, s6
+; GFX9-NEXT:    s_and_b32 s12, s12, 1
+; GFX9-NEXT:    s_add_u32 s11, s11, s13
+; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
+; GFX9-NEXT:    s_and_b32 s13, s13, 1
+; GFX9-NEXT:    s_mul_hi_u32 s14, s1, s4
+; GFX9-NEXT:    s_add_i32 s12, s12, s13
+; GFX9-NEXT:    s_add_u32 s11, s11, s14
+; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
+; GFX9-NEXT:    s_and_b32 s13, s13, 1
+; GFX9-NEXT:    s_mul_hi_u32 s15, s0, s5
+; GFX9-NEXT:    s_add_i32 s12, s12, s13
+; GFX9-NEXT:    s_add_u32 s11, s11, s15
+; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
+; GFX9-NEXT:    s_and_b32 s13, s13, 1
+; GFX9-NEXT:    s_add_i32 s12, s12, s13
+; GFX9-NEXT:    s_add_u32 s10, s11, s10
+; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
+; GFX9-NEXT:    s_and_b32 s11, s11, 1
+; GFX9-NEXT:    s_add_i32 s12, s12, s11
+; GFX9-NEXT:    s_mul_i32 s11, s2, s5
+; GFX9-NEXT:    s_mul_i32 s3, s3, s4
+; GFX9-NEXT:    s_mul_i32 s13, s1, s6
+; GFX9-NEXT:    s_add_i32 s3, s3, s11
+; GFX9-NEXT:    s_mul_i32 s7, s0, s7
+; GFX9-NEXT:    s_add_i32 s3, s3, s13
+; GFX9-NEXT:    s_mul_hi_u32 s2, s2, s4
+; GFX9-NEXT:    s_add_i32 s3, s3, s7
+; GFX9-NEXT:    s_mul_hi_u32 s1, s1, s5
+; GFX9-NEXT:    s_add_i32 s2, s3, s2
+; GFX9-NEXT:    s_mul_i32 s8, s0, s4
+; GFX9-NEXT:    s_add_i32 s1, s2, s1
+; GFX9-NEXT:    s_mul_hi_u32 s0, s0, s6
+; GFX9-NEXT:    s_add_i32 s0, s1, s0
+; GFX9-NEXT:    s_add_i32 s3, s0, s12
+; GFX9-NEXT:    s_mov_b32 s0, s8
+; GFX9-NEXT:    s_mov_b32 s1, s9
+; GFX9-NEXT:    s_mov_b32 s2, s10
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i128 %num, %den
+  %cast = bitcast i128 %result to <4 x i32>
+  ret <4 x i32> %cast
+}
+
+define i128 @v_mul_i128(i128 %num, i128 %den) {
+; GFX7-LABEL: v_mul_i128:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GFX7-NEXT:    v_mul_lo_u32 v10, v0, v5
+; GFX7-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX7-NEXT:    v_mul_lo_u32 v12, v1, v5
+; GFX7-NEXT:    v_mul_lo_u32 v13, v0, v6
+; GFX7-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GFX7-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GFX7-NEXT:    v_mul_lo_u32 v11, v2, v4
+; GFX7-NEXT:    v_mul_hi_u32 v14, v1, v4
+; GFX7-NEXT:    v_mul_hi_u32 v15, v0, v5
+; GFX7-NEXT:    v_mul_lo_u32 v3, v3, v4
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GFX7-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GFX7-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; GFX7-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
+; GFX7-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GFX7-NEXT:    v_mul_lo_u32 v12, v2, v5
+; GFX7-NEXT:    v_mul_lo_u32 v13, v1, v6
+; GFX7-NEXT:    v_mul_lo_u32 v7, v0, v7
+; GFX7-NEXT:    v_mul_hi_u32 v2, v2, v4
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v3, v12
+; GFX7-NEXT:    v_mul_hi_u32 v1, v1, v5
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v3, v13
+; GFX7-NEXT:    v_mul_lo_u32 v8, v0, v4
+; GFX7-NEXT:    v_mul_hi_u32 v0, v0, v6
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v0, v11
+; GFX7-NEXT:    v_mov_b32_e32 v0, v8
+; GFX7-NEXT:    v_mov_b32_e32 v1, v9
+; GFX7-NEXT:    v_mov_b32_e32 v2, v10
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i128:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GFX8-NEXT:    v_mul_lo_u32 v10, v0, v5
+; GFX8-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX8-NEXT:    v_mul_lo_u32 v12, v1, v5
+; GFX8-NEXT:    v_mul_lo_u32 v13, v0, v6
+; GFX8-NEXT:    v_add_u32_e32 v9, vcc, v9, v10
+; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v9, vcc, v9, v11
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v10, v11
+; GFX8-NEXT:    v_mul_lo_u32 v11, v2, v4
+; GFX8-NEXT:    v_mul_hi_u32 v14, v1, v4
+; GFX8-NEXT:    v_mul_hi_u32 v15, v0, v5
+; GFX8-NEXT:    v_mul_lo_u32 v3, v3, v4
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v11, v12
+; GFX8-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v11, v13
+; GFX8-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v12, vcc, v12, v13
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v11, v14
+; GFX8-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v12, vcc, v12, v13
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v11, v15
+; GFX8-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v12, vcc, v12, v13
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v11, v10
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v12, v11
+; GFX8-NEXT:    v_mul_lo_u32 v12, v2, v5
+; GFX8-NEXT:    v_mul_lo_u32 v13, v1, v6
+; GFX8-NEXT:    v_mul_lo_u32 v7, v0, v7
+; GFX8-NEXT:    v_mul_hi_u32 v2, v2, v4
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v12
+; GFX8-NEXT:    v_mul_hi_u32 v1, v1, v5
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v13
+; GFX8-NEXT:    v_mul_lo_u32 v8, v0, v4
+; GFX8-NEXT:    v_mul_hi_u32 v0, v0, v6
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v0, v11
+; GFX8-NEXT:    v_mov_b32_e32 v0, v8
+; GFX8-NEXT:    v_mov_b32_e32 v1, v9
+; GFX8-NEXT:    v_mov_b32_e32 v2, v10
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i128:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v13, v0, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX9-NEXT:    v_add_u32_e32 v10, v10, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v14, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v15, v0, v5
+; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v12
+; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v13
+; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v14
+; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v15
+; GFX9-NEXT:    v_add3_u32 v12, v12, v13, v14
+; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v11, v12, v13, v11
+; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v5
+; GFX9-NEXT:    v_mul_lo_u32 v13, v1, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v1, v1, v5
+; GFX9-NEXT:    v_mul_lo_u32 v8, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v0, v0, v6
+; GFX9-NEXT:    v_add_u32_e32 v3, v3, v12
+; GFX9-NEXT:    v_add3_u32 v3, v3, v13, v7
+; GFX9-NEXT:    v_add3_u32 v1, v3, v2, v1
+; GFX9-NEXT:    v_add3_u32 v3, v1, v0, v11
+; GFX9-NEXT:    v_mov_b32_e32 v0, v8
+; GFX9-NEXT:    v_mov_b32_e32 v1, v9
+; GFX9-NEXT:    v_mov_b32_e32 v2, v10
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i128 %num, %den
+  ret i128 %result
+}
+
+define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) {
+; GFX7-LABEL: s_mul_i256:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_mov_b32_e32 v0, s8
+; GFX7-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX7-NEXT:    s_mul_i32 s17, s1, s8
+; GFX7-NEXT:    s_mul_i32 s18, s0, s9
+; GFX7-NEXT:    s_add_u32 s17, s17, s18
+; GFX7-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s17, v0
+; GFX7-NEXT:    s_and_b32 s18, s18, 1
+; GFX7-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, s18, v1
+; GFX7-NEXT:    s_mul_i32 s17, s2, s8
+; GFX7-NEXT:    s_mul_i32 s18, s1, s9
+; GFX7-NEXT:    v_mov_b32_e32 v2, s1
+; GFX7-NEXT:    s_add_u32 s17, s17, s18
+; GFX7-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v2, v2, s8
+; GFX7-NEXT:    s_mul_i32 s19, s0, s10
+; GFX7-NEXT:    s_and_b32 s18, s18, 1
+; GFX7-NEXT:    s_add_u32 s17, s17, s19
+; GFX7-NEXT:    v_mov_b32_e32 v3, s9
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v4, s0, v3
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, s17, v2
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, s18, v5
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX7-NEXT:    s_mul_i32 s17, s3, s8
+; GFX7-NEXT:    s_mul_i32 s18, s2, s9
+; GFX7-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX7-NEXT:    s_add_u32 s17, s17, s18
+; GFX7-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX7-NEXT:    s_mul_i32 s19, s1, s10
+; GFX7-NEXT:    s_and_b32 s18, s18, 1
+; GFX7-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX7-NEXT:    s_add_u32 s17, s17, s19
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX7-NEXT:    v_mov_b32_e32 v4, s2
+; GFX7-NEXT:    v_mul_hi_u32 v5, v4, s8
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    s_mul_i32 s20, s0, s11
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    s_add_u32 s17, s17, s20
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v3, s1, v3
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, s17, v5
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_mov_b32_e32 v6, s10
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, s18, v8
+; GFX7-NEXT:    v_mul_hi_u32 v7, s0, v6
+; GFX7-NEXT:    s_mul_i32 s17, s4, s8
+; GFX7-NEXT:    s_mul_i32 s18, s3, s9
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX7-NEXT:    s_add_u32 s17, s17, s18
+; GFX7-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX7-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
+; GFX7-NEXT:    s_mul_i32 s19, s2, s10
+; GFX7-NEXT:    s_and_b32 s18, s18, 1
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX7-NEXT:    s_add_u32 s17, s17, s19
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX7-NEXT:    s_mul_i32 s20, s1, s11
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX7-NEXT:    s_add_u32 s17, s17, s20
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX7-NEXT:    v_mov_b32_e32 v5, s3
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_mul_hi_u32 v7, v5, s8
+; GFX7-NEXT:    s_mul_i32 s21, s0, s12
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    s_add_u32 s17, s17, s21
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, s17, v7
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_mul_hi_u32 v4, v4, s9
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, s18, v11
+; GFX7-NEXT:    s_mul_i32 s17, s5, s8
+; GFX7-NEXT:    s_mul_i32 s18, s4, s9
+; GFX7-NEXT:    s_add_u32 s17, s17, s18
+; GFX7-NEXT:    v_mul_hi_u32 v8, s1, v6
+; GFX7-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GFX7-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX7-NEXT:    v_mov_b32_e32 v9, s11
+; GFX7-NEXT:    s_mul_i32 s19, s3, s10
+; GFX7-NEXT:    s_and_b32 s18, s18, 1
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
+; GFX7-NEXT:    s_add_u32 s17, s17, s19
+; GFX7-NEXT:    v_mul_hi_u32 v10, s0, v9
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GFX7-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX7-NEXT:    s_mul_i32 s20, s2, s11
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GFX7-NEXT:    s_add_u32 s17, s17, s20
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX7-NEXT:    s_mul_i32 s21, s1, s12
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX7-NEXT:    s_add_u32 s17, s17, s21
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GFX7-NEXT:    v_mov_b32_e32 v7, s4
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_mul_hi_u32 v8, v7, s8
+; GFX7-NEXT:    s_mul_i32 s22, s0, s13
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    s_add_u32 s17, s17, s22
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, s17, v8
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_mul_hi_u32 v10, v5, s9
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v14, vcc, s18, v14
+; GFX7-NEXT:    s_mul_i32 s17, s6, s8
+; GFX7-NEXT:    s_mul_i32 s18, s5, s9
+; GFX7-NEXT:    s_add_u32 s17, s17, s18
+; GFX7-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v6, s2, v6
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GFX7-NEXT:    s_mul_i32 s19, s4, s10
+; GFX7-NEXT:    s_and_b32 s18, s18, 1
+; GFX7-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX7-NEXT:    s_add_u32 s17, s17, s19
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v14, v10
+; GFX7-NEXT:    v_mul_hi_u32 v11, s1, v9
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX7-NEXT:    v_mov_b32_e32 v12, s12
+; GFX7-NEXT:    s_mul_i32 s20, s3, s11
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GFX7-NEXT:    s_add_u32 s17, s17, s20
+; GFX7-NEXT:    v_mul_hi_u32 v13, s0, v12
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; GFX7-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GFX7-NEXT:    s_mul_i32 s21, s2, s12
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
+; GFX7-NEXT:    s_add_u32 s17, s17, s21
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX7-NEXT:    s_mul_i32 s22, s1, s13
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX7-NEXT:    s_add_u32 s17, s17, s22
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GFX7-NEXT:    v_mov_b32_e32 v8, s5
+; GFX7-NEXT:    v_mul_hi_u32 v10, v8, s8
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    s_mul_i32 s23, s0, s14
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    s_add_u32 s17, s17, s23
+; GFX7-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX7-NEXT:    v_mul_hi_u32 v11, v7, s9
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, s17, v10
+; GFX7-NEXT:    s_and_b32 s19, s19, 1
+; GFX7-NEXT:    s_add_i32 s18, s18, s19
+; GFX7-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v17, vcc, s18, v17
+; GFX7-NEXT:    v_mul_hi_u32 v5, v5, s10
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_mul_hi_u32 v13, s2, v9
+; GFX7-NEXT:    v_add_i32_e32 v11, vcc, v17, v11
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GFX7-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GFX7-NEXT:    v_mul_hi_u32 v14, s1, v12
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v5, v13
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_mov_b32_e32 v15, s13
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GFX7-NEXT:    v_mul_hi_u32 v16, s0, v15
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v5, v16
+; GFX7-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GFX7-NEXT:    v_mov_b32_e32 v13, s14
+; GFX7-NEXT:    s_mul_i32 s7, s7, s8
+; GFX7-NEXT:    s_mul_i32 s17, s6, s9
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GFX7-NEXT:    s_mul_i32 s16, s0, s8
+; GFX7-NEXT:    s_mul_i32 s5, s5, s10
+; GFX7-NEXT:    s_mul_i32 s15, s0, s15
+; GFX7-NEXT:    v_mul_hi_u32 v13, s0, v13
+; GFX7-NEXT:    s_add_i32 s0, s7, s17
+; GFX7-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX7-NEXT:    s_mul_i32 s4, s4, s11
+; GFX7-NEXT:    s_add_i32 s0, s0, s5
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; GFX7-NEXT:    v_mov_b32_e32 v10, s6
+; GFX7-NEXT:    s_mul_i32 s11, s3, s12
+; GFX7-NEXT:    s_add_i32 s0, s0, s4
+; GFX7-NEXT:    s_mul_i32 s12, s2, s13
+; GFX7-NEXT:    s_add_i32 s0, s0, s11
+; GFX7-NEXT:    v_mul_hi_u32 v10, v10, s8
+; GFX7-NEXT:    s_mul_i32 s13, s1, s14
+; GFX7-NEXT:    s_add_i32 s0, s0, s12
+; GFX7-NEXT:    v_mul_hi_u32 v8, v8, s9
+; GFX7-NEXT:    s_add_i32 s0, s0, s13
+; GFX7-NEXT:    v_mul_hi_u32 v7, v7, s10
+; GFX7-NEXT:    v_mul_hi_u32 v9, s3, v9
+; GFX7-NEXT:    s_add_i32 s0, s0, s15
+; GFX7-NEXT:    v_mul_hi_u32 v11, s2, v12
+; GFX7-NEXT:    v_add_i32_e32 v10, vcc, s0, v10
+; GFX7-NEXT:    v_mul_hi_u32 v12, s1, v15
+; GFX7-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX7-NEXT:    v_readfirstlane_b32 s4, v3
+; GFX7-NEXT:    v_readfirstlane_b32 s5, v4
+; GFX7-NEXT:    v_readfirstlane_b32 s6, v5
+; GFX7-NEXT:    v_readfirstlane_b32 s7, v6
+; GFX7-NEXT:    s_mov_b32 s0, s16
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_mul_i256:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s8
+; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX8-NEXT:    s_mul_i32 s17, s1, s8
+; GFX8-NEXT:    s_mul_i32 s18, s0, s9
+; GFX8-NEXT:    s_add_u32 s17, s17, s18
+; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s17, v0
+; GFX8-NEXT:    s_and_b32 s18, s18, 1
+; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, s18, v1
+; GFX8-NEXT:    s_mul_i32 s17, s2, s8
+; GFX8-NEXT:    s_mul_i32 s18, s1, s9
+; GFX8-NEXT:    v_mov_b32_e32 v2, s1
+; GFX8-NEXT:    s_add_u32 s17, s17, s18
+; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v2, v2, s8
+; GFX8-NEXT:    s_mul_i32 s19, s0, s10
+; GFX8-NEXT:    s_and_b32 s18, s18, 1
+; GFX8-NEXT:    s_add_u32 s17, s17, s19
+; GFX8-NEXT:    v_mov_b32_e32 v3, s9
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s0, v3
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s17, v2
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, s18, v5
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v4
+; GFX8-NEXT:    s_mul_i32 s17, s3, s8
+; GFX8-NEXT:    s_mul_i32 s18, s2, s9
+; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT:    s_add_u32 s17, s17, s18
+; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT:    s_mul_i32 s19, s1, s10
+; GFX8-NEXT:    s_and_b32 s18, s18, 1
+; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT:    s_add_u32 s17, s17, s19
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v4, v2
+; GFX8-NEXT:    v_mov_b32_e32 v4, s2
+; GFX8-NEXT:    v_mul_hi_u32 v5, v4, s8
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    s_mul_i32 s20, s0, s11
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    s_add_u32 s17, s17, s20
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v3, s1, v3
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, s17, v5
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_mov_b32_e32 v6, s10
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, s18, v8
+; GFX8-NEXT:    v_mul_hi_u32 v7, s0, v6
+; GFX8-NEXT:    s_mul_i32 s17, s4, s8
+; GFX8-NEXT:    s_mul_i32 s18, s3, s9
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v5, v3
+; GFX8-NEXT:    s_add_u32 s17, s17, s18
+; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v8, v5
+; GFX8-NEXT:    s_mul_i32 s19, s2, s10
+; GFX8-NEXT:    s_and_b32 s18, s18, 1
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v7
+; GFX8-NEXT:    s_add_u32 s17, s17, s19
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v5, v7
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
+; GFX8-NEXT:    s_mul_i32 s20, s1, s11
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX8-NEXT:    s_add_u32 s17, s17, s20
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v5, v3
+; GFX8-NEXT:    v_mov_b32_e32 v5, s3
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_mul_hi_u32 v7, v5, s8
+; GFX8-NEXT:    s_mul_i32 s21, s0, s12
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    s_add_u32 s17, s17, s21
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, s17, v7
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_mul_hi_u32 v4, v4, s9
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, s18, v11
+; GFX8-NEXT:    s_mul_i32 s17, s5, s8
+; GFX8-NEXT:    s_mul_i32 s18, s4, s9
+; GFX8-NEXT:    s_add_u32 s17, s17, s18
+; GFX8-NEXT:    v_mul_hi_u32 v8, s1, v6
+; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v7, v4
+; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX8-NEXT:    v_mov_b32_e32 v9, s11
+; GFX8-NEXT:    s_mul_i32 s19, s3, s10
+; GFX8-NEXT:    s_and_b32 s18, s18, 1
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v11, v7
+; GFX8-NEXT:    s_add_u32 s17, s17, s19
+; GFX8-NEXT:    v_mul_hi_u32 v10, s0, v9
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v8
+; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    s_mul_i32 s20, s2, s11
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v10
+; GFX8-NEXT:    s_add_u32 s17, s17, s20
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
+; GFX8-NEXT:    s_mul_i32 s21, s1, s12
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX8-NEXT:    s_add_u32 s17, s17, s21
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v7, v4
+; GFX8-NEXT:    v_mov_b32_e32 v7, s4
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_mul_hi_u32 v8, v7, s8
+; GFX8-NEXT:    s_mul_i32 s22, s0, s13
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    s_add_u32 s17, s17, s22
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, s17, v8
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_mul_hi_u32 v10, v5, s9
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v14, vcc, s18, v14
+; GFX8-NEXT:    s_mul_i32 s17, s6, s8
+; GFX8-NEXT:    s_mul_i32 s18, s5, s9
+; GFX8-NEXT:    s_add_u32 s17, s17, s18
+; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v6, s2, v6
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v8, v10
+; GFX8-NEXT:    s_mul_i32 s19, s4, s10
+; GFX8-NEXT:    s_and_b32 s18, s18, 1
+; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX8-NEXT:    s_add_u32 s17, s17, s19
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v14, v10
+; GFX8-NEXT:    v_mul_hi_u32 v11, s1, v9
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v8, v6
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX8-NEXT:    v_mov_b32_e32 v12, s12
+; GFX8-NEXT:    s_mul_i32 s20, s3, s11
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v10, v8
+; GFX8-NEXT:    s_add_u32 s17, s17, s20
+; GFX8-NEXT:    v_mul_hi_u32 v13, s0, v12
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v11
+; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v8, v10
+; GFX8-NEXT:    s_mul_i32 s21, s2, s12
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v13
+; GFX8-NEXT:    s_add_u32 s17, s17, s21
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v8, v10
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v6, v4
+; GFX8-NEXT:    s_mul_i32 s22, s1, s13
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX8-NEXT:    s_add_u32 s17, s17, s22
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v8, v6
+; GFX8-NEXT:    v_mov_b32_e32 v8, s5
+; GFX8-NEXT:    v_mul_hi_u32 v10, v8, s8
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    s_mul_i32 s23, s0, s14
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    s_add_u32 s17, s17, s23
+; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX8-NEXT:    v_mul_hi_u32 v11, v7, s9
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, s17, v10
+; GFX8-NEXT:    s_and_b32 s19, s19, 1
+; GFX8-NEXT:    s_add_i32 s18, s18, s19
+; GFX8-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v17, vcc, s18, v17
+; GFX8-NEXT:    v_mul_hi_u32 v5, v5, s10
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v10, v11
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_mul_hi_u32 v13, s2, v9
+; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v17, v11
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v10, v5
+; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v11, v10
+; GFX8-NEXT:    v_mul_hi_u32 v14, s1, v12
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v5, v13
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_mov_b32_e32 v15, s13
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v10, v11
+; GFX8-NEXT:    v_mul_hi_u32 v16, s0, v15
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v5, v14
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v10, v11
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v5, v16
+; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v10, v11
+; GFX8-NEXT:    v_mov_b32_e32 v13, s14
+; GFX8-NEXT:    s_mul_i32 s7, s7, s8
+; GFX8-NEXT:    s_mul_i32 s17, s6, s9
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v5, v6
+; GFX8-NEXT:    s_mul_i32 s16, s0, s8
+; GFX8-NEXT:    s_mul_i32 s5, s5, s10
+; GFX8-NEXT:    s_mul_i32 s15, s0, s15
+; GFX8-NEXT:    v_mul_hi_u32 v13, s0, v13
+; GFX8-NEXT:    s_add_i32 s0, s7, s17
+; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX8-NEXT:    s_mul_i32 s4, s4, s11
+; GFX8-NEXT:    s_add_i32 s0, s0, s5
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v10, v6
+; GFX8-NEXT:    v_mov_b32_e32 v10, s6
+; GFX8-NEXT:    s_mul_i32 s11, s3, s12
+; GFX8-NEXT:    s_add_i32 s0, s0, s4
+; GFX8-NEXT:    s_mul_i32 s12, s2, s13
+; GFX8-NEXT:    s_add_i32 s0, s0, s11
+; GFX8-NEXT:    v_mul_hi_u32 v10, v10, s8
+; GFX8-NEXT:    s_mul_i32 s13, s1, s14
+; GFX8-NEXT:    s_add_i32 s0, s0, s12
+; GFX8-NEXT:    v_mul_hi_u32 v8, v8, s9
+; GFX8-NEXT:    s_add_i32 s0, s0, s13
+; GFX8-NEXT:    v_mul_hi_u32 v7, v7, s10
+; GFX8-NEXT:    v_mul_hi_u32 v9, s3, v9
+; GFX8-NEXT:    s_add_i32 s0, s0, s15
+; GFX8-NEXT:    v_mul_hi_u32 v11, s2, v12
+; GFX8-NEXT:    v_add_u32_e32 v10, vcc, s0, v10
+; GFX8-NEXT:    v_mul_hi_u32 v12, s1, v15
+; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v10, v8
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v8, v7
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v9
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v11
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v12
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v13
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s4, v3
+; GFX8-NEXT:    v_readfirstlane_b32 s5, v4
+; GFX8-NEXT:    v_readfirstlane_b32 s6, v5
+; GFX8-NEXT:    v_readfirstlane_b32 s7, v6
+; GFX8-NEXT:    s_mov_b32 s0, s16
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_mul_i256:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mul_i32 s17, s1, s8
+; GFX9-NEXT:    s_mul_i32 s18, s0, s9
+; GFX9-NEXT:    s_add_u32 s17, s17, s18
+; GFX9-NEXT:    s_cselect_b32 s18, 1, 0
+; GFX9-NEXT:    s_mul_hi_u32 s19, s0, s8
+; GFX9-NEXT:    s_and_b32 s18, s18, 1
+; GFX9-NEXT:    s_add_u32 s17, s17, s19
+; GFX9-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX9-NEXT:    s_and_b32 s19, s19, 1
+; GFX9-NEXT:    s_add_i32 s18, s18, s19
+; GFX9-NEXT:    s_mul_i32 s19, s2, s8
+; GFX9-NEXT:    s_mul_i32 s20, s1, s9
+; GFX9-NEXT:    s_add_u32 s19, s19, s20
+; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
+; GFX9-NEXT:    s_mul_i32 s21, s0, s10
+; GFX9-NEXT:    s_and_b32 s20, s20, 1
+; GFX9-NEXT:    s_add_u32 s19, s19, s21
+; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
+; GFX9-NEXT:    s_and_b32 s21, s21, 1
+; GFX9-NEXT:    s_mul_hi_u32 s22, s1, s8
+; GFX9-NEXT:    s_add_i32 s20, s20, s21
+; GFX9-NEXT:    s_add_u32 s19, s19, s22
+; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
+; GFX9-NEXT:    s_and_b32 s21, s21, 1
+; GFX9-NEXT:    s_mul_hi_u32 s23, s0, s9
+; GFX9-NEXT:    s_add_i32 s20, s20, s21
+; GFX9-NEXT:    s_add_u32 s19, s19, s23
+; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
+; GFX9-NEXT:    s_and_b32 s21, s21, 1
+; GFX9-NEXT:    s_add_i32 s20, s20, s21
+; GFX9-NEXT:    s_add_u32 s18, s19, s18
+; GFX9-NEXT:    s_cselect_b32 s19, 1, 0
+; GFX9-NEXT:    s_and_b32 s19, s19, 1
+; GFX9-NEXT:    s_add_i32 s20, s20, s19
+; GFX9-NEXT:    s_mul_i32 s19, s3, s8
+; GFX9-NEXT:    s_mul_i32 s21, s2, s9
+; GFX9-NEXT:    s_add_u32 s19, s19, s21
+; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
+; GFX9-NEXT:    s_mul_i32 s22, s1, s10
+; GFX9-NEXT:    s_and_b32 s21, s21, 1
+; GFX9-NEXT:    s_add_u32 s19, s19, s22
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_mul_i32 s23, s0, s11
+; GFX9-NEXT:    s_add_i32 s21, s21, s22
+; GFX9-NEXT:    s_add_u32 s19, s19, s23
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_mul_hi_u32 s24, s2, s8
+; GFX9-NEXT:    s_add_i32 s21, s21, s22
+; GFX9-NEXT:    s_add_u32 s19, s19, s24
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_mul_hi_u32 s25, s1, s9
+; GFX9-NEXT:    s_add_i32 s21, s21, s22
+; GFX9-NEXT:    s_add_u32 s19, s19, s25
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_mul_hi_u32 s26, s0, s10
+; GFX9-NEXT:    s_add_i32 s21, s21, s22
+; GFX9-NEXT:    s_add_u32 s19, s19, s26
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_add_i32 s21, s21, s22
+; GFX9-NEXT:    s_add_u32 s19, s19, s20
+; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
+; GFX9-NEXT:    s_and_b32 s20, s20, 1
+; GFX9-NEXT:    s_add_i32 s21, s21, s20
+; GFX9-NEXT:    s_mul_i32 s20, s4, s8
+; GFX9-NEXT:    s_mul_i32 s22, s3, s9
+; GFX9-NEXT:    s_add_u32 s20, s20, s22
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_mul_i32 s23, s2, s10
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_add_u32 s20, s20, s23
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_mul_i32 s24, s1, s11
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s24
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_mul_i32 s25, s0, s12
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s25
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_mul_hi_u32 s26, s3, s8
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s26
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_mul_hi_u32 s27, s2, s9
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s27
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_mul_hi_u32 s28, s1, s10
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s28
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_mul_hi_u32 s29, s0, s11
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s29
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_add_i32 s22, s22, s23
+; GFX9-NEXT:    s_add_u32 s20, s20, s21
+; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
+; GFX9-NEXT:    s_and_b32 s21, s21, 1
+; GFX9-NEXT:    s_add_i32 s22, s22, s21
+; GFX9-NEXT:    s_mul_i32 s21, s5, s8
+; GFX9-NEXT:    s_mul_i32 s23, s4, s9
+; GFX9-NEXT:    s_add_u32 s21, s21, s23
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_mul_i32 s24, s3, s10
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_add_u32 s21, s21, s24
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_i32 s25, s2, s11
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s25
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_i32 s26, s1, s12
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s26
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_i32 s27, s0, s13
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s27
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_hi_u32 s28, s4, s8
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s28
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_hi_u32 s29, s3, s9
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s29
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_hi_u32 s30, s2, s10
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s30
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_hi_u32 s31, s1, s11
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s31
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_mul_hi_u32 s32, s0, s12
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s32
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_add_i32 s23, s23, s24
+; GFX9-NEXT:    s_add_u32 s21, s21, s22
+; GFX9-NEXT:    s_cselect_b32 s22, 1, 0
+; GFX9-NEXT:    s_and_b32 s22, s22, 1
+; GFX9-NEXT:    s_add_i32 s23, s23, s22
+; GFX9-NEXT:    s_mul_i32 s22, s6, s8
+; GFX9-NEXT:    s_mul_i32 s24, s5, s9
+; GFX9-NEXT:    s_add_u32 s22, s22, s24
+; GFX9-NEXT:    s_cselect_b32 s24, 1, 0
+; GFX9-NEXT:    s_mul_i32 s25, s4, s10
+; GFX9-NEXT:    s_and_b32 s24, s24, 1
+; GFX9-NEXT:    s_add_u32 s22, s22, s25
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_i32 s26, s3, s11
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s26
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_i32 s27, s2, s12
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s27
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_i32 s28, s1, s13
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s28
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_i32 s29, s0, s14
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s29
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_hi_u32 s30, s5, s8
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s30
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_hi_u32 s31, s4, s9
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s31
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_hi_u32 s32, s3, s10
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s32
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_hi_u32 s33, s2, s11
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s33
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_hi_u32 s34, s1, s12
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s34
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_mul_hi_u32 s35, s0, s13
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s35
+; GFX9-NEXT:    s_cselect_b32 s25, 1, 0
+; GFX9-NEXT:    s_and_b32 s25, s25, 1
+; GFX9-NEXT:    s_add_i32 s24, s24, s25
+; GFX9-NEXT:    s_add_u32 s22, s22, s23
+; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
+; GFX9-NEXT:    s_and_b32 s23, s23, 1
+; GFX9-NEXT:    s_add_i32 s24, s24, s23
+; GFX9-NEXT:    s_mul_i32 s23, s6, s9
+; GFX9-NEXT:    s_mul_i32 s7, s7, s8
+; GFX9-NEXT:    s_mul_i32 s25, s5, s10
+; GFX9-NEXT:    s_add_i32 s7, s7, s23
+; GFX9-NEXT:    s_mul_i32 s26, s4, s11
+; GFX9-NEXT:    s_add_i32 s7, s7, s25
+; GFX9-NEXT:    s_mul_i32 s27, s3, s12
+; GFX9-NEXT:    s_add_i32 s7, s7, s26
+; GFX9-NEXT:    s_mul_i32 s28, s2, s13
+; GFX9-NEXT:    s_add_i32 s7, s7, s27
+; GFX9-NEXT:    s_mul_i32 s29, s1, s14
+; GFX9-NEXT:    s_add_i32 s7, s7, s28
+; GFX9-NEXT:    s_mul_i32 s15, s0, s15
+; GFX9-NEXT:    s_add_i32 s7, s7, s29
+; GFX9-NEXT:    s_mul_hi_u32 s6, s6, s8
+; GFX9-NEXT:    s_add_i32 s7, s7, s15
+; GFX9-NEXT:    s_mul_hi_u32 s5, s5, s9
+; GFX9-NEXT:    s_add_i32 s6, s7, s6
+; GFX9-NEXT:    s_add_i32 s5, s6, s5
+; GFX9-NEXT:    s_mul_hi_u32 s4, s4, s10
+; GFX9-NEXT:    s_add_i32 s4, s5, s4
+; GFX9-NEXT:    s_mul_hi_u32 s3, s3, s11
+; GFX9-NEXT:    s_add_i32 s3, s4, s3
+; GFX9-NEXT:    s_mul_hi_u32 s2, s2, s12
+; GFX9-NEXT:    s_add_i32 s2, s3, s2
+; GFX9-NEXT:    s_mul_hi_u32 s1, s1, s13
+; GFX9-NEXT:    s_mul_i32 s16, s0, s8
+; GFX9-NEXT:    s_add_i32 s1, s2, s1
+; GFX9-NEXT:    s_mul_hi_u32 s0, s0, s14
+; GFX9-NEXT:    s_add_i32 s0, s1, s0
+; GFX9-NEXT:    s_add_i32 s7, s0, s24
+; GFX9-NEXT:    s_mov_b32 s0, s16
+; GFX9-NEXT:    s_mov_b32 s1, s17
+; GFX9-NEXT:    s_mov_b32 s2, s18
+; GFX9-NEXT:    s_mov_b32 s3, s19
+; GFX9-NEXT:    s_mov_b32 s4, s20
+; GFX9-NEXT:    s_mov_b32 s5, s21
+; GFX9-NEXT:    s_mov_b32 s6, s22
+; GFX9-NEXT:    ; return to shader part epilog
+  %result = mul i256 %num, %den
+  %cast = bitcast i256 %result to <8 x i32>
+  ret <8 x i32> %cast
+}
+
+define i256 @v_mul_i256(i256 %num, i256 %den) {
+; GFX7-LABEL: v_mul_i256:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mul_lo_u32 v16, v1, v8
+; GFX7-NEXT:    v_mul_lo_u32 v17, v0, v9
+; GFX7-NEXT:    v_mul_hi_u32 v18, v0, v8
+; GFX7-NEXT:    v_mul_lo_u32 v19, v2, v8
+; GFX7-NEXT:    v_mul_lo_u32 v20, v1, v9
+; GFX7-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
+; GFX7-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
+; GFX7-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v17, vcc, v17, v18
+; GFX7-NEXT:    v_mul_lo_u32 v18, v0, v10
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
+; GFX7-NEXT:    v_mul_hi_u32 v21, v1, v8
+; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
+; GFX7-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v21
+; GFX7-NEXT:    v_mul_hi_u32 v21, v0, v9
+; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
+; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v11
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v21
+; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
+; GFX7-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
+; GFX7-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX7-NEXT:    v_mul_lo_u32 v20, v3, v8
+; GFX7-NEXT:    v_mul_lo_u32 v21, v2, v9
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
+; GFX7-NEXT:    v_mul_lo_u32 v19, v1, v10
+; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
+; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v2, v8
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_mul_lo_u32 v7, v7, v8
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v1, v9
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_mul_lo_u32 v15, v0, v15
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v0, v10
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
+; GFX7-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX7-NEXT:    v_mul_lo_u32 v21, v4, v8
+; GFX7-NEXT:    v_mul_lo_u32 v22, v3, v9
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
+; GFX7-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_mul_lo_u32 v23, v0, v12
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v2, v9
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v0, v11
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
+; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX7-NEXT:    v_mul_lo_u32 v22, v5, v8
+; GFX7-NEXT:    v_mul_lo_u32 v23, v4, v9
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
+; GFX7-NEXT:    v_mul_lo_u32 v21, v3, v10
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v23, v22
+; GFX7-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v12
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_lo_u32 v23, v0, v13
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v4, v8
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v3, v9
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v2, v10
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v1, v11
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_hi_u32 v23, v0, v12
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
+; GFX7-NEXT:    v_mul_lo_u32 v22, v6, v8
+; GFX7-NEXT:    v_mul_lo_u32 v23, v5, v9
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_mul_lo_u32 v23, v4, v10
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v24, v23
+; GFX7-NEXT:    v_mul_lo_u32 v24, v3, v11
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_lo_u32 v24, v2, v12
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_lo_u32 v24, v1, v13
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_lo_u32 v24, v0, v14
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_hi_u32 v24, v5, v8
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_hi_u32 v24, v4, v9
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_hi_u32 v24, v3, v10
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_hi_u32 v24, v2, v11
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_hi_u32 v24, v1, v12
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_mul_hi_u32 v24, v0, v13
+; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v24
+; GFX7-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v24
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v23, vcc, v23, v22
+; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v8
+; GFX7-NEXT:    v_mul_hi_u32 v8, v6, v8
+; GFX7-NEXT:    v_mul_lo_u32 v6, v6, v9
+; GFX7-NEXT:    v_mul_hi_u32 v9, v5, v9
+; GFX7-NEXT:    v_mul_lo_u32 v5, v5, v10
+; GFX7-NEXT:    v_mul_hi_u32 v10, v4, v10
+; GFX7-NEXT:    v_mul_lo_u32 v4, v4, v11
+; GFX7-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GFX7-NEXT:    v_mul_lo_u32 v3, v3, v12
+; GFX7-NEXT:    v_mul_hi_u32 v12, v2, v12
+; GFX7-NEXT:    v_mul_lo_u32 v2, v2, v13
+; GFX7-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX7-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX7-NEXT:    v_mul_hi_u32 v13, v1, v13
+; GFX7-NEXT:    v_mul_lo_u32 v1, v1, v14
+; GFX7-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX7-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX7-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v15
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v8
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v10
+; GFX7-NEXT:    v_mul_hi_u32 v0, v0, v14
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v11
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v12
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v13
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
+; GFX7-NEXT:    v_add_i32_e32 v7, vcc, v0, v23
+; GFX7-NEXT:    v_mov_b32_e32 v0, v22
+; GFX7-NEXT:    v_mov_b32_e32 v1, v16
+; GFX7-NEXT:    v_mov_b32_e32 v2, v17
+; GFX7-NEXT:    v_mov_b32_e32 v3, v18
+; GFX7-NEXT:    v_mov_b32_e32 v4, v19
+; GFX7-NEXT:    v_mov_b32_e32 v5, v20
+; GFX7-NEXT:    v_mov_b32_e32 v6, v21
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_mul_i256:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mul_lo_u32 v16, v1, v8
+; GFX8-NEXT:    v_mul_lo_u32 v17, v0, v9
+; GFX8-NEXT:    v_mul_hi_u32 v18, v0, v8
+; GFX8-NEXT:    v_mul_lo_u32 v19, v2, v8
+; GFX8-NEXT:    v_mul_lo_u32 v20, v1, v9
+; GFX8-NEXT:    v_add_u32_e32 v16, vcc, v16, v17
+; GFX8-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v16, vcc, v16, v18
+; GFX8-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v17, vcc, v17, v18
+; GFX8-NEXT:    v_mul_lo_u32 v18, v0, v10
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
+; GFX8-NEXT:    v_mul_hi_u32 v21, v1, v8
+; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
+; GFX8-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v21
+; GFX8-NEXT:    v_mul_hi_u32 v21, v0, v9
+; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
+; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v11
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v21
+; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
+; GFX8-NEXT:    v_add_u32_e32 v17, vcc, v18, v17
+; GFX8-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX8-NEXT:    v_mul_lo_u32 v20, v3, v8
+; GFX8-NEXT:    v_mul_lo_u32 v21, v2, v9
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
+; GFX8-NEXT:    v_mul_lo_u32 v19, v1, v10
+; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
+; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v2, v8
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_mul_lo_u32 v7, v7, v8
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v1, v9
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_mul_lo_u32 v15, v0, v15
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v0, v10
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
+; GFX8-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX8-NEXT:    v_mul_lo_u32 v21, v4, v8
+; GFX8-NEXT:    v_mul_lo_u32 v22, v3, v9
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
+; GFX8-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_mul_lo_u32 v23, v0, v12
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v2, v9
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v0, v11
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
+; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX8-NEXT:    v_mul_lo_u32 v22, v5, v8
+; GFX8-NEXT:    v_mul_lo_u32 v23, v4, v9
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
+; GFX8-NEXT:    v_mul_lo_u32 v21, v3, v10
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v23, v22
+; GFX8-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v12
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_lo_u32 v23, v0, v13
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v4, v8
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v3, v9
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v2, v10
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v1, v11
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_hi_u32 v23, v0, v12
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
+; GFX8-NEXT:    v_mul_lo_u32 v22, v6, v8
+; GFX8-NEXT:    v_mul_lo_u32 v23, v5, v9
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_mul_lo_u32 v23, v4, v10
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v24, v23
+; GFX8-NEXT:    v_mul_lo_u32 v24, v3, v11
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_lo_u32 v24, v2, v12
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_lo_u32 v24, v1, v13
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_lo_u32 v24, v0, v14
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_hi_u32 v24, v5, v8
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_hi_u32 v24, v4, v9
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_hi_u32 v24, v3, v10
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_hi_u32 v24, v2, v11
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_hi_u32 v24, v1, v12
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_mul_hi_u32 v24, v0, v13
+; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v24
+; GFX8-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v24
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v23, vcc, v23, v22
+; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v8
+; GFX8-NEXT:    v_mul_hi_u32 v8, v6, v8
+; GFX8-NEXT:    v_mul_lo_u32 v6, v6, v9
+; GFX8-NEXT:    v_mul_hi_u32 v9, v5, v9
+; GFX8-NEXT:    v_mul_lo_u32 v5, v5, v10
+; GFX8-NEXT:    v_mul_hi_u32 v10, v4, v10
+; GFX8-NEXT:    v_mul_lo_u32 v4, v4, v11
+; GFX8-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GFX8-NEXT:    v_mul_lo_u32 v3, v3, v12
+; GFX8-NEXT:    v_mul_hi_u32 v12, v2, v12
+; GFX8-NEXT:    v_mul_lo_u32 v2, v2, v13
+; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
+; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v6, v5
+; GFX8-NEXT:    v_mul_hi_u32 v13, v1, v13
+; GFX8-NEXT:    v_mul_lo_u32 v1, v1, v14
+; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v5, v4
+; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v15
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v8
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v9
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v10
+; GFX8-NEXT:    v_mul_hi_u32 v0, v0, v14
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v11
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v12
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v13
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v0, v23
+; GFX8-NEXT:    v_mov_b32_e32 v0, v22
+; GFX8-NEXT:    v_mov_b32_e32 v1, v16
+; GFX8-NEXT:    v_mov_b32_e32 v2, v17
+; GFX8-NEXT:    v_mov_b32_e32 v3, v18
+; GFX8-NEXT:    v_mov_b32_e32 v4, v19
+; GFX8-NEXT:    v_mov_b32_e32 v5, v20
+; GFX8-NEXT:    v_mov_b32_e32 v6, v21
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_mul_i256:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_lo_u32 v16, v2, v8
+; GFX9-NEXT:    v_mul_lo_u32 v17, v1, v9
+; GFX9-NEXT:    v_mul_lo_u32 v18, v0, v10
+; GFX9-NEXT:    v_mul_hi_u32 v19, v1, v8
+; GFX9-NEXT:    v_mul_lo_u32 v20, v1, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v16, vcc, v16, v17
+; GFX9-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v16, vcc, v16, v18
+; GFX9-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v16, v19
+; GFX9-NEXT:    v_mul_lo_u32 v21, v0, v9
+; GFX9-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v18, v17, v18, v16
+; GFX9-NEXT:    v_mul_hi_u32 v16, v0, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v17, vcc, v20, v21
+; GFX9-NEXT:    v_mul_hi_u32 v21, v0, v9
+; GFX9-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v16, vcc, v17, v16
+; GFX9-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v21
+; GFX9-NEXT:    v_add_u32_e32 v17, v20, v17
+; GFX9-NEXT:    v_mul_lo_u32 v21, v3, v8
+; GFX9-NEXT:    v_mul_lo_u32 v22, v2, v9
+; GFX9-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v17, vcc, v19, v17
+; GFX9-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v18, v18, v20, v19
+; GFX9-NEXT:    v_mul_lo_u32 v19, v1, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v21, v22
+; GFX9-NEXT:    v_mul_lo_u32 v22, v0, v11
+; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v20, v19
+; GFX9-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v22
+; GFX9-NEXT:    v_mul_hi_u32 v23, v2, v8
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v20, v21, v20, v22
+; GFX9-NEXT:    v_mul_hi_u32 v21, v1, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v23
+; GFX9-NEXT:    v_mul_hi_u32 v23, v0, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v21
+; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v20, v20, v22, v21
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v23
+; GFX9-NEXT:    v_mul_lo_u32 v22, v4, v8
+; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v9
+; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v18, vcc, v19, v18
+; GFX9-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v19, v20, v21, v19
+; GFX9-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v22, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v21, v20
+; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v21, v22, v21, v23
+; GFX9-NEXT:    v_mul_lo_u32 v22, v0, v12
+; GFX9-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v22
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v21, v21, v22, v23
+; GFX9-NEXT:    v_mul_hi_u32 v22, v2, v9
+; GFX9-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v22
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v21, v21, v22, v23
+; GFX9-NEXT:    v_mul_hi_u32 v22, v0, v11
+; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v22
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v20, v19
+; GFX9-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v20, v21, v22, v20
+; GFX9-NEXT:    v_mul_lo_u32 v21, v5, v8
+; GFX9-NEXT:    v_mul_lo_u32 v22, v4, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v22
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v22, v22, v24, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v1, v12
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v0, v13
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v22, v22, v24, v23
+; GFX9-NEXT:    v_mul_hi_u32 v23, v4, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_mul_hi_u32 v23, v3, v9
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v22, v22, v24, v23
+; GFX9-NEXT:    v_mul_hi_u32 v23, v2, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_mul_hi_u32 v23, v1, v11
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v22, v22, v24, v23
+; GFX9-NEXT:    v_mul_hi_u32 v23, v0, v12
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v21, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v21, v20
+; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v21, v22, v23, v21
+; GFX9-NEXT:    v_mul_lo_u32 v22, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v23, v5, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v4, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v11
+; GFX9-NEXT:    v_cndmask_b32_e64 v25, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v23, v24, v25, v23
+; GFX9-NEXT:    v_mul_lo_u32 v24, v2, v12
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_mul_lo_u32 v24, v1, v13
+; GFX9-NEXT:    v_cndmask_b32_e64 v25, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v23, v23, v25, v24
+; GFX9-NEXT:    v_mul_lo_u32 v24, v0, v14
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_mul_hi_u32 v24, v5, v8
+; GFX9-NEXT:    v_cndmask_b32_e64 v25, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v23, v23, v25, v24
+; GFX9-NEXT:    v_mul_hi_u32 v24, v4, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_mul_hi_u32 v24, v3, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v25, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v23, v23, v25, v24
+; GFX9-NEXT:    v_mul_hi_u32 v24, v2, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_mul_hi_u32 v24, v1, v12
+; GFX9-NEXT:    v_cndmask_b32_e64 v25, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v23, v23, v25, v24
+; GFX9-NEXT:    v_mul_hi_u32 v24, v0, v13
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v24
+; GFX9-NEXT:    v_cndmask_b32_e64 v24, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v22, v21
+; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX9-NEXT:    v_add3_u32 v22, v23, v24, v22
+; GFX9-NEXT:    v_mul_lo_u32 v23, v6, v9
+; GFX9-NEXT:    v_mul_lo_u32 v24, v4, v11
+; GFX9-NEXT:    v_mul_hi_u32 v4, v4, v10
+; GFX9-NEXT:    v_mul_hi_u32 v6, v6, v8
+; GFX9-NEXT:    v_add_u32_e32 v7, v7, v23
+; GFX9-NEXT:    v_mul_lo_u32 v23, v5, v10
+; GFX9-NEXT:    v_mul_hi_u32 v5, v5, v9
+; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v11
+; GFX9-NEXT:    v_mul_hi_u32 v10, v2, v12
+; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v12
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v13
+; GFX9-NEXT:    v_mul_hi_u32 v11, v1, v13
+; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v14
+; GFX9-NEXT:    v_mul_lo_u32 v13, v0, v15
+; GFX9-NEXT:    v_add3_u32 v7, v7, v23, v24
+; GFX9-NEXT:    v_add3_u32 v2, v7, v3, v2
+; GFX9-NEXT:    v_mul_lo_u32 v1, v0, v8
+; GFX9-NEXT:    v_add3_u32 v2, v2, v12, v13
+; GFX9-NEXT:    v_mul_hi_u32 v0, v0, v14
+; GFX9-NEXT:    v_add3_u32 v2, v2, v6, v5
+; GFX9-NEXT:    v_add3_u32 v2, v2, v4, v9
+; GFX9-NEXT:    v_add3_u32 v2, v2, v10, v11
+; GFX9-NEXT:    v_add3_u32 v7, v2, v0, v22
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v1, v16
+; GFX9-NEXT:    v_mov_b32_e32 v2, v17
+; GFX9-NEXT:    v_mov_b32_e32 v3, v18
+; GFX9-NEXT:    v_mov_b32_e32 v4, v19
+; GFX9-NEXT:    v_mov_b32_e32 v5, v20
+; GFX9-NEXT:    v_mov_b32_e32 v6, v21
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %result = mul i256 %num, %den
+  ret i256 %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
index 47cbb9372d3a9..8d7d356533d78 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
@@ -18,9 +18,9 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32
   ; CHECK:   [[COPY8:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -44,9 +44,9 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
   ; CHECK:   [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -98,7 +98,7 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {
   ; CHECK:   [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV3]](s64), [[UV3]](s64), implicit $exec
   ; CHECK:   [[S_AND_B64_2:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_3]], [[S_AND_B64_1]], implicit-def $scc
   ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32), [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32), [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR1]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY8]](s32), [[BUILD_VECTOR1]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_2]], implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
   ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
@@ -107,7 +107,7 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {
   ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
   ; CHECK: bb.4:
   ; CHECK:   [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY9]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -160,7 +160,7 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg
   ; CHECK:   [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV3]](s64), [[UV3]](s64), implicit $exec
   ; CHECK:   [[S_AND_B64_2:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_3]], [[S_AND_B64_1]], implicit-def $scc
   ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32), [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32), [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR1]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY9]](s32), [[BUILD_VECTOR1]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_2]], implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
   ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
@@ -169,7 +169,7 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg
   ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
   ; CHECK: bb.4:
   ; CHECK:   [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[COPY10]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
index b673d22c38201..384e74a2fbbd5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
-; XUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
 
 ; Natural mapping
 define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
@@ -23,8 +23,8 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inre
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
   ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
   ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -53,8 +53,8 @@ define amdgpu_ps void @sample_1d_sgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inre
   ; CHECK:   [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
   ; CHECK:   [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
   ; CHECK:   [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[COPY12]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -111,7 +111,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsr
   ; CHECK:   [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV3]](s64), [[UV3]](s64), implicit $exec
   ; CHECK:   [[S_AND_B64_2:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_3]], [[S_AND_B64_1]], implicit-def $scc
   ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32), [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32), [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR2]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR2]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_2]], implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
   ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
@@ -119,7 +119,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsr
   ; CHECK:   successors: %bb.4(0x80000000)
   ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
   ; CHECK: bb.4:
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -166,7 +166,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inre
   ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
   ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
   ; CHECK:   [[BUILD_VECTOR2:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR2]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR2]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
   ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
@@ -174,7 +174,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inre
   ; CHECK:   successors: %bb.4(0x80000000)
   ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
   ; CHECK: bb.4:
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
@@ -243,7 +243,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsr
   ; CHECK:   [[V_CMP_EQ_U64_e64_5:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV5]](s64), [[UV5]](s64), implicit $exec
   ; CHECK:   [[S_AND_B64_4:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_5]], [[S_AND_B64_3]], implicit-def $scc
   ; CHECK:   [[BUILD_VECTOR3:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_8]](s32), [[V_READFIRSTLANE_B32_9]](s32), [[V_READFIRSTLANE_B32_10]](s32), [[V_READFIRSTLANE_B32_11]](s32)
-  ; CHECK:   [[INT:%[0-9]+]]:vgpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR2]](<8 x s32>), [[BUILD_VECTOR3]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
+  ; CHECK:   [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR2]](<8 x s32>), [[BUILD_VECTOR3]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
   ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_4]], implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
   ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
@@ -251,7 +251,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsr
   ; CHECK:   successors: %bb.4(0x80000000)
   ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
   ; CHECK: bb.4:
-  ; CHECK:   G_STORE [[INT]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
+  ; CHECK:   G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store 16 into `<4 x float> addrspace(1)* undef`, addrspace 1)
   ; CHECK:   S_ENDPGM 0
   %v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
   store <4 x float> %v, <4 x float> addrspace(1)* undef
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
index 28d5b16cc91b8..5c2bc3e931120 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
@@ -22,10 +22,12 @@ legalized: true
 
 body: |
   bb.0:
-    liveins: $vgpr0_vgpr1
+    liveins: $vgpr0
     ; CHECK-LABEL: name: anyext_s32_to_s64_v
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s64) = G_ANYEXT %0
 ...
@@ -98,7 +100,10 @@ body: |
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[ICMP]](s1)
+    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[SELECT]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -116,7 +121,9 @@ body: |
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[ICMP]](s1)
+    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -134,7 +141,11 @@ body: |
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[ICMP]](s1)
+    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[COPY2]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -231,7 +242,9 @@ body: |
     ; CHECK-LABEL: name: anyext_s1_to_s64_vgpr
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[TRUNC]](s1)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
+    ; CHECK: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[ANYEXT]](s32), [[DEF]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s64) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
index 0f37d77102805..fec347169d0c8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
@@ -61,10 +61,7 @@ body: |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s16) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -83,10 +80,7 @@ body: |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -105,10 +99,7 @@ body: |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s64) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -188,10 +179,7 @@ body: |
     ; CHECK-LABEL: name: sext_s1_to_s16_sgpr
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s16) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s16) = G_SEXT %1
@@ -207,10 +195,7 @@ body: |
     ; CHECK-LABEL: name: sext_s1_to_s32_sgpr
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s32) = G_SEXT %1
@@ -226,10 +211,7 @@ body: |
     ; CHECK-LABEL: name: sext_s1_to_s64_sgpr
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s64) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s64) = G_SEXT %1
@@ -245,10 +227,7 @@ body: |
     ; CHECK-LABEL: name: sext_s1_to_s16_vgpr
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 15
-    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:vgpr(s16) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $vgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s16) = G_SEXT %1
@@ -264,10 +243,7 @@ body: |
     ; CHECK-LABEL: name: sext_s1_to_s32_vgpr
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
-    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:vgpr(s32) = G_SEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $vgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s32) = G_SEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
index ee22c54205d7a..ef83a4c6c5296 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
@@ -60,10 +60,7 @@ body: |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s16) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -82,10 +79,7 @@ body: |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -104,10 +98,7 @@ body: |
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s64) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s64) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -187,10 +178,7 @@ body: |
     ; CHECK-LABEL: name: zext_s1_to_s16_sgpr
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s16) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s16) = G_ZEXT %1
@@ -206,10 +194,7 @@ body: |
     ; CHECK-LABEL: name: zext_s1_to_s32_sgpr
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s32) = G_ZEXT %1
@@ -225,10 +210,7 @@ body: |
     ; CHECK-LABEL: name: zext_s1_to_s64_sgpr
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
-    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s64) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s64) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $sgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s64) = G_ZEXT %1
@@ -244,10 +226,7 @@ body: |
     ; CHECK-LABEL: name: zext_s1_to_s16_vgpr
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 15
-    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s16) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $vgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s16) = G_ZEXT %1
@@ -263,10 +242,7 @@ body: |
     ; CHECK-LABEL: name: zext_s1_to_s32_vgpr
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
-    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
-    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
-    ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[SHL]], [[C]](s32)
+    ; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC]](s1)
     %0:_(s32) = COPY $vgpr0
     %1:_(s1) = G_TRUNC %0
     %2:_(s32) = G_ZEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 55796554b08e8..3695586633dfb 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -375,9 +375,9 @@ define amdgpu_kernel void @add_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: add_i32_varying:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -428,9 +428,9 @@ define amdgpu_kernel void @add_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: add_i32_varying:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -480,9 +480,9 @@ define amdgpu_kernel void @add_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: add_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -539,10 +539,10 @@ define amdgpu_kernel void @add_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: add_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
@@ -614,9 +614,9 @@ define amdgpu_kernel void @add_i32_varying_gfx1032(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: add_i32_varying_gfx1032:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -667,9 +667,9 @@ define amdgpu_kernel void @add_i32_varying_gfx1032(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: add_i32_varying_gfx1032:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -719,9 +719,9 @@ define amdgpu_kernel void @add_i32_varying_gfx1032(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: add_i32_varying_gfx1032:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -778,10 +778,10 @@ define amdgpu_kernel void @add_i32_varying_gfx1032(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: add_i32_varying_gfx1032:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
@@ -853,9 +853,9 @@ define amdgpu_kernel void @add_i32_varying_gfx1064(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: add_i32_varying_gfx1064:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -906,9 +906,9 @@ define amdgpu_kernel void @add_i32_varying_gfx1064(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: add_i32_varying_gfx1064:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -958,9 +958,9 @@ define amdgpu_kernel void @add_i32_varying_gfx1064(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: add_i32_varying_gfx1064:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -1017,10 +1017,10 @@ define amdgpu_kernel void @add_i32_varying_gfx1064(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: add_i32_varying_gfx1064:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
@@ -1934,9 +1934,9 @@ define amdgpu_kernel void @sub_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: sub_i32_varying:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -1987,9 +1987,9 @@ define amdgpu_kernel void @sub_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: sub_i32_varying:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -2039,9 +2039,9 @@ define amdgpu_kernel void @sub_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: sub_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -2098,10 +2098,10 @@ define amdgpu_kernel void @sub_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: sub_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
@@ -2917,9 +2917,9 @@ define amdgpu_kernel void @or_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: or_i32_varying:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -2970,9 +2970,9 @@ define amdgpu_kernel void @or_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: or_i32_varying:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -3022,9 +3022,9 @@ define amdgpu_kernel void @or_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: or_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -3081,10 +3081,10 @@ define amdgpu_kernel void @or_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: or_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
@@ -3159,9 +3159,9 @@ define amdgpu_kernel void @xor_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: xor_i32_varying:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -3212,9 +3212,9 @@ define amdgpu_kernel void @xor_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: xor_i32_varying:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -3264,9 +3264,9 @@ define amdgpu_kernel void @xor_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: xor_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -3323,10 +3323,10 @@ define amdgpu_kernel void @xor_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: xor_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
@@ -4265,9 +4265,9 @@ define amdgpu_kernel void @umax_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX8-LABEL: umax_i32_varying:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -4318,9 +4318,9 @@ define amdgpu_kernel void @umax_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX9-LABEL: umax_i32_varying:
 ; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -4370,9 +4370,9 @@ define amdgpu_kernel void @umax_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1064-LABEL: umax_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
+; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0
@@ -4429,10 +4429,10 @@ define amdgpu_kernel void @umax_i32_varying(i32 addrspace(1)* %out) {
 ;
 ; GFX1032-LABEL: umax_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
+; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    ; implicit-def: $vcc_hi
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_ne_u32_e64 s2, 1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/call-encoding.ll b/llvm/test/CodeGen/AMDGPU/call-encoding.ll
index f018e9b360df0..b3829bd53e0e6 100644
--- a/llvm/test/CodeGen/AMDGPU/call-encoding.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-encoding.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=fiji -d - | FileCheck -check-prefixes=GCN,VI %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=gfx900 -d - | FileCheck -check-prefixes=GCN,GFX9 %s
-; XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=hawaii -d - | FileCheck -check-prefixes=GCN,CI %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=fiji -d - | FileCheck --check-prefixes=GCN,VI %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx900 -d - | FileCheck --check-prefixes=GCN,GFX9 %s
+; XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -filetype=obj -verify-machineinstrs < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=hawaii -d - | FileCheck --check-prefixes=GCN,CI %s
 
 ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT: s_setpc_b64
diff --git a/llvm/test/CodeGen/AMDGPU/elf.ll b/llvm/test/CodeGen/AMDGPU/elf.ll
index 4ddb763ee53f0..be49e273ad9fb 100644
--- a/llvm/test/CodeGen/AMDGPU/elf.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf.ll
@@ -8,7 +8,7 @@
 ; Test that we don't try to produce a COFF file on windows
 ; RUN: llc < %s -mtriple=amdgcn-pc-mingw -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
 
-; ELF: Format: ELF64-amdgpu
+; ELF: Format: elf64-amdgpu
 ; ELF: OS/ABI: SystemV (0x0)
 ; ELF: Machine: EM_AMDGPU (0xE0)
 ; ELF: Name: .AMDGPU.config
diff --git a/llvm/test/CodeGen/AMDGPU/elf.r600.ll b/llvm/test/CodeGen/AMDGPU/elf.r600.ll
index 63a87ed0ea42c..2763107246304 100644
--- a/llvm/test/CodeGen/AMDGPU/elf.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf.r600.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -S - | FileCheck --check-prefix=ELF %s
 ; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s
 
-; ELF: Format: ELF32-amdgpu
+; ELF: Format: elf32-amdgpu
 ; ELF: Name: .AMDGPU.config
 
 ; CONFIG: .section .AMDGPU.config
diff --git a/llvm/test/CodeGen/AMDGPU/fshl.ll b/llvm/test/CodeGen/AMDGPU/fshl.ll
index 0e17df416cd26..0f2d16ebcc2cc 100644
--- a/llvm/test/CodeGen/AMDGPU/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshl.ll
@@ -16,14 +16,13 @@ define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_and_b32 s2, s2, 31
-; SI-NEXT:    s_sub_i32 s8, 32, s2
-; SI-NEXT:    s_lshl_b32 s3, s0, s2
-; SI-NEXT:    s_lshr_b32 s1, s1, s8
-; SI-NEXT:    s_or_b32 s1, s3, s1
+; SI-NEXT:    s_sub_i32 s3, 32, s2
 ; SI-NEXT:    v_mov_b32_e32 v0, s1
+; SI-NEXT:    v_mov_b32_e32 v1, s3
+; SI-NEXT:    s_and_b32 s1, s2, 31
+; SI-NEXT:    v_alignbit_b32 v0, s0, v0, v1
 ; SI-NEXT:    v_mov_b32_e32 v1, s0
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
+; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
@@ -33,15 +32,14 @@ define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x2c
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_and_b32 s2, s2, 31
 ; VI-NEXT:    s_sub_i32 s3, 32, s2
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_lshl_b32 s0, s0, s2
-; VI-NEXT:    s_lshr_b32 s1, s1, s3
-; VI-NEXT:    s_or_b32 s0, s0, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s1
+; VI-NEXT:    s_and_b32 s1, s2, 31
+; VI-NEXT:    v_mov_b32_e32 v2, s3
 ; VI-NEXT:    v_mov_b32_e32 v1, s0
-; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; VI-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc
+; VI-NEXT:    v_alignbit_b32 v0, s0, v0, v2
+; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
+; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    flat_store_dword v[0:1], v2
@@ -52,15 +50,14 @@ define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x2c
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_and_b32 s2, s2, 31
 ; GFX9-NEXT:    s_sub_i32 s3, 32, s2
-; GFX9-NEXT:    v_mov_b32_e32 v0, s0
-; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
-; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
-; GFX9-NEXT:    s_or_b32 s0, s0, s1
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    s_and_b32 s1, s2, 31
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s0
-; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc
+; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v2
+; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX9-NEXT:    global_store_dword v[0:1], v2, off
@@ -68,19 +65,17 @@ define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
 ;
 ; R600-LABEL: fshl_i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     AND_INT * T0.W, KC0[3].X, literal.x,
-; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; R600-NEXT:     SUB_INT * T1.W, literal.x, PV.W,
+; R600-NEXT:     SUB_INT * T0.W, literal.x, KC0[3].X,
 ; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T1.W, KC0[2].W, PV.W,
-; R600-NEXT:     LSHL * T2.W, KC0[2].Z, T0.W,
-; R600-NEXT:     OR_INT * T1.W, PS, PV.W,
-; R600-NEXT:     CNDE_INT T0.X, T0.W, KC0[2].Z, PV.W,
+; R600-NEXT:     BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, PV.W,
+; R600-NEXT:     AND_INT * T1.W, KC0[3].X, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     CNDE_INT T0.X, PS, KC0[2].Z, PV.W,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 entry:
@@ -153,22 +148,20 @@ define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v1, s3
-; SI-NEXT:    v_mov_b32_e32 v2, s2
+; SI-NEXT:    v_mov_b32_e32 v0, s9
+; SI-NEXT:    s_sub_i32 s10, 32, s1
+; SI-NEXT:    v_mov_b32_e32 v1, s10
 ; SI-NEXT:    s_and_b32 s1, s1, 31
-; SI-NEXT:    s_sub_i32 s11, 32, s1
-; SI-NEXT:    s_and_b32 s0, s0, 31
-; SI-NEXT:    s_lshl_b32 s10, s3, s1
-; SI-NEXT:    s_lshr_b32 s9, s9, s11
-; SI-NEXT:    s_sub_i32 s3, 32, s0
-; SI-NEXT:    s_or_b32 s9, s10, s9
+; SI-NEXT:    v_alignbit_b32 v0, s3, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; SI-NEXT:    s_lshl_b32 s1, s2, s0
-; SI-NEXT:    s_lshr_b32 s3, s8, s3
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    s_or_b32 s1, s1, s3
+; SI-NEXT:    v_mov_b32_e32 v1, s3
+; SI-NEXT:    s_sub_i32 s1, 32, s0
 ; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s1
+; SI-NEXT:    s_and_b32 s0, s0, 31
+; SI-NEXT:    v_mov_b32_e32 v0, s8
+; SI-NEXT:    v_mov_b32_e32 v2, s1
+; SI-NEXT:    v_alignbit_b32 v0, s2, v0, v2
+; SI-NEXT:    v_mov_b32_e32 v2, s2
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -181,22 +174,20 @@ define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ; VI-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v1, s5
-; VI-NEXT:    v_mov_b32_e32 v2, s4
+; VI-NEXT:    v_mov_b32_e32 v0, s7
+; VI-NEXT:    s_sub_i32 s8, 32, s1
+; VI-NEXT:    v_mov_b32_e32 v1, s8
 ; VI-NEXT:    s_and_b32 s1, s1, 31
-; VI-NEXT:    s_sub_i32 s9, 32, s1
-; VI-NEXT:    s_and_b32 s0, s0, 31
-; VI-NEXT:    s_lshl_b32 s8, s5, s1
-; VI-NEXT:    s_lshr_b32 s7, s7, s9
-; VI-NEXT:    s_sub_i32 s5, 32, s0
-; VI-NEXT:    s_or_b32 s7, s8, s7
+; VI-NEXT:    v_alignbit_b32 v0, s5, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; VI-NEXT:    s_lshl_b32 s1, s4, s0
-; VI-NEXT:    s_lshr_b32 s5, s6, s5
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    s_or_b32 s1, s1, s5
+; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    s_sub_i32 s1, 32, s0
 ; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s1
+; VI-NEXT:    s_and_b32 s0, s0, 31
+; VI-NEXT:    v_mov_b32_e32 v0, s6
+; VI-NEXT:    v_mov_b32_e32 v2, s1
+; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v2
+; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
 ; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; VI-NEXT:    v_mov_b32_e32 v2, s2
@@ -211,22 +202,20 @@ define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s5
-; GFX9-NEXT:    v_mov_b32_e32 v2, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s7
+; GFX9-NEXT:    s_sub_i32 s8, 32, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s8
 ; GFX9-NEXT:    s_and_b32 s1, s1, 31
-; GFX9-NEXT:    s_sub_i32 s9, 32, s1
-; GFX9-NEXT:    s_and_b32 s0, s0, 31
-; GFX9-NEXT:    s_lshl_b32 s8, s5, s1
-; GFX9-NEXT:    s_lshr_b32 s7, s7, s9
-; GFX9-NEXT:    s_sub_i32 s5, 32, s0
-; GFX9-NEXT:    s_or_b32 s7, s8, s7
+; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; GFX9-NEXT:    s_lshl_b32 s1, s4, s0
-; GFX9-NEXT:    s_lshr_b32 s5, s6, s5
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    s_or_b32 s1, s1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    s_sub_i32 s1, 32, s0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    s_and_b32 s0, s0, 31
+; GFX9-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v2
+; GFX9-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s2
@@ -236,27 +225,22 @@ define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ;
 ; R600-LABEL: fshl_v2i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 18, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
 ; R600-NEXT:     AND_INT T0.W, KC0[4].X, literal.x,
-; R600-NEXT:     AND_INT * T1.W, KC0[3].W, literal.x,
-; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; R600-NEXT:     SUB_INT * T2.W, literal.x, PV.W,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T0.Z, KC0[3].Z, PV.W,
-; R600-NEXT:     LSHL T2.W, KC0[3].X, T0.W, BS:VEC_021/SCL_122
-; R600-NEXT:     SUB_INT * T3.W, literal.x, T1.W,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T0.Y, KC0[3].Y, PS,
-; R600-NEXT:     LSHL T1.Z, KC0[2].W, T1.W,
-; R600-NEXT:     OR_INT T2.W, PV.W, PV.Z,
-; R600-NEXT:     SETE_INT * T0.W, T0.W, 0.0,
+; R600-NEXT:     SUB_INT * T1.W, literal.y, KC0[4].X,
+; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
+; R600-NEXT:     AND_INT T0.Y, KC0[3].W, literal.x,
+; R600-NEXT:     SUB_INT T0.Z, literal.y, KC0[3].W,
+; R600-NEXT:     BIT_ALIGN_INT T1.W, KC0[3].X, KC0[3].Z, PS,
+; R600-NEXT:     SETE_INT * T0.W, PV.W, 0.0,
+; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
 ; R600-NEXT:     CNDE_INT T1.Y, PS, PV.W, KC0[3].X,
-; R600-NEXT:     OR_INT T0.W, PV.Z, PV.Y,
-; R600-NEXT:     SETE_INT * T1.W, T1.W, 0.0,
+; R600-NEXT:     BIT_ALIGN_INT T0.W, KC0[2].W, KC0[3].Y, PV.Z,
+; R600-NEXT:     SETE_INT * T1.W, PV.Y, 0.0,
 ; R600-NEXT:     CNDE_INT T1.X, PS, PV.W, KC0[2].W,
 ; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
@@ -341,40 +325,36 @@ define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v1, s11
-; SI-NEXT:    v_mov_b32_e32 v4, s8
+; SI-NEXT:    v_mov_b32_e32 v0, s15
+; SI-NEXT:    s_sub_i32 s16, 32, s3
+; SI-NEXT:    v_mov_b32_e32 v1, s16
 ; SI-NEXT:    s_and_b32 s3, s3, 31
-; SI-NEXT:    s_sub_i32 s17, 32, s3
-; SI-NEXT:    s_and_b32 s2, s2, 31
-; SI-NEXT:    s_lshl_b32 s16, s11, s3
-; SI-NEXT:    s_lshr_b32 s15, s15, s17
-; SI-NEXT:    s_sub_i32 s11, 32, s2
-; SI-NEXT:    s_or_b32 s15, s16, s15
+; SI-NEXT:    v_alignbit_b32 v0, s11, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
-; SI-NEXT:    s_lshl_b32 s3, s10, s2
-; SI-NEXT:    s_lshr_b32 s11, s14, s11
-; SI-NEXT:    v_mov_b32_e32 v0, s15
-; SI-NEXT:    s_or_b32 s3, s3, s11
-; SI-NEXT:    s_and_b32 s1, s1, 31
+; SI-NEXT:    v_mov_b32_e32 v1, s11
+; SI-NEXT:    s_sub_i32 s3, 32, s2
 ; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s3
-; SI-NEXT:    s_sub_i32 s3, 32, s1
+; SI-NEXT:    s_and_b32 s2, s2, 31
+; SI-NEXT:    v_mov_b32_e32 v0, s14
+; SI-NEXT:    v_mov_b32_e32 v1, s3
+; SI-NEXT:    v_alignbit_b32 v0, s10, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; SI-NEXT:    s_lshl_b32 s2, s9, s1
-; SI-NEXT:    s_lshr_b32 s3, s13, s3
 ; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    s_or_b32 s2, s2, s3
-; SI-NEXT:    s_and_b32 s0, s0, 31
+; SI-NEXT:    s_sub_i32 s2, 32, s1
 ; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s2
-; SI-NEXT:    s_sub_i32 s2, 32, s0
+; SI-NEXT:    s_and_b32 s1, s1, 31
+; SI-NEXT:    v_mov_b32_e32 v0, s13
+; SI-NEXT:    v_mov_b32_e32 v1, s2
+; SI-NEXT:    v_alignbit_b32 v0, s9, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; SI-NEXT:    s_lshl_b32 s1, s8, s0
-; SI-NEXT:    s_lshr_b32 s2, s12, s2
 ; SI-NEXT:    v_mov_b32_e32 v1, s9
-; SI-NEXT:    s_or_b32 s1, s1, s2
+; SI-NEXT:    s_sub_i32 s1, 32, s0
 ; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s1
+; SI-NEXT:    s_and_b32 s0, s0, 31
+; SI-NEXT:    v_mov_b32_e32 v0, s12
+; SI-NEXT:    v_mov_b32_e32 v4, s1
+; SI-NEXT:    v_alignbit_b32 v0, s8, v0, v4
+; SI-NEXT:    v_mov_b32_e32 v4, s8
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
@@ -387,40 +367,36 @@ define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ; VI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v1, s7
-; VI-NEXT:    v_mov_b32_e32 v4, s4
+; VI-NEXT:    v_mov_b32_e32 v0, s11
+; VI-NEXT:    s_sub_i32 s14, 32, s3
+; VI-NEXT:    v_mov_b32_e32 v1, s14
 ; VI-NEXT:    s_and_b32 s3, s3, 31
-; VI-NEXT:    s_sub_i32 s15, 32, s3
-; VI-NEXT:    s_and_b32 s2, s2, 31
-; VI-NEXT:    s_lshl_b32 s14, s7, s3
-; VI-NEXT:    s_lshr_b32 s11, s11, s15
-; VI-NEXT:    s_sub_i32 s7, 32, s2
-; VI-NEXT:    s_or_b32 s11, s14, s11
+; VI-NEXT:    v_alignbit_b32 v0, s7, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
-; VI-NEXT:    s_lshl_b32 s3, s6, s2
-; VI-NEXT:    s_lshr_b32 s7, s10, s7
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    s_or_b32 s3, s3, s7
-; VI-NEXT:    s_and_b32 s1, s1, 31
+; VI-NEXT:    v_mov_b32_e32 v1, s7
+; VI-NEXT:    s_sub_i32 s3, 32, s2
 ; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    s_sub_i32 s3, 32, s1
+; VI-NEXT:    s_and_b32 s2, s2, 31
+; VI-NEXT:    v_mov_b32_e32 v0, s10
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    v_alignbit_b32 v0, s6, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; VI-NEXT:    s_lshl_b32 s2, s5, s1
-; VI-NEXT:    s_lshr_b32 s3, s9, s3
 ; VI-NEXT:    v_mov_b32_e32 v1, s6
-; VI-NEXT:    s_or_b32 s2, s2, s3
-; VI-NEXT:    s_and_b32 s0, s0, 31
+; VI-NEXT:    s_sub_i32 s2, 32, s1
 ; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s2
-; VI-NEXT:    s_sub_i32 s2, 32, s0
+; VI-NEXT:    s_and_b32 s1, s1, 31
+; VI-NEXT:    v_mov_b32_e32 v0, s9
+; VI-NEXT:    v_mov_b32_e32 v1, s2
+; VI-NEXT:    v_alignbit_b32 v0, s5, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; VI-NEXT:    s_lshl_b32 s1, s4, s0
-; VI-NEXT:    s_lshr_b32 s2, s8, s2
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
-; VI-NEXT:    s_or_b32 s1, s1, s2
+; VI-NEXT:    s_sub_i32 s1, 32, s0
 ; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s1
+; VI-NEXT:    s_and_b32 s0, s0, 31
+; VI-NEXT:    v_mov_b32_e32 v0, s8
+; VI-NEXT:    v_mov_b32_e32 v4, s1
+; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v4, s4
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
 ; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, s12
@@ -435,40 +411,36 @@ define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s7
-; GFX9-NEXT:    v_mov_b32_e32 v4, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s11
+; GFX9-NEXT:    s_sub_i32 s14, 32, s3
+; GFX9-NEXT:    v_mov_b32_e32 v1, s14
 ; GFX9-NEXT:    s_and_b32 s3, s3, 31
-; GFX9-NEXT:    s_sub_i32 s15, 32, s3
-; GFX9-NEXT:    s_and_b32 s2, s2, 31
-; GFX9-NEXT:    s_lshl_b32 s14, s7, s3
-; GFX9-NEXT:    s_lshr_b32 s11, s11, s15
-; GFX9-NEXT:    s_sub_i32 s7, 32, s2
-; GFX9-NEXT:    s_or_b32 s11, s14, s11
+; GFX9-NEXT:    v_alignbit_b32 v0, s7, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
-; GFX9-NEXT:    s_lshl_b32 s3, s6, s2
-; GFX9-NEXT:    s_lshr_b32 s7, s10, s7
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    s_or_b32 s3, s3, s7
-; GFX9-NEXT:    s_and_b32 s1, s1, 31
+; GFX9-NEXT:    v_mov_b32_e32 v1, s7
+; GFX9-NEXT:    s_sub_i32 s3, 32, s2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s3
-; GFX9-NEXT:    s_sub_i32 s3, 32, s1
+; GFX9-NEXT:    s_and_b32 s2, s2, 31
+; GFX9-NEXT:    v_mov_b32_e32 v0, s10
+; GFX9-NEXT:    v_mov_b32_e32 v1, s3
+; GFX9-NEXT:    v_alignbit_b32 v0, s6, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX9-NEXT:    s_lshl_b32 s2, s5, s1
-; GFX9-NEXT:    s_lshr_b32 s3, s9, s3
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s6
-; GFX9-NEXT:    s_or_b32 s2, s2, s3
-; GFX9-NEXT:    s_and_b32 s0, s0, 31
+; GFX9-NEXT:    s_sub_i32 s2, 32, s1
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s2
-; GFX9-NEXT:    s_sub_i32 s2, 32, s0
+; GFX9-NEXT:    s_and_b32 s1, s1, 31
+; GFX9-NEXT:    v_mov_b32_e32 v0, s9
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
+; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; GFX9-NEXT:    s_lshl_b32 s1, s4, s0
-; GFX9-NEXT:    s_lshr_b32 s2, s8, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s5
-; GFX9-NEXT:    s_or_b32 s1, s1, s2
+; GFX9-NEXT:    s_sub_i32 s1, 32, s0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    s_and_b32 s0, s0, 31
+; GFX9-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-NEXT:    v_mov_b32_e32 v4, s1
+; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; GFX9-NEXT:    v_mov_b32_e32 v4, s4
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s12
@@ -478,45 +450,36 @@ define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ;
 ; R600-LABEL: fshl_v4i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 34, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; R600-NEXT:    ALU 25, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     AND_INT T0.W, KC0[5].Y, literal.x,
+; R600-NEXT:     SUB_INT * T0.W, literal.x, KC0[6].X,
+; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,
 ; R600-NEXT:     AND_INT * T1.W, KC0[6].X, literal.x,
 ; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; R600-NEXT:     SUB_INT * T2.W, literal.x, PV.W,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T0.Z, KC0[4].Y, PV.W,
-; R600-NEXT:     SUB_INT T2.W, literal.x, T1.W,
-; R600-NEXT:     AND_INT * T3.W, KC0[5].W, literal.y,
-; R600-NEXT:    32(4.484155e-44), 31(4.344025e-44)
-; R600-NEXT:     AND_INT T0.Y, KC0[5].Z, literal.x,
-; R600-NEXT:     SUB_INT T1.Z, literal.y, PS,
-; R600-NEXT:     LSHR * T2.W, KC0[5].X, PV.W,
+; R600-NEXT:     AND_INT T0.X, KC0[5].Z, literal.x,
+; R600-NEXT:     SUB_INT T0.Y, literal.y, KC0[5].Z,
+; R600-NEXT:     SETE_INT T0.Z, PV.W, 0.0,
+; R600-NEXT:     SUB_INT T1.W, literal.y, KC0[5].W,
+; R600-NEXT:     AND_INT * T2.W, KC0[5].W, literal.x,
 ; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
-; R600-NEXT:     LSHL * T4.W, KC0[4].X, T1.W,
-; R600-NEXT:     OR_INT T0.X, PV.W, T2.W,
-; R600-NEXT:     SETE_INT T1.Y, T1.W, 0.0,
-; R600-NEXT:     LSHR T1.Z, KC0[4].W, T1.Z,
-; R600-NEXT:     LSHL T1.W, KC0[3].W, T3.W, BS:VEC_021/SCL_122
-; R600-NEXT:     SUB_INT * T2.W, literal.x, T0.Y,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHR T1.X, KC0[4].Z, PS,
-; R600-NEXT:     LSHL T2.Y, KC0[3].Z, T0.Y,
-; R600-NEXT:     OR_INT T1.Z, PV.W, PV.Z,
-; R600-NEXT:     SETE_INT * T1.W, T3.W, 0.0,
-; R600-NEXT:     CNDE_INT * T2.W, T1.Y, T0.X, KC0[4].X,
-; R600-NEXT:     LSHL T1.Y, KC0[3].Y, T0.W,
-; R600-NEXT:     CNDE_INT T2.Z, T1.W, T1.Z, KC0[3].W,
-; R600-NEXT:     OR_INT T1.W, T2.Y, T1.X,
-; R600-NEXT:     SETE_INT * T3.W, T0.Y, 0.0,
-; R600-NEXT:     CNDE_INT T2.Y, PS, PV.W, KC0[3].Z,
-; R600-NEXT:     OR_INT T1.W, PV.Y, T0.Z,
-; R600-NEXT:     SETE_INT * T0.W, T0.W, 0.0,
-; R600-NEXT:     CNDE_INT T2.X, PS, PV.W, KC0[3].Y,
-; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT:     SETE_INT T1.Z, PS, 0.0,
+; R600-NEXT:     BIT_ALIGN_INT * T1.W, KC0[3].W, KC0[4].W, PV.W,
+; R600-NEXT:     CNDE_INT * T0.W, T0.Z, T0.W, KC0[4].X,
+; R600-NEXT:     CNDE_INT T0.Z, T1.Z, T1.W, KC0[3].W,
+; R600-NEXT:     BIT_ALIGN_INT T1.W, KC0[3].Z, KC0[4].Z, T0.Y,
+; R600-NEXT:     SETE_INT * T2.W, T0.X, 0.0,
+; R600-NEXT:     CNDE_INT T0.Y, PS, PV.W, KC0[3].Z,
+; R600-NEXT:     AND_INT T1.W, KC0[5].Y, literal.x,
+; R600-NEXT:     SUB_INT * T2.W, literal.y, KC0[5].Y,
+; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
+; R600-NEXT:     BIT_ALIGN_INT T2.W, KC0[3].Y, KC0[4].Y, PS,
+; R600-NEXT:     SETE_INT * T1.W, PV.W, 0.0,
+; R600-NEXT:     CNDE_INT T0.X, PS, PV.W, KC0[3].Y,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 entry:
   %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index f90863b26d5ac..f5d7671b9cf31 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -128,24 +128,18 @@ define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v1, s9
+; SI-NEXT:    v_mov_b32_e32 v0, s9
 ; SI-NEXT:    s_and_b32 s1, s1, 31
-; SI-NEXT:    s_sub_i32 s11, 32, s1
-; SI-NEXT:    s_lshr_b32 s10, s9, s1
-; SI-NEXT:    s_lshl_b32 s3, s3, s11
-; SI-NEXT:    s_or_b32 s3, s3, s10
+; SI-NEXT:    v_mov_b32_e32 v1, s1
 ; SI-NEXT:    s_and_b32 s0, s0, 31
-; SI-NEXT:    v_mov_b32_e32 v0, s3
-; SI-NEXT:    s_sub_i32 s3, 32, s0
+; SI-NEXT:    v_alignbit_b32 v1, s3, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; SI-NEXT:    s_lshr_b32 s1, s8, s0
-; SI-NEXT:    s_lshl_b32 s2, s2, s3
-; SI-NEXT:    s_or_b32 s1, s2, s1
-; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s1
-; SI-NEXT:    v_mov_b32_e32 v2, s8
+; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT:    v_mov_b32_e32 v0, s8
+; SI-NEXT:    v_mov_b32_e32 v2, s0
+; SI-NEXT:    v_alignbit_b32 v2, s2, v0, v2
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
-; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
@@ -156,24 +150,18 @@ define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ; VI-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v1, s7
+; VI-NEXT:    v_mov_b32_e32 v0, s7
 ; VI-NEXT:    s_and_b32 s1, s1, 31
-; VI-NEXT:    s_sub_i32 s9, 32, s1
-; VI-NEXT:    s_lshr_b32 s8, s7, s1
-; VI-NEXT:    s_lshl_b32 s5, s5, s9
-; VI-NEXT:    s_or_b32 s5, s5, s8
+; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    s_and_b32 s0, s0, 31
-; VI-NEXT:    v_mov_b32_e32 v0, s5
-; VI-NEXT:    s_sub_i32 s5, 32, s0
+; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; VI-NEXT:    s_lshr_b32 s1, s6, s0
-; VI-NEXT:    s_lshl_b32 s4, s4, s5
-; VI-NEXT:    s_or_b32 s1, s4, s1
-; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s6
+; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
+; VI-NEXT:    v_mov_b32_e32 v0, s6
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_alignbit_b32 v2, s4, v0, v2
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
-; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    v_mov_b32_e32 v3, s3
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
@@ -186,24 +174,18 @@ define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s7
+; GFX9-NEXT:    v_mov_b32_e32 v0, s7
 ; GFX9-NEXT:    s_and_b32 s1, s1, 31
-; GFX9-NEXT:    s_sub_i32 s9, 32, s1
-; GFX9-NEXT:    s_lshr_b32 s8, s7, s1
-; GFX9-NEXT:    s_lshl_b32 s5, s5, s9
-; GFX9-NEXT:    s_or_b32 s5, s5, s8
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX9-NEXT:    s_and_b32 s0, s0, 31
-; GFX9-NEXT:    v_mov_b32_e32 v0, s5
-; GFX9-NEXT:    s_sub_i32 s5, 32, s0
+; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; GFX9-NEXT:    s_lshr_b32 s1, s6, s0
-; GFX9-NEXT:    s_lshl_b32 s4, s4, s5
-; GFX9-NEXT:    s_or_b32 s1, s4, s1
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s1
-; GFX9-NEXT:    v_mov_b32_e32 v2, s6
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
+; GFX9-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_alignbit_b32 v2, s4, v0, v2
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
@@ -211,29 +193,22 @@ define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x,
 ;
 ; R600-LABEL: fshr_v2i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 18, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
+; R600-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     AND_INT T0.W, KC0[4].X, literal.x,
-; R600-NEXT:     AND_INT * T1.W, KC0[3].W, literal.x,
+; R600-NEXT:     AND_INT * T0.W, KC0[4].X, literal.x,
 ; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; R600-NEXT:     SUB_INT * T2.W, literal.x, PV.W,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHL T0.Z, KC0[3].X, PV.W,
-; R600-NEXT:     LSHR T2.W, KC0[3].Z, T0.W, BS:VEC_021/SCL_122
-; R600-NEXT:     SUB_INT * T3.W, literal.x, T1.W,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHL T0.Y, KC0[2].W, PS,
-; R600-NEXT:     LSHR T1.Z, KC0[3].Y, T1.W,
-; R600-NEXT:     OR_INT T2.W, PV.Z, PV.W,
-; R600-NEXT:     SETE_INT * T0.W, T0.W, 0.0,
-; R600-NEXT:     CNDE_INT T1.Y, PS, PV.W, KC0[3].Z,
-; R600-NEXT:     OR_INT T0.W, PV.Y, PV.Z,
-; R600-NEXT:     SETE_INT * T1.W, T1.W, 0.0,
-; R600-NEXT:     CNDE_INT T1.X, PS, PV.W, KC0[3].Y,
-; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT:     BIT_ALIGN_INT T1.W, KC0[3].X, KC0[3].Z, PV.W,
+; R600-NEXT:     SETE_INT * T0.W, PV.W, 0.0,
+; R600-NEXT:     CNDE_INT T0.Y, PS, PV.W, KC0[3].Z,
+; R600-NEXT:     AND_INT * T0.W, KC0[3].W, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     BIT_ALIGN_INT T1.W, KC0[2].W, KC0[3].Y, PV.W,
+; R600-NEXT:     SETE_INT * T0.W, PV.W, 0.0,
+; R600-NEXT:     CNDE_INT T0.X, PS, PV.W, KC0[3].Y,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 entry:
   %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
@@ -316,42 +291,30 @@ define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v1, s15
+; SI-NEXT:    v_mov_b32_e32 v0, s15
 ; SI-NEXT:    s_and_b32 s3, s3, 31
-; SI-NEXT:    s_sub_i32 s17, 32, s3
-; SI-NEXT:    s_lshr_b32 s16, s15, s3
-; SI-NEXT:    s_lshl_b32 s11, s11, s17
-; SI-NEXT:    s_or_b32 s11, s11, s16
-; SI-NEXT:    s_and_b32 s2, s2, 31
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    s_sub_i32 s11, 32, s2
+; SI-NEXT:    v_mov_b32_e32 v1, s3
+; SI-NEXT:    v_alignbit_b32 v1, s11, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
-; SI-NEXT:    s_lshr_b32 s3, s14, s2
-; SI-NEXT:    s_lshl_b32 s10, s10, s11
-; SI-NEXT:    s_or_b32 s3, s10, s3
-; SI-NEXT:    s_and_b32 s1, s1, 31
-; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s3
-; SI-NEXT:    s_sub_i32 s3, 32, s1
+; SI-NEXT:    s_and_b32 s2, s2, 31
+; SI-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc
+; SI-NEXT:    v_mov_b32_e32 v0, s14
+; SI-NEXT:    v_mov_b32_e32 v1, s2
+; SI-NEXT:    v_alignbit_b32 v1, s10, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; SI-NEXT:    s_lshr_b32 s2, s13, s1
-; SI-NEXT:    s_lshl_b32 s3, s9, s3
-; SI-NEXT:    v_mov_b32_e32 v1, s14
-; SI-NEXT:    s_or_b32 s2, s3, s2
+; SI-NEXT:    s_and_b32 s1, s1, 31
+; SI-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc
+; SI-NEXT:    v_mov_b32_e32 v0, s13
+; SI-NEXT:    v_mov_b32_e32 v1, s1
 ; SI-NEXT:    s_and_b32 s0, s0, 31
-; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s2
-; SI-NEXT:    s_sub_i32 s2, 32, s0
+; SI-NEXT:    v_alignbit_b32 v1, s9, v0, v1
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; SI-NEXT:    s_lshr_b32 s1, s12, s0
-; SI-NEXT:    s_lshl_b32 s2, s8, s2
-; SI-NEXT:    v_mov_b32_e32 v1, s13
-; SI-NEXT:    s_or_b32 s1, s2, s1
-; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v0, s1
-; SI-NEXT:    v_mov_b32_e32 v4, s12
+; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT:    v_mov_b32_e32 v0, s12
+; SI-NEXT:    v_mov_b32_e32 v4, s0
+; SI-NEXT:    v_alignbit_b32 v4, s8, v0, v4
 ; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
-; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
@@ -362,42 +325,30 @@ define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ; VI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v1, s11
+; VI-NEXT:    v_mov_b32_e32 v0, s11
 ; VI-NEXT:    s_and_b32 s3, s3, 31
-; VI-NEXT:    s_sub_i32 s15, 32, s3
-; VI-NEXT:    s_lshr_b32 s14, s11, s3
-; VI-NEXT:    s_lshl_b32 s7, s7, s15
-; VI-NEXT:    s_or_b32 s7, s7, s14
-; VI-NEXT:    s_and_b32 s2, s2, 31
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    s_sub_i32 s7, 32, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    v_alignbit_b32 v1, s7, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
-; VI-NEXT:    s_lshr_b32 s3, s10, s2
-; VI-NEXT:    s_lshl_b32 s6, s6, s7
-; VI-NEXT:    s_or_b32 s3, s6, s3
-; VI-NEXT:    s_and_b32 s1, s1, 31
-; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    s_sub_i32 s3, 32, s1
+; VI-NEXT:    s_and_b32 s2, s2, 31
+; VI-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc
+; VI-NEXT:    v_mov_b32_e32 v0, s10
+; VI-NEXT:    v_mov_b32_e32 v1, s2
+; VI-NEXT:    v_alignbit_b32 v1, s6, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; VI-NEXT:    s_lshr_b32 s2, s9, s1
-; VI-NEXT:    s_lshl_b32 s3, s5, s3
-; VI-NEXT:    v_mov_b32_e32 v1, s10
-; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_and_b32 s1, s1, 31
+; VI-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc
+; VI-NEXT:    v_mov_b32_e32 v0, s9
+; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    s_and_b32 s0, s0, 31
-; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s2
-; VI-NEXT:    s_sub_i32 s2, 32, s0
+; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; VI-NEXT:    s_lshr_b32 s1, s8, s0
-; VI-NEXT:    s_lshl_b32 s2, s4, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s9
-; VI-NEXT:    s_or_b32 s1, s2, s1
-; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s1
-; VI-NEXT:    v_mov_b32_e32 v4, s8
+; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
+; VI-NEXT:    v_mov_b32_e32 v0, s8
+; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    v_alignbit_b32 v4, s4, v0, v4
 ; VI-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
-; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, s12
 ; VI-NEXT:    v_mov_b32_e32 v5, s13
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
@@ -410,42 +361,30 @@ define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s11
+; GFX9-NEXT:    v_mov_b32_e32 v0, s11
 ; GFX9-NEXT:    s_and_b32 s3, s3, 31
-; GFX9-NEXT:    s_sub_i32 s15, 32, s3
-; GFX9-NEXT:    s_lshr_b32 s14, s11, s3
-; GFX9-NEXT:    s_lshl_b32 s7, s7, s15
-; GFX9-NEXT:    s_or_b32 s7, s7, s14
-; GFX9-NEXT:    s_and_b32 s2, s2, 31
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    s_sub_i32 s7, 32, s2
+; GFX9-NEXT:    v_mov_b32_e32 v1, s3
+; GFX9-NEXT:    v_alignbit_b32 v1, s7, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
-; GFX9-NEXT:    s_lshr_b32 s3, s10, s2
-; GFX9-NEXT:    s_lshl_b32 s6, s6, s7
-; GFX9-NEXT:    s_or_b32 s3, s6, s3
-; GFX9-NEXT:    s_and_b32 s1, s1, 31
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s3
-; GFX9-NEXT:    s_sub_i32 s3, 32, s1
+; GFX9-NEXT:    s_and_b32 s2, s2, 31
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc
+; GFX9-NEXT:    v_mov_b32_e32 v0, s10
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
+; GFX9-NEXT:    v_alignbit_b32 v1, s6, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX9-NEXT:    s_lshr_b32 s2, s9, s1
-; GFX9-NEXT:    s_lshl_b32 s3, s5, s3
-; GFX9-NEXT:    v_mov_b32_e32 v1, s10
-; GFX9-NEXT:    s_or_b32 s2, s3, s2
+; GFX9-NEXT:    s_and_b32 s1, s1, 31
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc
+; GFX9-NEXT:    v_mov_b32_e32 v0, s9
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX9-NEXT:    s_and_b32 s0, s0, 31
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s2
-; GFX9-NEXT:    s_sub_i32 s2, 32, s0
+; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s1, 0
-; GFX9-NEXT:    s_lshr_b32 s1, s8, s0
-; GFX9-NEXT:    s_lshl_b32 s2, s4, s2
-; GFX9-NEXT:    v_mov_b32_e32 v1, s9
-; GFX9-NEXT:    s_or_b32 s1, s2, s1
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s1
-; GFX9-NEXT:    v_mov_b32_e32 v4, s8
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
+; GFX9-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-NEXT:    v_mov_b32_e32 v4, s0
+; GFX9-NEXT:    v_alignbit_b32 v4, s4, v0, v4
 ; GFX9-NEXT:    v_cmp_eq_u32_e64 vcc, s0, 0
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s12
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s13
 ; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
@@ -453,44 +392,30 @@ define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x,
 ;
 ; R600-LABEL: fshr_v4i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 34, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; R600-NEXT:    ALU 20, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     AND_INT T0.W, KC0[5].Y, literal.x,
+; R600-NEXT:     AND_INT T0.W, KC0[5].Z, literal.x,
 ; R600-NEXT:     AND_INT * T1.W, KC0[6].X, literal.x,
 ; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; R600-NEXT:     SUB_INT * T2.W, literal.x, PV.W,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHL T0.Z, KC0[3].Y, PV.W,
-; R600-NEXT:     SUB_INT T2.W, literal.x, T1.W,
-; R600-NEXT:     AND_INT * T3.W, KC0[5].W, literal.y,
-; R600-NEXT:    32(4.484155e-44), 31(4.344025e-44)
-; R600-NEXT:     AND_INT T0.Y, KC0[5].Z, literal.x,
-; R600-NEXT:     SUB_INT T1.Z, literal.y, PS,
-; R600-NEXT:     LSHL * T2.W, KC0[4].X, PV.W,
-; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
-; R600-NEXT:     LSHR * T4.W, KC0[5].X, T1.W,
-; R600-NEXT:     OR_INT T0.X, T2.W, PV.W,
-; R600-NEXT:     SETE_INT T1.Y, T1.W, 0.0, BS:VEC_120/SCL_212
-; R600-NEXT:     LSHL T1.Z, KC0[3].W, T1.Z,
-; R600-NEXT:     LSHR T1.W, KC0[4].W, T3.W, BS:VEC_021/SCL_122
-; R600-NEXT:     SUB_INT * T2.W, literal.x, T0.Y,
-; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; R600-NEXT:     LSHL T1.X, KC0[3].Z, PS,
-; R600-NEXT:     LSHR T2.Y, KC0[4].Z, T0.Y,
-; R600-NEXT:     OR_INT T1.Z, PV.Z, PV.W,
-; R600-NEXT:     SETE_INT * T1.W, T3.W, 0.0,
-; R600-NEXT:     CNDE_INT * T2.W, T1.Y, T0.X, KC0[5].X,
-; R600-NEXT:     LSHR T1.Y, KC0[4].Y, T0.W,
-; R600-NEXT:     CNDE_INT T2.Z, T1.W, T1.Z, KC0[4].W,
-; R600-NEXT:     OR_INT T1.W, T1.X, T2.Y,
-; R600-NEXT:     SETE_INT * T3.W, T0.Y, 0.0,
-; R600-NEXT:     CNDE_INT T2.Y, PS, PV.W, KC0[4].Z,
-; R600-NEXT:     OR_INT T1.W, T0.Z, PV.Y,
+; R600-NEXT:     SETE_INT T0.Z, PS, 0.0,
+; R600-NEXT:     BIT_ALIGN_INT * T1.W, KC0[4].X, KC0[5].X, PS,
+; R600-NEXT:     AND_INT * T2.W, KC0[5].W, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     SETE_INT T1.Z, PV.W, 0.0,
+; R600-NEXT:     BIT_ALIGN_INT * T2.W, KC0[3].W, KC0[4].W, PV.W,
+; R600-NEXT:     CNDE_INT * T1.W, T0.Z, T1.W, KC0[5].X,
+; R600-NEXT:     CNDE_INT T1.Z, T1.Z, T2.W, KC0[4].W,
+; R600-NEXT:     BIT_ALIGN_INT T2.W, KC0[3].Z, KC0[4].Z, T0.W,
 ; R600-NEXT:     SETE_INT * T0.W, T0.W, 0.0,
-; R600-NEXT:     CNDE_INT T2.X, PS, PV.W, KC0[4].Y,
+; R600-NEXT:     CNDE_INT T1.Y, PS, PV.W, KC0[4].Z,
+; R600-NEXT:     AND_INT * T0.W, KC0[5].Y, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     BIT_ALIGN_INT T2.W, KC0[3].Y, KC0[4].Y, PV.W,
+; R600-NEXT:     SETE_INT * T0.W, PV.W, 0.0,
+; R600-NEXT:     CNDE_INT T1.X, PS, PV.W, KC0[4].Y,
 ; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call.ll b/llvm/test/CodeGen/AMDGPU/indirect-call.ll
new file mode 100644
index 0000000000000..5481246279972
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/indirect-call.ll
@@ -0,0 +1,201 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+@gv.fptr0 = external hidden unnamed_addr addrspace(4) constant void()*, align 4
+@gv.fptr1 = external hidden unnamed_addr addrspace(4) constant void(i32)*, align 4
+
+define amdgpu_kernel void @test_indirect_call_sgpr_ptr() {
+; GCN-LABEL: test_indirect_call_sgpr_ptr:
+; GCN:         .amd_kernel_code_t
+; GCN-NEXT:     amd_code_version_major = 1
+; GCN-NEXT:     amd_code_version_minor = 2
+; GCN-NEXT:     amd_machine_kind = 1
+; GCN-NEXT:     amd_machine_version_major = 7
+; GCN-NEXT:     amd_machine_version_minor = 0
+; GCN-NEXT:     amd_machine_version_stepping = 0
+; GCN-NEXT:     kernel_code_entry_byte_offset = 256
+; GCN-NEXT:     kernel_code_prefetch_byte_size = 0
+; GCN-NEXT:     granulated_workitem_vgpr_count = 7
+; GCN-NEXT:     granulated_wavefront_sgpr_count = 5
+; GCN-NEXT:     priority = 0
+; GCN-NEXT:     float_mode = 192
+; GCN-NEXT:     priv = 0
+; GCN-NEXT:     enable_dx10_clamp = 1
+; GCN-NEXT:     debug_mode = 0
+; GCN-NEXT:     enable_ieee_mode = 1
+; GCN-NEXT:     enable_wgp_mode = 0
+; GCN-NEXT:     enable_mem_ordered = 0
+; GCN-NEXT:     enable_fwd_progress = 0
+; GCN-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 1
+; GCN-NEXT:     user_sgpr_count = 14
+; GCN-NEXT:     enable_trap_handler = 0
+; GCN-NEXT:     enable_sgpr_workgroup_id_x = 1
+; GCN-NEXT:     enable_sgpr_workgroup_id_y = 1
+; GCN-NEXT:     enable_sgpr_workgroup_id_z = 1
+; GCN-NEXT:     enable_sgpr_workgroup_info = 0
+; GCN-NEXT:     enable_vgpr_workitem_id = 2
+; GCN-NEXT:     enable_exception_msb = 0
+; GCN-NEXT:     granulated_lds_size = 0
+; GCN-NEXT:     enable_exception = 0
+; GCN-NEXT:     enable_sgpr_private_segment_buffer = 1
+; GCN-NEXT:     enable_sgpr_dispatch_ptr = 1
+; GCN-NEXT:     enable_sgpr_queue_ptr = 1
+; GCN-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; GCN-NEXT:     enable_sgpr_dispatch_id = 1
+; GCN-NEXT:     enable_sgpr_flat_scratch_init = 1
+; GCN-NEXT:     enable_sgpr_private_segment_size = 0
+; GCN-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; GCN-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; GCN-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; GCN-NEXT:     enable_wavefront_size32 = 0
+; GCN-NEXT:     enable_ordered_append_gds = 0
+; GCN-NEXT:     private_element_size = 1
+; GCN-NEXT:     is_ptr64 = 1
+; GCN-NEXT:     is_dynamic_callstack = 1
+; GCN-NEXT:     is_debug_enabled = 0
+; GCN-NEXT:     is_xnack_enabled = 1
+; GCN-NEXT:     workitem_private_segment_byte_size = 16384
+; GCN-NEXT:     workgroup_group_segment_byte_size = 0
+; GCN-NEXT:     gds_segment_byte_size = 0
+; GCN-NEXT:     kernarg_segment_byte_size = 0
+; GCN-NEXT:     workgroup_fbarrier_count = 0
+; GCN-NEXT:     wavefront_sgpr_count = 48
+; GCN-NEXT:     workitem_vgpr_count = 32
+; GCN-NEXT:     reserved_vgpr_first = 0
+; GCN-NEXT:     reserved_vgpr_count = 0
+; GCN-NEXT:     reserved_sgpr_first = 0
+; GCN-NEXT:     reserved_sgpr_count = 0
+; GCN-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; GCN-NEXT:     debug_private_segment_buffer_sgpr = 0
+; GCN-NEXT:     kernarg_segment_alignment = 4
+; GCN-NEXT:     group_segment_alignment = 4
+; GCN-NEXT:     private_segment_alignment = 4
+; GCN-NEXT:     wavefront_size = 6
+; GCN-NEXT:     call_convention = -1
+; GCN-NEXT:     runtime_loader_kernel_symbol = 0
+; GCN-NEXT:    .end_amd_kernel_code_t
+; GCN-NEXT:  ; %bb.0:
+; GCN-NEXT:    s_mov_b32 s33, s17
+; GCN-NEXT:    s_mov_b32 s32, s33
+; GCN-NEXT:    s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT:    s_add_u32 s12, s12, s33
+; GCN-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, gv.fptr0@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, gv.fptr0@rel32@hi+4
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; GCN-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
+; GCN-NEXT:    v_or_b32_e32 v31, v0, v2
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; GCN-NEXT:    s_endpgm
+  %fptr = load void()*, void()* addrspace(4)* @gv.fptr0
+  call void %fptr()
+  ret void
+}
+
+define amdgpu_kernel void @test_indirect_call_sgpr_ptr_arg() {
+; GCN-LABEL: test_indirect_call_sgpr_ptr_arg:
+; GCN:         .amd_kernel_code_t
+; GCN-NEXT:     amd_code_version_major = 1
+; GCN-NEXT:     amd_code_version_minor = 2
+; GCN-NEXT:     amd_machine_kind = 1
+; GCN-NEXT:     amd_machine_version_major = 7
+; GCN-NEXT:     amd_machine_version_minor = 0
+; GCN-NEXT:     amd_machine_version_stepping = 0
+; GCN-NEXT:     kernel_code_entry_byte_offset = 256
+; GCN-NEXT:     kernel_code_prefetch_byte_size = 0
+; GCN-NEXT:     granulated_workitem_vgpr_count = 7
+; GCN-NEXT:     granulated_wavefront_sgpr_count = 5
+; GCN-NEXT:     priority = 0
+; GCN-NEXT:     float_mode = 192
+; GCN-NEXT:     priv = 0
+; GCN-NEXT:     enable_dx10_clamp = 1
+; GCN-NEXT:     debug_mode = 0
+; GCN-NEXT:     enable_ieee_mode = 1
+; GCN-NEXT:     enable_wgp_mode = 0
+; GCN-NEXT:     enable_mem_ordered = 0
+; GCN-NEXT:     enable_fwd_progress = 0
+; GCN-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 1
+; GCN-NEXT:     user_sgpr_count = 14
+; GCN-NEXT:     enable_trap_handler = 0
+; GCN-NEXT:     enable_sgpr_workgroup_id_x = 1
+; GCN-NEXT:     enable_sgpr_workgroup_id_y = 1
+; GCN-NEXT:     enable_sgpr_workgroup_id_z = 1
+; GCN-NEXT:     enable_sgpr_workgroup_info = 0
+; GCN-NEXT:     enable_vgpr_workitem_id = 2
+; GCN-NEXT:     enable_exception_msb = 0
+; GCN-NEXT:     granulated_lds_size = 0
+; GCN-NEXT:     enable_exception = 0
+; GCN-NEXT:     enable_sgpr_private_segment_buffer = 1
+; GCN-NEXT:     enable_sgpr_dispatch_ptr = 1
+; GCN-NEXT:     enable_sgpr_queue_ptr = 1
+; GCN-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; GCN-NEXT:     enable_sgpr_dispatch_id = 1
+; GCN-NEXT:     enable_sgpr_flat_scratch_init = 1
+; GCN-NEXT:     enable_sgpr_private_segment_size = 0
+; GCN-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; GCN-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; GCN-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; GCN-NEXT:     enable_wavefront_size32 = 0
+; GCN-NEXT:     enable_ordered_append_gds = 0
+; GCN-NEXT:     private_element_size = 1
+; GCN-NEXT:     is_ptr64 = 1
+; GCN-NEXT:     is_dynamic_callstack = 1
+; GCN-NEXT:     is_debug_enabled = 0
+; GCN-NEXT:     is_xnack_enabled = 1
+; GCN-NEXT:     workitem_private_segment_byte_size = 16384
+; GCN-NEXT:     workgroup_group_segment_byte_size = 0
+; GCN-NEXT:     gds_segment_byte_size = 0
+; GCN-NEXT:     kernarg_segment_byte_size = 0
+; GCN-NEXT:     workgroup_fbarrier_count = 0
+; GCN-NEXT:     wavefront_sgpr_count = 48
+; GCN-NEXT:     workitem_vgpr_count = 32
+; GCN-NEXT:     reserved_vgpr_first = 0
+; GCN-NEXT:     reserved_vgpr_count = 0
+; GCN-NEXT:     reserved_sgpr_first = 0
+; GCN-NEXT:     reserved_sgpr_count = 0
+; GCN-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; GCN-NEXT:     debug_private_segment_buffer_sgpr = 0
+; GCN-NEXT:     kernarg_segment_alignment = 4
+; GCN-NEXT:     group_segment_alignment = 4
+; GCN-NEXT:     private_segment_alignment = 4
+; GCN-NEXT:     wavefront_size = 6
+; GCN-NEXT:     call_convention = -1
+; GCN-NEXT:     runtime_loader_kernel_symbol = 0
+; GCN-NEXT:    .end_amd_kernel_code_t
+; GCN-NEXT:  ; %bb.0:
+; GCN-NEXT:    s_mov_b32 s33, s17
+; GCN-NEXT:    s_mov_b32 s32, s33
+; GCN-NEXT:    s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT:    s_add_u32 s12, s12, s33
+; GCN-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, gv.fptr1@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, gv.fptr1@rel32@hi+4
+; GCN-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
+; GCN-NEXT:    v_or_b32_e32 v31, v0, v2
+; GCN-NEXT:    v_mov_b32_e32 v0, 0x7b
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; GCN-NEXT:    s_endpgm
+  %fptr = load void(i32)*, void(i32)* addrspace(4)* @gv.fptr1
+  call void %fptr(i32 123)
+  ret void
+}
+
+; FIXME
+; define void @test_indirect_call_vgpr_ptr(void()* %fptr) {
+;   call void %fptr()
+;   ret void
+; }
+
+; define void @test_indirect_call_vgpr_ptr_arg(void(i32)* %fptr) {
+;   call void %fptr(i32 123)
+;   ret void
+; }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
index 60c6897b2adc2..efdbde63ce196 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
@@ -5,47 +5,39 @@
 define amdgpu_kernel void @round_f64(double addrspace(1)* %out, double %x) #0 {
 ; SI-LABEL: round_f64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s6, -1
-; SI-NEXT:    s_mov_b32 s11, 0x80000
-; SI-NEXT:    s_mov_b32 s10, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s3, 0xfffff
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    v_mov_b32_e32 v4, 0x3ff00000
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s4, s0
-; SI-NEXT:    s_bfe_u32 s0, s3, 0xb0014
-; SI-NEXT:    s_add_i32 s12, s0, 0xfffffc01
-; SI-NEXT:    s_mov_b32 s5, s1
-; SI-NEXT:    s_mov_b32 s1, 0xfffff
-; SI-NEXT:    s_mov_b32 s0, s6
-; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s12
-; SI-NEXT:    s_and_b64 s[8:9], s[2:3], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[10:11], s12
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v2, s3
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s2, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v2, s0
-; SI-NEXT:    v_and_b32_e32 v2, v1, v2
-; SI-NEXT:    v_not_b32_e32 v1, s1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    s_brev_b32 s0, -2
-; SI-NEXT:    v_mov_b32_e32 v3, s3
-; SI-NEXT:    v_bfi_b32 v1, s0, v1, v3
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
+; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
+; SI-NEXT:    s_add_i32 s5, s0, 0xfffffc01
+; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s5
+; SI-NEXT:    s_andn2_b64 s[2:3], s[10:11], s[0:1]
+; SI-NEXT:    s_and_b32 s0, s11, 0x80000000
+; SI-NEXT:    v_mov_b32_e32 v1, s0
+; SI-NEXT:    v_mov_b32_e32 v0, s3
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s5, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT:    v_mov_b32_e32 v1, s3
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
+; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s5, 51
+; SI-NEXT:    v_mov_b32_e32 v1, s11
 ; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v2, s2
+; SI-NEXT:    v_mov_b32_e32 v0, s2
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, s10
 ; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; SI-NEXT:    v_add_f64 v[2:3], s[10:11], -v[0:1]
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_mov_b32_e32 v5, s11
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; SI-NEXT:    v_bfi_b32 v4, s0, v4, v5
+; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0
+; SI-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s4, s8
+; SI-NEXT:    s_mov_b32 s5, s9
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
@@ -77,47 +69,42 @@ define amdgpu_kernel void @round_f64(double addrspace(1)* %out, double %x) #0 {
 define amdgpu_kernel void @v_round_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
 ; SI-LABEL: v_round_f64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    s_mov_b32 s6, 0
+; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
 ; SI-NEXT:    v_mov_b32_e32 v1, 0
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]
-; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
-; SI-NEXT:    s_movk_i32 s11, 0xfc01
-; SI-NEXT:    s_mov_b32 s9, 0xfffff
-; SI-NEXT:    s_mov_b32 s8, -1
+; SI-NEXT:    s_mov_b64 s[0:1], s[6:7]
+; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
+; SI-NEXT:    s_movk_i32 s9, 0xfc01
+; SI-NEXT:    s_mov_b32 s7, 0xfffff
+; SI-NEXT:    s_mov_b32 s6, -1
+; SI-NEXT:    s_brev_b32 s8, -2
 ; SI-NEXT:    v_mov_b32_e32 v8, 0x3ff00000
-; SI-NEXT:    s_brev_b32 s10, -2
-; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]
-; SI-NEXT:    s_mov_b32 s7, 0x80000
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    v_bfe_u32 v4, v3, 20, 11
-; SI-NEXT:    v_add_i32_e32 v10, vcc, s11, v4
-; SI-NEXT:    v_lshr_b64 v[4:5], s[8:9], v10
-; SI-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v10
-; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
-; SI-NEXT:    v_bfi_b32 v11, s10, v8, v3
-; SI-NEXT:    v_and_b32_e32 v9, v3, v5
-; SI-NEXT:    v_and_b32_e32 v8, v2, v4
-; SI-NEXT:    v_lshr_b64 v[6:7], s[6:7], v10
-; SI-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
+; SI-NEXT:    v_add_i32_e32 v6, vcc, s9, v4
+; SI-NEXT:    v_lshr_b64 v[4:5], s[6:7], v6
+; SI-NEXT:    v_and_b32_e32 v7, 0x80000000, v3
 ; SI-NEXT:    v_not_b32_e32 v4, v4
-; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
-; SI-NEXT:    v_add_i32_e32 v6, vcc, v2, v6
-; SI-NEXT:    v_addc_u32_e32 v7, vcc, v3, v7, vcc
 ; SI-NEXT:    v_not_b32_e32 v5, v5
-; SI-NEXT:    v_and_b32_e32 v5, v7, v5
-; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v10
-; SI-NEXT:    v_and_b32_e32 v4, v6, v4
-; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
+; SI-NEXT:    v_and_b32_e32 v5, v3, v5
+; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v6
+; SI-NEXT:    v_and_b32_e32 v4, v2, v4
+; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
 ; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
-; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 51, v10
-; SI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
+; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 51, v6
+; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc
+; SI-NEXT:    v_add_f64 v[6:7], v[2:3], -v[4:5]
+; SI-NEXT:    v_bfi_b32 v2, s8, v8, v3
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; SI-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0
+; SI-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
+; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: v_round_f64:
@@ -158,73 +145,60 @@ define amdgpu_kernel void @round_v2f64(<2 x double> addrspace(1)* %out, <2 x dou
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
 ; SI-NEXT:    s_mov_b32 s6, -1
-; SI-NEXT:    s_movk_i32 s18, 0xfc01
+; SI-NEXT:    s_movk_i32 s7, 0xfc01
 ; SI-NEXT:    s_mov_b32 s3, 0xfffff
 ; SI-NEXT:    s_mov_b32 s2, s6
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
-; SI-NEXT:    s_add_i32 s19, s0, s18
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s19
-; SI-NEXT:    s_and_b64 s[12:13], s[10:11], s[0:1]
-; SI-NEXT:    s_mov_b32 s15, 0x80000
-; SI-NEXT:    s_mov_b32 s14, 0
-; SI-NEXT:    s_lshr_b64 s[16:17], s[14:15], s19
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[12:13], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s16
-; SI-NEXT:    v_mov_b32_e32 v0, s17
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v2, s11
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v2, s0
-; SI-NEXT:    v_and_b32_e32 v1, v1, v2
-; SI-NEXT:    v_not_b32_e32 v2, s1
-; SI-NEXT:    v_mov_b32_e32 v4, 0x3ff00000
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s19, -1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v2
-; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
-; SI-NEXT:    s_brev_b32 s12, -2
-; SI-NEXT:    v_mov_b32_e32 v3, s11
-; SI-NEXT:    v_bfi_b32 v2, s12, v2, v3
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s19, 0
-; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; SI-NEXT:    v_mov_b32_e32 v2, s11
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s19, 51
-; SI-NEXT:    v_cndmask_b32_e64 v3, v0, v2, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
+; SI-NEXT:    s_add_i32 s14, s0, s7
+; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s14
+; SI-NEXT:    s_brev_b32 s15, 1
+; SI-NEXT:    s_andn2_b64 s[12:13], s[10:11], s[0:1]
+; SI-NEXT:    s_and_b32 s0, s11, s15
+; SI-NEXT:    v_mov_b32_e32 v1, s0
+; SI-NEXT:    v_mov_b32_e32 v0, s13
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s14, 0
+; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT:    v_mov_b32_e32 v1, s11
+; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s14, 51
+; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; SI-NEXT:    v_mov_b32_e32 v0, s12
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, s10
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; SI-NEXT:    v_add_f64 v[2:3], s[10:11], -v[0:1]
 ; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
-; SI-NEXT:    s_add_i32 s13, s0, s18
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s13
-; SI-NEXT:    s_and_b64 s[2:3], s[8:9], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[14:15], s13
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[2:3], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v5, s9
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v5, s0
-; SI-NEXT:    v_and_b32_e32 v5, v1, v5
-; SI-NEXT:    v_not_b32_e32 v1, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s13, -1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v1
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
-; SI-NEXT:    v_mov_b32_e32 v4, s9
-; SI-NEXT:    v_bfi_b32 v1, s12, v1, v4
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s13, 0
+; SI-NEXT:    s_add_i32 s7, s0, s7
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; SI-NEXT:    s_brev_b32 s10, -2
+; SI-NEXT:    v_mov_b32_e32 v6, 0x3ff00000
+; SI-NEXT:    v_mov_b32_e32 v4, s11
+; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s7
+; SI-NEXT:    v_bfi_b32 v4, s10, v6, v4
+; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0
+; SI-NEXT:    s_andn2_b64 s[2:3], s[8:9], s[0:1]
+; SI-NEXT:    s_and_b32 s0, s9, s15
+; SI-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]
+; SI-NEXT:    v_mov_b32_e32 v1, s0
+; SI-NEXT:    v_mov_b32_e32 v0, s3
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s7, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s7, 51
 ; SI-NEXT:    v_mov_b32_e32 v1, s9
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s13, 51
 ; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v5, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v0, s2
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
 ; SI-NEXT:    v_mov_b32_e32 v4, s8
-; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; SI-NEXT:    v_add_f64 v[4:5], s[8:9], -v[0:1]
+; SI-NEXT:    v_mov_b32_e32 v7, s9
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; SI-NEXT:    v_bfi_b32 v6, s10, v6, v7
+; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v6, vcc
+; SI-NEXT:    v_mov_b32_e32 v4, 0
+; SI-NEXT:    v_add_f64 v[0:1], v[0:1], v[4:5]
+; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
@@ -266,127 +240,102 @@ define amdgpu_kernel void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x dou
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; SI-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0x11
 ; SI-NEXT:    s_mov_b32 s6, -1
-; SI-NEXT:    s_movk_i32 s22, 0xfc01
+; SI-NEXT:    s_movk_i32 s18, 0xfc01
 ; SI-NEXT:    s_mov_b32 s3, 0xfffff
 ; SI-NEXT:    s_mov_b32 s2, s6
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
-; SI-NEXT:    s_add_i32 s23, s0, s22
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s23
-; SI-NEXT:    s_and_b64 s[16:17], s[10:11], s[0:1]
-; SI-NEXT:    s_mov_b32 s19, 0x80000
-; SI-NEXT:    s_mov_b32 s18, 0
-; SI-NEXT:    s_lshr_b64 s[20:21], s[18:19], s23
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[16:17], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s20
-; SI-NEXT:    v_mov_b32_e32 v0, s21
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v2, s11
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v2, s0
-; SI-NEXT:    v_and_b32_e32 v1, v1, v2
-; SI-NEXT:    v_not_b32_e32 v2, s1
-; SI-NEXT:    v_mov_b32_e32 v4, 0x3ff00000
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s23, -1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v2
-; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
-; SI-NEXT:    s_brev_b32 s20, -2
-; SI-NEXT:    v_mov_b32_e32 v3, s11
-; SI-NEXT:    v_bfi_b32 v2, s20, v2, v3
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s23, 0
-; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s23, 51
-; SI-NEXT:    v_cndmask_b32_e64 v3, v0, v3, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
-; SI-NEXT:    s_add_i32 s21, s0, s22
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s21
-; SI-NEXT:    s_and_b64 s[10:11], s[8:9], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[16:17], s[18:19], s21
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[10:11], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s16
+; SI-NEXT:    s_add_i32 s19, s0, s18
+; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s19
+; SI-NEXT:    s_brev_b32 s20, 1
+; SI-NEXT:    s_andn2_b64 s[16:17], s[10:11], s[0:1]
+; SI-NEXT:    s_and_b32 s0, s11, s20
+; SI-NEXT:    v_mov_b32_e32 v1, s0
 ; SI-NEXT:    v_mov_b32_e32 v0, s17
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v5, s9
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v5, s0
-; SI-NEXT:    v_and_b32_e32 v5, v1, v5
-; SI-NEXT:    v_not_b32_e32 v1, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s21, -1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v1
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
-; SI-NEXT:    v_mov_b32_e32 v6, s9
-; SI-NEXT:    v_bfi_b32 v1, s20, v1, v6
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s21, 0
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s19, 0
+; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT:    v_mov_b32_e32 v4, s11
+; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s19, 51
+; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v4, s[0:1]
+; SI-NEXT:    v_mov_b32_e32 v0, s16
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, s10
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; SI-NEXT:    v_add_f64 v[2:3], s[10:11], -v[0:1]
+; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
+; SI-NEXT:    s_add_i32 s17, s0, s18
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; SI-NEXT:    s_brev_b32 s16, -2
+; SI-NEXT:    v_mov_b32_e32 v12, 0x3ff00000
+; SI-NEXT:    v_bfi_b32 v4, s16, v12, v4
+; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s17
+; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0
+; SI-NEXT:    s_andn2_b64 s[10:11], s[8:9], s[0:1]
+; SI-NEXT:    s_and_b32 s0, s9, s20
+; SI-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]
+; SI-NEXT:    v_mov_b32_e32 v1, s0
+; SI-NEXT:    v_mov_b32_e32 v0, s11
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s17, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s21, 51
+; SI-NEXT:    v_mov_b32_e32 v6, s9
+; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s17, 51
 ; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v6, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v5, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v5, s8
-; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
+; SI-NEXT:    v_mov_b32_e32 v0, s10
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v4, s8
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; SI-NEXT:    v_add_f64 v[4:5], s[8:9], -v[0:1]
 ; SI-NEXT:    s_bfe_u32 s0, s15, 0xb0014
-; SI-NEXT:    s_add_i32 s16, s0, s22
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s16
-; SI-NEXT:    s_and_b64 s[8:9], s[14:15], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[18:19], s16
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v6, s10
-; SI-NEXT:    v_mov_b32_e32 v5, s11
-; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
-; SI-NEXT:    v_mov_b32_e32 v7, s15
-; SI-NEXT:    v_add_i32_e32 v6, vcc, s14, v6
-; SI-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; SI-NEXT:    v_not_b32_e32 v7, s0
-; SI-NEXT:    v_and_b32_e32 v6, v6, v7
-; SI-NEXT:    v_not_b32_e32 v7, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s16, -1
-; SI-NEXT:    v_and_b32_e32 v5, v5, v7
-; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v4, vcc
-; SI-NEXT:    v_mov_b32_e32 v8, s15
-; SI-NEXT:    v_bfi_b32 v7, s20, v7, v8
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s16, 0
-; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s16, 51
-; SI-NEXT:    v_cndmask_b32_e64 v7, v5, v8, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v5, v6, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v6, s14
-; SI-NEXT:    v_cndmask_b32_e64 v6, v5, v6, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s13, 0xb0014
-; SI-NEXT:    s_add_i32 s10, s0, s22
+; SI-NEXT:    s_add_i32 s10, s0, s18
 ; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s10
-; SI-NEXT:    s_and_b64 s[2:3], s[12:13], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[8:9], s[18:19], s10
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[2:3], 0
-; SI-NEXT:    v_mov_b32_e32 v8, s8
-; SI-NEXT:    v_mov_b32_e32 v5, s9
-; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
-; SI-NEXT:    v_mov_b32_e32 v9, s13
-; SI-NEXT:    v_add_i32_e32 v8, vcc, s12, v8
-; SI-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; SI-NEXT:    v_not_b32_e32 v9, s0
-; SI-NEXT:    v_and_b32_e32 v8, v8, v9
-; SI-NEXT:    v_not_b32_e32 v9, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s10, -1
-; SI-NEXT:    v_and_b32_e32 v5, v5, v9
-; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-NEXT:    v_mov_b32_e32 v9, s13
-; SI-NEXT:    v_bfi_b32 v4, s20, v4, v9
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; SI-NEXT:    s_andn2_b64 s[8:9], s[14:15], s[0:1]
+; SI-NEXT:    v_bfi_b32 v6, s16, v12, v6
+; SI-NEXT:    s_and_b32 s0, s15, s20
+; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v6, vcc
+; SI-NEXT:    v_mov_b32_e32 v5, s0
+; SI-NEXT:    v_mov_b32_e32 v4, s9
 ; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
-; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT:    v_mov_b32_e32 v10, s15
 ; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s10, 51
-; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v9, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v4, v8, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v8, s12
+; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v10, s[0:1]
+; SI-NEXT:    v_mov_b32_e32 v4, s8
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v6, s14
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
+; SI-NEXT:    v_add_f64 v[6:7], s[14:15], -v[4:5]
+; SI-NEXT:    s_bfe_u32 s0, s13, 0xb0014
+; SI-NEXT:    s_add_i32 s8, s0, s18
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s8
+; SI-NEXT:    v_bfi_b32 v10, s16, v12, v10
+; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v10, vcc
+; SI-NEXT:    v_mov_b32_e32 v6, 0
+; SI-NEXT:    s_andn2_b64 s[2:3], s[12:13], s[0:1]
+; SI-NEXT:    s_and_b32 s0, s13, s20
+; SI-NEXT:    v_add_f64 v[6:7], v[4:5], v[6:7]
+; SI-NEXT:    v_mov_b32_e32 v5, s0
+; SI-NEXT:    v_mov_b32_e32 v4, s3
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s8, 0
+; SI-NEXT:    v_mov_b32_e32 v13, s13
+; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s8, 51
+; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v13, s[0:1]
+; SI-NEXT:    v_mov_b32_e32 v4, s2
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v10, s12
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
+; SI-NEXT:    v_add_f64 v[10:11], s[12:13], -v[4:5]
+; SI-NEXT:    v_bfi_b32 v12, s16, v12, v13
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
+; SI-NEXT:    v_mov_b32_e32 v10, 0
+; SI-NEXT:    v_cndmask_b32_e32 v11, 0, v12, vcc
+; SI-NEXT:    v_mov_b32_e32 v8, 0
+; SI-NEXT:    v_add_f64 v[4:5], v[4:5], v[10:11]
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[0:1]
+; SI-NEXT:    v_add_f64 v[0:1], v[0:1], v[8:9]
 ; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
@@ -443,244 +392,196 @@ define amdgpu_kernel void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x dou
 define amdgpu_kernel void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 {
 ; SI-LABEL: round_v8f64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; SI-NEXT:    s_load_dwordx16 s[8:23], s[0:1], 0x19
 ; SI-NEXT:    s_mov_b32 s6, -1
-; SI-NEXT:    s_movk_i32 s30, 0xfc01
-; SI-NEXT:    s_mov_b32 s3, 0xfffff
-; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_movk_i32 s7, 0xfc01
+; SI-NEXT:    s_mov_b32 s5, 0xfffff
+; SI-NEXT:    s_mov_b32 s4, s6
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_bfe_u32 s0, s11, 0xb0014
-; SI-NEXT:    s_add_i32 s31, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s31
-; SI-NEXT:    s_and_b64 s[26:27], s[10:11], s[0:1]
-; SI-NEXT:    s_mov_b32 s25, 0x80000
-; SI-NEXT:    s_mov_b32 s24, 0
-; SI-NEXT:    s_lshr_b64 s[28:29], s[24:25], s31
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[26:27], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s28
-; SI-NEXT:    v_mov_b32_e32 v0, s29
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v2, s11
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s10, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v2, s0
-; SI-NEXT:    v_and_b32_e32 v1, v1, v2
-; SI-NEXT:    v_not_b32_e32 v2, s1
-; SI-NEXT:    v_mov_b32_e32 v12, 0x3ff00000
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s31, -1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v2
-; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v12, vcc
-; SI-NEXT:    s_brev_b32 s28, -2
-; SI-NEXT:    v_mov_b32_e32 v3, s11
-; SI-NEXT:    v_bfi_b32 v2, s28, v2, v3
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s31, 0
-; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s31, 51
-; SI-NEXT:    v_cndmask_b32_e64 v3, v0, v3, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s9, 0xb0014
-; SI-NEXT:    s_add_i32 s29, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s29
-; SI-NEXT:    s_and_b64 s[10:11], s[8:9], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[26:27], s[24:25], s29
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[10:11], 0
-; SI-NEXT:    v_mov_b32_e32 v1, s26
-; SI-NEXT:    v_mov_b32_e32 v0, s27
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT:    v_mov_b32_e32 v4, s9
-; SI-NEXT:    v_add_i32_e32 v1, vcc, s8, v1
-; SI-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; SI-NEXT:    v_not_b32_e32 v4, s0
-; SI-NEXT:    v_and_b32_e32 v4, v1, v4
-; SI-NEXT:    v_not_b32_e32 v1, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s29, -1
-; SI-NEXT:    v_and_b32_e32 v0, v0, v1
-; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v12, vcc
-; SI-NEXT:    v_mov_b32_e32 v5, s9
-; SI-NEXT:    v_bfi_b32 v1, s28, v1, v5
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s29, 0
-; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s29, 51
-; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v5, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v4, s8
-; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s15, 0xb0014
-; SI-NEXT:    s_add_i32 s26, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s26
-; SI-NEXT:    s_and_b64 s[8:9], s[14:15], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s26
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v5, s10
-; SI-NEXT:    v_mov_b32_e32 v4, s11
-; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-NEXT:    v_mov_b32_e32 v6, s15
-; SI-NEXT:    v_add_i32_e32 v5, vcc, s14, v5
-; SI-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
-; SI-NEXT:    v_not_b32_e32 v6, s0
-; SI-NEXT:    v_and_b32_e32 v5, v5, v6
-; SI-NEXT:    v_not_b32_e32 v6, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s26, -1
-; SI-NEXT:    v_and_b32_e32 v4, v4, v6
-; SI-NEXT:    v_cndmask_b32_e32 v6, 0, v12, vcc
-; SI-NEXT:    v_mov_b32_e32 v7, s15
-; SI-NEXT:    v_bfi_b32 v6, s28, v6, v7
+; SI-NEXT:    s_bfe_u32 s2, s11, 0xb0014
+; SI-NEXT:    s_add_i32 s26, s2, s7
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s26
+; SI-NEXT:    s_brev_b32 s27, 1
+; SI-NEXT:    s_andn2_b64 s[24:25], s[10:11], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s11, s27
+; SI-NEXT:    v_mov_b32_e32 v1, s2
+; SI-NEXT:    v_mov_b32_e32 v0, s25
 ; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s26, 0
-; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s26, 51
-; SI-NEXT:    v_cndmask_b32_e64 v7, v4, v7, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v4, v5, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v5, s14
-; SI-NEXT:    v_cndmask_b32_e64 v6, v4, v5, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s13, 0xb0014
-; SI-NEXT:    s_add_i32 s14, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s14
-; SI-NEXT:    s_and_b64 s[8:9], s[12:13], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s14
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v5, s10
+; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-NEXT:    v_mov_b32_e32 v4, s11
-; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
-; SI-NEXT:    v_mov_b32_e32 v8, s13
-; SI-NEXT:    v_add_i32_e32 v5, vcc, s12, v5
-; SI-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; SI-NEXT:    v_not_b32_e32 v8, s0
-; SI-NEXT:    v_and_b32_e32 v8, v5, v8
-; SI-NEXT:    v_not_b32_e32 v5, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s14, -1
-; SI-NEXT:    v_and_b32_e32 v4, v4, v5
-; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v12, vcc
-; SI-NEXT:    v_mov_b32_e32 v9, s13
-; SI-NEXT:    v_bfi_b32 v5, s28, v5, v9
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s14, 0
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s26, 51
+; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v4, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v0, s24
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, s10
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; SI-NEXT:    v_add_f64 v[2:3], s[10:11], -v[0:1]
+; SI-NEXT:    s_bfe_u32 s2, s9, 0xb0014
+; SI-NEXT:    s_add_i32 s25, s2, s7
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; SI-NEXT:    s_brev_b32 s24, -2
+; SI-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
+; SI-NEXT:    v_bfi_b32 v4, s24, v18, v4
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s25
+; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0
+; SI-NEXT:    s_andn2_b64 s[10:11], s[8:9], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s9, s27
+; SI-NEXT:    v_add_f64 v[2:3], v[0:1], v[2:3]
+; SI-NEXT:    v_mov_b32_e32 v1, s2
+; SI-NEXT:    v_mov_b32_e32 v0, s11
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s25, 0
+; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT:    v_mov_b32_e32 v6, s9
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s25, 51
+; SI-NEXT:    v_cndmask_b32_e64 v1, v0, v6, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v0, s10
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v4, s8
+; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[2:3]
+; SI-NEXT:    v_add_f64 v[4:5], s[8:9], -v[0:1]
+; SI-NEXT:    s_bfe_u32 s2, s15, 0xb0014
+; SI-NEXT:    s_add_i32 s10, s2, s7
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; SI-NEXT:    v_bfi_b32 v6, s24, v18, v6
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s10
+; SI-NEXT:    v_cndmask_b32_e32 v5, 0, v6, vcc
+; SI-NEXT:    v_mov_b32_e32 v4, 0
+; SI-NEXT:    s_andn2_b64 s[8:9], s[14:15], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s15, s27
+; SI-NEXT:    v_add_f64 v[0:1], v[0:1], v[4:5]
+; SI-NEXT:    v_mov_b32_e32 v5, s2
+; SI-NEXT:    v_mov_b32_e32 v4, s9
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s14, 51
-; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v9, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v4, v8, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v8, s15
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s10, 51
+; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v8, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v4, s8
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v6, s14
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[2:3]
+; SI-NEXT:    v_add_f64 v[6:7], s[14:15], -v[4:5]
+; SI-NEXT:    s_bfe_u32 s2, s13, 0xb0014
+; SI-NEXT:    s_add_i32 s10, s2, s7
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; SI-NEXT:    v_bfi_b32 v8, s24, v18, v8
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s10
+; SI-NEXT:    v_cndmask_b32_e32 v7, 0, v8, vcc
+; SI-NEXT:    v_mov_b32_e32 v6, 0
+; SI-NEXT:    s_andn2_b64 s[8:9], s[12:13], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s13, s27
+; SI-NEXT:    v_add_f64 v[6:7], v[4:5], v[6:7]
+; SI-NEXT:    v_mov_b32_e32 v5, s2
+; SI-NEXT:    v_mov_b32_e32 v4, s9
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
+; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT:    v_mov_b32_e32 v10, s13
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s10, 51
+; SI-NEXT:    v_cndmask_b32_e64 v5, v4, v10, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v4, s8
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
 ; SI-NEXT:    v_mov_b32_e32 v8, s12
-; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s19, 0xb0014
-; SI-NEXT:    s_add_i32 s12, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s12
-; SI-NEXT:    s_and_b64 s[8:9], s[18:19], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s12
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v9, s10
-; SI-NEXT:    v_mov_b32_e32 v8, s11
-; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
-; SI-NEXT:    v_mov_b32_e32 v10, s19
-; SI-NEXT:    v_add_i32_e32 v9, vcc, s18, v9
-; SI-NEXT:    v_addc_u32_e32 v8, vcc, v10, v8, vcc
-; SI-NEXT:    v_not_b32_e32 v10, s0
-; SI-NEXT:    v_and_b32_e32 v9, v9, v10
-; SI-NEXT:    v_not_b32_e32 v10, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
-; SI-NEXT:    v_and_b32_e32 v8, v8, v10
-; SI-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
-; SI-NEXT:    v_mov_b32_e32 v11, s19
-; SI-NEXT:    v_bfi_b32 v10, s28, v10, v11
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
-; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
-; SI-NEXT:    v_cndmask_b32_e64 v11, v8, v11, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v8, v9, 0, vcc
+; SI-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[2:3]
+; SI-NEXT:    v_add_f64 v[8:9], s[12:13], -v[4:5]
+; SI-NEXT:    s_bfe_u32 s2, s19, 0xb0014
+; SI-NEXT:    s_add_i32 s10, s2, s7
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5
+; SI-NEXT:    v_bfi_b32 v10, s24, v18, v10
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s10
+; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v10, vcc
+; SI-NEXT:    v_mov_b32_e32 v8, 0
+; SI-NEXT:    s_andn2_b64 s[8:9], s[18:19], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s19, s27
+; SI-NEXT:    v_add_f64 v[4:5], v[4:5], v[8:9]
+; SI-NEXT:    v_mov_b32_e32 v9, s2
+; SI-NEXT:    v_mov_b32_e32 v8, s9
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
+; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; SI-NEXT:    v_mov_b32_e32 v19, s19
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s10, 51
+; SI-NEXT:    v_cndmask_b32_e64 v13, v8, v19, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v8, s8
+; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, vcc
 ; SI-NEXT:    v_mov_b32_e32 v9, s18
-; SI-NEXT:    v_cndmask_b32_e64 v10, v8, v9, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s17, 0xb0014
-; SI-NEXT:    s_add_i32 s12, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s12
-; SI-NEXT:    s_and_b64 s[8:9], s[16:17], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s12
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v9, s10
+; SI-NEXT:    v_cndmask_b32_e64 v12, v8, v9, s[2:3]
+; SI-NEXT:    s_bfe_u32 s2, s17, 0xb0014
+; SI-NEXT:    s_add_i32 s12, s2, s7
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s12
+; SI-NEXT:    s_andn2_b64 s[8:9], s[16:17], s[2:3]
+; SI-NEXT:    s_bfe_u32 s2, s23, 0xb0014
+; SI-NEXT:    s_add_i32 s14, s2, s7
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s14
+; SI-NEXT:    s_andn2_b64 s[10:11], s[22:23], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s23, s27
+; SI-NEXT:    v_mov_b32_e32 v9, s2
 ; SI-NEXT:    v_mov_b32_e32 v8, s11
-; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
-; SI-NEXT:    v_mov_b32_e32 v13, s17
-; SI-NEXT:    v_add_i32_e32 v9, vcc, s16, v9
-; SI-NEXT:    v_addc_u32_e32 v8, vcc, v13, v8, vcc
-; SI-NEXT:    v_not_b32_e32 v13, s0
-; SI-NEXT:    v_and_b32_e32 v13, v9, v13
-; SI-NEXT:    v_not_b32_e32 v9, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
-; SI-NEXT:    v_and_b32_e32 v8, v8, v9
-; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v12, vcc
-; SI-NEXT:    v_mov_b32_e32 v14, s17
-; SI-NEXT:    v_bfi_b32 v9, s28, v9, v14
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s14, 0
 ; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
-; SI-NEXT:    v_cndmask_b32_e64 v9, v8, v14, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v8, v13, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v13, s16
-; SI-NEXT:    v_cndmask_b32_e64 v8, v8, v13, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s23, 0xb0014
-; SI-NEXT:    s_add_i32 s12, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s12
-; SI-NEXT:    s_and_b64 s[8:9], s[22:23], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[10:11], s[24:25], s12
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[8:9], 0
-; SI-NEXT:    v_mov_b32_e32 v14, s10
-; SI-NEXT:    v_mov_b32_e32 v13, s11
-; SI-NEXT:    v_cndmask_b32_e32 v14, 0, v14, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
-; SI-NEXT:    v_mov_b32_e32 v15, s23
-; SI-NEXT:    v_add_i32_e32 v14, vcc, s22, v14
-; SI-NEXT:    v_addc_u32_e32 v13, vcc, v15, v13, vcc
-; SI-NEXT:    v_not_b32_e32 v15, s0
-; SI-NEXT:    v_and_b32_e32 v14, v14, v15
-; SI-NEXT:    v_not_b32_e32 v15, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s12, -1
-; SI-NEXT:    v_and_b32_e32 v13, v13, v15
-; SI-NEXT:    v_cndmask_b32_e32 v15, 0, v12, vcc
 ; SI-NEXT:    v_mov_b32_e32 v16, s23
-; SI-NEXT:    v_bfi_b32 v15, s28, v15, v16
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
-; SI-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s12, 51
-; SI-NEXT:    v_cndmask_b32_e64 v15, v13, v16, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v13, v14, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v14, s22
-; SI-NEXT:    v_cndmask_b32_e64 v14, v13, v14, s[0:1]
-; SI-NEXT:    s_bfe_u32 s0, s21, 0xb0014
-; SI-NEXT:    s_add_i32 s10, s0, s30
-; SI-NEXT:    s_lshr_b64 s[0:1], s[2:3], s10
-; SI-NEXT:    s_and_b64 s[2:3], s[20:21], s[0:1]
-; SI-NEXT:    s_lshr_b64 s[8:9], s[24:25], s10
-; SI-NEXT:    v_cmp_ne_u64_e64 vcc, s[2:3], 0
-; SI-NEXT:    v_mov_b32_e32 v16, s8
-; SI-NEXT:    v_mov_b32_e32 v13, s9
-; SI-NEXT:    v_cndmask_b32_e32 v16, 0, v16, vcc
-; SI-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
-; SI-NEXT:    v_mov_b32_e32 v17, s21
-; SI-NEXT:    v_add_i32_e32 v16, vcc, s20, v16
-; SI-NEXT:    v_addc_u32_e32 v13, vcc, v17, v13, vcc
-; SI-NEXT:    v_not_b32_e32 v17, s0
-; SI-NEXT:    v_and_b32_e32 v16, v16, v17
-; SI-NEXT:    v_not_b32_e32 v17, s1
-; SI-NEXT:    v_cmp_eq_u32_e64 vcc, s10, -1
-; SI-NEXT:    v_and_b32_e32 v13, v13, v17
-; SI-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s14, 51
+; SI-NEXT:    v_cndmask_b32_e64 v9, v8, v16, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v8, s10
+; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v10, s22
+; SI-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[2:3]
+; SI-NEXT:    s_bfe_u32 s2, s21, 0xb0014
+; SI-NEXT:    s_add_i32 s7, s2, s7
+; SI-NEXT:    s_lshr_b64 s[2:3], s[4:5], s7
+; SI-NEXT:    s_andn2_b64 s[4:5], s[20:21], s[2:3]
+; SI-NEXT:    s_and_b32 s2, s21, s27
+; SI-NEXT:    v_mov_b32_e32 v11, s2
+; SI-NEXT:    v_mov_b32_e32 v10, s5
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s7, 0
+; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s7, 51
 ; SI-NEXT:    v_mov_b32_e32 v17, s21
-; SI-NEXT:    v_bfi_b32 v12, s28, v12, v17
-; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s10, 0
-; SI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
-; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], s10, 51
-; SI-NEXT:    v_cndmask_b32_e64 v13, v12, v17, s[0:1]
-; SI-NEXT:    v_cndmask_b32_e64 v12, v16, 0, vcc
-; SI-NEXT:    v_mov_b32_e32 v16, s20
+; SI-NEXT:    v_cndmask_b32_e64 v15, v10, v17, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v10, s4
+; SI-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v11, s20
+; SI-NEXT:    v_cndmask_b32_e64 v14, v10, v11, s[2:3]
+; SI-NEXT:    v_add_f64 v[10:11], s[20:21], -v[14:15]
+; SI-NEXT:    v_bfi_b32 v16, s24, v18, v16
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
+; SI-NEXT:    v_add_f64 v[10:11], s[22:23], -v[8:9]
+; SI-NEXT:    v_bfi_b32 v17, s24, v18, v17
+; SI-NEXT:    v_cmp_ge_f64_e64 s[2:3], |v[10:11]|, 0.5
+; SI-NEXT:    v_mov_b32_e32 v10, 0
+; SI-NEXT:    v_cndmask_b32_e64 v11, 0, v16, s[2:3]
+; SI-NEXT:    v_add_f64 v[10:11], v[8:9], v[10:11]
+; SI-NEXT:    v_cndmask_b32_e32 v9, 0, v17, vcc
+; SI-NEXT:    v_mov_b32_e32 v8, 0
+; SI-NEXT:    s_and_b32 s13, s17, s27
+; SI-NEXT:    v_add_f64 v[8:9], v[14:15], v[8:9]
+; SI-NEXT:    v_mov_b32_e32 v14, s9
+; SI-NEXT:    v_mov_b32_e32 v15, s13
+; SI-NEXT:    v_cmp_lt_i32_e64 vcc, s12, 0
+; SI-NEXT:    v_cndmask_b32_e32 v14, v14, v15, vcc
+; SI-NEXT:    v_mov_b32_e32 v15, s17
+; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], s12, 51
+; SI-NEXT:    v_cndmask_b32_e64 v17, v14, v15, s[2:3]
+; SI-NEXT:    v_mov_b32_e32 v14, s8
+; SI-NEXT:    v_cndmask_b32_e64 v14, v14, 0, vcc
+; SI-NEXT:    v_mov_b32_e32 v16, s16
+; SI-NEXT:    v_cndmask_b32_e64 v16, v14, v16, s[2:3]
+; SI-NEXT:    v_bfi_b32 v19, s24, v18, v19
+; SI-NEXT:    v_bfi_b32 v18, s24, v18, v15
+; SI-NEXT:    v_add_f64 v[14:15], s[16:17], -v[16:17]
+; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT:    v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
+; SI-NEXT:    v_add_f64 v[14:15], s[18:19], -v[12:13]
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_cndmask_b32_e64 v12, v12, v16, s[0:1]
-; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:48
-; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32
+; SI-NEXT:    v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
+; SI-NEXT:    v_mov_b32_e32 v14, 0
+; SI-NEXT:    v_cndmask_b32_e64 v15, 0, v19, s[0:1]
+; SI-NEXT:    v_add_f64 v[14:15], v[12:13], v[14:15]
+; SI-NEXT:    v_cndmask_b32_e32 v13, 0, v18, vcc
+; SI-NEXT:    v_mov_b32_e32 v12, 0
+; SI-NEXT:    v_add_f64 v[12:13], v[16:17], v[12:13]
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
+; SI-NEXT:    buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
 ; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
index 04a530d58a424..29206d2f5cf8c 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
@@ -24,9 +24,9 @@ define amdgpu_kernel void @min_size_large_static_memcpy_caller0(i8 addrspace(1)*
 ; OPT:       load-store-loop:
 ; OPT-NEXT:    [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP4:%.*]], [[LOAD_STORE_LOOP]] ]
 ; OPT-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    [[TMP2:%.*]] = load i8, i8 addrspace(1)* [[TMP1]]
+; OPT-NEXT:    [[TMP2:%.*]] = load i8, i8 addrspace(1)* [[TMP1]], align 1
 ; OPT-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    store i8 [[TMP2]], i8 addrspace(1)* [[TMP3]]
+; OPT-NEXT:    store i8 [[TMP2]], i8 addrspace(1)* [[TMP3]], align 1
 ; OPT-NEXT:    [[TMP4]] = add i64 [[LOOP_INDEX]], 1
 ; OPT-NEXT:    [[TMP5:%.*]] = icmp ult i64 [[TMP4]], 1025
 ; OPT-NEXT:    br i1 [[TMP5]], label [[LOAD_STORE_LOOP]], label [[MEMCPY_SPLIT:%.*]]
@@ -57,9 +57,9 @@ define amdgpu_kernel void @min_size_large_static_memmove_caller0(i8 addrspace(1)
 ; OPT-NEXT:    [[TMP1:%.*]] = phi i64 [ [[INDEX_PTR:%.*]], [[COPY_BACKWARDS_LOOP]] ], [ 1025, [[COPY_BACKWARDS]] ]
 ; OPT-NEXT:    [[INDEX_PTR]] = sub i64 [[TMP1]], 1
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC]], i64 [[INDEX_PTR]]
-; OPT-NEXT:    [[ELEMENT:%.*]] = load i8, i8 addrspace(1)* [[TMP2]]
+; OPT-NEXT:    [[ELEMENT:%.*]] = load i8, i8 addrspace(1)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST]], i64 [[INDEX_PTR]]
-; OPT-NEXT:    store i8 [[ELEMENT]], i8 addrspace(1)* [[TMP3]]
+; OPT-NEXT:    store i8 [[ELEMENT]], i8 addrspace(1)* [[TMP3]], align 1
 ; OPT-NEXT:    [[TMP4:%.*]] = icmp eq i64 [[INDEX_PTR]], 0
 ; OPT-NEXT:    br i1 [[TMP4]], label [[MEMMOVE_DONE]], label [[COPY_BACKWARDS_LOOP]]
 ; OPT:       copy_forward:
@@ -67,9 +67,9 @@ define amdgpu_kernel void @min_size_large_static_memmove_caller0(i8 addrspace(1)
 ; OPT:       copy_forward_loop:
 ; OPT-NEXT:    [[INDEX_PTR1:%.*]] = phi i64 [ [[INDEX_INCREMENT:%.*]], [[COPY_FORWARD_LOOP]] ], [ 0, [[COPY_FORWARD]] ]
 ; OPT-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC]], i64 [[INDEX_PTR1]]
-; OPT-NEXT:    [[ELEMENT2:%.*]] = load i8, i8 addrspace(1)* [[TMP5]]
+; OPT-NEXT:    [[ELEMENT2:%.*]] = load i8, i8 addrspace(1)* [[TMP5]], align 1
 ; OPT-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST]], i64 [[INDEX_PTR1]]
-; OPT-NEXT:    store i8 [[ELEMENT2]], i8 addrspace(1)* [[TMP6]]
+; OPT-NEXT:    store i8 [[ELEMENT2]], i8 addrspace(1)* [[TMP6]], align 1
 ; OPT-NEXT:    [[INDEX_INCREMENT]] = add i64 [[INDEX_PTR1]], 1
 ; OPT-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_INCREMENT]], 1025
 ; OPT-NEXT:    br i1 [[TMP7]], label [[MEMMOVE_DONE]], label [[COPY_FORWARD_LOOP]]
@@ -95,7 +95,7 @@ define amdgpu_kernel void @min_size_large_static_memset_caller0(i8 addrspace(1)*
 ; OPT:       loadstoreloop:
 ; OPT-NEXT:    [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
-; OPT-NEXT:    store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]]
+; OPT-NEXT:    store i8 [[VAL:%.*]], i8 addrspace(1)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP3]] = add i64 [[TMP1]], 1
 ; OPT-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 1025
 ; OPT-NEXT:    br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
@@ -113,9 +113,9 @@ define amdgpu_kernel void @variable_memcpy_caller0(i8 addrspace(1)* %dst, i8 add
 ; OPT:       loop-memcpy-expansion:
 ; OPT-NEXT:    [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[LOOP_MEMCPY_EXPANSION]] ]
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]]
+; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]]
+; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]], align 1
 ; OPT-NEXT:    [[TMP5]] = add i64 [[LOOP_INDEX]], 1
 ; OPT-NEXT:    [[TMP6:%.*]] = icmp ult i64 [[TMP5]], [[N]]
 ; OPT-NEXT:    br i1 [[TMP6]], label [[LOOP_MEMCPY_EXPANSION]], label [[POST_LOOP_MEMCPY_EXPANSION]]
@@ -133,9 +133,9 @@ define amdgpu_kernel void @variable_memcpy_caller1(i8 addrspace(1)* %dst, i8 add
 ; OPT:       loop-memcpy-expansion:
 ; OPT-NEXT:    [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[LOOP_MEMCPY_EXPANSION]] ]
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]]
+; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]]
+; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]], align 1
 ; OPT-NEXT:    [[TMP5]] = add i64 [[LOOP_INDEX]], 1
 ; OPT-NEXT:    [[TMP6:%.*]] = icmp ult i64 [[TMP5]], [[N]]
 ; OPT-NEXT:    br i1 [[TMP6]], label [[LOOP_MEMCPY_EXPANSION]], label [[POST_LOOP_MEMCPY_EXPANSION]]
@@ -153,9 +153,9 @@ define amdgpu_kernel void @memcpy_multi_use_one_function(i8 addrspace(1)* %dst0,
 ; OPT:       loop-memcpy-expansion2:
 ; OPT-NEXT:    [[LOOP_INDEX3:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[LOOP_MEMCPY_EXPANSION2]] ]
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC:%.*]], i64 [[LOOP_INDEX3]]
-; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]]
+; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST0:%.*]], i64 [[LOOP_INDEX3]]
-; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]]
+; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]], align 1
 ; OPT-NEXT:    [[TMP5]] = add i64 [[LOOP_INDEX3]], 1
 ; OPT-NEXT:    [[TMP6:%.*]] = icmp ult i64 [[TMP5]], [[N]]
 ; OPT-NEXT:    br i1 [[TMP6]], label [[LOOP_MEMCPY_EXPANSION2]], label [[POST_LOOP_MEMCPY_EXPANSION1]]
@@ -165,9 +165,9 @@ define amdgpu_kernel void @memcpy_multi_use_one_function(i8 addrspace(1)* %dst0,
 ; OPT:       loop-memcpy-expansion:
 ; OPT-NEXT:    [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[POST_LOOP_MEMCPY_EXPANSION1]] ], [ [[TMP11:%.*]], [[LOOP_MEMCPY_EXPANSION]] ]
 ; OPT-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    [[TMP9:%.*]] = load i8, i8 addrspace(1)* [[TMP8]]
+; OPT-NEXT:    [[TMP9:%.*]] = load i8, i8 addrspace(1)* [[TMP8]], align 1
 ; OPT-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST1:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    store i8 [[TMP9]], i8 addrspace(1)* [[TMP10]]
+; OPT-NEXT:    store i8 [[TMP9]], i8 addrspace(1)* [[TMP10]], align 1
 ; OPT-NEXT:    [[TMP11]] = add i64 [[LOOP_INDEX]], 1
 ; OPT-NEXT:    [[TMP12:%.*]] = icmp ult i64 [[TMP11]], [[M]]
 ; OPT-NEXT:    br i1 [[TMP12]], label [[LOOP_MEMCPY_EXPANSION]], label [[POST_LOOP_MEMCPY_EXPANSION]]
@@ -186,9 +186,9 @@ define amdgpu_kernel void @memcpy_alt_type(i8 addrspace(1)* %dst, i8 addrspace(3
 ; OPT:       loop-memcpy-expansion:
 ; OPT-NEXT:    [[LOOP_INDEX:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[LOOP_MEMCPY_EXPANSION]] ]
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(3)* [[SRC:%.*]], i32 [[LOOP_INDEX]]
-; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(3)* [[TMP2]]
+; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(3)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i32 [[LOOP_INDEX]]
-; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]]
+; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]], align 1
 ; OPT-NEXT:    [[TMP5]] = add i32 [[LOOP_INDEX]], 1
 ; OPT-NEXT:    [[TMP6:%.*]] = icmp ult i32 [[TMP5]], [[N]]
 ; OPT-NEXT:    br i1 [[TMP6]], label [[LOOP_MEMCPY_EXPANSION]], label [[POST_LOOP_MEMCPY_EXPANSION]]
@@ -207,9 +207,9 @@ define amdgpu_kernel void @memcpy_multi_use_one_function_keep_small(i8 addrspace
 ; OPT:       loop-memcpy-expansion:
 ; OPT-NEXT:    [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[LOOP_MEMCPY_EXPANSION]] ]
 ; OPT-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[SRC:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]]
+; OPT-NEXT:    [[TMP3:%.*]] = load i8, i8 addrspace(1)* [[TMP2]], align 1
 ; OPT-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST0:%.*]], i64 [[LOOP_INDEX]]
-; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]]
+; OPT-NEXT:    store i8 [[TMP3]], i8 addrspace(1)* [[TMP4]], align 1
 ; OPT-NEXT:    [[TMP5]] = add i64 [[LOOP_INDEX]], 1
 ; OPT-NEXT:    [[TMP6:%.*]] = icmp ult i64 [[TMP5]], [[N]]
 ; OPT-NEXT:    br i1 [[TMP6]], label [[LOOP_MEMCPY_EXPANSION]], label [[POST_LOOP_MEMCPY_EXPANSION]]
diff --git a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
index fafc38dbc78df..c09d18e104f79 100644
--- a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
+++ b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
@@ -719,6 +719,46 @@ bb5:                                              ; preds = %bb3
   unreachable
 }
 
+; Test that there is an extra export inserted after the normal export,
+; if the normal export is inside a uniformly reached block and there is
+; an infinite loop in the pixel shader.
+
+; IR-LABEL: @uniformly_reached_export
+; IR-NEXT: .entry:
+; IR: br i1 [[CND:%.*]], label %[[EXP:.*]], label %[[FLOW:.*]]
+
+; IR: [[FLOW]]:
+; IR-NEXT: phi
+; IR-NEXT: br i1 [[CND2:%.*]], label %[[PREHEADER:.*]], label %[[FLOW2:.*]]
+
+; IR: [[FLOW2]]:
+; IR-NEXT: br label %UnifiedReturnBlock
+
+; IR: [[EXP]]:
+; IR-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> <half 0xH3C00, half 0xH0000>, <2 x half> <half 0xH0000, half 0xH3C00>, i1 immarg false, i1 immarg true)
+; IR-NEXT: br label %[[FLOW]]
+
+; IR: UnifiedReturnBlock:
+; IR-NEXT: call void @llvm.amdgcn.exp.f32(i32 9, i32 0, float undef, float undef, float undef, float undef, i1 true, i1 true)
+; IR-NEXT: ret void
+
+define amdgpu_ps void @uniformly_reached_export(float inreg %tmp25) {
+.entry:
+  %tmp26 = fcmp olt float %tmp25, 0.000000e+00
+  br i1 %tmp26, label %.preheader.1, label %bb27
+
+.preheader.1:                                     ; preds = %.entry
+  br label %bb
+
+bb:                                               ; preds = %bb, %.preheader.1
+  br label %bb
+
+bb27:                                             ; preds = %.entry
+  call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> <half 0xH3C00, half 0xH0000>, <2 x half> <half 0xH0000, half 0xH3C00>, i1 immarg true, i1 immarg true)
+  ret void
+}
+
+declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) #0
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/nop-data.ll b/llvm/test/CodeGen/AMDGPU/nop-data.ll
index 0635c76cd858a..7b6853acce285 100644
--- a/llvm/test/CodeGen/AMDGPU/nop-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/nop-data.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - --mcpu=fiji | FileCheck %s
 
 ; CHECK: <kernel0>:
 ; CHECK-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/s_code_end.ll b/llvm/test/CodeGen/AMDGPU/s_code_end.ll
index 47ded0ad8c439..80f49427f56e3 100644
--- a/llvm/test/CodeGen/AMDGPU/s_code_end.ll
+++ b/llvm/test/CodeGen/AMDGPU/s_code_end.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10END,GFX10END-ASM %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10END,GFX10END-OBJ %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx1010 -d - | FileCheck --check-prefixes=GCN,GCN-OBJ,GFX10END,GFX10END-OBJ %s
 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10END,GFX10END-ASM %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10NOEND,GFX10NOEND-ASM %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10NOEND,GFX10NOEND-OBJ %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx1010 -d - | FileCheck --check-prefixes=GCN,GCN-OBJ,GFX10NOEND,GFX10NOEND-OBJ %s
 
 ; GCN:            a_kernel1{{>?}}:
 ; GCN:                    s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll b/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
new file mode 100755
index 0000000000000..6ce316d79d4c4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
+
+define amdgpu_kernel void @sext_i16_to_i32_uniform(i32 addrspace(1)* %out, i16 %a, i32 %b) {
+; GCN-LABEL: sext_i16_to_i32_uniform:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_sext_i32_i16 s0, s0
+; GCN-NEXT:    s_add_i32 s0, s1, s0
+; GCN-NEXT:    v_mov_b32_e32 v0, s0
+; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GCN-NEXT:    s_endpgm
+  %sext = sext i16 %a to i32
+  %res = add i32 %b, %sext
+  store i32 %res, i32 addrspace(1)* %out
+  ret void
+}
+
+
+define amdgpu_kernel void @sext_i16_to_i64_uniform(i64 addrspace(1)* %out, i16 %a, i64 %b) {
+; GCN-LABEL: sext_i16_to_i64_uniform:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-NEXT:    s_add_u32 s0, s0, s2
+; GCN-NEXT:    s_addc_u32 s1, s1, s3
+; GCN-NEXT:    v_mov_b32_e32 v0, s0
+; GCN-NEXT:    v_mov_b32_e32 v1, s1
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    s_endpgm
+  %sext = sext i16 %a to i64
+  %res = add i64 %b, %sext
+  store i64 %res, i64 addrspace(1)* %out
+  ret void
+}
+
+define amdgpu_kernel void @sext_i16_to_i32_divergent(i32 addrspace(1)* %out, i16 %a, i32 %b) {
+; GCN-LABEL: sext_i16_to_i32_divergent:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GCN-NEXT:    s_endpgm
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %tid.truncated = trunc i32 %tid to i16
+  %divergent.a = add i16 %a, %tid.truncated
+  %sext = sext i16 %divergent.a to i32
+  store i32 %sext, i32 addrspace(1)* %out
+  ret void
+}
+
+
+define amdgpu_kernel void @sext_i16_to_i64_divergent(i64 addrspace(1)* %out, i16 %a, i64 %b) {
+; GCN-LABEL: sext_i16_to_i64_divergent:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    s_endpgm
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %tid.truncated = trunc i32 %tid to i16
+  %divergent.a = add i16 %a, %tid.truncated
+  %sext = sext i16 %divergent.a to i64
+  store i64 %sext, i64 addrspace(1)* %out
+  ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone speculatable }
diff --git a/llvm/test/CodeGen/AMDGPU/update-phi.ll b/llvm/test/CodeGen/AMDGPU/update-phi.ll
index a40ccd6c1031d..9cdd32ccf63d6 100644
--- a/llvm/test/CodeGen/AMDGPU/update-phi.ll
+++ b/llvm/test/CodeGen/AMDGPU/update-phi.ll
@@ -17,8 +17,6 @@ define amdgpu_ps void @_amdgpu_ps_main() local_unnamed_addr #3 {
 ; IR-NEXT:    br i1 true, label [[TRANSITIONBLOCK]], label [[UNIFIEDRETURNBLOCK:%.*]]
 ; IR:       TransitionBlock:
 ; IR-NEXT:    br i1 [[N30]], label [[DOTLOOPEXIT]], label [[N28]]
-; IR:       n31:
-; IR-NEXT:    ret void
 ; IR:       UnifiedReturnBlock:
 ; IR-NEXT:    call void @llvm.amdgcn.exp.f32(i32 9, i32 0, float undef, float undef, float undef, float undef, i1 true, i1 true)
 ; IR-NEXT:    ret void
diff --git a/llvm/test/CodeGen/AMDGPU/wqm.mir b/llvm/test/CodeGen/AMDGPU/wqm.mir
index ec285db3aaba4..288afea1f5e99 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm.mir
+++ b/llvm/test/CodeGen/AMDGPU/wqm.mir
@@ -107,3 +107,38 @@ body:             |
     S_ENDPGM 0
 
 ...
+
+---
+# Ensure that wwm is not put around an EXEC copy
+#CHECK-LABEL: name: copy_exec
+#CHECK: %7:sreg_64 = COPY $exec
+#CHECK-NEXT: %14:sreg_64 = ENTER_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+#CHECK-NEXT: %8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+#CHECK-NEXT: $exec = EXIT_WWM %14
+#CHECK-NEXT: %9:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %7.sub0, 0, implicit $exec
+name:            copy_exec
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+
+    %3:sgpr_32 = COPY $sgpr3
+    %2:sgpr_32 = COPY $sgpr2
+    %1:sgpr_32 = COPY $sgpr1
+    %0:sgpr_32 = COPY $sgpr0
+    %4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
+    %5:sreg_32 = S_MOV_B32 0
+    %6:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %4, %5, 0, 0, 0, 0, 0, 0, implicit $exec
+
+    %8:sreg_64 = COPY $exec
+    %9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %10:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %8.sub0:sreg_64, 0, implicit $exec
+    %11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, %10:vgpr_32, 312, 15, 15, 0, implicit $exec
+    %12:sreg_32 = V_READLANE_B32 %11:vgpr_32, 63
+    early-clobber %13:sreg_32 = WWM %9:vgpr_32, implicit $exec
+
+    %14:vgpr_32 = COPY %13
+    BUFFER_STORE_DWORD_OFFSET_exact killed %14, %4, %5, 4, 0, 0, 0, 0, 0, implicit $exec
+    S_ENDPGM 0
+
+...
diff --git a/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll b/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
index e75df160e0040..0934e2805ab7b 100644
--- a/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
+++ b/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple thumbv7--windows-itanium -code-model large -verify-machineinstrs -filetype obj -o - %s \
-; RUN:    | llvm-objdump -no-show-raw-insn -d - | FileCheck %s
+; RUN:    | llvm-objdump --no-show-raw-insn -d - | FileCheck %s
 
 ; ModuleID = 'reduced.c'
 target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/CodeGen/ARM/Windows/division-range.ll b/llvm/test/CodeGen/ARM/Windows/division-range.ll
index b14339e30ad32..c341042ad0b60 100644
--- a/llvm/test/CodeGen/ARM/Windows/division-range.ll
+++ b/llvm/test/CodeGen/ARM/Windows/division-range.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple thumbv7--windows-itanium -filetype obj -o - %s | llvm-objdump -disassemble - | FileCheck %s
+; RUN: llc -O0 -mtriple thumbv7--windows-itanium -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s
 
 declare i32 @llvm.arm.space(i32, i32)
 
diff --git a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
index 3be378d8adc59..414cfb76b391a 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
@@ -1,4 +1,4 @@
-;RUN:  llc -mtriple=armv7-linux-gnueabi < %s | llvm-mc -triple=armv7-linux-gnueabi -filetype=obj | llvm-objdump -triple=armv7 -d - | FileCheck %s
+;RUN:  llc -mtriple=armv7-linux-gnueabi < %s | llvm-mc -triple=armv7-linux-gnueabi -filetype=obj | llvm-objdump --triple=armv7 -d - | FileCheck %s
 ;RUN:  llc -mtriple=armv7-linux-gnueabi < %s | FileCheck %s -check-prefix=ASM
 ;RUN:  llc -mtriple=armv7-apple-darwin < %s | FileCheck %s -check-prefix=ASM
 
diff --git a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
index b9bd4c24da0f3..db2df7021d00d 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
@@ -1,4 +1,4 @@
-;RUN:  llc -mtriple=thumbv7-linux-gnueabi < %s | llvm-mc -triple=thumbv7-linux-gnueabi -filetype=obj | llvm-objdump -triple=thumbv7 -d - | FileCheck %s
+;RUN:  llc -mtriple=thumbv7-linux-gnueabi < %s | llvm-mc -triple=thumbv7-linux-gnueabi -filetype=obj | llvm-objdump --triple=thumbv7 -d - | FileCheck %s
 ;RUN:  llc -mtriple=thumbv7-linux-gnueabi < %s | FileCheck %s -check-prefix=ASM
 ;RUN:  llc -mtriple=thumbv7-apple-darwin < %s | FileCheck %s -check-prefix=ASM
 
diff --git a/llvm/test/CodeGen/ARM/ipra-extra-spills-exceptions.ll b/llvm/test/CodeGen/ARM/ipra-extra-spills-exceptions.ll
new file mode 100644
index 0000000000000..ead0278cb3624
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ipra-extra-spills-exceptions.ll
@@ -0,0 +1,149 @@
+; RUN: llc -mtriple armv7a--none-eabi   -enable-ipra=true -arm-extra-spills -arm-extra-spills-force -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple thumbv7a--none-eabi -enable-ipra=true -arm-extra-spills -arm-extra-spills-force -verify-machineinstrs < %s | FileCheck %s
+
+; Test the interaction between IPRA and C++ exception handling. Currently, IPRA
+; only marks registers as preserved on the non-exceptional return path, not in
+; the landing pad.
+
+declare dso_local i8* @__cxa_allocate_exception(i32) local_unnamed_addr
+declare dso_local void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr
+declare dso_local i32 @__gxx_personality_v0(...)
+declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
+declare dso_local i8* @__cxa_begin_catch(i8*) local_unnamed_addr
+declare dso_local void @__cxa_end_catch() local_unnamed_addr
+
+@g = dso_local local_unnamed_addr global i32 0, align 4
+@_ZTIi = external dso_local constant i8*
+
+define dso_local i32 @_Z11maybe_throwv() minsize {
+; This function might return normally, or might throw an exception. r0 is used
+; for a return value, we can preserve r1-r3 for IPRA.
+; CHECK:      .save   {r1, r2, r3, lr}
+; CHECK-NEXT: push    {r1, r2, r3, lr}
+; CHECK:      pop{{(..)?}}    {r1, r2, r3, pc}
+entry:
+  %0 = load i32, i32* @g, align 4
+  %tobool = icmp eq i32 %0, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  %exception = tail call i8* @__cxa_allocate_exception(i32 4)
+  %1 = bitcast i8* %exception to i32*
+  store i32 42, i32* %1, align 8
+  tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
+  unreachable
+
+if.else:                                          ; preds = %entry
+  ret i32 1337
+}
+
+; Use inline assembly to force r0-r3 to be alive across a potentially throwing
+; call, using them on the non-exceptional return path. r0 is the return value,
+; so must be copied to another register. r1-r3 are voluntarily preserved by the
+; callee, so can be left in those registers.
+define dso_local i32 @_Z25test_non_exceptional_pathv() minsize personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; CHECK:      @APP
+; CHECK-NEXT: @ def r0-r3
+; CHECK-NEXT: @NO_APP
+; CHECK-NEXT: mov     [[SAVE_R0:r[0-9]+]], r0
+; CHECK-NEXT: .Ltmp{{.*}}
+; CHECK-NEXT: bl      _Z11maybe_throwv
+; CHECK:      mov     r0, [[SAVE_R0]]
+; CHECK-NEXT: @APP
+; CHECK-NEXT: @ use r0-r3
+; CHECK-NEXT: @NO_APP
+entry:
+  %0 = tail call { i32, i32, i32, i32 } asm sideeffect "// def r0-r3", "={r0},={r1},={r2},={r3}"()
+  %call = invoke i32 @_Z11maybe_throwv()
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 }
+          cleanup
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %2 = extractvalue { i8*, i32 } %1, 1
+  %3 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %2, %3
+  br i1 %matches, label %catch, label %ehcleanup
+
+catch:                                            ; preds = %lpad
+  %4 = extractvalue { i8*, i32 } %1, 0
+  %5 = tail call i8* @__cxa_begin_catch(i8* %4)
+  %6 = bitcast i8* %5 to i32*
+  %7 = load i32, i32* %6, align 4
+  tail call void @__cxa_end_catch()
+  br label %cleanup
+
+try.cont:                                         ; preds = %entry
+  %asmresult3 = extractvalue { i32, i32, i32, i32 } %0, 3
+  %asmresult2 = extractvalue { i32, i32, i32, i32 } %0, 2
+  %asmresult1 = extractvalue { i32, i32, i32, i32 } %0, 1
+  %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
+  tail call void asm sideeffect "// use r0-r3", "{r0},{r1},{r2},{r3}"(i32 %asmresult, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3)
+  br label %cleanup
+
+cleanup:                                          ; preds = %try.cont, %catch
+  %retval.0 = phi i32 [ 0, %try.cont ], [ %7, %catch ]
+  ret i32 %retval.0
+
+ehcleanup:                                        ; preds = %lpad
+  resume { i8*, i32 } %1
+}
+
+
+; Use inline assembly to force r0-r3 to be alive across a potentially throwing
+; call, using them after catching the exception. IPRA does not currently mark
+; voluntarily preserved registers as live into the landing pad block, so all
+; four registers must be copied elsewhere.
+define dso_local i32 @_Z21test_exceptional_pathv() local_unnamed_addr minsize personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; CHECK:      @APP
+; CHECK-NEXT: @ def r0-r3
+; CHECK-NEXT: @NO_APP
+; CHECK-DAG: mov [[SAVE_R0:r[0-9]+]], r0
+; CHECK-DAG: mov [[SAVE_R1:r[0-9]+]], r1
+; CHECK-DAG: mov [[SAVE_R2:r[0-9]+]], r2
+; CHECK-DAG: mov [[SAVE_R3:r[0-9]+]], r3
+; CHECK:      bl      _Z11maybe_throw
+
+; CHECK:      bl      __cxa_begin_catch
+; CHECK:      mov     r0, [[SAVE_R0]]
+; CHECK-NEXT: mov     r1, [[SAVE_R1]]
+; CHECK-NEXT: mov     r2, [[SAVE_R2]]
+; CHECK-NEXT: mov     r3, [[SAVE_R3]]
+; CHECK-NEXT: @APP
+; CHECK-NEXT: @ use r0-r3
+; CHECK-NEXT: @NO_APP
+entry:
+  %0 = tail call { i32, i32, i32, i32 } asm sideeffect "// def r0-r3", "={r0},={r1},={r2},={r3}"()
+  %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
+  %asmresult1 = extractvalue { i32, i32, i32, i32 } %0, 1
+  %asmresult2 = extractvalue { i32, i32, i32, i32 } %0, 2
+  %asmresult3 = extractvalue { i32, i32, i32, i32 } %0, 3
+  %call = invoke i32 @_Z11maybe_throwv()
+          to label %cleanup unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %1 = landingpad { i8*, i32 }
+          cleanup
+          catch i8* bitcast (i8** @_ZTIi to i8*)
+  %2 = extractvalue { i8*, i32 } %1, 1
+  %3 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+  %matches = icmp eq i32 %2, %3
+  br i1 %matches, label %catch, label %ehcleanup
+
+catch:                                            ; preds = %lpad
+  %4 = extractvalue { i8*, i32 } %1, 0
+  %5 = tail call i8* @__cxa_begin_catch(i8* %4)
+  %6 = bitcast i8* %5 to i32*
+  %7 = load i32, i32* %6, align 4
+  tail call void asm sideeffect "// use r0-r3", "{r0},{r1},{r2},{r3}"(i32 %asmresult, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3)
+  tail call void @__cxa_end_catch()
+  br label %cleanup
+
+cleanup:                                          ; preds = %entry, %catch
+  %retval.0 = phi i32 [ %7, %catch ], [ 0, %entry ]
+  ret i32 %retval.0
+
+ehcleanup:                                        ; preds = %lpad
+  resume { i8*, i32 } %1
+}
diff --git a/llvm/test/CodeGen/ARM/ipra-extra-spills.ll b/llvm/test/CodeGen/ARM/ipra-extra-spills.ll
new file mode 100644
index 0000000000000..ad9f30abdbbdd
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ipra-extra-spills.ll
@@ -0,0 +1,406 @@
+; RUN: llc -mtriple armv7a--none-eabi   -enable-ipra=true -arm-extra-spills -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -mtriple thumbv7a--none-eabi -enable-ipra=true -arm-extra-spills -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB2
+; RUN: llc -mtriple thumbv6m--none-eabi -enable-ipra=true -arm-extra-spills -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1
+
+; This clobbers r0, and already needs a push/pop, so we also save and restore
+; r0. The push of r11 is to maintain stack alignment (though that isn't
+; technically needed in this example).
+define void @test_r0_r4() minsize nounwind {
+; CHECK-LABEL: test_r0_r4:
+; ARM: .save   {r0, r4, r11, lr}
+; ARM: push    {r0, r4, r11, lr}
+; ARM: pop     {r0, r4, r11, pc}
+; THUMB1: .save   {r0, r4, r7, lr}
+; THUMB1: push    {r0, r4, r7, lr}
+; THUMB1: pop     {r0, r4, r7, pc}
+; THUMB2: .save   {r0, r4, r7, lr}
+; THUMB2: push    {r0, r4, r7, lr}
+; THUMB2: pop     {r0, r4, r7, pc}
+  call void asm sideeffect "", "~{r0},~{r4}"()
+  ret void
+}
+
+; This clobbers r0-r3, and already needs a push/pop, so we also save and
+; restore all of them.
+define void @test_r0_r1_r2_r3_r4() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4:
+; CHECK: .save   {r0, r1, r2, r3, r4, lr}
+; CHECK: push    {r0, r1, r2, r3, r4, lr}
+; CHECK: pop     {r0, r1, r2, r3, r4, pc}
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
+  ret void
+}
+
+; Check that IPRA does make use of the extra saved registers.
+define void @test_ipra() nounwind {
+; CHECK-LABEL: test_ipra:
+; CHECK: ASM1: r0, r1, r2, r3
+; CHECK-NOT: r0
+; CHECK-NOT: r1
+; CHECK-NOT: r2
+; CHECK-NOT: r3
+; CHECK: bl      test_r0_r1_r2_r3_r4
+; CHECK-NOT: r0
+; CHECK-NOT: r1
+; CHECK-NOT: r2
+; CHECK-NOT: r3
+; CHECK: ASM2: r0, r1, r2, r3
+  %regs = call { i32, i32, i32, i32 } asm sideeffect "// ASM1: $0, $1, $2, $3", "={r0},={r1},={r2},={r3}"() 
+  %r0 = extractvalue { i32, i32, i32, i32 } %regs, 0
+  %r1 = extractvalue { i32, i32, i32, i32 } %regs, 1
+  %r2 = extractvalue { i32, i32, i32, i32 } %regs, 2
+  %r3 = extractvalue { i32, i32, i32, i32 } %regs, 3
+  call void @test_r0_r1_r2_r3_r4()
+  call void asm sideeffect "// ASM2: $0, $1, $2, $3", "{r0},{r1},{r2},{r3}"(i32 %r0, i32 %r1, i32 %r2, i32 %r3)
+  ret void
+}
+
+; This clobbers r0-r3, but doesn't otherwise need a push/pop, so we don't add
+; them.
+define void @test_r0_r1_r2_r3() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3:
+; CHECK-NOT: push
+; CHECK-NOT: pop
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3}"()
+  ret void
+}
+
+; This isn't called in this function, so we don't push any extra registers.
+define void @test_r0_r4_not_called() minsize nounwind {
+; CHECK-LABEL: test_r0_r4_not_called:
+; CHECK: .save   {r4, lr}
+; CHECK: push    {r4, lr}
+; CHECK: pop     {r4, pc}
+; CHECK-NOT: push
+; CHECK-NOT: pop
+  call void asm sideeffect "", "~{r0},~{r4}"()
+  ret void
+}
+
+; This function is only optsize, not minsize, so we don't add any extra saves.
+define void @test_r0_r4_not_minsize() optsize nounwind {
+; CHECK-LABEL: test_r0_r4_not_minsize:
+; CHECK: .save   {r4, lr}
+; CHECK: push    {r4, lr}
+; CHECK: pop     {r4, pc}
+; CHECK-NOT: push
+; CHECK-NOT: pop
+  call void asm sideeffect "", "~{r0},~{r4}"()
+  ret void
+}
+
+; This function is not an exact definition (the linker could pick an
+; alternative version of it), so we don't add any extra saves.
+define linkonce_odr void @test_r0_r4_not_exact() minsize nounwind {
+; CHECK-LABEL: test_r0_r4_not_exact:
+; CHECK: .save   {r4, lr}
+; CHECK: push    {r4, lr}
+; CHECK: pop     {r4, pc}
+; CHECK-NOT: push
+; CHECK-NOT: pop
+  call void asm sideeffect "", "~{r0},~{r4}"()
+  ret void
+}
+
+; This clobbers r0-r3, but returns a value in r0, so only r1-r3 are saved.
+define i32 @test_r0_r1_r2_r3_r4_return_1() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_1:
+; ARM: .save   {r1, r2, r3, r4, r11, lr}
+; ARM: push    {r1, r2, r3, r4, r11, lr}
+; ARM: pop     {r1, r2, r3, r4, r11, pc}
+; THUMB1: .save   {r1, r2, r3, r4, r7, lr}
+; THUMB1: push    {r1, r2, r3, r4, r7, lr}
+; THUMB1: pop     {r1, r2, r3, r4, r7, pc}
+; THUMB2: .save   {r1, r2, r3, r4, r7, lr}
+; THUMB2: push    {r1, r2, r3, r4, r7, lr}
+; THUMB2: pop     {r1, r2, r3, r4, r7, pc}
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
+  ret i32 42
+}
+
+; This clobbers r0-r3, but returns a value in r0 and r1, so only r2-r3 are
+; saved.
+define i64 @test_r0_r1_r2_r3_r4_return_2() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_2:
+; CHECK: .save   {r2, r3, r4, lr}
+; CHECK: push    {r2, r3, r4, lr}
+; CHECK: pop     {r2, r3, r4, pc}
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
+  ret i64 42
+}
+
+; This clobbers r0-r3, but returns a value in all of r0-r3, so none of them can
+; be saved.
+define i128 @test_r0_r1_r2_r3_r4_return_4() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_4:
+; CHECK: .save   {r4, lr}
+; CHECK: push    {r4, lr}
+; CHECK: pop     {r4, pc}
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
+  ret i128 42
+}
+
+; This clobbers r0-r3, and returns a value in s0, so all of r0-r3 are saved (we
+; previously only checked the number of return registers, ignoring their
+; class).
+define arm_aapcs_vfpcc float @test_r0_r1_r2_r3_r4_return_float() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_float:
+; ARM: .save   {r0, r1, r2, r3, r4, lr}
+; ARM: push    {r0, r1, r2, r3, r4, lr}
+; ARM: pop     {r0, r1, r2, r3, r4, pc}
+; THUMB1: .save   {r1, r2, r3, r4, r7, lr}
+; THUMB1: push    {r1, r2, r3, r4, r7, lr}
+; THUMB1: pop     {r1, r2, r3, r4, r7, pc}
+; THUMB2: .save   {r0, r1, r2, r3, r4, lr}
+; THUMB2: push    {r0, r1, r2, r3, r4, lr}
+; THUMB2: pop     {r0, r1, r2, r3, r4, pc}
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
+  ret float 42.0
+}
+
+; Saving of high registers in thumb1 is more complicated, because they need to
+; be copied down to low registers to use push/pop instructions. Luckily, the
+; extra registers we are preserving are low registers, which are handled by the
+; outer-most push/pop pair, so this doesn't interact badly.
+define void @test_save_high_regs() minsize nounwind {
+; CHECK-LABEL: test_save_high_regs:
+; ARM: .save   {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
+; ARM: push    {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
+; ARM: pop     {r0, r1, r2, r3, r7, r8, r9, r10, r11, pc}
+; THUMB1:      .save   {r0, r1, r2, r3, r7, lr}
+; THUMB1-NEXT: push    {r0, r1, r2, r3, r7, lr}
+; THUMB1-NEXT: mov     lr, r11
+; THUMB1-NEXT: mov     r7, r10
+; THUMB1-NEXT: mov     r3, r9
+; THUMB1-NEXT: mov     r2, r8
+; THUMB1-NEXT: .save   {r8, r9, r10, r11}
+; THUMB1-NEXT: push    {r2, r3, r7, lr}
+; THUMB1:      pop     {r0, r1, r2, r3}
+; THUMB1-NEXT: mov     r8, r0
+; THUMB1-NEXT: mov     r9, r1
+; THUMB1-NEXT: mov     r10, r2
+; THUMB1-NEXT: mov     r11, r3
+; THUMB1-NEXT: pop     {r0, r1, r2, r3, r7, pc}
+; THUMB2: .save   {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
+; THUMB2: push.w  {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
+; THUMB2: pop.w   {r0, r1, r2, r3, r7, r8, r9, r10, r11, pc}
+  call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r8},~{r9},~{r10},~{r11}"()
+  ret void
+}
+
+; We can also use extra registers in the PUSH/POP instructions to move the SP
+; to make space for local variables. These registers aren't preserved, because
+; the space they are saved in is used for the local variable. We try to back
+; off the extra-CSRs optimisation to allow this to still happen. In this case,
+; there are 8 bytes of stack space needed, so we preserve two argument
+; registers and use the other two for the SP update.
+define void @test_r0_r1_r2_r3_r4_stack8() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack8:
+; CHECK: .save   {r2, r3, r4, lr}
+; CHECK: push    {r0, r1, r2, r3, r4, lr}
+; CHECK: pop     {r0, r1, r2, r3, r4, pc}
+  %a = alloca [2 x i32], align 4
+  call void asm sideeffect "str $1, [$0]; str $1, [$0, #4]", "{r0},{r1},~{r2},~{r3},~{r4}"([2 x i32]* %a, i32 42)
+  ret void
+}
+
+; Check that, when the above function is called, r0 and r1 (used for the SP
+; updates) are considered clobbered, and r2 and r3 are preserved.
+define void @test_r0_r1_r2_r3_r4_stack8_caller() nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack8_caller:
+; CHECK:      ASM1: r0, r1, r2, r3
+; CHECK-NEXT: @NO_APP
+; CHECK-NEXT: mov     r4, r0
+; CHECK-NEXT: mov     r5, r1
+; CHECK-NEXT: bl      test_r0_r1_r2_r3_r4
+; CHECK-NEXT: mov     r0, r4
+; CHECK-NEXT: mov     r1, r5
+; CHECK-NEXT: @APP
+; CHECK-NEXT: ASM2: r0, r1, r2, r3
+  %regs = call { i32, i32, i32, i32 } asm sideeffect "// ASM1: $0, $1, $2, $3", "={r0},={r1},={r2},={r3}"() 
+  %r0 = extractvalue { i32, i32, i32, i32 } %regs, 0
+  %r1 = extractvalue { i32, i32, i32, i32 } %regs, 1
+  %r2 = extractvalue { i32, i32, i32, i32 } %regs, 2
+  %r3 = extractvalue { i32, i32, i32, i32 } %regs, 3
+  call void @test_r0_r1_r2_r3_r4_stack8()
+  call void asm sideeffect "// ASM2: $0, $1, $2, $3", "{r0},{r1},{r2},{r3}"(i32 %r0, i32 %r1, i32 %r2, i32 %r3)
+  ret void
+}
+
+; Like @test_r0_r1_r2_r3_r4_stack8, but 16 bytes of stack space are needed, so
+; all of r0-r3 are used for the SP update, and not preserved.
+define void @test_r0_r1_r2_r3_r4_stack16() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack16:
+; CHECK: .save   {r4, lr}
+; CHECK: push    {r0, r1, r2, r3, r4, lr}
+; CHECK: pop     {r0, r1, r2, r3, r4, pc}
+  %a = alloca [4 x i32], align 4
+  call void asm sideeffect "str $1, [$0]; str $1, [$0, #4]", "{r0},{r1},~{r2},~{r3},~{r4}"([4 x i32]* %a, i32 42)
+  ret void
+}
+
+; If more than 16 bytes of stack space are needed, it's unlikely that the
+; SP-update folding optimisation will succeed, so we revert back to preserving
+; r0-r3 for use in our callers.
+define void @test_r0_r1_r2_r3_r4_stack24() minsize nounwind {
+; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack24:
+; CHECK: .save   {r0, r1, r2, r3, r4, lr}
+; CHECK: push    {r0, r1, r2, r3, r4, lr}
+; CHECK: pop     {r0, r1, r2, r3, r4, pc}
+  %a = alloca [6 x i32], align 4
+  call void asm sideeffect "str $1, [$0]; str $1, [$0, #4]", "{r0},{r1},~{r2},~{r3},~{r4}"([6 x i32]* %a, i32 42)
+  ret void
+}
+
+define i32 @tail_callee(i32 %a, i32 %b) minsize nounwind {
+entry:
+  tail call void asm sideeffect "", "~{r2}"()
+  ret i32 %a
+}
+
+; The tail call happens outside the save/restore region, so prevents us from
+; preserving some registers. r0 and r1 are outgoing arguments to the tail-call,
+; so can't be preserved. r2 is modified inside the tail-called function, so
+; can't be presrved. r3 is known to be preserved by the callee, so can be
+; presrved. For Thumb1, we can't (efficiently) use a tail-call here, so r1-r3
+; are all preserved, with r0 being the return value.
+define i32 @test_tail_call() minsize nounwind {
+entry:
+; CHECK-LABEL: test_tail_call:
+; ARM: .save   {r3, lr}
+; ARM: push    {r3, lr}
+; ARM: pop     {r3, lr}
+; ARM: b       tail_callee
+; THUMB2: .save   {r3, lr}
+; THUMB2: push    {r3, lr}
+; THUMB2: pop.w   {r3, lr}
+; THUMB2: b       tail_callee
+; THUMB1: .save   {r1, r2, r3, lr}
+; THUMB1: push    {r1, r2, r3, lr}
+; THUMB1: bl      tail_callee
+; THUMB1: pop     {r1, r2, r3, pc}
+  tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{lr}"()
+  %call = tail call i32 @tail_callee(i32 3, i32 4)
+  ret i32 %call
+}
+
+declare i32 @tail_callee_external(i32 %a, i32 %b)
+
+; If we tail-call an external function, it could clobber any of r0-r3.
+define i32 @test_tail_call_external() minsize nounwind {
+entry:
+; CHECK-LABEL: test_tail_call_external:
+; ARM: .save   {r11, lr}
+; ARM: push    {r11, lr}
+; ARM: pop     {r11, lr}
+; ARM: b       tail_callee_external
+; THUMB2: .save   {r7, lr}
+; THUMB2: push    {r7, lr}
+; THUMB2: pop.w   {r7, lr}
+; THUMB2: b       tail_callee_external
+; THUMB1: .save   {r1, r2, r3, lr}
+; THUMB1: push    {r1, r2, r3, lr}
+; THUMB1: bl      tail_callee_external
+; THUMB1: pop     {r1, r2, r3, pc}
+  tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{lr}"()
+  %call = tail call i32 @tail_callee_external(i32 3, i32 4)
+  ret i32 %call
+}
+
+define linkonce_odr i32 @tail_callee_linkonce_odr(i32 %a, i32 %b) minsize nounwind {
+entry:
+  tail call void asm sideeffect "", "~{r2}"()
+  ret i32 %a
+}
+
+; If a tail-callee has an interposable linkage type (such as linkonce_odr), we
+; can't assume the linker will pick the definition we can see, so must assume
+; it clobbers all of r0-r3.
+define i32 @test_tail_call_linkonce_odr() minsize nounwind {
+entry:
+; CHECK-LABEL: test_tail_call_linkonce_odr:
+; ARM: .save   {r11, lr}
+; ARM: push    {r11, lr}
+; ARM: pop     {r11, lr}
+; ARM: b       tail_callee_linkonce_odr
+; THUMB2: .save   {r7, lr}
+; THUMB2: push    {r7, lr}
+; THUMB2: pop.w   {r7, lr}
+; THUMB2: b       tail_callee_linkonce_odr
+; THUMB1: .save   {r1, r2, r3, lr}
+; THUMB1: push    {r1, r2, r3, lr}
+; THUMB1: bl      tail_callee_linkonce_odr
+; THUMB1: pop     {r1, r2, r3, pc}
+  tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{lr}"()
+  %call = tail call i32 @tail_callee_linkonce_odr(i32 3, i32 4)
+  ret i32 %call
+}
+
+; This function doesn't have the nounwind attribute, so unwind tables will be
+; emitted. Saving r0-r3 requires a longer unwind instruction sequence, which
+; results in an increase in total code size if there are few callers to make
+; use of the extra registers.
+define void @test_unwind_tables() minsize {
+; CHECK-LABEL: test_unwind_tables:
+; ARM: .save   {r4, lr}
+; ARM: push    {r4, lr}
+; ARM: pop     {r4, pc}
+; THUMB1: .save   {r4, lr}
+; THUMB1: push    {r4, lr}
+; THUMB1: pop     {r4, pc}
+; THUMB2: .save   {r4, lr}
+; THUMB2: push    {r4, lr}
+; THUMB2: pop     {r4, pc}
+  call void asm sideeffect "", "~{r0},~{r4}"()
+  ret void
+}
+
+; This requires an unwind table, but has many call sites, so overall we expect
+; the benefits to outweigh the size increase of the unwind table.
+define void @test_unwind_tables_many_calls() minsize {
+; CHECK-LABEL: test_unwind_tables_many_calls:
+; ARM: .save   {r0, r4, r11, lr}
+; ARM: push    {r0, r4, r11, lr}
+; ARM: pop     {r0, r4, r11, pc}
+; THUMB1: .save   {r0, r4, r7, lr}
+; THUMB1: push    {r0, r4, r7, lr}
+; THUMB1: pop     {r0, r4, r7, pc}
+; THUMB2: .save   {r0, r4, r7, lr}
+; THUMB2: push    {r0, r4, r7, lr}
+; THUMB2: pop     {r0, r4, r7, pc}
+  call void asm sideeffect "", "~{r0},~{r4}"()
+  ret void
+}
+
+; We don't do this optimisation is there are no callers in the same translation
+; unit (otherwise IPRA wouldn't be able to take advantage of the extra saved
+; registers), so most functions in this file are called here.
+define void @caller() {
+; CHECK-LABEL: caller:
+  call void @test_r0_r4()
+  call void @test_r0_r1_r2_r3_r4()
+  call void @test_r0_r1_r2_r3()
+  call void @test_r0_r4_not_minsize()
+  call void @test_r0_r4_not_exact()
+  %t1 = call i32 @test_r0_r1_r2_r3_r4_return_1()
+  %t2 = call i64 @test_r0_r1_r2_r3_r4_return_2()
+  %t3 = call i128 @test_r0_r1_r2_r3_r4_return_4()
+  %t4 = call float @test_r0_r1_r2_r3_r4_return_float()
+  call void @test_save_high_regs()
+  call void @test_r0_r1_r2_r3_r4_stack16()
+  call void @test_r0_r1_r2_r3_r4_stack24()
+  %t5 = call i32 @test_tail_call()
+  %t6 = call i32 @test_tail_call_external()
+  %t7 = call i32 @test_tail_call_linkonce_odr()
+  call void @test_unwind_tables()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  call void @test_unwind_tables_many_calls()
+  ret void
+}
diff --git a/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll b/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
index 222664a904ca7..5b589ab979c58 100644
--- a/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
+++ b/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
@@ -10,8 +10,8 @@
 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -mattr=-hwdiv,-hwdiv-arm | FileCheck %s --check-prefix=NODIV_KRAIT
 
 ; check if correct instruction is emitted by integrated assembler
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple armv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV
-; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple thumbv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump --mcpu=krait --triple=armv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump --mcpu=krait --triple=thumbv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV
 
 ; arch_extension attribute
 ; DIV_EXTENSION:  .cpu cortex-a9
diff --git a/llvm/test/CodeGen/ARM/local-call.ll b/llvm/test/CodeGen/ARM/local-call.ll
index c07294685e924..dd0953379fb19 100644
--- a/llvm/test/CodeGen/ARM/local-call.ll
+++ b/llvm/test/CodeGen/ARM/local-call.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=thumbv7-apple-ios -filetype=obj %s -o %t
-; RUN: llvm-objdump -macho -d %t | FileCheck %s
+; RUN: llvm-objdump --macho -d %t | FileCheck %s
 
 ; This function just messes up the offsets enough to make the libcall in
 ; test_local_call unencodable with a blx.
diff --git a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
index 819662e7beb98..1ff8a39fbb8e2 100644
--- a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
+++ b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
@@ -1,13 +1,13 @@
-;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi   -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi   -disassemble - | FileCheck %s --check-prefix=ARM
-;RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=THUMB2
-;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi   -mattr=-neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi   -disassemble - | FileCheck %s --check-prefix=NO_NEON
+;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi   -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump --triple=armv7-none-linux-gnueabi   -d - | FileCheck %s --check-prefix=ARM
+;RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump --triple=thumbv7-none-linux-gnueabi -d - | FileCheck %s --check-prefix=THUMB2
+;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi   -mattr=-neon -verify-machineinstrs -filetype=obj | llvm-objdump --triple=armv7-none-linux-gnueabi   -d - | FileCheck %s --check-prefix=NO_NEON
 ;We want to have both positive and negative checks for thumb1. These checks
 ;are not easy to do in a single pass so we generate the output once to a
 ;temp file and run filecheck twice with different prefixes.
-;RUN: llc < %s -mtriple=thumbv5-none-linux-gnueabi              -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv5-none-linux-gnueabi -disassemble - > %t
+;RUN: llc < %s -mtriple=thumbv5-none-linux-gnueabi              -verify-machineinstrs -filetype=obj | llvm-objdump --triple=thumbv5-none-linux-gnueabi -d - > %t
 ;RUN: cat %t | FileCheck %s --check-prefix=THUMB1
 ;RUN: cat %t | FileCheck %s --check-prefix=T1POST
-;RUN: llc < %s -mtriple=thumbv8m.base-arm-none-eabi             -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv8m.base-arm-none-eabi -disassemble - > %t
+;RUN: llc < %s -mtriple=thumbv8m.base-arm-none-eabi             -verify-machineinstrs -filetype=obj | llvm-objdump --triple=thumbv8m.base-arm-none-eabi -d - > %t
 ;RUN: cat %t | FileCheck %s --check-prefix=THUMB1
 ;RUN: cat %t | FileCheck %s --check-prefix=T1POST
 ;RUN: cat %t | FileCheck %s --check-prefix=V8MBASE
diff --git a/llvm/test/CodeGen/ARM/thumb1-varalloc.ll b/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
index 8d56fe1da90d5..06b67d7813611 100644
--- a/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
+++ b/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
 ; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-darwin
-; RUN: llvm-objdump -triple=thumbv6-apple-darwin -d %t | FileCheck %s
+; RUN: llvm-objdump --triple=thumbv6-apple-darwin -d %t | FileCheck %s
 
 @__bar = external hidden global i8*
 @__baz = external hidden global i8*
diff --git a/llvm/test/CodeGen/ARM/trap.ll b/llvm/test/CodeGen/ARM/trap.ll
index c45f7133febeb..69a8bb719baa3 100644
--- a/llvm/test/CodeGen/ARM/trap.ll
+++ b/llvm/test/CodeGen/ARM/trap.ll
@@ -6,24 +6,24 @@
 ; RUN: llc < %s -mtriple=thumbv7 | FileCheck %s -check-prefix=THUMB
 
 ; RUN: llc -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \
+; RUN:  | llvm-objdump -d --triple=armv7 --mattr=+nacl-trap - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-NACL
 ; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \
+; RUN:  | llvm-objdump -d --triple=armv7 --mattr=+nacl-trap - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-NACL
 
 ; RUN: llc -mtriple=armv7 -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -disassemble -triple armv7 - \
+; RUN:  | llvm-objdump -d --triple=armv7 - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-ARM
 ; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -disassemble -triple armv7 - \
+; RUN:  | llvm-objdump -d --triple=armv7 - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-ARM
 
 ; RUN: llc -mtriple=thumbv7 -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -disassemble -triple thumbv7 - \
+; RUN:  | llvm-objdump -d --triple=thumbv7 - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-THUMB
 ; RUN: llc -verify-machineinstrs -fast-isel -mtriple=thumbv7 -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -disassemble -triple thumbv7 - \
+; RUN:  | llvm-objdump -d --triple=thumbv7 - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-THUMB
 
 ; rdar://7961298
diff --git a/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll b/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
index 252e98bf4e73e..c49c47a086ff2 100644
--- a/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
+++ b/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=thumbv7-- -mcpu=cortex-a9 -O1 -filetype=obj %s -o - | llvm-objdump -triple=thumbv7-- -mcpu=cortex-a9 -d - | FileCheck %s
+; RUN: llc -mtriple=thumbv7-- -mcpu=cortex-a9 -O1 -filetype=obj %s -o - | llvm-objdump --triple=thumbv7-- --mcpu=cortex-a9 -d - | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "thumbv7--linux-gnueabi"
diff --git a/llvm/test/CodeGen/BPF/objdump_imm_hex.ll b/llvm/test/CodeGen/BPF/objdump_imm_hex.ll
index a245a6c791f20..0fd1d45deaa4f 100644
--- a/llvm/test/CodeGen/BPF/objdump_imm_hex.ll
+++ b/llvm/test/CodeGen/BPF/objdump_imm_hex.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-DEC %s
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d -print-imm-hex - | FileCheck --check-prefix=CHECK-HEX %s
+; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d --print-imm-hex - | FileCheck --check-prefix=CHECK-HEX %s
 
 ; Source Code:
 ; int gbl;
diff --git a/llvm/test/CodeGen/Generic/csw-debug-assert.ll b/llvm/test/CodeGen/Generic/csw-debug-assert.ll
new file mode 100644
index 0000000000000..b87638eb8f737
--- /dev/null
+++ b/llvm/test/CodeGen/Generic/csw-debug-assert.ll
@@ -0,0 +1,64 @@
+; Check that compiler doesn't crash when calculateSpillWeightsAndHints is called with dbg instrs present
+; REQUIRES: asserts
+; REQUIRES: x86_64-linux
+; RUN: llc -O1 -regalloc=pbqp < %s | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK-LABEL: test:
+define dso_local void @test(i32* %a) local_unnamed_addr #0 !dbg !7 {
+entry:
+  ; CHECK: DEBUG_VALUE: i <- 0
+  call void @llvm.dbg.value(metadata i32* %a, metadata !14, metadata !DIExpression()), !dbg !17
+  call void @llvm.dbg.value(metadata i32 0, metadata !15, metadata !DIExpression()), !dbg !17
+  br label %for.cond, !dbg !17
+
+for.cond:                                         ; preds = %for.body, %entry
+  %a.addr.0 = phi i32* [ %a, %entry ], [ %incdec.ptr, %for.body ]
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ], !dbg !17
+  call void @llvm.dbg.value(metadata i32 %i.0, metadata !15, metadata !DIExpression()), !dbg !17
+  call void @llvm.dbg.value(metadata i32* %a.addr.0, metadata !14, metadata !DIExpression()), !dbg !17
+  %cmp = icmp slt i32 %i.0, 32, !dbg !17
+  br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !17
+
+for.cond.cleanup:                                 ; preds = %for.cond
+  ret void, !dbg !17
+
+for.body:                                         ; preds = %for.cond
+  %incdec.ptr = getelementptr inbounds i32, i32* %a.addr.0, i32 1, !dbg !17
+  call void @llvm.dbg.value(metadata i32* %incdec.ptr, metadata !14, metadata !DIExpression()), !dbg !17
+  store i32 42, i32* %a.addr.0, align 4, !dbg !17
+  %inc = add nsw i32 %i.0, 1, !dbg !17
+  call void @llvm.dbg.value(metadata i32 %inc, metadata !15, metadata !DIExpression()), !dbg !17
+  br label %for.cond, !dbg !17
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare void @llvm.dbg.value(metadata, metadata, metadata) #1
+
+attributes #0 = { nounwind uwtable optnone noinline }
+attributes #1 = { nounwind readnone speculatable willreturn }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!llvm.ident = !{!6}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0 (https://github.com/llvm/llvm-project.git afaeb817468d2fdc0a315a7ff136db245e59a8eb)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "csw-debug-assert.c", directory: "dir")
+!2 = !{}
+!3 = !{i32 7, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git afaeb817468d2fdc0a315a7ff136db245e59a8eb)"}
+!7 = distinct !DISubprogram(name: "test", scope: !8, file: !8, line: 5, type: !9, scopeLine: 5, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !13)
+!8 = !DIFile(filename: "csw-debug-assert.c", directory: "dir")
+!9 = !DISubroutineType(types: !10)
+!10 = !{null, !11}
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64)
+!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!13 = !{!14, !15}
+!14 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !8, line: 5, type: !11)
+!15 = !DILocalVariable(name: "i", scope: !16, file: !8, line: 6, type: !12)
+!16 = distinct !DILexicalBlock(scope: !7, file: !8, line: 6, column: 5)
+!17 = !DILocation(line: 0, scope: !7)
diff --git a/llvm/test/CodeGen/Hexagon/bug18008.ll b/llvm/test/CodeGen/Hexagon/bug18008.ll
index 04ccecb98df94..8e83c5e858f55 100644
--- a/llvm/test/CodeGen/Hexagon/bug18008.ll
+++ b/llvm/test/CodeGen/Hexagon/bug18008.ll
@@ -1,4 +1,4 @@
-;RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump -mv60 -mhvx -d - | FileCheck %s
+;RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump --mv60 --mhvx -d - | FileCheck %s
 
 ; Should not crash! and map to vxor
 
diff --git a/llvm/test/CodeGen/Hexagon/vect-regpairs.ll b/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
index 4d505fc2f4eef..7ee2b7fc30c2f 100644
--- a/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
+++ b/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
@@ -1,5 +1,5 @@
-;RUN: llc -march=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj < %s -o - | llvm-objdump -mv66 -mhvx -d - | FileCheck --check-prefix=CHECK-V66 %s
-;RUN: llc -march=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj < %s -o - | llvm-objdump -mv67 -mhvx -d - | FileCheck --check-prefix=CHECK-V67 %s
+;RUN: llc -march=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj < %s -o - | llvm-objdump --mv66 --mhvx -d - | FileCheck --check-prefix=CHECK-V66 %s
+;RUN: llc -march=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj < %s -o - | llvm-objdump --mv67 --mhvx -d - | FileCheck --check-prefix=CHECK-V67 %s
 
 ; Should not attempt to use v<even>:<odd> 'reverse' vector regpairs
 ; on old or new arches (should not crash).
diff --git a/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir b/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
index 07da099a742cc..520a8fadf7a53 100644
--- a/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
+++ b/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
@@ -89,8 +89,8 @@ body:             |
     ; CHECK: t2STRi12 killed renamable $r0, $sp, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.s)
     ; CHECK: renamable $r0 = t2LDRi12 $sp, 4, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.s)
     ; CHECK: tBL 14 /* CC::al */, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp
-    ; CHECK: $sp = t2ADDspImm12 killed $sp, 4008, 14 /* CC::al */, $noreg
-    ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc
+    ; CHECK: $sp = frame-destroy t2ADDspImm12 killed $sp, 4008, 14 /* CC::al */, $noreg
+    ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc
     renamable $r0 = t2ADDri %stack.0.v, 0, 14, $noreg, $noreg
     t2STRi12 killed renamable $r0, %stack.1.s, 0, 14, $noreg :: (store 4 into %ir.s)
     renamable $r0 = t2LDRi12 %stack.1.s, 0, 14, $noreg :: (dereferenceable load 4 from %ir.s)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
index 7901de7ea6d7c..e02508ffd4fdd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
@@ -525,8 +525,7 @@ body:             |
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
     ; MIPS32: $v0 = COPY [[LSHR]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
@@ -707,27 +706,26 @@ body:             |
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
     ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
-    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
-    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[C]]
-    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY4]]
+    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
+    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
     ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[C]]
-    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY4]](s32), [[C1]]
-    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY2]](s32)
     ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32)
-    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY4]](s32)
+    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY2]](s32)
     ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
     ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32)
     ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
     ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C1]]
-    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
     ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
-    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
     ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[COPY1]], [[SELECT1]]
     ; MIPS32: $v0 = COPY [[SELECT]](s32)
     ; MIPS32: $v1 = COPY [[SELECT2]](s32)
@@ -759,29 +757,28 @@ body:             |
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
     ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
-    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
-    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[C]]
-    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY4]]
+    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
+    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
     ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[C]]
-    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY4]](s32), [[C1]]
-    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[COPY4]](s32)
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY4]](s32)
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[COPY2]](s32)
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
     ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
     ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
     ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
     ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C2]](s32)
     ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[SUB]](s32)
     ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
     ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
-    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
-    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
     ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
-    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
     ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
     ; MIPS32: $v0 = COPY [[SELECT1]](s32)
     ; MIPS32: $v1 = COPY [[SELECT2]](s32)
@@ -813,27 +810,26 @@ body:             |
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
     ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
-    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
-    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[C]]
-    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY4]]
+    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
+    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
     ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[C]]
-    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY4]](s32), [[C1]]
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[COPY4]](s32)
-    ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY4]](s32)
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[COPY2]](s32)
+    ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
     ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
     ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
     ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB]](s32)
     ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
     ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
-    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
-    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
     ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
-    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
     ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]]
     ; MIPS32: $v0 = COPY [[SELECT1]](s32)
     ; MIPS32: $v1 = COPY [[SELECT2]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
index 34ccfd97e278b..0d77d27ee2ff0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
@@ -17,8 +17,7 @@ body:             |
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; MIPS32: $v0 = COPY [[COPY2]](s32)
+    ; MIPS32: $v0 = COPY [[COPY]](s32)
     ; MIPS32: RetRA implicit $v0
     %1:_(s32) = COPY $a0
     %2:_(s32) = COPY $a1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index 3e779d7dd2758..c176f0ee3ad83 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -218,8 +218,7 @@ body:             |
     ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
     ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
     ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[ASHR]](s32)
     ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
     ; MIPS32: $v0 = COPY [[UV]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
index 93d3c17aac778..b389be8030088 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
@@ -44,8 +44,7 @@ body:             |
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
     ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
-    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
     ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
     ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
     ; MIPS32: $v0 = COPY [[UV]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
index bc59860313543..ec4252c17dee1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
@@ -114,8 +114,7 @@ define i64 @load4_s32_to_sextLoad4_s64(i32* %px) {
 ; MIPS32-LABEL: load4_s32_to_sextLoad4_s64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lw $1, 0($4)
-; MIPS32-NEXT:    ori $2, $zero, 31
-; MIPS32-NEXT:    srav $3, $1, $2
+; MIPS32-NEXT:    sra $3, $1, 31
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
index 1249d5c955411..7f54f810b8ddc 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
@@ -16,8 +16,7 @@ entry:
 define i64 @sext(i32 %x) {
 ; MIPS32-LABEL: sext:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 31
-; MIPS32-NEXT:    srav $3, $4, $1
+; MIPS32-NEXT:    sra $3, $4, 31
 ; MIPS32-NEXT:    move $2, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
index 3da485c6c0cd7..fdfaf3f7ee040 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
 
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump --no-show-raw-insn --arch=mips --mcpu=mips32r6 --mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
 
 ; Test the callee-saved registers are callee-saved as specified by section
 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
diff --git a/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll b/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
index be97a07c8366e..5e607c2639f3b 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
 ; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
-; RUN:     -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
+; RUN:     -o - | llvm-objdump -d - | FileCheck %s --check-prefix=ENCODING
 ; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
 ; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
-; RUN:     -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
+; RUN:     -o - | llvm-objdump -d - | FileCheck %s --check-prefix=ENCODING
 
 ; bnezc and beqzc have restriction that $rt != 0
 
diff --git a/llvm/test/CodeGen/Mips/micromips-atomic1.ll b/llvm/test/CodeGen/Mips/micromips-atomic1.ll
index d7c66c27b6e22..2174c218b11bf 100644
--- a/llvm/test/CodeGen/Mips/micromips-atomic1.ll
+++ b/llvm/test/CodeGen/Mips/micromips-atomic1.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \
-; RUN:   | llvm-objdump -no-show-raw-insn -d - | FileCheck %s -check-prefix=MICROMIPS
+; RUN:   | llvm-objdump --no-show-raw-insn -d - | FileCheck %s --check-prefix=MICROMIPS
 
 ; Use llvm-objdump to check wheter the encodings of microMIPS atomic instructions are correct.
 ; While emitting assembly files directly when in microMIPS mode, it is possible to emit a mips32r2
diff --git a/llvm/test/CodeGen/Mips/micromips-eva.mir b/llvm/test/CodeGen/Mips/micromips-eva.mir
index 3210d584fc8c5..fd30529f7097c 100644
--- a/llvm/test/CodeGen/Mips/micromips-eva.mir
+++ b/llvm/test/CodeGen/Mips/micromips-eva.mir
@@ -1,5 +1,5 @@
 # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
-# RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
+# RUN:     -filetype obj %s -o - | llvm-objdump --mattr=+eva -d - | FileCheck %s
 
 --- |
 
diff --git a/llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll b/llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll
index 25a5e5b8fff5c..8005fe66e595c 100644
--- a/llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll
+++ b/llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll
@@ -1,30 +1,30 @@
 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC32
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=PIC32
 
 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC32
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=STATIC32
 
 ; RUN: llc -filetype=obj -march=mips64el -relocation-model=pic -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC64
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=PIC64
 
 ; RUN: llc -filetype=obj -march=mips64el -relocation-model=static -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC64
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=STATIC64
 
 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -mattr=+micromips -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC32MM
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=PIC32MM
 
 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -mattr=+micromips -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC32MM
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=STATIC32MM
 
 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s  -check-prefix=PIC32R6
+; RUN:   | llvm-objdump -d - | FileCheck %s  --check-prefix=PIC32R6
 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -mcpu=mips32r6 -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC32R6
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=STATIC32R6
 
 ; RUN: llc -filetype=obj -march=mips64el -relocation-model=pic -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=PIC64R6
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=PIC64R6
 ; RUN: llc -filetype=obj -march=mips64el -relocation-model=static -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \
-; RUN:   | llvm-objdump  -d - | FileCheck %s -check-prefix=STATIC64R6
+; RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=STATIC64R6
 
 
 define internal i8 @f2(i8) {
diff --git a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
index 84ef651e286ce..47e9a3205e09e 100644
--- a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
+++ b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
@@ -1,5 +1,5 @@
 # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
-# RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
+# RUN:     -filetype obj %s -o - | llvm-objdump --mattr=+eva -d - | FileCheck %s
 
 # Test that MIPS unaligned load/store instructions can be mapped to their
 # corresponding microMIPS instructions.
diff --git a/llvm/test/CodeGen/PowerPC/2016-04-28-setjmp.ll b/llvm/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
index bfa0d40bc630d..198d79f4c7530 100644
--- a/llvm/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
+++ b/llvm/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj <%s | llvm-objdump --disassemble - | FileCheck %s
+; RUN: llc -filetype=obj <%s | llvm-objdump -d - | FileCheck %s
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-byval-param.ll b/llvm/test/CodeGen/PowerPC/aix-byval-param.ll
deleted file mode 100644
index 2dfdf7f8535f0..0000000000000
--- a/llvm/test/CodeGen/PowerPC/aix-byval-param.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
-; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
-
-%struct.S = type { i32, i32 }
-
-define void @bar() {
-entry:
-  %s1 = alloca %struct.S, align 4
-  %agg.tmp = alloca %struct.S, align 4
-  call void @foo(%struct.S* byval(%struct.S) align 4 %agg.tmp)
-  ret void
-}
-
-declare void @foo(%struct.S* byval(%struct.S) align 4)
-
-; CHECK: LLVM ERROR: Passing structure by value is unimplemented.
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation1.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation1.ll
new file mode 100644
index 0000000000000..745323ce8a5d8
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation1.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
+
+%struct.S = type { [9 x i8] }
+
+define void @bar() {
+entry:
+  %s1 = alloca %struct.S, align 1
+  %agg.tmp = alloca %struct.S, align 1
+  call void @foo(%struct.S* byval(%struct.S) align 1 %agg.tmp)
+  ret void
+}
+
+declare void @foo(%struct.S* byval(%struct.S) align 1)
+
+; CHECK: LLVM ERROR: Pass-by-value arguments are only supported in a single register.
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation2.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation2.ll
new file mode 100644
index 0000000000000..b9c48272d147d
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation2.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
+
+%struct.S = type { [1 x i8] }
+
+define void @bar() {
+entry:
+  %s1 = alloca %struct.S, align 1
+  %agg.tmp = alloca %struct.S, align 1
+  call void @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, %struct.S* byval(%struct.S) align 1 %agg.tmp)
+  ret void
+}
+
+declare void @foo(i32, i32, i32, i32, i32, i32, i32, i32, %struct.S* byval(%struct.S) align 1)
+
+; CHECK: LLVM ERROR: Pass-by-value arguments are only supported in a single register.
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation3.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation3.ll
new file mode 100644
index 0000000000000..357acfe595bbc
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation3.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
+
+%struct.S = type { [1 x i8] }
+
+define void @bar() {
+entry:
+  %s1 = alloca %struct.S, align 32
+  %agg.tmp = alloca %struct.S, align 32
+  call void @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, %struct.S* byval(%struct.S) align 32 %agg.tmp)
+  ret void
+}
+
+declare void @foo(i32, i32, i32, i32, i32, i32, i32, i32, %struct.S* byval(%struct.S) align 32)
+
+; CHECK: LLVM ERROR: Pass-by-value arguments with alignment greater than register width are not supported.
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
new file mode 100644
index 0000000000000..0f90da66d60d9
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
@@ -0,0 +1,206 @@
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN:  -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM32PWR4 %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN:  -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
+
+%struct.S1 = type { [1 x i8] }
+@gS1 = external global %struct.S1, align 1
+
+define void @call_test_byval_1Byte() {
+entry:
+  call void @test_byval_1Byte(%struct.S1* byval(%struct.S1) align 1 @gS1)
+  ret void
+}
+
+declare void @test_byval_1Byte(%struct.S1* byval(%struct.S1) align 1)
+
+; CHECK-LABEL: name: call_test_byval_1Byte{{.*}}
+
+; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS1, $r2 :: (load 4 from got)
+; 32BIT-NEXT:  renamable $r3 = LBZ 0, killed renamable $r[[REG]] :: (load 1)
+; 32BIT-NEXT:  renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; CHECKASM-LABEL: .call_test_byval_1Byte:
+
+; ASM32PWR4:       stwu 1, -64(1)
+; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32PWR4-NEXT:  lbz 3, 0([[REG]])
+; ASM32PWR4-NEXT:  slwi 3, 3, 24
+; ASM32PWR4-NEXT:  bl .test_byval_1Byte
+; ASM32PWR4-NEXT:  nop
+; ASM32PWR4-NEXT:  addi 1, 1, 64
+
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got)
+; 64BIT-NEXT:  renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load 1)
+; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 56, 7
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_1Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; ASM64PWR4:       std 0, 16(1)
+; ASM64PWR4-NEXT:  stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-NEXT:  lbz 3, 0([[REG]])
+; ASM64PWR4-NEXT:  sldi 3, 3, 56
+; ASM64PWR4-NEXT:  bl .test_byval_1Byte
+; ASM64PWR4-NEXT:  nop
+; ASM64PWR4-NEXT:  addi 1, 1, 112
+
+%struct.S2 = type { [2 x i8] }
+
+@gS2 = external global %struct.S2, align 1
+
+define void @call_test_byval_2Byte() {
+entry:
+  call void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1 @gS2)
+  ret void
+}
+
+declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
+
+; CHECK-LABEL: name: call_test_byval_2Byte{{.*}}
+
+; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS2, $r2 :: (load 4 from got)
+; 32BIT-NEXT:  renamable $r3 = LHZ 0, killed renamable $r[[REG]] :: (load 2)
+; 32BIT-NEXT:  renamable $r3 = RLWINM killed renamable $r3, 16, 0, 15
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; CHECKASM-LABEL: .call_test_byval_2Byte:
+
+; ASM32PWR4:       stwu 1, -64(1)
+; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32PWR4-NEXT:  lhz 3, 0([[REG]])
+; ASM32PWR4-NEXT:  slwi 3, 3, 16
+; ASM32PWR4-NEXT:  bl .test_byval_2Byte
+; ASM32PWR4-NEXT:  nop
+; ASM32PWR4-NEXT:  addi 1, 1, 64
+
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS2, $x2 :: (load 8 from got)
+; 64BIT-NEXT:  renamable $x3 = LHZ8 0, killed renamable $x[[REG]] :: (load 2)
+; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 48, 15
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_2Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; ASM64PWR4:       std 0, 16(1)
+; ASM64PWR4-NEXT:  stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-NEXT:  lhz 3, 0([[REG]])
+; ASM64PWR4-NEXT:  sldi 3, 3, 48
+; ASM64PWR4-NEXT:  bl .test_byval_2Byte
+; ASM64PWR4-NEXT:  nop
+; ASM64PWR4-NEXT:  addi 1, 1, 112
+
+%struct.S3 = type { [3 x i8] }
+
+@gS3 = external global %struct.S3, align 1
+
+define void @call_test_byval_3Byte() {
+entry:
+  call void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1 @gS3)
+  ret void
+}
+
+declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
+
+; CHECK-LABEL: name: call_test_byval_3Byte{{.*}}
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS3, $r2 :: (load 4 from got)
+; 32BIT-DAG:   renamable $r[[REG1:[0-9]+]] = LHZ 0, killed renamable $r[[REGADDR]] :: (load 2)
+; 32BIT-DAG:   renamable $r[[REG2:[0-9]+]] = LBZ 2, renamable $r[[REGADDR]] :: (load 1)
+; 32BIT-DAG:   renamable $r3 = RLWINM killed renamable $r[[REG2]], 8, 16, 23
+; 32BIT-DAG:   renamable $r3 = RLWIMI killed renamable $r3, killed renamable $r[[REG1]], 16, 0, 15
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_3Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; CHECKASM-LABEL: .call_test_byval_3Byte:
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; ASM32PWR4:       stwu 1, -64(1)
+; ASM32PWR4-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32PWR4-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
+; ASM32PWR4-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
+; ASM32PWR4-DAG:   rlwinm 3, [[REG2]], 8, 16, 23
+; ASM32PWR4-DAG:   rlwimi 3, [[REG1]], 16, 0, 15
+; ASM32PWR4-NEXT:  bl .test_byval_3Byte
+; ASM32PWR4-NEXT:  nop
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-DAG:   renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS3, $x2 :: (load 8 from got)
+; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LHZ8 0, killed renamable $x[[REGADDR]] :: (load 2)
+; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 2, renamable $x[[REGADDR]] :: (load 1)
+; 64BIT-DAG:   renamable $x3 = RLDIC killed renamable $x[[REG2]], 40, 16
+; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 48, 0
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_3Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; ASM64PWR4:       stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
+; ASM64PWR4-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
+; ASM64PWR4-DAG:   rldic 3, [[REG2]], 40, 16
+; ASM64PWR4-DAG:   rldimi 3, [[REG1]], 48, 0
+; ASM64PWR4-NEXT:  bl .test_byval_3Byte
+; ASM64PWR4-NEXT:  nop
+
+%struct.S4 = type { [4 x i8] }
+
+@gS4 = external global %struct.S4, align 1
+
+define void @call_test_byval_4Byte() {
+entry:
+  call void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 @gS4)
+  ret void
+}
+
+declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1)
+
+; CHECK-LABEL: name: call_test_byval_4Byte{{.*}}
+
+; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS4, $r2 :: (load 4 from got)
+; 32BIT-NEXT:  renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4)
+; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; CHECKASM-LABEL: .call_test_byval_4Byte:
+
+; ASM32PWR4:       stwu 1, -64(1)
+; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32PWR4-NEXT:  lwz 3, 0([[REG]])
+; ASM32PWR4-NEXT:  bl .test_byval_4Byte
+; ASM32PWR4-NEXT:  nop
+; ASM32PWR4-NEXT:  addi 1, 1, 64
+
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
+; 64BIT-NEXT:  renamable $x3 = LWZ8 0, killed renamable $x[[REG]] :: (load 4)
+; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 32, 31
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; ASM64PWR4:       stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-NEXT:  lwz 3, 0([[REG]])
+; ASM64PWR4-NEXT:  sldi 3, 3, 32
+; ASM64PWR4-NEXT:  bl .test_byval_4Byte
+; ASM64PWR4-NEXT:  nop
+; ASM64PWR4-NEXT:  addi 1, 1, 112
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
new file mode 100644
index 0000000000000..599ab13530b84
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
@@ -0,0 +1,146 @@
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN:  -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
+
+%struct.S5 = type { [5 x i8] }
+
+@gS5 = external global %struct.S5, align 1
+
+define void @call_test_byval_5Byte() {
+entry:
+  call void @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5)
+  ret void
+}
+
+declare void @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
+
+; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
+
+; CHECKASM-LABEL: .call_test_byval_5Byte:
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
+; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
+; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
+; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
+; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; ASM64PWR4:       stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
+; ASM64PWR4-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
+; ASM64PWR4-DAG:   rlwinm 3, [[REG2]], 24, 0, 7
+; ASM64PWR4-DAG:   rldimi 3, [[REG1]], 32, 0
+; ASM64PWR4-NEXT:  bl .test_byval_5Byte
+; ASM64PWR4-NEXT:  nop
+
+%struct.S6 = type { [6 x i8] }
+
+@gS6 = external global %struct.S6, align 1
+
+define void @call_test_byval_6Byte() {
+entry:
+  call void @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
+  ret void
+}
+
+declare void @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
+
+; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
+
+; CHECKASM-LABEL: .call_test_byval_6Byte:
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
+; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
+; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
+; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
+; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; ASM64PWR4:       stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
+; ASM64PWR4-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
+; ASM64PWR4-DAG:   rlwinm 3, [[REG2]], 16, 0, 15
+; ASM64PWR4-DAG:   rldimi 3, [[REG1]], 32, 0
+; ASM64PWR4-NEXT:  bl .test_byval_6Byte
+; ASM64PWR4-NEXT:  nop
+
+%struct.S7 = type { [7 x i8] }
+
+@gS7 = external global %struct.S7, align 1
+
+define void @call_test_byval_7Byte() {
+entry:
+  call void @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7)
+  ret void
+}
+
+declare void @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
+
+; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
+
+; CHECKASM-LABEL: .call_test_byval_7Byte:
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
+; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
+; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
+; 64BIT-DAG:   renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
+; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
+; 64BIT-DAG:   renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
+; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
+; ASM64PWR4:       stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
+; ASM64PWR4-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
+; ASM64PWR4-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])
+; ASM64PWR4-DAG:   rlwinm 3, [[REG3]], 8, 16, 23
+; ASM64PWR4-DAG:   rlwimi 3, [[REG2]], 16, 0, 15
+; ASM64PWR4-DAG:   rldimi 3, [[REG1]], 32, 0
+; ASM64PWR4-NEXT:  bl .test_byval_7Byte
+; ASM64PWR4-NEXT:  nop
+
+%struct.S8 = type { [8 x i8] }
+
+@gS8 = external global %struct.S8, align 1
+
+define void @call_test_byval_8Byte() {
+entry:
+  call void @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
+  ret void
+}
+
+declare void @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
+
+; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
+
+; CHECKASM-LABEL: .call_test_byval_8Byte:
+
+; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
+; 64BIT-NEXT:  renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+; ASM64PWR4:       stdu 1, -112(1)
+; ASM64PWR4-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64PWR4-NEXT:  ld 3, 0([[REGADDR]])
+; ASM64PWR4-NEXT:  bl .test_byval_8Byte
+; ASM64PWR4-NEXT:  nop
diff --git a/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir b/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir
index 041f0f9747fec..2ec09b0fb26b7 100644
--- a/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir
+++ b/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir
@@ -1,10 +1,10 @@
 # RUN: llc -mcpu=future -mtriple=powerpc64le-unknown-unknown %s \
 # RUN:   -start-before=ppc-branch-select -verify-machineinstrs \
-# RUN:   -filetype=obj -o - | llvm-objdump -mcpu=future -d -r - | \
+# RUN:   -filetype=obj -o - | llvm-objdump --mcpu=future -d -r - | \
 # RUN:   FileCheck --check-prefix=CHECK-LE %s
 # RUN: llc -mcpu=future -mtriple=powerpc64-unknown-unknown %s \
 # RUN:   -start-before=ppc-branch-select -verify-machineinstrs \
-# RUN:   -filetype=obj -o - | llvm-objdump -mcpu=future -d -r - | \
+# RUN:   -filetype=obj -o - | llvm-objdump --mcpu=future -d -r - | \
 # RUN:   FileCheck --check-prefix=CHECK-BE %s
 
 # The purpose of this test is to check that long branches are selected correctly
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index df5b040b5dcd1..c922312eae12d 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -550,6 +550,14 @@
     ret i64 %and
   }
   
+  ; Function Attrs: norecurse nounwind readnone
+  define i64 @testRLDICL_MB0(i64 %a) local_unnamed_addr #0 {
+  entry:
+    %shr = lshr i64 %a, 11
+    %and = and i64 %shr, 16777215
+    ret i64 %and
+  }
+  
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLDICL_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
@@ -3882,6 +3890,52 @@ body:             |
     $x3 = COPY %1
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
+...
+---
+name:            testRLDICL_MB0
+# CHECK-ALL: name: testRLDICL_MB0
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: g8rc, preferred-register: '' }
+  - { id: 1, class: g8rc, preferred-register: '' }
+liveins:         
+  - { reg: '$x3', virtual-reg: '%0' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0.entry:
+    liveins: $x3
+  
+    %0 = LI8 32
+    %1 = RLDICL %0, 60, 0
+    ; CHECK: LI8 2
+    ; CHECK-LATE: li 3, 2
+    $x3 = COPY %1
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
 ...
 ---
 name:            testRLDICL_rec
diff --git a/llvm/test/CodeGen/PowerPC/early-ret.mir b/llvm/test/CodeGen/PowerPC/early-ret.mir
index 6897b208bb927..f534fd0e2702d 100644
--- a/llvm/test/CodeGen/PowerPC/early-ret.mir
+++ b/llvm/test/CodeGen/PowerPC/early-ret.mir
@@ -1,6 +1,39 @@
 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -run-pass=ppc-early-ret -o \
 # RUN:   - %s -verify-machineinstrs | FileCheck %s
 
+---
+name:            testBLR
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $r3, $r4
+
+    renamable $cr0 = CMPWI renamable $r3, 0
+    BC killed renamable $cr0gt, %bb.1
+    B %bb.2
+
+  bb.1.entry:
+    successors: %bb.2(0x80000000)
+    liveins: $r4
+
+    renamable $r3 = ADDI killed renamable $r4, 0
+
+  bb.2.entry:
+    liveins: $r3, $r4, $cr0eq, $cr0lt, $cr0un, $cr0, $cr0gt, $r3, $r3, $r4, $r3, $cr0gt
+
+    BLR implicit $lr, implicit $rm, implicit killed $r3
+
+  ; CHECK-LABEL: name: testBLR
+  ; CHECK: bb.0.entry:
+  ; CHECK:   renamable $cr0 = CMPWI renamable $r3, 0
+  ; CHECK:   BC killed renamable $cr0gt, %bb.1
+  ; CHECK:   BLR implicit $lr, implicit $rm, implicit $lr, implicit $rm, implicit killed $r3
+  ; CHECK: bb.1.entry:
+  ; CHECK:   renamable $r3 = ADDI killed renamable $r4, 0
+  ; CHECK:   BLR implicit $lr, implicit $rm, implicit killed $r3
+...
+
+
 ---
 name:            testBCLRn
 body:             |
@@ -81,3 +114,33 @@ body:             |
   ; CHECK:   $v2 = VOR killed $v3, $v3
   ; CHECK:   BLR implicit $lr, implicit $rm, implicit killed $v2
 ...
+
+
+---
+name:            testBCCLR
+body:             |
+  bb.0.entry:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+
+    renamable $r4 = LI 0
+    renamable $cr0 = CMPLWI killed renamable $r4, 0
+    BCC 68, renamable $cr0, %bb.2
+
+  bb.1:
+    successors: %bb.2(0x40000000)
+    liveins: $cr0
+
+    BCC 68, killed renamable $cr0, %bb.2
+
+  bb.2:
+    BLR implicit $lr, implicit $rm
+
+  ; CHECK-LABEL: name: testBCCLR
+  ; CHECK: bb.0.entry:
+  ; CHECK: renamable $r4 = LI 0
+  ; CHECK: renamable $cr0 = CMPLWI killed renamable $r4, 0
+  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm, implicit $lr, implicit $rm
+  ; CHECK: bb.1:
+  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm, implicit $lr, implicit $rm
+  ; CHECK: BLR implicit $lr, implicit $rm
+...
diff --git a/llvm/test/CodeGen/PowerPC/fma-precision.ll b/llvm/test/CodeGen/PowerPC/fma-precision.ll
index 24c304d26e5fd..89b5e097d8a6d 100644
--- a/llvm/test/CodeGen/PowerPC/fma-precision.ll
+++ b/llvm/test/CodeGen/PowerPC/fma-precision.ll
@@ -5,10 +5,10 @@
 define double @fsub1(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fsub1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsmuldp 3, 4, 3
 ; CHECK-NEXT:    xsmuldp 0, 2, 1
-; CHECK-NEXT:    xsmsubadp 3, 2, 1
-; CHECK-NEXT:    xsmuldp 1, 0, 3
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    xsnmsubadp 1, 4, 3
+; CHECK-NEXT:    xsmuldp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
   %mul = fmul fast double %b, %a
@@ -97,3 +97,67 @@ entry:
   %add = fadd fast double %mul1, %mul
   ret double %add
 }
+
+define double @fma_multi_uses1(double %a, double %b, double %c, double %d, double* %p1, double* %p2, double* %p3) {
+; CHECK-LABEL: fma_multi_uses1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xsmuldp 1, 1, 2
+; CHECK-NEXT:    xsmuldp 0, 3, 4
+; CHECK-NEXT:    stfd 1, 0(7)
+; CHECK-NEXT:    stfd 1, 0(8)
+; CHECK-NEXT:    xsnmsubadp 1, 3, 4
+; CHECK-NEXT:    stfd 0, 0(9)
+; CHECK-NEXT:    blr
+  %ab = fmul fast double %a, %b
+  %cd = fmul fast double %c, %d
+  store double %ab, double* %p1 ; extra use of %ab
+  store double %ab, double* %p2 ; another extra use of %ab
+  store double %cd, double* %p3 ; extra use of %cd
+  %r = fsub fast double %ab, %cd
+  ret double %r
+}
+
+define double @fma_multi_uses2(double %a, double %b, double %c, double %d, double* %p1, double* %p2, double* %p3) {
+; CHECK-LABEL: fma_multi_uses2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xsmuldp 5, 1, 2
+; CHECK-NEXT:    xsmuldp 0, 3, 4
+; CHECK-NEXT:    stfd 5, 0(7)
+; CHECK-NEXT:    stfd 0, 0(8)
+; CHECK-NEXT:    stfd 0, 0(9)
+; CHECK-NEXT:    xsmsubadp 0, 1, 2
+; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    blr
+  %ab = fmul fast double %a, %b
+  %cd = fmul fast double %c, %d
+  store double %ab, double* %p1 ; extra use of %ab
+  store double %cd, double* %p2 ; extra use of %cd
+  store double %cd, double* %p3 ; another extra use of %cd
+  %r = fsub fast double %ab, %cd
+  ret double %r
+}
+
+define double @fma_multi_uses3(double %a, double %b, double %c, double %d, double %f, double %g, double* %p1, double* %p2, double* %p3) {
+; CHECK-LABEL: fma_multi_uses3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xsmuldp 0, 1, 2
+; CHECK-NEXT:    xsmuldp 1, 5, 6
+; CHECK-NEXT:    ld 3, 96(1)
+; CHECK-NEXT:    stfd 0, 0(9)
+; CHECK-NEXT:    stfd 0, 0(10)
+; CHECK-NEXT:    stfd 1, 0(3)
+; CHECK-NEXT:    xsnmsubadp 1, 3, 4
+; CHECK-NEXT:    xsnmsubadp 0, 3, 4
+; CHECK-NEXT:    xsadddp 1, 0, 1
+; CHECK-NEXT:    blr
+  %ab = fmul fast double %a, %b
+  %cd = fmul fast double %c, %d
+  %fg = fmul fast double %f, %g
+  store double %ab, double* %p1 ; extra use of %ab
+  store double %ab, double* %p2 ; another extra use of %ab
+  store double %fg, double* %p3 ; extra use of %fg
+  %q = fsub fast double %fg, %cd ; The uses of %cd reduce to 1 after %r is folded. 2 uses of %fg, fold %cd, remove def of %cd
+  %r = fsub fast double %ab, %cd ; Fold %r before %q. 3 uses of %ab, 2 uses of %cd, fold %cd
+  %add = fadd fast double %r, %q
+  ret double %add
+}
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt.mir b/llvm/test/CodeGen/PowerPC/ifcvt.mir
new file mode 100644
index 0000000000000..b54c972baa17f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ifcvt.mir
@@ -0,0 +1,53 @@
+# RUN: llc -mtriple=ppc32-- -run-pass=if-converter -o - -verify-machineinstrs \
+# RUN:   %s | FileCheck %s
+
+---
+name:            testBDZLR
+body:             |
+  bb.0.entry:
+    successors: %bb.5(0x40000000), %bb.1(0x40000000)
+    liveins: $r3
+  
+    renamable $r4 = LI 0
+    renamable $cr0 = CMPLWI killed renamable $r4, 0
+    BCC 68, renamable $cr0, %bb.5
+  
+  bb.1:
+    successors: %bb.2(0x40000000), %bb.5(0x40000000)
+    liveins: $cr0, $r3
+  
+    BCC 68, killed renamable $cr0, %bb.5
+  
+  bb.2:
+    successors: %bb.3(0x80000000)
+    liveins: $r3
+  
+    MTCTRloop killed renamable $r3, implicit-def dead $ctr
+    renamable $r3 = LI 0
+    renamable $r5 = IMPLICIT_DEF
+    renamable $r4 = LI 0
+  
+  bb.3:
+    successors: %bb.4(0x7c000000), %bb.5(0x04000000)
+    liveins: $r3, $r4, $r5
+  
+    renamable $r6 = RLWINM renamable $r4, 3, 0, 28
+    renamable $r4 = ADDIC killed renamable $r4, 1, implicit-def $carry
+    renamable $r5 = ADD4 killed renamable $r5, killed renamable $r6
+    renamable $r6 = ADD4 killed renamable $r6, renamable $r6
+    renamable $r3 = ADDZE killed renamable $r3, implicit-def dead $carry, implicit $carry
+    BDZ %bb.5, implicit-def $ctr, implicit $ctr
+  
+  bb.4:
+    successors: %bb.3(0x80000000)
+    liveins: $r3, $r4
+  
+    B %bb.3
+  
+  bb.5:
+    BLR implicit $lr, implicit $rm
+
+
+  ; CHECK-LABEL: name: testBDZLR
+  ; CHECK: BDZLR implicit $lr, implicit $rm
+...
diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
index f6efcdd7d8528..ce2f93871359a 100644
--- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -35,8 +35,8 @@ define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) {
 define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) {
 ; CHECK-LABEL: zeroEqualityTest01:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld 5, 0(3)
-; CHECK-NEXT:    ld 6, 0(4)
+; CHECK-NEXT:    ldx 5, 0, 3
+; CHECK-NEXT:    ldx 6, 0, 4
 ; CHECK-NEXT:    cmpld 5, 6
 ; CHECK-NEXT:    bne 0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %loadbb1
@@ -125,7 +125,7 @@ define signext i32 @equalityFoldTwoConstants() {
 define signext i32 @equalityFoldOneConstant(i8* %X) {
 ; CHECK-LABEL: equalityFoldOneConstant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld 4, 0(3)
+; CHECK-NEXT:    ldx 4, 0, 3
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    sldi 5, 5, 32
 ; CHECK-NEXT:    cmpld 4, 5
diff --git a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
index 298ce90b74ee4..181683e7a7f48 100644
--- a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
+++ b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
@@ -8,8 +8,8 @@
 define zeroext i1 @opeq1(
 ; PPC64LE-LABEL: opeq1:
 ; PPC64LE:       # %bb.0: # %"entry+land.rhs.i"
-; PPC64LE-NEXT:    ld 3, 0(3)
-; PPC64LE-NEXT:    ld 4, 0(4)
+; PPC64LE-NEXT:    ldx 3, 0, 3
+; PPC64LE-NEXT:    ldx 4, 0, 4
 ; PPC64LE-NEXT:    xor 3, 3, 4
 ; PPC64LE-NEXT:    cntlzd 3, 3
 ; PPC64LE-NEXT:    rldicl 3, 3, 58, 63
diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll
index 7323d1e775b16..7fb9b07152eff 100644
--- a/llvm/test/CodeGen/PowerPC/recipest.ll
+++ b/llvm/test/CodeGen/PowerPC/recipest.ll
@@ -177,12 +177,11 @@ define float @rsqrt_fmul_fmf(float %a, float %b, float %c) {
 ; CHECK-NEXT:    fmuls 1, 1, 0
 ; CHECK-NEXT:    fmadds 1, 1, 0, 4
 ; CHECK-NEXT:    fmuls 0, 0, 5
-; CHECK-NEXT:    fres 5, 2
+; CHECK-NEXT:    fmuls 0, 0, 1
+; CHECK-NEXT:    fres 1, 2
 ; CHECK-NEXT:    fmuls 4, 0, 1
-; CHECK-NEXT:    fmuls 4, 4, 5
-; CHECK-NEXT:    fmuls 2, 2, 4
-; CHECK-NEXT:    fmsubs 0, 0, 1, 2
-; CHECK-NEXT:    fmadds 0, 5, 0, 4
+; CHECK-NEXT:    fnmsubs 0, 2, 4, 0
+; CHECK-NEXT:    fmadds 0, 1, 0, 4
 ; CHECK-NEXT:    fmuls 1, 3, 0
 ; CHECK-NEXT:    blr
   %x = call fast float @llvm.sqrt.f32(float %a)
diff --git a/llvm/test/CodeGen/PowerPC/rotl-2.ll b/llvm/test/CodeGen/PowerPC/rotl-2.ll
index 43d34f6f8c73f..d69c0eaf77f60 100644
--- a/llvm/test/CodeGen/PowerPC/rotl-2.ll
+++ b/llvm/test/CodeGen/PowerPC/rotl-2.ll
@@ -1,9 +1,11 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | grep rotlwi | count 2
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | grep clrlwi | count 2
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | grep rotlw | count 4
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32--  | not grep or
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s
 
 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
+; CHECK-LABEL: rotl32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rotlw 3, 3, 4
+; CHECK-NEXT:    blr
 	%shift.upgrd.1 = zext i8 %Amt to i32		; <i32> [#uses=1]
 	%B = shl i32 %A, %shift.upgrd.1		; <i32> [#uses=1]
 	%Amt2 = sub i8 32, %Amt		; <i8> [#uses=1]
@@ -14,6 +16,11 @@ define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
 }
 
 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
+; CHECK-LABEL: rotr32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subfic 4, 4, 32
+; CHECK-NEXT:    rotlw 3, 3, 4
+; CHECK-NEXT:    blr
 	%shift.upgrd.3 = zext i8 %Amt to i32		; <i32> [#uses=1]
 	%B = lshr i32 %A, %shift.upgrd.3		; <i32> [#uses=1]
 	%Amt2 = sub i8 32, %Amt		; <i8> [#uses=1]
@@ -24,6 +31,10 @@ define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
 }
 
 define i32 @rotli32(i32 %A) nounwind {
+; CHECK-LABEL: rotli32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rotlwi 3, 3, 5
+; CHECK-NEXT:    blr
 	%B = shl i32 %A, 5		; <i32> [#uses=1]
 	%C = lshr i32 %A, 27		; <i32> [#uses=1]
 	%D = or i32 %B, %C		; <i32> [#uses=1]
@@ -31,6 +42,10 @@ define i32 @rotli32(i32 %A) nounwind {
 }
 
 define i32 @rotri32(i32 %A) nounwind {
+; CHECK-LABEL: rotri32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rotlwi 3, 3, 27
+; CHECK-NEXT:    blr
 	%B = lshr i32 %A, 5		; <i32> [#uses=1]
 	%C = shl i32 %A, 27		; <i32> [#uses=1]
 	%D = or i32 %B, %C		; <i32> [#uses=1]
diff --git a/llvm/test/CodeGen/RISCV/compress-float.ll b/llvm/test/CodeGen/RISCV/compress-float.ll
index c18ac1d5ab148..89ba6463285aa 100644
--- a/llvm/test/CodeGen/RISCV/compress-float.ll
+++ b/llvm/test/CodeGen/RISCV/compress-float.ll
@@ -7,21 +7,21 @@
 ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
 ; RUN:   -disable-block-placement < %t.tgtattr \
-; RUN:   | llvm-objdump -d -triple=riscv32 -mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.fnattr
 ; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f,+d" }' >> %t.fnattr
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \
 ; RUN:   -disable-block-placement < %t.fnattr \
-; RUN:   | llvm-objdump -d -triple=riscv32 -mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 ;
 ; RUN: cat %s > %t.mixedattr
 ; RUN: echo 'attributes #0 = { nounwind "target-features"="+f,+d" }' >> %t.mixedattr
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c -filetype=obj \
 ; RUN:   -disable-block-placement < %t.mixedattr \
-; RUN:   | llvm-objdump -d -triple=riscv32 -mattr=+c,+f,+d -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 
 ; This acts as a sanity check for the codegen instruction compression path,
diff --git a/llvm/test/CodeGen/RISCV/compress-inline-asm.ll b/llvm/test/CodeGen/RISCV/compress-inline-asm.ll
index 6b58566d2bbec..5a29b8c6c57f5 100644
--- a/llvm/test/CodeGen/RISCV/compress-inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/compress-inline-asm.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+c  -filetype=obj < %s\
-; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\
+; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\
 ; RUN: | FileCheck -check-prefix=CHECK %s
 
 @ext = external global i32
diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll
index f6caf5e8f6904..21547e671e9b3 100644
--- a/llvm/test/CodeGen/RISCV/compress.ll
+++ b/llvm/test/CodeGen/RISCV/compress.ll
@@ -5,14 +5,14 @@
 ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
 ; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \
 ; RUN:   -disable-block-placement < %t.tgtattr \
-; RUN:   | llvm-objdump -d -triple=riscv32 -mattr=+c -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IC %s
 ;
 ; RUN: cat %s > %t.fnattr
 ; RUN: echo 'attributes #0 = { nounwind "target-features"="+c" }' >> %t.fnattr
 ; RUN: llc -mtriple=riscv32 -filetype=obj \
 ; RUN:   -disable-block-placement < %t.fnattr \
-; RUN:   | llvm-objdump -d -triple=riscv32 -mattr=+c -M no-aliases - \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IC %s
 
 ; This acts as a sanity check for the codegen instruction compression path,
diff --git a/llvm/test/CodeGen/RISCV/option-norvc.ll b/llvm/test/CodeGen/RISCV/option-norvc.ll
index 063c48c9cb83f..785322d2cc25f 100644
--- a/llvm/test/CodeGen/RISCV/option-norvc.ll
+++ b/llvm/test/CodeGen/RISCV/option-norvc.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+c  -filetype=obj < %s\
-; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\
+; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\
 ; RUN: | FileCheck -check-prefix=CHECK %s
 
 ; This test demonstrates that .option norvc has no effect on codegen when
diff --git a/llvm/test/CodeGen/RISCV/option-rvc.ll b/llvm/test/CodeGen/RISCV/option-rvc.ll
index 43829fe164bd1..6234af27a3276 100644
--- a/llvm/test/CodeGen/RISCV/option-rvc.ll
+++ b/llvm/test/CodeGen/RISCV/option-rvc.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=riscv32 -filetype=obj < %s\
-; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -M no-aliases -\
+; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases -\
 ; RUN: | FileCheck -check-prefix=CHECK %s
 
 ; This test demonstrates that .option norvc has no effect on codegen when
diff --git a/llvm/test/CodeGen/SystemZ/rot-01.ll b/llvm/test/CodeGen/SystemZ/rot-01.ll
index ea275e68df546..fc0a6821c49ae 100644
--- a/llvm/test/CodeGen/SystemZ/rot-01.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test shortening of NILL to NILF when the result is used as a rotate amount.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,9 +6,11 @@
 ; Test 32-bit rotate.
 define i32 @f1(i32 %val, i32 %amt) {
 ; CHECK-LABEL: f1:
-; CHECK: nill %r3, 31
-; CHECK: rll %r2, %r2, 0(%r3)
-  %mod = urem i32 %amt, 32
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 15
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
+  %mod = urem i32 %amt, 16
 
   %inv = sub i32 32, %mod
   %parta = shl i32 %val, %mod
@@ -21,8 +24,10 @@ define i32 @f1(i32 %val, i32 %amt) {
 ; Test 64-bit rotate.
 define i64 @f2(i64 %val, i64 %amt) {
 ; CHECK-LABEL: f2:
-; CHECK: nill %r3, 31
-; CHECK: rllg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %mod = urem i64 %amt, 32
 
   %inv = sub i64 64, %mod
diff --git a/llvm/test/CodeGen/SystemZ/rot-02.ll b/llvm/test/CodeGen/SystemZ/rot-02.ll
index 12b09f131850f..491951f637bbf 100644
--- a/llvm/test/CodeGen/SystemZ/rot-02.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-02.ll
@@ -1,14 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test removal of AND operations that don't affect last 6 bits of rotate amount
 ; operand.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-; Test that AND is not removed when some lower 6 bits are not set.
+; Test that AND is not removed when some lower 5 bits are not set.
 define i32 @f1(i32 %val, i32 %amt) {
 ; CHECK-LABEL: f1:
-; CHECK: nil{{[lf]}} %r3, 31
-; CHECK: rll %r2, %r2, 0(%r3)
-  %and = and i32 %amt, 31
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 15
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
+  %and = and i32 %amt, 15
 
   %inv = sub i32 32, %and
   %parta = shl i32 %val, %and
@@ -22,8 +25,9 @@ define i32 @f1(i32 %val, i32 %amt) {
 ; Test removal of AND mask with only bottom 6 bits set.
 define i32 @f2(i32 %val, i32 %amt) {
 ; CHECK-LABEL: f2:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: rll %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %amt, 63
 
   %inv = sub i32 32, %and
@@ -38,8 +42,9 @@ define i32 @f2(i32 %val, i32 %amt) {
 ; Test removal of AND mask including but not limited to bottom 6 bits.
 define i32 @f3(i32 %val, i32 %amt) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: nil{{[lf]}} %r3, 255
-; CHECK: rll %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %amt, 255
 
   %inv = sub i32 32, %and
@@ -54,8 +59,9 @@ define i32 @f3(i32 %val, i32 %amt) {
 ; Test removal of AND mask from RLLG.
 define i64 @f4(i64 %val, i64 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: rllg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %amt, 63
 
   %inv = sub i64 64, %and
@@ -70,9 +76,11 @@ define i64 @f4(i64 %val, i64 %amt) {
 ; Test that AND is not entirely removed if the result is reused.
 define i32 @f5(i32 %val, i32 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: nil{{[lf]}} %r3, 63
-; CHECK: ar %r2, %r3
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    nilf %r3, 63
+; CHECK-NEXT:    ar %r2, %r3
+; CHECK-NEXT:    br %r14
   %and = and i32 %amt, 63
 
   %inv = sub i32 32, %and
diff --git a/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll b/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
index c29f6ab996c61..29adcf6b5a11a 100644
--- a/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-shift-64-sub-amt.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test that the case of (64 - shift) used by a shift/rotate instruction is
 ; implemented with an lcr. This should also work for any multiple of 64.
 ;
@@ -5,8 +6,10 @@
 
 define i64 @f1(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f1:
-; CHECK: lcr %r1, %r3
-; CHECK: sllg %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 64, %sh
   %shl = shl i64 %in, %sub
   ret i64 %shl
@@ -14,8 +17,10 @@ define i64 @f1(i64 %in, i64 %sh) {
 
 define i64 @f2(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f2:
-; CHECK: lcr %r1, %r3
-; CHECK: srag %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    srag %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 64, %sh
   %shl = ashr i64 %in, %sub
   ret i64 %shl
@@ -23,8 +28,10 @@ define i64 @f2(i64 %in, i64 %sh) {
 
 define i64 @f3(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f3:
-; CHECK: lcr %r1, %r3
-; CHECK: srlg %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 64, %sh
   %shl = lshr i64 %in, %sub
   ret i64 %shl
@@ -32,8 +39,10 @@ define i64 @f3(i64 %in, i64 %sh) {
 
 define i64 @f4(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f4:
-; CHECK: lcr %r1, %r3
-; CHECK: rllg %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %shr = lshr i64 %in, %sh
   %sub = sub i64 64, %sh
   %shl = shl i64 %in, %sub
@@ -43,8 +52,10 @@ define i64 @f4(i64 %in, i64 %sh) {
 
 define i64 @f5(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f5:
-; CHECK: lcr %r1, %r3
-; CHECK: sllg %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 128, %sh
   %shl = shl i64 %in, %sub
   ret i64 %shl
@@ -52,8 +63,10 @@ define i64 @f5(i64 %in, i64 %sh) {
 
 define i64 @f6(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f6:
-; CHECK: lcr %r1, %r3
-; CHECK: srag %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    srag %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 256, %sh
   %shl = ashr i64 %in, %sub
   ret i64 %shl
@@ -61,8 +74,10 @@ define i64 @f6(i64 %in, i64 %sh) {
 
 define i64 @f7(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f7:
-; CHECK: lcr %r1, %r3
-; CHECK: srlg %r2, %r2, 0(%r1)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 512, %sh
   %shl = lshr i64 %in, %sub
   ret i64 %shl
@@ -70,10 +85,12 @@ define i64 @f7(i64 %in, i64 %sh) {
 
 define i64 @f8(i64 %in, i64 %sh) {
 ; CHECK-LABEL: f8:
-; CHECK: lcr %r1, %r3
-; CHECK: srlg %r0, %r2, 0(%r3)
-; CHECK: sllg %r2, %r2, 0(%r1)
-; CHECK: ogr %r2, %r0
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lcr %r1, %r3
+; CHECK-NEXT:    srlg %r0, %r2, 0(%r3)
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    ogr %r2, %r0
+; CHECK-NEXT:    br %r14
   %shr = lshr i64 %in, %sh
   %sub = sub i64 1024, %sh
   %shl = shl i64 %in, %sub
diff --git a/llvm/test/CodeGen/SystemZ/shift-01.ll b/llvm/test/CodeGen/SystemZ/shift-01.ll
index 924c623832870..9c1142d633aad 100644
--- a/llvm/test/CodeGen/SystemZ/shift-01.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit shifts left.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the SLL range.
 define i32 @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: sll %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 1
+; CHECK-NEXT:    br %r14
   %shift = shl i32 %a, 1
   ret i32 %shift
 }
@@ -14,8 +16,9 @@ define i32 @f1(i32 %a) {
 ; Check the high end of the defined SLL range.
 define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: sll %r2, 31
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 31
+; CHECK-NEXT:    br %r14
   %shift = shl i32 %a, 31
   ret i32 %shift
 }
@@ -23,8 +26,8 @@ define i32 @f2(i32 %a) {
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: sll %r2, 32
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    br %r14
   %shift = shl i32 %a, 32
   ret i32 %shift
 }
@@ -32,8 +35,10 @@ define i32 @f3(i32 %a) {
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK-NOT: sll %r2, -1{{.*}}
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ahi %r3, -1
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i32 %amt, 1
   %shift = shl i32 %a, %sub
   ret i32 %shift
@@ -42,8 +47,9 @@ define i32 @f4(i32 %a, i32 %amt) {
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: sll %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %shift = shl i32 %a, %amt
   ret i32 %shift
 }
@@ -51,8 +57,9 @@ define i32 @f5(i32 %a, i32 %amt) {
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: sll %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %shift = shl i32 %a, %add
   ret i32 %shift
@@ -61,8 +68,9 @@ define i32 @f6(i32 %a, i32 %amt) {
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: sll %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %trunc = trunc i64 %add to i32
   %shift = shl i32 %a, %trunc
@@ -73,8 +81,9 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: sll %r2, 4095(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 4095(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 4095
   %shift = shl i32 %a, %add
   ret i32 %shift
@@ -83,9 +92,10 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: ahi %r3, 4096
-; CHECK: sll %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ahi %r3, 4096
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 4096
   %shift = shl i32 %a, %add
   ret i32 %shift
@@ -94,9 +104,10 @@ define i32 @f9(i32 %a, i32 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f10:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: sll %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ar %r3, %r4
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %b, %c
   %shift = shl i32 %a, %add
   ret i32 %shift
@@ -105,9 +116,10 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
 ; CHECK-LABEL: f11:
-; CHECK: l %r1, 0(%r3)
-; CHECK: sll %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 0(%r3)
+; CHECK-NEXT:    sll %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i32, i32 *%ptr
   %shift = shl i32 %a, %amt
   ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-02.ll b/llvm/test/CodeGen/SystemZ/shift-02.ll
index e9cbb2b1a8f83..cf3e69d556d5e 100644
--- a/llvm/test/CodeGen/SystemZ/shift-02.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit logical shifts right.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the SRL range.
 define i32 @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: srl %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 1
+; CHECK-NEXT:    br %r14
   %shift = lshr i32 %a, 1
   ret i32 %shift
 }
@@ -14,8 +16,9 @@ define i32 @f1(i32 %a) {
 ; Check the high end of the defined SRL range.
 define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: srl %r2, 31
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 31
+; CHECK-NEXT:    br %r14
   %shift = lshr i32 %a, 31
   ret i32 %shift
 }
@@ -23,8 +26,8 @@ define i32 @f2(i32 %a) {
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: srl %r2, 32
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    br %r14
   %shift = lshr i32 %a, 32
   ret i32 %shift
 }
@@ -32,8 +35,10 @@ define i32 @f3(i32 %a) {
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK-NOT: srl %r2, -1{{.*}}
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ahi %r3, -1
+; CHECK-NEXT:    srl %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i32 %amt, 1
   %shift = lshr i32 %a, %sub
   ret i32 %shift
@@ -42,8 +47,9 @@ define i32 @f4(i32 %a, i32 %amt) {
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: srl %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %shift = lshr i32 %a, %amt
   ret i32 %shift
 }
@@ -51,8 +57,9 @@ define i32 @f5(i32 %a, i32 %amt) {
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: srl %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %shift = lshr i32 %a, %add
   ret i32 %shift
@@ -61,8 +68,9 @@ define i32 @f6(i32 %a, i32 %amt) {
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: srl %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %trunc = trunc i64 %add to i32
   %shift = lshr i32 %a, %trunc
@@ -73,8 +81,9 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: srl %r2, 4095(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 4095(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 4095
   %shift = lshr i32 %a, %add
   ret i32 %shift
@@ -83,9 +92,10 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: ahi %r3, 4096
-; CHECK: srl %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ahi %r3, 4096
+; CHECK-NEXT:    srl %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 4096
   %shift = lshr i32 %a, %add
   ret i32 %shift
@@ -94,9 +104,10 @@ define i32 @f9(i32 %a, i32 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f10:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: srl %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ar %r3, %r4
+; CHECK-NEXT:    srl %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %b, %c
   %shift = lshr i32 %a, %add
   ret i32 %shift
@@ -105,9 +116,10 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
 ; CHECK-LABEL: f11:
-; CHECK: l %r1, 0(%r3)
-; CHECK: srl %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 0(%r3)
+; CHECK-NEXT:    srl %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i32, i32 *%ptr
   %shift = lshr i32 %a, %amt
   ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-03.ll b/llvm/test/CodeGen/SystemZ/shift-03.ll
index 13cdbb0ea5faa..e5a95f9707b56 100644
--- a/llvm/test/CodeGen/SystemZ/shift-03.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit arithmetic shifts right.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the SRA range.
 define i32 @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: sra %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 1
+; CHECK-NEXT:    br %r14
   %shift = ashr i32 %a, 1
   ret i32 %shift
 }
@@ -14,8 +16,9 @@ define i32 @f1(i32 %a) {
 ; Check the high end of the defined SRA range.
 define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: sra %r2, 31
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 31
+; CHECK-NEXT:    br %r14
   %shift = ashr i32 %a, 31
   ret i32 %shift
 }
@@ -23,8 +26,8 @@ define i32 @f2(i32 %a) {
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: sra %r2, 32
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    br %r14
   %shift = ashr i32 %a, 32
   ret i32 %shift
 }
@@ -32,8 +35,10 @@ define i32 @f3(i32 %a) {
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK-NOT: sra %r2, -1{{.*}}
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ahi %r3, -1
+; CHECK-NEXT:    sra %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i32 %amt, 1
   %shift = ashr i32 %a, %sub
   ret i32 %shift
@@ -42,8 +47,9 @@ define i32 @f4(i32 %a, i32 %amt) {
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: sra %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %shift = ashr i32 %a, %amt
   ret i32 %shift
 }
@@ -51,8 +57,9 @@ define i32 @f5(i32 %a, i32 %amt) {
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: sra %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %shift = ashr i32 %a, %add
   ret i32 %shift
@@ -61,8 +68,9 @@ define i32 @f6(i32 %a, i32 %amt) {
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: sra %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %trunc = trunc i64 %add to i32
   %shift = ashr i32 %a, %trunc
@@ -73,8 +81,9 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: sra %r2, 4095(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 4095(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 4095
   %shift = ashr i32 %a, %add
   ret i32 %shift
@@ -83,9 +92,10 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: ahi %r3, 4096
-; CHECK: sra %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ahi %r3, 4096
+; CHECK-NEXT:    sra %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 4096
   %shift = ashr i32 %a, %add
   ret i32 %shift
@@ -94,9 +104,10 @@ define i32 @f9(i32 %a, i32 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f10:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: sra %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ar %r3, %r4
+; CHECK-NEXT:    sra %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %b, %c
   %shift = ashr i32 %a, %add
   ret i32 %shift
@@ -105,9 +116,10 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
 ; CHECK-LABEL: f11:
-; CHECK: l %r1, 0(%r3)
-; CHECK: sra %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 0(%r3)
+; CHECK-NEXT:    sra %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i32, i32 *%ptr
   %shift = ashr i32 %a, %amt
   ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-04.ll b/llvm/test/CodeGen/SystemZ/shift-04.ll
index bdabc54322ad8..b2967b72d159e 100644
--- a/llvm/test/CodeGen/SystemZ/shift-04.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit rotates left.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the RLL range.
 define i32 @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: rll %r2, %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 1
+; CHECK-NEXT:    br %r14
   %parta = shl i32 %a, 1
   %partb = lshr i32 %a, 31
   %or = or i32 %parta, %partb
@@ -16,8 +18,9 @@ define i32 @f1(i32 %a) {
 ; Check the high end of the defined RLL range.
 define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: rll %r2, %r2, 31
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 31
+; CHECK-NEXT:    br %r14
   %parta = shl i32 %a, 31
   %partb = lshr i32 %a, 1
   %or = or i32 %parta, %partb
@@ -27,8 +30,9 @@ define i32 @f2(i32 %a) {
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: rll
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lhi %r2, -1
+; CHECK-NEXT:    br %r14
   %parta = shl i32 %a, 32
   %partb = lshr i32 %a, 0
   %or = or i32 %parta, %partb
@@ -38,8 +42,9 @@ define i32 @f3(i32 %a) {
 ; Check variable shifts.
 define i32 @f4(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %amtb = sub i32 32, %amt
   %parta = shl i32 %a, %amt
   %partb = lshr i32 %a, %amtb
@@ -50,8 +55,9 @@ define i32 @f4(i32 %a, i32 %amt) {
 ; Check shift amounts that have a constant term.
 define i32 @f5(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %sub = sub i32 32, %add
   %parta = shl i32 %a, %add
@@ -63,8 +69,9 @@ define i32 @f5(i32 %a, i32 %amt) {
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f6(i32 %a, i64 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %addtrunc = trunc i64 %add to i32
   %sub = sub i32 32, %addtrunc
@@ -77,8 +84,9 @@ define i32 @f6(i32 %a, i64 %amt) {
 ; ...and again with a different truncation representation.
 define i32 @f7(i32 %a, i64 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %sub = sub i64 32, %add
   %addtrunc = trunc i64 %add to i32
@@ -89,12 +97,13 @@ define i32 @f7(i32 %a, i64 %amt) {
   ret i32 %or
 }
 
-; Check shift amounts that have the largest in-range constant term.  We could
-; mask the amount instead.
+; Check shift amounts that have the largest in-range constant term, and then
+; mask the amount.
 define i32 @f8(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: rll %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 524287
   %sub = sub i32 32, %add
   %parta = shl i32 %a, %add
@@ -107,9 +116,10 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; addition.
 define i32 @f9(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: afi %r3, 524288
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, 524288
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 524288
   %sub = sub i32 32, %add
   %parta = shl i32 %a, %add
@@ -121,8 +131,9 @@ define i32 @f9(i32 %a, i32 %amt) {
 ; Check cases where 1 is subtracted from the shift amount.
 define i32 @f10(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f10:
-; CHECK: rll %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %suba = sub i32 %amt, 1
   %subb = sub i32 32, %suba
   %parta = shl i32 %a, %suba
@@ -135,8 +146,9 @@ define i32 @f10(i32 %a, i32 %amt) {
 ; Again, we could mask the shift amount instead.
 define i32 @f11(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f11:
-; CHECK: rll %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, -524288(%r3)
+; CHECK-NEXT:    br %r14
   %suba = sub i32 %amt, 524288
   %subb = sub i32 32, %suba
   %parta = shl i32 %a, %suba
@@ -145,13 +157,12 @@ define i32 @f11(i32 %a, i32 %amt) {
   ret i32 %or
 }
 
-; Check the next value down, which without masking must use a separate
-; addition.
+; Check the next value down, masking the amount removes the addition.
 define i32 @f12(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f12:
-; CHECK: afi %r3, -524289
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %suba = sub i32 %amt, 524289
   %subb = sub i32 32, %suba
   %parta = shl i32 %a, %suba
@@ -163,9 +174,10 @@ define i32 @f12(i32 %a, i32 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f13(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f13:
-; CHECK: ar {{%r3, %r4|%r4, %r3}}
-; CHECK: rll %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ar %r3, %r4
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %b, %c
   %sub = sub i32 32, %add
   %parta = shl i32 %a, %add
@@ -177,9 +189,10 @@ define i32 @f13(i32 %a, i32 %b, i32 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f14(i32 %a, i32 *%ptr) {
 ; CHECK-LABEL: f14:
-; CHECK: l %r1, 0(%r3)
-; CHECK: rll %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 0(%r3)
+; CHECK-NEXT:    rll %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i32, i32 *%ptr
   %amtb = sub i32 32, %amt
   %parta = shl i32 %a, %amt
@@ -192,8 +205,9 @@ define i32 @f14(i32 %a, i32 *%ptr) {
 ; instcombine.
 define i32 @f15(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f15:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %sub = sub i32 22, %amt
   %parta = shl i32 %a, %add
@@ -205,8 +219,9 @@ define i32 @f15(i32 %a, i32 %amt) {
 ; Likewise for f7.
 define i32 @f16(i32 %a, i64 %amt) {
 ; CHECK-LABEL: f16:
-; CHECK: rll %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rll %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %sub = sub i64 22, %amt
   %addtrunc = trunc i64 %add to i32
@@ -220,8 +235,9 @@ define i32 @f16(i32 %a, i64 %amt) {
 ; Check cases where (-x & 31) is used instead of 32 - x.
 define i32 @f17(i32 %x, i32 %y) {
 ; CHECK-LABEL: f17:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
 entry:
   %shl = shl i32 %x, %y
   %sub = sub i32 0, %y
@@ -234,8 +250,9 @@ entry:
 ; ...and again with ((32 - x) & 31).
 define i32 @f18(i32 %x, i32 %y) {
 ; CHECK-LABEL: f18:
-; CHECK: rll %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rll %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
 entry:
   %shl = shl i32 %x, %y
   %sub = sub i32 32, %y
@@ -248,8 +265,15 @@ entry:
 ; This is not a rotation.
 define i32 @f19(i32 %x, i32 %y) {
 ; CHECK-LABEL: f19:
-; CHECK-NOT: rll
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lr %r0, %r2
+; CHECK-NEXT:    sll %r0, 0(%r3)
+; CHECK-NEXT:    lhi %r1, 16
+; CHECK-NEXT:    sr %r1, %r3
+; CHECK-NEXT:    nill %r1, 31
+; CHECK-NEXT:    srl %r2, 0(%r1)
+; CHECK-NEXT:    or %r2, %r0
+; CHECK-NEXT:    br %r14
 entry:
   %shl = shl i32 %x, %y
   %sub = sub i32 16, %y
@@ -262,8 +286,9 @@ entry:
 ; Repeat f17 with an addition on the shift count.
 define i32 @f20(i32 %x, i32 %y) {
 ; CHECK-LABEL: f20:
-; CHECK: rll %r2, %r2, 199(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rll %r2, %r2, 199(%r3)
+; CHECK-NEXT:    br %r14
 entry:
   %add = add i32 %y, 199
   %shl = shl i32 %x, %add
@@ -277,8 +302,9 @@ entry:
 ; ...and again with the InstCombine version.
 define i32 @f21(i32 %x, i32 %y) {
 ; CHECK-LABEL: f21:
-; CHECK: rll %r2, %r2, 199(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rll %r2, %r2, 199(%r3)
+; CHECK-NEXT:    br %r14
 entry:
   %add = add i32 %y, 199
   %shl = shl i32 %x, %add
diff --git a/llvm/test/CodeGen/SystemZ/shift-05.ll b/llvm/test/CodeGen/SystemZ/shift-05.ll
index 625ec9b0b92c9..f1062aca35741 100644
--- a/llvm/test/CodeGen/SystemZ/shift-05.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit shifts left.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the SLLG range.
 define i64 @f1(i64 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: sllg %r2, %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 1
+; CHECK-NEXT:    br %r14
   %shift = shl i64 %a, 1
   ret i64 %shift
 }
@@ -14,8 +16,9 @@ define i64 @f1(i64 %a) {
 ; Check the high end of the defined SLLG range.
 define i64 @f2(i64 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: sllg %r2, %r2, 63
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 63
+; CHECK-NEXT:    br %r14
   %shift = shl i64 %a, 63
   ret i64 %shift
 }
@@ -23,8 +26,8 @@ define i64 @f2(i64 %a) {
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: sllg
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    br %r14
   %shift = shl i64 %a, 64
   ret i64 %shift
 }
@@ -32,8 +35,9 @@ define i64 @f3(i64 %a) {
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK: sllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %shift = shl i64 %a, %amt
   ret i64 %shift
 }
@@ -41,8 +45,9 @@ define i64 @f4(i64 %a, i64 %amt) {
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: sllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %shift = shl i64 %a, %add
   ret i64 %shift
@@ -51,8 +56,9 @@ define i64 @f5(i64 %a, i64 %amt) {
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: sllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %addext = sext i32 %add to i64
   %shift = shl i64 %a, %addext
@@ -62,8 +68,9 @@ define i64 @f6(i64 %a, i32 %amt) {
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: sllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %addext = zext i32 %add to i64
   %shift = shl i64 %a, %addext
@@ -74,8 +81,9 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: sllg %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 524287(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524287
   %shift = shl i64 %a, %add
   ret i64 %shift
@@ -85,9 +93,10 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: sllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, 524288
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524288
   %shift = shl i64 %a, %add
   ret i64 %shift
@@ -96,8 +105,9 @@ define i64 @f9(i64 %a, i64 %amt) {
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f10:
-; CHECK: sllg %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 1
   %shift = shl i64 %a, %sub
   ret i64 %shift
@@ -107,8 +117,9 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f11:
-; CHECK: sllg %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, -524288(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 524288
   %shift = shl i64 %a, %sub
   ret i64 %shift
@@ -118,9 +129,10 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: sllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, -524289
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 524289
   %shift = shl i64 %a, %sub
   ret i64 %shift
@@ -129,9 +141,10 @@ define i64 @f12(i64 %a, i64 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: sllg %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    agr %r3, %r4
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %b, %c
   %shift = shl i64 %a, %add
   ret i64 %shift
@@ -140,9 +153,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: sllg %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 4(%r3)
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i64, i64 *%ptr
   %shift = shl i64 %a, %amt
   ret i64 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-06.ll b/llvm/test/CodeGen/SystemZ/shift-06.ll
index 6769fbb4343e0..e956e6293f485 100644
--- a/llvm/test/CodeGen/SystemZ/shift-06.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-06.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit logical shifts right.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the SRLG range.
 define i64 @f1(i64 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: srlg %r2, %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 1
+; CHECK-NEXT:    br %r14
   %shift = lshr i64 %a, 1
   ret i64 %shift
 }
@@ -14,8 +16,9 @@ define i64 @f1(i64 %a) {
 ; Check the high end of the defined SRLG range.
 define i64 @f2(i64 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: srlg %r2, %r2, 63
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 63
+; CHECK-NEXT:    br %r14
   %shift = lshr i64 %a, 63
   ret i64 %shift
 }
@@ -23,8 +26,8 @@ define i64 @f2(i64 %a) {
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: srlg
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    br %r14
   %shift = lshr i64 %a, 64
   ret i64 %shift
 }
@@ -32,8 +35,9 @@ define i64 @f3(i64 %a) {
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK: srlg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %shift = lshr i64 %a, %amt
   ret i64 %shift
 }
@@ -41,8 +45,9 @@ define i64 @f4(i64 %a, i64 %amt) {
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: srlg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %shift = lshr i64 %a, %add
   ret i64 %shift
@@ -51,8 +56,9 @@ define i64 @f5(i64 %a, i64 %amt) {
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: srlg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %addext = sext i32 %add to i64
   %shift = lshr i64 %a, %addext
@@ -62,8 +68,9 @@ define i64 @f6(i64 %a, i32 %amt) {
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: srlg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %addext = zext i32 %add to i64
   %shift = lshr i64 %a, %addext
@@ -74,8 +81,9 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: srlg %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 524287(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524287
   %shift = lshr i64 %a, %add
   ret i64 %shift
@@ -85,9 +93,10 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: srlg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, 524288
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524288
   %shift = lshr i64 %a, %add
   ret i64 %shift
@@ -96,8 +105,9 @@ define i64 @f9(i64 %a, i64 %amt) {
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f10:
-; CHECK: srlg %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 1
   %shift = lshr i64 %a, %sub
   ret i64 %shift
@@ -107,8 +117,9 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f11:
-; CHECK: srlg %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, -524288(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 524288
   %shift = lshr i64 %a, %sub
   ret i64 %shift
@@ -118,9 +129,10 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: srlg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, -524289
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 524289
   %shift = lshr i64 %a, %sub
   ret i64 %shift
@@ -129,9 +141,10 @@ define i64 @f12(i64 %a, i64 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: srlg %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    agr %r3, %r4
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %b, %c
   %shift = lshr i64 %a, %add
   ret i64 %shift
@@ -140,9 +153,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: srlg %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 4(%r3)
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i64, i64 *%ptr
   %shift = lshr i64 %a, %amt
   ret i64 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-07.ll b/llvm/test/CodeGen/SystemZ/shift-07.ll
index e0a11f6e6ed1e..fb2712d084b70 100644
--- a/llvm/test/CodeGen/SystemZ/shift-07.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-07.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit arithmetic shifts right.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the SRAG range.
 define i64 @f1(i64 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: srag %r2, %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 1
+; CHECK-NEXT:    br %r14
   %shift = ashr i64 %a, 1
   ret i64 %shift
 }
@@ -14,8 +16,9 @@ define i64 @f1(i64 %a) {
 ; Check the high end of the defined SRAG range.
 define i64 @f2(i64 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: srag %r2, %r2, 63
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 63
+; CHECK-NEXT:    br %r14
   %shift = ashr i64 %a, 63
   ret i64 %shift
 }
@@ -23,8 +26,8 @@ define i64 @f2(i64 %a) {
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: srag
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    br %r14
   %shift = ashr i64 %a, 64
   ret i64 %shift
 }
@@ -32,8 +35,9 @@ define i64 @f3(i64 %a) {
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK: srag %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %shift = ashr i64 %a, %amt
   ret i64 %shift
 }
@@ -41,8 +45,9 @@ define i64 @f4(i64 %a, i64 %amt) {
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: srag %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %shift = ashr i64 %a, %add
   ret i64 %shift
@@ -51,8 +56,9 @@ define i64 @f5(i64 %a, i64 %amt) {
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: srag %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %addext = sext i32 %add to i64
   %shift = ashr i64 %a, %addext
@@ -62,8 +68,9 @@ define i64 @f6(i64 %a, i32 %amt) {
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: srag %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %addext = zext i32 %add to i64
   %shift = ashr i64 %a, %addext
@@ -74,8 +81,9 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: srag %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 524287(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524287
   %shift = ashr i64 %a, %add
   ret i64 %shift
@@ -85,9 +93,10 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: srag %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, 524288
+; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524288
   %shift = ashr i64 %a, %add
   ret i64 %shift
@@ -96,8 +105,9 @@ define i64 @f9(i64 %a, i64 %amt) {
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f10:
-; CHECK: srag %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 1
   %shift = ashr i64 %a, %sub
   ret i64 %shift
@@ -107,8 +117,9 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f11:
-; CHECK: srag %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, -524288(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 524288
   %shift = ashr i64 %a, %sub
   ret i64 %shift
@@ -118,9 +129,10 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: srag %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, -524289
+; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %sub = sub i64 %amt, 524289
   %shift = ashr i64 %a, %sub
   ret i64 %shift
@@ -129,9 +141,10 @@ define i64 @f12(i64 %a, i64 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: srag %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    agr %r3, %r4
+; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %b, %c
   %shift = ashr i64 %a, %add
   ret i64 %shift
@@ -140,9 +153,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: srag %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 4(%r3)
+; CHECK-NEXT:    srag %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i64, i64 *%ptr
   %shift = ashr i64 %a, %amt
   ret i64 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-08.ll b/llvm/test/CodeGen/SystemZ/shift-08.ll
index 027b05f73134b..d91afd620c09b 100644
--- a/llvm/test/CodeGen/SystemZ/shift-08.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-08.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test 32-bit rotates left.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check the low end of the RLLG range.
 define i64 @f1(i64 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: rllg %r2, %r2, 1
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 1
+; CHECK-NEXT:    br %r14
   %parta = shl i64 %a, 1
   %partb = lshr i64 %a, 63
   %or = or i64 %parta, %partb
@@ -16,8 +18,9 @@ define i64 @f1(i64 %a) {
 ; Check the high end of the defined RLLG range.
 define i64 @f2(i64 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: rllg %r2, %r2, 63
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 63
+; CHECK-NEXT:    br %r14
   %parta = shl i64 %a, 63
   %partb = lshr i64 %a, 1
   %or = or i64 %parta, %partb
@@ -27,8 +30,9 @@ define i64 @f2(i64 %a) {
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: rllg
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lghi %r2, -1
+; CHECK-NEXT:    br %r14
   %parta = shl i64 %a, 64
   %partb = lshr i64 %a, 0
   %or = or i64 %parta, %partb
@@ -38,8 +42,9 @@ define i64 @f3(i64 %a) {
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK: rllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %amtb = sub i64 64, %amt
   %parta = shl i64 %a, %amt
   %partb = lshr i64 %a, %amtb
@@ -50,8 +55,9 @@ define i64 @f4(i64 %a, i64 %amt) {
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: rllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 10
   %sub = sub i64 64, %add
   %parta = shl i64 %a, %add
@@ -63,8 +69,9 @@ define i64 @f5(i64 %a, i64 %amt) {
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: rllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %sub = sub i32 64, %add
   %addext = sext i32 %add to i64
@@ -78,8 +85,9 @@ define i64 @f6(i64 %a, i32 %amt) {
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
 ; CHECK-LABEL: f7:
-; CHECK: rllg %r2, %r2, 10(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, 10(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 10
   %sub = sub i32 64, %add
   %addext = zext i32 %add to i64
@@ -90,12 +98,13 @@ define i64 @f7(i64 %a, i32 %amt) {
   ret i64 %or
 }
 
-; Check shift amounts that have the largest in-range constant term.  We could
-; mask the amount instead.
+; Check shift amounts that have the largest in-range constant term, and then
+; mask the amount.
 define i64 @f8(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f8:
-; CHECK: rllg %r2, %r2, 524287(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524287
   %sub = sub i64 64, %add
   %parta = shl i64 %a, %add
@@ -108,9 +117,10 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f9:
-; CHECK: a{{g?}}fi %r3, 524288
-; CHECK: rllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    afi %r3, 524288
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %amt, 524288
   %sub = sub i64 64, %add
   %parta = shl i64 %a, %add
@@ -122,8 +132,9 @@ define i64 @f9(i64 %a, i64 %amt) {
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f10:
-; CHECK: rllg %r2, %r2, -1(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %suba = sub i64 %amt, 1
   %subb = sub i64 64, %suba
   %parta = shl i64 %a, %suba
@@ -136,8 +147,9 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f11:
-; CHECK: rllg %r2, %r2, -524288(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, -524288(%r3)
+; CHECK-NEXT:    br %r14
   %suba = sub i64 %amt, 524288
   %subb = sub i64 64, %suba
   %parta = shl i64 %a, %suba
@@ -146,13 +158,12 @@ define i64 @f11(i64 %a, i64 %amt) {
   ret i64 %or
 }
 
-; Check the next value down, which without masking must use a separate
-; addition.
+; Check the next value down, masking the amount removes the addition.
 define i64 @f12(i64 %a, i64 %amt) {
 ; CHECK-LABEL: f12:
-; CHECK: a{{g?}}fi %r3, -524289
-; CHECK: rllg %r2, %r2, 0(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rllg %r2, %r2, -1(%r3)
+; CHECK-NEXT:    br %r14
   %suba = sub i64 %amt, 524289
   %subb = sub i64 64, %suba
   %parta = shl i64 %a, %suba
@@ -164,9 +175,10 @@ define i64 @f12(i64 %a, i64 %amt) {
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: f13:
-; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
-; CHECK: rllg %r2, %r2, 0({{%r[34]}})
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    agr %r3, %r4
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i64 %b, %c
   %sub = sub i64 64, %add
   %parta = shl i64 %a, %add
@@ -178,9 +190,10 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
 ; CHECK-LABEL: f14:
-; CHECK: l %r1, 4(%r3)
-; CHECK: rllg %r2, %r2, 0(%r1)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    l %r1, 4(%r3)
+; CHECK-NEXT:    rllg %r2, %r2, 0(%r1)
+; CHECK-NEXT:    br %r14
   %amt = load i64, i64 *%ptr
   %amtb = sub i64 64, %amt
   %parta = shl i64 %a, %amt
diff --git a/llvm/test/CodeGen/SystemZ/shift-09.ll b/llvm/test/CodeGen/SystemZ/shift-09.ll
index c87cf0d9a1ee8..0822c7a44bf24 100644
--- a/llvm/test/CodeGen/SystemZ/shift-09.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-09.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test three-operand shifts.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
@@ -5,8 +6,9 @@
 ; Check that we use SLLK over SLL where useful.
 define i32 @f1(i32 %a, i32 %b, i32 %amt) {
 ; CHECK-LABEL: f1:
-; CHECK: sllk %r2, %r3, 15(%r4)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllk %r2, %r3, 15(%r4)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 15
   %shift = shl i32 %b, %add
   ret i32 %shift
@@ -15,8 +17,9 @@ define i32 @f1(i32 %a, i32 %b, i32 %amt) {
 ; Check that we use SLL over SLLK where possible.
 define i32 @f2(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f2:
-; CHECK: sll %r2, 15(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 15(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 15
   %shift = shl i32 %a, %add
   ret i32 %shift
@@ -25,8 +28,9 @@ define i32 @f2(i32 %a, i32 %amt) {
 ; Check that we use SRLK over SRL where useful.
 define i32 @f3(i32 %a, i32 %b, i32 %amt) {
 ; CHECK-LABEL: f3:
-; CHECK: srlk %r2, %r3, 15(%r4)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlk %r2, %r3, 15(%r4)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 15
   %shift = lshr i32 %b, %add
   ret i32 %shift
@@ -35,8 +39,9 @@ define i32 @f3(i32 %a, i32 %b, i32 %amt) {
 ; Check that we use SRL over SRLK where possible.
 define i32 @f4(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f4:
-; CHECK: srl %r2, 15(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 15(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 15
   %shift = lshr i32 %a, %add
   ret i32 %shift
@@ -45,8 +50,9 @@ define i32 @f4(i32 %a, i32 %amt) {
 ; Check that we use SRAK over SRA where useful.
 define i32 @f5(i32 %a, i32 %b, i32 %amt) {
 ; CHECK-LABEL: f5:
-; CHECK: srak %r2, %r3, 15(%r4)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srak %r2, %r3, 15(%r4)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 15
   %shift = ashr i32 %b, %add
   ret i32 %shift
@@ -55,8 +61,9 @@ define i32 @f5(i32 %a, i32 %b, i32 %amt) {
 ; Check that we use SRA over SRAK where possible.
 define i32 @f6(i32 %a, i32 %amt) {
 ; CHECK-LABEL: f6:
-; CHECK: sra %r2, 15(%r3)
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 15(%r3)
+; CHECK-NEXT:    br %r14
   %add = add i32 %amt, 15
   %shift = ashr i32 %a, %add
   ret i32 %shift
diff --git a/llvm/test/CodeGen/SystemZ/shift-10.ll b/llvm/test/CodeGen/SystemZ/shift-10.ll
index 176f7dea8c354..711ec5d38eb81 100644
--- a/llvm/test/CodeGen/SystemZ/shift-10.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-10.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test compound shifts.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,9 +6,11 @@
 ; Test a shift right followed by a sign extension.  This can use two shifts.
 define i64 @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: risbg %r0, %r2, 63, 191, 63
-; CHECK: lcgr  %r2, %r0
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbg %r0, %r2, 63, 191, 63
+; CHECK-NEXT:    lcgr %r2, %r0
+; CHECK-NEXT:    br %r14
   %shr = lshr i32 %a, 1
   %trunc = trunc i32 %shr to i1
   %ext = sext i1 %trunc to i64
@@ -18,9 +21,11 @@ define i64 @f1(i32 %a) {
 ; ashr/sext pair.
 define i64 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: risbg %r0, %r2, 63, 191, 34
-; CHECK: lcgr  %r2, %r0
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbg %r0, %r2, 63, 191, 34
+; CHECK-NEXT:    lcgr %r2, %r0
+; CHECK-NEXT:    br %r14
   %shr = lshr i32 %a, 30
   %trunc = trunc i32 %shr to i1
   %ext = sext i1 %trunc to i64
@@ -31,8 +36,10 @@ define i64 @f2(i32 %a) {
 ; is possible.
 define i64 @f3(i32 %a) {
 ; CHECK-LABEL: f3:
-; CHECK: risbg %r2, %r2, 27, 181, 9
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbg %r2, %r2, 27, 181, 9
+; CHECK-NEXT:    br %r14
   %shr = lshr i32 %a, 1
   %ext = zext i32 %shr to i64
   %shl = shl i64 %ext, 10
@@ -43,8 +50,10 @@ define i64 @f3(i32 %a) {
 ; ...and again with a larger right shift.
 define i64 @f4(i32 %a) {
 ; CHECK-LABEL: f4:
-; CHECK: risbg %r2, %r2, 30, 158, 3
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbg %r2, %r2, 30, 158, 3
+; CHECK-NEXT:    br %r14
   %shr = lshr i32 %a, 30
   %ext = sext i32 %shr to i64
   %shl = shl i64 %ext, 33
@@ -56,9 +65,11 @@ define i64 @f4(i32 %a) {
 ; bottom 3 matter.
 define i64 @f5(i32 %a) {
 ; CHECK-LABEL: f5:
-; CHECK: risbg %r2, %r2, 29, 158, 3
-; CHECK: lhi %r2, 7
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    risbg %r2, %r2, 29, 158, 3
+; CHECK-NEXT:    lhi %r2, 7
+; CHECK-NEXT:    br %r14
   %shr = lshr i32 %a, 30
   %ext = sext i32 %shr to i64
   %shl = shl i64 %ext, 33
@@ -70,8 +81,9 @@ define i64 @f5(i32 %a) {
 ; that matters.
 define i64 @f6(i64 %a) {
 ; CHECK-LABEL: f6:
-; CHECK: risbg %r2, %r2, 55, 183, 19
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    risbg %r2, %r2, 55, 183, 19
+; CHECK-NEXT:    br %r14
   %shl = shl i64 %a, 10
   %shr = ashr i64 %shl, 60
   %and = and i64 %shr, 256
@@ -81,9 +93,11 @@ define i64 @f6(i64 %a) {
 ; Test another form of f1.
 define i64 @f7(i32 %a) {
 ; CHECK-LABEL: f7:
-; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
-; CHECK: srag %r2, [[REG]], 63
-; CHECK: br %r14
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT:    sllg %r0, %r2, 62
+; CHECK-NEXT:    srag %r2, %r0, 63
+; CHECK-NEXT:    br %r14
   %1 = shl i32 %a, 30
   %sext = ashr i32 %1, 31
   %ext = sext i32 %sext to i64
diff --git a/llvm/test/CodeGen/SystemZ/shift-11.ll b/llvm/test/CodeGen/SystemZ/shift-11.ll
index 3d6fc6a05143d..fab9fde9d6d75 100644
--- a/llvm/test/CodeGen/SystemZ/shift-11.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-11.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test shortening of NILL to NILF when the result is used as a shift amount.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -5,8 +6,10 @@
 ; Test logical shift right.
 define i32 @f1(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f1:
-; CHECK: nill %r3, 31
-; CHECK: srl %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    srl %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 31
   %shift = lshr i32 %a, %and
   ret i32 %shift
@@ -15,8 +18,10 @@ define i32 @f1(i32 %a, i32 %sh) {
 ; Test arithmetic shift right.
 define i32 @f2(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f2:
-; CHECK: nill %r3, 31
-; CHECK: sra %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    sra %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 31
   %shift = ashr i32 %a, %and
   ret i32 %shift
@@ -25,8 +30,10 @@ define i32 @f2(i32 %a, i32 %sh) {
 ; Test shift left.
 define i32 @f3(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f3:
-; CHECK: nill %r3, 31
-; CHECK: sll %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 31
   %shift = shl i32 %a, %and
   ret i32 %shift
@@ -35,8 +42,10 @@ define i32 @f3(i32 %a, i32 %sh) {
 ; Test 64-bit logical shift right.
 define i64 @f4(i64 %a, i64 %sh) {
 ; CHECK-LABEL: f4:
-; CHECK: nill %r3, 31
-; CHECK: srlg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, 31
   %shift = lshr i64 %a, %and
   ret i64 %shift
@@ -45,8 +54,10 @@ define i64 @f4(i64 %a, i64 %sh) {
 ; Test 64-bit arithmetic shift right.
 define i64 @f5(i64 %a, i64 %sh) {
 ; CHECK-LABEL: f5:
-; CHECK: nill %r3, 31
-; CHECK: srag %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, 31
   %shift = ashr i64 %a, %and
   ret i64 %shift
@@ -55,8 +66,10 @@ define i64 @f5(i64 %a, i64 %sh) {
 ; Test 64-bit shift left.
 define i64 @f6(i64 %a, i64 %sh) {
 ; CHECK-LABEL: f6:
-; CHECK: nill %r3, 31
-; CHECK: sllg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, 31
   %shift = shl i64 %a, %and
   ret i64 %shift
@@ -65,8 +78,10 @@ define i64 @f6(i64 %a, i64 %sh) {
 ; Test shift with negative 32-bit value.
 define i32 @f8(i32 %a, i32 %sh, i32 %test) {
 ; CHECK-LABEL: f8:
-; CHECK: nill %r3, 65529
-; CHECK: sll %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 65529
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, -7
   %shift = shl i32 %a, %and
 
@@ -76,8 +91,10 @@ define i32 @f8(i32 %a, i32 %sh, i32 %test) {
 ; Test shift with negative 64-bit value.
 define i64 @f9(i64 %a, i64 %sh, i64 %test) {
 ; CHECK-LABEL: f9:
-; CHECK: nill %r3, 65529
-; CHECK: sllg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 65529
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, -7
   %shift = shl i64 %a, %and
 
diff --git a/llvm/test/CodeGen/SystemZ/shift-12.ll b/llvm/test/CodeGen/SystemZ/shift-12.ll
index 53d3d5362dfdb..7559602aa2565 100644
--- a/llvm/test/CodeGen/SystemZ/shift-12.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-12.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test removal of AND operations that don't affect last 6 bits of shift amount
 ; operand.
 ;
@@ -6,8 +7,10 @@
 ; Test that AND is not removed when some lower 6 bits are not set.
 define i32 @f1(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f1:
-; CHECK: nil{{[lf]}} %r3, 31
-; CHECK: sll %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nill %r3, 31
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 31
   %shift = shl i32 %a, %and
   ret i32 %shift
@@ -16,8 +19,9 @@ define i32 @f1(i32 %a, i32 %sh) {
 ; Test removal of AND mask with only bottom 6 bits set.
 define i32 @f2(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f2:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: sll %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 63
   %shift = shl i32 %a, %and
   ret i32 %shift
@@ -26,8 +30,9 @@ define i32 @f2(i32 %a, i32 %sh) {
 ; Test removal of AND mask including but not limited to bottom 6 bits.
 define i32 @f3(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f3:
-; CHECK-NOT: nil{{[lf]}} %r3, 255
-; CHECK: sll %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 255
   %shift = shl i32 %a, %and
   ret i32 %shift
@@ -36,8 +41,9 @@ define i32 @f3(i32 %a, i32 %sh) {
 ; Test removal of AND mask from SRA.
 define i32 @f4(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f4:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: sra %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sra %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 63
   %shift = ashr i32 %a, %and
   ret i32 %shift
@@ -46,8 +52,9 @@ define i32 @f4(i32 %a, i32 %sh) {
 ; Test removal of AND mask from SRL.
 define i32 @f5(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f5:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: srl %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srl %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 63
   %shift = lshr i32 %a, %and
   ret i32 %shift
@@ -56,8 +63,9 @@ define i32 @f5(i32 %a, i32 %sh) {
 ; Test removal of AND mask from SLLG.
 define i64 @f6(i64 %a, i64 %sh) {
 ; CHECK-LABEL: f6:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: sllg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, 63
   %shift = shl i64 %a, %and
   ret i64 %shift
@@ -66,8 +74,9 @@ define i64 @f6(i64 %a, i64 %sh) {
 ; Test removal of AND mask from SRAG.
 define i64 @f7(i64 %a, i64 %sh) {
 ; CHECK-LABEL: f7:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: srag %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, 63
   %shift = ashr i64 %a, %and
   ret i64 %shift
@@ -76,8 +85,9 @@ define i64 @f7(i64 %a, i64 %sh) {
 ; Test removal of AND mask from SRLG.
 define i64 @f8(i64 %a, i64 %sh) {
 ; CHECK-LABEL: f8:
-; CHECK-NOT: nil{{[lf]}} %r3, 63
-; CHECK: srlg %r2, %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i64 %sh, 63
   %shift = lshr i64 %a, %and
   ret i64 %shift
@@ -86,8 +96,10 @@ define i64 @f8(i64 %a, i64 %sh) {
 ; Test that AND with two register operands is not affected.
 define i32 @f9(i32 %a, i32 %b, i32 %sh) {
 ; CHECK-LABEL: f9:
-; CHECK: nr %r3, %r4
-; CHECK: sll %r2, 0(%r3)
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nr %r3, %r4
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, %b
   %shift = shl i32 %a, %and
   ret i32 %shift
@@ -96,9 +108,11 @@ define i32 @f9(i32 %a, i32 %b, i32 %sh) {
 ; Test that AND is not entirely removed if the result is reused.
 define i32 @f10(i32 %a, i32 %sh) {
 ; CHECK-LABEL: f10:
-; CHECK: sll %r2, 0(%r3)
-; CHECK: nil{{[lf]}} %r3, 63
-; CHECK: ar %r2, %r3
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sll %r2, 0(%r3)
+; CHECK-NEXT:    nilf %r3, 63
+; CHECK-NEXT:    ar %r2, %r3
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 63
   %shift = shl i32 %a, %and
   %reuse = add i32 %and, %shift
@@ -108,8 +122,29 @@ define i32 @f10(i32 %a, i32 %sh) {
 ; Test that AND is not removed for i128 (which calls __ashlti3)
 define i128 @f11(i128 %a, i32 %sh) {
 ; CHECK-LABEL: f11:
-; CHECK: risbg %r4, %r4, 57, 191, 0
-; CHECK: brasl %r14, __ashlti3@PLT
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT:    .cfi_offset %r13, -56
+; CHECK-NEXT:    .cfi_offset %r14, -48
+; CHECK-NEXT:    .cfi_offset %r15, -40
+; CHECK-NEXT:    aghi %r15, -192
+; CHECK-NEXT:    .cfi_def_cfa_offset 352
+; CHECK-NEXT:    lg %r0, 8(%r3)
+; CHECK-NEXT:    # kill: def $r4l killed $r4l def $r4d
+; CHECK-NEXT:    lgr %r13, %r2
+; CHECK-NEXT:    lg %r1, 0(%r3)
+; CHECK-NEXT:    stg %r0, 168(%r15)
+; CHECK-NEXT:    risbg %r4, %r4, 57, 191, 0
+; CHECK-NEXT:    la %r2, 176(%r15)
+; CHECK-NEXT:    la %r3, 160(%r15)
+; CHECK-NEXT:    stg %r1, 160(%r15)
+; CHECK-NEXT:    brasl %r14, __ashlti3@PLT
+; CHECK-NEXT:    lg %r0, 184(%r15)
+; CHECK-NEXT:    lg %r1, 176(%r15)
+; CHECK-NEXT:    stg %r0, 8(%r13)
+; CHECK-NEXT:    stg %r1, 0(%r13)
+; CHECK-NEXT:    lmg %r13, %r15, 296(%r15)
+; CHECK-NEXT:    br %r14
   %and = and i32 %sh, 127
   %ext = zext i32 %and to i128
   %shift = shl i128 %a, %ext
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-23.ll b/llvm/test/CodeGen/SystemZ/vec-move-23.ll
new file mode 100644
index 0000000000000..430e879bcc069
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-move-23.ll
@@ -0,0 +1,131 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefixes=CHECK,Z14
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s -check-prefixes=CHECK,Z15
+;
+; Check that int-to-fp conversions from a narrower type get a vector extension.
+
+define void @fun0(<2 x i8> %Src, <2 x double>* %Dst) {
+; CHECK-LABEL: fun0:
+; CHECK:      vuphb	%v0, %v24
+; CHECK-NEXT: vuphh	%v0, %v0
+; CHECK-NEXT: vuphf	%v0, %v0
+; CHECK-NEXT: vcdgb	%v0, %v0, 0, 0
+; CHECK-NEXT: vst	%v0, 0(%r2), 3
+; CHECK-NEXT: br	%r14
+  %c = sitofp <2 x i8> %Src to <2 x double>
+  store <2 x double> %c, <2 x double>* %Dst
+  ret void
+}
+
+define void @fun1(<2 x i16> %Src, <2 x double>* %Dst) {
+; CHECK-LABEL: fun1:
+; CHECK:      vuphh	%v0, %v24
+; CHECK-NEXT: vuphf	%v0, %v0
+; CHECK-NEXT: vcdgb	%v0, %v0, 0, 0
+; CHECK-NEXT: vst	%v0, 0(%r2), 3
+; CHECK-NEXT: br	%r14
+  %c = sitofp <2 x i16> %Src to <2 x double>
+  store <2 x double> %c, <2 x double>* %Dst
+  ret void
+}
+
+define void @fun2(<2 x i32> %Src, <2 x double>* %Dst) {
+; CHECK-LABEL: fun2:
+; CHECK:      vuphf	%v0, %v24
+; CHECK-NEXT: vcdgb	%v0, %v0, 0, 0
+; CHECK-NEXT: vst	%v0, 0(%r2), 3
+; CHECK-NEXT: br	%r14
+  %c = sitofp <2 x i32> %Src to <2 x double>
+  store <2 x double> %c, <2 x double>* %Dst
+  ret void
+}
+
+define void @fun3(<4 x i16> %Src, <4 x float>* %Dst) {
+; CHECK-LABEL: fun3:
+
+; Z14:      vuphh	%v0, %v24
+; Z14-NEXT: vlgvf	%r0, %v0, 3
+; Z14-NEXT: cefbr	%f1, %r0
+; Z14-NEXT: vlgvf	%r0, %v0, 2
+; Z14-NEXT: cefbr	%f2, %r0
+; Z14-NEXT: vlgvf	%r0, %v0, 1
+; Z14-NEXT: vmrhf	%v1, %v2, %v1
+; Z14-NEXT: cefbr	%f2, %r0
+; Z14-NEXT: vlgvf	%r0, %v0, 0
+; Z14-NEXT: cefbr	%f0, %r0
+; Z14-NEXT: vmrhf	%v0, %v0, %v2
+; Z14-NEXT: vmrhg	%v0, %v0, %v1
+; Z14-NEXT: vst	%v0, 0(%r2), 3
+; Z14-NEXT: br	%r14
+
+; Z15:      vuphh	%v0, %v24
+; Z15-NEXT: vcefb	%v0, %v0, 0, 0
+; Z15-NEXT: vst	        %v0, 0(%r2), 3
+; Z15-NEXT: br	        %r14
+  %c = sitofp <4 x i16> %Src to <4 x float>
+  store <4 x float> %c, <4 x float>* %Dst
+  ret void
+}
+
+define void @fun4(<2 x i8> %Src, <2 x double>* %Dst) {
+; CHECK-LABEL: fun4:
+; CHECK:      vuplhb	%v0, %v24
+; CHECK-NEXT: vuplhh	%v0, %v0
+; CHECK-NEXT: vuplhf	%v0, %v0
+; CHECK-NEXT: vcdlgb	%v0, %v0, 0, 0
+; CHECK-NEXT: vst	%v0, 0(%r2), 3
+; CHECK-NEXT: br	%r14
+  %c = uitofp <2 x i8> %Src to <2 x double>
+  store <2 x double> %c, <2 x double>* %Dst
+  ret void
+}
+
+define void @fun5(<2 x i16> %Src, <2 x double>* %Dst) {
+; CHECK-LABEL: fun5:
+; CHECK:      vuplhh	%v0, %v24
+; CHECK-NEXT: vuplhf	%v0, %v0
+; CHECK-NEXT: vcdlgb	%v0, %v0, 0, 0
+; CHECK-NEXT: vst	%v0, 0(%r2), 3
+; CHECK-NEXT: br	%r14
+  %c = uitofp <2 x i16> %Src to <2 x double>
+  store <2 x double> %c, <2 x double>* %Dst
+  ret void
+}
+
+define void @fun6(<2 x i32> %Src, <2 x double>* %Dst) {
+; CHECK-LABEL: fun6:
+; CHECK:      vuplhf	%v0, %v24
+; CHECK-NEXT: vcdlgb	%v0, %v0, 0, 0
+; CHECK-NEXT: vst	%v0, 0(%r2), 3
+; CHECK-NEXT: br	%r14
+  %c = uitofp <2 x i32> %Src to <2 x double>
+  store <2 x double> %c, <2 x double>* %Dst
+  ret void
+}
+
+define void @fun7(<4 x i16> %Src, <4 x float>* %Dst) {
+; CHECK-LABEL: fun7:
+
+; Z14:      vuplhh	%v0, %v24
+; Z14-NEXT: vlgvf	%r0, %v0, 3
+; Z14-NEXT: celfbr	%f1, 0, %r0, 0
+; Z14-NEXT: vlgvf	%r0, %v0, 2
+; Z14-NEXT: celfbr	%f2, 0, %r0, 0
+; Z14-NEXT: vlgvf	%r0, %v0, 1
+; Z14-NEXT: vmrhf	%v1, %v2, %v1
+; Z14-NEXT: celfbr	%f2, 0, %r0, 0
+; Z14-NEXT: vlgvf	%r0, %v0, 0
+; Z14-NEXT: celfbr	%f0, 0, %r0, 0
+; Z14-NEXT: vmrhf	%v0, %v0, %v2
+; Z14-NEXT: vmrhg	%v0, %v0, %v1
+; Z14-NEXT: vst	%v0, 0(%r2), 3
+; Z14-NEXT: br	%r14
+
+; Z15:      vuplhh	%v0, %v24
+; Z15-NEXT: vcelfb	%v0, %v0, 0, 0
+; Z15-NEXT: vst	        %v0, 0(%r2), 3
+; Z15-NEXT: br	        %r14
+  %c = uitofp <4 x i16> %Src to <4 x float>
+  store <4 x float> %c, <4 x float>* %Dst
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/Thumb/large-stack.ll b/llvm/test/CodeGen/Thumb/large-stack.ll
index 0a55ee5dd8a5d..1872eb7dce49e 100644
--- a/llvm/test/CodeGen/Thumb/large-stack.ll
+++ b/llvm/test/CodeGen/Thumb/large-stack.ll
@@ -1,9 +1,9 @@
 ; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
 ; RUN: llc < %s -mtriple=thumb-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
 ; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-ios
-; RUN: llvm-objdump -triple=thumbv6-apple-ios -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
+; RUN: llvm-objdump --triple=thumbv6-apple-ios -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
 ; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-none-eabi
-; RUN: llvm-objdump -triple=thumbv6-none-eabi -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
+; RUN: llvm-objdump --triple=thumbv6-none-eabi -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
 
 ; Largest stack for which a single tADDspi/tSUBspi is enough
 define void @test1() {
diff --git a/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll b/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll
index 146a2223c3570..63726ce18df15 100644
--- a/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll
+++ b/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll
@@ -66,16 +66,13 @@ return:                                           ; preds = %entry, %if.end
 define void @f3(i32 %x) #0 {
 ; CHECK-LABEL: f3:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    cmp r0, #1
-; CHECK-NEXT:    bne .LBB2_2
-; CHECK-NEXT:  @ %bb.1: @ %t
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
-; CHECK-NEXT:    movs r0, #0
-; CHECK-NEXT:    bl fn
-; CHECK-NEXT:    pop.w {r7, lr}
-; CHECK-NEXT:  .LBB2_2: @ %f
-; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    cmp r0, #1
+; CHECK-NEXT:    itt eq
+; CHECK-NEXT:    moveq r0, #0
+; CHECK-NEXT:    bleq fn
+; CHECK-NEXT:    pop {r7, pc}
 entry:
   %p = icmp eq i32 %x, 1
   br i1 %p, label %t, label %f
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
index fcdb29f7e2f29..fdad64e962e6e 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
@@ -101,6 +101,264 @@ entry:
   ret <4 x float> %1
 }
 
+define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
+; CHECK-LABEL: test_vmlaq_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmla.u8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
+  %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %0 = mul <16 x i8> %.splat, %b
+  %1 = add <16 x i8> %0, %a
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
+; CHECK-LABEL: test_vmlaq_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmla.u16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
+  %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %0 = mul <8 x i16> %.splat, %b
+  %1 = add <8 x i16> %0, %a
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vmlaq_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmla.u32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
+  %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %0 = mul <4 x i32> %.splat, %b
+  %1 = add <4 x i32> %0, %a
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c) {
+; CHECK-LABEL: test_vmlaq_n_u8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmla.u8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
+  %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %0 = mul <16 x i8> %.splat, %b
+  %1 = add <16 x i8> %0, %a
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c) {
+; CHECK-LABEL: test_vmlaq_n_u16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmla.u16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
+  %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %0 = mul <8 x i16> %.splat, %b
+  %1 = add <8 x i16> %0, %a
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vmlaq_n_u32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmla.u32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
+  %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %0 = mul <4 x i32> %.splat, %b
+  %1 = add <4 x i32> %0, %a
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
+; CHECK-LABEL: test_vmlasq_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlas.u8 q1, q0, r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = mul <16 x i8> %b, %a
+  %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
+  %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %1 = add <16 x i8> %.splat, %0
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
+; CHECK-LABEL: test_vmlasq_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlas.u16 q1, q0, r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = mul <8 x i16> %b, %a
+  %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
+  %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %1 = add <8 x i16> %.splat, %0
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vmlasq_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlas.u32 q1, q0, r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = mul <4 x i32> %b, %a
+  %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
+  %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %1 = add <4 x i32> %.splat, %0
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c) {
+; CHECK-LABEL: test_vmlasq_n_u8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlas.u8 q1, q0, r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = mul <16 x i8> %b, %a
+  %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
+  %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %1 = add <16 x i8> %.splat, %0
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c) {
+; CHECK-LABEL: test_vmlasq_n_u16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlas.u16 q1, q0, r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = mul <8 x i16> %b, %a
+  %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
+  %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %1 = add <8 x i16> %.splat, %0
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vmlasq_n_u32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlas.u32 q1, q0, r0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = mul <4 x i32> %b, %a
+  %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
+  %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %1 = add <4 x i32> %.splat, %0
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
+; CHECK-LABEL: test_vqdmlahq_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlah.s8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = tail call <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlahq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
+; CHECK-LABEL: test_vqdmlahq_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlah.s16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = tail call <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlahq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vqdmlahq_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlah.s32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
+; CHECK-LABEL: test_vqrdmlahq_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlah.s8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = tail call <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
+; CHECK-LABEL: test_vqrdmlahq_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlah.s16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = tail call <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vqrdmlahq_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlah.s32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlashq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
+; CHECK-LABEL: test_vqrdmlashq_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlash.s8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = tail call <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlashq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
+; CHECK-LABEL: test_vqrdmlashq_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlash.s16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = tail call <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlashq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: test_vqrdmlashq_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlash.s32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)
+  ret <4 x i32> %0
+}
+
 define arm_aapcs_vfpcc <8 x half> @test_vfmaq_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vfmaq_m_f16:
 ; CHECK:       @ %bb.0: @ %entry
@@ -233,6 +491,315 @@ entry:
   ret <4 x float> %3
 }
 
+define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlaq_m_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlat.u8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlaq_m_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlat.u16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlaq_m_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlat.u32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlaq_m_n_u8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlat.u8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlaq_m_n_u16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlat.u16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlaq_m_n_u32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlat.u32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlasq_m_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlast.u8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlasq_m_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlast.u16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlasq_m_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlast.u32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlasq_m_n_u8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlast.u8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlasq_m_n_u16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlast.u16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vmlasq_m_n_u32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vmlast.u32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlahq_m_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlaht.s8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlahq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlahq_m_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlaht.s16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlahq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlahq_m_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlaht.s32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlahq_m_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlaht.s8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlahq_m_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlaht.s16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlahq_m_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlaht.s32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlashq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlashq_m_n_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlasht.s8 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i8 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
+  %3 = tail call <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
+  ret <16 x i8> %3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlashq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlashq_m_n_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlasht.s16 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %c to i32
+  %1 = zext i16 %p to i32
+  %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
+  %3 = tail call <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
+  ret <8 x i16> %3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlashq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlashq_m_n_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r1
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlasht.s32 q0, q1, r0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
 
@@ -240,3 +807,27 @@ declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
 declare <8 x half> @llvm.arm.mve.fma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x half>, <8 x i1>)
 declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>)
+declare <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
+declare <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
+declare <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
+declare <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
+declare <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
+declare <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
+declare <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8>, <16 x i8>, i32)
+declare <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16>, <8 x i16>, i32)
+declare <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32>, <4 x i32>, i32)
+declare <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
+declare <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
+declare <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
+declare <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
+declare <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
+declare <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
+declare <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
+declare <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
+declare <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmlad.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmlad.ll
new file mode 100644
index 0000000000000..0396f96457f43
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmlad.ll
@@ -0,0 +1,589 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqdmladhq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmladh.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqdmladhq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmladh.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqdmladhq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmladh.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqdmladhxq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmladhx.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqdmladhxq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmladhx.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqdmladhxq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmladhx.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqdmlsdhq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlsdh.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqdmlsdhq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlsdh.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqdmlsdhq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlsdh.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqdmlsdhxq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlsdhx.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqdmlsdhxq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlsdhx.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqdmlsdhxq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqdmlsdhx.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqrdmladhq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmladh.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqrdmladhq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmladh.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqrdmladhq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmladh.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqrdmladhxq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmladhx.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqrdmladhxq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmladhx.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqrdmladhxq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmladhx.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqrdmlsdhq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlsdh.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqrdmlsdhq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlsdh.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqrdmlsdhq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlsdh.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhxq_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vqrdmlsdhxq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlsdhx.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhxq_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vqrdmlsdhxq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlsdhx.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhxq_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vqrdmlsdhxq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqrdmlsdhx.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1)
+  ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmladhq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmladht.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmladhq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmladht.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmladhq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmladht.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmladhxq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmladhxt.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmladhxq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmladhxt.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmladhxq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmladhxt.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlsdhq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlsdht.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlsdhq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlsdht.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlsdhq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlsdht.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlsdhxq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlsdhxt.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlsdhxq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlsdhxt.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqdmlsdhxq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqdmlsdhxt.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmladhq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmladht.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmladhq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmladht.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmladhq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmladht.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmladhxq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmladhxt.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmladhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmladhxq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmladhxt.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmladhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmladhxq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmladhxt.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlsdhq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlsdht.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlsdhq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlsdht.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlsdhq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlsdht.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlsdhxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlsdhxq_m_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlsdhxt.s8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
+  %2 = tail call <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1, <16 x i1> %1)
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlsdhxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlsdhxq_m_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlsdhxt.s16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
+  %2 = tail call <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1, <8 x i1> %1)
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlsdhxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
+; CHECK-LABEL: test_vqrdmlsdhxq_m_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vqrdmlsdhxt.s32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = zext i16 %p to i32
+  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
+  %2 = tail call <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1, <4 x i1> %1)
+  ret <4 x i32> %2
+}
+
+declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
+declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
+declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
+
+declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32)
+declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32)
+declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32)
+declare <16 x i8> @llvm.arm.mve.vqdmlad.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32, <16 x i1>)
+declare <8 x i16> @llvm.arm.mve.vqdmlad.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32, <8 x i1>)
+declare <4 x i32> @llvm.arm.mve.vqdmlad.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32, <4 x i1>)
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-ror.ll b/llvm/test/CodeGen/Thumb2/thumb2-ror.ll
index 71b00153c2985..e1a748d8ae256 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-ror.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-ror.ll
@@ -1,21 +1,34 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
-; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=THUMB1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -mtriple=thumb-eabi | FileCheck %s -check-prefix=THUMB1
 
-; CHECK-LABEL: f1:
-; CHECK: 	ror.w	r0, r0, #22
 define i32 @f1(i32 %a) {
+; CHECK-LABEL: f1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ror.w r0, r0, #22
+; CHECK-NEXT:    bx lr
+;
+; THUMB1-LABEL: f1:
+; THUMB1:       @ %bb.0:
+; THUMB1-NEXT:    movs r1, #22
+; THUMB1-NEXT:    rors r0, r1
+; THUMB1-NEXT:    bx lr
     %l8 = shl i32 %a, 10
     %r8 = lshr i32 %a, 22
     %tmp = or i32 %l8, %r8
     ret i32 %tmp
 }
 
-; CHECK-LABEL: f2:
-; CHECK-NOT: and
-; CHECK: ror
-; THUMB1: f2
-; THUMB1: and
 define i32 @f2(i32 %v, i32 %nbits) {
+; CHECK-LABEL: f2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    rors r0, r1
+; CHECK-NEXT:    bx lr
+;
+; THUMB1-LABEL: f2:
+; THUMB1:       @ %bb.0: @ %entry
+; THUMB1-NEXT:    rors r0, r1
+; THUMB1-NEXT:    bx lr
 entry:
   %and = and i32 %nbits, 31
   %shr = lshr i32 %v, %and
diff --git a/llvm/test/CodeGen/X86/2014-08-29-CompactUnwind.ll b/llvm/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
index 9516c374b5808..e0d303e58c328 100644
--- a/llvm/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
+++ b/llvm/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - | llvm-objdump -d -unwind-info -s - | FileCheck %s
+; RUN: llc < %s -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - | llvm-objdump -d --unwind-info -s - | FileCheck %s
 ; Regression test for http://llvm.org/bugs/show_bug.cgi?id=20800.
 
 ; ModuleID = 'asan_report.ii'
diff --git a/llvm/test/CodeGen/X86/avx512-calling-conv.ll b/llvm/test/CodeGen/X86/avx512-calling-conv.ll
index 09fbf9e06c5fd..c42bd502b12a0 100644
--- a/llvm/test/CodeGen/X86/avx512-calling-conv.ll
+++ b/llvm/test/CodeGen/X86/avx512-calling-conv.ll
@@ -3,6 +3,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mcpu=knl -x86-enable-old-knl-abi | FileCheck %s --check-prefix=ALL_X64 --check-prefix=KNL --check-prefix=KNL-OLD
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mcpu=skx | FileCheck %s --check-prefix=ALL_X64 --check-prefix=SKX
 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mcpu=knl | FileCheck %s --check-prefix=KNL_X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mcpu=skx -fast-isel | FileCheck %s --check-prefix=FASTISEL
 
 define <16 x i1> @test1() {
 ; ALL_X64-LABEL: test1:
@@ -14,6 +15,11 @@ define <16 x i1> @test1() {
 ; KNL_X32:       ## %bb.0:
 ; KNL_X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test1:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; FASTISEL-NEXT:    retq
   ret <16 x i1> zeroinitializer
 }
 
@@ -27,6 +33,16 @@ define <16 x i1> @test2(<16 x i1>%a, <16 x i1>%b) {
 ; KNL_X32:       ## %bb.0:
 ; KNL_X32-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test2:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    vpsllw $7, %xmm1, %xmm1
+; FASTISEL-NEXT:    vpmovb2m %xmm1, %k0
+; FASTISEL-NEXT:    vpsllw $7, %xmm0, %xmm0
+; FASTISEL-NEXT:    vpmovb2m %xmm0, %k1
+; FASTISEL-NEXT:    kandw %k0, %k1, %k0
+; FASTISEL-NEXT:    vpmovm2b %k0, %xmm0
+; FASTISEL-NEXT:    retq
   %c = and <16 x i1>%a, %b
   ret <16 x i1> %c
 }
@@ -41,6 +57,16 @@ define <8 x i1> @test3(<8 x i1>%a, <8 x i1>%b) {
 ; KNL_X32:       ## %bb.0:
 ; KNL_X32-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test3:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    vpsllw $15, %xmm1, %xmm1
+; FASTISEL-NEXT:    vpmovw2m %xmm1, %k0
+; FASTISEL-NEXT:    vpsllw $15, %xmm0, %xmm0
+; FASTISEL-NEXT:    vpmovw2m %xmm0, %k1
+; FASTISEL-NEXT:    kandb %k0, %k1, %k0
+; FASTISEL-NEXT:    vpmovm2w %k0, %xmm0
+; FASTISEL-NEXT:    retq
   %c = and <8 x i1>%a, %b
   ret <8 x i1> %c
 }
@@ -55,6 +81,16 @@ define <4 x i1> @test4(<4 x i1>%a, <4 x i1>%b) {
 ; KNL_X32:       ## %bb.0:
 ; KNL_X32-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test4:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    vpslld $31, %xmm1, %xmm1
+; FASTISEL-NEXT:    vpmovd2m %xmm1, %k0
+; FASTISEL-NEXT:    vpslld $31, %xmm0, %xmm0
+; FASTISEL-NEXT:    vpmovd2m %xmm0, %k1
+; FASTISEL-NEXT:    kandw %k0, %k1, %k0
+; FASTISEL-NEXT:    vpmovm2d %k0, %xmm0
+; FASTISEL-NEXT:    retq
   %c = and <4 x i1>%a, %b
   ret <4 x i1> %c
 }
@@ -103,6 +139,20 @@ define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) {
 ; KNL_X32-NEXT:    vpsrad $31, %ymm0, %ymm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test5:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rax
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    vpcmpgtd %ymm1, %ymm0, %k0
+; FASTISEL-NEXT:    vpmovm2w %k0, %xmm0
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    callq _func8xi1
+; FASTISEL-NEXT:    vpsllw $15, %xmm0, %xmm0
+; FASTISEL-NEXT:    vpmovw2m %xmm0, %k0
+; FASTISEL-NEXT:    vpmovm2d %k0, %ymm0
+; FASTISEL-NEXT:    popq %rax
+; FASTISEL-NEXT:    retq
   %cmpRes = icmp sgt <8 x i32>%a, %b
   %resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes)
   %res = sext <8 x i1>%resi to <8 x i32>
@@ -153,6 +203,20 @@ define <16 x i32> @test6(<16 x i32>%a, <16 x i32>%b) {
 ; KNL_X32-NEXT:    vpsrad $31, %zmm0, %zmm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test6:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rax
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    vpcmpgtd %zmm1, %zmm0, %k0
+; FASTISEL-NEXT:    vpmovm2b %k0, %xmm0
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    callq _func16xi1
+; FASTISEL-NEXT:    vpsllw $7, %xmm0, %xmm0
+; FASTISEL-NEXT:    vpmovb2m %xmm0, %k0
+; FASTISEL-NEXT:    vpmovm2d %k0, %zmm0
+; FASTISEL-NEXT:    popq %rax
+; FASTISEL-NEXT:    retq
   %cmpRes = icmp sgt <16 x i32>%a, %b
   %resi = call <16 x i1> @func16xi1(<16 x i1> %cmpRes)
   %res = sext <16 x i1>%resi to <16 x i32>
@@ -183,6 +247,19 @@ define <4 x i32> @test7(<4 x i32>%a, <4 x i32>%b) {
 ; KNL_X32-NEXT:    vpsrad $31, %xmm0, %xmm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test7:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rax
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    vpcmpgtd %xmm1, %xmm0, %k0
+; FASTISEL-NEXT:    vpmovm2d %k0, %xmm0
+; FASTISEL-NEXT:    callq _func4xi1
+; FASTISEL-NEXT:    vpslld $31, %xmm0, %xmm0
+; FASTISEL-NEXT:    vpmovd2m %xmm0, %k0
+; FASTISEL-NEXT:    vpmovm2d %k0, %xmm0
+; FASTISEL-NEXT:    popq %rax
+; FASTISEL-NEXT:    retq
   %cmpRes = icmp sgt <4 x i32>%a, %b
   %resi = call <4 x i1> @func4xi1(<4 x i1> %cmpRes)
   %res = sext <4 x i1>%resi to <4 x i32>
@@ -225,6 +302,18 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
 ; KNL_X32-NEXT:    vandps LCPI7_0, %xmm0, %xmm0
 ; KNL_X32-NEXT:    addl $12, %esp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test7a:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rax
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    vpcmpgtd %ymm1, %ymm0, %k0
+; FASTISEL-NEXT:    vpmovm2w %k0, %xmm0
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    callq _func8xi1
+; FASTISEL-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; FASTISEL-NEXT:    popq %rax
+; FASTISEL-NEXT:    retq
   %cmpRes = icmp sgt <8 x i32>%a, %b
   %resi = call <8 x i1> @func8xi1(<8 x i1> %cmpRes)
   %res = and <8 x i1>%resi,  <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
@@ -249,6 +338,15 @@ define <16 x i8> @test8(<16 x i8> %a1, <16 x i8> %a2, i1 %cond) {
 ; KNL_X32-NEXT:    vmovaps %xmm1, %xmm0
 ; KNL_X32-NEXT:  LBB8_2:
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test8:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    testb $1, %dil
+; FASTISEL-NEXT:    jne LBB8_2
+; FASTISEL-NEXT:  ## %bb.1:
+; FASTISEL-NEXT:    vmovaps %xmm1, %xmm0
+; FASTISEL-NEXT:  LBB8_2:
+; FASTISEL-NEXT:    retq
   %res = select i1 %cond, <16 x i8> %a1, <16 x i8> %a2
   ret <16 x i8> %res
 }
@@ -266,6 +364,12 @@ define i1 @test9(double %a, double %b) {
 ; KNL_X32-NEXT:    vucomisd {{[0-9]+}}(%esp), %xmm0
 ; KNL_X32-NEXT:    setb %al
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test9:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    vucomisd %xmm0, %xmm1
+; FASTISEL-NEXT:    setb %al
+; FASTISEL-NEXT:    retq
   %c = fcmp ugt double %a, %b
   ret i1 %c
 }
@@ -286,6 +390,13 @@ define i32 @test10(i32 %a, i32 %b, i1 %cond) {
 ; KNL_X32-NEXT:    cmovnel %eax, %ecx
 ; KNL_X32-NEXT:    movl (%ecx), %eax
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test10:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    movl %edi, %eax
+; FASTISEL-NEXT:    testb $1, %dl
+; FASTISEL-NEXT:    cmovel %esi, %eax
+; FASTISEL-NEXT:    retq
   %c = select i1 %cond, i32 %a, i32 %b
   ret i32 %c
 }
@@ -303,6 +414,12 @@ define i1 @test11(i32 %a, i32 %b) {
 ; KNL_X32-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; KNL_X32-NEXT:    setg %al
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test11:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    cmpl %esi, %edi
+; FASTISEL-NEXT:    setg %al
+; FASTISEL-NEXT:    retq
   %c = icmp sgt i32 %a, %b
   ret i1 %c
 }
@@ -369,6 +486,34 @@ define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
 ; KNL_X32-NEXT:    popl %edi
 ; KNL_X32-NEXT:    popl %ebx
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test12:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rbp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    pushq %r14
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 24
+; FASTISEL-NEXT:    pushq %rbx
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 32
+; FASTISEL-NEXT:    .cfi_offset %rbx, -32
+; FASTISEL-NEXT:    .cfi_offset %r14, -24
+; FASTISEL-NEXT:    .cfi_offset %rbp, -16
+; FASTISEL-NEXT:    movl %esi, %r14d
+; FASTISEL-NEXT:    movl %edi, %ebp
+; FASTISEL-NEXT:    movl %edx, %esi
+; FASTISEL-NEXT:    callq _test11
+; FASTISEL-NEXT:    movzbl %al, %ebx
+; FASTISEL-NEXT:    movl %ebp, %edi
+; FASTISEL-NEXT:    movl %r14d, %esi
+; FASTISEL-NEXT:    movl %ebx, %edx
+; FASTISEL-NEXT:    callq _test10
+; FASTISEL-NEXT:    xorl %ecx, %ecx
+; FASTISEL-NEXT:    testb $1, %bl
+; FASTISEL-NEXT:    cmovel %ecx, %eax
+; FASTISEL-NEXT:    popq %rbx
+; FASTISEL-NEXT:    popq %r14
+; FASTISEL-NEXT:    popq %rbp
+; FASTISEL-NEXT:    retq
   %cond = call i1 @test11(i32 %a1, i32 %b1)
   %res = call i32 @test10(i32 %a1, i32 %a2, i1 %cond)
   %res1 = select i1 %cond, i32 %res, i32 0
@@ -395,6 +540,13 @@ define <1 x i1> @test13(<1 x i1>* %foo) {
 ; KNL_X32-NEXT:    movzbl (%eax), %eax
 ; KNL_X32-NEXT:    ## kill: def $al killed $al killed $eax
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test13:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    kmovb (%rdi), %k0
+; FASTISEL-NEXT:    kmovd %k0, %eax
+; FASTISEL-NEXT:    ## kill: def $al killed $al killed $eax
+; FASTISEL-NEXT:    retq
   %bar = load <1 x i1>, <1 x i1>* %foo
   ret <1 x i1> %bar
 }
@@ -453,6 +605,19 @@ define void @test14(<32 x i16>* %x) {
 ; KNL_X32-NEXT:    addl $8, %esp
 ; KNL_X32-NEXT:    popl %esi
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test14:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rbx
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    .cfi_offset %rbx, -16
+; FASTISEL-NEXT:    movq %rdi, %rbx
+; FASTISEL-NEXT:    vmovaps (%rdi), %zmm0
+; FASTISEL-NEXT:    callq _test14_callee
+; FASTISEL-NEXT:    vmovaps %zmm0, (%rbx)
+; FASTISEL-NEXT:    popq %rbx
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   %a = load <32 x i16>, <32 x i16>* %x
   %b = call <32 x i16> @test14_callee(<32 x i16> %a)
   store <32 x i16> %b, <32 x i16>* %x
@@ -514,6 +679,19 @@ define void @test15(<64 x i8>* %x) {
 ; KNL_X32-NEXT:    addl $8, %esp
 ; KNL_X32-NEXT:    popl %esi
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: test15:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rbx
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    .cfi_offset %rbx, -16
+; FASTISEL-NEXT:    movq %rdi, %rbx
+; FASTISEL-NEXT:    vmovaps (%rdi), %zmm0
+; FASTISEL-NEXT:    callq _test15_callee
+; FASTISEL-NEXT:    vmovaps %zmm0, (%rbx)
+; FASTISEL-NEXT:    popq %rbx
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   %a = load <64 x i8>, <64 x i8>* %x
   %b = call <64 x i8> @test15_callee(<64 x i8> %a)
   store <64 x i8> %b, <64 x i8>* %x
@@ -1497,6 +1675,321 @@ define <17 x i1> @test16(<17 x i1> %a, <17 x i1> %b) nounwind {
 ; KNL_X32-NEXT:    popl %ebx
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl $4
+;
+; FASTISEL-LABEL: test16:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rbp
+; FASTISEL-NEXT:    pushq %r15
+; FASTISEL-NEXT:    pushq %r14
+; FASTISEL-NEXT:    pushq %r13
+; FASTISEL-NEXT:    pushq %r12
+; FASTISEL-NEXT:    pushq %rbx
+; FASTISEL-NEXT:    movq %rdi, %rax
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    movl $-3, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k2
+; FASTISEL-NEXT:    kmovd %k2, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k2, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $30, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-5, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $29, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-9, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $28, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    movl $-17, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k2
+; FASTISEL-NEXT:    kmovd %k2, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k2, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $27, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-33, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $26, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-65, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $25, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    movl $-129, %edi
+; FASTISEL-NEXT:    kmovd %edi, %k2
+; FASTISEL-NEXT:    kmovd %k2, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k2, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $24, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-257, %edi ## imm = 0xFEFF
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $23, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-513, %edi ## imm = 0xFDFF
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $22, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    movl $-1025, %edi ## imm = 0xFBFF
+; FASTISEL-NEXT:    kmovd %edi, %k6
+; FASTISEL-NEXT:    kandd %k6, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $21, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-2049, %edi ## imm = 0xF7FF
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $20, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-4097, %edi ## imm = 0xEFFF
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovd %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $19, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    movl $-8193, %edi ## imm = 0xDFFF
+; FASTISEL-NEXT:    kmovd %edi, %k4
+; FASTISEL-NEXT:    kandd %k4, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $18, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-16385, %edi ## imm = 0xBFFF
+; FASTISEL-NEXT:    kmovd %edi, %k5
+; FASTISEL-NEXT:    kandd %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $17, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    movl $-32769, %edi ## imm = 0xFFFF7FFF
+; FASTISEL-NEXT:    kmovd %edi, %k3
+; FASTISEL-NEXT:    kandd %k3, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k7
+; FASTISEL-NEXT:    kshiftld $31, %k7, %k7
+; FASTISEL-NEXT:    kshiftrd $16, %k7, %k7
+; FASTISEL-NEXT:    kord %k7, %k0, %k7
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    movl $-65537, %edi ## imm = 0xFFFEFFFF
+; FASTISEL-NEXT:    kmovd %edi, %k2
+; FASTISEL-NEXT:    kandd %k2, %k7, %k7
+; FASTISEL-NEXT:    kshiftld $31, %k0, %k0
+; FASTISEL-NEXT:    kshiftrd $15, %k0, %k0
+; FASTISEL-NEXT:    kord %k0, %k7, %k0
+; FASTISEL-NEXT:    kmovd %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; FASTISEL-NEXT:    kmovd %esi, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd %edx, %k7
+; FASTISEL-NEXT:    kshiftld $31, %k7, %k7
+; FASTISEL-NEXT:    kshiftrd $30, %k7, %k7
+; FASTISEL-NEXT:    kord %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd %ecx, %k7
+; FASTISEL-NEXT:    kshiftld $31, %k7, %k7
+; FASTISEL-NEXT:    kshiftrd $29, %k7, %k7
+; FASTISEL-NEXT:    kord %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd %r8d, %k7
+; FASTISEL-NEXT:    kshiftld $31, %k7, %k7
+; FASTISEL-NEXT:    kshiftrd $28, %k7, %k7
+; FASTISEL-NEXT:    kord %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd %r9d, %k7
+; FASTISEL-NEXT:    kshiftld $31, %k7, %k7
+; FASTISEL-NEXT:    kshiftrd $27, %k7, %k7
+; FASTISEL-NEXT:    kord %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k7
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k1
+; FASTISEL-NEXT:    kshiftld $31, %k7, %k7
+; FASTISEL-NEXT:    kshiftrd $26, %k7, %k7
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kord %k7, %k1, %k1
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k7 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k7, %k1, %k1
+; FASTISEL-NEXT:    kshiftld $31, %k0, %k0
+; FASTISEL-NEXT:    kshiftrd $25, %k0, %k0
+; FASTISEL-NEXT:    kord %k0, %k1, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $24, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $23, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $22, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kandd %k6, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $21, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k6 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k6, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $20, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k6
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kshiftld $31, %k6, %k1
+; FASTISEL-NEXT:    kshiftrd $19, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kandd %k4, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $18, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kandd %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $17, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kandd %k3, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $16, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kandd %k2, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftld $31, %k1, %k1
+; FASTISEL-NEXT:    kshiftrd $15, %k1, %k1
+; FASTISEL-NEXT:    kord %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 4-byte Reload
+; FASTISEL-NEXT:    kandd %k1, %k0, %k0
+; FASTISEL-NEXT:    kshiftrd $16, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r8d
+; FASTISEL-NEXT:    kshiftrd $1, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r9d
+; FASTISEL-NEXT:    kshiftrd $2, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r10d
+; FASTISEL-NEXT:    kshiftrd $3, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r11d
+; FASTISEL-NEXT:    kshiftrd $4, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r12d
+; FASTISEL-NEXT:    kshiftrd $5, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r15d
+; FASTISEL-NEXT:    kshiftrd $6, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r14d
+; FASTISEL-NEXT:    kshiftrd $7, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r13d
+; FASTISEL-NEXT:    kshiftrd $8, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %ebx
+; FASTISEL-NEXT:    kshiftrd $9, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %esi
+; FASTISEL-NEXT:    kshiftrd $10, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %ebp
+; FASTISEL-NEXT:    kshiftrd $11, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %ecx
+; FASTISEL-NEXT:    kshiftrd $12, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %edx
+; FASTISEL-NEXT:    kshiftrd $13, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %edi
+; FASTISEL-NEXT:    kshiftrd $14, %k0, %k1
+; FASTISEL-NEXT:    andl $1, %r8d
+; FASTISEL-NEXT:    movb %r8b, 2(%rax)
+; FASTISEL-NEXT:    kmovd %k0, %r8d
+; FASTISEL-NEXT:    andl $1, %r8d
+; FASTISEL-NEXT:    andl $1, %r9d
+; FASTISEL-NEXT:    leal (%r8,%r9,2), %r8d
+; FASTISEL-NEXT:    kmovd %k1, %r9d
+; FASTISEL-NEXT:    kshiftrd $15, %k0, %k0
+; FASTISEL-NEXT:    andl $1, %r10d
+; FASTISEL-NEXT:    leal (%r8,%r10,4), %r8d
+; FASTISEL-NEXT:    kmovd %k0, %r10d
+; FASTISEL-NEXT:    andl $1, %r11d
+; FASTISEL-NEXT:    leal (%r8,%r11,8), %r8d
+; FASTISEL-NEXT:    andl $1, %r12d
+; FASTISEL-NEXT:    shll $4, %r12d
+; FASTISEL-NEXT:    orl %r8d, %r12d
+; FASTISEL-NEXT:    andl $1, %r15d
+; FASTISEL-NEXT:    shll $5, %r15d
+; FASTISEL-NEXT:    orl %r12d, %r15d
+; FASTISEL-NEXT:    andl $1, %r14d
+; FASTISEL-NEXT:    shll $6, %r14d
+; FASTISEL-NEXT:    andl $1, %r13d
+; FASTISEL-NEXT:    shll $7, %r13d
+; FASTISEL-NEXT:    orl %r14d, %r13d
+; FASTISEL-NEXT:    andl $1, %ebx
+; FASTISEL-NEXT:    shll $8, %ebx
+; FASTISEL-NEXT:    orl %r13d, %ebx
+; FASTISEL-NEXT:    andl $1, %esi
+; FASTISEL-NEXT:    shll $9, %esi
+; FASTISEL-NEXT:    orl %ebx, %esi
+; FASTISEL-NEXT:    andl $1, %ebp
+; FASTISEL-NEXT:    shll $10, %ebp
+; FASTISEL-NEXT:    orl %esi, %ebp
+; FASTISEL-NEXT:    orl %r15d, %ebp
+; FASTISEL-NEXT:    andl $1, %ecx
+; FASTISEL-NEXT:    shll $11, %ecx
+; FASTISEL-NEXT:    andl $1, %edx
+; FASTISEL-NEXT:    shll $12, %edx
+; FASTISEL-NEXT:    orl %ecx, %edx
+; FASTISEL-NEXT:    andl $1, %edi
+; FASTISEL-NEXT:    shll $13, %edi
+; FASTISEL-NEXT:    orl %edx, %edi
+; FASTISEL-NEXT:    andl $1, %r9d
+; FASTISEL-NEXT:    shll $14, %r9d
+; FASTISEL-NEXT:    orl %edi, %r9d
+; FASTISEL-NEXT:    andl $1, %r10d
+; FASTISEL-NEXT:    shll $15, %r10d
+; FASTISEL-NEXT:    orl %r9d, %r10d
+; FASTISEL-NEXT:    orl %ebp, %r10d
+; FASTISEL-NEXT:    movw %r10w, (%rax)
+; FASTISEL-NEXT:    popq %rbx
+; FASTISEL-NEXT:    popq %r12
+; FASTISEL-NEXT:    popq %r13
+; FASTISEL-NEXT:    popq %r14
+; FASTISEL-NEXT:    popq %r15
+; FASTISEL-NEXT:    popq %rbp
+; FASTISEL-NEXT:    retq
   %c = and <17 x i1> %a, %b
   ret <17 x i1> %c
 }
@@ -2700,6 +3193,383 @@ define <7 x i1> @test17(<7 x i1> %a, <7 x i1> %b, <7 x i1> %c, <7 x i1> %d, <7 x
 ; KNL_X32-NEXT:    addl $16, %esp
 ; KNL_X32-NEXT:    popl %ebx
 ; KNL_X32-NEXT:    retl $4
+;
+; FASTISEL-LABEL: test17:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    movq %rdi, %rax
+; FASTISEL-NEXT:    movb $-3, %dil
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $6, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    movb $-5, %dil
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $5, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k3
+; FASTISEL-NEXT:    movb $-9, %dil
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k3, %k3
+; FASTISEL-NEXT:    kshiftrb $4, %k3, %k3
+; FASTISEL-NEXT:    korb %k3, %k0, %k0
+; FASTISEL-NEXT:    movb $-17, %dil
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kmovw %k1, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k4
+; FASTISEL-NEXT:    kshiftlb $7, %k4, %k4
+; FASTISEL-NEXT:    kshiftrb $3, %k4, %k4
+; FASTISEL-NEXT:    korb %k4, %k0, %k0
+; FASTISEL-NEXT:    movb $-33, %dil
+; FASTISEL-NEXT:    kmovd %edi, %k1
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovq %k1, %k4
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k5
+; FASTISEL-NEXT:    kshiftlb $7, %k5, %k5
+; FASTISEL-NEXT:    kshiftrb $2, %k5, %k5
+; FASTISEL-NEXT:    korb %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k7
+; FASTISEL-NEXT:    movb $-65, %dil
+; FASTISEL-NEXT:    kmovd %edi, %k6
+; FASTISEL-NEXT:    kandb %k6, %k0, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k7, %k7
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kshiftrb $1, %k7, %k7
+; FASTISEL-NEXT:    korb %k7, %k1, %k7
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k3 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k3, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $6, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k2, %k0, %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $5, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    korb %k1, %k2, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k5 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k5, %k1, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k0, %k0
+; FASTISEL-NEXT:    kshiftrb $4, %k0, %k0
+; FASTISEL-NEXT:    korb %k0, %k1, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k2, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $3, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k4, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $2, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k6, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $1, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kandb %k3, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $6, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k7 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $5, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $4, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kmovq %k2, %k3
+; FASTISEL-NEXT:    kandb %k2, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $3, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k4, %k0, %k0
+; FASTISEL-NEXT:    kmovq %k4, %k5
+; FASTISEL-NEXT:    kmovw %k4, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k1
+; FASTISEL-NEXT:    kshiftrb $2, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovq %k6, %k4
+; FASTISEL-NEXT:    kandb %k6, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $1, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k6 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k6, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $6, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k7, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k1
+; FASTISEL-NEXT:    kshiftrb $5, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k7 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $4, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k3, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $3, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $2, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k4, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $1, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kandb %k6, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $6, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k5 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k5, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $5, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k7, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $4, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kandb %k3, %k1, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $3, %k2, %k2
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k2, %k1, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k0, %k0
+; FASTISEL-NEXT:    kshiftrb $2, %k0, %k0
+; FASTISEL-NEXT:    korb %k0, %k1, %k0
+; FASTISEL-NEXT:    kmovq %k4, %k3
+; FASTISEL-NEXT:    kmovw %k4, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kandb %k4, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $1, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kmovq %k6, %k4
+; FASTISEL-NEXT:    kandb %k6, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $6, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $5, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k7, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $4, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k6 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k6, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $3, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kandb %k2, %k0, %k0
+; FASTISEL-NEXT:    kmovq %k2, %k7
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $2, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k3, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftrb $1, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k4, %k2, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $6, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kandb %k5, %k1, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $5, %k2, %k2
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k3
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k4 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k4, %k1, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k3, %k2
+; FASTISEL-NEXT:    kshiftrb $4, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k6, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $3, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k7, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $2, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k3 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k3, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $1, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k0, %k1, %k0
+; FASTISEL-NEXT:    kmovw %k0, {{[-0-9]+}}(%r{{[sb]}}p) ## 2-byte Spill
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k5 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k5, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $6, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $5, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k4, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $4, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kandb %k6, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $3, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k7, %k0, %k0
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k1
+; FASTISEL-NEXT:    kshiftrb $2, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kandb %k3, %k0, %k0
+; FASTISEL-NEXT:    kmovq %k3, %k7
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k1, %k1
+; FASTISEL-NEXT:    kshiftrb $1, %k1, %k1
+; FASTISEL-NEXT:    korb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovd %esi, %k1
+; FASTISEL-NEXT:    kandb %k5, %k1, %k1
+; FASTISEL-NEXT:    kmovd %edx, %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $6, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovd %ecx, %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $5, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k4, %k1, %k1
+; FASTISEL-NEXT:    kmovd %r8d, %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $4, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k6, %k1, %k1
+; FASTISEL-NEXT:    kmovd %r9d, %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $3, %k2, %k2
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k3
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k2 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k2, %k1, %k1
+; FASTISEL-NEXT:    kshiftlb $7, %k3, %k2
+; FASTISEL-NEXT:    kshiftrb $2, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k7, %k1, %k1
+; FASTISEL-NEXT:    kmovb {{[0-9]+}}(%rsp), %k2
+; FASTISEL-NEXT:    kshiftlb $7, %k2, %k2
+; FASTISEL-NEXT:    kshiftrb $1, %k2, %k2
+; FASTISEL-NEXT:    korb %k2, %k1, %k1
+; FASTISEL-NEXT:    kandb %k0, %k1, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kmovw {{[-0-9]+}}(%r{{[sb]}}p), %k1 ## 2-byte Reload
+; FASTISEL-NEXT:    kandb %k1, %k0, %k0
+; FASTISEL-NEXT:    kshiftrb $6, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r8d
+; FASTISEL-NEXT:    kshiftrb $5, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r9d
+; FASTISEL-NEXT:    kshiftrb $4, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %r10d
+; FASTISEL-NEXT:    kshiftrb $3, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %edi
+; FASTISEL-NEXT:    kshiftrb $2, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %ecx
+; FASTISEL-NEXT:    kshiftrb $1, %k0, %k1
+; FASTISEL-NEXT:    kmovd %k1, %edx
+; FASTISEL-NEXT:    kmovd %k0, %esi
+; FASTISEL-NEXT:    andb $1, %sil
+; FASTISEL-NEXT:    andb $1, %dl
+; FASTISEL-NEXT:    addb %dl, %dl
+; FASTISEL-NEXT:    orb %sil, %dl
+; FASTISEL-NEXT:    andb $1, %cl
+; FASTISEL-NEXT:    shlb $2, %cl
+; FASTISEL-NEXT:    orb %dl, %cl
+; FASTISEL-NEXT:    andb $1, %dil
+; FASTISEL-NEXT:    shlb $3, %dil
+; FASTISEL-NEXT:    orb %cl, %dil
+; FASTISEL-NEXT:    andb $1, %r10b
+; FASTISEL-NEXT:    shlb $4, %r10b
+; FASTISEL-NEXT:    orb %dil, %r10b
+; FASTISEL-NEXT:    andb $1, %r9b
+; FASTISEL-NEXT:    shlb $5, %r9b
+; FASTISEL-NEXT:    orb %r10b, %r9b
+; FASTISEL-NEXT:    shlb $6, %r8b
+; FASTISEL-NEXT:    orb %r9b, %r8b
+; FASTISEL-NEXT:    andb $127, %r8b
+; FASTISEL-NEXT:    movb %r8b, (%rax)
+; FASTISEL-NEXT:    retq
   %j = and <7 x i1> %a, %b
   %k = and <7 x i1> %j, %c
   %l = and <7 x i1> %k, %d
@@ -2757,6 +3627,19 @@ define void @v2i1_mem(<128 x i32> %x, <2 x i1> %y) {
 ; KNL_X32-NEXT:    movl %ebp, %esp
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: v2i1_mem:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    subq $24, %rsp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 32
+; FASTISEL-NEXT:    vpsllq $63, {{[0-9]+}}(%rsp), %xmm8
+; FASTISEL-NEXT:    vpmovq2m %xmm8, %k0
+; FASTISEL-NEXT:    vpmovm2q %k0, %xmm8
+; FASTISEL-NEXT:    vmovdqa %xmm8, (%rsp)
+; FASTISEL-NEXT:    callq _v2i1_mem_callee
+; FASTISEL-NEXT:    addq $24, %rsp
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   call void @v2i1_mem_callee(<128 x i32> %x, <2 x i1> %y)
   ret void
 }
@@ -2807,6 +3690,19 @@ define void @v4i1_mem(<128 x i32> %x, <4 x i1> %y) {
 ; KNL_X32-NEXT:    movl %ebp, %esp
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: v4i1_mem:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    subq $24, %rsp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 32
+; FASTISEL-NEXT:    vpslld $31, {{[0-9]+}}(%rsp), %xmm8
+; FASTISEL-NEXT:    vpmovd2m %xmm8, %k0
+; FASTISEL-NEXT:    vpmovm2d %k0, %xmm8
+; FASTISEL-NEXT:    vmovdqa %xmm8, (%rsp)
+; FASTISEL-NEXT:    callq _v4i1_mem_callee
+; FASTISEL-NEXT:    addq $24, %rsp
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   call void @v4i1_mem_callee(<128 x i32> %x, <4 x i1> %y)
   ret void
 }
@@ -2857,6 +3753,19 @@ define void @v8i1_mem(<128 x i32> %x, <8 x i1> %y) {
 ; KNL_X32-NEXT:    movl %ebp, %esp
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: v8i1_mem:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    subq $24, %rsp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 32
+; FASTISEL-NEXT:    vpsllw $15, {{[0-9]+}}(%rsp), %xmm8
+; FASTISEL-NEXT:    vpmovw2m %xmm8, %k0
+; FASTISEL-NEXT:    vpmovm2w %k0, %xmm8
+; FASTISEL-NEXT:    vmovdqa %xmm8, (%rsp)
+; FASTISEL-NEXT:    callq _v8i1_mem_callee
+; FASTISEL-NEXT:    addq $24, %rsp
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   call void @v8i1_mem_callee(<128 x i32> %x, <8 x i1> %y)
   ret void
 }
@@ -2907,6 +3816,19 @@ define void @v16i1_mem(<128 x i32> %x, <16 x i1> %y) {
 ; KNL_X32-NEXT:    movl %ebp, %esp
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: v16i1_mem:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    subq $24, %rsp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 32
+; FASTISEL-NEXT:    vpsllw $7, {{[0-9]+}}(%rsp), %xmm8
+; FASTISEL-NEXT:    vpmovb2m %xmm8, %k0
+; FASTISEL-NEXT:    vpmovm2b %k0, %xmm8
+; FASTISEL-NEXT:    vmovdqa %xmm8, (%rsp)
+; FASTISEL-NEXT:    callq _v16i1_mem_callee
+; FASTISEL-NEXT:    addq $24, %rsp
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   call void @v16i1_mem_callee(<128 x i32> %x, <16 x i1> %y)
   ret void
 }
@@ -2969,6 +3891,25 @@ define void @v32i1_mem(<128 x i32> %x, <32 x i1> %y) {
 ; KNL_X32-NEXT:    movl %ebp, %esp
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: v32i1_mem:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rbp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    .cfi_offset %rbp, -16
+; FASTISEL-NEXT:    movq %rsp, %rbp
+; FASTISEL-NEXT:    .cfi_def_cfa_register %rbp
+; FASTISEL-NEXT:    andq $-32, %rsp
+; FASTISEL-NEXT:    subq $64, %rsp
+; FASTISEL-NEXT:    vpsllw $7, 16(%rbp), %ymm8
+; FASTISEL-NEXT:    vpmovb2m %ymm8, %k0
+; FASTISEL-NEXT:    vpmovm2b %k0, %ymm8
+; FASTISEL-NEXT:    vmovdqa %ymm8, (%rsp)
+; FASTISEL-NEXT:    callq _v32i1_mem_callee
+; FASTISEL-NEXT:    movq %rbp, %rsp
+; FASTISEL-NEXT:    popq %rbp
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   call void @v32i1_mem_callee(<128 x i32> %x, <32 x i1> %y)
   ret void
 }
@@ -3265,6 +4206,25 @@ define void @v64i1_mem(<128 x i32> %x, <64 x i1> %y) {
 ; KNL_X32-NEXT:    movl %ebp, %esp
 ; KNL_X32-NEXT:    popl %ebp
 ; KNL_X32-NEXT:    retl
+;
+; FASTISEL-LABEL: v64i1_mem:
+; FASTISEL:       ## %bb.0:
+; FASTISEL-NEXT:    pushq %rbp
+; FASTISEL-NEXT:    .cfi_def_cfa_offset 16
+; FASTISEL-NEXT:    .cfi_offset %rbp, -16
+; FASTISEL-NEXT:    movq %rsp, %rbp
+; FASTISEL-NEXT:    .cfi_def_cfa_register %rbp
+; FASTISEL-NEXT:    andq $-64, %rsp
+; FASTISEL-NEXT:    subq $128, %rsp
+; FASTISEL-NEXT:    vpsllw $7, 16(%rbp), %zmm8
+; FASTISEL-NEXT:    vpmovb2m %zmm8, %k0
+; FASTISEL-NEXT:    vpmovm2b %k0, %zmm8
+; FASTISEL-NEXT:    vmovdqa64 %zmm8, (%rsp)
+; FASTISEL-NEXT:    callq _v64i1_mem_callee
+; FASTISEL-NEXT:    movq %rbp, %rsp
+; FASTISEL-NEXT:    popq %rbp
+; FASTISEL-NEXT:    vzeroupper
+; FASTISEL-NEXT:    retq
   call void @v64i1_mem_callee(<128 x i32> %x, <64 x i1> %y)
   ret void
 }
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-cold.ll b/llvm/test/CodeGen/X86/basicblock-sections-cold.ll
new file mode 100644
index 0000000000000..5ddaf8f7cf7f3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-cold.ll
@@ -0,0 +1,41 @@
+; Check if basic blocks that don't get unique sections are placed in cold sections.
+; Basic block with id 1 and 2 must be in the cold section.
+; RUN: echo '!_Z3bazb' > %t
+; RUN: echo '!!0' >> %t
+; RUN: cat %t
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=%t -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+
+define void @_Z3bazb(i1 zeroext) {
+  %2 = alloca i8, align 1
+  %3 = zext i1 %0 to i8
+  store i8 %3, i8* %2, align 1
+  %4 = load i8, i8* %2, align 1
+  %5 = trunc i8 %4 to i1
+  br i1 %5, label %6, label %8
+
+6:                                                ; preds = %1
+  %7 = call i32 @_Z3barv()
+  br label %10
+
+8:                                                ; preds = %1
+  %9 = call i32 @_Z3foov()
+  br label %10
+
+10:                                               ; preds = %8, %6
+  ret void
+}
+
+declare i32 @_Z3barv() #1
+
+declare i32 @_Z3foov() #1
+
+; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
+; LINUX-SECTIONS: _Z3bazb:
+; Check that the basic block with id 1 doesn't get a section.
+; LINUX-SECTIONS-NOT: .section        .text._Z3bazb.r.BB._Z3bazb,"ax",@progbits,unique
+; Check that a single cold section is started here and id 1 and 2 blocks are placed here.
+; LINUX-SECTIONS: .section	.text._Z3bazb.unlikely,"ax",@progbits
+; LINUX-SECTIONS: r.BB._Z3bazb:
+; LINUX-SECTIONS-NOT: .section        .text._Z3bazb.rr.BB._Z3bazb,"ax",@progbits,unique
+; LINUX-SECTIONS: rr.BB._Z3bazb:
+; LINUX-SECTIONS: .size   _Z3bazb, .Lfunc_end{{[0-9]}}-_Z3bazb
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-directjumps.ll b/llvm/test/CodeGen/X86/basicblock-sections-directjumps.ll
new file mode 100644
index 0000000000000..7038b689ab506
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-directjumps.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=all -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu  -function-sections -basicblock-sections=all -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+
+define void @_Z3bazb(i1 zeroext) {
+  %2 = alloca i8, align 1
+  %3 = zext i1 %0 to i8
+  store i8 %3, i8* %2, align 1
+  %4 = load i8, i8* %2, align 1
+  %5 = trunc i8 %4 to i1
+  br i1 %5, label %6, label %9
+
+6:                                                ; preds = %1
+  %7 = call i32 @_Z3barv()
+  %8 = trunc i32 %7 to i1
+  br i1 %8, label %11, label %9
+
+9:                                                ; preds = %1
+  %10 = call i32 @_Z3foov()
+  br label %11
+
+11:                                               ; preds = %9, %6
+  ret void
+}
+
+declare i32 @_Z3barv() #1
+
+declare i32 @_Z3foov() #1
+
+
+; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
+; LINUX-SECTIONS: _Z3bazb:
+; LINUX-SECTIONS: jmp a.BB._Z3bazb
+; LINUX-SECTIONS: .section        .text._Z3bazb.a.BB._Z3bazb,"ax",@progbits,unique,1
+; LINUX-SECTIONS: a.BB._Z3bazb:
+; LINUX-SECTIONS: jmp aa.BB._Z3bazb
+; LINUX-SECTIONS: .section        .text._Z3bazb.aa.BB._Z3bazb,"ax",@progbits,unique,2
+; LINUX-SECTIONS: aa.BB._Z3bazb:
+; LINUX-SECTIONS: jmp raa.BB._Z3bazb
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-eh.ll b/llvm/test/CodeGen/X86/basicblock-sections-eh.ll
new file mode 100644
index 0000000000000..239ac4000fe6d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-eh.ll
@@ -0,0 +1,84 @@
+; Check if landing pads are kept in a separate eh section
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu  -function-sections -basicblock-sections=all -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+
+@_ZTIb = external constant i8*
+define i32 @_Z3foob(i1 zeroext %0) #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+  %2 = alloca i32, align 4
+  %3 = alloca i8, align 1
+  %4 = alloca i8*
+  %5 = alloca i32
+  %6 = alloca i8, align 1
+  %7 = zext i1 %0 to i8
+  store i8 %7, i8* %3, align 1
+  %8 = load i8, i8* %3, align 1
+  %9 = trunc i8 %8 to i1
+  br i1 %9, label %10, label %11
+
+10:                                               ; preds = %1
+  store i32 1, i32* %2, align 4
+  br label %31
+
+11:                                               ; preds = %1
+  %12 = call i8* @__cxa_allocate_exception(i64 1) #2
+  %13 = load i8, i8* %3, align 1
+  %14 = trunc i8 %13 to i1
+  %15 = zext i1 %14 to i8
+  store i8 %15, i8* %12, align 16
+  invoke void @__cxa_throw(i8* %12, i8* bitcast (i8** @_ZTIb to i8*), i8* null) #3
+          to label %38 unwind label %16
+
+16:                                               ; preds = %11
+  %17 = landingpad { i8*, i32 }
+          catch i8* bitcast (i8** @_ZTIb to i8*)
+  %18 = extractvalue { i8*, i32 } %17, 0
+  store i8* %18, i8** %4, align 8
+  %19 = extractvalue { i8*, i32 } %17, 1
+  store i32 %19, i32* %5, align 4
+  br label %20
+
+20:                                               ; preds = %16
+  %21 = load i32, i32* %5, align 4
+  %22 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIb to i8*)) #2
+  %23 = icmp eq i32 %21, %22
+  br i1 %23, label %24, label %33
+
+24:                                               ; preds = %20
+  %25 = load i8*, i8** %4, align 8
+  %26 = call i8* @__cxa_begin_catch(i8* %25) #2
+  %27 = load i8, i8* %26, align 1
+  %28 = trunc i8 %27 to i1
+  %29 = zext i1 %28 to i8
+  store i8 %29, i8* %6, align 1
+  call void @__cxa_end_catch() #2
+  br label %30
+
+30:                                               ; preds = %24
+  store i32 0, i32* %2, align 4
+  br label %31
+
+31:                                               ; preds = %30, %10
+  %32 = load i32, i32* %2, align 4
+  ret i32 %32
+
+33:                                               ; preds = %20
+  %34 = load i8*, i8** %4, align 8
+  %35 = load i32, i32* %5, align 4
+  %36 = insertvalue { i8*, i32 } undef, i8* %34, 0
+  %37 = insertvalue { i8*, i32 } %36, i32 %35, 1
+  resume { i8*, i32 } %37
+
+38:                                               ; preds = %11
+  unreachable
+}
+declare i8* @__cxa_allocate_exception(i64)
+declare void @__cxa_throw(i8*, i8*, i8*)
+declare i32 @__gxx_personality_v0(...)
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #1
+declare i8* @__cxa_begin_catch(i8*)
+declare void @__cxa_end_catch()
+
+;LINUX-SECTIONS: .section	.text._Z3foob,"ax",@progbits
+;LINUX-SECTIONS: _Z3foob:
+;LINUX-SECTIONS: .section	.text._Z3foob.eh,"ax",@progbits
+;LINUX-SECTIONS: l{{[a|r]*}}.BB._Z3foob:
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-labels.ll b/llvm/test/CodeGen/X86/basicblock-sections-labels.ll
new file mode 100644
index 0000000000000..2f077e6866924
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-labels.ll
@@ -0,0 +1,33 @@
+; Check the basic block sections labels option
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=labels | FileCheck %s -check-prefix=LINUX-LABELS
+
+define void @_Z3bazb(i1 zeroext) {
+  %2 = alloca i8, align 1
+  %3 = zext i1 %0 to i8
+  store i8 %3, i8* %2, align 1
+  %4 = load i8, i8* %2, align 1
+  %5 = trunc i8 %4 to i1
+  br i1 %5, label %6, label %8
+
+6:                                                ; preds = %1
+  %7 = call i32 @_Z3barv()
+  br label %10
+
+8:                                                ; preds = %1
+  %9 = call i32 @_Z3foov()
+  br label %10
+
+10:                                               ; preds = %8, %6
+  ret void
+}
+
+declare i32 @_Z3barv() #1
+
+declare i32 @_Z3foov() #1
+
+; LINUX-LABELS: .section
+; LINUX-LABELS: _Z3bazb:
+; LINUX-LABELS-NOT: .section
+; LINUX-LABELS: r.BB._Z3bazb:
+; LINUX-LABELS-NOT: .section
+; LINUX-LABELS: rr.BB._Z3bazb:
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-list.ll b/llvm/test/CodeGen/X86/basicblock-sections-list.ll
new file mode 100644
index 0000000000000..93db874165cf3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-list.ll
@@ -0,0 +1,76 @@
+; Check the basic block sections list option.
+; RUN: echo '!_Z3foob' > %t
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=%t -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+
+define i32 @_Z3foob(i1 zeroext %0) #0 {
+  %2 = alloca i32, align 4
+  %3 = alloca i8, align 1
+  %4 = zext i1 %0 to i8
+  store i8 %4, i8* %3, align 1
+  %5 = load i8, i8* %3, align 1
+  %6 = trunc i8 %5 to i1
+  %7 = zext i1 %6 to i32
+  %8 = icmp sgt i32 %7, 0
+  br i1 %8, label %9, label %11
+
+9:                                                ; preds = %1
+  %10 = call i32 @_Z3barv()
+  store i32 %10, i32* %2, align 4
+  br label %13
+
+11:                                               ; preds = %1
+  %12 = call i32 @_Z3bazv()
+  store i32 %12, i32* %2, align 4
+  br label %13
+
+13:                                               ; preds = %11, %9
+  %14 = load i32, i32* %2, align 4
+  ret i32 %14
+}
+
+declare i32 @_Z3barv() #1
+declare i32 @_Z3bazv() #1
+
+define i32 @_Z3zipb(i1 zeroext %0) #0 {
+  %2 = alloca i32, align 4
+  %3 = alloca i8, align 1
+  %4 = zext i1 %0 to i8
+  store i8 %4, i8* %3, align 1
+  %5 = load i8, i8* %3, align 1
+  %6 = trunc i8 %5 to i1
+  %7 = zext i1 %6 to i32
+  %8 = icmp sgt i32 %7, 0
+  br i1 %8, label %9, label %11
+
+9:                                                ; preds = %1
+  %10 = call i32 @_Z3barv()
+  store i32 %10, i32* %2, align 4
+  br label %13
+
+11:                                               ; preds = %1
+  %12 = call i32 @_Z3bazv()
+  store i32 %12, i32* %2, align 4
+  br label %13
+
+13:                                               ; preds = %11, %9
+  %14 = load i32, i32* %2, align 4
+  ret i32 %14
+}
+
+; LINUX-SECTIONS: .section        .text._Z3foob,"ax",@progbits
+; LINUX-SECTIONS: _Z3foob:
+; LINUX-SECTIONS: .section        .text._Z3foob.a.BB._Z3foob,"ax",@progbits,unique,1
+; LINUX-SECTIONS: a.BB._Z3foob:
+; LINUX-SECTIONS: .section        .text._Z3foob.aa.BB._Z3foob,"ax",@progbits,unique,2
+; LINUX-SECTIONS: aa.BB._Z3foob:
+; LINUX-SECTIONS: .section        .text._Z3foob.raa.BB._Z3foob,"ax",@progbits,unique,3
+; LINUX-SECTIONS: raa.BB._Z3foob:
+
+; LINUX-SECTIONS: .section        .text._Z3zipb,"ax",@progbits
+; LINUX-SECTIONS: _Z3zipb:
+; LINUX-SECTIONS-NOT: .section        .text._Z3zipb.a.BB._Z3zipb,"ax",@progbits,unique,1
+; LINUX-SECTIONS-NOT: a.BB._Z3zipb:
+; LINUX-SECTIONS-NOT: .section        .text._Z3zipb.aa.BB._Z3zipb,"ax",@progbits,unique,2
+; LINUX-SECTIONS-NOT: aa.BB._Z3zipb:
+; LINUX-SECTIONS-NOT: .section        .text._Z3zipb.raa.BB._Z3zipb,"ax",@progbits,unique,3
+; LINUX-SECTIONS-NOT: raa.BB._Z3zipb:
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-listbb.ll b/llvm/test/CodeGen/X86/basicblock-sections-listbb.ll
new file mode 100644
index 0000000000000..9bc8cacb4aa92
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-listbb.ll
@@ -0,0 +1,38 @@
+; Fine-grained basic block sections, subset of basic blocks in a function.
+; Only basic block with id 2 must get a section.
+; RUN: echo '!_Z3bazb' > %t
+; RUN: echo '!!2' >> %t
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=%t -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+
+define void @_Z3bazb(i1 zeroext) {
+  %2 = alloca i8, align 1
+  %3 = zext i1 %0 to i8
+  store i8 %3, i8* %2, align 1
+  %4 = load i8, i8* %2, align 1
+  %5 = trunc i8 %4 to i1
+  br i1 %5, label %6, label %8
+
+6:                                                ; preds = %1
+  %7 = call i32 @_Z3barv()
+  br label %10
+
+8:                                                ; preds = %1
+  %9 = call i32 @_Z3foov()
+  br label %10
+
+10:                                               ; preds = %8, %6
+  ret void
+}
+
+declare i32 @_Z3barv() #1
+
+declare i32 @_Z3foov() #1
+
+; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
+; LINUX-SECTIONS: _Z3bazb:
+; Check that the basic block with id 1 doesn't get a section.
+; LINUX-SECTIONS-NOT: .section        .text._Z3bazb.r.BB._Z3bazb,"ax",@progbits,unique
+; LINUX-SECTIONS: r.BB._Z3bazb:
+; LINUX-SECTIONS: .section        .text._Z3bazb.rr.BB._Z3bazb,"ax",@progbits,unique
+; LINUX-SECTIONS: rr.BB._Z3bazb:
+; LINUX-SECTIONS: .size   rr.BB._Z3bazb, .Ltmp1-rr.BB._Z3bazb
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-mir-parse.mir b/llvm/test/CodeGen/X86/basicblock-sections-mir-parse.mir
new file mode 100644
index 0000000000000..81db8b0327288
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-mir-parse.mir
@@ -0,0 +1,131 @@
+# Start after bbsections0-prepare and check if the right code is generated.
+# RUN: llc -mtriple x86_64-unknown-linux-gnu -start-after=bbsections-prepare  %s -o - | FileCheck %s -check-prefix=CHECK
+
+
+# How to generate the input:
+# foo.cc
+# int foo(bool k) {
+#  if (k) return 1;
+#  return 0;
+# }
+#
+# clang -O0 -S -emit-llvm foo.cc
+# llc < foo.ll -stop-after=bbsections-prepare -basicblock-sections=all
+
+--- |
+  ; Function Attrs: noinline nounwind optnone uwtable
+  define dso_local i32 @_Z3foob(i1 zeroext %0) #0 {
+    %2 = alloca i32, align 4
+    %3 = alloca i8, align 1
+    %4 = zext i1 %0 to i8
+    store i8 %4, i8* %3, align 1
+    %5 = load i8, i8* %3, align 1
+    %6 = trunc i8 %5 to i1
+    br i1 %6, label %7, label %8
+  
+  7:                                                ; preds = %1
+    store i32 1, i32* %2, align 4
+    br label %9
+  
+  8:                                                ; preds = %1
+    store i32 0, i32* %2, align 4
+    br label %9
+  
+  9:                                                ; preds = %8, %7
+    %10 = load i32, i32* %2, align 4
+    ret i32 %10
+  }
+  
+  attributes #0 = { "frame-pointer"="all"  "target-cpu"="x86-64" }
+  
+
+...
+---
+name:            _Z3foob
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$edi', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: -8
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default, 
+      callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', 
+      debug-info-expression: '', debug-info-location: '' }
+stack:
+  - { id: 0, type: default, offset: -24, size: 4, 
+      alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, type: default, offset: -17, size: 1, 
+      alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.1, bbsections Entry):
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $edi
+  
+    frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset $rbp, -16
+    $rbp = frame-setup MOV64rr $rsp
+    CFI_INSTRUCTION def_cfa_register $rbp
+    renamable $dil = AND8ri renamable $dil, 1, implicit-def dead $eflags, implicit killed $edi, implicit-def $edi
+    MOV8mr $rbp, 1, $noreg, -1, $noreg, renamable $dil, implicit killed $edi :: (store 1 into %ir.3)
+    TEST8mi $rbp, 1, $noreg, -1, $noreg, 1, implicit-def $eflags :: (load 1 from %ir.3)
+    JCC_1 %bb.2, 4, implicit killed $eflags
+    JMP_1 %bb.1
+  
+  bb.1 (%ir-block.7, bbsections Unique):
+    successors: %bb.3(0x80000000)
+  
+    MOV32mi $rbp, 1, $noreg, -8, $noreg, 1 :: (store 4 into %ir.2)
+    JMP_1 %bb.3
+  
+  bb.2 (%ir-block.8, bbsections Unique):
+    successors: %bb.3(0x80000000)
+  
+    MOV32mi $rbp, 1, $noreg, -8, $noreg, 0 :: (store 4 into %ir.2)
+    JMP_1 %bb.3
+  
+  bb.3 (%ir-block.9, bbsections Unique):
+    renamable $eax = MOV32rm $rbp, 1, $noreg, -8, $noreg :: (load 4 from %ir.2)
+    $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
+    CFI_INSTRUCTION def_cfa $rsp, 8
+    RETQ implicit $eax
+
+...
+
+# CHECK: _Z3foob:
+# CHECK: .section	.text,"ax",@progbits,unique
+# CHECK: a.BB._Z3foob:
+# CHECK: .section	.text,"ax",@progbits,unique
+# CHECK: aa.BB._Z3foob:
+# CHECK: .section	.text,"ax",@progbits,unique
+# CHECK: aaa.BB._Z3foob:
diff --git a/llvm/test/CodeGen/X86/basicblock-sections-mir-print.ll b/llvm/test/CodeGen/X86/basicblock-sections-mir-print.ll
new file mode 100644
index 0000000000000..93ac4d1af942e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections-mir-print.ll
@@ -0,0 +1,32 @@
+; Stop after bbsections-prepare and check MIR output for section type.
+; RUN: echo '!_Z3foob' > %t
+; RUN: echo '!!1' >> %t
+; RUN: llc < %s -O0 -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=%t -stop-after=bbsections-prepare | FileCheck %s -check-prefix=CHECK
+
+@_ZTIb = external constant i8*
+define dso_local i32 @_Z3foob(i1 zeroext %0) {
+  %2 = alloca i32, align 4
+  %3 = alloca i8, align 1
+  %4 = zext i1 %0 to i8
+  store i8 %4, i8* %3, align 1
+  %5 = load i8, i8* %3, align 1
+  %6 = trunc i8 %5 to i1
+  br i1 %6, label %7, label %8
+
+7:                                                ; preds = %1
+  store i32 1, i32* %2, align 4
+  br label %9
+
+8:                                                ; preds = %1
+  store i32 0, i32* %2, align 4
+  br label %9
+
+9:                                                ; preds = %8, %7
+  %10 = load i32, i32* %2, align 4
+  ret i32 %10
+}
+
+; CHECK: bbsections Entry
+; CHECK: bbsections Cold
+; CHECK: bbsections Cold
+; CHECK: bbsections Unique
diff --git a/llvm/test/CodeGen/X86/basicblock-sections.ll b/llvm/test/CodeGen/X86/basicblock-sections.ll
new file mode 100644
index 0000000000000..3ba4d4ac92826
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basicblock-sections.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basicblock-sections=all -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu  -function-sections -basicblock-sections=all -unique-bb-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS
+
+define void @_Z3bazb(i1 zeroext) {
+  %2 = alloca i8, align 1
+  %3 = zext i1 %0 to i8
+  store i8 %3, i8* %2, align 1
+  %4 = load i8, i8* %2, align 1
+  %5 = trunc i8 %4 to i1
+  br i1 %5, label %6, label %8
+
+6:                                                ; preds = %1
+  %7 = call i32 @_Z3barv()
+  br label %10
+
+8:                                                ; preds = %1
+  %9 = call i32 @_Z3foov()
+  br label %10
+
+10:                                               ; preds = %8, %6
+  ret void
+}
+
+declare i32 @_Z3barv() #1
+
+declare i32 @_Z3foov() #1
+
+
+; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
+; LINUX-SECTIONS: _Z3bazb:
+; LINUX-SECTIONS: .section        .text._Z3bazb.r.BB._Z3bazb,"ax",@progbits,unique,1
+; LINUX-SECTIONS: r.BB._Z3bazb:
+; LINUX-SECTIONS: .size   r.BB._Z3bazb, .Ltmp0-r.BB._Z3bazb
+; LINUX-SECTIONS: .section        .text._Z3bazb.rr.BB._Z3bazb,"ax",@progbits,unique,2
+; LINUX-SECTIONS: rr.BB._Z3bazb:
+; LINUX-SECTIONS: .size   rr.BB._Z3bazb, .Ltmp1-rr.BB._Z3bazb
diff --git a/llvm/test/CodeGen/X86/callbr-asm-obj-file.ll b/llvm/test/CodeGen/X86/callbr-asm-obj-file.ll
index 6e6cafa2e1efc..a8a392541b496 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-obj-file.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-obj-file.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-linux-gnu -filetype=obj -o - \
-; RUN:  | llvm-objdump -triple x86_64-linux-gnu -d - \
+; RUN:  | llvm-objdump --triple=x86_64-linux-gnu -d - \
 ; RUN:  | FileCheck %s
 
 ; CHECK: 0000000000000000 <test1>:
diff --git a/llvm/test/CodeGen/X86/combine-rotates.ll b/llvm/test/CodeGen/X86/combine-rotates.ll
index 15aec1aead30b..d1fcd2fb0259a 100644
--- a/llvm/test/CodeGen/X86/combine-rotates.ll
+++ b/llvm/test/CodeGen/X86/combine-rotates.ll
@@ -118,57 +118,55 @@ define i32 @combine_rot_select_zero(i32, i32) {
 define <4 x i32> @combine_vec_rot_select_zero(<4 x i32>, <4 x i32>) {
 ; SSE2-LABEL: combine_vec_rot_select_zero:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [31,31,31,31]
-; SSE2-NEXT:    pand %xmm1, %xmm2
-; SSE2-NEXT:    pxor %xmm3, %xmm3
-; SSE2-NEXT:    pslld $23, %xmm2
-; SSE2-NEXT:    paddd {{.*}}(%rip), %xmm2
-; SSE2-NEXT:    cvttps2dq %xmm2, %xmm2
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [31,31,31,31]
+; SSE2-NEXT:    pand %xmm1, %xmm3
+; SSE2-NEXT:    pslld $23, %xmm3
+; SSE2-NEXT:    paddd {{.*}}(%rip), %xmm3
+; SSE2-NEXT:    cvttps2dq %xmm3, %xmm3
 ; SSE2-NEXT:    movdqa %xmm0, %xmm4
-; SSE2-NEXT:    pmuludq %xmm2, %xmm4
+; SSE2-NEXT:    pmuludq %xmm3, %xmm4
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[1,3,2,3]
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE2-NEXT:    pmuludq %xmm6, %xmm2
-; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm2[1,3,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm6, %xmm3
+; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm3[1,3,2,3]
 ; SSE2-NEXT:    punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
 ; SSE2-NEXT:    por %xmm5, %xmm4
-; SSE2-NEXT:    pcmpeqd %xmm1, %xmm3
-; SSE2-NEXT:    pand %xmm3, %xmm0
-; SSE2-NEXT:    pandn %xmm4, %xmm3
-; SSE2-NEXT:    por %xmm3, %xmm0
+; SSE2-NEXT:    pcmpeqd %xmm1, %xmm2
+; SSE2-NEXT:    pand %xmm2, %xmm0
+; SSE2-NEXT:    pandn %xmm4, %xmm2
+; SSE2-NEXT:    por %xmm2, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; XOP-LABEL: combine_vec_rot_select_zero:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vpand {{.*}}(%rip), %xmm1, %xmm2
-; XOP-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; XOP-NEXT:    vprotd %xmm2, %xmm0, %xmm2
-; XOP-NEXT:    vpcomeqd %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vblendvps %xmm1, %xmm0, %xmm2, %xmm0
+; XOP-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; XOP-NEXT:    vprotd %xmm1, %xmm0, %xmm3
+; XOP-NEXT:    vpcomeqd %xmm2, %xmm1, %xmm1
+; XOP-NEXT:    vblendvps %xmm1, %xmm0, %xmm3, %xmm0
 ; XOP-NEXT:    retq
 ;
 ; AVX2-LABEL: combine_vec_rot_select_zero:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
-; AVX2-NEXT:    vpand %xmm2, %xmm1, %xmm2
-; AVX2-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX2-NEXT:    vpsllvd %xmm2, %xmm0, %xmm4
+; AVX2-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm3 = [31,31,31,31]
+; AVX2-NEXT:    vpand %xmm3, %xmm1, %xmm3
+; AVX2-NEXT:    vpsllvd %xmm3, %xmm0, %xmm4
 ; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm5 = [32,32,32,32]
-; AVX2-NEXT:    vpsubd %xmm2, %xmm5, %xmm2
-; AVX2-NEXT:    vpsrlvd %xmm2, %xmm0, %xmm2
-; AVX2-NEXT:    vpor %xmm2, %xmm4, %xmm2
-; AVX2-NEXT:    vpcmpeqd %xmm3, %xmm1, %xmm1
-; AVX2-NEXT:    vblendvps %xmm1, %xmm0, %xmm2, %xmm0
+; AVX2-NEXT:    vpsubd %xmm3, %xmm5, %xmm3
+; AVX2-NEXT:    vpsrlvd %xmm3, %xmm0, %xmm3
+; AVX2-NEXT:    vpor %xmm3, %xmm4, %xmm3
+; AVX2-NEXT:    vpcmpeqd %xmm2, %xmm1, %xmm1
+; AVX2-NEXT:    vblendvps %xmm1, %xmm0, %xmm3, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: combine_vec_rot_select_zero:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm2
-; AVX512-NEXT:    vprolvd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT:    vprolvd %xmm1, %xmm0, %xmm2
 ; AVX512-NEXT:    vptestnmd %xmm1, %xmm1, %k1
 ; AVX512-NEXT:    vmovdqa32 %xmm0, %xmm2 {%k1}
 ; AVX512-NEXT:    vmovdqa %xmm2, %xmm0
@@ -310,14 +308,13 @@ define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
 ; XOP-LABEL: rotate_demanded_bits_3:
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vpaddd %xmm1, %xmm1, %xmm1
-; XOP-NEXT:    vpand {{.*}}(%rip), %xmm1, %xmm1
 ; XOP-NEXT:    vprotd %xmm1, %xmm0, %xmm0
 ; XOP-NEXT:    retq
 ;
 ; AVX2-LABEL: rotate_demanded_bits_3:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm1, %xmm1
-; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm2 = [30,30,30,30]
+; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
 ; AVX2-NEXT:    vpand %xmm2, %xmm1, %xmm1
 ; AVX2-NEXT:    vpsllvd %xmm1, %xmm0, %xmm2
 ; AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
@@ -329,7 +326,6 @@ define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
 ; AVX512-LABEL: rotate_demanded_bits_3:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm1, %xmm1
-; AVX512-NEXT:    vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
 ; AVX512-NEXT:    vprolvd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %3 = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/CodeGen/X86/compact-unwind.ll b/llvm/test/CodeGen/X86/compact-unwind.ll
index ab85f599b3ae5..75af4339af385 100644
--- a/llvm/test/CodeGen/X86/compact-unwind.ll
+++ b/llvm/test/CodeGen/X86/compact-unwind.ll
@@ -1,18 +1,18 @@
 ; RUN: llc < %s -frame-pointer=all -mtriple x86_64-apple-darwin11 -mcpu corei7 | FileCheck -check-prefix=ASM %s
 ; RUN: llc < %s -frame-pointer=all -mtriple x86_64-apple-darwin11 -mcpu corei7 -filetype=obj -o - \
-; RUN:  | llvm-objdump -triple x86_64-apple-darwin11 -unwind-info - \
+; RUN:  | llvm-objdump --triple=x86_64-apple-darwin11 --unwind-info - \
 ; RUN:  | FileCheck -check-prefix=CU %s
 ; RUN: llc < %s -frame-pointer=all -mtriple x86_64-apple-darwin11 -mcpu corei7 \
 ; RUN:  | llvm-mc -triple x86_64-apple-darwin11 -filetype=obj -o - \
-; RUN:  | llvm-objdump -triple x86_64-apple-darwin11 -unwind-info - \
+; RUN:  | llvm-objdump --triple=x86_64-apple-darwin11 --unwind-info - \
 ; RUN:  | FileCheck -check-prefix=FROM-ASM %s
 
 ; RUN: llc < %s -mtriple x86_64-apple-macosx10.8.0 -mcpu corei7 -filetype=obj -o - \
-; RUN:  | llvm-objdump -triple x86_64-apple-macosx10.8.0 -unwind-info - \
+; RUN:  | llvm-objdump --triple=x86_64-apple-macosx10.8.0 --unwind-info - \
 ; RUN:  | FileCheck -check-prefix=NOFP-CU %s
 ; RUN: llc < %s -mtriple x86_64-apple-darwin11 -mcpu corei7 \
 ; RUN:  | llvm-mc -triple x86_64-apple-darwin11 -filetype=obj -o - \
-; RUN:  | llvm-objdump -triple x86_64-apple-darwin11 -unwind-info - \
+; RUN:  | llvm-objdump --triple=x86_64-apple-darwin11 --unwind-info - \
 ; RUN:  | FileCheck -check-prefix=NOFP-FROM-ASM %s
 
 %ty = type { i8* }
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
index ff483ab176015..4f2859d4bffab 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
@@ -108,7 +108,7 @@ entry:
 ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0)
 ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.1, align 16)
 ; CHECK: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt %fixed-stack.3, 1, $noreg, 0, $noreg :: (load 8 from %fixed-stack.3, align 16)
-; CHECK: %3:fr64 = nofpexcept DIVSDrm [[MOVSDrm_alt]], %fixed-stack.2, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.2)
+; CHECK: %3:fr64 = DIVSDrm [[MOVSDrm_alt]], %fixed-stack.2, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %fixed-stack.2)
 ; CHECK: MOVSDmr killed [[MOV32rm1]], 1, $noreg, 0, $noreg, %3 :: (store 8 into %ir.x, align 4)
 ; CHECK: MOVSDmr killed [[MOV32rm]], 1, $noreg, 0, $noreg, %3 :: (store 8 into %ir.y, align 4)
 ; CHECK: RET 0
@@ -126,7 +126,7 @@ entry:
 ; CHECK-LABEL: name: sitofp_cse
 ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0, align 8)
 ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.1)
-; CHECK: %2:fr64 = nofpexcept CVTSI2SDrm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.2, align 16)
+; CHECK: %2:fr64 = CVTSI2SDrm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.2, align 16)
 ; CHECK: MOVSDmr killed [[MOV32rm1]], 1, $noreg, 0, $noreg, %2 :: (store 8 into %ir.x, align 4)
 ; CHECK: MOVSDmr killed [[MOV32rm]], 1, $noreg, 0, $noreg, %2 :: (store 8 into %ir.y, align 4)
 ; CHECK: RET 0
diff --git a/llvm/test/CodeGen/X86/implicit-faultmap.ll b/llvm/test/CodeGen/X86/implicit-faultmap.ll
index 1701b0fc5fd33..261c0bf60b461 100644
--- a/llvm/test/CodeGen/X86/implicit-faultmap.ll
+++ b/llvm/test/CodeGen/X86/implicit-faultmap.ll
@@ -2,12 +2,12 @@
 
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx -enable-implicit-null-checks \
 ; RUN:    | llvm-mc -triple x86_64-apple-macosx -filetype=obj -o - \
-; RUN:    | llvm-objdump -triple x86_64-apple-macosx -fault-map-section - \
+; RUN:    | llvm-objdump --triple=x86_64-apple-macosx --fault-map-section - \
 ; RUN:    | FileCheck %s -check-prefix OBJDUMP
 
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -enable-implicit-null-checks \
 ; RUN:    | llvm-mc -triple x86_64-unknown-linux-gnu -filetype=obj -o - \
-; RUN:    | llvm-objdump -triple x86_64-unknown-linux-gnu -fault-map-section - \
+; RUN:    | llvm-objdump --triple=x86_64-unknown-linux-gnu --fault-map-section - \
 ; RUN:    | FileCheck %s -check-prefix OBJDUMP
 
 ;; The tests in this file exist just to check basic validity of the FaultMap
diff --git a/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll b/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll
new file mode 100644
index 0000000000000..c14e82dc8f3d6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mtriple=i386-unknown-unknown < %s | FileCheck %s
+
+;There should be 2 endbr* instruction at entry and catch pad.
+;CHECK-COUNT-2: endbr
+
+declare void @_Z20function_that_throwsv()
+declare i32 @__gxx_personality_sj0(...)
+declare i8* @__cxa_begin_catch(i8*)
+declare void @__cxa_end_catch()
+
+define void @test8() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+entry:
+  invoke void @_Z20function_that_throwsv()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %0 = landingpad { i8*, i32 }
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  %2 = tail call i8* @__cxa_begin_catch(i8* %1)
+  tail call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"cf-protection-branch", i32 1}
diff --git a/llvm/test/CodeGen/X86/mingw-comdats-xdata.ll b/llvm/test/CodeGen/X86/mingw-comdats-xdata.ll
index b8a2167a87853..04effedfaf7b1 100644
--- a/llvm/test/CodeGen/X86/mingw-comdats-xdata.ll
+++ b/llvm/test/CodeGen/X86/mingw-comdats-xdata.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=x86_64-w64-windows-gnu < %s | FileCheck %s --check-prefix=GNU
-; RUN: llc -mtriple=x86_64-w64-windows-gnu < %s -filetype=obj | llvm-objdump - -headers | FileCheck %s --check-prefix=GNUOBJ
+; RUN: llc -mtriple=x86_64-w64-windows-gnu < %s -filetype=obj | llvm-objdump - --headers | FileCheck %s --check-prefix=GNUOBJ
 
 ; When doing GCC style comdats for MinGW, the .xdata sections don't have a normal comdat
 ; symbol attached, which requires a bit of adjustments for the assembler output.
diff --git a/llvm/test/CodeGen/X86/mingw-comdats.ll b/llvm/test/CodeGen/X86/mingw-comdats.ll
index 35f4fd12670c2..c7caf925250ba 100644
--- a/llvm/test/CodeGen/X86/mingw-comdats.ll
+++ b/llvm/test/CodeGen/X86/mingw-comdats.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -function-sections -mtriple=x86_64-windows-msvc < %s | FileCheck %s
 ; RUN: llc -function-sections -mtriple=x86_64-w64-windows-gnu < %s | FileCheck %s --check-prefix=GNU
 ; RUN: llc -function-sections -mtriple=i686-w64-windows-gnu < %s | FileCheck %s --check-prefix=GNU32
-; RUN: llc -function-sections -mtriple=x86_64-w64-windows-gnu < %s -filetype=obj | llvm-objdump - -headers | FileCheck %s --check-prefix=GNUOBJ
+; RUN: llc -function-sections -mtriple=x86_64-w64-windows-gnu < %s -filetype=obj | llvm-objdump - --headers | FileCheck %s --check-prefix=GNUOBJ
 
 ; GCC and MSVC handle comdats completely differently. Make sure we do the right
 ; thing for each.
diff --git a/llvm/test/CodeGen/X86/movmsk-cmp.ll b/llvm/test/CodeGen/X86/movmsk-cmp.ll
index 7f0a1418a7192..4fdde8c06641b 100644
--- a/llvm/test/CodeGen/X86/movmsk-cmp.ll
+++ b/llvm/test/CodeGen/X86/movmsk-cmp.ll
@@ -4225,40 +4225,25 @@ define i1 @movmsk_v16i8(<16 x i8> %x, <16 x i8> %y) {
   ret i1 %u2
 }
 
-; TODO: Replace shift+mask chain with NOT+TEST+SETE
 define i1 @movmsk_v8i16(<8 x i16> %x, <8 x i16> %y) {
 ; SSE2-LABEL: movmsk_v8i16:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    pcmpgtw %xmm1, %xmm0
 ; SSE2-NEXT:    packsswb %xmm0, %xmm0
-; SSE2-NEXT:    pmovmskb %xmm0, %ecx
-; SSE2-NEXT:    movl %ecx, %eax
-; SSE2-NEXT:    shrb $7, %al
-; SSE2-NEXT:    movl %ecx, %edx
-; SSE2-NEXT:    andb $16, %dl
-; SSE2-NEXT:    shrb $4, %dl
-; SSE2-NEXT:    andb %al, %dl
-; SSE2-NEXT:    movl %ecx, %eax
-; SSE2-NEXT:    shrb %al
-; SSE2-NEXT:    andb %dl, %al
-; SSE2-NEXT:    andb %cl, %al
+; SSE2-NEXT:    pmovmskb %xmm0, %eax
+; SSE2-NEXT:    andb $-109, %al
+; SSE2-NEXT:    cmpb $-109, %al
+; SSE2-NEXT:    sete %al
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: movmsk_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
-; AVX-NEXT:    vpmovmskb %xmm0, %ecx
-; AVX-NEXT:    movl %ecx, %eax
-; AVX-NEXT:    shrb $7, %al
-; AVX-NEXT:    movl %ecx, %edx
-; AVX-NEXT:    andb $16, %dl
-; AVX-NEXT:    shrb $4, %dl
-; AVX-NEXT:    andb %al, %dl
-; AVX-NEXT:    movl %ecx, %eax
-; AVX-NEXT:    shrb %al
-; AVX-NEXT:    andb %dl, %al
-; AVX-NEXT:    andb %cl, %al
+; AVX-NEXT:    vpmovmskb %xmm0, %eax
+; AVX-NEXT:    andb $-109, %al
+; AVX-NEXT:    cmpb $-109, %al
+; AVX-NEXT:    sete %al
 ; AVX-NEXT:    retq
 ;
 ; KNL-LABEL: movmsk_v8i16:
@@ -4266,34 +4251,20 @@ define i1 @movmsk_v8i16(<8 x i16> %x, <8 x i16> %y) {
 ; KNL-NEXT:    vpcmpgtw %xmm1, %xmm0, %xmm0
 ; KNL-NEXT:    vpmovsxwq %xmm0, %zmm0
 ; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k0
-; KNL-NEXT:    kshiftrw $4, %k0, %k1
-; KNL-NEXT:    kmovw %k1, %ecx
-; KNL-NEXT:    kshiftrw $7, %k0, %k1
-; KNL-NEXT:    kmovw %k1, %eax
-; KNL-NEXT:    kshiftrw $1, %k0, %k1
-; KNL-NEXT:    kmovw %k1, %edx
-; KNL-NEXT:    kmovw %k0, %esi
-; KNL-NEXT:    andb %cl, %al
-; KNL-NEXT:    andb %dl, %al
-; KNL-NEXT:    andb %sil, %al
-; KNL-NEXT:    # kill: def $al killed $al killed $eax
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:    andb $-109, %al
+; KNL-NEXT:    cmpb $-109, %al
+; KNL-NEXT:    sete %al
 ; KNL-NEXT:    vzeroupper
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: movmsk_v8i16:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpcmpgtw %xmm1, %xmm0, %k0
-; SKX-NEXT:    kshiftrb $4, %k0, %k1
-; SKX-NEXT:    kmovd %k1, %ecx
-; SKX-NEXT:    kshiftrb $7, %k0, %k1
-; SKX-NEXT:    kmovd %k1, %eax
-; SKX-NEXT:    kshiftrb $1, %k0, %k1
-; SKX-NEXT:    kmovd %k1, %edx
-; SKX-NEXT:    kmovd %k0, %esi
-; SKX-NEXT:    andb %cl, %al
-; SKX-NEXT:    andb %dl, %al
-; SKX-NEXT:    andb %sil, %al
-; SKX-NEXT:    # kill: def $al killed $al killed $eax
+; SKX-NEXT:    kmovd %k0, %eax
+; SKX-NEXT:    andb $-109, %al
+; SKX-NEXT:    cmpb $-109, %al
+; SKX-NEXT:    sete %al
 ; SKX-NEXT:    retq
   %cmp = icmp sgt <8 x i16> %x, %y
   %e1 = extractelement <8 x i1> %cmp, i32 0
@@ -4478,30 +4449,18 @@ define i1 @movmsk_v4f32(<4 x float> %x, <4 x float> %y) {
 ; KNL-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
 ; KNL-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; KNL-NEXT:    vcmpeq_uqps %zmm1, %zmm0, %k0
-; KNL-NEXT:    kshiftrw $3, %k0, %k1
-; KNL-NEXT:    kmovw %k1, %ecx
-; KNL-NEXT:    kshiftrw $2, %k0, %k1
-; KNL-NEXT:    kmovw %k1, %eax
-; KNL-NEXT:    kshiftrw $1, %k0, %k0
-; KNL-NEXT:    kmovw %k0, %edx
-; KNL-NEXT:    orb %cl, %al
-; KNL-NEXT:    orb %dl, %al
-; KNL-NEXT:    # kill: def $al killed $al killed $eax
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:    testb $14, %al
+; KNL-NEXT:    setne %al
 ; KNL-NEXT:    vzeroupper
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: movmsk_v4f32:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vcmpeq_uqps %xmm1, %xmm0, %k0
-; SKX-NEXT:    kshiftrb $3, %k0, %k1
-; SKX-NEXT:    kmovd %k1, %ecx
-; SKX-NEXT:    kshiftrb $2, %k0, %k1
-; SKX-NEXT:    kmovd %k1, %eax
-; SKX-NEXT:    kshiftrb $1, %k0, %k0
-; SKX-NEXT:    kmovd %k0, %edx
-; SKX-NEXT:    orb %cl, %al
-; SKX-NEXT:    orb %dl, %al
-; SKX-NEXT:    # kill: def $al killed $al killed $eax
+; SKX-NEXT:    kmovd %k0, %eax
+; SKX-NEXT:    testb $14, %al
+; SKX-NEXT:    setne %al
 ; SKX-NEXT:    retq
   %cmp = fcmp ueq <4 x float> %x, %y
   %e1 = extractelement <4 x i1> %cmp, i32 1
diff --git a/llvm/test/CodeGen/X86/noreturn-call-win64.ll b/llvm/test/CodeGen/X86/noreturn-call-win64.ll
index 7f9dcc0c9bb9a..6289eef6bb48f 100644
--- a/llvm/test/CodeGen/X86/noreturn-call-win64.ll
+++ b/llvm/test/CodeGen/X86/noreturn-call-win64.ll
@@ -1,8 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-windows-msvc | FileCheck %s
 
-%struct.MakeCleanup = type { i8 }
-%eh.ThrowInfo = type { i32, i32, i32, i32 }
-
 ; Function Attrs: noinline nounwind optnone uwtable
 define dso_local i32 @foo() {
 entry:
@@ -54,58 +51,3 @@ declare dso_local i32 @cond()
 declare dso_local void @abort1() noreturn
 declare dso_local void @abort2() noreturn
 declare dso_local void @abort3() noreturn
-
-define dso_local void @throw_exception() uwtable personality i32 (...)* @__CxxFrameHandler3 {
-entry:
-  %o = alloca %struct.MakeCleanup, align 1
-  %call = invoke i32 @cond()
-          to label %invoke.cont unwind label %ehcleanup
-
-invoke.cont:                                      ; preds = %entry
-  %cmp1 = icmp eq i32 0, %call
-  br i1 %cmp1, label %if.then, label %if.end
-
-if.then:                                          ; preds = %invoke.cont
-  invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null)
-          to label %unreachable unwind label %ehcleanup
-
-if.end:                                           ; preds = %invoke.cont
-  %call2 = invoke i32 @cond()
-          to label %invoke.cont1 unwind label %ehcleanup
-
-invoke.cont1:                                     ; preds = %if.end
-  %cmp2 = icmp eq i32 0, %call2
-  br i1 %cmp2, label %if.then3, label %if.end4
-
-if.then3:                                         ; preds = %invoke.cont1
-  invoke void @_CxxThrowException(i8* null, %eh.ThrowInfo* null)
-          to label %unreachable unwind label %ehcleanup
-
-if.end4:                                          ; preds = %invoke.cont1
-  call void @"??1MakeCleanup@@QEAA@XZ"(%struct.MakeCleanup* nonnull %o)
-  ret void
-
-ehcleanup:                                        ; preds = %if.then3, %if.end, %if.then, %entry
-  %cp = cleanuppad within none []
-  call void @"??1MakeCleanup@@QEAA@XZ"(%struct.MakeCleanup* nonnull %o) [ "funclet"(token %cp) ]
-  cleanupret from %cp unwind to caller
-
-unreachable:                                      ; preds = %if.then3, %if.then
-  unreachable
-}
-
-declare dso_local i32 @__CxxFrameHandler3(...)
-declare dso_local void @_CxxThrowException(i8*, %eh.ThrowInfo*)
-declare dso_local void @"??1MakeCleanup@@QEAA@XZ"(%struct.MakeCleanup*)
-
-; CHECK-LABEL: throw_exception:
-; CHECK: callq cond
-; CHECK: je
-; CHECK: callq cond
-; CHECK: je
-; CHECK: retq
-; CHECK: callq _CxxThrowException
-; CHECK-NOT: {{(addq|subq) .*, %rsp}}
-; CHECK: callq _CxxThrowException
-; CHECK-NOT: {{(addq|subq) .*, %rsp}}
-; CHECK: .seh_handlerdata
diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll b/llvm/test/CodeGen/X86/patchable-prologue.ll
index b66694a39e839..38a2e8852b6b0 100644
--- a/llvm/test/CodeGen/X86/patchable-prologue.ll
+++ b/llvm/test/CodeGen/X86/patchable-prologue.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -filetype=obj -o - -mtriple=x86_64-apple-macosx < %s | llvm-objdump -triple x86_64-apple-macosx -disassemble - | FileCheck %s
+; RUN: llc -verify-machineinstrs -filetype=obj -o - -mtriple=x86_64-apple-macosx < %s | llvm-objdump --triple=x86_64-apple-macosx -d - | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx < %s | FileCheck %s --check-prefix=CHECK-ALIGN
 
 declare void @callee(i64*)
diff --git a/llvm/test/CodeGen/X86/shift-by-signext.ll b/llvm/test/CodeGen/X86/shift-by-signext.ll
index 85ca2bd6e1d39..e315e6aa6be42 100644
--- a/llvm/test/CodeGen/X86/shift-by-signext.ll
+++ b/llvm/test/CodeGen/X86/shift-by-signext.ll
@@ -88,9 +88,9 @@ declare i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
 define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) nounwind {
 ; X86-LABEL: n6_fshl:
 ; X86:       # %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    shldl %cl, %edx, %eax
 ; X86-NEXT:    retl
 ;
@@ -108,9 +108,9 @@ define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) nounwind {
 define i32 @n7_fshr(i32 %x, i32 %y, i8 %shamt) nounwind {
 ; X86-LABEL: n7_fshr:
 ; X86:       # %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    shrdl %cl, %edx, %eax
 ; X86-NEXT:    retl
 ;
diff --git a/llvm/test/CodeGen/X86/shift-double-x86_64.ll b/llvm/test/CodeGen/X86/shift-double-x86_64.ll
index a410595e03cf9..7a086ba364742 100644
--- a/llvm/test/CodeGen/X86/shift-double-x86_64.ll
+++ b/llvm/test/CodeGen/X86/shift-double-x86_64.ll
@@ -8,7 +8,6 @@ define i64 @test1(i64 %hi, i64 %lo, i64 %bits) nounwind {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq %rdx, %rcx
 ; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    andl $63, %ecx
 ; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
 ; CHECK-NEXT:    shldq %cl, %rsi, %rax
 ; CHECK-NEXT:    retq
@@ -25,7 +24,6 @@ define i64 @test2(i64 %hi, i64 %lo, i64 %bits) nounwind {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq %rdx, %rcx
 ; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    andl $63, %ecx
 ; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
 ; CHECK-NEXT:    shrdq %cl, %rdi, %rax
 ; CHECK-NEXT:    retq
diff --git a/llvm/test/CodeGen/X86/shift-double.ll b/llvm/test/CodeGen/X86/shift-double.ll
index 9621c9445937c..c0872957f2b84 100644
--- a/llvm/test/CodeGen/X86/shift-double.ll
+++ b/llvm/test/CodeGen/X86/shift-double.ll
@@ -290,11 +290,9 @@ define i64 @test10(i64 %val, i32 %bits) nounwind {
 define i32 @test11(i32 %hi, i32 %lo, i32 %bits) nounwind {
 ; X86-LABEL: test11:
 ; X86:       # %bb.0:
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    andl $31, %ecx
-; X86-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X86-NEXT:    shldl %cl, %edx, %eax
 ; X86-NEXT:    retl
 ;
@@ -302,7 +300,6 @@ define i32 @test11(i32 %hi, i32 %lo, i32 %bits) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edx, %ecx
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    andl $31, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shldl %cl, %esi, %eax
 ; X64-NEXT:    retq
@@ -317,11 +314,9 @@ define i32 @test11(i32 %hi, i32 %lo, i32 %bits) nounwind {
 define i32 @test12(i32 %hi, i32 %lo, i32 %bits) nounwind {
 ; X86-LABEL: test12:
 ; X86:       # %bb.0:
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    andl $31, %ecx
-; X86-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X86-NEXT:    shrdl %cl, %edx, %eax
 ; X86-NEXT:    retl
 ;
@@ -329,7 +324,6 @@ define i32 @test12(i32 %hi, i32 %lo, i32 %bits) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edx, %ecx
 ; X64-NEXT:    movl %esi, %eax
-; X64-NEXT:    andl $31, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrdl %cl, %edi, %eax
 ; X64-NEXT:    retq
diff --git a/llvm/test/CodeGen/X86/stack-folding-avx512bf16.ll b/llvm/test/CodeGen/X86/stack-folding-avx512bf16.ll
index e368b08798a87..dbc7ddeb82445 100644
--- a/llvm/test/CodeGen/X86/stack-folding-avx512bf16.ll
+++ b/llvm/test/CodeGen/X86/stack-folding-avx512bf16.ll
@@ -32,9 +32,9 @@ define <32 x i16> @stack_fold_cvtne2ps2bf16_mask(<16 x float> %a0, <16 x float>
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vmovdqa64 (%rdi), %zmm2
+; CHECK-NEXT:    vmovaps (%rdi), %zmm2
 ; CHECK-NEXT:    vcvtne2ps2bf16 {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 {%k1} # 64-byte Folded Reload
-; CHECK-NEXT:    vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT:    vmovaps %zmm2, %zmm0
 ; CHECK-NEXT:    retq
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
   %2 = call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %a0, <16 x float> %a1)
@@ -194,9 +194,9 @@ define <16 x i16> @stack_fold_cvtne2ps2bf16_mask_ymm(<8 x float> %a0, <8 x float
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vmovdqa (%rdi), %ymm2
+; CHECK-NEXT:    vmovaps (%rdi), %ymm2
 ; CHECK-NEXT:    vcvtne2ps2bf16 {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm2 {%k1} # 32-byte Folded Reload
-; CHECK-NEXT:    vmovdqa %ymm2, %ymm0
+; CHECK-NEXT:    vmovaps %ymm2, %ymm0
 ; CHECK-NEXT:    retq
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
   %2 = call <16 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.256(<8 x float> %a0, <8 x float> %a1)
@@ -361,9 +361,9 @@ define <8 x i16> @stack_fold_cvtne2ps2bf16_mask_xmm(<4 x float> %a0, <4 x float>
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    kmovd %esi, %k1
-; CHECK-NEXT:    vmovdqa (%rdi), %xmm2
+; CHECK-NEXT:    vmovaps (%rdi), %xmm2
 ; CHECK-NEXT:    vcvtne2ps2bf16 {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 {%k1} # 16-byte Folded Reload
-; CHECK-NEXT:    vmovdqa %xmm2, %xmm0
+; CHECK-NEXT:    vmovaps %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
   %2 = call <8 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.128(<4 x float> %a0, <4 x float> %a1)
diff --git a/llvm/test/CodeGen/X86/stack-guard-oob.ll b/llvm/test/CodeGen/X86/stack-guard-oob.ll
new file mode 100644
index 0000000000000..74eb69328e6dd
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stack-guard-oob.ll
@@ -0,0 +1,415 @@
+; RUN: llc -mtriple=i686 -O0 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -O0 < %s | FileCheck %s
+
+; CHECK-LABEL: in_bounds:
+; CHECK-NOT: __stack_chk_guard
+define i32 @in_bounds() #0 {
+  %var = alloca i32, align 4
+  store i32 0, i32* %var, align 4
+  %gep = getelementptr inbounds i32, i32* %var, i32 0
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: constant_out_of_bounds:
+; CHECK: __stack_chk_guard
+define i32 @constant_out_of_bounds() #0 {
+  %var = alloca i32, align 4
+  store i32 0, i32* %var, align 4
+  %gep = getelementptr inbounds i32, i32* %var, i32 1
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: nonconstant_out_of_bounds:
+; CHECK: __stack_chk_guard
+define i32 @nonconstant_out_of_bounds(i32 %n) #0 {
+  %var = alloca i32, align 4
+  store i32 0, i32* %var, align 4
+  %gep = getelementptr inbounds i32, i32* %var, i32 %n
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_before_gep_in_bounds:
+; CHECK-NOT: __stack_chk_guard
+define i32 @phi_before_gep_in_bounds(i32 %k) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %then
+
+if:
+  br label %then
+
+then:
+  %ptr = phi i32* [ %var1, %entry ], [ %var2, %if ]
+  %gep = getelementptr inbounds i32, i32* %ptr, i32 0
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_before_gep_constant_out_of_bounds:
+; CHECK: __stack_chk_guard
+define i32 @phi_before_gep_constant_out_of_bounds(i32 %k) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %then
+
+if:
+  br label %then
+
+then:
+  %ptr = phi i32* [ %var1, %entry ], [ %var2, %if ]
+  %gep = getelementptr inbounds i32, i32* %ptr, i32 1
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_before_gep_nonconstant_out_of_bounds:
+; CHECK: __stack_chk_guard
+define i32 @phi_before_gep_nonconstant_out_of_bounds(i32 %k, i32 %n) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %then
+
+if:
+  br label %then
+
+then:
+  %ptr = phi i32* [ %var1, %entry ], [ %var2, %if ]
+  %gep = getelementptr inbounds i32, i32* %ptr, i32 %n
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_after_gep_in_bounds:
+; CHECK-NOT: __stack_chk_guard
+define i32 @phi_after_gep_in_bounds(i32 %k) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %else
+
+if:
+  %gep1 = getelementptr inbounds i32, i32* %var1, i32 0
+  br label %then
+
+else:
+  %gep2 = getelementptr inbounds i32, i32* %var2, i32 0
+  br label %then
+
+then:
+  %ptr = phi i32* [ %gep1, %if ], [ %gep2, %else ]
+  %ret = load i32, i32* %ptr, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_after_gep_constant_out_of_bounds_a:
+; CHECK: __stack_chk_guard
+define i32 @phi_after_gep_constant_out_of_bounds_a(i32 %k) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %else
+
+if:
+  %gep1 = getelementptr inbounds i32, i32* %var1, i32 0
+  br label %then
+
+else:
+  %gep2 = getelementptr inbounds i32, i32* %var2, i32 1
+  br label %then
+
+then:
+  %ptr = phi i32* [ %gep1, %if ], [ %gep2, %else ]
+  %ret = load i32, i32* %ptr, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_after_gep_constant_out_of_bounds_b:
+; CHECK: __stack_chk_guard
+define i32 @phi_after_gep_constant_out_of_bounds_b(i32 %k) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %else
+
+if:
+  %gep1 = getelementptr inbounds i32, i32* %var1, i32 1
+  br label %then
+
+else:
+  %gep2 = getelementptr inbounds i32, i32* %var2, i32 0
+  br label %then
+
+then:
+  %ptr = phi i32* [ %gep1, %if ], [ %gep2, %else ]
+  %ret = load i32, i32* %ptr, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_different_types_a:
+; CHECK: __stack_chk_guard
+define i64 @phi_different_types_a(i32 %k) #0 {
+entry:
+  %var1 = alloca i64, align 4
+  %var2 = alloca i32, align 4
+  store i64 0, i64* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %then
+
+if:
+  %bitcast = bitcast i32* %var2 to i64*
+  br label %then
+
+then:
+  %ptr = phi i64* [ %var1, %entry ], [ %bitcast, %if ]
+  %ret = load i64, i64* %ptr, align 4
+  ret i64 %ret
+}
+
+; CHECK-LABEL: phi_different_types_b:
+; CHECK: __stack_chk_guard
+define i64 @phi_different_types_b(i32 %k) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i64, align 4
+  store i32 0, i32* %var1, align 4
+  store i64 0, i64* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %then
+
+if:
+  %bitcast = bitcast i32* %var1 to i64*
+  br label %then
+
+then:
+  %ptr = phi i64* [ %var2, %entry ], [ %bitcast, %if ]
+  %ret = load i64, i64* %ptr, align 4
+  ret i64 %ret
+}
+
+; CHECK-LABEL: phi_after_gep_nonconstant_out_of_bounds_a:
+; CHECK: __stack_chk_guard
+define i32 @phi_after_gep_nonconstant_out_of_bounds_a(i32 %k, i32 %n) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %else
+
+if:
+  %gep1 = getelementptr inbounds i32, i32* %var1, i32 0
+  br label %then
+
+else:
+  %gep2 = getelementptr inbounds i32, i32* %var2, i32 %n
+  br label %then
+
+then:
+  %ptr = phi i32* [ %gep1, %if ], [ %gep2, %else ]
+  %ret = load i32, i32* %ptr, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: phi_after_gep_nonconstant_out_of_bounds_b:
+; CHECK: __stack_chk_guard
+define i32 @phi_after_gep_nonconstant_out_of_bounds_b(i32 %k, i32 %n) #0 {
+entry:
+  %var1 = alloca i32, align 4
+  %var2 = alloca i32, align 4
+  store i32 0, i32* %var1, align 4
+  store i32 0, i32* %var2, align 4
+  %cmp = icmp ne i32 %k, 0
+  br i1 %cmp, label %if, label %else
+
+if:
+  %gep1 = getelementptr inbounds i32, i32* %var1, i32 %n
+  br label %then
+
+else:
+  %gep2 = getelementptr inbounds i32, i32* %var2, i32 0
+  br label %then
+
+then:
+  %ptr = phi i32* [ %gep1, %if ], [ %gep2, %else ]
+  %ret = load i32, i32* %ptr, align 4
+  ret i32 %ret
+}
+
+%struct.outer = type { %struct.inner, %struct.inner }
+%struct.inner = type { i32, i32 }
+
+; CHECK-LABEL: struct_in_bounds:
+; CHECK-NOT: __stack_chk_guard
+define void @struct_in_bounds() #0 {
+  %var = alloca %struct.outer, align 4
+  %outergep = getelementptr inbounds %struct.outer, %struct.outer* %var, i32 0, i32 1
+  %innergep = getelementptr inbounds %struct.inner, %struct.inner* %outergep, i32 0, i32 1
+  store i32 0, i32* %innergep, align 4
+  ret void
+}
+
+; CHECK-LABEL: struct_constant_out_of_bounds_a:
+; CHECK: __stack_chk_guard
+define void @struct_constant_out_of_bounds_a() #0 {
+  %var = alloca %struct.outer, align 4
+  %outergep = getelementptr inbounds %struct.outer, %struct.outer* %var, i32 1, i32 0
+  %innergep = getelementptr inbounds %struct.inner, %struct.inner* %outergep, i32 0, i32 0
+  store i32 0, i32* %innergep, align 4
+  ret void
+}
+
+; CHECK-LABEL: struct_constant_out_of_bounds_b:
+; Here the offset is out-of-bounds of the addressed struct.inner member, but
+; still within bounds of the outer struct so no stack guard is needed.
+; CHECK-NOT: __stack_chk_guard
+define void @struct_constant_out_of_bounds_b() #0 {
+  %var = alloca %struct.outer, align 4
+  %outergep = getelementptr inbounds %struct.outer, %struct.outer* %var, i32 0, i32 0
+  %innergep = getelementptr inbounds %struct.inner, %struct.inner* %outergep, i32 1, i32 0
+  store i32 0, i32* %innergep, align 4
+  ret void
+}
+
+; CHECK-LABEL: struct_constant_out_of_bounds_c:
+; Here we are out-of-bounds of both the inner and outer struct.
+; CHECK: __stack_chk_guard
+define void @struct_constant_out_of_bounds_c() #0 {
+  %var = alloca %struct.outer, align 4
+  %outergep = getelementptr inbounds %struct.outer, %struct.outer* %var, i32 0, i32 1
+  %innergep = getelementptr inbounds %struct.inner, %struct.inner* %outergep, i32 1, i32 0
+  store i32 0, i32* %innergep, align 4
+  ret void
+}
+
+; CHECK-LABEL: struct_nonconstant_out_of_bounds_a:
+; CHECK: __stack_chk_guard
+define void @struct_nonconstant_out_of_bounds_a(i32 %n) #0 {
+  %var = alloca %struct.outer, align 4
+  %outergep = getelementptr inbounds %struct.outer, %struct.outer* %var, i32 %n, i32 0
+  %innergep = getelementptr inbounds %struct.inner, %struct.inner* %outergep, i32 0, i32 0
+  store i32 0, i32* %innergep, align 4
+  ret void
+}
+
+; CHECK-LABEL: struct_nonconstant_out_of_bounds_b:
+; CHECK: __stack_chk_guard
+define void @struct_nonconstant_out_of_bounds_b(i32 %n) #0 {
+  %var = alloca %struct.outer, align 4
+  %outergep = getelementptr inbounds %struct.outer, %struct.outer* %var, i32 0, i32 0
+  %innergep = getelementptr inbounds %struct.inner, %struct.inner* %outergep, i32 %n, i32 0
+  store i32 0, i32* %innergep, align 4
+  ret void
+}
+
+; CHECK-LABEL: bitcast_smaller_load
+; CHECK-NOT: __stack_chk_guard
+define i32 @bitcast_smaller_load() #0 {
+  %var = alloca i64, align 4
+  store i64 0, i64* %var, align 4
+  %bitcast = bitcast i64* %var to i32*
+  %ret = load i32, i32* %bitcast, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: bitcast_same_size_load
+; CHECK-NOT: __stack_chk_guard
+define i32 @bitcast_same_size_load() #0 {
+  %var = alloca i64, align 4
+  store i64 0, i64* %var, align 4
+  %bitcast = bitcast i64* %var to %struct.inner*
+  %gep = getelementptr inbounds %struct.inner, %struct.inner* %bitcast, i32 0, i32 1
+  %ret = load i32, i32* %gep, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: bitcast_larger_load
+; CHECK: __stack_chk_guard
+define i64 @bitcast_larger_load() #0 {
+  %var = alloca i32, align 4
+  store i32 0, i32* %var, align 4
+  %bitcast = bitcast i32* %var to i64*
+  %ret = load i64, i64* %bitcast, align 4
+  ret i64 %ret
+}
+
+; CHECK-LABEL: bitcast_larger_store
+; CHECK: __stack_chk_guard
+define i32 @bitcast_larger_store() #0 {
+  %var = alloca i32, align 4
+  %bitcast = bitcast i32* %var to i64*
+  store i64 0, i64* %bitcast, align 4
+  %ret = load i32, i32* %var, align 4
+  ret i32 %ret
+}
+
+; CHECK-LABEL: bitcast_larger_cmpxchg
+; CHECK: __stack_chk_guard
+define i64 @bitcast_larger_cmpxchg(i64 %desired, i64 %new) #0 {
+  %var = alloca i32, align 4
+  %bitcast = bitcast i32* %var to i64*
+  %pair = cmpxchg i64* %bitcast, i64 %desired, i64 %new seq_cst monotonic
+  %ret = extractvalue { i64, i1 } %pair, 0
+  ret i64 %ret
+}
+
+; CHECK-LABEL: bitcast_larger_atomic_rmw
+; CHECK: __stack_chk_guard
+define i64 @bitcast_larger_atomic_rmw() #0 {
+  %var = alloca i32, align 4
+  %bitcast = bitcast i32* %var to i64*
+  %ret = atomicrmw add i64* %bitcast, i64 1 monotonic
+  ret i64 %ret
+}
+
+%struct.packed = type <{ i16, i32 }>
+
+; CHECK-LABEL: bitcast_overlap
+; CHECK: __stack_chk_guard
+define i32 @bitcast_overlap() #0 {
+  %var = alloca i32, align 4
+  %bitcast = bitcast i32* %var to %struct.packed*
+  %gep = getelementptr inbounds %struct.packed, %struct.packed* %bitcast, i32 0, i32 1
+  %ret = load i32, i32* %gep, align 2
+  ret i32 %ret
+}
+
+%struct.multi_dimensional = type { [10 x [10 x i32]], i32 }
+
+; CHECK-LABEL: multi_dimensional_array
+; CHECK: __stack_chk_guard
+define i32 @multi_dimensional_array() #0 {
+  %var = alloca %struct.multi_dimensional, align 4
+  %gep1 = getelementptr inbounds %struct.multi_dimensional, %struct.multi_dimensional* %var, i32 0, i32 0
+  %gep2 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* %gep1, i32 0, i32 10
+  %gep3 = getelementptr inbounds [10 x i32], [10 x i32]* %gep2, i32 0, i32 5
+  %ret = load i32, i32* %gep3, align 4
+  ret i32 %ret
+}
+
+attributes #0 = { sspstrong }
diff --git a/llvm/test/CodeGen/X86/vector-fshl-rot-512.ll b/llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
index 1c37b721b9c2a..2786fe5113014 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
@@ -124,23 +124,21 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
 ; AVX512F-NEXT:    vpsllw $4, %ymm3, %ymm6
 ; AVX512F-NEXT:    vpand %ymm5, %ymm6, %ymm6
 ; AVX512F-NEXT:    vpor %ymm4, %ymm6, %ymm4
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; AVX512F-NEXT:    vpand %ymm6, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpsllw $5, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
 ; AVX512F-NEXT:    vpsrlw $6, %ymm3, %ymm4
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; AVX512F-NEXT:    vpandn %ymm4, %ymm7, %ymm4
-; AVX512F-NEXT:    vpsllw $2, %ymm3, %ymm8
-; AVX512F-NEXT:    vpand %ymm7, %ymm8, %ymm8
-; AVX512F-NEXT:    vpor %ymm4, %ymm8, %ymm4
+; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; AVX512F-NEXT:    vpandn %ymm4, %ymm6, %ymm4
+; AVX512F-NEXT:    vpsllw $2, %ymm3, %ymm7
+; AVX512F-NEXT:    vpand %ymm6, %ymm7, %ymm7
+; AVX512F-NEXT:    vpor %ymm4, %ymm7, %ymm4
 ; AVX512F-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
 ; AVX512F-NEXT:    vpsrlw $7, %ymm3, %ymm4
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; AVX512F-NEXT:    vpand %ymm4, %ymm8, %ymm4
-; AVX512F-NEXT:    vpaddb %ymm3, %ymm3, %ymm9
-; AVX512F-NEXT:    vpor %ymm4, %ymm9, %ymm4
+; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; AVX512F-NEXT:    vpand %ymm7, %ymm4, %ymm4
+; AVX512F-NEXT:    vpaddb %ymm3, %ymm3, %ymm8
+; AVX512F-NEXT:    vpor %ymm4, %ymm8, %ymm4
 ; AVX512F-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm2
 ; AVX512F-NEXT:    vpsrlw $4, %ymm0, %ymm3
@@ -148,18 +146,17 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
 ; AVX512F-NEXT:    vpsllw $4, %ymm0, %ymm4
 ; AVX512F-NEXT:    vpand %ymm5, %ymm4, %ymm4
 ; AVX512F-NEXT:    vpor %ymm3, %ymm4, %ymm3
-; AVX512F-NEXT:    vpand %ymm6, %ymm1, %ymm1
 ; AVX512F-NEXT:    vpsllw $5, %ymm1, %ymm1
 ; AVX512F-NEXT:    vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpsrlw $6, %ymm0, %ymm3
-; AVX512F-NEXT:    vpandn %ymm3, %ymm7, %ymm3
+; AVX512F-NEXT:    vpandn %ymm3, %ymm6, %ymm3
 ; AVX512F-NEXT:    vpsllw $2, %ymm0, %ymm4
-; AVX512F-NEXT:    vpand %ymm7, %ymm4, %ymm4
+; AVX512F-NEXT:    vpand %ymm6, %ymm4, %ymm4
 ; AVX512F-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512F-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
 ; AVX512F-NEXT:    vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpsrlw $7, %ymm0, %ymm3
-; AVX512F-NEXT:    vpand %ymm3, %ymm8, %ymm3
+; AVX512F-NEXT:    vpand %ymm7, %ymm3, %ymm3
 ; AVX512F-NEXT:    vpaddb %ymm0, %ymm0, %ymm4
 ; AVX512F-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512F-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
@@ -175,36 +172,33 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
 ; AVX512VL-NEXT:    vpsllw $4, %ymm3, %ymm5
 ; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
 ; AVX512VL-NEXT:    vpternlogq $226, %ymm4, %ymm6, %ymm5
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; AVX512VL-NEXT:    vpand %ymm4, %ymm2, %ymm2
 ; AVX512VL-NEXT:    vpsllw $5, %ymm2, %ymm2
 ; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm5, %ymm3, %ymm3
-; AVX512VL-NEXT:    vpsrlw $6, %ymm3, %ymm5
-; AVX512VL-NEXT:    vpsllw $2, %ymm3, %ymm7
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; AVX512VL-NEXT:    vpternlogq $226, %ymm5, %ymm8, %ymm7
+; AVX512VL-NEXT:    vpsrlw $6, %ymm3, %ymm4
+; AVX512VL-NEXT:    vpsllw $2, %ymm3, %ymm5
+; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; AVX512VL-NEXT:    vpternlogq $226, %ymm4, %ymm7, %ymm5
 ; AVX512VL-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
-; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm7, %ymm3, %ymm3
-; AVX512VL-NEXT:    vpsrlw $7, %ymm3, %ymm5
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; AVX512VL-NEXT:    vpand %ymm7, %ymm5, %ymm5
-; AVX512VL-NEXT:    vpaddb %ymm3, %ymm3, %ymm9
-; AVX512VL-NEXT:    vpor %ymm5, %ymm9, %ymm5
+; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm5, %ymm3, %ymm3
+; AVX512VL-NEXT:    vpsrlw $7, %ymm3, %ymm4
+; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; AVX512VL-NEXT:    vpand %ymm5, %ymm4, %ymm4
+; AVX512VL-NEXT:    vpaddb %ymm3, %ymm3, %ymm8
+; AVX512VL-NEXT:    vpor %ymm4, %ymm8, %ymm4
 ; AVX512VL-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
-; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm5, %ymm3, %ymm2
+; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm2
 ; AVX512VL-NEXT:    vpsrlw $4, %ymm0, %ymm3
-; AVX512VL-NEXT:    vpsllw $4, %ymm0, %ymm5
-; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm6, %ymm5
-; AVX512VL-NEXT:    vpand %ymm4, %ymm1, %ymm1
+; AVX512VL-NEXT:    vpsllw $4, %ymm0, %ymm4
+; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm6, %ymm4
 ; AVX512VL-NEXT:    vpsllw $5, %ymm1, %ymm1
-; AVX512VL-NEXT:    vpblendvb %ymm1, %ymm5, %ymm0, %ymm0
+; AVX512VL-NEXT:    vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpsrlw $6, %ymm0, %ymm3
 ; AVX512VL-NEXT:    vpsllw $2, %ymm0, %ymm4
-; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm8, %ymm4
+; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm7, %ymm4
 ; AVX512VL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
 ; AVX512VL-NEXT:    vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpsrlw $7, %ymm0, %ymm3
-; AVX512VL-NEXT:    vpand %ymm7, %ymm3, %ymm3
+; AVX512VL-NEXT:    vpand %ymm5, %ymm3, %ymm3
 ; AVX512VL-NEXT:    vpaddb %ymm0, %ymm0, %ymm4
 ; AVX512VL-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512VL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/vector-fshr-rot-512.ll b/llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
index 4862a88e4bf74..3e433a8bdfcc9 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
@@ -132,23 +132,21 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
 ; AVX512F-NEXT:    vpor %ymm4, %ymm6, %ymm4
 ; AVX512F-NEXT:    vpxor %xmm6, %xmm6, %xmm6
 ; AVX512F-NEXT:    vpsubb %ymm2, %ymm6, %ymm2
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; AVX512F-NEXT:    vpand %ymm7, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpsllw $5, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
 ; AVX512F-NEXT:    vpsrlw $6, %ymm3, %ymm4
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; AVX512F-NEXT:    vpandn %ymm4, %ymm8, %ymm4
-; AVX512F-NEXT:    vpsllw $2, %ymm3, %ymm9
-; AVX512F-NEXT:    vpand %ymm8, %ymm9, %ymm9
-; AVX512F-NEXT:    vpor %ymm4, %ymm9, %ymm4
+; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; AVX512F-NEXT:    vpandn %ymm4, %ymm7, %ymm4
+; AVX512F-NEXT:    vpsllw $2, %ymm3, %ymm8
+; AVX512F-NEXT:    vpand %ymm7, %ymm8, %ymm8
+; AVX512F-NEXT:    vpor %ymm4, %ymm8, %ymm4
 ; AVX512F-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
 ; AVX512F-NEXT:    vpsrlw $7, %ymm3, %ymm4
-; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; AVX512F-NEXT:    vpand %ymm4, %ymm9, %ymm4
-; AVX512F-NEXT:    vpaddb %ymm3, %ymm3, %ymm10
-; AVX512F-NEXT:    vpor %ymm4, %ymm10, %ymm4
+; AVX512F-NEXT:    vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; AVX512F-NEXT:    vpand %ymm4, %ymm8, %ymm4
+; AVX512F-NEXT:    vpaddb %ymm3, %ymm3, %ymm9
+; AVX512F-NEXT:    vpor %ymm4, %ymm9, %ymm4
 ; AVX512F-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
 ; AVX512F-NEXT:    vpblendvb %ymm2, %ymm4, %ymm3, %ymm2
 ; AVX512F-NEXT:    vpsrlw $4, %ymm0, %ymm3
@@ -157,18 +155,17 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
 ; AVX512F-NEXT:    vpand %ymm5, %ymm4, %ymm4
 ; AVX512F-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512F-NEXT:    vpsubb %ymm1, %ymm6, %ymm1
-; AVX512F-NEXT:    vpand %ymm7, %ymm1, %ymm1
 ; AVX512F-NEXT:    vpsllw $5, %ymm1, %ymm1
 ; AVX512F-NEXT:    vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpsrlw $6, %ymm0, %ymm3
-; AVX512F-NEXT:    vpandn %ymm3, %ymm8, %ymm3
+; AVX512F-NEXT:    vpandn %ymm3, %ymm7, %ymm3
 ; AVX512F-NEXT:    vpsllw $2, %ymm0, %ymm4
-; AVX512F-NEXT:    vpand %ymm4, %ymm8, %ymm4
+; AVX512F-NEXT:    vpand %ymm7, %ymm4, %ymm4
 ; AVX512F-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512F-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
 ; AVX512F-NEXT:    vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpsrlw $7, %ymm0, %ymm3
-; AVX512F-NEXT:    vpand %ymm3, %ymm9, %ymm3
+; AVX512F-NEXT:    vpand %ymm3, %ymm8, %ymm3
 ; AVX512F-NEXT:    vpaddb %ymm0, %ymm0, %ymm4
 ; AVX512F-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512F-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
@@ -186,37 +183,34 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
 ; AVX512VL-NEXT:    vpternlogq $226, %ymm4, %ymm6, %ymm5
 ; AVX512VL-NEXT:    vpxor %xmm4, %xmm4, %xmm4
 ; AVX512VL-NEXT:    vpsubb %ymm2, %ymm4, %ymm2
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; AVX512VL-NEXT:    vpand %ymm7, %ymm2, %ymm2
 ; AVX512VL-NEXT:    vpsllw $5, %ymm2, %ymm2
 ; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm5, %ymm3, %ymm3
 ; AVX512VL-NEXT:    vpsrlw $6, %ymm3, %ymm5
-; AVX512VL-NEXT:    vpsllw $2, %ymm3, %ymm8
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; AVX512VL-NEXT:    vpternlogq $226, %ymm5, %ymm9, %ymm8
+; AVX512VL-NEXT:    vpsllw $2, %ymm3, %ymm7
+; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; AVX512VL-NEXT:    vpternlogq $226, %ymm5, %ymm8, %ymm7
 ; AVX512VL-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
-; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm8, %ymm3, %ymm3
+; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm7, %ymm3, %ymm3
 ; AVX512VL-NEXT:    vpsrlw $7, %ymm3, %ymm5
-; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; AVX512VL-NEXT:    vpand %ymm5, %ymm8, %ymm5
-; AVX512VL-NEXT:    vpaddb %ymm3, %ymm3, %ymm10
-; AVX512VL-NEXT:    vpor %ymm5, %ymm10, %ymm5
+; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
+; AVX512VL-NEXT:    vpand %ymm7, %ymm5, %ymm5
+; AVX512VL-NEXT:    vpaddb %ymm3, %ymm3, %ymm9
+; AVX512VL-NEXT:    vpor %ymm5, %ymm9, %ymm5
 ; AVX512VL-NEXT:    vpaddb %ymm2, %ymm2, %ymm2
 ; AVX512VL-NEXT:    vpblendvb %ymm2, %ymm5, %ymm3, %ymm2
 ; AVX512VL-NEXT:    vpsrlw $4, %ymm0, %ymm3
 ; AVX512VL-NEXT:    vpsllw $4, %ymm0, %ymm5
 ; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm6, %ymm5
 ; AVX512VL-NEXT:    vpsubb %ymm1, %ymm4, %ymm1
-; AVX512VL-NEXT:    vpand %ymm7, %ymm1, %ymm1
 ; AVX512VL-NEXT:    vpsllw $5, %ymm1, %ymm1
 ; AVX512VL-NEXT:    vpblendvb %ymm1, %ymm5, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpsrlw $6, %ymm0, %ymm3
 ; AVX512VL-NEXT:    vpsllw $2, %ymm0, %ymm4
-; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm9, %ymm4
+; AVX512VL-NEXT:    vpternlogq $226, %ymm3, %ymm8, %ymm4
 ; AVX512VL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
 ; AVX512VL-NEXT:    vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpsrlw $7, %ymm0, %ymm3
-; AVX512VL-NEXT:    vpand %ymm3, %ymm8, %ymm3
+; AVX512VL-NEXT:    vpand %ymm7, %ymm3, %ymm3
 ; AVX512VL-NEXT:    vpaddb %ymm0, %ymm0, %ymm4
 ; AVX512VL-NEXT:    vpor %ymm3, %ymm4, %ymm3
 ; AVX512VL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/xray-section-group.ll b/llvm/test/CodeGen/X86/xray-section-group.ll
index cd742a6b38d05..7c5d38ad17096 100644
--- a/llvm/test/CodeGen/X86/xray-section-group.ll
+++ b/llvm/test/CodeGen/X86/xray-section-group.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -verify-machineinstrs -filetype=asm -o - -mtriple=x86_64-unknown-linux-gnu -function-sections < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -filetype=obj -o %t -mtriple=x86_64-unknown-linux-gnu -function-sections < %s
-; RUN: llvm-objdump -triple x86_64-unknown-linux-gnu -disassemble-all %t | FileCheck %s --check-prefix=CHECK-OBJ
+; RUN: llvm-objdump --triple=x86_64-unknown-linux-gnu --disassemble-all %t | FileCheck %s --check-prefix=CHECK-OBJ
 
 define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
 ; CHECK: .section .text.foo,"ax",@progbits
diff --git a/llvm/test/DebugInfo/AArch64/big-endian-dump.ll b/llvm/test/DebugInfo/AArch64/big-endian-dump.ll
index 4a1a9e78ae9f3..d18f82ea612e4 100644
--- a/llvm/test/DebugInfo/AArch64/big-endian-dump.ll
+++ b/llvm/test/DebugInfo/AArch64/big-endian-dump.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O0 -filetype=obj -mtriple=aarch64_be-none-linux < %s | llvm-dwarfdump - | FileCheck %s
 
-; CHECK: file format ELF64-aarch64-big
+; CHECK: file format elf64-bigaarch64
 
 target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128"
 
diff --git a/llvm/test/DebugInfo/AArch64/dbgcall-site-float-entry-value.ll b/llvm/test/DebugInfo/AArch64/dbgcall-site-float-entry-value.ll
new file mode 100644
index 0000000000000..a925cd0c1452d
--- /dev/null
+++ b/llvm/test/DebugInfo/AArch64/dbgcall-site-float-entry-value.ll
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple aarch64-linux-gnu -emit-call-site-info -debug-entry-values -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s
+
+; Based on the following C reproducer:
+;
+; extern void callee(float);
+;
+; void foo(float param) {
+;   callee(param);
+; }
+
+; Verify that a call site value using DW_OP_GNU_entry_value(DW_OP_regx B0) is
+; emitted for the float parameter. Previously the entry value's multi-byte
+; DW_OP_regx expression would be truncated.
+
+; CHECK: DW_TAG_GNU_call_site_parameter
+; CHECK-NEXT: DW_AT_location (DW_OP_regx B0)
+; CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_regx B0)
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64"
+
+; Function Attrs: nounwind
+define dso_local void @foo(float %param) local_unnamed_addr !dbg !12 {
+entry:
+  tail call void @callee(float %param), !dbg !13
+  ret void, !dbg !14
+}
+
+declare !dbg !4 dso_local void @callee(float) local_unnamed_addr
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8, !9, !10}
+!llvm.ident = !{!11}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "float.c", directory: "/")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "callee", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null, !7}
+!7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+!8 = !{i32 7, !"Dwarf Version", i32 4}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !{i32 1, !"wchar_size", i32 4}
+!11 = !{!"clang version 11.0.0 "}
+!12 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
+!13 = !DILocation(line: 4, scope: !12)
+!14 = !DILocation(line: 5, scope: !12)
diff --git a/llvm/test/DebugInfo/AArch64/little-endian-dump.ll b/llvm/test/DebugInfo/AArch64/little-endian-dump.ll
index 65330c9eb95ae..d4626db47a141 100644
--- a/llvm/test/DebugInfo/AArch64/little-endian-dump.ll
+++ b/llvm/test/DebugInfo/AArch64/little-endian-dump.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O0 -filetype=obj -mtriple=aarch64-none-linux < %s | llvm-dwarfdump - | FileCheck %s
 
-; CHECK: file format ELF64-aarch64-little
+; CHECK: file format elf64-littleaarch64
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 
diff --git a/llvm/test/DebugInfo/AMDGPU/print-reg-name.s b/llvm/test/DebugInfo/AMDGPU/print-reg-name.s
index 8c2ae89ce4280..fdd2c59bdd168 100644
--- a/llvm/test/DebugInfo/AMDGPU/print-reg-name.s
+++ b/llvm/test/DebugInfo/AMDGPU/print-reg-name.s
@@ -1,10 +1,16 @@
 ; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm %s | FileCheck %s
 
-; Check that we can print symbolic register operands in CFI instructions.
+; FIXME: Currently we can't print register names in CFI directives
+; without extending MC to support DWARF register names that are distinct
+; from physical register names.
 
 .text
 f:
 .cfi_startproc
-; CHECK: .cfi_undefined s0
-.cfi_undefined s0
+; CHECK: .cfi_undefined 2560
+.cfi_undefined 2560
+; FIXME: Until we implement a distinct set of DWARF register names we
+; will continue to parse physical registers and pick an arbitrary encoding.
+; CHECK: .cfi_undefined 2560
+.cfi_undefined v0
 .cfi_endproc
diff --git a/llvm/test/DebugInfo/AMDGPU/register-mapping.s b/llvm/test/DebugInfo/AMDGPU/register-mapping.s
deleted file mode 100644
index 5d967c36eb204..0000000000000
--- a/llvm/test/DebugInfo/AMDGPU/register-mapping.s
+++ /dev/null
@@ -1,37 +0,0 @@
-; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s
-
-; Check that we implement the DWARF register mapping.
-
-.text
-f:
-.cfi_startproc
-; CHECK: CIE
-; CHECK: Return address column: 16
-
-; CHECK: FDE
-; CHECK: DW_CFA_undefined: reg16
-.cfi_undefined pc
-; CHECK: DW_CFA_undefined: reg17
-.cfi_undefined exec
-
-; CHECK: DW_CFA_undefined: reg32
-.cfi_undefined s0
-; CHECK: DW_CFA_undefined: reg95
-.cfi_undefined s63
-
-; CHECK: DW_CFA_undefined: reg1088
-.cfi_undefined s64
-; CHECK: DW_CFA_undefined: reg1129
-.cfi_undefined s105
-
-; CHECK: DW_CFA_undefined: reg2560
-.cfi_undefined v0
-; CHECK: DW_CFA_undefined: reg2815
-.cfi_undefined v255
-
-; CHECK: DW_CFA_undefined: reg3072
-.cfi_undefined a0
-; CHECK: DW_CFA_undefined: reg3327
-.cfi_undefined a255
-
-.cfi_endproc
diff --git a/llvm/test/DebugInfo/ARM/big-endian-dump.ll b/llvm/test/DebugInfo/ARM/big-endian-dump.ll
index 7bfe24eb2300b..daaa9b4f29a2e 100644
--- a/llvm/test/DebugInfo/ARM/big-endian-dump.ll
+++ b/llvm/test/DebugInfo/ARM/big-endian-dump.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O0 -filetype=obj -mtriple=armeb-none-linux < %s | llvm-dwarfdump - | FileCheck %s
 
-; CHECK: file format ELF32-arm-big
+; CHECK: file format elf32-bigarm
 
 target datalayout = "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 
diff --git a/llvm/test/DebugInfo/ARM/little-endian-dump.ll b/llvm/test/DebugInfo/ARM/little-endian-dump.ll
index b5f86e979be9e..60f6675edcde3 100644
--- a/llvm/test/DebugInfo/ARM/little-endian-dump.ll
+++ b/llvm/test/DebugInfo/ARM/little-endian-dump.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O0 -filetype=obj -mtriple=arm-none-linux < %s | llvm-dwarfdump - | FileCheck %s
 
-; CHECK: file format ELF32-arm-little
+; CHECK: file format elf32-littlearm
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 
diff --git a/llvm/test/DebugInfo/COFF/no-cus.ll b/llvm/test/DebugInfo/COFF/no-cus.ll
index 349fe680de665..4aec54d65a0ee 100644
--- a/llvm/test/DebugInfo/COFF/no-cus.ll
+++ b/llvm/test/DebugInfo/COFF/no-cus.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -filetype=obj -o %t.o
-; RUN: llvm-objdump -section-headers %t.o | FileCheck %s
+; RUN: llvm-objdump --section-headers %t.o | FileCheck %s
 
 ; Don't emit debug info in this scenario and don't crash.
 
diff --git a/llvm/test/DebugInfo/MIR/X86/callsite-stack-value.mir b/llvm/test/DebugInfo/MIR/X86/callsite-stack-value.mir
new file mode 100644
index 0000000000000..6d69f06302029
--- /dev/null
+++ b/llvm/test/DebugInfo/MIR/X86/callsite-stack-value.mir
@@ -0,0 +1,68 @@
+# RUN: llc -start-after=livedebugvalues -mtriple=x86_64-apple-darwin -o - %s -filetype=obj \
+# RUN:   -emit-call-site-info -debug-entry-values | llvm-dwarfdump - | FileCheck %s -implicit-check-not=call_site_parameter
+
+# CHECK: DW_TAG_formal_parameter
+# CHECK-NEXT: DW_AT_location
+# CHECK-NEXT: DW_OP_reg17
+
+# struct S {
+#   float w;
+# };
+# void f(long w, long b);
+# void g(struct S s) {
+#   int w = s.w;
+#   f(w, w*4);
+# }
+
+--- |
+  define void @g(float %s.coerce) local_unnamed_addr !dbg !20 {
+  entry:
+    ret void, !dbg !31
+  }
+  declare !dbg !14 void @f(i64, i64) local_unnamed_addr
+  !llvm.module.flags = !{!6, !7, !8, !9}
+  !llvm.dbg.cu = !{!10}
+  !6 = !{i32 7, !"Dwarf Version", i32 4}
+  !7 = !{i32 2, !"Debug Info Version", i32 3}
+  !8 = !{i32 1, !"wchar_size", i32 4}
+  !9 = !{i32 7, !"PIC Level", i32 2}
+  !10 = distinct !DICompileUnit(language: DW_LANG_ObjC, file: !15, producer: "", isOptimized: true, runtimeVersion: 2, emissionKind: FullDebug, enums: !12, retainedTypes: !13, nameTableKind: None, sysroot: "/")
+  !12 = !{}
+  !13 = !{!14}
+  !14 = !DISubprogram(name: "f", scope: !15, file: !15, line: 4, type: !16, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !12)
+  !15 = !DIFile(filename: "test.m", directory: "/")
+  !16 = !DISubroutineType(types: !17)
+  !17 = !{null, !18, !18}
+  !18 = !DIBasicType(name: "long int", size: 64, encoding: DW_ATE_signed)
+  !20 = distinct !DISubprogram(name: "g", scope: !15, file: !15, line: 5, type: !21, scopeLine: 5, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !10, retainedNodes: !27)
+  !21 = !DISubroutineType(types: !22)
+  !22 = !{null, !23}
+  !23 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S", file: !15, line: 1, size: 32, elements: !24)
+  !24 = !{!25}
+  !25 = !DIDerivedType(tag: DW_TAG_member, name: "w", scope: !23, file: !15, line: 2, baseType: !26, size: 32)
+  !26 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+  !27 = !{!28, !29}
+  !28 = !DILocalVariable(name: "s", arg: 1, scope: !20, file: !15, line: 5, type: !23)
+  !29 = !DILocalVariable(name: "w", scope: !20, file: !15, line: 6, type: !30)
+  !30 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !31 = !DILocation(line: 0, scope: !20)
+name:            g
+callSites:
+  - { bb: 0, offset: 13, fwdArgRegs: 
+      - { arg: 1, reg: '$rsi' } }
+body:             |
+  bb.0.entry:
+    DBG_VALUE $xmm0, $noreg, !28, !DIExpression(), debug-location !31
+    DBG_VALUE $xmm0, $noreg, !28, !DIExpression(), debug-location !31
+    frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset $rbp, -16
+    $rbp = frame-setup MOV64rr $rsp
+    CFI_INSTRUCTION def_cfa_register $rbp
+    renamable $eax = nofpexcept CVTTSS2SIrr killed renamable $xmm0, implicit $mxcsr, debug-location !31
+    DBG_VALUE $eax, $noreg, !29, !DIExpression(), debug-location !31
+    renamable $rdi = MOVSX64rr32 killed renamable $eax, debug-location !31
+    renamable $eax = LEA64_32r $noreg, 4, renamable $rdi, 0, $noreg, debug-location !31
+    renamable $rsi = MOVSX64rr32 killed renamable $eax, debug-location !31
+    $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
+    TAILJMPd64 @f, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, debug-location !31
diff --git a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
index b283522ea3a91..e923810aa72fa 100644
--- a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
+++ b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o %t.o
 ; RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=READOBJ-RELOCS %s
-; RUN: llvm-objdump --source %t.o | FileCheck -check-prefix=OBJDUMP-SOURCE %s
+; RUN: llvm-objdump --source %t.o | FileCheck --check-prefix=OBJDUMP-SOURCE %s
 ; RUN: llvm-dwarfdump --debug-info --debug-line %t.o | \
 ; RUN:     FileCheck -check-prefix=DWARF-DUMP %s
 
diff --git a/llvm/test/DebugInfo/Sparc/gnu-window-save.ll b/llvm/test/DebugInfo/Sparc/gnu-window-save.ll
index d81bcb6edb03b..38467bd0c7bed 100644
--- a/llvm/test/DebugInfo/Sparc/gnu-window-save.ll
+++ b/llvm/test/DebugInfo/Sparc/gnu-window-save.ll
@@ -4,7 +4,7 @@
 ; Check for DW_CFA_GNU_Window_save in debug_frame. Also, Ensure that relocations
 ; are performed correctly in debug_info.
 
-; SPARC64: file format ELF64-sparc
+; SPARC64: file format elf64-sparc
 
 ; SPARC64: .debug_info
 ; SPARC64:      DW_TAG_compile_unit
@@ -20,7 +20,7 @@
 ; SPARC64-NEXT: DW_CFA_register
 
 
-; SPARC32: file format ELF32-sparc
+; SPARC32: file format elf32-sparc
 
 ; SPARC32: .debug_info
 ; SPARC32:      DW_TAG_compile_unit
diff --git a/llvm/test/DebugInfo/X86/DW_AT_location-reference.ll b/llvm/test/DebugInfo/X86/DW_AT_location-reference.ll
index 74b0afb2cf052..d516a4c5d0813 100644
--- a/llvm/test/DebugInfo/X86/DW_AT_location-reference.ll
+++ b/llvm/test/DebugInfo/X86/DW_AT_location-reference.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -O1 -filetype=obj -mtriple=x86_64-apple-darwin < %s > %t
 ; RUN: llvm-dwarfdump -v %t  | FileCheck %s
-; RUN: llvm-objdump -r %t | FileCheck -check-prefix=DARWIN %s
+; RUN: llvm-objdump -r %t | FileCheck --check-prefix=DARWIN %s
 ; RUN: llc -O1 -filetype=obj -mtriple=x86_64-pc-linux-gnu < %s > %t
 ; RUN: llvm-dwarfdump -v %t  | FileCheck %s
-; RUN: llvm-objdump -r %t | FileCheck -check-prefix=LINUX %s
+; RUN: llvm-objdump -r %t | FileCheck --check-prefix=LINUX %s
 
 ; PR9493
 ; Adapted from the original test case in r127757.
diff --git a/llvm/test/MC/AArch64/SVE/abs.s b/llvm/test/MC/AArch64/SVE/abs.s
index 460f846cdc034..5c03ea0e9819c 100644
--- a/llvm/test/MC/AArch64/SVE/abs.s
+++ b/llvm/test/MC/AArch64/SVE/abs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/add.s b/llvm/test/MC/AArch64/SVE/add.s
index 2064181d18d24..467352d4e9988 100644
--- a/llvm/test/MC/AArch64/SVE/add.s
+++ b/llvm/test/MC/AArch64/SVE/add.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/addpl.s b/llvm/test/MC/AArch64/SVE/addpl.s
index a5288f8b26138..b508b277d6015 100644
--- a/llvm/test/MC/AArch64/SVE/addpl.s
+++ b/llvm/test/MC/AArch64/SVE/addpl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/addvl.s b/llvm/test/MC/AArch64/SVE/addvl.s
index 6ae5a9df8e2ab..31de092abe5b4 100644
--- a/llvm/test/MC/AArch64/SVE/addvl.s
+++ b/llvm/test/MC/AArch64/SVE/addvl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/adr.s b/llvm/test/MC/AArch64/SVE/adr.s
index 80f2c3f8fead3..2b2a6a003a029 100644
--- a/llvm/test/MC/AArch64/SVE/adr.s
+++ b/llvm/test/MC/AArch64/SVE/adr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/and.s b/llvm/test/MC/AArch64/SVE/and.s
index 0dc99ab2be9d6..b45c84db14572 100644
--- a/llvm/test/MC/AArch64/SVE/and.s
+++ b/llvm/test/MC/AArch64/SVE/and.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ands.s b/llvm/test/MC/AArch64/SVE/ands.s
index 07c890709b498..eb48e75921557 100644
--- a/llvm/test/MC/AArch64/SVE/ands.s
+++ b/llvm/test/MC/AArch64/SVE/ands.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/andv.s b/llvm/test/MC/AArch64/SVE/andv.s
index da0ec1f5ed5cd..431c7b09db276 100644
--- a/llvm/test/MC/AArch64/SVE/andv.s
+++ b/llvm/test/MC/AArch64/SVE/andv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/asr.s b/llvm/test/MC/AArch64/SVE/asr.s
index d514eda2af13c..4ba7705732a08 100644
--- a/llvm/test/MC/AArch64/SVE/asr.s
+++ b/llvm/test/MC/AArch64/SVE/asr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/asrd.s b/llvm/test/MC/AArch64/SVE/asrd.s
index 78fbbba5b3388..37b3d00303a20 100644
--- a/llvm/test/MC/AArch64/SVE/asrd.s
+++ b/llvm/test/MC/AArch64/SVE/asrd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/asrr.s b/llvm/test/MC/AArch64/SVE/asrr.s
index f9cc7ea6f8ee5..d24a93a1b99be 100644
--- a/llvm/test/MC/AArch64/SVE/asrr.s
+++ b/llvm/test/MC/AArch64/SVE/asrr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/bic.s b/llvm/test/MC/AArch64/SVE/bic.s
index 064e295a9c663..8907ceafead02 100644
--- a/llvm/test/MC/AArch64/SVE/bic.s
+++ b/llvm/test/MC/AArch64/SVE/bic.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/bics.s b/llvm/test/MC/AArch64/SVE/bics.s
index 92447351fa8b4..58259e0711500 100644
--- a/llvm/test/MC/AArch64/SVE/bics.s
+++ b/llvm/test/MC/AArch64/SVE/bics.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brka.s b/llvm/test/MC/AArch64/SVE/brka.s
index d87e7632e3fd7..7797de72b2aef 100644
--- a/llvm/test/MC/AArch64/SVE/brka.s
+++ b/llvm/test/MC/AArch64/SVE/brka.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkas.s b/llvm/test/MC/AArch64/SVE/brkas.s
index f75c5bc8069dc..7edf359795173 100644
--- a/llvm/test/MC/AArch64/SVE/brkas.s
+++ b/llvm/test/MC/AArch64/SVE/brkas.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkb.s b/llvm/test/MC/AArch64/SVE/brkb.s
index 393d29449588c..70a071610e3f4 100644
--- a/llvm/test/MC/AArch64/SVE/brkb.s
+++ b/llvm/test/MC/AArch64/SVE/brkb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkbs.s b/llvm/test/MC/AArch64/SVE/brkbs.s
index 708ec91345c34..47ec49b4739af 100644
--- a/llvm/test/MC/AArch64/SVE/brkbs.s
+++ b/llvm/test/MC/AArch64/SVE/brkbs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkn.s b/llvm/test/MC/AArch64/SVE/brkn.s
index 8494e547732fe..2757bf61aa9af 100644
--- a/llvm/test/MC/AArch64/SVE/brkn.s
+++ b/llvm/test/MC/AArch64/SVE/brkn.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkns.s b/llvm/test/MC/AArch64/SVE/brkns.s
index 6fd47f69c91fc..0ccae4d621895 100644
--- a/llvm/test/MC/AArch64/SVE/brkns.s
+++ b/llvm/test/MC/AArch64/SVE/brkns.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkpa.s b/llvm/test/MC/AArch64/SVE/brkpa.s
index c283ee2fdea66..b0c62f48ded43 100644
--- a/llvm/test/MC/AArch64/SVE/brkpa.s
+++ b/llvm/test/MC/AArch64/SVE/brkpa.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkpas.s b/llvm/test/MC/AArch64/SVE/brkpas.s
index 81d5900966815..2d54e95312b09 100644
--- a/llvm/test/MC/AArch64/SVE/brkpas.s
+++ b/llvm/test/MC/AArch64/SVE/brkpas.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkpb.s b/llvm/test/MC/AArch64/SVE/brkpb.s
index 039e71f5e3221..d55fb3a6805fb 100644
--- a/llvm/test/MC/AArch64/SVE/brkpb.s
+++ b/llvm/test/MC/AArch64/SVE/brkpb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/brkpbs.s b/llvm/test/MC/AArch64/SVE/brkpbs.s
index 1d44178659dd3..76798e92c8ddd 100644
--- a/llvm/test/MC/AArch64/SVE/brkpbs.s
+++ b/llvm/test/MC/AArch64/SVE/brkpbs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/clasta.s b/llvm/test/MC/AArch64/SVE/clasta.s
index 05f6f92afac98..3e752b0d5842f 100644
--- a/llvm/test/MC/AArch64/SVE/clasta.s
+++ b/llvm/test/MC/AArch64/SVE/clasta.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/clastb.s b/llvm/test/MC/AArch64/SVE/clastb.s
index 6785edb87ceed..c1ff87741af33 100644
--- a/llvm/test/MC/AArch64/SVE/clastb.s
+++ b/llvm/test/MC/AArch64/SVE/clastb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cls.s b/llvm/test/MC/AArch64/SVE/cls.s
index e860a7b404013..db6a68b179005 100644
--- a/llvm/test/MC/AArch64/SVE/cls.s
+++ b/llvm/test/MC/AArch64/SVE/cls.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/clz.s b/llvm/test/MC/AArch64/SVE/clz.s
index ff69f383e70c7..1eb457b550cf1 100644
--- a/llvm/test/MC/AArch64/SVE/clz.s
+++ b/llvm/test/MC/AArch64/SVE/clz.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmpeq.s b/llvm/test/MC/AArch64/SVE/cmpeq.s
index a654043413462..7d462ecaf9461 100644
--- a/llvm/test/MC/AArch64/SVE/cmpeq.s
+++ b/llvm/test/MC/AArch64/SVE/cmpeq.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmpge.s b/llvm/test/MC/AArch64/SVE/cmpge.s
index db670b27fb3a3..78a5fda33a5a6 100644
--- a/llvm/test/MC/AArch64/SVE/cmpge.s
+++ b/llvm/test/MC/AArch64/SVE/cmpge.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmpgt.s b/llvm/test/MC/AArch64/SVE/cmpgt.s
index fa0389fbc548d..986d10880bb53 100644
--- a/llvm/test/MC/AArch64/SVE/cmpgt.s
+++ b/llvm/test/MC/AArch64/SVE/cmpgt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmphi.s b/llvm/test/MC/AArch64/SVE/cmphi.s
index aabb8da9dac68..96c27206b82b6 100644
--- a/llvm/test/MC/AArch64/SVE/cmphi.s
+++ b/llvm/test/MC/AArch64/SVE/cmphi.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmphs.s b/llvm/test/MC/AArch64/SVE/cmphs.s
index f0712c1e153f8..c68e3f29d0deb 100644
--- a/llvm/test/MC/AArch64/SVE/cmphs.s
+++ b/llvm/test/MC/AArch64/SVE/cmphs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmple.s b/llvm/test/MC/AArch64/SVE/cmple.s
index 23f399b9a69bf..db27650eeeab0 100644
--- a/llvm/test/MC/AArch64/SVE/cmple.s
+++ b/llvm/test/MC/AArch64/SVE/cmple.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmplo.s b/llvm/test/MC/AArch64/SVE/cmplo.s
index 72d165203f194..34adf32511c38 100644
--- a/llvm/test/MC/AArch64/SVE/cmplo.s
+++ b/llvm/test/MC/AArch64/SVE/cmplo.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmpls.s b/llvm/test/MC/AArch64/SVE/cmpls.s
index be713ee5febb0..9fef6ba2598b2 100644
--- a/llvm/test/MC/AArch64/SVE/cmpls.s
+++ b/llvm/test/MC/AArch64/SVE/cmpls.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmplt.s b/llvm/test/MC/AArch64/SVE/cmplt.s
index c7225066a3486..8ccb5390221e5 100644
--- a/llvm/test/MC/AArch64/SVE/cmplt.s
+++ b/llvm/test/MC/AArch64/SVE/cmplt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cmpne.s b/llvm/test/MC/AArch64/SVE/cmpne.s
index 0dc87cc25cf1c..54641b34bfa1f 100644
--- a/llvm/test/MC/AArch64/SVE/cmpne.s
+++ b/llvm/test/MC/AArch64/SVE/cmpne.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cnot.s b/llvm/test/MC/AArch64/SVE/cnot.s
index 83f21816c8594..dca6db87d9d0b 100644
--- a/llvm/test/MC/AArch64/SVE/cnot.s
+++ b/llvm/test/MC/AArch64/SVE/cnot.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cnt.s b/llvm/test/MC/AArch64/SVE/cnt.s
index 86373cbe08e34..354ca3a0c2d3a 100644
--- a/llvm/test/MC/AArch64/SVE/cnt.s
+++ b/llvm/test/MC/AArch64/SVE/cnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cntb.s b/llvm/test/MC/AArch64/SVE/cntb.s
index c5539caa50d12..d7a142fa6aa28 100644
--- a/llvm/test/MC/AArch64/SVE/cntb.s
+++ b/llvm/test/MC/AArch64/SVE/cntb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cntd.s b/llvm/test/MC/AArch64/SVE/cntd.s
index 31fc96878e399..27fc87e29a271 100644
--- a/llvm/test/MC/AArch64/SVE/cntd.s
+++ b/llvm/test/MC/AArch64/SVE/cntd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cnth.s b/llvm/test/MC/AArch64/SVE/cnth.s
index 404f83587a0f4..81e2e8c778804 100644
--- a/llvm/test/MC/AArch64/SVE/cnth.s
+++ b/llvm/test/MC/AArch64/SVE/cnth.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cntp.s b/llvm/test/MC/AArch64/SVE/cntp.s
index ec96928ad500d..dcc4744106ff7 100644
--- a/llvm/test/MC/AArch64/SVE/cntp.s
+++ b/llvm/test/MC/AArch64/SVE/cntp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cntw.s b/llvm/test/MC/AArch64/SVE/cntw.s
index 0f4a53ed6fbf1..ba7a79ddaaaf0 100644
--- a/llvm/test/MC/AArch64/SVE/cntw.s
+++ b/llvm/test/MC/AArch64/SVE/cntw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/compact.s b/llvm/test/MC/AArch64/SVE/compact.s
index 9c0f0a024b995..318882b82463b 100644
--- a/llvm/test/MC/AArch64/SVE/compact.s
+++ b/llvm/test/MC/AArch64/SVE/compact.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/cpy.s b/llvm/test/MC/AArch64/SVE/cpy.s
index 968bc5ddfe8d7..d3fabef943a27 100644
--- a/llvm/test/MC/AArch64/SVE/cpy.s
+++ b/llvm/test/MC/AArch64/SVE/cpy.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ctermeq.s b/llvm/test/MC/AArch64/SVE/ctermeq.s
index 3dfac002350ae..22db85eb14801 100644
--- a/llvm/test/MC/AArch64/SVE/ctermeq.s
+++ b/llvm/test/MC/AArch64/SVE/ctermeq.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ctermne.s b/llvm/test/MC/AArch64/SVE/ctermne.s
index 54dc5e23a9c50..8abc859901e35 100644
--- a/llvm/test/MC/AArch64/SVE/ctermne.s
+++ b/llvm/test/MC/AArch64/SVE/ctermne.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/decb.s b/llvm/test/MC/AArch64/SVE/decb.s
index d96380aa49e64..c2236cc8066a4 100644
--- a/llvm/test/MC/AArch64/SVE/decb.s
+++ b/llvm/test/MC/AArch64/SVE/decb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/decd.s b/llvm/test/MC/AArch64/SVE/decd.s
index 6d3b5f54aa80e..0680c8fd9460e 100644
--- a/llvm/test/MC/AArch64/SVE/decd.s
+++ b/llvm/test/MC/AArch64/SVE/decd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/dech.s b/llvm/test/MC/AArch64/SVE/dech.s
index 83ec024b7ccc8..7e5ddcf2b3087 100644
--- a/llvm/test/MC/AArch64/SVE/dech.s
+++ b/llvm/test/MC/AArch64/SVE/dech.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/decp.s b/llvm/test/MC/AArch64/SVE/decp.s
index 6cf73033e69ea..a9b9347874c4e 100644
--- a/llvm/test/MC/AArch64/SVE/decp.s
+++ b/llvm/test/MC/AArch64/SVE/decp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/decw.s b/llvm/test/MC/AArch64/SVE/decw.s
index 00d367178cc12..c9292c07322d2 100644
--- a/llvm/test/MC/AArch64/SVE/decw.s
+++ b/llvm/test/MC/AArch64/SVE/decw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/dup.s b/llvm/test/MC/AArch64/SVE/dup.s
index b55aeeb7eafb8..73e304eb331c2 100644
--- a/llvm/test/MC/AArch64/SVE/dup.s
+++ b/llvm/test/MC/AArch64/SVE/dup.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/dupm.s b/llvm/test/MC/AArch64/SVE/dupm.s
index 9bfa53a572977..0b6e51e8942e2 100644
--- a/llvm/test/MC/AArch64/SVE/dupm.s
+++ b/llvm/test/MC/AArch64/SVE/dupm.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/eon.s b/llvm/test/MC/AArch64/SVE/eon.s
index d03755d5a94e4..f8c99f243b0d5 100644
--- a/llvm/test/MC/AArch64/SVE/eon.s
+++ b/llvm/test/MC/AArch64/SVE/eon.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/eor.s b/llvm/test/MC/AArch64/SVE/eor.s
index e2c41ce5fed7d..adae11fe982f8 100644
--- a/llvm/test/MC/AArch64/SVE/eor.s
+++ b/llvm/test/MC/AArch64/SVE/eor.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/eors.s b/llvm/test/MC/AArch64/SVE/eors.s
index 9643cb4a06d34..b99140f9fecca 100644
--- a/llvm/test/MC/AArch64/SVE/eors.s
+++ b/llvm/test/MC/AArch64/SVE/eors.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/eorv.s b/llvm/test/MC/AArch64/SVE/eorv.s
index 3b65447bdff97..0e32cd6cbb609 100644
--- a/llvm/test/MC/AArch64/SVE/eorv.s
+++ b/llvm/test/MC/AArch64/SVE/eorv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ext.s b/llvm/test/MC/AArch64/SVE/ext.s
index 632f61eb107c5..3c428f1311c9a 100644
--- a/llvm/test/MC/AArch64/SVE/ext.s
+++ b/llvm/test/MC/AArch64/SVE/ext.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fabd.s b/llvm/test/MC/AArch64/SVE/fabd.s
index 7549f554a95fb..a54d128b9468b 100644
--- a/llvm/test/MC/AArch64/SVE/fabd.s
+++ b/llvm/test/MC/AArch64/SVE/fabd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fabs.s b/llvm/test/MC/AArch64/SVE/fabs.s
index 1bd2c833d1cd7..f48539f8bbc7a 100644
--- a/llvm/test/MC/AArch64/SVE/fabs.s
+++ b/llvm/test/MC/AArch64/SVE/fabs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/facge.s b/llvm/test/MC/AArch64/SVE/facge.s
index 194bc78fda169..e034375eb9811 100644
--- a/llvm/test/MC/AArch64/SVE/facge.s
+++ b/llvm/test/MC/AArch64/SVE/facge.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/facgt.s b/llvm/test/MC/AArch64/SVE/facgt.s
index e47812c67fe18..6f3fd9ea686ac 100644
--- a/llvm/test/MC/AArch64/SVE/facgt.s
+++ b/llvm/test/MC/AArch64/SVE/facgt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/facle.s b/llvm/test/MC/AArch64/SVE/facle.s
index a56ea9f062240..cb564e1025f24 100644
--- a/llvm/test/MC/AArch64/SVE/facle.s
+++ b/llvm/test/MC/AArch64/SVE/facle.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/faclt.s b/llvm/test/MC/AArch64/SVE/faclt.s
index b38ce25c6c045..1d48f5db7cc33 100644
--- a/llvm/test/MC/AArch64/SVE/faclt.s
+++ b/llvm/test/MC/AArch64/SVE/faclt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fadd.s b/llvm/test/MC/AArch64/SVE/fadd.s
index 10935c37fc058..979cbad3a8751 100644
--- a/llvm/test/MC/AArch64/SVE/fadd.s
+++ b/llvm/test/MC/AArch64/SVE/fadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fadda.s b/llvm/test/MC/AArch64/SVE/fadda.s
index 8f99eb020327b..0a4bbcfb690ac 100644
--- a/llvm/test/MC/AArch64/SVE/fadda.s
+++ b/llvm/test/MC/AArch64/SVE/fadda.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/faddv.s b/llvm/test/MC/AArch64/SVE/faddv.s
index a6b01928d3b3b..01d67cf921599 100644
--- a/llvm/test/MC/AArch64/SVE/faddv.s
+++ b/llvm/test/MC/AArch64/SVE/faddv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcadd.s b/llvm/test/MC/AArch64/SVE/fcadd.s
index 9d2398ab25a87..1ed89d64e9347 100644
--- a/llvm/test/MC/AArch64/SVE/fcadd.s
+++ b/llvm/test/MC/AArch64/SVE/fcadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmeq.s b/llvm/test/MC/AArch64/SVE/fcmeq.s
index 5b75f6494d40b..fa889dd7d864b 100644
--- a/llvm/test/MC/AArch64/SVE/fcmeq.s
+++ b/llvm/test/MC/AArch64/SVE/fcmeq.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmge.s b/llvm/test/MC/AArch64/SVE/fcmge.s
index 163b5d6275b3a..aa963c6905c5b 100644
--- a/llvm/test/MC/AArch64/SVE/fcmge.s
+++ b/llvm/test/MC/AArch64/SVE/fcmge.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmgt.s b/llvm/test/MC/AArch64/SVE/fcmgt.s
index edc7b7a57d9dd..bac648c3c8835 100644
--- a/llvm/test/MC/AArch64/SVE/fcmgt.s
+++ b/llvm/test/MC/AArch64/SVE/fcmgt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmla.s b/llvm/test/MC/AArch64/SVE/fcmla.s
index 2e4dd7f55357c..554e33c9d0e10 100644
--- a/llvm/test/MC/AArch64/SVE/fcmla.s
+++ b/llvm/test/MC/AArch64/SVE/fcmla.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmle.s b/llvm/test/MC/AArch64/SVE/fcmle.s
index eec273fab5c3b..74f9985342136 100644
--- a/llvm/test/MC/AArch64/SVE/fcmle.s
+++ b/llvm/test/MC/AArch64/SVE/fcmle.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmlt.s b/llvm/test/MC/AArch64/SVE/fcmlt.s
index aa0bb7d551cf2..475f7294a3ceb 100644
--- a/llvm/test/MC/AArch64/SVE/fcmlt.s
+++ b/llvm/test/MC/AArch64/SVE/fcmlt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmne.s b/llvm/test/MC/AArch64/SVE/fcmne.s
index 3420e67e60844..7ee8d3a13f8a8 100644
--- a/llvm/test/MC/AArch64/SVE/fcmne.s
+++ b/llvm/test/MC/AArch64/SVE/fcmne.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcmuo.s b/llvm/test/MC/AArch64/SVE/fcmuo.s
index 194da77c08887..5bceb0ebace3f 100644
--- a/llvm/test/MC/AArch64/SVE/fcmuo.s
+++ b/llvm/test/MC/AArch64/SVE/fcmuo.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcpy.s b/llvm/test/MC/AArch64/SVE/fcpy.s
index 5510e035dd1d3..3b3a3a42e0657 100644
--- a/llvm/test/MC/AArch64/SVE/fcpy.s
+++ b/llvm/test/MC/AArch64/SVE/fcpy.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcvt.s b/llvm/test/MC/AArch64/SVE/fcvt.s
index 3a0d524711862..9a9961848ceb1 100644
--- a/llvm/test/MC/AArch64/SVE/fcvt.s
+++ b/llvm/test/MC/AArch64/SVE/fcvt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcvtzs.s b/llvm/test/MC/AArch64/SVE/fcvtzs.s
index ecb7adc46b849..a0c8eba7b487c 100644
--- a/llvm/test/MC/AArch64/SVE/fcvtzs.s
+++ b/llvm/test/MC/AArch64/SVE/fcvtzs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fcvtzu.s b/llvm/test/MC/AArch64/SVE/fcvtzu.s
index cd6993c0f5891..8d5a19cbf2db5 100644
--- a/llvm/test/MC/AArch64/SVE/fcvtzu.s
+++ b/llvm/test/MC/AArch64/SVE/fcvtzu.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fdiv.s b/llvm/test/MC/AArch64/SVE/fdiv.s
index 9f1d4ddf1b77e..5da6740cce717 100644
--- a/llvm/test/MC/AArch64/SVE/fdiv.s
+++ b/llvm/test/MC/AArch64/SVE/fdiv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fdivr.s b/llvm/test/MC/AArch64/SVE/fdivr.s
index 37fd871461e36..3a2d8c6d5b1ed 100644
--- a/llvm/test/MC/AArch64/SVE/fdivr.s
+++ b/llvm/test/MC/AArch64/SVE/fdivr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fdup.s b/llvm/test/MC/AArch64/SVE/fdup.s
index b82a06c31e922..87efc5f4e0dbf 100644
--- a/llvm/test/MC/AArch64/SVE/fdup.s
+++ b/llvm/test/MC/AArch64/SVE/fdup.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fexpa.s b/llvm/test/MC/AArch64/SVE/fexpa.s
index 503af1ef80aa9..7cfd3cd115b62 100644
--- a/llvm/test/MC/AArch64/SVE/fexpa.s
+++ b/llvm/test/MC/AArch64/SVE/fexpa.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmad.s b/llvm/test/MC/AArch64/SVE/fmad.s
index 2cfb6a74156cb..002010c3c857f 100644
--- a/llvm/test/MC/AArch64/SVE/fmad.s
+++ b/llvm/test/MC/AArch64/SVE/fmad.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmax.s b/llvm/test/MC/AArch64/SVE/fmax.s
index bcdc904039492..de22ec10de7fc 100644
--- a/llvm/test/MC/AArch64/SVE/fmax.s
+++ b/llvm/test/MC/AArch64/SVE/fmax.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmaxnm.s b/llvm/test/MC/AArch64/SVE/fmaxnm.s
index 5c44861ea9542..d630173cb3037 100644
--- a/llvm/test/MC/AArch64/SVE/fmaxnm.s
+++ b/llvm/test/MC/AArch64/SVE/fmaxnm.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmaxnmv.s b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
index 0f18ae486a7cd..ce81d0db6a8d9 100644
--- a/llvm/test/MC/AArch64/SVE/fmaxnmv.s
+++ b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmaxv.s b/llvm/test/MC/AArch64/SVE/fmaxv.s
index cd12d266b4afb..ea2c1064d1fa5 100644
--- a/llvm/test/MC/AArch64/SVE/fmaxv.s
+++ b/llvm/test/MC/AArch64/SVE/fmaxv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmin.s b/llvm/test/MC/AArch64/SVE/fmin.s
index 1b0cb4e589c39..2c7953f3f7585 100644
--- a/llvm/test/MC/AArch64/SVE/fmin.s
+++ b/llvm/test/MC/AArch64/SVE/fmin.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fminnm.s b/llvm/test/MC/AArch64/SVE/fminnm.s
index 482b7f561ef26..c30187975e574 100644
--- a/llvm/test/MC/AArch64/SVE/fminnm.s
+++ b/llvm/test/MC/AArch64/SVE/fminnm.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fminnmv.s b/llvm/test/MC/AArch64/SVE/fminnmv.s
index 7391b3565fbc7..e2ab1bea13cd4 100644
--- a/llvm/test/MC/AArch64/SVE/fminnmv.s
+++ b/llvm/test/MC/AArch64/SVE/fminnmv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fminv.s b/llvm/test/MC/AArch64/SVE/fminv.s
index 9b310049dedde..e3a0c2859a9b4 100644
--- a/llvm/test/MC/AArch64/SVE/fminv.s
+++ b/llvm/test/MC/AArch64/SVE/fminv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmla.s b/llvm/test/MC/AArch64/SVE/fmla.s
index a28204da0a146..62e3f600c4a26 100644
--- a/llvm/test/MC/AArch64/SVE/fmla.s
+++ b/llvm/test/MC/AArch64/SVE/fmla.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmls.s b/llvm/test/MC/AArch64/SVE/fmls.s
index 390a3128fc44f..7d6b32eca19c5 100644
--- a/llvm/test/MC/AArch64/SVE/fmls.s
+++ b/llvm/test/MC/AArch64/SVE/fmls.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmov.s b/llvm/test/MC/AArch64/SVE/fmov.s
index abd1044bc1630..37746de53fb46 100644
--- a/llvm/test/MC/AArch64/SVE/fmov.s
+++ b/llvm/test/MC/AArch64/SVE/fmov.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmsb.s b/llvm/test/MC/AArch64/SVE/fmsb.s
index c1203e2f1f386..cb6ffaa1e6ab9 100644
--- a/llvm/test/MC/AArch64/SVE/fmsb.s
+++ b/llvm/test/MC/AArch64/SVE/fmsb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmul.s b/llvm/test/MC/AArch64/SVE/fmul.s
index 3cf35f33f8ca5..89da873372774 100644
--- a/llvm/test/MC/AArch64/SVE/fmul.s
+++ b/llvm/test/MC/AArch64/SVE/fmul.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fmulx.s b/llvm/test/MC/AArch64/SVE/fmulx.s
index 0c49421fddbc0..3c2413b014436 100644
--- a/llvm/test/MC/AArch64/SVE/fmulx.s
+++ b/llvm/test/MC/AArch64/SVE/fmulx.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fneg.s b/llvm/test/MC/AArch64/SVE/fneg.s
index 47f833e9b81c3..7a73e73281c9b 100644
--- a/llvm/test/MC/AArch64/SVE/fneg.s
+++ b/llvm/test/MC/AArch64/SVE/fneg.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fnmad.s b/llvm/test/MC/AArch64/SVE/fnmad.s
index 3bec7b6be8842..a4fb7d0b52b3a 100644
--- a/llvm/test/MC/AArch64/SVE/fnmad.s
+++ b/llvm/test/MC/AArch64/SVE/fnmad.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fnmla.s b/llvm/test/MC/AArch64/SVE/fnmla.s
index aa3eb3be9195f..afad12725e18d 100644
--- a/llvm/test/MC/AArch64/SVE/fnmla.s
+++ b/llvm/test/MC/AArch64/SVE/fnmla.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fnmls.s b/llvm/test/MC/AArch64/SVE/fnmls.s
index 90bde2edc4ce8..d8cd19fa87e18 100644
--- a/llvm/test/MC/AArch64/SVE/fnmls.s
+++ b/llvm/test/MC/AArch64/SVE/fnmls.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fnmsb.s b/llvm/test/MC/AArch64/SVE/fnmsb.s
index a1767c4091cf9..ca805f3f1e4af 100644
--- a/llvm/test/MC/AArch64/SVE/fnmsb.s
+++ b/llvm/test/MC/AArch64/SVE/fnmsb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frecpe.s b/llvm/test/MC/AArch64/SVE/frecpe.s
index 3b559d951f679..afc60b50150e4 100644
--- a/llvm/test/MC/AArch64/SVE/frecpe.s
+++ b/llvm/test/MC/AArch64/SVE/frecpe.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frecps.s b/llvm/test/MC/AArch64/SVE/frecps.s
index 442cbd8f32502..258b65334ceea 100644
--- a/llvm/test/MC/AArch64/SVE/frecps.s
+++ b/llvm/test/MC/AArch64/SVE/frecps.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frecpx.s b/llvm/test/MC/AArch64/SVE/frecpx.s
index a044703ab714b..24175913c2e59 100644
--- a/llvm/test/MC/AArch64/SVE/frecpx.s
+++ b/llvm/test/MC/AArch64/SVE/frecpx.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frinta.s b/llvm/test/MC/AArch64/SVE/frinta.s
index c89e1618ae7b0..539c782a78a02 100644
--- a/llvm/test/MC/AArch64/SVE/frinta.s
+++ b/llvm/test/MC/AArch64/SVE/frinta.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frinti.s b/llvm/test/MC/AArch64/SVE/frinti.s
index a05cc9fe7b462..5a997b5899742 100644
--- a/llvm/test/MC/AArch64/SVE/frinti.s
+++ b/llvm/test/MC/AArch64/SVE/frinti.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frintm.s b/llvm/test/MC/AArch64/SVE/frintm.s
index e085683f9d177..dc8f98f2e9f82 100644
--- a/llvm/test/MC/AArch64/SVE/frintm.s
+++ b/llvm/test/MC/AArch64/SVE/frintm.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frintn.s b/llvm/test/MC/AArch64/SVE/frintn.s
index 1318c8b88318c..e3f4863246185 100644
--- a/llvm/test/MC/AArch64/SVE/frintn.s
+++ b/llvm/test/MC/AArch64/SVE/frintn.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frintp.s b/llvm/test/MC/AArch64/SVE/frintp.s
index a36831ecc2ddf..384580f105a33 100644
--- a/llvm/test/MC/AArch64/SVE/frintp.s
+++ b/llvm/test/MC/AArch64/SVE/frintp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frintx.s b/llvm/test/MC/AArch64/SVE/frintx.s
index 60244a9cb334f..b7968f67bd868 100644
--- a/llvm/test/MC/AArch64/SVE/frintx.s
+++ b/llvm/test/MC/AArch64/SVE/frintx.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frintz.s b/llvm/test/MC/AArch64/SVE/frintz.s
index af794b79a2f2a..2499f34f667da 100644
--- a/llvm/test/MC/AArch64/SVE/frintz.s
+++ b/llvm/test/MC/AArch64/SVE/frintz.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frsqrte.s b/llvm/test/MC/AArch64/SVE/frsqrte.s
index e0fa387b665a8..0fd3da1aa966f 100644
--- a/llvm/test/MC/AArch64/SVE/frsqrte.s
+++ b/llvm/test/MC/AArch64/SVE/frsqrte.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/frsqrts.s b/llvm/test/MC/AArch64/SVE/frsqrts.s
index ac61e882f70ce..230c531e19eca 100644
--- a/llvm/test/MC/AArch64/SVE/frsqrts.s
+++ b/llvm/test/MC/AArch64/SVE/frsqrts.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fscale.s b/llvm/test/MC/AArch64/SVE/fscale.s
index ab928b4c77f1e..4d19be7f7b3cb 100644
--- a/llvm/test/MC/AArch64/SVE/fscale.s
+++ b/llvm/test/MC/AArch64/SVE/fscale.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fsqrt.s b/llvm/test/MC/AArch64/SVE/fsqrt.s
index b72d2438b33f1..98e2ff55e7869 100644
--- a/llvm/test/MC/AArch64/SVE/fsqrt.s
+++ b/llvm/test/MC/AArch64/SVE/fsqrt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fsub.s b/llvm/test/MC/AArch64/SVE/fsub.s
index 49d7448e85746..d891d75da7c86 100644
--- a/llvm/test/MC/AArch64/SVE/fsub.s
+++ b/llvm/test/MC/AArch64/SVE/fsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/fsubr.s b/llvm/test/MC/AArch64/SVE/fsubr.s
index 349871702498d..3bcceabb88740 100644
--- a/llvm/test/MC/AArch64/SVE/fsubr.s
+++ b/llvm/test/MC/AArch64/SVE/fsubr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ftmad.s b/llvm/test/MC/AArch64/SVE/ftmad.s
index 3a59a1fb4fd7e..d5b44de595543 100644
--- a/llvm/test/MC/AArch64/SVE/ftmad.s
+++ b/llvm/test/MC/AArch64/SVE/ftmad.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ftsmul.s b/llvm/test/MC/AArch64/SVE/ftsmul.s
index 1b41fca7c2b77..c0ba4d7cb291c 100644
--- a/llvm/test/MC/AArch64/SVE/ftsmul.s
+++ b/llvm/test/MC/AArch64/SVE/ftsmul.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ftssel.s b/llvm/test/MC/AArch64/SVE/ftssel.s
index 3e9ec71a55427..db59001d66109 100644
--- a/llvm/test/MC/AArch64/SVE/ftssel.s
+++ b/llvm/test/MC/AArch64/SVE/ftssel.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/incb.s b/llvm/test/MC/AArch64/SVE/incb.s
index d28e0aec45804..f2397d854c6c3 100644
--- a/llvm/test/MC/AArch64/SVE/incb.s
+++ b/llvm/test/MC/AArch64/SVE/incb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/incd.s b/llvm/test/MC/AArch64/SVE/incd.s
index 9774c450ed12a..84ac45b39effd 100644
--- a/llvm/test/MC/AArch64/SVE/incd.s
+++ b/llvm/test/MC/AArch64/SVE/incd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/inch.s b/llvm/test/MC/AArch64/SVE/inch.s
index fd952cd7d3dbe..76edf37e2b54c 100644
--- a/llvm/test/MC/AArch64/SVE/inch.s
+++ b/llvm/test/MC/AArch64/SVE/inch.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/incp.s b/llvm/test/MC/AArch64/SVE/incp.s
index b180fcc698d28..f6056478f2e29 100644
--- a/llvm/test/MC/AArch64/SVE/incp.s
+++ b/llvm/test/MC/AArch64/SVE/incp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/incw.s b/llvm/test/MC/AArch64/SVE/incw.s
index fb6a05ee6f57a..eb6ec3e3cd16b 100644
--- a/llvm/test/MC/AArch64/SVE/incw.s
+++ b/llvm/test/MC/AArch64/SVE/incw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/index.s b/llvm/test/MC/AArch64/SVE/index.s
index a728e4c3d1c34..f03f4ac0f0f6e 100644
--- a/llvm/test/MC/AArch64/SVE/index.s
+++ b/llvm/test/MC/AArch64/SVE/index.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/insr.s b/llvm/test/MC/AArch64/SVE/insr.s
index 2626113000196..8d77833e95631 100644
--- a/llvm/test/MC/AArch64/SVE/insr.s
+++ b/llvm/test/MC/AArch64/SVE/insr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/lasta.s b/llvm/test/MC/AArch64/SVE/lasta.s
index 7d17ab2a961ae..7e8d962911f54 100644
--- a/llvm/test/MC/AArch64/SVE/lasta.s
+++ b/llvm/test/MC/AArch64/SVE/lasta.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/lastb.s b/llvm/test/MC/AArch64/SVE/lastb.s
index 2589d669678fb..6227f9f41c3fe 100644
--- a/llvm/test/MC/AArch64/SVE/lastb.s
+++ b/llvm/test/MC/AArch64/SVE/lastb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1b.s b/llvm/test/MC/AArch64/SVE/ld1b.s
index 34ac5a887aba2..88103f8367cbd 100644
--- a/llvm/test/MC/AArch64/SVE/ld1b.s
+++ b/llvm/test/MC/AArch64/SVE/ld1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1d.s b/llvm/test/MC/AArch64/SVE/ld1d.s
index 59dce412959d0..692b882ab4ea5 100644
--- a/llvm/test/MC/AArch64/SVE/ld1d.s
+++ b/llvm/test/MC/AArch64/SVE/ld1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1h.s b/llvm/test/MC/AArch64/SVE/ld1h.s
index 41ee04cb79b6f..f2e095efa1e4b 100644
--- a/llvm/test/MC/AArch64/SVE/ld1h.s
+++ b/llvm/test/MC/AArch64/SVE/ld1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rb.s b/llvm/test/MC/AArch64/SVE/ld1rb.s
index 59e01bd09a463..c8a4706aa92a1 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rd.s b/llvm/test/MC/AArch64/SVE/ld1rd.s
index 6d11e909a06ae..2f3707eba01d3 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rd.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rh.s b/llvm/test/MC/AArch64/SVE/ld1rh.s
index c64096d228c53..5e2e15d0e3161 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rqb.s b/llvm/test/MC/AArch64/SVE/ld1rqb.s
index 0ea34dedb0423..655e900e96bb9 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rqd.s b/llvm/test/MC/AArch64/SVE/ld1rqd.s
index ee192ae28ec6b..4fa546bde5772 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqd.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rqh.s b/llvm/test/MC/AArch64/SVE/ld1rqh.s
index 7b8cba791ef2a..2d388b6c98cf2 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rqw.s b/llvm/test/MC/AArch64/SVE/ld1rqw.s
index 6d7388ff9e608..1cf52c1d02a26 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rsb.s b/llvm/test/MC/AArch64/SVE/ld1rsb.s
index 882dce52eafd1..5b86aef4a5a24 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rsb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rsb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rsh.s b/llvm/test/MC/AArch64/SVE/ld1rsh.s
index 78abbb1ee75f8..04c7d4f96e879 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rsh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rsh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rsw.s b/llvm/test/MC/AArch64/SVE/ld1rsw.s
index 4dd344cc146f1..dd3efc6e6ae54 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rsw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rsw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1rw.s b/llvm/test/MC/AArch64/SVE/ld1rw.s
index 5bc87b3bfa9c0..847f8a299785d 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1sb.s b/llvm/test/MC/AArch64/SVE/ld1sb.s
index 7f12189ea0885..d36c04c1d39b2 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1sh.s b/llvm/test/MC/AArch64/SVE/ld1sh.s
index c329724e254de..608c167cf80a5 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1sw.s b/llvm/test/MC/AArch64/SVE/ld1sw.s
index a8b3f18c960b5..f8dd329169bd2 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld1w.s b/llvm/test/MC/AArch64/SVE/ld1w.s
index 720260f41a735..771bc614c04d8 100644
--- a/llvm/test/MC/AArch64/SVE/ld1w.s
+++ b/llvm/test/MC/AArch64/SVE/ld1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld2b.s b/llvm/test/MC/AArch64/SVE/ld2b.s
index d7d5d3ec86c40..5738108e904ef 100644
--- a/llvm/test/MC/AArch64/SVE/ld2b.s
+++ b/llvm/test/MC/AArch64/SVE/ld2b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld2d.s b/llvm/test/MC/AArch64/SVE/ld2d.s
index 6e1d98c649bd9..7970b9a82f4f1 100644
--- a/llvm/test/MC/AArch64/SVE/ld2d.s
+++ b/llvm/test/MC/AArch64/SVE/ld2d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld2h.s b/llvm/test/MC/AArch64/SVE/ld2h.s
index 282b45f477bee..e874e2ba4e511 100644
--- a/llvm/test/MC/AArch64/SVE/ld2h.s
+++ b/llvm/test/MC/AArch64/SVE/ld2h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld2w.s b/llvm/test/MC/AArch64/SVE/ld2w.s
index 38a9da7159042..ab8db06af18c3 100644
--- a/llvm/test/MC/AArch64/SVE/ld2w.s
+++ b/llvm/test/MC/AArch64/SVE/ld2w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld3b.s b/llvm/test/MC/AArch64/SVE/ld3b.s
index 7209ee954050a..1b40cfd48041c 100644
--- a/llvm/test/MC/AArch64/SVE/ld3b.s
+++ b/llvm/test/MC/AArch64/SVE/ld3b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld3d.s b/llvm/test/MC/AArch64/SVE/ld3d.s
index af5db90e0e4e5..3216c161f4c60 100644
--- a/llvm/test/MC/AArch64/SVE/ld3d.s
+++ b/llvm/test/MC/AArch64/SVE/ld3d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld3h.s b/llvm/test/MC/AArch64/SVE/ld3h.s
index 1cefcf304ea3f..3ad0c03587601 100644
--- a/llvm/test/MC/AArch64/SVE/ld3h.s
+++ b/llvm/test/MC/AArch64/SVE/ld3h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld3w.s b/llvm/test/MC/AArch64/SVE/ld3w.s
index 26f54e1130d11..d8cce83ce76b3 100644
--- a/llvm/test/MC/AArch64/SVE/ld3w.s
+++ b/llvm/test/MC/AArch64/SVE/ld3w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld4b.s b/llvm/test/MC/AArch64/SVE/ld4b.s
index b78ca35f431fa..f53d37e96fe97 100644
--- a/llvm/test/MC/AArch64/SVE/ld4b.s
+++ b/llvm/test/MC/AArch64/SVE/ld4b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld4d.s b/llvm/test/MC/AArch64/SVE/ld4d.s
index 6bc5bd21f9b37..28efab13afd15 100644
--- a/llvm/test/MC/AArch64/SVE/ld4d.s
+++ b/llvm/test/MC/AArch64/SVE/ld4d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld4h.s b/llvm/test/MC/AArch64/SVE/ld4h.s
index f4ec9dd5ed2ad..0f10c08172cab 100644
--- a/llvm/test/MC/AArch64/SVE/ld4h.s
+++ b/llvm/test/MC/AArch64/SVE/ld4h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ld4w.s b/llvm/test/MC/AArch64/SVE/ld4w.s
index 9d219d087ff2f..b24ffbbb3dce2 100644
--- a/llvm/test/MC/AArch64/SVE/ld4w.s
+++ b/llvm/test/MC/AArch64/SVE/ld4w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1b.s b/llvm/test/MC/AArch64/SVE/ldff1b.s
index ca1192908c97a..89e5f2296c218 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1d.s b/llvm/test/MC/AArch64/SVE/ldff1d.s
index 4ba710b9050eb..2659d211ba81d 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1h.s b/llvm/test/MC/AArch64/SVE/ldff1h.s
index d4e4ebaa4e8c3..c803d940f7856 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sb.s b/llvm/test/MC/AArch64/SVE/ldff1sb.s
index fbab69927bbef..f81f07e197396 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh.s b/llvm/test/MC/AArch64/SVE/ldff1sh.s
index 3444840334f97..ae47be85bb2a4 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw.s b/llvm/test/MC/AArch64/SVE/ldff1sw.s
index 0ee1b9c01c7ce..993da6f354460 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldff1w.s b/llvm/test/MC/AArch64/SVE/ldff1w.s
index 019974316260b..cb96aab4c3ab2 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1b.s b/llvm/test/MC/AArch64/SVE/ldnf1b.s
index 81870c419af68..c6a9d9c357e41 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1d.s b/llvm/test/MC/AArch64/SVE/ldnf1d.s
index 8fbcec3511328..4264969fc2aba 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1h.s b/llvm/test/MC/AArch64/SVE/ldnf1h.s
index d8ef89a53658c..4c873d9682e2a 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1sb.s b/llvm/test/MC/AArch64/SVE/ldnf1sb.s
index db3e4a51c9218..fed903e3bbaa0 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1sb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1sh.s b/llvm/test/MC/AArch64/SVE/ldnf1sh.s
index 04afcd9be0fb9..42ec6298a4fc8 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1sh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1sw.s b/llvm/test/MC/AArch64/SVE/ldnf1sw.s
index 955fbf7ab413d..0d26c91a2f706 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1sw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnf1w.s b/llvm/test/MC/AArch64/SVE/ldnf1w.s
index 5010cdc3149d9..7964a74258dc1 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnt1b.s b/llvm/test/MC/AArch64/SVE/ldnt1b.s
index 2d92f1fbd9d12..bce8726d7046f 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnt1d.s b/llvm/test/MC/AArch64/SVE/ldnt1d.s
index 379683733fa28..bb2d505964ae2 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnt1h.s b/llvm/test/MC/AArch64/SVE/ldnt1h.s
index 6c5196a418f8f..ad12b815a19e3 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldnt1w.s b/llvm/test/MC/AArch64/SVE/ldnt1w.s
index 01ed05fa05d27..7ed6c5fd1eaa1 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ldr.s b/llvm/test/MC/AArch64/SVE/ldr.s
index 940d8d6e79de5..b08951dfe4a8b 100644
--- a/llvm/test/MC/AArch64/SVE/ldr.s
+++ b/llvm/test/MC/AArch64/SVE/ldr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/lsl.s b/llvm/test/MC/AArch64/SVE/lsl.s
index 38b895b745a6a..d7602a88242dd 100644
--- a/llvm/test/MC/AArch64/SVE/lsl.s
+++ b/llvm/test/MC/AArch64/SVE/lsl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/lslr.s b/llvm/test/MC/AArch64/SVE/lslr.s
index 16e19dec95629..7d69ba6d1f209 100644
--- a/llvm/test/MC/AArch64/SVE/lslr.s
+++ b/llvm/test/MC/AArch64/SVE/lslr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/lsr.s b/llvm/test/MC/AArch64/SVE/lsr.s
index 4813261249301..448c52d5f8cd8 100644
--- a/llvm/test/MC/AArch64/SVE/lsr.s
+++ b/llvm/test/MC/AArch64/SVE/lsr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/lsrr.s b/llvm/test/MC/AArch64/SVE/lsrr.s
index ec87a711dbfa0..fad949429fea3 100644
--- a/llvm/test/MC/AArch64/SVE/lsrr.s
+++ b/llvm/test/MC/AArch64/SVE/lsrr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/mad.s b/llvm/test/MC/AArch64/SVE/mad.s
index b9712d6ef3bb5..cc145d4d96162 100644
--- a/llvm/test/MC/AArch64/SVE/mad.s
+++ b/llvm/test/MC/AArch64/SVE/mad.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/mla.s b/llvm/test/MC/AArch64/SVE/mla.s
index d76ee0996a8ef..910a17691500b 100644
--- a/llvm/test/MC/AArch64/SVE/mla.s
+++ b/llvm/test/MC/AArch64/SVE/mla.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/mls.s b/llvm/test/MC/AArch64/SVE/mls.s
index 32d3d0e2dd8bf..17ed6a7a1b6db 100644
--- a/llvm/test/MC/AArch64/SVE/mls.s
+++ b/llvm/test/MC/AArch64/SVE/mls.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/mov.s b/llvm/test/MC/AArch64/SVE/mov.s
index 5704e50c941a5..0abee5df8f637 100644
--- a/llvm/test/MC/AArch64/SVE/mov.s
+++ b/llvm/test/MC/AArch64/SVE/mov.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/movprfx.s b/llvm/test/MC/AArch64/SVE/movprfx.s
index 8065967ebc3ad..ccd768b5f4a50 100644
--- a/llvm/test/MC/AArch64/SVE/movprfx.s
+++ b/llvm/test/MC/AArch64/SVE/movprfx.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/movs.s b/llvm/test/MC/AArch64/SVE/movs.s
index 9ec0320297df2..c03c975ced685 100644
--- a/llvm/test/MC/AArch64/SVE/movs.s
+++ b/llvm/test/MC/AArch64/SVE/movs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/msb.s b/llvm/test/MC/AArch64/SVE/msb.s
index 94715616db513..3cf884b23213f 100644
--- a/llvm/test/MC/AArch64/SVE/msb.s
+++ b/llvm/test/MC/AArch64/SVE/msb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/mul.s b/llvm/test/MC/AArch64/SVE/mul.s
index d1a1f867847fb..774070a92b3a9 100644
--- a/llvm/test/MC/AArch64/SVE/mul.s
+++ b/llvm/test/MC/AArch64/SVE/mul.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/nand.s b/llvm/test/MC/AArch64/SVE/nand.s
index c730ab488b4ae..f7824d5a6f335 100644
--- a/llvm/test/MC/AArch64/SVE/nand.s
+++ b/llvm/test/MC/AArch64/SVE/nand.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/nands.s b/llvm/test/MC/AArch64/SVE/nands.s
index 01f019ad491b2..427c30c33352f 100644
--- a/llvm/test/MC/AArch64/SVE/nands.s
+++ b/llvm/test/MC/AArch64/SVE/nands.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/neg.s b/llvm/test/MC/AArch64/SVE/neg.s
index 437f0e959b2d9..b7133f1073ce1 100644
--- a/llvm/test/MC/AArch64/SVE/neg.s
+++ b/llvm/test/MC/AArch64/SVE/neg.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/nor.s b/llvm/test/MC/AArch64/SVE/nor.s
index fdd5c53628514..0e44a678d8b35 100644
--- a/llvm/test/MC/AArch64/SVE/nor.s
+++ b/llvm/test/MC/AArch64/SVE/nor.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/nors.s b/llvm/test/MC/AArch64/SVE/nors.s
index 0de7d1b3b9325..b6204f5221d01 100644
--- a/llvm/test/MC/AArch64/SVE/nors.s
+++ b/llvm/test/MC/AArch64/SVE/nors.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/not.s b/llvm/test/MC/AArch64/SVE/not.s
index 35e72bb06ac11..22789491e9913 100644
--- a/llvm/test/MC/AArch64/SVE/not.s
+++ b/llvm/test/MC/AArch64/SVE/not.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/nots.s b/llvm/test/MC/AArch64/SVE/nots.s
index 833ddf9c94cab..0df73cebc9dfd 100644
--- a/llvm/test/MC/AArch64/SVE/nots.s
+++ b/llvm/test/MC/AArch64/SVE/nots.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/orn.s b/llvm/test/MC/AArch64/SVE/orn.s
index 1028414070f0d..6d1aa8e1edf26 100644
--- a/llvm/test/MC/AArch64/SVE/orn.s
+++ b/llvm/test/MC/AArch64/SVE/orn.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/orns.s b/llvm/test/MC/AArch64/SVE/orns.s
index e7b81efd1ed64..61c371c31d32a 100644
--- a/llvm/test/MC/AArch64/SVE/orns.s
+++ b/llvm/test/MC/AArch64/SVE/orns.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/orr.s b/llvm/test/MC/AArch64/SVE/orr.s
index 084587787ba0f..4f98afae6757e 100644
--- a/llvm/test/MC/AArch64/SVE/orr.s
+++ b/llvm/test/MC/AArch64/SVE/orr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/orrs.s b/llvm/test/MC/AArch64/SVE/orrs.s
index 0fda5d422284b..3cd7bfb3baf02 100644
--- a/llvm/test/MC/AArch64/SVE/orrs.s
+++ b/llvm/test/MC/AArch64/SVE/orrs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/orv.s b/llvm/test/MC/AArch64/SVE/orv.s
index 8ae0371ccf9db..5d10dbbff35f2 100644
--- a/llvm/test/MC/AArch64/SVE/orv.s
+++ b/llvm/test/MC/AArch64/SVE/orv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/pfalse.s b/llvm/test/MC/AArch64/SVE/pfalse.s
index b1385d8b863f3..b180f1a6b87c6 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/pfirst.s b/llvm/test/MC/AArch64/SVE/pfirst.s
index 8090bf72a0ef7..68526d4044b81 100644
--- a/llvm/test/MC/AArch64/SVE/pfirst.s
+++ b/llvm/test/MC/AArch64/SVE/pfirst.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/pnext.s b/llvm/test/MC/AArch64/SVE/pnext.s
index 3d788deb05c43..5e323b1034361 100644
--- a/llvm/test/MC/AArch64/SVE/pnext.s
+++ b/llvm/test/MC/AArch64/SVE/pnext.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/prfb.s b/llvm/test/MC/AArch64/SVE/prfb.s
index 4476dfe5940f3..59f4822283e53 100644
--- a/llvm/test/MC/AArch64/SVE/prfb.s
+++ b/llvm/test/MC/AArch64/SVE/prfb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/prfd.s b/llvm/test/MC/AArch64/SVE/prfd.s
index 1fcc3f61e3346..403072a340b91 100644
--- a/llvm/test/MC/AArch64/SVE/prfd.s
+++ b/llvm/test/MC/AArch64/SVE/prfd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/prfh.s b/llvm/test/MC/AArch64/SVE/prfh.s
index b77fdc9267dae..74f90d1fbb3e9 100644
--- a/llvm/test/MC/AArch64/SVE/prfh.s
+++ b/llvm/test/MC/AArch64/SVE/prfh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/prfw.s b/llvm/test/MC/AArch64/SVE/prfw.s
index c03c39fd2d4a6..0932910b18802 100644
--- a/llvm/test/MC/AArch64/SVE/prfw.s
+++ b/llvm/test/MC/AArch64/SVE/prfw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ptest.s b/llvm/test/MC/AArch64/SVE/ptest.s
index 29622c08c92fe..609befe2f5e70 100644
--- a/llvm/test/MC/AArch64/SVE/ptest.s
+++ b/llvm/test/MC/AArch64/SVE/ptest.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ptrue.s b/llvm/test/MC/AArch64/SVE/ptrue.s
index 2ee6c77ba650b..5757e346f271b 100644
--- a/llvm/test/MC/AArch64/SVE/ptrue.s
+++ b/llvm/test/MC/AArch64/SVE/ptrue.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ptrues.s b/llvm/test/MC/AArch64/SVE/ptrues.s
index c19e6628c26d3..3b6e37c66cc44 100644
--- a/llvm/test/MC/AArch64/SVE/ptrues.s
+++ b/llvm/test/MC/AArch64/SVE/ptrues.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/punpkhi.s b/llvm/test/MC/AArch64/SVE/punpkhi.s
index 54cbc4b5115cb..c05104e9aabfb 100644
--- a/llvm/test/MC/AArch64/SVE/punpkhi.s
+++ b/llvm/test/MC/AArch64/SVE/punpkhi.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/punpklo.s b/llvm/test/MC/AArch64/SVE/punpklo.s
index ed0fd25ce72c2..a82e74e550825 100644
--- a/llvm/test/MC/AArch64/SVE/punpklo.s
+++ b/llvm/test/MC/AArch64/SVE/punpklo.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/rbit.s b/llvm/test/MC/AArch64/SVE/rbit.s
index 2acba0ebc4e66..54aae153a56cc 100644
--- a/llvm/test/MC/AArch64/SVE/rbit.s
+++ b/llvm/test/MC/AArch64/SVE/rbit.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/rdffr.s b/llvm/test/MC/AArch64/SVE/rdffr.s
index 3ae4c69f95ffa..c0a2c878987e2 100644
--- a/llvm/test/MC/AArch64/SVE/rdffr.s
+++ b/llvm/test/MC/AArch64/SVE/rdffr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/rdffrs.s b/llvm/test/MC/AArch64/SVE/rdffrs.s
index 9586d84af9499..b9708c73e43d7 100644
--- a/llvm/test/MC/AArch64/SVE/rdffrs.s
+++ b/llvm/test/MC/AArch64/SVE/rdffrs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/rdvl.s b/llvm/test/MC/AArch64/SVE/rdvl.s
index 03ed0b8ab8b10..75959c4ace2ae 100644
--- a/llvm/test/MC/AArch64/SVE/rdvl.s
+++ b/llvm/test/MC/AArch64/SVE/rdvl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/rev.s b/llvm/test/MC/AArch64/SVE/rev.s
index bc68fbbddd4d0..df60a676a0ea0 100644
--- a/llvm/test/MC/AArch64/SVE/rev.s
+++ b/llvm/test/MC/AArch64/SVE/rev.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/revb.s b/llvm/test/MC/AArch64/SVE/revb.s
index 1393160b80d03..27a3114d9aba3 100644
--- a/llvm/test/MC/AArch64/SVE/revb.s
+++ b/llvm/test/MC/AArch64/SVE/revb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/revh.s b/llvm/test/MC/AArch64/SVE/revh.s
index d37b1bdec5301..016eb4ee55676 100644
--- a/llvm/test/MC/AArch64/SVE/revh.s
+++ b/llvm/test/MC/AArch64/SVE/revh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/revw.s b/llvm/test/MC/AArch64/SVE/revw.s
index c2e419fe25425..bf556d84502fa 100644
--- a/llvm/test/MC/AArch64/SVE/revw.s
+++ b/llvm/test/MC/AArch64/SVE/revw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sabd.s b/llvm/test/MC/AArch64/SVE/sabd.s
index 4186ff048299b..1bd3ccaae6f46 100644
--- a/llvm/test/MC/AArch64/SVE/sabd.s
+++ b/llvm/test/MC/AArch64/SVE/sabd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/saddv.s b/llvm/test/MC/AArch64/SVE/saddv.s
index 28a64d7181bbf..613f6ac377e06 100644
--- a/llvm/test/MC/AArch64/SVE/saddv.s
+++ b/llvm/test/MC/AArch64/SVE/saddv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/scvtf.s b/llvm/test/MC/AArch64/SVE/scvtf.s
index 8089e4a0c21f5..c21bac886d804 100644
--- a/llvm/test/MC/AArch64/SVE/scvtf.s
+++ b/llvm/test/MC/AArch64/SVE/scvtf.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sdiv.s b/llvm/test/MC/AArch64/SVE/sdiv.s
index 5b617eb763e56..acbf312f6af31 100644
--- a/llvm/test/MC/AArch64/SVE/sdiv.s
+++ b/llvm/test/MC/AArch64/SVE/sdiv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sdivr.s b/llvm/test/MC/AArch64/SVE/sdivr.s
index b85cecedf30d2..0032bf4df65e5 100644
--- a/llvm/test/MC/AArch64/SVE/sdivr.s
+++ b/llvm/test/MC/AArch64/SVE/sdivr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sdot.s b/llvm/test/MC/AArch64/SVE/sdot.s
index a7d7e7ecb6daa..d61cea6596843 100644
--- a/llvm/test/MC/AArch64/SVE/sdot.s
+++ b/llvm/test/MC/AArch64/SVE/sdot.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sel.s b/llvm/test/MC/AArch64/SVE/sel.s
index 3286d8ee6a62a..b6b18bac5bbc0 100644
--- a/llvm/test/MC/AArch64/SVE/sel.s
+++ b/llvm/test/MC/AArch64/SVE/sel.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/setffr.s b/llvm/test/MC/AArch64/SVE/setffr.s
index 17d5f178f30d3..3a4a693ffd641 100644
--- a/llvm/test/MC/AArch64/SVE/setffr.s
+++ b/llvm/test/MC/AArch64/SVE/setffr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/smax.s b/llvm/test/MC/AArch64/SVE/smax.s
index 1fbcc84110e63..0096cb8804ec5 100644
--- a/llvm/test/MC/AArch64/SVE/smax.s
+++ b/llvm/test/MC/AArch64/SVE/smax.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/smaxv.s b/llvm/test/MC/AArch64/SVE/smaxv.s
index bb0b62783a7da..74c5802e523ce 100644
--- a/llvm/test/MC/AArch64/SVE/smaxv.s
+++ b/llvm/test/MC/AArch64/SVE/smaxv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/smin.s b/llvm/test/MC/AArch64/SVE/smin.s
index da26ac04462f6..48caec1a1db71 100644
--- a/llvm/test/MC/AArch64/SVE/smin.s
+++ b/llvm/test/MC/AArch64/SVE/smin.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sminv.s b/llvm/test/MC/AArch64/SVE/sminv.s
index 6490813fdecf1..fb21394c1fef3 100644
--- a/llvm/test/MC/AArch64/SVE/sminv.s
+++ b/llvm/test/MC/AArch64/SVE/sminv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/smulh.s b/llvm/test/MC/AArch64/SVE/smulh.s
index 7ef8d80dc7862..6bf6c97db6742 100644
--- a/llvm/test/MC/AArch64/SVE/smulh.s
+++ b/llvm/test/MC/AArch64/SVE/smulh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/splice.s b/llvm/test/MC/AArch64/SVE/splice.s
index 719a761f30228..97a0f36daff9d 100644
--- a/llvm/test/MC/AArch64/SVE/splice.s
+++ b/llvm/test/MC/AArch64/SVE/splice.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqadd.s b/llvm/test/MC/AArch64/SVE/sqadd.s
index 8f722ea1da488..cef3508fe7b4e 100644
--- a/llvm/test/MC/AArch64/SVE/sqadd.s
+++ b/llvm/test/MC/AArch64/SVE/sqadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdecb.s b/llvm/test/MC/AArch64/SVE/sqdecb.s
index 570c3331e07ee..d09fb40ba930d 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecb.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdecd.s b/llvm/test/MC/AArch64/SVE/sqdecd.s
index 107d630cb3e44..a9b300f05d4c8 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecd.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdech.s b/llvm/test/MC/AArch64/SVE/sqdech.s
index 574316825b182..0006d1a13103a 100644
--- a/llvm/test/MC/AArch64/SVE/sqdech.s
+++ b/llvm/test/MC/AArch64/SVE/sqdech.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdecp.s b/llvm/test/MC/AArch64/SVE/sqdecp.s
index 7da00beb7b24a..e2fe21957716a 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecp.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdecw.s b/llvm/test/MC/AArch64/SVE/sqdecw.s
index e48d5999d409e..9a3510d895af8 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecw.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincb.s b/llvm/test/MC/AArch64/SVE/sqincb.s
index 8a3d3566b0ab9..89a05da2563ba 100644
--- a/llvm/test/MC/AArch64/SVE/sqincb.s
+++ b/llvm/test/MC/AArch64/SVE/sqincb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincd.s b/llvm/test/MC/AArch64/SVE/sqincd.s
index 440e4b708ffca..2071589cb615f 100644
--- a/llvm/test/MC/AArch64/SVE/sqincd.s
+++ b/llvm/test/MC/AArch64/SVE/sqincd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqinch.s b/llvm/test/MC/AArch64/SVE/sqinch.s
index 6ed6dc4758e03..3d0ad285fb948 100644
--- a/llvm/test/MC/AArch64/SVE/sqinch.s
+++ b/llvm/test/MC/AArch64/SVE/sqinch.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincp.s b/llvm/test/MC/AArch64/SVE/sqincp.s
index e523796a39f12..256dc5fbf34ff 100644
--- a/llvm/test/MC/AArch64/SVE/sqincp.s
+++ b/llvm/test/MC/AArch64/SVE/sqincp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincw.s b/llvm/test/MC/AArch64/SVE/sqincw.s
index 7ff2bc6540a7c..89ef557f65d4c 100644
--- a/llvm/test/MC/AArch64/SVE/sqincw.s
+++ b/llvm/test/MC/AArch64/SVE/sqincw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sqsub.s b/llvm/test/MC/AArch64/SVE/sqsub.s
index c91d5fe3d1244..0616374a37592 100644
--- a/llvm/test/MC/AArch64/SVE/sqsub.s
+++ b/llvm/test/MC/AArch64/SVE/sqsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st1b.s b/llvm/test/MC/AArch64/SVE/st1b.s
index 62961c7ea2133..a6f766bdfd7cc 100644
--- a/llvm/test/MC/AArch64/SVE/st1b.s
+++ b/llvm/test/MC/AArch64/SVE/st1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st1d.s b/llvm/test/MC/AArch64/SVE/st1d.s
index 51d11d8be65d0..ba4a0e5be114b 100644
--- a/llvm/test/MC/AArch64/SVE/st1d.s
+++ b/llvm/test/MC/AArch64/SVE/st1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st1h.s b/llvm/test/MC/AArch64/SVE/st1h.s
index c44d8e25e6a48..cd6c20d83482e 100644
--- a/llvm/test/MC/AArch64/SVE/st1h.s
+++ b/llvm/test/MC/AArch64/SVE/st1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st1w.s b/llvm/test/MC/AArch64/SVE/st1w.s
index 8d37a08257028..e20194f5747e9 100644
--- a/llvm/test/MC/AArch64/SVE/st1w.s
+++ b/llvm/test/MC/AArch64/SVE/st1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st2b.s b/llvm/test/MC/AArch64/SVE/st2b.s
index 43266733d378a..87a025fa94435 100644
--- a/llvm/test/MC/AArch64/SVE/st2b.s
+++ b/llvm/test/MC/AArch64/SVE/st2b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st2d.s b/llvm/test/MC/AArch64/SVE/st2d.s
index ac5f14c241d19..a32c6d98254d5 100644
--- a/llvm/test/MC/AArch64/SVE/st2d.s
+++ b/llvm/test/MC/AArch64/SVE/st2d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st2h.s b/llvm/test/MC/AArch64/SVE/st2h.s
index 7fc44efbb14a3..8daea62aefa79 100644
--- a/llvm/test/MC/AArch64/SVE/st2h.s
+++ b/llvm/test/MC/AArch64/SVE/st2h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st2w.s b/llvm/test/MC/AArch64/SVE/st2w.s
index 723de51e54b80..80085cbed7cf2 100644
--- a/llvm/test/MC/AArch64/SVE/st2w.s
+++ b/llvm/test/MC/AArch64/SVE/st2w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st3b.s b/llvm/test/MC/AArch64/SVE/st3b.s
index cda9e3d2a3e5c..8c8ed3e5806f3 100644
--- a/llvm/test/MC/AArch64/SVE/st3b.s
+++ b/llvm/test/MC/AArch64/SVE/st3b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st3d.s b/llvm/test/MC/AArch64/SVE/st3d.s
index 1ef8f40e771e4..7d7d05cc88515 100644
--- a/llvm/test/MC/AArch64/SVE/st3d.s
+++ b/llvm/test/MC/AArch64/SVE/st3d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st3h.s b/llvm/test/MC/AArch64/SVE/st3h.s
index d183d2236683a..efba357658f18 100644
--- a/llvm/test/MC/AArch64/SVE/st3h.s
+++ b/llvm/test/MC/AArch64/SVE/st3h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st3w.s b/llvm/test/MC/AArch64/SVE/st3w.s
index 69582c4301619..7f14e48c5c83c 100644
--- a/llvm/test/MC/AArch64/SVE/st3w.s
+++ b/llvm/test/MC/AArch64/SVE/st3w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st4b.s b/llvm/test/MC/AArch64/SVE/st4b.s
index c4a5cfcbb837d..c53e8cde16d75 100644
--- a/llvm/test/MC/AArch64/SVE/st4b.s
+++ b/llvm/test/MC/AArch64/SVE/st4b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st4d.s b/llvm/test/MC/AArch64/SVE/st4d.s
index 1e93f7027bd5a..3d4a0f6dac915 100644
--- a/llvm/test/MC/AArch64/SVE/st4d.s
+++ b/llvm/test/MC/AArch64/SVE/st4d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st4h.s b/llvm/test/MC/AArch64/SVE/st4h.s
index 526f357eecaee..7091a7e24b086 100644
--- a/llvm/test/MC/AArch64/SVE/st4h.s
+++ b/llvm/test/MC/AArch64/SVE/st4h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/st4w.s b/llvm/test/MC/AArch64/SVE/st4w.s
index a52488dda3876..fa13dd63a47cb 100644
--- a/llvm/test/MC/AArch64/SVE/st4w.s
+++ b/llvm/test/MC/AArch64/SVE/st4w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/stnt1b.s b/llvm/test/MC/AArch64/SVE/stnt1b.s
index 602051982e7d1..c10705a2e810a 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1b.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/stnt1d.s b/llvm/test/MC/AArch64/SVE/stnt1d.s
index 4cfce6583210d..a8d798992a192 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1d.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/stnt1h.s b/llvm/test/MC/AArch64/SVE/stnt1h.s
index 454e342e58c65..2da9cebd22f20 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1h.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/stnt1w.s b/llvm/test/MC/AArch64/SVE/stnt1w.s
index 6072ecaa05d97..3291c108dc776 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1w.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/str.s b/llvm/test/MC/AArch64/SVE/str.s
index f14772dd53372..9eff364ef6481 100644
--- a/llvm/test/MC/AArch64/SVE/str.s
+++ b/llvm/test/MC/AArch64/SVE/str.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sub.s b/llvm/test/MC/AArch64/SVE/sub.s
index 8e74cf8cf3f2a..12ae031afa359 100644
--- a/llvm/test/MC/AArch64/SVE/sub.s
+++ b/llvm/test/MC/AArch64/SVE/sub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/subr.s b/llvm/test/MC/AArch64/SVE/subr.s
index ec6fa65c96212..40f09e43a361a 100644
--- a/llvm/test/MC/AArch64/SVE/subr.s
+++ b/llvm/test/MC/AArch64/SVE/subr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sunpkhi.s b/llvm/test/MC/AArch64/SVE/sunpkhi.s
index 9dabf0d3fb942..6965406c47f9e 100644
--- a/llvm/test/MC/AArch64/SVE/sunpkhi.s
+++ b/llvm/test/MC/AArch64/SVE/sunpkhi.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sunpklo.s b/llvm/test/MC/AArch64/SVE/sunpklo.s
index 5c809892d3825..ce297910645ed 100644
--- a/llvm/test/MC/AArch64/SVE/sunpklo.s
+++ b/llvm/test/MC/AArch64/SVE/sunpklo.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sxtb.s b/llvm/test/MC/AArch64/SVE/sxtb.s
index b9fa8b62c71c9..dc26ffc1d71d5 100644
--- a/llvm/test/MC/AArch64/SVE/sxtb.s
+++ b/llvm/test/MC/AArch64/SVE/sxtb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sxth.s b/llvm/test/MC/AArch64/SVE/sxth.s
index e422de5dd6aff..d5e6a6685d90b 100644
--- a/llvm/test/MC/AArch64/SVE/sxth.s
+++ b/llvm/test/MC/AArch64/SVE/sxth.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/sxtw.s b/llvm/test/MC/AArch64/SVE/sxtw.s
index 96c66cb30472c..646c55dec4a5d 100644
--- a/llvm/test/MC/AArch64/SVE/sxtw.s
+++ b/llvm/test/MC/AArch64/SVE/sxtw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/system-regs.s b/llvm/test/MC/AArch64/SVE/system-regs.s
index 17829ebdaaca2..20773ea7d812e 100644
--- a/llvm/test/MC/AArch64/SVE/system-regs.s
+++ b/llvm/test/MC/AArch64/SVE/system-regs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/tbl.s b/llvm/test/MC/AArch64/SVE/tbl.s
index 94e0531115616..8d10db25d9c85 100644
--- a/llvm/test/MC/AArch64/SVE/tbl.s
+++ b/llvm/test/MC/AArch64/SVE/tbl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/trn1.s b/llvm/test/MC/AArch64/SVE/trn1.s
index b943b6d8f807a..5f90835f7d25e 100644
--- a/llvm/test/MC/AArch64/SVE/trn1.s
+++ b/llvm/test/MC/AArch64/SVE/trn1.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/trn2.s b/llvm/test/MC/AArch64/SVE/trn2.s
index 213d3b6ca831a..e47bd6be2b3f8 100644
--- a/llvm/test/MC/AArch64/SVE/trn2.s
+++ b/llvm/test/MC/AArch64/SVE/trn2.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uabd.s b/llvm/test/MC/AArch64/SVE/uabd.s
index 0f1a4b382518d..72a77402f2043 100644
--- a/llvm/test/MC/AArch64/SVE/uabd.s
+++ b/llvm/test/MC/AArch64/SVE/uabd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uaddv.s b/llvm/test/MC/AArch64/SVE/uaddv.s
index 07da5ab7ae2af..255353238d5f1 100644
--- a/llvm/test/MC/AArch64/SVE/uaddv.s
+++ b/llvm/test/MC/AArch64/SVE/uaddv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/ucvtf.s b/llvm/test/MC/AArch64/SVE/ucvtf.s
index 9e5f4f792b147..b777463b58334 100644
--- a/llvm/test/MC/AArch64/SVE/ucvtf.s
+++ b/llvm/test/MC/AArch64/SVE/ucvtf.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/udiv.s b/llvm/test/MC/AArch64/SVE/udiv.s
index ca528ee6d0744..66a4cb059e732 100644
--- a/llvm/test/MC/AArch64/SVE/udiv.s
+++ b/llvm/test/MC/AArch64/SVE/udiv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/udivr.s b/llvm/test/MC/AArch64/SVE/udivr.s
index 45bc391d0ef56..d67ad22d56e3c 100644
--- a/llvm/test/MC/AArch64/SVE/udivr.s
+++ b/llvm/test/MC/AArch64/SVE/udivr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/udot.s b/llvm/test/MC/AArch64/SVE/udot.s
index c9b441172de29..13c4aa6258efe 100644
--- a/llvm/test/MC/AArch64/SVE/udot.s
+++ b/llvm/test/MC/AArch64/SVE/udot.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/umax.s b/llvm/test/MC/AArch64/SVE/umax.s
index bd89da13241b3..b15a05d90f372 100644
--- a/llvm/test/MC/AArch64/SVE/umax.s
+++ b/llvm/test/MC/AArch64/SVE/umax.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/umaxv.s b/llvm/test/MC/AArch64/SVE/umaxv.s
index c573e1bc2c61d..e59dd3101e6a4 100644
--- a/llvm/test/MC/AArch64/SVE/umaxv.s
+++ b/llvm/test/MC/AArch64/SVE/umaxv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/umin.s b/llvm/test/MC/AArch64/SVE/umin.s
index 9aac3092df21b..9d26044938ae0 100644
--- a/llvm/test/MC/AArch64/SVE/umin.s
+++ b/llvm/test/MC/AArch64/SVE/umin.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uminv.s b/llvm/test/MC/AArch64/SVE/uminv.s
index e2512dad0a800..6fc8fbc63b1a2 100644
--- a/llvm/test/MC/AArch64/SVE/uminv.s
+++ b/llvm/test/MC/AArch64/SVE/uminv.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/umulh.s b/llvm/test/MC/AArch64/SVE/umulh.s
index a5d6eb58603aa..2f5f196f8d4ac 100644
--- a/llvm/test/MC/AArch64/SVE/umulh.s
+++ b/llvm/test/MC/AArch64/SVE/umulh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqadd.s b/llvm/test/MC/AArch64/SVE/uqadd.s
index 23e213ac85f91..73f7c7754ea41 100644
--- a/llvm/test/MC/AArch64/SVE/uqadd.s
+++ b/llvm/test/MC/AArch64/SVE/uqadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecb.s b/llvm/test/MC/AArch64/SVE/uqdecb.s
index 4b4e0664fc19c..eba286aa36b39 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecb.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecd.s b/llvm/test/MC/AArch64/SVE/uqdecd.s
index f47d0d412990d..62f27f5380749 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecd.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdech.s b/llvm/test/MC/AArch64/SVE/uqdech.s
index 9a1ff52560404..adaa3669f9caa 100644
--- a/llvm/test/MC/AArch64/SVE/uqdech.s
+++ b/llvm/test/MC/AArch64/SVE/uqdech.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecp.s b/llvm/test/MC/AArch64/SVE/uqdecp.s
index 6e4717ba93234..2b15ac1010c75 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecp.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecw.s b/llvm/test/MC/AArch64/SVE/uqdecw.s
index 6ed544d5733f2..cf80420b6b254 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecw.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincb.s b/llvm/test/MC/AArch64/SVE/uqincb.s
index 16c621c512a20..a6f6d2e4a5417 100644
--- a/llvm/test/MC/AArch64/SVE/uqincb.s
+++ b/llvm/test/MC/AArch64/SVE/uqincb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincd.s b/llvm/test/MC/AArch64/SVE/uqincd.s
index d72672ced4247..53d5fb7b19f95 100644
--- a/llvm/test/MC/AArch64/SVE/uqincd.s
+++ b/llvm/test/MC/AArch64/SVE/uqincd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqinch.s b/llvm/test/MC/AArch64/SVE/uqinch.s
index 03c7fb7fe9a85..91d035ac88fb6 100644
--- a/llvm/test/MC/AArch64/SVE/uqinch.s
+++ b/llvm/test/MC/AArch64/SVE/uqinch.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincp.s b/llvm/test/MC/AArch64/SVE/uqincp.s
index 05cfdea05a301..f5791c6d2fb36 100644
--- a/llvm/test/MC/AArch64/SVE/uqincp.s
+++ b/llvm/test/MC/AArch64/SVE/uqincp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincw.s b/llvm/test/MC/AArch64/SVE/uqincw.s
index 1944d69625e5f..7e0c49714d9e5 100644
--- a/llvm/test/MC/AArch64/SVE/uqincw.s
+++ b/llvm/test/MC/AArch64/SVE/uqincw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uqsub.s b/llvm/test/MC/AArch64/SVE/uqsub.s
index 5bcc10f8b2ea1..90ee664fdbedd 100644
--- a/llvm/test/MC/AArch64/SVE/uqsub.s
+++ b/llvm/test/MC/AArch64/SVE/uqsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uunpkhi.s b/llvm/test/MC/AArch64/SVE/uunpkhi.s
index 39404904ca9f3..1e31b07a4bf99 100644
--- a/llvm/test/MC/AArch64/SVE/uunpkhi.s
+++ b/llvm/test/MC/AArch64/SVE/uunpkhi.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uunpklo.s b/llvm/test/MC/AArch64/SVE/uunpklo.s
index f825f6c4698c9..6ca6c825b1586 100644
--- a/llvm/test/MC/AArch64/SVE/uunpklo.s
+++ b/llvm/test/MC/AArch64/SVE/uunpklo.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uxtb.s b/llvm/test/MC/AArch64/SVE/uxtb.s
index 81d7dc01e02ab..c7c17877b9797 100644
--- a/llvm/test/MC/AArch64/SVE/uxtb.s
+++ b/llvm/test/MC/AArch64/SVE/uxtb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uxth.s b/llvm/test/MC/AArch64/SVE/uxth.s
index 10074b4094296..5bbbc6e4c5480 100644
--- a/llvm/test/MC/AArch64/SVE/uxth.s
+++ b/llvm/test/MC/AArch64/SVE/uxth.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uxtw.s b/llvm/test/MC/AArch64/SVE/uxtw.s
index c72fedf31de3d..9733c0ff0cf4e 100644
--- a/llvm/test/MC/AArch64/SVE/uxtw.s
+++ b/llvm/test/MC/AArch64/SVE/uxtw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uzp1.s b/llvm/test/MC/AArch64/SVE/uzp1.s
index a8eeaa29ca3ba..aced50d4983cb 100644
--- a/llvm/test/MC/AArch64/SVE/uzp1.s
+++ b/llvm/test/MC/AArch64/SVE/uzp1.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/uzp2.s b/llvm/test/MC/AArch64/SVE/uzp2.s
index 49573f1370cc6..d60aca0c59a73 100644
--- a/llvm/test/MC/AArch64/SVE/uzp2.s
+++ b/llvm/test/MC/AArch64/SVE/uzp2.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/whilele.s b/llvm/test/MC/AArch64/SVE/whilele.s
index e8c48a6e926f7..477d3e1bd9615 100644
--- a/llvm/test/MC/AArch64/SVE/whilele.s
+++ b/llvm/test/MC/AArch64/SVE/whilele.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/whilelo.s b/llvm/test/MC/AArch64/SVE/whilelo.s
index 30fa35dcd2cfb..1f8dfaf33c2fd 100644
--- a/llvm/test/MC/AArch64/SVE/whilelo.s
+++ b/llvm/test/MC/AArch64/SVE/whilelo.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/whilels.s b/llvm/test/MC/AArch64/SVE/whilels.s
index 3e127d3e1720b..1b1221b2950b6 100644
--- a/llvm/test/MC/AArch64/SVE/whilels.s
+++ b/llvm/test/MC/AArch64/SVE/whilels.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/whilelt.s b/llvm/test/MC/AArch64/SVE/whilelt.s
index 9a0723cdc7c92..f0fa31c6e6e3d 100644
--- a/llvm/test/MC/AArch64/SVE/whilelt.s
+++ b/llvm/test/MC/AArch64/SVE/whilelt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/wrffr.s b/llvm/test/MC/AArch64/SVE/wrffr.s
index dec71605be8cd..23cca9c1fabcd 100644
--- a/llvm/test/MC/AArch64/SVE/wrffr.s
+++ b/llvm/test/MC/AArch64/SVE/wrffr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/zip1.s b/llvm/test/MC/AArch64/SVE/zip1.s
index 47d08328fd91e..9c5d658e67e7f 100644
--- a/llvm/test/MC/AArch64/SVE/zip1.s
+++ b/llvm/test/MC/AArch64/SVE/zip1.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE/zip2.s b/llvm/test/MC/AArch64/SVE/zip2.s
index 3158e989ce745..c91a0dd620aa2 100644
--- a/llvm/test/MC/AArch64/SVE/zip2.s
+++ b/llvm/test/MC/AArch64/SVE/zip2.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/adclb.s b/llvm/test/MC/AArch64/SVE2/adclb.s
index bcc0297173d03..4f5c2bc5fea9c 100644
--- a/llvm/test/MC/AArch64/SVE2/adclb.s
+++ b/llvm/test/MC/AArch64/SVE2/adclb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/adclt.s b/llvm/test/MC/AArch64/SVE2/adclt.s
index 46de92fd5a542..ab2798d2f0b81 100644
--- a/llvm/test/MC/AArch64/SVE2/adclt.s
+++ b/llvm/test/MC/AArch64/SVE2/adclt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/addhnb.s b/llvm/test/MC/AArch64/SVE2/addhnb.s
index fa9e855634bac..8b479298421ca 100644
--- a/llvm/test/MC/AArch64/SVE2/addhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/addhnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/addhnt.s b/llvm/test/MC/AArch64/SVE2/addhnt.s
index fe77e5abe713e..3ca3320b852fa 100644
--- a/llvm/test/MC/AArch64/SVE2/addhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/addhnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/addp.s b/llvm/test/MC/AArch64/SVE2/addp.s
index 24de93b86f411..0ea7375c4d965 100644
--- a/llvm/test/MC/AArch64/SVE2/addp.s
+++ b/llvm/test/MC/AArch64/SVE2/addp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/aesd.s b/llvm/test/MC/AArch64/SVE2/aesd.s
index 656664e900cd4..db78ad5f038f3 100644
--- a/llvm/test/MC/AArch64/SVE2/aesd.s
+++ b/llvm/test/MC/AArch64/SVE2/aesd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/aese.s b/llvm/test/MC/AArch64/SVE2/aese.s
index 5def632228be4..f013105ca83c0 100644
--- a/llvm/test/MC/AArch64/SVE2/aese.s
+++ b/llvm/test/MC/AArch64/SVE2/aese.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/aesimc.s b/llvm/test/MC/AArch64/SVE2/aesimc.s
index 224d56bcfc8ff..932ee55f89602 100644
--- a/llvm/test/MC/AArch64/SVE2/aesimc.s
+++ b/llvm/test/MC/AArch64/SVE2/aesimc.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/aesmc.s b/llvm/test/MC/AArch64/SVE2/aesmc.s
index c7951d63edfb9..9cacf97e1eaf7 100644
--- a/llvm/test/MC/AArch64/SVE2/aesmc.s
+++ b/llvm/test/MC/AArch64/SVE2/aesmc.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bcax.s b/llvm/test/MC/AArch64/SVE2/bcax.s
index 9263712bc0a54..55448fb69c718 100644
--- a/llvm/test/MC/AArch64/SVE2/bcax.s
+++ b/llvm/test/MC/AArch64/SVE2/bcax.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bdep.s b/llvm/test/MC/AArch64/SVE2/bdep.s
index 0bc935226373f..26d28f1ce75fb 100644
--- a/llvm/test/MC/AArch64/SVE2/bdep.s
+++ b/llvm/test/MC/AArch64/SVE2/bdep.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bext.s b/llvm/test/MC/AArch64/SVE2/bext.s
index ae3d0bfbff5ef..b11d57c532215 100644
--- a/llvm/test/MC/AArch64/SVE2/bext.s
+++ b/llvm/test/MC/AArch64/SVE2/bext.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bgrp.s b/llvm/test/MC/AArch64/SVE2/bgrp.s
index 3d994c0a3648d..5b671c589b839 100644
--- a/llvm/test/MC/AArch64/SVE2/bgrp.s
+++ b/llvm/test/MC/AArch64/SVE2/bgrp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bsl.s b/llvm/test/MC/AArch64/SVE2/bsl.s
index acf3a65fc5543..e19fe7a989003 100644
--- a/llvm/test/MC/AArch64/SVE2/bsl.s
+++ b/llvm/test/MC/AArch64/SVE2/bsl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bsl1n.s b/llvm/test/MC/AArch64/SVE2/bsl1n.s
index fda643103e702..8edefc197ddee 100644
--- a/llvm/test/MC/AArch64/SVE2/bsl1n.s
+++ b/llvm/test/MC/AArch64/SVE2/bsl1n.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/bsl2n.s b/llvm/test/MC/AArch64/SVE2/bsl2n.s
index f4482ef134848..e01e6c88ecd59 100644
--- a/llvm/test/MC/AArch64/SVE2/bsl2n.s
+++ b/llvm/test/MC/AArch64/SVE2/bsl2n.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/cadd.s b/llvm/test/MC/AArch64/SVE2/cadd.s
index 75d1deb29f0fc..6df6a7b4233ea 100644
--- a/llvm/test/MC/AArch64/SVE2/cadd.s
+++ b/llvm/test/MC/AArch64/SVE2/cadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/cdot.s b/llvm/test/MC/AArch64/SVE2/cdot.s
index 5f81bbbcd6ff6..dd0da23a1f119 100644
--- a/llvm/test/MC/AArch64/SVE2/cdot.s
+++ b/llvm/test/MC/AArch64/SVE2/cdot.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/cmla.s b/llvm/test/MC/AArch64/SVE2/cmla.s
index 84b870a0d13dc..6c15b40e52e21 100644
--- a/llvm/test/MC/AArch64/SVE2/cmla.s
+++ b/llvm/test/MC/AArch64/SVE2/cmla.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/eor3.s b/llvm/test/MC/AArch64/SVE2/eor3.s
index cf385122744ca..ac2f02389979d 100644
--- a/llvm/test/MC/AArch64/SVE2/eor3.s
+++ b/llvm/test/MC/AArch64/SVE2/eor3.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/eorbt.s b/llvm/test/MC/AArch64/SVE2/eorbt.s
index 6c88b63bb6ee6..966417f442809 100644
--- a/llvm/test/MC/AArch64/SVE2/eorbt.s
+++ b/llvm/test/MC/AArch64/SVE2/eorbt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/eortb.s b/llvm/test/MC/AArch64/SVE2/eortb.s
index 2fe781c1fd675..895ba1829eedc 100644
--- a/llvm/test/MC/AArch64/SVE2/eortb.s
+++ b/llvm/test/MC/AArch64/SVE2/eortb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ext.s b/llvm/test/MC/AArch64/SVE2/ext.s
index 17e8249127626..146b2a2f64420 100644
--- a/llvm/test/MC/AArch64/SVE2/ext.s
+++ b/llvm/test/MC/AArch64/SVE2/ext.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/faddp.s b/llvm/test/MC/AArch64/SVE2/faddp.s
index 8c05eff4cc14b..bdc5309271c01 100644
--- a/llvm/test/MC/AArch64/SVE2/faddp.s
+++ b/llvm/test/MC/AArch64/SVE2/faddp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fcvtlt.s b/llvm/test/MC/AArch64/SVE2/fcvtlt.s
index d5942ad447244..e437526264031 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtlt.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtlt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fcvtnt.s b/llvm/test/MC/AArch64/SVE2/fcvtnt.s
index 9de9ea7a82f0e..1d6b38862e7a4 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtnt.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fcvtx.s b/llvm/test/MC/AArch64/SVE2/fcvtx.s
index 55d60cfeb10de..7d0d587bc6c04 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtx.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtx.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fcvtxnt.s b/llvm/test/MC/AArch64/SVE2/fcvtxnt.s
index 25bb1672d0a4c..32df6a2087142 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtxnt.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtxnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/flogb.s b/llvm/test/MC/AArch64/SVE2/flogb.s
index 4ef28f0859a39..4668ed1766bb3 100644
--- a/llvm/test/MC/AArch64/SVE2/flogb.s
+++ b/llvm/test/MC/AArch64/SVE2/flogb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fmaxnmp.s b/llvm/test/MC/AArch64/SVE2/fmaxnmp.s
index 6a35174a498a1..1f143adceecc5 100644
--- a/llvm/test/MC/AArch64/SVE2/fmaxnmp.s
+++ b/llvm/test/MC/AArch64/SVE2/fmaxnmp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fmaxp.s b/llvm/test/MC/AArch64/SVE2/fmaxp.s
index 9d2eb4c2f38f4..5d4b293c4e4b5 100644
--- a/llvm/test/MC/AArch64/SVE2/fmaxp.s
+++ b/llvm/test/MC/AArch64/SVE2/fmaxp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fminnmp.s b/llvm/test/MC/AArch64/SVE2/fminnmp.s
index b40510a064532..4afedb17e28ae 100644
--- a/llvm/test/MC/AArch64/SVE2/fminnmp.s
+++ b/llvm/test/MC/AArch64/SVE2/fminnmp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fminp.s b/llvm/test/MC/AArch64/SVE2/fminp.s
index f33ad1b0e5822..b533f085d6882 100644
--- a/llvm/test/MC/AArch64/SVE2/fminp.s
+++ b/llvm/test/MC/AArch64/SVE2/fminp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fmlalb.s b/llvm/test/MC/AArch64/SVE2/fmlalb.s
index 87e3c83670109..9cd315efa1144 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlalb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fmlalt.s b/llvm/test/MC/AArch64/SVE2/fmlalt.s
index 2082bfff5bcd5..fcafb33dfd9ae 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlalt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fmlslb.s b/llvm/test/MC/AArch64/SVE2/fmlslb.s
index 1b3ffbf36affe..b56e9e59308de 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlslb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/fmlslt.s b/llvm/test/MC/AArch64/SVE2/fmlslt.s
index 4a92adc77eb6c..c9e4f6f725255 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlslt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/histcnt.s b/llvm/test/MC/AArch64/SVE2/histcnt.s
index e5ac009e2b642..ec004229282d9 100644
--- a/llvm/test/MC/AArch64/SVE2/histcnt.s
+++ b/llvm/test/MC/AArch64/SVE2/histcnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/histseg.s b/llvm/test/MC/AArch64/SVE2/histseg.s
index be670d01b3104..9e11d9a90bb1b 100644
--- a/llvm/test/MC/AArch64/SVE2/histseg.s
+++ b/llvm/test/MC/AArch64/SVE2/histseg.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1b.s b/llvm/test/MC/AArch64/SVE2/ldnt1b.s
index 71f1ae6a513e8..c64b8e4b5d7bb 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1b.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1d.s b/llvm/test/MC/AArch64/SVE2/ldnt1d.s
index c83c0c2425d1b..71c489e44d833 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1d.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1h.s b/llvm/test/MC/AArch64/SVE2/ldnt1h.s
index 419bb43dad78b..abf046fc9d300 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1h.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1sb.s b/llvm/test/MC/AArch64/SVE2/ldnt1sb.s
index cb7ae1e6d4461..7a2bd31248352 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1sb.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1sb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1sh.s b/llvm/test/MC/AArch64/SVE2/ldnt1sh.s
index 7d8f4d228d5ae..3f2563b642c48 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1sh.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1sh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1sw.s b/llvm/test/MC/AArch64/SVE2/ldnt1sw.s
index 52b474739e55f..fabc0668d67d4 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1sw.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1sw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ldnt1w.s b/llvm/test/MC/AArch64/SVE2/ldnt1w.s
index 89191303d3e73..0a4210ba3d8a9 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1w.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/match.s b/llvm/test/MC/AArch64/SVE2/match.s
index 07008f0d506d1..cbb94adec021c 100644
--- a/llvm/test/MC/AArch64/SVE2/match.s
+++ b/llvm/test/MC/AArch64/SVE2/match.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/mla.s b/llvm/test/MC/AArch64/SVE2/mla.s
index 8abd8b1bc7173..bd06840af4892 100644
--- a/llvm/test/MC/AArch64/SVE2/mla.s
+++ b/llvm/test/MC/AArch64/SVE2/mla.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/mls.s b/llvm/test/MC/AArch64/SVE2/mls.s
index 9d8e178448eb1..239ef20cf45c9 100644
--- a/llvm/test/MC/AArch64/SVE2/mls.s
+++ b/llvm/test/MC/AArch64/SVE2/mls.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/mul.s b/llvm/test/MC/AArch64/SVE2/mul.s
index 38f487d20b98f..1a54715f18e6d 100644
--- a/llvm/test/MC/AArch64/SVE2/mul.s
+++ b/llvm/test/MC/AArch64/SVE2/mul.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/nbsl.s b/llvm/test/MC/AArch64/SVE2/nbsl.s
index 5df8ad0c398fa..dafb6fe4bdfae 100644
--- a/llvm/test/MC/AArch64/SVE2/nbsl.s
+++ b/llvm/test/MC/AArch64/SVE2/nbsl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/nmatch.s b/llvm/test/MC/AArch64/SVE2/nmatch.s
index 6121f5530c446..5e1fe14f5e264 100644
--- a/llvm/test/MC/AArch64/SVE2/nmatch.s
+++ b/llvm/test/MC/AArch64/SVE2/nmatch.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/pmul.s b/llvm/test/MC/AArch64/SVE2/pmul.s
index fb77cdaab52c5..e42a388ed96b6 100644
--- a/llvm/test/MC/AArch64/SVE2/pmul.s
+++ b/llvm/test/MC/AArch64/SVE2/pmul.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/pmullb-128.s b/llvm/test/MC/AArch64/SVE2/pmullb-128.s
index 021874e9e69a0..119b391289213 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullb-128.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullb-128.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/pmullb.s b/llvm/test/MC/AArch64/SVE2/pmullb.s
index 5a9989ab3837e..b906ddb0f1d8d 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullb.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/pmullt-128.s b/llvm/test/MC/AArch64/SVE2/pmullt-128.s
index 5b454b01f33b0..a55dafda4deac 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullt-128.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullt-128.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/pmullt.s b/llvm/test/MC/AArch64/SVE2/pmullt.s
index 9493e2a1a8248..601234c9cd90e 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullt.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/raddhnb.s b/llvm/test/MC/AArch64/SVE2/raddhnb.s
index ff04d6b512c0f..a0069f076417a 100644
--- a/llvm/test/MC/AArch64/SVE2/raddhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/raddhnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/raddhnt.s b/llvm/test/MC/AArch64/SVE2/raddhnt.s
index f6e79af85e5e7..8d85ca19d6699 100644
--- a/llvm/test/MC/AArch64/SVE2/raddhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/raddhnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/rax1.s b/llvm/test/MC/AArch64/SVE2/rax1.s
index 44634d45bde2e..7cfb0327f2603 100644
--- a/llvm/test/MC/AArch64/SVE2/rax1.s
+++ b/llvm/test/MC/AArch64/SVE2/rax1.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sha3 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-sha3 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-sha3 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sha3 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/rshrnb.s b/llvm/test/MC/AArch64/SVE2/rshrnb.s
index 1d503099b1452..93d98eeab8885 100644
--- a/llvm/test/MC/AArch64/SVE2/rshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/rshrnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/rshrnt.s b/llvm/test/MC/AArch64/SVE2/rshrnt.s
index 4e997d841e7ec..eeee12dad5b5a 100644
--- a/llvm/test/MC/AArch64/SVE2/rshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/rshrnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/rsubhnb.s b/llvm/test/MC/AArch64/SVE2/rsubhnb.s
index 55a93177d78e6..e929217e01a04 100644
--- a/llvm/test/MC/AArch64/SVE2/rsubhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/rsubhnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/rsubhnt.s b/llvm/test/MC/AArch64/SVE2/rsubhnt.s
index 16505e5e31787..76395deb85854 100644
--- a/llvm/test/MC/AArch64/SVE2/rsubhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/rsubhnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/saba.s b/llvm/test/MC/AArch64/SVE2/saba.s
index 7d02e9816fbcb..1df4d662b21e1 100644
--- a/llvm/test/MC/AArch64/SVE2/saba.s
+++ b/llvm/test/MC/AArch64/SVE2/saba.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sabalb.s b/llvm/test/MC/AArch64/SVE2/sabalb.s
index 450c005fb55ef..f393cd3cf5139 100644
--- a/llvm/test/MC/AArch64/SVE2/sabalb.s
+++ b/llvm/test/MC/AArch64/SVE2/sabalb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sabalt.s b/llvm/test/MC/AArch64/SVE2/sabalt.s
index 2653848efb172..00aca2d5b631b 100644
--- a/llvm/test/MC/AArch64/SVE2/sabalt.s
+++ b/llvm/test/MC/AArch64/SVE2/sabalt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sabdlb.s b/llvm/test/MC/AArch64/SVE2/sabdlb.s
index af2b358cea737..f56fad5ed6d3c 100644
--- a/llvm/test/MC/AArch64/SVE2/sabdlb.s
+++ b/llvm/test/MC/AArch64/SVE2/sabdlb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sabdlt.s b/llvm/test/MC/AArch64/SVE2/sabdlt.s
index f8819b5a388ae..0a8c69d93017d 100644
--- a/llvm/test/MC/AArch64/SVE2/sabdlt.s
+++ b/llvm/test/MC/AArch64/SVE2/sabdlt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sadalp.s b/llvm/test/MC/AArch64/SVE2/sadalp.s
index bc6ab03fe7b04..94ab1d60a1cae 100644
--- a/llvm/test/MC/AArch64/SVE2/sadalp.s
+++ b/llvm/test/MC/AArch64/SVE2/sadalp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/saddlb.s b/llvm/test/MC/AArch64/SVE2/saddlb.s
index d592ae8ec6a79..3e883ab2f356b 100644
--- a/llvm/test/MC/AArch64/SVE2/saddlb.s
+++ b/llvm/test/MC/AArch64/SVE2/saddlb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/saddlbt.s b/llvm/test/MC/AArch64/SVE2/saddlbt.s
index 5dcec3bc13c19..a4e53cd39a455 100644
--- a/llvm/test/MC/AArch64/SVE2/saddlbt.s
+++ b/llvm/test/MC/AArch64/SVE2/saddlbt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/saddlt.s b/llvm/test/MC/AArch64/SVE2/saddlt.s
index 047bc4fa2ba37..03387961f9aa7 100644
--- a/llvm/test/MC/AArch64/SVE2/saddlt.s
+++ b/llvm/test/MC/AArch64/SVE2/saddlt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/saddwb.s b/llvm/test/MC/AArch64/SVE2/saddwb.s
index 2b9213de26070..55a81d968884c 100644
--- a/llvm/test/MC/AArch64/SVE2/saddwb.s
+++ b/llvm/test/MC/AArch64/SVE2/saddwb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/saddwt.s b/llvm/test/MC/AArch64/SVE2/saddwt.s
index 7521eb6f0133e..72c57f38bee03 100644
--- a/llvm/test/MC/AArch64/SVE2/saddwt.s
+++ b/llvm/test/MC/AArch64/SVE2/saddwt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sbclb.s b/llvm/test/MC/AArch64/SVE2/sbclb.s
index bec58658aa431..fd385ebde8f2a 100644
--- a/llvm/test/MC/AArch64/SVE2/sbclb.s
+++ b/llvm/test/MC/AArch64/SVE2/sbclb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sbclt.s b/llvm/test/MC/AArch64/SVE2/sbclt.s
index e35499f72a31b..79e613cc743b9 100644
--- a/llvm/test/MC/AArch64/SVE2/sbclt.s
+++ b/llvm/test/MC/AArch64/SVE2/sbclt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/shadd.s b/llvm/test/MC/AArch64/SVE2/shadd.s
index d6cc03a7baf05..f2d3aa1350d39 100644
--- a/llvm/test/MC/AArch64/SVE2/shadd.s
+++ b/llvm/test/MC/AArch64/SVE2/shadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/shrnb.s b/llvm/test/MC/AArch64/SVE2/shrnb.s
index e59f35a275cd5..5aae42ed5eb1b 100644
--- a/llvm/test/MC/AArch64/SVE2/shrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/shrnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/shrnt.s b/llvm/test/MC/AArch64/SVE2/shrnt.s
index 539f415a2de74..3cdc7c97829f0 100644
--- a/llvm/test/MC/AArch64/SVE2/shrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/shrnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/shsub.s b/llvm/test/MC/AArch64/SVE2/shsub.s
index 944be967bb9ec..57b85f98cfc50 100644
--- a/llvm/test/MC/AArch64/SVE2/shsub.s
+++ b/llvm/test/MC/AArch64/SVE2/shsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/shsubr.s b/llvm/test/MC/AArch64/SVE2/shsubr.s
index 3e8ff54099ced..34e7ec00afc47 100644
--- a/llvm/test/MC/AArch64/SVE2/shsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/shsubr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sli.s b/llvm/test/MC/AArch64/SVE2/sli.s
index e5100fd057874..9a5e10dd4d80d 100644
--- a/llvm/test/MC/AArch64/SVE2/sli.s
+++ b/llvm/test/MC/AArch64/SVE2/sli.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sm4e.s b/llvm/test/MC/AArch64/SVE2/sm4e.s
index c11cee5081ba5..7a4d29d3e7de3 100644
--- a/llvm/test/MC/AArch64/SVE2/sm4e.s
+++ b/llvm/test/MC/AArch64/SVE2/sm4e.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sm4ekey.s b/llvm/test/MC/AArch64/SVE2/sm4ekey.s
index 555eb09da748a..b9d51fd52bbe7 100644
--- a/llvm/test/MC/AArch64/SVE2/sm4ekey.s
+++ b/llvm/test/MC/AArch64/SVE2/sm4ekey.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smaxp.s b/llvm/test/MC/AArch64/SVE2/smaxp.s
index 3e466dd20ef38..d9b324545ebf5 100644
--- a/llvm/test/MC/AArch64/SVE2/smaxp.s
+++ b/llvm/test/MC/AArch64/SVE2/smaxp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sminp.s b/llvm/test/MC/AArch64/SVE2/sminp.s
index 5876571c5a244..e776fb0041af4 100644
--- a/llvm/test/MC/AArch64/SVE2/sminp.s
+++ b/llvm/test/MC/AArch64/SVE2/sminp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smlalb.s b/llvm/test/MC/AArch64/SVE2/smlalb.s
index 069e98447a449..fde3579313596 100644
--- a/llvm/test/MC/AArch64/SVE2/smlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/smlalb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smlalt.s b/llvm/test/MC/AArch64/SVE2/smlalt.s
index 43192dcb1b99b..51a397c182b11 100644
--- a/llvm/test/MC/AArch64/SVE2/smlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/smlalt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smlslb.s b/llvm/test/MC/AArch64/SVE2/smlslb.s
index 34aa1ebdbbf28..78ee12a38931e 100644
--- a/llvm/test/MC/AArch64/SVE2/smlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/smlslb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smlslt.s b/llvm/test/MC/AArch64/SVE2/smlslt.s
index b0bc1641818c1..c2b6a6f4eb933 100644
--- a/llvm/test/MC/AArch64/SVE2/smlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/smlslt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smulh.s b/llvm/test/MC/AArch64/SVE2/smulh.s
index cc99e472f338a..4fa9a15e60e86 100644
--- a/llvm/test/MC/AArch64/SVE2/smulh.s
+++ b/llvm/test/MC/AArch64/SVE2/smulh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smullb.s b/llvm/test/MC/AArch64/SVE2/smullb.s
index 259189df2aee2..a8f693a25c34b 100644
--- a/llvm/test/MC/AArch64/SVE2/smullb.s
+++ b/llvm/test/MC/AArch64/SVE2/smullb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/smullt.s b/llvm/test/MC/AArch64/SVE2/smullt.s
index c5f488b264cbd..63dbe1b38455b 100644
--- a/llvm/test/MC/AArch64/SVE2/smullt.s
+++ b/llvm/test/MC/AArch64/SVE2/smullt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/splice.s b/llvm/test/MC/AArch64/SVE2/splice.s
index 4bc03e3bd38f5..6ddd646147be5 100644
--- a/llvm/test/MC/AArch64/SVE2/splice.s
+++ b/llvm/test/MC/AArch64/SVE2/splice.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqabs.s b/llvm/test/MC/AArch64/SVE2/sqabs.s
index 23c7c5708b4fc..8c3cd8adb1b75 100644
--- a/llvm/test/MC/AArch64/SVE2/sqabs.s
+++ b/llvm/test/MC/AArch64/SVE2/sqabs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqadd.s b/llvm/test/MC/AArch64/SVE2/sqadd.s
index 77c3ca9f499fe..14c07102095bd 100644
--- a/llvm/test/MC/AArch64/SVE2/sqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/sqadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqcadd.s b/llvm/test/MC/AArch64/SVE2/sqcadd.s
index 2784d1d15bd0b..b5f85bfdc9289 100644
--- a/llvm/test/MC/AArch64/SVE2/sqcadd.s
+++ b/llvm/test/MC/AArch64/SVE2/sqcadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlalb.s b/llvm/test/MC/AArch64/SVE2/sqdmlalb.s
index 5aef676916c19..8c95d5a348c9d 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlalb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s b/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
index 014c6aa1392dd..1bfbab88624a4 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlalt.s b/llvm/test/MC/AArch64/SVE2/sqdmlalt.s
index f95d7ac8eaa93..9ca31bbf7173c 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlalt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlslb.s b/llvm/test/MC/AArch64/SVE2/sqdmlslb.s
index de3ad67ef76de..78cb0fc9afa98 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlslb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s b/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
index fea1f868f1e91..d56af2ea31a50 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlslt.s b/llvm/test/MC/AArch64/SVE2/sqdmlslt.s
index 3dea4614d7617..5447b3200c3f9 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlslt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmulh.s b/llvm/test/MC/AArch64/SVE2/sqdmulh.s
index c3829c1703bbe..06be58f32aaa0 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmulh.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmulh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmullb.s b/llvm/test/MC/AArch64/SVE2/sqdmullb.s
index ee992b0e6cc84..47bc1c83b4f00 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmullb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmullb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqdmullt.s b/llvm/test/MC/AArch64/SVE2/sqdmullt.s
index 8bc7895b4b4a0..56132a37b4a3c 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmullt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmullt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqneg.s b/llvm/test/MC/AArch64/SVE2/sqneg.s
index a66d5768ebbfb..1bef14594c0cb 100644
--- a/llvm/test/MC/AArch64/SVE2/sqneg.s
+++ b/llvm/test/MC/AArch64/SVE2/sqneg.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s b/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
index be91086f1fa21..378bfa1c6c024 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrdmlah.s b/llvm/test/MC/AArch64/SVE2/sqrdmlah.s
index e6f6b08d6bbf7..277265c58e8f8 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdmlah.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdmlah.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s b/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
index 78a3cb58d82df..97531eed26bba 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrdmulh.s b/llvm/test/MC/AArch64/SVE2/sqrdmulh.s
index 6deeb76849b3b..c356c475b5850 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdmulh.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdmulh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrshl.s b/llvm/test/MC/AArch64/SVE2/sqrshl.s
index 048d952629674..1f0a0fb0ca0df 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshl.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrshlr.s b/llvm/test/MC/AArch64/SVE2/sqrshlr.s
index 4566611ee14a1..9a52ba6643e23 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshlr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrnb.s b/llvm/test/MC/AArch64/SVE2/sqrshrnb.s
index d5c6e8cd85138..0260c5abc27aa 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrnt.s b/llvm/test/MC/AArch64/SVE2/sqrshrnt.s
index f299e9db34804..eabdf96b88736 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrunb.s b/llvm/test/MC/AArch64/SVE2/sqrshrunb.s
index 2380347f8c34b..2a557bdaa7259 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrunb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrunb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrunt.s b/llvm/test/MC/AArch64/SVE2/sqrshrunt.s
index 95f060db6231c..1dc68333c7d96 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrunt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrunt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshl.s b/llvm/test/MC/AArch64/SVE2/sqshl.s
index c7065a50ccd53..5d3c0bb4ea524 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshl.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshlr.s b/llvm/test/MC/AArch64/SVE2/sqshlr.s
index 36e95d7fd3b7d..3ea9c2fabba20 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshlr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshlu.s b/llvm/test/MC/AArch64/SVE2/sqshlu.s
index 196db03a26dfe..c549bcf8010e5 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshlu.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshlu.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshrnb.s b/llvm/test/MC/AArch64/SVE2/sqshrnb.s
index e829f4995f0c6..a0ed5414fcf56 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshrnt.s b/llvm/test/MC/AArch64/SVE2/sqshrnt.s
index f57b2c00369a8..a66ee2441287b 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshrunb.s b/llvm/test/MC/AArch64/SVE2/sqshrunb.s
index 8275da0f16ff3..3e5dedd5edacf 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrunb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrunb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqshrunt.s b/llvm/test/MC/AArch64/SVE2/sqshrunt.s
index 86d62285a6134..5847a0436afe8 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrunt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrunt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqsub.s b/llvm/test/MC/AArch64/SVE2/sqsub.s
index 9a3e4c73bfcec..661f187a0b2a7 100644
--- a/llvm/test/MC/AArch64/SVE2/sqsub.s
+++ b/llvm/test/MC/AArch64/SVE2/sqsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqsubr.s b/llvm/test/MC/AArch64/SVE2/sqsubr.s
index a19d4fef39ecd..bf8f2d639db49 100644
--- a/llvm/test/MC/AArch64/SVE2/sqsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/sqsubr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqxtnb.s b/llvm/test/MC/AArch64/SVE2/sqxtnb.s
index 7f0dcea20a3e8..a91c8fd2cd897 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtnb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqxtnt.s b/llvm/test/MC/AArch64/SVE2/sqxtnt.s
index 9715b97b14f25..1b391d1bc9f43 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtnt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqxtunb.s b/llvm/test/MC/AArch64/SVE2/sqxtunb.s
index 6db3885001226..c38c7be79f743 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtunb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtunb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sqxtunt.s b/llvm/test/MC/AArch64/SVE2/sqxtunt.s
index bd09163c08bcc..44811be3eb45f 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtunt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtunt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/srhadd.s b/llvm/test/MC/AArch64/SVE2/srhadd.s
index 6d323c7623164..5a995ddb69f38 100644
--- a/llvm/test/MC/AArch64/SVE2/srhadd.s
+++ b/llvm/test/MC/AArch64/SVE2/srhadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sri.s b/llvm/test/MC/AArch64/SVE2/sri.s
index c06fa6bc4527e..74551697af885 100644
--- a/llvm/test/MC/AArch64/SVE2/sri.s
+++ b/llvm/test/MC/AArch64/SVE2/sri.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/srshl.s b/llvm/test/MC/AArch64/SVE2/srshl.s
index ab0c8f2944522..47f13094d0443 100644
--- a/llvm/test/MC/AArch64/SVE2/srshl.s
+++ b/llvm/test/MC/AArch64/SVE2/srshl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/srshlr.s b/llvm/test/MC/AArch64/SVE2/srshlr.s
index 822a4b82e2fb8..c0ad547087445 100644
--- a/llvm/test/MC/AArch64/SVE2/srshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/srshlr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/srshr.s b/llvm/test/MC/AArch64/SVE2/srshr.s
index 34955fed55d3e..ba96cdacc2f61 100644
--- a/llvm/test/MC/AArch64/SVE2/srshr.s
+++ b/llvm/test/MC/AArch64/SVE2/srshr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/srsra.s b/llvm/test/MC/AArch64/SVE2/srsra.s
index 2ac7fa78736a3..920f7b856ae6b 100644
--- a/llvm/test/MC/AArch64/SVE2/srsra.s
+++ b/llvm/test/MC/AArch64/SVE2/srsra.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sshllb.s b/llvm/test/MC/AArch64/SVE2/sshllb.s
index 14824c583f5cd..8c6b54c98fa92 100644
--- a/llvm/test/MC/AArch64/SVE2/sshllb.s
+++ b/llvm/test/MC/AArch64/SVE2/sshllb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/sshllt.s b/llvm/test/MC/AArch64/SVE2/sshllt.s
index 88bf9dee6fbcb..614d86b6dcb9d 100644
--- a/llvm/test/MC/AArch64/SVE2/sshllt.s
+++ b/llvm/test/MC/AArch64/SVE2/sshllt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssra.s b/llvm/test/MC/AArch64/SVE2/ssra.s
index 5daeb9a667e3a..2d23095b1c936 100644
--- a/llvm/test/MC/AArch64/SVE2/ssra.s
+++ b/llvm/test/MC/AArch64/SVE2/ssra.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssublb.s b/llvm/test/MC/AArch64/SVE2/ssublb.s
index 3ccc3abf52dc1..6455413c7afd3 100644
--- a/llvm/test/MC/AArch64/SVE2/ssublb.s
+++ b/llvm/test/MC/AArch64/SVE2/ssublb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssublbt.s b/llvm/test/MC/AArch64/SVE2/ssublbt.s
index 0dff839ce0a77..155d4a0952d65 100644
--- a/llvm/test/MC/AArch64/SVE2/ssublbt.s
+++ b/llvm/test/MC/AArch64/SVE2/ssublbt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssublt.s b/llvm/test/MC/AArch64/SVE2/ssublt.s
index ffd7d54cab975..97dfc5804a1ef 100644
--- a/llvm/test/MC/AArch64/SVE2/ssublt.s
+++ b/llvm/test/MC/AArch64/SVE2/ssublt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssubltb.s b/llvm/test/MC/AArch64/SVE2/ssubltb.s
index 590fc44acf801..10428d5531d2a 100644
--- a/llvm/test/MC/AArch64/SVE2/ssubltb.s
+++ b/llvm/test/MC/AArch64/SVE2/ssubltb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssubwb.s b/llvm/test/MC/AArch64/SVE2/ssubwb.s
index be3a41e91322e..a99c15862b5f8 100644
--- a/llvm/test/MC/AArch64/SVE2/ssubwb.s
+++ b/llvm/test/MC/AArch64/SVE2/ssubwb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ssubwt.s b/llvm/test/MC/AArch64/SVE2/ssubwt.s
index 1894548a6d3f9..e5693e1eddaa3 100644
--- a/llvm/test/MC/AArch64/SVE2/ssubwt.s
+++ b/llvm/test/MC/AArch64/SVE2/ssubwt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/stnt1b.s b/llvm/test/MC/AArch64/SVE2/stnt1b.s
index cab8a6b7f30e2..1c3f2f8109fa2 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1b.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1b.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/stnt1d.s b/llvm/test/MC/AArch64/SVE2/stnt1d.s
index 462b8bce0104a..3f8d5ac7000b7 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1d.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1d.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/stnt1h.s b/llvm/test/MC/AArch64/SVE2/stnt1h.s
index 07c9c328636ba..fe5c58b8fa9fc 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1h.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1h.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/stnt1w.s b/llvm/test/MC/AArch64/SVE2/stnt1w.s
index 90d4c8e6e142a..86675f2161d97 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1w.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1w.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/subhnb.s b/llvm/test/MC/AArch64/SVE2/subhnb.s
index 4b90166a5b048..3dda8308bb9b2 100644
--- a/llvm/test/MC/AArch64/SVE2/subhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/subhnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/subhnt.s b/llvm/test/MC/AArch64/SVE2/subhnt.s
index 624147e66b829..271be5278eed6 100644
--- a/llvm/test/MC/AArch64/SVE2/subhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/subhnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/suqadd.s b/llvm/test/MC/AArch64/SVE2/suqadd.s
index 016275da2e0c2..eabbe25d749a9 100644
--- a/llvm/test/MC/AArch64/SVE2/suqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/suqadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/tbl.s b/llvm/test/MC/AArch64/SVE2/tbl.s
index 6cb122ed353f0..e8a77196fd5f5 100644
--- a/llvm/test/MC/AArch64/SVE2/tbl.s
+++ b/llvm/test/MC/AArch64/SVE2/tbl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/tbx.s b/llvm/test/MC/AArch64/SVE2/tbx.s
index 8e49185873447..200f5c9a13db4 100644
--- a/llvm/test/MC/AArch64/SVE2/tbx.s
+++ b/llvm/test/MC/AArch64/SVE2/tbx.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uaba.s b/llvm/test/MC/AArch64/SVE2/uaba.s
index f714902fabe5f..76226ca90a8d1 100644
--- a/llvm/test/MC/AArch64/SVE2/uaba.s
+++ b/llvm/test/MC/AArch64/SVE2/uaba.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uabalb.s b/llvm/test/MC/AArch64/SVE2/uabalb.s
index b2cda012973f6..790ff380f6f27 100644
--- a/llvm/test/MC/AArch64/SVE2/uabalb.s
+++ b/llvm/test/MC/AArch64/SVE2/uabalb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uabalt.s b/llvm/test/MC/AArch64/SVE2/uabalt.s
index f49dede472ae9..1a6fb8a7fb3cf 100644
--- a/llvm/test/MC/AArch64/SVE2/uabalt.s
+++ b/llvm/test/MC/AArch64/SVE2/uabalt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uabdlb.s b/llvm/test/MC/AArch64/SVE2/uabdlb.s
index 7782fdb9fec70..a7a2bace3a9c1 100644
--- a/llvm/test/MC/AArch64/SVE2/uabdlb.s
+++ b/llvm/test/MC/AArch64/SVE2/uabdlb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uabdlt.s b/llvm/test/MC/AArch64/SVE2/uabdlt.s
index 118c286c18739..b867b694bf101 100644
--- a/llvm/test/MC/AArch64/SVE2/uabdlt.s
+++ b/llvm/test/MC/AArch64/SVE2/uabdlt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uadalp.s b/llvm/test/MC/AArch64/SVE2/uadalp.s
index 6aadb95cb3288..0bf6fe23019de 100644
--- a/llvm/test/MC/AArch64/SVE2/uadalp.s
+++ b/llvm/test/MC/AArch64/SVE2/uadalp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uaddlb.s b/llvm/test/MC/AArch64/SVE2/uaddlb.s
index 6804540fdf0d7..d8e2b2bc5e3f9 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddlb.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddlb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uaddlt.s b/llvm/test/MC/AArch64/SVE2/uaddlt.s
index 366f2c42ed4d6..fe41b0e59db94 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddlt.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddlt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uaddwb.s b/llvm/test/MC/AArch64/SVE2/uaddwb.s
index d07d779b1c27c..52f2ead72f9c1 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddwb.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddwb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uaddwt.s b/llvm/test/MC/AArch64/SVE2/uaddwt.s
index 6520bd449187f..956d84da9c1e0 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddwt.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddwt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uhadd.s b/llvm/test/MC/AArch64/SVE2/uhadd.s
index bc10eb247f95c..f2e60f4a02545 100644
--- a/llvm/test/MC/AArch64/SVE2/uhadd.s
+++ b/llvm/test/MC/AArch64/SVE2/uhadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uhsub.s b/llvm/test/MC/AArch64/SVE2/uhsub.s
index 37aa31f81ee3e..8fd485b963cc7 100644
--- a/llvm/test/MC/AArch64/SVE2/uhsub.s
+++ b/llvm/test/MC/AArch64/SVE2/uhsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uhsubr.s b/llvm/test/MC/AArch64/SVE2/uhsubr.s
index 512a381f10c64..e221eea98f166 100644
--- a/llvm/test/MC/AArch64/SVE2/uhsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/uhsubr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umaxp.s b/llvm/test/MC/AArch64/SVE2/umaxp.s
index fd8c213039fea..19dd68af7203e 100644
--- a/llvm/test/MC/AArch64/SVE2/umaxp.s
+++ b/llvm/test/MC/AArch64/SVE2/umaxp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uminp.s b/llvm/test/MC/AArch64/SVE2/uminp.s
index b5ce206d91333..06a9126e0a175 100644
--- a/llvm/test/MC/AArch64/SVE2/uminp.s
+++ b/llvm/test/MC/AArch64/SVE2/uminp.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umlalb.s b/llvm/test/MC/AArch64/SVE2/umlalb.s
index 4dcbe87685413..c4b7bd38ca210 100644
--- a/llvm/test/MC/AArch64/SVE2/umlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/umlalb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umlalt.s b/llvm/test/MC/AArch64/SVE2/umlalt.s
index 9a8573f7b8dbd..d3083adad92a0 100644
--- a/llvm/test/MC/AArch64/SVE2/umlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/umlalt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umlslb.s b/llvm/test/MC/AArch64/SVE2/umlslb.s
index 194a2c1fae17b..4347f7bb9e242 100644
--- a/llvm/test/MC/AArch64/SVE2/umlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/umlslb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umlslt.s b/llvm/test/MC/AArch64/SVE2/umlslt.s
index 24e7f4fe8a10e..df80e46be5b16 100644
--- a/llvm/test/MC/AArch64/SVE2/umlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/umlslt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umulh.s b/llvm/test/MC/AArch64/SVE2/umulh.s
index 38d7b258872a3..293e65ce5ecf0 100644
--- a/llvm/test/MC/AArch64/SVE2/umulh.s
+++ b/llvm/test/MC/AArch64/SVE2/umulh.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umullb.s b/llvm/test/MC/AArch64/SVE2/umullb.s
index 13ffcf520ecdd..45b16db630ef5 100644
--- a/llvm/test/MC/AArch64/SVE2/umullb.s
+++ b/llvm/test/MC/AArch64/SVE2/umullb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/umullt.s b/llvm/test/MC/AArch64/SVE2/umullt.s
index 72d9c9448d17d..08af5e5615b52 100644
--- a/llvm/test/MC/AArch64/SVE2/umullt.s
+++ b/llvm/test/MC/AArch64/SVE2/umullt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqadd.s b/llvm/test/MC/AArch64/SVE2/uqadd.s
index 54d96163994ed..f8fb061659206 100644
--- a/llvm/test/MC/AArch64/SVE2/uqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/uqadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqrshl.s b/llvm/test/MC/AArch64/SVE2/uqrshl.s
index 8dde5efb5e244..5af61b5034ce5 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshl.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqrshlr.s b/llvm/test/MC/AArch64/SVE2/uqrshlr.s
index eb6aabf6a014b..5da4bed0b34aa 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshlr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqrshrnb.s b/llvm/test/MC/AArch64/SVE2/uqrshrnb.s
index a10b02f097b35..08f06a664e9d3 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshrnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqrshrnt.s b/llvm/test/MC/AArch64/SVE2/uqrshrnt.s
index 6eaf48440f78a..59da1d1bdae1a 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshrnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqshl.s b/llvm/test/MC/AArch64/SVE2/uqshl.s
index 36e8c6e11757a..1f10b02264b94 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshl.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqshlr.s b/llvm/test/MC/AArch64/SVE2/uqshlr.s
index eaadc0ba72157..a39236abc8177 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshlr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqshrnb.s b/llvm/test/MC/AArch64/SVE2/uqshrnb.s
index 9f04d2346da08..4bae0c1216d37 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshrnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqshrnt.s b/llvm/test/MC/AArch64/SVE2/uqshrnt.s
index dc151a2c786c7..b29bc402918b1 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshrnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqsub.s b/llvm/test/MC/AArch64/SVE2/uqsub.s
index 0df03aa2f30d0..9e66f1befa9ed 100644
--- a/llvm/test/MC/AArch64/SVE2/uqsub.s
+++ b/llvm/test/MC/AArch64/SVE2/uqsub.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqsubr.s b/llvm/test/MC/AArch64/SVE2/uqsubr.s
index 64f95c72d8612..6da4c3296f5c5 100644
--- a/llvm/test/MC/AArch64/SVE2/uqsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/uqsubr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqxtnb.s b/llvm/test/MC/AArch64/SVE2/uqxtnb.s
index e0361addc8eec..cf55b06c94481 100644
--- a/llvm/test/MC/AArch64/SVE2/uqxtnb.s
+++ b/llvm/test/MC/AArch64/SVE2/uqxtnb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/uqxtnt.s b/llvm/test/MC/AArch64/SVE2/uqxtnt.s
index 73dfc27a0fda0..0ae286e44e44f 100644
--- a/llvm/test/MC/AArch64/SVE2/uqxtnt.s
+++ b/llvm/test/MC/AArch64/SVE2/uqxtnt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/urecpe.s b/llvm/test/MC/AArch64/SVE2/urecpe.s
index 3687e6f6068ba..079a866f32d79 100644
--- a/llvm/test/MC/AArch64/SVE2/urecpe.s
+++ b/llvm/test/MC/AArch64/SVE2/urecpe.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/urhadd.s b/llvm/test/MC/AArch64/SVE2/urhadd.s
index c620181f4b51e..0310226897ee9 100644
--- a/llvm/test/MC/AArch64/SVE2/urhadd.s
+++ b/llvm/test/MC/AArch64/SVE2/urhadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/urshl.s b/llvm/test/MC/AArch64/SVE2/urshl.s
index 9e057fb261156..deb4a0ef743e0 100644
--- a/llvm/test/MC/AArch64/SVE2/urshl.s
+++ b/llvm/test/MC/AArch64/SVE2/urshl.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/urshlr.s b/llvm/test/MC/AArch64/SVE2/urshlr.s
index 170eb4a7aeb64..de308e771557a 100644
--- a/llvm/test/MC/AArch64/SVE2/urshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/urshlr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/urshr.s b/llvm/test/MC/AArch64/SVE2/urshr.s
index b06edfeb9b792..c7c012847efd4 100644
--- a/llvm/test/MC/AArch64/SVE2/urshr.s
+++ b/llvm/test/MC/AArch64/SVE2/urshr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ursqrte.s b/llvm/test/MC/AArch64/SVE2/ursqrte.s
index a6280e5df44d4..ce90590d73e12 100644
--- a/llvm/test/MC/AArch64/SVE2/ursqrte.s
+++ b/llvm/test/MC/AArch64/SVE2/ursqrte.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ursra.s b/llvm/test/MC/AArch64/SVE2/ursra.s
index dfa1e8454962b..6ff57df4e0329 100644
--- a/llvm/test/MC/AArch64/SVE2/ursra.s
+++ b/llvm/test/MC/AArch64/SVE2/ursra.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ushllb.s b/llvm/test/MC/AArch64/SVE2/ushllb.s
index c67581a597e51..9d894a608c1ef 100644
--- a/llvm/test/MC/AArch64/SVE2/ushllb.s
+++ b/llvm/test/MC/AArch64/SVE2/ushllb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/ushllt.s b/llvm/test/MC/AArch64/SVE2/ushllt.s
index a3be73226c5cb..1e387f5d02bf2 100644
--- a/llvm/test/MC/AArch64/SVE2/ushllt.s
+++ b/llvm/test/MC/AArch64/SVE2/ushllt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/usqadd.s b/llvm/test/MC/AArch64/SVE2/usqadd.s
index 9bec555dcbd6b..e335a6ffe2ef7 100644
--- a/llvm/test/MC/AArch64/SVE2/usqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/usqadd.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/usra.s b/llvm/test/MC/AArch64/SVE2/usra.s
index 6e7c35ad415f7..4397f3fda6170 100644
--- a/llvm/test/MC/AArch64/SVE2/usra.s
+++ b/llvm/test/MC/AArch64/SVE2/usra.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/usublb.s b/llvm/test/MC/AArch64/SVE2/usublb.s
index a985e38af659d..08711916f84f0 100644
--- a/llvm/test/MC/AArch64/SVE2/usublb.s
+++ b/llvm/test/MC/AArch64/SVE2/usublb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/usublt.s b/llvm/test/MC/AArch64/SVE2/usublt.s
index 9a7f23d6a5427..8da50e51aeb71 100644
--- a/llvm/test/MC/AArch64/SVE2/usublt.s
+++ b/llvm/test/MC/AArch64/SVE2/usublt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/usubwb.s b/llvm/test/MC/AArch64/SVE2/usubwb.s
index d1ebf20c725ce..b04b015a5b13b 100644
--- a/llvm/test/MC/AArch64/SVE2/usubwb.s
+++ b/llvm/test/MC/AArch64/SVE2/usubwb.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/usubwt.s b/llvm/test/MC/AArch64/SVE2/usubwt.s
index 2b3874ac89531..cf19beeed0158 100644
--- a/llvm/test/MC/AArch64/SVE2/usubwt.s
+++ b/llvm/test/MC/AArch64/SVE2/usubwt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/whilege.s b/llvm/test/MC/AArch64/SVE2/whilege.s
index a506794f449d7..8b7dee797cb21 100644
--- a/llvm/test/MC/AArch64/SVE2/whilege.s
+++ b/llvm/test/MC/AArch64/SVE2/whilege.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/whilegt.s b/llvm/test/MC/AArch64/SVE2/whilegt.s
index 3f307bcc56a0e..2f17c6138e1fd 100644
--- a/llvm/test/MC/AArch64/SVE2/whilegt.s
+++ b/llvm/test/MC/AArch64/SVE2/whilegt.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/whilehi.s b/llvm/test/MC/AArch64/SVE2/whilehi.s
index 8e6272dd0239d..7400676a1aac0 100644
--- a/llvm/test/MC/AArch64/SVE2/whilehi.s
+++ b/llvm/test/MC/AArch64/SVE2/whilehi.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/whilehs.s b/llvm/test/MC/AArch64/SVE2/whilehs.s
index 1e01a1964be45..b736580b748e1 100644
--- a/llvm/test/MC/AArch64/SVE2/whilehs.s
+++ b/llvm/test/MC/AArch64/SVE2/whilehs.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/whilerw.s b/llvm/test/MC/AArch64/SVE2/whilerw.s
index b4a5bd0962f3f..e90f7b13f956b 100644
--- a/llvm/test/MC/AArch64/SVE2/whilerw.s
+++ b/llvm/test/MC/AArch64/SVE2/whilerw.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/whilewr.s b/llvm/test/MC/AArch64/SVE2/whilewr.s
index 588d1b2262b34..7287fb6898307 100644
--- a/llvm/test/MC/AArch64/SVE2/whilewr.s
+++ b/llvm/test/MC/AArch64/SVE2/whilewr.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/SVE2/xar.s b/llvm/test/MC/AArch64/SVE2/xar.s
index 7389df33754ea..f91a8045d9deb 100644
--- a/llvm/test/MC/AArch64/SVE2/xar.s
+++ b/llvm/test/MC/AArch64/SVE2/xar.s
@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
-// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
diff --git a/llvm/test/MC/AArch64/adrp-annotation.s b/llvm/test/MC/AArch64/adrp-annotation.s
index d3a752bd23eda..af22804e06d58 100644
--- a/llvm/test/MC/AArch64/adrp-annotation.s
+++ b/llvm/test/MC/AArch64/adrp-annotation.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple aarch64-apple-ios %s -filetype=obj -o %t.o
-; RUN: llvm-objdump -macho -d %t.o | FileCheck %s
+; RUN: llvm-objdump --macho -d %t.o | FileCheck %s
 
   .data_region
   .space 0x4124
diff --git a/llvm/test/MC/AArch64/arm32-elf-relocs.s b/llvm/test/MC/AArch64/arm32-elf-relocs.s
index 33e63c2993d02..a4d2ebd80e1eb 100644
--- a/llvm/test/MC/AArch64/arm32-elf-relocs.s
+++ b/llvm/test/MC/AArch64/arm32-elf-relocs.s
@@ -3,7 +3,7 @@
 // RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \
 // RUN:    -o - < %s | FileCheck --check-prefix=CHECK-ENCODING %s
 // RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj < %s | \
-// RUN:   llvm-objdump -triple=arm64-linux-gnu - -r | \
+// RUN:   llvm-objdump --triple=arm64-linux-gnu - -r | \
 // RUN:   FileCheck %s --check-prefix=CHECK-OBJ-ILP32
 
    add x0, x2, #:lo12:sym
diff --git a/llvm/test/MC/AArch64/arm64-compact-unwind-fallback.s b/llvm/test/MC/AArch64/arm64-compact-unwind-fallback.s
index 2c533ea26a10b..f4bb9147464d7 100644
--- a/llvm/test/MC/AArch64/arm64-compact-unwind-fallback.s
+++ b/llvm/test/MC/AArch64/arm64-compact-unwind-fallback.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -triple=arm64-apple-ios -filetype=obj %s -o %t
-// RUN: llvm-objdump -macho -unwind-info -dwarf=frames %t | FileCheck %s
+// RUN: llvm-objdump --macho --unwind-info --dwarf=frames %t | FileCheck %s
 
 // Check that we fallback on DWARF instead of asserting.
 
diff --git a/llvm/test/MC/AArch64/arm64-elf-relocs.s b/llvm/test/MC/AArch64/arm64-elf-relocs.s
index 594837449c06c..bba1d440c343d 100644
--- a/llvm/test/MC/AArch64/arm64-elf-relocs.s
+++ b/llvm/test/MC/AArch64/arm64-elf-relocs.s
@@ -2,7 +2,7 @@
 // RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - < %s | \
 // RUN:   FileCheck --check-prefix=CHECK-ENCODING %s
 // RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \
-// RUN:   llvm-objdump -triple=arm64-linux-gnu - -r | \
+// RUN:   llvm-objdump --triple=arm64-linux-gnu - -r | \
 // RUN:   FileCheck %s --check-prefix=CHECK-OBJ-LP64
 
    add x0, x2, #:lo12:sym
diff --git a/llvm/test/MC/AArch64/arm64-leaf-compact-unwind.s b/llvm/test/MC/AArch64/arm64-leaf-compact-unwind.s
index 7cbab05945369..258b259a3df8b 100644
--- a/llvm/test/MC/AArch64/arm64-leaf-compact-unwind.s
+++ b/llvm/test/MC/AArch64/arm64-leaf-compact-unwind.s
@@ -4,7 +4,7 @@
 //
 // rdar://13070556
 
-// FIXME: we should add compact unwind support to llvm-objdump -unwind-info
+// FIXME: we should add compact unwind support to llvm-objdump --unwind-info
 
 // CHECK:      Section {
 // CHECK:        Index: 1
diff --git a/llvm/test/MC/AArch64/coff-relocations.s b/llvm/test/MC/AArch64/coff-relocations.s
index 965955809dab3..c37b2bb7c3cc0 100644
--- a/llvm/test/MC/AArch64/coff-relocations.s
+++ b/llvm/test/MC/AArch64/coff-relocations.s
@@ -1,6 +1,6 @@
 ; RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
 ; RUN: llvm-readobj -r %t.obj | FileCheck %s
-; RUN: llvm-objdump -d %t.obj | FileCheck %s -check-prefix DISASM
+; RUN: llvm-objdump -d %t.obj | FileCheck %s --check-prefix=DISASM
 
 ; IMAGE_REL_ARM64_ADDR32
 .Linfo_foo:
diff --git a/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s b/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
index 32632abd19d86..f3e31b224c21c 100644
--- a/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
+++ b/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -triple=aarch64-darwin -filetype=obj %s -o - | \
-// RUN:   llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
+// RUN:   llvm-objdump -r -d - | FileCheck --check-prefix=OBJ %s
 
 // OBJ-LABEL: Disassembly of section __TEXT,__text:
 
diff --git a/llvm/test/MC/AArch64/elf-reloc-addsubimm.s b/llvm/test/MC/AArch64/elf-reloc-addsubimm.s
index f4d8d9c7784f0..deecd20d59a87 100644
--- a/llvm/test/MC/AArch64/elf-reloc-addsubimm.s
+++ b/llvm/test/MC/AArch64/elf-reloc-addsubimm.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
-// RUN:   llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
+// RUN:   llvm-objdump -r -d - | FileCheck --check-prefix=OBJ %s
 
 // OBJ-LABEL: Disassembly of section .text:
 
diff --git a/llvm/test/MC/AArch64/optional-hash.s b/llvm/test/MC/AArch64/optional-hash.s
index 6573d3e8001ca..3a1cbe1524f8b 100644
--- a/llvm/test/MC/AArch64/optional-hash.s
+++ b/llvm/test/MC/AArch64/optional-hash.s
@@ -1,6 +1,6 @@
 // PR18929
 // RUN: llvm-mc < %s -triple=aarch64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \
-// RUN: | llvm-objdump --disassemble -arch=arm64 - | FileCheck %s
+// RUN: | llvm-objdump -d --arch=arm64 - | FileCheck %s
 
     .text
 // CHECK: cmp w0, #123
diff --git a/llvm/test/MC/AMDGPU/branch-comment.s b/llvm/test/MC/AMDGPU/branch-comment.s
index 32c82b672aef3..443f0b3085809 100644
--- a/llvm/test/MC/AMDGPU/branch-comment.s
+++ b/llvm/test/MC/AMDGPU/branch-comment.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -disassemble -mcpu=fiji - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -d --mcpu=fiji - | FileCheck %s --check-prefix=BIN
 
 // FIXME: Immediate operands to sopp_br instructions are currently scaled by a
 // factor of 4, are unsigned, are always PC relative, don't accept most
diff --git a/llvm/test/MC/AMDGPU/data.s b/llvm/test/MC/AMDGPU/data.s
index 2800b672483e5..e799553dd6896 100644
--- a/llvm/test/MC/AMDGPU/data.s
+++ b/llvm/test/MC/AMDGPU/data.s
@@ -1,6 +1,6 @@
 // We check that unrecognized opcodes are disassembled by llvm-objdump as data using the .long directive 
 // and any trailing bytes are disassembled using the .byte directive
-// RUN: llvm-mc -filetype=obj -triple=amdgcn--amdpal -mcpu=gfx900 -show-encoding %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple=amdgcn--amdpal -mcpu=gfx900 -show-encoding %s | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s
 
 .text
         v_mov_b32     v7, s24
diff --git a/llvm/test/MC/AMDGPU/labels-branch-gfx9.s b/llvm/test/MC/AMDGPU/labels-branch-gfx9.s
index c187f6d85d98d..8bf6b968a7091 100644
--- a/llvm/test/MC/AMDGPU/labels-branch-gfx9.s
+++ b/llvm/test/MC/AMDGPU/labels-branch-gfx9.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
 
 loop_start:
 
diff --git a/llvm/test/MC/AMDGPU/labels-branch.s b/llvm/test/MC/AMDGPU/labels-branch.s
index e71c767ae95dc..7315f0d54053b 100644
--- a/llvm/test/MC/AMDGPU/labels-branch.s
+++ b/llvm/test/MC/AMDGPU/labels-branch.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -disassemble -mcpu=fiji - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -d --mcpu=fiji - | FileCheck %s --check-prefix=BIN
 
 loop_start:
 s_branch loop_start
diff --git a/llvm/test/MC/AMDGPU/offsetbug_once.s b/llvm/test/MC/AMDGPU/offsetbug_once.s
index 646c61f68b503..f357c40f3c948 100644
--- a/llvm/test/MC/AMDGPU/offsetbug_once.s
+++ b/llvm/test/MC/AMDGPU/offsetbug_once.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
 	s_getpc_b64 s[0:1]
 	s_cbranch_vccnz BB0_1
 // GFX10: s_cbranch_vccnz BB0_1           ; encoding: [A,A,0x87,0xbf]
diff --git a/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s b/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
index ad24cb52e5f98..875ea44b225cf 100644
--- a/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
+++ b/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
 	s_getpc_b64 s[0:1]
 	s_cbranch_vccnz BB0_1
 // GFX10: s_cbranch_vccnz BB0_1           ; encoding: [A,A,0x87,0xbf]
diff --git a/llvm/test/MC/AMDGPU/offsetbug_twice.s b/llvm/test/MC/AMDGPU/offsetbug_twice.s
index 60480e11aa212..1bcc1adc25816 100644
--- a/llvm/test/MC/AMDGPU/offsetbug_twice.s
+++ b/llvm/test/MC/AMDGPU/offsetbug_twice.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
 	s_getpc_b64 s[0:1]
 	s_cbranch_vccnz BB0_2
 // GFX10: s_cbranch_vccnz BB0_2           ; encoding: [A,A,0x87,0xbf]
diff --git a/llvm/test/MC/AMDGPU/s_endpgm.s b/llvm/test/MC/AMDGPU/s_endpgm.s
index 49b3323e7e37d..6a9d3ea285faa 100644
--- a/llvm/test/MC/AMDGPU/s_endpgm.s
+++ b/llvm/test/MC/AMDGPU/s_endpgm.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc -arch=amdgcn %s | FileCheck -strict-whitespace %s -check-prefix=WHITESPACE
 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
 
 // WHITESPACE: s_endpgm{{$}}
 // GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
diff --git a/llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s b/llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s
index 1d6735320007d..ca78f2acc2894 100644
--- a/llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s
+++ b/llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - \
-# RUN:   | llvm-objdump -no-show-raw-insn -triple armv7 -disassemble - | FileCheck %s
+# RUN:   | llvm-objdump --no-show-raw-insn --triple=armv7 -d - | FileCheck %s
 
 # On ARM each instruction is 4 bytes long so padding for individual
 # instructions should not be inserted. However, for bundle-locked groups
diff --git a/llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s b/llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s
index 341358b9db170..c01c8c178afeb 100644
--- a/llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s
+++ b/llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - \
-# RUN:   | llvm-objdump -no-show-raw-insn -triple armv7 -disassemble - | FileCheck %s
+# RUN:   | llvm-objdump --no-show-raw-insn --triple=armv7 -d - | FileCheck %s
 
 	.syntax unified
 	.text
diff --git a/llvm/test/MC/ARM/AlignedBundling/subtarget-change.s b/llvm/test/MC/ARM/AlignedBundling/subtarget-change.s
index a06b83899c34d..81c9b25a3a5f7 100644
--- a/llvm/test/MC/ARM/AlignedBundling/subtarget-change.s
+++ b/llvm/test/MC/ARM/AlignedBundling/subtarget-change.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - \
-# RUN:   | llvm-objdump -no-show-raw-insn -triple armv7 -disassemble - | FileCheck %s
+# RUN:   | llvm-objdump --no-show-raw-insn --triple=armv7 -d - | FileCheck %s
 
         # We can switch subtargets with .arch outside of a bundle
         .syntax unified
diff --git a/llvm/test/MC/ARM/Windows/mov32t-range.s b/llvm/test/MC/ARM/Windows/mov32t-range.s
index fef8ff2aca7ab..5b29e75b53d33 100644
--- a/llvm/test/MC/ARM/Windows/mov32t-range.s
+++ b/llvm/test/MC/ARM/Windows/mov32t-range.s
@@ -2,7 +2,7 @@
 @ RUN:   | llvm-readobj -r - | FileCheck -check-prefix CHECK-RELOCATIONS %s
 
 @ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
-@ RUN:   | llvm-objdump -d - | FileCheck -check-prefix CHECK-ENCODING %s
+@ RUN:   | llvm-objdump -d - | FileCheck --check-prefix=CHECK-ENCODING %s
 
 	.syntax unified
 	.thumb
diff --git a/llvm/test/MC/ARM/align_arm_2_thumb.s b/llvm/test/MC/ARM/align_arm_2_thumb.s
index 120e96480b5cb..553dc89f2a360 100644
--- a/llvm/test/MC/ARM/align_arm_2_thumb.s
+++ b/llvm/test/MC/ARM/align_arm_2_thumb.s
@@ -1,8 +1,8 @@
 @ RUN: llvm-mc -triple armv7-none-linux -filetype=obj -o %t.o %s
-@ RUN: llvm-objdump -triple thumbv7-none-linux -d %t.o | FileCheck --check-prefix=ARM_2_THUMB %s
+@ RUN: llvm-objdump --triple=thumbv7-none-linux -d %t.o | FileCheck --check-prefix=ARM_2_THUMB %s
 
 @ RUN: llvm-mc -triple armv7-apple-darwin -filetype=obj -o %t_darwin.o %s
-@ RUN: llvm-objdump -triple thumbv7-apple-darwin -d %t_darwin.o | FileCheck --check-prefix=ARM_2_THUMB %s
+@ RUN: llvm-objdump --triple=thumbv7-apple-darwin -d %t_darwin.o | FileCheck --check-prefix=ARM_2_THUMB %s
 
 .syntax unified
 .code 16
diff --git a/llvm/test/MC/ARM/align_thumb_2_arm.s b/llvm/test/MC/ARM/align_thumb_2_arm.s
index 328bfabce65c3..693a3ab5d6c91 100644
--- a/llvm/test/MC/ARM/align_thumb_2_arm.s
+++ b/llvm/test/MC/ARM/align_thumb_2_arm.s
@@ -1,8 +1,8 @@
 @ RUN: llvm-mc -triple thumbv7-none-linux -filetype=obj -o %t.o %s
-@ RUN: llvm-objdump -triple armv7-none-linux -d %t.o | FileCheck --check-prefix=THUMB_2_ARM %s
+@ RUN: llvm-objdump --triple=armv7-none-linux -d %t.o | FileCheck --check-prefix=THUMB_2_ARM %s
 
 @ RUN: llvm-mc -triple thumbv7-apple-darwin -filetype=obj -o %t_darwin.o %s
-@ RUN: llvm-objdump -triple armv7-apple-darwin -d %t_darwin.o | FileCheck --check-prefix=THUMB_2_ARM %s
+@ RUN: llvm-objdump --triple=armv7-apple-darwin -d %t_darwin.o | FileCheck --check-prefix=THUMB_2_ARM %s
 
 .syntax unified
 .code 32
diff --git a/llvm/test/MC/ARM/aligned-blx.s b/llvm/test/MC/ARM/aligned-blx.s
index 39f335934c4b0..f1e387c434195 100644
--- a/llvm/test/MC/ARM/aligned-blx.s
+++ b/llvm/test/MC/ARM/aligned-blx.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc -triple thumbv7-apple-ios -filetype=obj %s -o %t
-@ RUN: llvm-objdump -macho -d %t | FileCheck %s
+@ RUN: llvm-objdump --macho -d %t | FileCheck %s
 
         @ Size: 2 bytes
         .thumb_func _f1
diff --git a/llvm/test/MC/ARM/assembler-fill.s b/llvm/test/MC/ARM/assembler-fill.s
index 8c7dfbff0a6b9..cb5f2d9e5721b 100644
--- a/llvm/test/MC/ARM/assembler-fill.s
+++ b/llvm/test/MC/ARM/assembler-fill.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc --triple=thumbv7eb-linux-gnueabihf %s -filetype=obj | llvm-objdump -triple=thumbv7eb-linux-gnueabihf -s - | FileCheck %s
+// RUN: llvm-mc --triple=thumbv7eb-linux-gnueabihf %s -filetype=obj | llvm-objdump --triple=thumbv7eb-linux-gnueabihf -s - | FileCheck %s
 
 // CHECK: Contents of section .text
 // CHECK-NEXT: 0000 d000bf00 
diff --git a/llvm/test/MC/ARM/branch-disassemble.s b/llvm/test/MC/ARM/branch-disassemble.s
index 5380a1d0b9e41..33fedc3bb685c 100644
--- a/llvm/test/MC/ARM/branch-disassemble.s
+++ b/llvm/test/MC/ARM/branch-disassemble.s
@@ -1,9 +1,9 @@
 @ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7-arm-none-eabi -filetype obj -o - %s \
-@ RUN:   | llvm-objdump -mcpu=cortex-a9 -triple armv7-arm-none-eabi -d - \
+@ RUN:   | llvm-objdump --mcpu=cortex-a9 --triple=armv7-arm-none-eabi -d - \
 @ RUN:   | FileCheck %s -check-prefix CHECK-ARM
 
 @ RUN: llvm-mc -mcpu=cortex-m3 -triple thumbv7m-arm-none-eabi -filetype obj -o - %s \
-@ RUN:   | llvm-objdump -mcpu=cortex-m3 -triple thumbv7m-arm-none-eabi -d - \
+@ RUN:   | llvm-objdump --mcpu=cortex-m3 --triple=thumbv7m-arm-none-eabi -d - \
 @ RUN:   | FileCheck %s -check-prefix CHECK-THUMB
 
 b.w .Lbranch
diff --git a/llvm/test/MC/ARM/cmp-immediate-fixup.s b/llvm/test/MC/ARM/cmp-immediate-fixup.s
index e21d5c20ccda4..0f1ba5e107c6a 100644
--- a/llvm/test/MC/ARM/cmp-immediate-fixup.s
+++ b/llvm/test/MC/ARM/cmp-immediate-fixup.s
@@ -1,6 +1,6 @@
 @ PR18931
 @ RUN: llvm-mc < %s -triple=arm-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-objdump --disassemble -arch=arm - | FileCheck %s
+@ RUN: | llvm-objdump -d --arch=arm - | FileCheck %s
 
     .text
 @ CHECK: cmp r2, #1
diff --git a/llvm/test/MC/ARM/cmp-immediate-fixup2.s b/llvm/test/MC/ARM/cmp-immediate-fixup2.s
index c091145523c03..de0941eac2730 100644
--- a/llvm/test/MC/ARM/cmp-immediate-fixup2.s
+++ b/llvm/test/MC/ARM/cmp-immediate-fixup2.s
@@ -1,6 +1,6 @@
 @ PR18931
 @ RUN: llvm-mc < %s -triple=arm-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-objdump --disassemble -arch=arm - | FileCheck %s
+@ RUN: | llvm-objdump -d --arch=arm - | FileCheck %s
 
     .text
 @ CHECK: cmp r2, #0
diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s
index 20fd7f16a07a6..73211b9ca9019 100644
--- a/llvm/test/MC/ARM/coff-relocations.s
+++ b/llvm/test/MC/ARM/coff-relocations.s
@@ -2,7 +2,7 @@
 @ RUN:   | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-RELOCATION
 
 @ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \
-@ RUN:   | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-ENCODING
+@ RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-ENCODING
 
 	.syntax unified
 	.text
diff --git a/llvm/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s b/llvm/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s
index 7de9d11262bb6..98c8c95e72006 100644
--- a/llvm/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s
+++ b/llvm/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp -dwarf-version 2 2>&1 | FileCheck -check-prefix MESSAGES %s
 // RUN: llvm-dwarfdump -a %t | FileCheck -check-prefix DWARF %s
-// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s
+// RUN: llvm-objdump -r %t | FileCheck --check-prefix=RELOC %s
 
   .section .text, "ax"
 a:
diff --git a/llvm/test/MC/ARM/dwarf-asm-no-code.s b/llvm/test/MC/ARM/dwarf-asm-no-code.s
index dc1eb95e745d8..1a009e8a6ed35 100644
--- a/llvm/test/MC/ARM/dwarf-asm-no-code.s
+++ b/llvm/test/MC/ARM/dwarf-asm-no-code.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp
 // RUN: llvm-dwarfdump -v %t | FileCheck -check-prefix DWARF %s
-// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s
+// RUN: llvm-objdump -r %t | FileCheck --check-prefix=RELOC %s
 
 // If there is no code in an assembly file, no debug info is produced
 
@@ -8,7 +8,7 @@
 a:
 .long 42
 
-// DWARF: ELF32-arm-little
+// DWARF: elf32-littlearm
 // DWARF-NOT: contents:
 // DWARF: .debug_line contents:
 
diff --git a/llvm/test/MC/ARM/dwarf-asm-nonstandard-section.s b/llvm/test/MC/ARM/dwarf-asm-nonstandard-section.s
index 92fa6e544b094..e3fafc8c46669 100644
--- a/llvm/test/MC/ARM/dwarf-asm-nonstandard-section.s
+++ b/llvm/test/MC/ARM/dwarf-asm-nonstandard-section.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp
 // RUN: llvm-dwarfdump -a %t | FileCheck -check-prefix DWARF %s
-// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s
+// RUN: llvm-objdump -r %t | FileCheck --check-prefix=RELOC %s
 
   .section foo, "ax"
 b:
diff --git a/llvm/test/MC/ARM/dwarf-asm-single-section.s b/llvm/test/MC/ARM/dwarf-asm-single-section.s
index d376e89484941..324534a1d49d5 100644
--- a/llvm/test/MC/ARM/dwarf-asm-single-section.s
+++ b/llvm/test/MC/ARM/dwarf-asm-single-section.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp
 // RUN: llvm-dwarfdump -a %t | FileCheck -check-prefix DWARF %s
-// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s
+// RUN: llvm-objdump -r %t | FileCheck --check-prefix=RELOC %s
 
   .section .text, "ax"
 a:
diff --git a/llvm/test/MC/ARM/ehabi-personality-abs.s b/llvm/test/MC/ARM/ehabi-personality-abs.s
index fd8bf7397bd06..051b837c698a5 100644
--- a/llvm/test/MC/ARM/ehabi-personality-abs.s
+++ b/llvm/test/MC/ARM/ehabi-personality-abs.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple armv7-linux -filetype obj -o - %s | llvm-objdump -triple armv7 -D -r - | FileCheck %s
+@ RUN: llvm-mc -triple armv7-linux -filetype obj -o - %s | llvm-objdump --triple=armv7 -D -r - | FileCheck %s
 
 	.text
 
diff --git a/llvm/test/MC/ARM/elf-movt.s b/llvm/test/MC/ARM/elf-movt.s
index eb8466d0fff17..0478a233b23cf 100644
--- a/llvm/test/MC/ARM/elf-movt.s
+++ b/llvm/test/MC/ARM/elf-movt.s
@@ -1,8 +1,8 @@
 @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s
 @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o %t.o
-@ RUN: llvm-objdump -d -r %t.o -triple=armv7-linux-gnueabi | FileCheck -check-prefix=OBJ %s
+@ RUN: llvm-objdump -d -r %t.o --triple=armv7-linux-gnueabi | FileCheck --check-prefix=OBJ %s
 @ RUN: llvm-mc %s -triple=thumbv7-linux-gnueabi -filetype=obj -o %t.o
-@ RUN: llvm-objdump -d -r %t.o -triple=thumbv7-linux-gnueabi | FileCheck -check-prefix=THUMB %s
+@ RUN: llvm-objdump -d -r %t.o --triple=thumbv7-linux-gnueabi | FileCheck --check-prefix=THUMB %s
 
 	.syntax unified
 	.text
diff --git a/llvm/test/MC/ARM/fixup-cpu-mode.s b/llvm/test/MC/ARM/fixup-cpu-mode.s
index 17f29f94d2d6f..bc5feacdb35fa 100644
--- a/llvm/test/MC/ARM/fixup-cpu-mode.s
+++ b/llvm/test/MC/ARM/fixup-cpu-mode.s
@@ -1,5 +1,5 @@
 // RUN: llvm-mc -filetype=obj -triple thumbv7-linux-gnu %s -o %t
-// RUN: llvm-objdump -triple thumbv7-linux-gnu -d %t | FileCheck %s
+// RUN: llvm-objdump --triple=thumbv7-linux-gnu -d %t | FileCheck %s
 
 //PR18303
 .code 16
diff --git a/llvm/test/MC/ARM/inst-directive-other.s b/llvm/test/MC/ARM/inst-directive-other.s
index f5f0cafe66eb6..06c89f5333ee0 100644
--- a/llvm/test/MC/ARM/inst-directive-other.s
+++ b/llvm/test/MC/ARM/inst-directive-other.s
@@ -1,7 +1,7 @@
 // RUN: llvm-mc %s -triple=armv7-apple-darwin -filetype=asm -o - \
 // RUN:   | FileCheck %s --check-prefix=CHECK-ASM
 // RUN: llvm-mc %s -triple=armv7-apple-darwin -filetype=obj -o - \
-// RUN:   | llvm-objdump -triple=thumbv7 -d - | FileCheck %s --check-prefixes=CHECK-OBJ-CODE
+// RUN:   | llvm-objdump --triple=thumbv7 -d - | FileCheck %s --check-prefixes=CHECK-OBJ-CODE
 // RUN: llvm-mc %s -triple=thumbv7-win32-gnu -filetype=asm -o - \
 // RUN:   | FileCheck %s --check-prefix=CHECK-ASM
 // RUN: llvm-mc %s -triple=thumbv7-win32-gnu -filetype=obj -o - \
@@ -9,7 +9,7 @@
 // RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=asm -o - \
 // RUN:   | FileCheck %s --check-prefix=CHECK-ASM
 // RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - \
-// RUN:   | llvm-objdump -d -triple=thumbv7 - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-DATA
+// RUN:   | llvm-objdump -d --triple=thumbv7 - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-DATA
 
     .text
 
diff --git a/llvm/test/MC/ARM/macho-reloc-thumb-local.s b/llvm/test/MC/ARM/macho-reloc-thumb-local.s
index 1bb1c7e5ef3be..1461b1ef1f54c 100644
--- a/llvm/test/MC/ARM/macho-reloc-thumb-local.s
+++ b/llvm/test/MC/ARM/macho-reloc-thumb-local.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc -triple thumbv6m-apple-macho %s -filetype=obj -o %t
-@ RUN: llvm-objdump -macho -section=__DATA,__data %t | FileCheck %s
+@ RUN: llvm-objdump --macho --section=__DATA,__data %t | FileCheck %s
 
 @ CHECK: 00000000 00000003
         .data
diff --git a/llvm/test/MC/ARM/macho-word-reloc-thumb.s b/llvm/test/MC/ARM/macho-word-reloc-thumb.s
index 1562f21747a80..bd98f6b33f974 100644
--- a/llvm/test/MC/ARM/macho-word-reloc-thumb.s
+++ b/llvm/test/MC/ARM/macho-word-reloc-thumb.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc -triple thumbv7-apple-ios %s -filetype=obj -o %t
-@ RUN: llvm-objdump -macho -d %t -triple thumbv7-apple-ios | FileCheck %s
+@ RUN: llvm-objdump --macho -d %t --triple=thumbv7-apple-ios | FileCheck %s
 
 @ ARM relocatable object files try to look like they're pre-linked, so the
 @ offsets in the instructions are a best-guess. I suspect the "-3" should b
diff --git a/llvm/test/MC/ARM/modified-immediate-fixup.s b/llvm/test/MC/ARM/modified-immediate-fixup.s
index 288814b4009ea..da441957db883 100644
--- a/llvm/test/MC/ARM/modified-immediate-fixup.s
+++ b/llvm/test/MC/ARM/modified-immediate-fixup.s
@@ -1,6 +1,6 @@
 @ PR24346
 @ RUN: llvm-mc < %s -triple=arm-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-objdump --disassemble -arch=arm - | FileCheck %s
+@ RUN: | llvm-objdump -d --arch=arm - | FileCheck %s
 
     .data
     .align 8
diff --git a/llvm/test/MC/ARM/symbol-variants.s b/llvm/test/MC/ARM/symbol-variants.s
index 96fc4bda037de..6ddf810cf0331 100644
--- a/llvm/test/MC/ARM/symbol-variants.s
+++ b/llvm/test/MC/ARM/symbol-variants.s
@@ -1,5 +1,5 @@
-@ RUN: llvm-mc < %s -triple armv7-none-linux-gnueabi -filetype=obj  | llvm-objdump -triple armv7-none-linux-gnueabi -r - | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-@ RUN: llvm-mc < %s -triple thumbv7-none-linux-gnueabi -filetype=obj  | llvm-objdump -triple thumbv7-none-linux-gnueabi -r - | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
+@ RUN: llvm-mc < %s -triple armv7-none-linux-gnueabi -filetype=obj  | llvm-objdump --triple=armv7-none-linux-gnueabi -r - | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+@ RUN: llvm-mc < %s -triple thumbv7-none-linux-gnueabi -filetype=obj  | llvm-objdump --triple=thumbv7-none-linux-gnueabi -r - | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
 
 @ CHECK-LABEL: RELOCATION RECORDS FOR [.text]
 .Lsym:
diff --git a/llvm/test/MC/ARM/t2-modified-immediate-fixup.s b/llvm/test/MC/ARM/t2-modified-immediate-fixup.s
index ad0fae2e666ee..3eb12ad9336d7 100644
--- a/llvm/test/MC/ARM/t2-modified-immediate-fixup.s
+++ b/llvm/test/MC/ARM/t2-modified-immediate-fixup.s
@@ -1,6 +1,6 @@
 @ PR28647
 @ RUN: llvm-mc < %s -triple=thumbv7a-linux-gnueabi -filetype=obj -o - \
-@ RUN: | llvm-objdump --disassemble -triple=thumbv7a-linux-gnueabi - | FileCheck %s
+@ RUN: | llvm-objdump -d --triple=thumbv7a-linux-gnueabi - | FileCheck %s
     .text
     .syntax unified
     .balign 2
diff --git a/llvm/test/MC/ARM/thumb-cb-thumbfunc.s b/llvm/test/MC/ARM/thumb-cb-thumbfunc.s
index 12995f2a44919..faff72e252e53 100644
--- a/llvm/test/MC/ARM/thumb-cb-thumbfunc.s
+++ b/llvm/test/MC/ARM/thumb-cb-thumbfunc.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc -triple thumbv7-apple-macho -filetype=obj -o %t %s
-@ RUN: llvm-objdump -d -triple thumbv7 %t | FileCheck %s
+@ RUN: llvm-objdump -d --triple=thumbv7 %t | FileCheck %s
 
 @ CHECK: cbnz r0, #0
   .thumb_func label4
diff --git a/llvm/test/MC/ARM/thumb1-relax-bcc.s b/llvm/test/MC/ARM/thumb1-relax-bcc.s
index f17840ff763f0..d746c92a5f4d0 100644
--- a/llvm/test/MC/ARM/thumb1-relax-bcc.s
+++ b/llvm/test/MC/ARM/thumb1-relax-bcc.s
@@ -1,7 +1,7 @@
 @ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
 @ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
 @ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s
-@ RUN:    llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
+@ RUN:    llvm-objdump -d -r --triple=thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
 
         .global func1
 _func1:
diff --git a/llvm/test/MC/ARM/thumb1-relax-br.s b/llvm/test/MC/ARM/thumb1-relax-br.s
index 92a8275273882..550737e80c5dc 100644
--- a/llvm/test/MC/ARM/thumb1-relax-br.s
+++ b/llvm/test/MC/ARM/thumb1-relax-br.s
@@ -1,8 +1,8 @@
 @ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
 @ RUN: llvm-mc -triple thumbv7m-none-macho -filetype=obj -o %t %s
-@ RUN:    llvm-objdump -d -r -triple thumbv7m-none-macho %t | FileCheck --check-prefix=CHECK-MACHO %s
+@ RUN:    llvm-objdump -d -r --triple=thumbv7m-none-macho %t | FileCheck --check-prefix=CHECK-MACHO %s
 @ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s
-@ RUN:    llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
+@ RUN:    llvm-objdump -d -r --triple=thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s
 
         .global func1
 _func1:
diff --git a/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s b/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
index a7ad11b245083..52ceafea27de0 100644
--- a/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
+++ b/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc -triple thumbv7-apple-darwin -filetype=obj -o %t.o %s
-@ RUN: llvm-objdump -triple thumbv7-apple-darwin -d %t.o | FileCheck %s
+@ RUN: llvm-objdump --triple=thumbv7-apple-darwin -d %t.o | FileCheck %s
 
 .thumb
 start:
diff --git a/llvm/test/MC/ARM/tls-directives.s b/llvm/test/MC/ARM/tls-directives.s
index 69a026892899f..26dd68034d230 100644
--- a/llvm/test/MC/ARM/tls-directives.s
+++ b/llvm/test/MC/ARM/tls-directives.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc -triple thumbv7-apple-ios -filetype=obj -o %t %s
-@ RUN: llvm-objdump -macho -p -indirect-symbols %t | FileCheck %s
+@ RUN: llvm-objdump --macho -p --indirect-symbols %t | FileCheck %s
 
 @ CHECK: Indirect symbols for (__DATA,__thread_ptr)
 @ CHECK: 0x0000001c     5 _a
diff --git a/llvm/test/MC/AVR/dwarf-asm-no-code.s b/llvm/test/MC/AVR/dwarf-asm-no-code.s
index cbe0bf49ad1e3..98c8151d73358 100644
--- a/llvm/test/MC/AVR/dwarf-asm-no-code.s
+++ b/llvm/test/MC/AVR/dwarf-asm-no-code.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc < %s -triple=avr -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp
 // RUN: llvm-dwarfdump -v %t | FileCheck -check-prefix DWARF %s
-// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s
+// RUN: llvm-objdump -r %t | FileCheck --check-prefix=RELOC %s
 
 // If there is no code in an assembly file, no debug info is produced
 
@@ -8,7 +8,7 @@
 a:
 .long 42
 
-// DWARF: ELF32-avr
+// DWARF: elf32-avr
 // DWARF-NOT: contents:
 // DWARF: .debug_line contents:
 
diff --git a/llvm/test/MC/AVR/inst-adc.s b/llvm/test/MC/AVR/inst-adc.s
index 40c0f636cfbc8..d1157bc7a9b3b 100644
--- a/llvm/test/MC/AVR/inst-adc.s
+++ b/llvm/test/MC/AVR/inst-adc.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-add.s b/llvm/test/MC/AVR/inst-add.s
index 37bc8a3c716cc..49ad5de80c06b 100644
--- a/llvm/test/MC/AVR/inst-add.s
+++ b/llvm/test/MC/AVR/inst-add.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-adiw.s b/llvm/test/MC/AVR/inst-adiw.s
index d1009e79fe0b4..4de394d91f9d7 100644
--- a/llvm/test/MC/AVR/inst-adiw.s
+++ b/llvm/test/MC/AVR/inst-adiw.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=addsubiw -show-encoding < %s | FileCheck %s
-; RUNx: llvm-mc -filetype=obj -triple avr -mattr=addsubiw < %s | llvm-objdump -d -mattr=addsubiw - | FileCheck -check-prefix=CHECK-INST %s
+; RUNx: llvm-mc -filetype=obj -triple avr -mattr=addsubiw < %s | llvm-objdump -d --mattr=addsubiw - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-and.s b/llvm/test/MC/AVR/inst-and.s
index 729361203e364..c4d90bfba3747 100644
--- a/llvm/test/MC/AVR/inst-and.s
+++ b/llvm/test/MC/AVR/inst-and.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-andi.s b/llvm/test/MC/AVR/inst-andi.s
index ab90ea6257dca..e94824dbb90a3 100644
--- a/llvm/test/MC/AVR/inst-andi.s
+++ b/llvm/test/MC/AVR/inst-andi.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-bld.s b/llvm/test/MC/AVR/inst-bld.s
index 2c6e106602f66..f7059d8277881 100644
--- a/llvm/test/MC/AVR/inst-bld.s
+++ b/llvm/test/MC/AVR/inst-bld.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-break.s b/llvm/test/MC/AVR/inst-break.s
index 059a309b9fc2c..a1bfde93c5a0d 100644
--- a/llvm/test/MC/AVR/inst-break.s
+++ b/llvm/test/MC/AVR/inst-break.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=break -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=break < %s | llvm-objdump -d -mattr=break - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=break < %s | llvm-objdump -d --mattr=break - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-bst.s b/llvm/test/MC/AVR/inst-bst.s
index 923e4fef7b92d..1bb83e986d0da 100644
--- a/llvm/test/MC/AVR/inst-bst.s
+++ b/llvm/test/MC/AVR/inst-bst.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-cbr.s b/llvm/test/MC/AVR/inst-cbr.s
index cb2a16022a5ed..8a487579a4421 100644
--- a/llvm/test/MC/AVR/inst-cbr.s
+++ b/llvm/test/MC/AVR/inst-cbr.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-clr.s b/llvm/test/MC/AVR/inst-clr.s
index e4cae8f30823c..d5966ae8e0953 100644
--- a/llvm/test/MC/AVR/inst-clr.s
+++ b/llvm/test/MC/AVR/inst-clr.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-cp.s b/llvm/test/MC/AVR/inst-cp.s
index e7d41830c0922..68c363046bb9d 100644
--- a/llvm/test/MC/AVR/inst-cp.s
+++ b/llvm/test/MC/AVR/inst-cp.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-cpc.s b/llvm/test/MC/AVR/inst-cpc.s
index e29b7b1d8fc28..04c96b1d81417 100644
--- a/llvm/test/MC/AVR/inst-cpc.s
+++ b/llvm/test/MC/AVR/inst-cpc.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-cpi.s b/llvm/test/MC/AVR/inst-cpi.s
index d049eecd0e383..b66545124bf85 100644
--- a/llvm/test/MC/AVR/inst-cpi.s
+++ b/llvm/test/MC/AVR/inst-cpi.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-cpse.s b/llvm/test/MC/AVR/inst-cpse.s
index ffcd12edcfc81..209491ec70c67 100644
--- a/llvm/test/MC/AVR/inst-cpse.s
+++ b/llvm/test/MC/AVR/inst-cpse.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-des.s b/llvm/test/MC/AVR/inst-des.s
index 1e9a92534a9dd..90580e9abb88c 100644
--- a/llvm/test/MC/AVR/inst-des.s
+++ b/llvm/test/MC/AVR/inst-des.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=des -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=des < %s | llvm-objdump -d -mattr=des - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=des < %s | llvm-objdump -d --mattr=des - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-eicall.s b/llvm/test/MC/AVR/inst-eicall.s
index bbcabfdc77757..49ce225518617 100644
--- a/llvm/test/MC/AVR/inst-eicall.s
+++ b/llvm/test/MC/AVR/inst-eicall.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=eijmpcall -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=eijmpcall < %s | llvm-objdump -d -mattr=eijmpcall - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=eijmpcall < %s | llvm-objdump -d --mattr=eijmpcall - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-eijmp.s b/llvm/test/MC/AVR/inst-eijmp.s
index 942af21fb9303..78e2f539a8b00 100644
--- a/llvm/test/MC/AVR/inst-eijmp.s
+++ b/llvm/test/MC/AVR/inst-eijmp.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=eijmpcall -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=eijmpcall < %s | llvm-objdump -d -mattr=eijmpcall - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=eijmpcall < %s | llvm-objdump -d --mattr=eijmpcall - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-eor.s b/llvm/test/MC/AVR/inst-eor.s
index eb3ded799ca79..1664eeed40e50 100644
--- a/llvm/test/MC/AVR/inst-eor.s
+++ b/llvm/test/MC/AVR/inst-eor.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-family-set-clr-flag.s b/llvm/test/MC/AVR/inst-family-set-clr-flag.s
index ef80b10b1b992..364e727866280 100644
--- a/llvm/test/MC/AVR/inst-family-set-clr-flag.s
+++ b/llvm/test/MC/AVR/inst-family-set-clr-flag.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 foo:
 
diff --git a/llvm/test/MC/AVR/inst-icall.s b/llvm/test/MC/AVR/inst-icall.s
index 2f25c82028fd3..48e1e7a9546b0 100644
--- a/llvm/test/MC/AVR/inst-icall.s
+++ b/llvm/test/MC/AVR/inst-icall.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=ijmpcall -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=ijmpcall < %s | llvm-objdump -d -mattr=ijmpcall - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=ijmpcall < %s | llvm-objdump -d --mattr=ijmpcall - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-ijmp.s b/llvm/test/MC/AVR/inst-ijmp.s
index c16eea415e4ea..b2781b43c17ff 100644
--- a/llvm/test/MC/AVR/inst-ijmp.s
+++ b/llvm/test/MC/AVR/inst-ijmp.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=ijmpcall -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=ijmpcall < %s | llvm-objdump -d -mattr=ijmpcall - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=ijmpcall < %s | llvm-objdump -d --mattr=ijmpcall - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-ldi.s b/llvm/test/MC/AVR/inst-ldi.s
index 9696a36b430be..e8e46cdf5e28a 100644
--- a/llvm/test/MC/AVR/inst-ldi.s
+++ b/llvm/test/MC/AVR/inst-ldi.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -d -mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -d --mattr=sram - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-lsl.s b/llvm/test/MC/AVR/inst-lsl.s
index deceac9f6f79c..fbb4d2ce5666c 100644
--- a/llvm/test/MC/AVR/inst-lsl.s
+++ b/llvm/test/MC/AVR/inst-lsl.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-mov.s b/llvm/test/MC/AVR/inst-mov.s
index 9808b007d75ca..5294b1bc52bed 100644
--- a/llvm/test/MC/AVR/inst-mov.s
+++ b/llvm/test/MC/AVR/inst-mov.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-nop.s b/llvm/test/MC/AVR/inst-nop.s
index 5e09fed91cfad..a7b6fff3f8001 100644
--- a/llvm/test/MC/AVR/inst-nop.s
+++ b/llvm/test/MC/AVR/inst-nop.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-or.s b/llvm/test/MC/AVR/inst-or.s
index c3489639dddf7..c30e6b136bc04 100644
--- a/llvm/test/MC/AVR/inst-or.s
+++ b/llvm/test/MC/AVR/inst-or.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-ori.s b/llvm/test/MC/AVR/inst-ori.s
index dd374f21e9cda..bbd6821e3f4b7 100644
--- a/llvm/test/MC/AVR/inst-ori.s
+++ b/llvm/test/MC/AVR/inst-ori.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-ret.s b/llvm/test/MC/AVR/inst-ret.s
index d39821c59d4fe..92b1e30118618 100644
--- a/llvm/test/MC/AVR/inst-ret.s
+++ b/llvm/test/MC/AVR/inst-ret.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-reti.s b/llvm/test/MC/AVR/inst-reti.s
index 43d0571e738d8..aa338d3024e13 100644
--- a/llvm/test/MC/AVR/inst-reti.s
+++ b/llvm/test/MC/AVR/inst-reti.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-rol.s b/llvm/test/MC/AVR/inst-rol.s
index ffb266c633518..434505aa88c06 100644
--- a/llvm/test/MC/AVR/inst-rol.s
+++ b/llvm/test/MC/AVR/inst-rol.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-sbc.s b/llvm/test/MC/AVR/inst-sbc.s
index 62872b0499efc..d92bd63ba2077 100644
--- a/llvm/test/MC/AVR/inst-sbc.s
+++ b/llvm/test/MC/AVR/inst-sbc.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-sbci.s b/llvm/test/MC/AVR/inst-sbci.s
index 459dad2d54358..e1497280837ff 100644
--- a/llvm/test/MC/AVR/inst-sbci.s
+++ b/llvm/test/MC/AVR/inst-sbci.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-sbiw.s b/llvm/test/MC/AVR/inst-sbiw.s
index abd2df854dec4..cb0242841dff2 100644
--- a/llvm/test/MC/AVR/inst-sbiw.s
+++ b/llvm/test/MC/AVR/inst-sbiw.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -mattr=addsubiw -show-encoding < %s | FileCheck %s
-; RUNx: llvm-mc -filetype=obj -triple avr -mattr=addsubiw < %s | llvm-objdump -d -mattr=addsubiw - | FileCheck -check-prefix=CHECK-INST %s
+; RUNx: llvm-mc -filetype=obj -triple avr -mattr=addsubiw < %s | llvm-objdump -d --mattr=addsubiw - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-sbr.s b/llvm/test/MC/AVR/inst-sbr.s
index 4d1c8983a0c5f..8e059d3ba36de 100644
--- a/llvm/test/MC/AVR/inst-sbr.s
+++ b/llvm/test/MC/AVR/inst-sbr.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-ser.s b/llvm/test/MC/AVR/inst-ser.s
index ac2a5fe86c07d..c5bb5d01094c3 100644
--- a/llvm/test/MC/AVR/inst-ser.s
+++ b/llvm/test/MC/AVR/inst-ser.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-sleep.s b/llvm/test/MC/AVR/inst-sleep.s
index 1483a8831cc3b..5aeaeb4623961 100644
--- a/llvm/test/MC/AVR/inst-sleep.s
+++ b/llvm/test/MC/AVR/inst-sleep.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-sub.s b/llvm/test/MC/AVR/inst-sub.s
index 04909af2c6bc7..9dc5f2006aa13 100644
--- a/llvm/test/MC/AVR/inst-sub.s
+++ b/llvm/test/MC/AVR/inst-sub.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-subi.s b/llvm/test/MC/AVR/inst-subi.s
index 7c1cc03f652b9..ce68b6996f708 100644
--- a/llvm/test/MC/AVR/inst-subi.s
+++ b/llvm/test/MC/AVR/inst-subi.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-tst.s b/llvm/test/MC/AVR/inst-tst.s
index 93c80953adb42..5097a81916ad0 100644
--- a/llvm/test/MC/AVR/inst-tst.s
+++ b/llvm/test/MC/AVR/inst-tst.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/inst-wdr.s b/llvm/test/MC/AVR/inst-wdr.s
index 66a1544ce5c4e..fdded7cca1047 100644
--- a/llvm/test/MC/AVR/inst-wdr.s
+++ b/llvm/test/MC/AVR/inst-wdr.s
@@ -1,5 +1,5 @@
 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
-; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
 
 foo:
diff --git a/llvm/test/MC/AVR/relocations-abs.s b/llvm/test/MC/AVR/relocations-abs.s
index 05485479e42b4..b384cadcec202 100644
--- a/llvm/test/MC/AVR/relocations-abs.s
+++ b/llvm/test/MC/AVR/relocations-abs.s
@@ -1,4 +1,4 @@
-; RUN: llvm-mc -filetype=obj -triple=avr %s | llvm-objdump -dr - | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple=avr %s | llvm-objdump -d -r - | FileCheck %s
 
 ; CHECK: <bar>:
 ; CHECK-NEXT: 00 00 nop
diff --git a/llvm/test/MC/AsmParser/directive_fill_2.s b/llvm/test/MC/AsmParser/directive_fill_2.s
index 232a6a36b4629..6b40d142c0e0b 100644
--- a/llvm/test/MC/AsmParser/directive_fill_2.s
+++ b/llvm/test/MC/AsmParser/directive_fill_2.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -defsym=I=6 -triple i686-unknown-unknown %s | llvm-objdump -triple i686-unknown-unknown -s - | FileCheck --check-prefix="CHECK" %s
+# RUN: llvm-mc -filetype=obj -defsym=I=6 -triple i686-unknown-unknown %s | llvm-objdump --triple=i686-unknown-unknown -s - | FileCheck --check-prefix="CHECK" %s
 # RUN: not llvm-mc -filetype=obj -defsym=I=4 -triple i686-unknown-unknown %s -o /dev/null 2>&1 | FileCheck --check-prefix="CHECK-ERR" %s
 
 
diff --git a/llvm/test/MC/AsmParser/non-english-characters.s b/llvm/test/MC/AsmParser/non-english-characters.s
index 0e47a943bd306..4eae7a1c6c8d9 100644
--- a/llvm/test/MC/AsmParser/non-english-characters.s
+++ b/llvm/test/MC/AsmParser/non-english-characters.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple i386-linux-gnu -filetype=obj -o %t \
 # RUN:   %S/Inputs/non-english-characters-comments.s
 # RUN: llvm-readobj %t | FileCheck %s
-# CHECK: Format: ELF32-i386
+# CHECK: Format: elf32-i386
 
 # RUN: not llvm-mc -triple i386-linux-gnu -filetype=obj -o %t \
 # RUN:   %S/Inputs/non-english-characters-section-name.s 2>&1 | \
diff --git a/llvm/test/MC/BPF/insn-unit-32.s b/llvm/test/MC/BPF/insn-unit-32.s
index 9d09bd29135e1..d7cb9a62098bc 100644
--- a/llvm/test/MC/BPF/insn-unit-32.s
+++ b/llvm/test/MC/BPF/insn-unit-32.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc -triple bpfel -filetype=obj -o %t %s
 # RUN: llvm-objdump -d -r %t | FileCheck %s
-# RUN: llvm-objdump -mattr=+alu32 -d -r %t | FileCheck %s
+# RUN: llvm-objdump --mattr=+alu32 -d -r %t | FileCheck %s
 
 // ======== BPF_ALU Class ========
   w1 = -w1    // BPF_NEG
diff --git a/llvm/test/MC/BPF/insn-unit.s b/llvm/test/MC/BPF/insn-unit.s
index 5e0c96cb03601..bb05fb982210b 100644
--- a/llvm/test/MC/BPF/insn-unit.s
+++ b/llvm/test/MC/BPF/insn-unit.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc -triple bpfel -filetype=obj -o %t %s
 # RUN: llvm-objdump -d -r %t | FileCheck --check-prefixes CHECK,CHECK-64 %s
-# RUN: llvm-objdump -mattr=+alu32 -d -r %t | FileCheck --check-prefixes CHECK,CHECK-32 %s
+# RUN: llvm-objdump --mattr=+alu32 -d -r %t | FileCheck --check-prefixes CHECK,CHECK-32 %s
 
 // ======== BPF_LD Class ========
 // Some extra whitespaces are deliberately added to test the parser.
diff --git a/llvm/test/MC/BPF/load-store-32.s b/llvm/test/MC/BPF/load-store-32.s
index be576d2720465..fb849d06b0086 100644
--- a/llvm/test/MC/BPF/load-store-32.s
+++ b/llvm/test/MC/BPF/load-store-32.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -triple bpfel -filetype=obj -o %t %s
-# RUN: llvm-objdump -mattr=+alu32 -d -r %t | FileCheck --check-prefix=CHECK-32 %s
+# RUN: llvm-objdump --mattr=+alu32 -d -r %t | FileCheck --check-prefix=CHECK-32 %s
 # RUN: llvm-objdump -d -r %t | FileCheck %s
 
 // ======== BPF_LDX Class ========
diff --git a/llvm/test/MC/Disassembler/ARM/mve-lol.txt b/llvm/test/MC/Disassembler/ARM/mve-lol.txt
index b16e131bc1dfd..1646b7f252364 100644
--- a/llvm/test/MC/Disassembler/ARM/mve-lol.txt
+++ b/llvm/test/MC/Disassembler/ARM/mve-lol.txt
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -assemble -triple=thumbv8.1m.main -mattr=+mve -filetype=obj %s -o - 2>&1 | \
-# RUN:   llvm-objdump -d -r -triple=thumbv8.1m.main -mattr=+mve - | FileCheck %s
+# RUN:   llvm-objdump -d -r --triple=thumbv8.1m.main --mattr=+mve - | FileCheck %s
 
 # Test to check that we can evaluate branches and their targets, i.e.
 # checking that we see branch targets annotations like <$t.0+0xc> in the
diff --git a/llvm/test/MC/ELF/empty.s b/llvm/test/MC/ELF/empty.s
index e640715591af2..bc5c80a218156 100644
--- a/llvm/test/MC/ELF/empty.s
+++ b/llvm/test/MC/ELF/empty.s
@@ -5,8 +5,8 @@
 // Check that we can create ELF files for darwin/windows, even though
 // it is not the default file format.
 
-// DARWIN:       Format: ELF64-x86-64
-// WINDOWS:      Format: ELF64-x86-64
+// DARWIN:       Format: elf64-x86-64
+// WINDOWS:      Format: elf64-x86-64
 // DARWIN-NEXT:  Arch: x86_64
 // WINDOWS-NEXT: Arch: x86_64
 
diff --git a/llvm/test/MC/ELF/relax-all-flag.s b/llvm/test/MC/ELF/relax-all-flag.s
index 4c1c78c3925da..c0dd87acd63c8 100644
--- a/llvm/test/MC/ELF/relax-all-flag.s
+++ b/llvm/test/MC/ELF/relax-all-flag.s
@@ -4,10 +4,10 @@
 // expect to see a different instruction.
 
 // RUN: llvm-mc -filetype=obj -mc-relax-all -triple x86_64-pc-linux-gnu %s -o - \
-// RUN:  | llvm-objdump -disassemble - | FileCheck -check-prefix=RELAXALL %s
+// RUN:  | llvm-objdump -d - | FileCheck --check-prefix=RELAXALL %s
 
 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
-// RUN:  | llvm-objdump -disassemble - | FileCheck %s
+// RUN:  | llvm-objdump -d - | FileCheck %s
 
 .text
 foo:
diff --git a/llvm/test/MC/ELF/relocation-386.s b/llvm/test/MC/ELF/relocation-386.s
index e2c4e1073ad94..d06cea9be9fdc 100644
--- a/llvm/test/MC/ELF/relocation-386.s
+++ b/llvm/test/MC/ELF/relocation-386.s
@@ -4,8 +4,8 @@
 // Test that we produce the correct relocation types and that the relocations
 // correctly point to the section or the symbol.
 
-// IAMCU: Format: ELF32-iamcu
-// I386: Format: ELF32-i386
+// IAMCU: Format: elf32-iamcu
+// I386: Format: elf32-i386
 // CHECK:      Relocations [
 // CHECK-NEXT:   Section {{.*}} .rel.text {
 // CHECK-NEXT:     0x2          R_386_GOTOFF     .Lfoo 0x0
diff --git a/llvm/test/MC/Hexagon/J2_trap1_dep.s b/llvm/test/MC/Hexagon/J2_trap1_dep.s
index 8beb55598f083..7d322b18696b2 100644
--- a/llvm/test/MC/Hexagon/J2_trap1_dep.s
+++ b/llvm/test/MC/Hexagon/J2_trap1_dep.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -mcpu=hexagonv62 -d - | FileCheck %s --check-prefix=CHECK-V62
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump -mcpu=hexagonv65 -d - | FileCheck %s --check-prefix=CHECK-V65
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --mcpu=hexagonv62 -d - | FileCheck %s --check-prefix=CHECK-V62
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --mcpu=hexagonv65 -d - | FileCheck %s --check-prefix=CHECK-V65
 
 # CHECK-V62: trap1(#0)
 # CHECK-V65: trap1(r0,#0)
diff --git a/llvm/test/MC/Hexagon/align.s b/llvm/test/MC/Hexagon/align.s
index e85534def21f2..3469b83c21fec 100644
--- a/llvm/test/MC/Hexagon/align.s
+++ b/llvm/test/MC/Hexagon/align.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump --mhvx -d - | FileCheck %s
 
 # Verify that the .align directive emits the proper insn packets.
 
diff --git a/llvm/test/MC/Hexagon/basic.ll b/llvm/test/MC/Hexagon/basic.ll
index 98b4cbc0a31d3..5fba44f3a5f9f 100644
--- a/llvm/test/MC/Hexagon/basic.ll
+++ b/llvm/test/MC/Hexagon/basic.ll
@@ -1,7 +1,7 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
 
-; OBJ: Format: ELF32-hexagon
+; OBJ: Format: elf32-hexagon
 ; OBJ: Arch: hexagon
 ; OBJ: AddressSize: 32bit
 ; OBJ: Machine: EM_HEXAGON (0xA4)
diff --git a/llvm/test/MC/Hexagon/cmpyrw.s b/llvm/test/MC/Hexagon/cmpyrw.s
index 37244f7547dc4..d90739000eea8 100644
--- a/llvm/test/MC/Hexagon/cmpyrw.s
+++ b/llvm/test/MC/Hexagon/cmpyrw.s
@@ -1,3 +1,3 @@
-# RUN: llvm-mc -arch=hexagon -mv67t -filetype=obj %s | llvm-objdump -mv67t -mattr=+audio -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv67t -filetype=obj %s | llvm-objdump --mv67t --mattr=+audio -d - | FileCheck %s
 r23:22 = cmpyrw(r15:14,r21:20*)
 # CHECK:   r23:22 = cmpyrw(r15:14,r21:20*)
diff --git a/llvm/test/MC/Hexagon/extensions/v67_hvx.s b/llvm/test/MC/Hexagon/extensions/v67_hvx.s
index aca9c8e117ab1..ca046f8ae5f13 100644
--- a/llvm/test/MC/Hexagon/extensions/v67_hvx.s
+++ b/llvm/test/MC/Hexagon/extensions/v67_hvx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv67 -mhvx -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mhvx -d - | FileCheck --implicit-check-not='{' %s
 
 
 
diff --git a/llvm/test/MC/Hexagon/extensions/v67t_audio.s b/llvm/test/MC/Hexagon/extensions/v67t_audio.s
index c0cdb340203b3..cffc21a32d95c 100644
--- a/llvm/test/MC/Hexagon/extensions/v67t_audio.s
+++ b/llvm/test/MC/Hexagon/extensions/v67t_audio.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t  -filetype=obj %s | llvm-objdump -mcpu=hexagonv67t  -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t  -filetype=obj %s | llvm-objdump --mcpu=hexagonv67t  -d - | FileCheck --implicit-check-not='{' %s
 
 
 
diff --git a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
index 8719281067d3c..94d303341b9cc 100644
--- a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
+++ b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d -mhvx - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d --mhvx - | FileCheck %s
 
 # CHECK: vhist
 vhist
diff --git a/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s b/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
index 1ddec177e7838..617b1afff0bd8 100644
--- a/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
+++ b/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon -mcpu=hexagonv67 -mhvx %s | llvm-objdump -d -mcpu=hexagonv67 -mhvx - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=hexagon -mcpu=hexagonv67 -mhvx %s | llvm-objdump -d --mcpu=hexagonv67 --mhvx - | FileCheck %s
 # RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv65 -mhvx -filetype=asm %s 2>%t; FileCheck --check-prefix=CHECK-V65 --implicit-check-not="error:" %s <%t
 
 v1:0.w = vadd(v0.h, v1.h) // Normal
diff --git a/llvm/test/MC/Hexagon/quad_regs.s b/llvm/test/MC/Hexagon/quad_regs.s
index 6805f3bdb35a4..7053a292c630b 100644
--- a/llvm/test/MC/Hexagon/quad_regs.s
+++ b/llvm/test/MC/Hexagon/quad_regs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mhvx -d - | FileCheck %s
 
 # Test for quad register parsing and printing
 # CHECK: { v3:0.w = vrmpyz(v0.b,r0.b) }
diff --git a/llvm/test/MC/Hexagon/smallcore_dis.s b/llvm/test/MC/Hexagon/smallcore_dis.s
index b94169e864511..d2b17ba1caa0a 100644
--- a/llvm/test/MC/Hexagon/smallcore_dis.s
+++ b/llvm/test/MC/Hexagon/smallcore_dis.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump -d - | FileCheck %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump -mv67t -d - | FileCheck %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump -mcpu=hexagonv67t -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --mv67t -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --mcpu=hexagonv67t -d - | FileCheck %s
 
     .text
 {
diff --git a/llvm/test/MC/Hexagon/v60-alu.s b/llvm/test/MC/Hexagon/v60-alu.s
index 856a9fec91afc..7c32d86117bb1 100644
--- a/llvm/test/MC/Hexagon/v60-alu.s
+++ b/llvm/test/MC/Hexagon/v60-alu.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd }
diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s
index a7ec36cfa956d..1e10ab17bad10 100644
--- a/llvm/test/MC/Hexagon/v60-misc.s
+++ b/llvm/test/MC/Hexagon/v60-misc.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump --arch=hexagon --mcpu=hexagonv60 --mhvx -d - | FileCheck %s
 
 .L0:
 
diff --git a/llvm/test/MC/Hexagon/v60-permute.s b/llvm/test/MC/Hexagon/v60-permute.s
index 0b0697a9e2fa3..b46d8cff847ff 100644
--- a/llvm/test/MC/Hexagon/v60-permute.s
+++ b/llvm/test/MC/Hexagon/v60-permute.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat }
diff --git a/llvm/test/MC/Hexagon/v60-shift.s b/llvm/test/MC/Hexagon/v60-shift.s
index 0002714cab4ab..ea913032e10a5 100644
--- a/llvm/test/MC/Hexagon/v60-shift.s
+++ b/llvm/test/MC/Hexagon/v60-shift.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) }
diff --git a/llvm/test/MC/Hexagon/v60-vcmp.s b/llvm/test/MC/Hexagon/v60-vcmp.s
index 712f570f99ed6..1206acceb67e9 100644
--- a/llvm/test/MC/Hexagon/v60-vcmp.s
+++ b/llvm/test/MC/Hexagon/v60-vcmp.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
diff --git a/llvm/test/MC/Hexagon/v60-vmem.s b/llvm/test/MC/Hexagon/v60-vmem.s
index bf549c893a11a..c484c41e05ea3 100644
--- a/llvm/test/MC/Hexagon/v60-vmem.s
+++ b/llvm/test/MC/Hexagon/v60-vmem.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 292cc11b { vmem(r12++#1) = v27 }
diff --git a/llvm/test/MC/Hexagon/v60-vmpy-acc.s b/llvm/test/MC/Hexagon/v60-vmpy-acc.s
index a582a5f740c9e..ae70292934012 100644
--- a/llvm/test/MC/Hexagon/v60-vmpy-acc.s
+++ b/llvm/test/MC/Hexagon/v60-vmpy-acc.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat }
diff --git a/llvm/test/MC/Hexagon/v60-vmpy1.s b/llvm/test/MC/Hexagon/v60-vmpy1.s
index dd86a084d1f63..19d03ede0b149 100644
--- a/llvm/test/MC/Hexagon/v60-vmpy1.s
+++ b/llvm/test/MC/Hexagon/v60-vmpy1.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
 #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat }
diff --git a/llvm/test/MC/Hexagon/v60lookup.s b/llvm/test/MC/Hexagon/v60lookup.s
index d4c520210a0ab..dc3d7939fb768 100644
--- a/llvm/test/MC/Hexagon/v60lookup.s
+++ b/llvm/test/MC/Hexagon/v60lookup.s
@@ -1,5 +1,5 @@
 #RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \
-#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \
+#RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv60 --mhvx -d - | \
 #RUN: FileCheck %s
 
                     V31.b = vlut32(V29.b, V15.b, R1)
diff --git a/llvm/test/MC/Hexagon/v62_all.s b/llvm/test/MC/Hexagon/v62_all.s
index 79e30982e96d1..b34b6f919e36c 100644
--- a/llvm/test/MC/Hexagon/v62_all.s
+++ b/llvm/test/MC/Hexagon/v62_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump --arch=hexagon --mcpu=hexagonv62 --mhvx -d - | FileCheck %s
 
 //   V6_lvsplatb
 //   Vd32.b=vsplat(Rt32)
diff --git a/llvm/test/MC/Hexagon/v62_jumps.s b/llvm/test/MC/Hexagon/v62_jumps.s
index 0197ecdd23215..d1a1585619d23 100644
--- a/llvm/test/MC/Hexagon/v62_jumps.s
+++ b/llvm/test/MC/Hexagon/v62_jumps.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --arch=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
 
 # verify compound is split into single instructions if needed
 {
diff --git a/llvm/test/MC/Hexagon/v62a.s b/llvm/test/MC/Hexagon/v62a.s
index 4cc6302f6fab8..4c6a25e26fde5 100644
--- a/llvm/test/MC/Hexagon/v62a.s
+++ b/llvm/test/MC/Hexagon/v62a.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s | llvm-objdump -arch=hexagon -arch=hexagon -mcpu=hexagonv62 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s | llvm-objdump --arch=hexagon --arch=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
 
   r31:30=vabsdiffb(r29:28, r27:26)
 # CHECK: e8fadc1e { r31:30 = vabsdiffb(r29:28,r27:26)
diff --git a/llvm/test/MC/Hexagon/v65_all.s b/llvm/test/MC/Hexagon/v65_all.s
index 4f52a063a34e5..0c3412a984805 100644
--- a/llvm/test/MC/Hexagon/v65_all.s
+++ b/llvm/test/MC/Hexagon/v65_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump -mv65 -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump --mv65 --mhvx -d - | FileCheck %s
 
 // Warning: This file is auto generated by mktest.py.  Do not edit!
 // Created on:  2016-06-01 @ 17:33:01
diff --git a/llvm/test/MC/Hexagon/v66.s b/llvm/test/MC/Hexagon/v66.s
index 465345fb35e77..f02dc1ef762bd 100644
--- a/llvm/test/MC/Hexagon/v66.s
+++ b/llvm/test/MC/Hexagon/v66.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mhvx -d - | FileCheck %s
 
 # CHECK: 1d8362e4 { v4.w = vsatdw(v2.w,v3.w)
 {
diff --git a/llvm/test/MC/Hexagon/v67.s b/llvm/test/MC/Hexagon/v67.s
index c1da560c021bd..059a08f61b64a 100644
--- a/llvm/test/MC/Hexagon/v67.s
+++ b/llvm/test/MC/Hexagon/v67.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump -mhvx=v66 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump --mhvx=v66 -d - | FileCheck %s
 
 # CHECK: 1a81e0e2 { v2.uw = vrotr(v0.uw,v1.uw) }
   v2.uw=vrotr(v0.uw, v1.uw)
diff --git a/llvm/test/MC/Hexagon/v67_all.s b/llvm/test/MC/Hexagon/v67_all.s
index c9611e128419c..065001db353c2 100644
--- a/llvm/test/MC/Hexagon/v67_all.s
+++ b/llvm/test/MC/Hexagon/v67_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump -mhvx=v66 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump --mhvx=v66 -d - | FileCheck %s
 
 # CHECK: { v3:0.w = vrmpyz(v0.b,r0.ub) }
 V3:0.w=vrmpyz(v0.b,r0.ub)
diff --git a/llvm/test/MC/Hexagon/z-instructions.s b/llvm/test/MC/Hexagon/z-instructions.s
index 2a2482e17d9e6..308e40ccade9f 100644
--- a/llvm/test/MC/Hexagon/z-instructions.s
+++ b/llvm/test/MC/Hexagon/z-instructions.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mhvx -d - | FileCheck --implicit-check-not='{' %s
 
 # CHECK:      2d00c000 { z = vmem(r0++#0) }
 z = vmem(r0++#0)
diff --git a/llvm/test/MC/MSP430/opcode.s b/llvm/test/MC/MSP430/opcode.s
index 14655fe091fa6..7033429181021 100644
--- a/llvm/test/MC/MSP430/opcode.s
+++ b/llvm/test/MC/MSP430/opcode.s
@@ -2,7 +2,7 @@
 ; RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 
 ; RUN: llvm-mc -triple msp430 -filetype=obj %s \
-; RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+; RUN:     | llvm-objdump -d - | FileCheck --check-prefix=CHECK-INST %s
 
   ;; IForm8 instructions
   mov.b  r7, r8 ; CHECK-INST: mov.b  r7, r8
diff --git a/llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s b/llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s
index 6e8a855cafca7..51ec86b8d66af 100644
--- a/llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s
+++ b/llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=thumbv7k-apple-watchos2.0.0 -filetype=obj -o %t < %s && llvm-objdump -unwind-info %t | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv7k-apple-watchos2.0.0 -filetype=obj -o %t < %s && llvm-objdump --unwind-info %t | FileCheck %s
 
 @ CHECK: Contents of __compact_unwind section:
 
diff --git a/llvm/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s b/llvm/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s
index 7fcec529947f2..02c95197c6013 100644
--- a/llvm/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s
+++ b/llvm/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=thumbv7-apple-ios -filetype=obj -o - < %s | llvm-objdump -d -macho -triple=thumbv7-apple-ios - | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv7-apple-ios -filetype=obj -o - < %s | llvm-objdump -d --macho --triple=thumbv7-apple-ios - | FileCheck %s
 	nop
 # CHECK:        0:	00 bf                                        	nop
 # We are checking that disassembly happens when there are no symbols.
diff --git a/llvm/test/MC/MachO/ARM/llvm-objdump-macho.s b/llvm/test/MC/MachO/ARM/llvm-objdump-macho.s
index c8aec932ad6c9..3dae5a6fe7f13 100644
--- a/llvm/test/MC/MachO/ARM/llvm-objdump-macho.s
+++ b/llvm/test/MC/MachO/ARM/llvm-objdump-macho.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=thumbv7-apple-ios -filetype=obj -o - < %s | llvm-objdump -d -macho -triple=thumbv7-apple-ios - | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv7-apple-ios -filetype=obj -o - < %s | llvm-objdump -d --macho --triple=thumbv7-apple-ios - | FileCheck %s
 .thumb
 .thumb_func _fib
 _fib:
diff --git a/llvm/test/MC/MachO/ARM/no-tls-assert.ll b/llvm/test/MC/MachO/ARM/no-tls-assert.ll
index 691700154d4db..0152c8286c21f 100644
--- a/llvm/test/MC/MachO/ARM/no-tls-assert.ll
+++ b/llvm/test/MC/MachO/ARM/no-tls-assert.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj -o - %s | llvm-objdump -section-headers - | FileCheck %s
+; RUN: llc -filetype=obj -o - %s | llvm-objdump --section-headers - | FileCheck %s
 ; This should not trigger the "Creating regular section after DWARF" assert.
 ; CHECK: __text
 ; CHECK: __thread_ptr  00000004
diff --git a/llvm/test/MC/MachO/darwin-sdk-version.ll b/llvm/test/MC/MachO/darwin-sdk-version.ll
index 5052e058eadd4..bb3db56337020 100644
--- a/llvm/test/MC/MachO/darwin-sdk-version.ll
+++ b/llvm/test/MC/MachO/darwin-sdk-version.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s
+; RUN: llc %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s
 ; RUN: llc %s -filetype=asm -o - | FileCheck --check-prefix=ASM %s
 
 target triple = "x86_64-apple-macos10.14";
diff --git a/llvm/test/MC/MachO/darwin-version-min-load-command.s b/llvm/test/MC/MachO/darwin-version-min-load-command.s
index 100faac04f823..ad43bd7235668 100644
--- a/llvm/test/MC/MachO/darwin-version-min-load-command.s
+++ b/llvm/test/MC/MachO/darwin-version-min-load-command.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -triple x86_64-apple-macosx10.10.0 %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s
-// RUN: llvm-mc -triple x86_64-apple-ios8.0.0 %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s --check-prefix=CHECK-IOS
-// RUN: llvm-mc -triple x86_64-apple-darwin %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s --check-prefix=CHECK-DARWIN
-// RUN: llvm-mc -triple x86_64-apple-ios13.0-macabi %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s --check-prefix=CHECK-MACCATALYST
+// RUN: llvm-mc -triple x86_64-apple-macosx10.10.0 %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s
+// RUN: llvm-mc -triple x86_64-apple-ios8.0.0 %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s --check-prefix=CHECK-IOS
+// RUN: llvm-mc -triple x86_64-apple-darwin %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s --check-prefix=CHECK-DARWIN
+// RUN: llvm-mc -triple x86_64-apple-ios13.0-macabi %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s --check-prefix=CHECK-MACCATALYST
 
 // Test version-min load command should be inferred from triple and should always be generated on Darwin
 // CHECK: Load command
@@ -17,8 +17,8 @@
 // CHECK-DARWIN-NOT: LC_VERSION_MIN
 
 
-// RUN: llvm-mc -triple x86_64-apple-watchos1.0.0 %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s --check-prefix=CHECK-WATCHOS
-// RUN: llvm-mc -triple x86_64-apple-tvos8.0.0 %s -filetype=obj -o - | llvm-objdump -macho -private-headers - | FileCheck %s --check-prefix=CHECK-TVOS
+// RUN: llvm-mc -triple x86_64-apple-watchos1.0.0 %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s --check-prefix=CHECK-WATCHOS
+// RUN: llvm-mc -triple x86_64-apple-tvos8.0.0 %s -filetype=obj -o - | llvm-objdump --macho --private-headers - | FileCheck %s --check-prefix=CHECK-TVOS
 // CHECK-WATCHOS: Load command
 // CHECK-WATCHOS:           cmd LC_VERSION_MIN_WATCHOS
 // CHECK-WATCHOS-NEXT:   cmdsize 16
diff --git a/llvm/test/MC/Mips/cfi-encoding.s b/llvm/test/MC/Mips/cfi-encoding.s
index 98a5ad1afe832..a4d643001df25 100644
--- a/llvm/test/MC/Mips/cfi-encoding.s
+++ b/llvm/test/MC/Mips/cfi-encoding.s
@@ -1,9 +1,9 @@
 # RUN: llvm-mc -filetype=obj -triple mips--gnu -g %s \
-# RUN:   | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=O32 %s
+# RUN:   | llvm-objdump -s --section=.eh_frame - | FileCheck --check-prefix=O32 %s
 # RUN: llvm-mc -filetype=obj -triple mips64--gnuabin32 -g %s \
-# RUN:   | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=N32 %s
+# RUN:   | llvm-objdump -s --section=.eh_frame - | FileCheck --check-prefix=N32 %s
 # RUN: llvm-mc -filetype=obj -triple mips64--gnuabi64 -g %s \
-# RUN:   | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=N64 %s
+# RUN:   | llvm-objdump -s --section=.eh_frame - | FileCheck --check-prefix=N64 %s
 
 # O32: 0000 00000010 00000000 017a5200 017c1f01
 # O32: 0010 0b0d1d00 00000010 00000018 00000000
diff --git a/llvm/test/MC/Mips/cpload.s b/llvm/test/MC/Mips/cpload.s
index 2c09fa2bbeca0..47025f9c95e61 100644
--- a/llvm/test/MC/Mips/cpload.s
+++ b/llvm/test/MC/Mips/cpload.s
@@ -3,15 +3,15 @@
 #
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu -mcpu=mips32r2 \
 # RUN:            -filetype=obj -o - \
-# RUN:  | llvm-objdump -d -r - | FileCheck %s -check-prefix=OBJ-O32
+# RUN:  | llvm-objdump -d -r - | FileCheck %s --check-prefix=OBJ-O32
 
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -mcpu=mips64r2 \
 # RUN:            -filetype=obj -o - \
-# RUN:  | llvm-objdump -d -r - | FileCheck %s -check-prefix=OBJ-N32
+# RUN:  | llvm-objdump -d -r - | FileCheck %s --check-prefix=OBJ-N32
 
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnu -mcpu=mips64r2 \
 # RUN:            -filetype=obj -o - \
-# RUN:  | llvm-objdump -d -r - | FileCheck %s -check-prefix=OBJ-N64
+# RUN:  | llvm-objdump -d -r - | FileCheck %s --check-prefix=OBJ-N64
 
 # ASM:    .text
 # ASM:    .option pic2
diff --git a/llvm/test/MC/Mips/cplocal.s b/llvm/test/MC/Mips/cplocal.s
index bfd9ba560b5de..a4f1299927494 100644
--- a/llvm/test/MC/Mips/cplocal.s
+++ b/llvm/test/MC/Mips/cplocal.s
@@ -9,10 +9,10 @@
 
 # RUN: llvm-mc -triple=mips64-unknown-linux-gnuabin32 \
 # RUN:         -position-independent -filetype=obj -o - %s \
-# RUN:   | llvm-objdump -d -r - | FileCheck -check-prefix=OBJ32 %s
+# RUN:   | llvm-objdump -d -r - | FileCheck --check-prefix=OBJ32 %s
 # RUN: llvm-mc -triple=mips64-unknown-linux-gnu \
 # RUN:         -position-independent -filetype=obj -o - %s \
-# RUN:   | llvm-objdump -d -r - | FileCheck -check-prefix=OBJ64 %s
+# RUN:   | llvm-objdump -d -r - | FileCheck --check-prefix=OBJ64 %s
 
 # ASM-PIC32:  .text
 # ASM-PIC32:  .cplocal $4
diff --git a/llvm/test/MC/Mips/cprestore-noreorder-noat.s b/llvm/test/MC/Mips/cprestore-noreorder-noat.s
index cba299eaf6abe..b661777824926 100644
--- a/llvm/test/MC/Mips/cprestore-noreorder-noat.s
+++ b/llvm/test/MC/Mips/cprestore-noreorder-noat.s
@@ -11,10 +11,10 @@
 # RUN:   | FileCheck %s -allow-empty -check-prefix=N32
 
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -filetype=obj -o - \
-# RUN:   | llvm-objdump -d -r - | FileCheck %s -check-prefix=NO-STORE
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=NO-STORE
 
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnu -filetype=obj -o - \
-# RUN:   | llvm-objdump -d -r - | FileCheck %s -check-prefix=NO-STORE
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=NO-STORE
 
   .text
   .ent foo
diff --git a/llvm/test/MC/Mips/cprestore-noreorder.s b/llvm/test/MC/Mips/cprestore-noreorder.s
index cd7a8c0b84e5a..4ae2f296ea361 100644
--- a/llvm/test/MC/Mips/cprestore-noreorder.s
+++ b/llvm/test/MC/Mips/cprestore-noreorder.s
@@ -3,7 +3,7 @@
 
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu --position-independent \
 # RUN:            -filetype=obj -o - \
-# RUN:   | llvm-objdump -d -r - | FileCheck %s -check-prefix=CHECK-FOR-STORE
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=CHECK-FOR-STORE
 
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu -mattr=+micromips \
 # RUN:            --position-independent -show-encoding \
diff --git a/llvm/test/MC/Mips/cprestore-reorder.s b/llvm/test/MC/Mips/cprestore-reorder.s
index 9666969b01594..6396824652e67 100644
--- a/llvm/test/MC/Mips/cprestore-reorder.s
+++ b/llvm/test/MC/Mips/cprestore-reorder.s
@@ -2,7 +2,7 @@
 # RUN:  FileCheck %s
 
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu --position-independent -filetype=obj -o -| \
-# RUN:  llvm-objdump -d -r - | FileCheck %s -check-prefix=CHECK-FOR-STORE
+# RUN:  llvm-objdump -d -r - | FileCheck %s --check-prefix=CHECK-FOR-STORE
 
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu -mattr=+micromips --position-independent -show-encoding | \
 # RUN:  FileCheck %s -check-prefix=MICROMIPS
diff --git a/llvm/test/MC/Mips/cpsetup.s b/llvm/test/MC/Mips/cpsetup.s
index 0e27a80bc3a5d..15e9c4db15f29 100644
--- a/llvm/test/MC/Mips/cpsetup.s
+++ b/llvm/test/MC/Mips/cpsetup.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 -filetype=obj -o - %s | \
-# RUN:   llvm-objdump -d -r -z - | FileCheck -check-prefixes=ALL,O32 %s
+# RUN:   llvm-objdump -d -r -z - | FileCheck --check-prefixes=ALL,O32 %s
 
 # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 %s | \
 # RUN:   FileCheck -check-prefixes=ASM,ASM-O32 %s
diff --git a/llvm/test/MC/Mips/expansion-j-sym-pic.s b/llvm/test/MC/Mips/expansion-j-sym-pic.s
index b04355593c66d..5856f56502976 100644
--- a/llvm/test/MC/Mips/expansion-j-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-j-sym-pic.s
@@ -13,11 +13,11 @@
 # Repeat the tests using ELF output.
 
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-O32
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-O32
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-NXX,ELF-N32
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-NXX,ELF-N32
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnu -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-NXX,ELF-N64
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-NXX,ELF-N64
 
   .weak weak_label
 
diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
index df7ac1bbbc5b0..b8429e108ab8a 100644
--- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s
@@ -25,17 +25,17 @@
 # direct objection emission match.
 
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-O32
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-O32
 # RUN: llvm-mc %s -triple mips-unknown-linux-gnu -mattr=+xgot -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-XO32
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-XO32
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-N32
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-N32
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -mattr=+xgot -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-XN32
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-XN32
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnu -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-N64
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-N64
 # RUN: llvm-mc %s -triple mips64-unknown-linux-gnu -mattr=+xgot -filetype=obj | \
-# RUN:   llvm-objdump -d -r - | FileCheck %s -check-prefixes=ELF-XN64
+# RUN:   llvm-objdump -d -r - | FileCheck %s --check-prefixes=ELF-XN64
 
   .weak weak_label
 
diff --git a/llvm/test/MC/Mips/higher-highest-addressing.s b/llvm/test/MC/Mips/higher-highest-addressing.s
index e3df151caab40..4eb27d4c0d30d 100644
--- a/llvm/test/MC/Mips/higher-highest-addressing.s
+++ b/llvm/test/MC/Mips/higher-highest-addressing.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
-# RUN:   | llvm-objdump -disassemble - | FileCheck %s
+# RUN:   | llvm-objdump -d - | FileCheck %s
 
 # RUN: llvm-mc -filetype=obj -triple=mips64el-unknown-linux -mcpu=mips64r2 %s \
 # RUN:   | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
diff --git a/llvm/test/MC/Mips/hilo-addressing.s b/llvm/test/MC/Mips/hilo-addressing.s
index 720c7e256bb10..960f5b705d5b8 100644
--- a/llvm/test/MC/Mips/hilo-addressing.s
+++ b/llvm/test/MC/Mips/hilo-addressing.s
@@ -2,7 +2,7 @@
 # RUN:  | FileCheck %s -check-prefix=CHECK-ENC
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux %s \
-# RUN:  | llvm-objdump -disassemble - | FileCheck %s -check-prefix=CHECK-INSTR
+# RUN:  | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INSTR
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux %s \
 # RUN:  | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
diff --git a/llvm/test/MC/Mips/micromips-neg-offset.s b/llvm/test/MC/Mips/micromips-neg-offset.s
index 212294f804abd..e821474c35a5b 100644
--- a/llvm/test/MC/Mips/micromips-neg-offset.s
+++ b/llvm/test/MC/Mips/micromips-neg-offset.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips -mcpu=mips32r6 %s -o - \
-# RUN:   | llvm-objdump -d -mattr=micromips - | FileCheck %s
+# RUN:   | llvm-objdump -d --mattr=micromips - | FileCheck %s
 
 # CHECK: 0:   8f 7e        beqzc16  $6, -4
 # CHECK: 2:   cf fe        bc16     -4
diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
index 7cdbd89f1d4f8..cb590a7df5cfd 100644
--- a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s
@@ -36,8 +36,6 @@
         neg.ps    $f19,$f13           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmadd.ps  $f27,$f4,$f9,$f25   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmsub.ps  $f6,$f12,$f14,$f17  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        pul.ps    $f9,$f30,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        puu.ps    $f24,$f9,$f2        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         sub.ps    $f5,$f14,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         c.eq.s    $fcc1, $f2, $f8     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
         c.f.s     $fcc4, $f2, $f7     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s
index d309385c3d8ed..bfce1e55b4baa 100644
--- a/llvm/test/MC/Mips/mips1/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s
@@ -73,6 +73,8 @@
         movz.s    $f25,$f7,$v1      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         pll.ps    $f25,$f9,$f30     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         plu.ps    $f1,$f26,$f29     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        pul.ps    $f9,$f30,$f26     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        puu.ps    $f24,$f9,$f2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.d $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.d $f6,$f4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
index 199f2ce3891d9..0bd2ef65489b6 100644
--- a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s
@@ -36,6 +36,4 @@
         neg.ps    $f19,$f13           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmadd.ps  $f27,$f4,$f9,$f25   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmsub.ps  $f6,$f12,$f14,$f17  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        pul.ps    $f9,$f30,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        puu.ps    $f24,$f9,$f2        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         sub.ps    $f5,$f14,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5.s b/llvm/test/MC/Mips/mips2/invalid-mips5.s
index 7485f6dcb7881..ad5f2b583f068 100644
--- a/llvm/test/MC/Mips/mips2/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips5.s
@@ -69,6 +69,8 @@
         movz.s    $f25,$f7,$v1    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         pll.ps    $f25,$f9,$f30   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         plu.ps    $f1,$f26,$f29   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        pul.ps    $f9,$f30,$f26     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        puu.ps    $f24,$f9,$f2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.d $f12,$f1        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s $f25,$f5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.l.d $f23,$f23       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
index 43b9bfdf06d45..19711ba05f280 100644
--- a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s
@@ -36,7 +36,5 @@
         neg.ps    $f19,$f13           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmadd.ps  $f27,$f4,$f9,$f25   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmsub.ps  $f6,$f12,$f14,$f17  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        pul.ps    $f9,$f30,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        puu.ps    $f24,$f9,$f2        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         sub.ps    $f5,$f14,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
 
diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5.s b/llvm/test/MC/Mips/mips3/invalid-mips5.s
index 15928d59a7d5d..31896e0392e65 100644
--- a/llvm/test/MC/Mips/mips3/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips3/invalid-mips5.s
@@ -32,6 +32,8 @@
         movz.s    $f25,$f7,$v1    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         pll.ps    $f25,$f9,$f30   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         plu.ps    $f1,$f26,$f29   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        pul.ps    $f9,$f30,$f26     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        puu.ps    $f24,$f9,$f2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         sdxc1     $f11,$a6($t2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         suxc1     $f12,$k1($t1)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         swxc1     $f19,$t0($k0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips3d/valid.s b/llvm/test/MC/Mips/mips3d/valid.s
new file mode 100644
index 0000000000000..bb90186d55109
--- /dev/null
+++ b/llvm/test/MC/Mips/mips3d/valid.s
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -show-encoding -triple=mips-unknown-unknown -mcpu=mips64r2 -mattr=mips3d %s | FileCheck %s
+#
+        .set noat
+        addr.ps $f7, $f11, $f3  # CHECK: addr.ps $f7, $f11, $f3  # encoding: [0x46,0xc3,0x59,0xd8]
+        cvt.ps.pw $f3, $f18     # CHECK: cvt.ps.pw $f3, $f18     # encoding: [0x46,0x80,0x90,0xe6]
+        cvt.pw.ps $f5, $f20     # CHECK: cvt.pw.ps $f5, $f20     # encoding: [0x46,0xc0,0xa1,0x64]
+        mulr.ps $f23, $f5, $f1  # CHECK: mulr.ps $f23, $f5, $f1  # encoding: [0x46,0xc1,0x2d,0xda]
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
index c7a07bf286b20..1a2f020cb9de8 100644
--- a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s
@@ -36,6 +36,4 @@
         neg.ps    $f19,$f13           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmadd.ps  $f27,$f4,$f9,$f25   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmsub.ps  $f6,$f12,$f14,$f17  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        pul.ps    $f9,$f30,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        puu.ps    $f24,$f9,$f2        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         sub.ps    $f5,$f14,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5.s b/llvm/test/MC/Mips/mips4/invalid-mips5.s
index 04526fc1e153f..2dc7681bd0382 100644
--- a/llvm/test/MC/Mips/mips4/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips4/invalid-mips5.s
@@ -11,4 +11,6 @@
         cvt.s.pl  $f30,$f1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         cvt.s.pu  $f14,$f25           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         pll.ps    $f25,$f9,$f30       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        plu.ps    $f1,$f26,$f29       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
\ No newline at end of file
+        plu.ps    $f1,$f26,$f29       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        pul.ps    $f9,$f30,$f26     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        puu.ps    $f24,$f9,$f2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips64extins.s b/llvm/test/MC/Mips/mips64extins.s
index c913b7ca41fe2..f82237ff1eadb 100644
--- a/llvm/test/MC/Mips/mips64extins.s
+++ b/llvm/test/MC/Mips/mips64extins.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
-# RUN:   | llvm-objdump -disassemble - | FileCheck --check-prefix=OBJ %s
+# RUN:   | llvm-objdump -d - | FileCheck --check-prefix=OBJ %s
 
 # RUN: llvm-mc -arch=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \
 # RUN:   | FileCheck --check-prefix=ASM %s
diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
index f043b6b934ef2..7c7ed52748282 100644
--- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
@@ -65,8 +65,6 @@
         nmsub.ps        $f6,$f12,$f14,$f17
         preceq.w.phl    $s8,$gp
         preceq.w.phr    $s5,$15
-        pul.ps          $f9,$f30,$f26
-        puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
         rorv            $13,$a3,$s5
         sbe             $s7,33($s1)
diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s
index c093102d75937..c7696ba455e4f 100644
--- a/llvm/test/MC/Mips/mips64r2/valid.s
+++ b/llvm/test/MC/Mips/mips64r2/valid.s
@@ -294,6 +294,12 @@ a:
         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLU_PS64
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        pul.ps $f9,$f30,$f26           # CHECK: pul.ps $f9, $f30, $f26  # encoding: [0x46,0xda,0xf2,0x6e]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUL_PS64
+
+        puu.ps $f24,$f9,$f2            # CHECK: puu.ps $f24, $f9, $f2   # encoding: [0x46,0xc2,0x4e,0x2f]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUU_PS64
+
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr     $sp,$11              # CHECK:      .set  push
diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s
index 319db7d6a83e5..4c368e5f12e27 100644
--- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s
@@ -68,8 +68,6 @@
         nmsub.ps        $f6,$f12,$f14,$f17
         preceq.w.phl    $s8,$gp
         preceq.w.phr    $s5,$15
-        pul.ps          $f9,$f30,$f26
-        puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
         rorv            $13,$a3,$s5
         sbe             $s7,33($s1)
diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s
index 84c2c443f7863..76c6f13bc21a5 100644
--- a/llvm/test/MC/Mips/mips64r3/valid.s
+++ b/llvm/test/MC/Mips/mips64r3/valid.s
@@ -288,6 +288,10 @@ a:
         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLU_PS64
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        pul.ps $f9,$f30,$f26           # CHECK: pul.ps $f9, $f30, $f26  # encoding: [0x46,0xda,0xf2,0x6e]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUL_PS64
+        puu.ps $f24,$f9,$f2            # CHECK: puu.ps $f24, $f9, $f2   # encoding: [0x46,0xc2,0x4e,0x2f]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUU_PS64
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr     $sp,$11              # CHECK:      .set  push
diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s
index 23805c5f0f86b..d75f2b2bb930c 100644
--- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s
@@ -68,8 +68,6 @@
         nmsub.ps        $f6,$f12,$f14,$f17
         preceq.w.phl    $s8,$gp
         preceq.w.phr    $s5,$15
-        pul.ps          $f9,$f30,$f26
-        puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
         rorv            $13,$a3,$s5
         sbe             $s7,33($s1)
diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s
index 13069d08992d0..540a832146f47 100644
--- a/llvm/test/MC/Mips/mips64r5/valid.s
+++ b/llvm/test/MC/Mips/mips64r5/valid.s
@@ -290,6 +290,10 @@ a:
         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLU_PS64
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        pul.ps $f9,$f30,$f26           # CHECK: pul.ps $f9, $f30, $f26  # encoding: [0x46,0xda,0xf2,0x6e]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUL_PS64
+        puu.ps $f24,$f9,$f2            # CHECK: puu.ps $f24, $f9, $f2   # encoding: [0x46,0xc2,0x4e,0x2f]
+                                       # CHECK:                         # <MCInst #{{[0-9]+}} PUU_PS64
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.
         rdhwr     $sp,$11              # CHECK:      .set  push
diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
index 0758164d0c77a..5125d0755c726 100644
--- a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s
@@ -28,7 +28,6 @@
         c.ule.ps        $fcc6,$f17,$f3      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         c.ult.ps        $fcc7,$f14,$f0      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         c.un.ps         $fcc4,$f2,$f26      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        cvt.ps.pw       $f3,$f18            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         madd.ps         $f22,$f3,$f14,$f3   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         mov.ps          $f22,$f17           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         movf.ps         $f10,$f28,$fcc6     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
@@ -40,6 +39,4 @@
         neg.ps          $f19,$f13           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmadd.ps        $f27,$f4,$f9,$f25   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         nmsub.ps        $f6,$f12,$f14,$f17  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        pul.ps          $f9,$f30,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
-        puu.ps          $f24,$f9,$f2        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         sub.ps          $f5,$f14,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5.s
index e7fd99a6b05bb..3d8daf36be2a5 100644
--- a/llvm/test/MC/Mips/mips64r6/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5.s
@@ -8,5 +8,11 @@
         bgezal    $0, 21100           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bgezal    $6, 21100           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltzal    $6, 21100           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        cvt.ps.pw $f3,$f18            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        cvt.pw.ps $f1, $f2            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         luxc1     $f19,$s6($s5)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        pll.ps    $f25,$f9,$f30     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        plu.ps    $f1,$f26,$f29     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        pul.ps    $f9,$f30,$f26     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        puu.ps    $f24,$f9,$f2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         suxc1     $f12,$k1($13)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips64shift.ll b/llvm/test/MC/Mips/mips64shift.ll
index 40a531b736da5..d36ef37b947e3 100644
--- a/llvm/test/MC/Mips/mips64shift.ll
+++ b/llvm/test/MC/Mips/mips64shift.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
-; RUN:   | llvm-objdump -disassemble - | FileCheck %s
+; RUN:   | llvm-objdump -d - | FileCheck %s
 
 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
-; RUN:   | llvm-objdump -disassemble - | FileCheck %s
+; RUN:   | llvm-objdump -d - | FileCheck %s
 
 define i64 @f3(i64 %a0) nounwind readnone {
 entry:
diff --git a/llvm/test/MC/Mips/mips_gprel16.s b/llvm/test/MC/Mips/mips_gprel16.s
index 72c6fa710c220..a2feb5a86f279 100644
--- a/llvm/test/MC/Mips/mips_gprel16.s
+++ b/llvm/test/MC/Mips/mips_gprel16.s
@@ -4,9 +4,9 @@
 // field.
 
 // RUN: llvm-mc -mcpu=mips32r2 -triple=mipsel-pc-linux -filetype=obj %s -o - \
-// RUN: | llvm-objdump -disassemble - | FileCheck %s
+// RUN: | llvm-objdump -d - | FileCheck %s
 // RUN: llvm-mc -mcpu=mips32r2 -triple=mips-pc-linux -filetype=obj %s -o - \
-// RUN: | llvm-objdump -disassemble - | FileCheck %s
+// RUN: | llvm-objdump -d - | FileCheck %s
 
 	.text
 	.abicalls
diff --git a/llvm/test/MC/Mips/nacl-mask.s b/llvm/test/MC/Mips/nacl-mask.s
index 17247a8d92f32..2248d61565f01 100644
--- a/llvm/test/MC/Mips/nacl-mask.s
+++ b/llvm/test/MC/Mips/nacl-mask.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
-# RUN:   | llvm-objdump -disassemble -z -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d -z --no-show-raw-insn - | FileCheck %s
 
 # This test tests that address-masking sandboxing is added when given assembly
 # input.
diff --git a/llvm/test/MC/Mips/sext_64_32.ll b/llvm/test/MC/Mips/sext_64_32.ll
index f5c4a87625d29..7b3e263a037cf 100644
--- a/llvm/test/MC/Mips/sext_64_32.ll
+++ b/llvm/test/MC/Mips/sext_64_32.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
-; RUN:   llvm-objdump -disassemble - | FileCheck %s
+; RUN:   llvm-objdump -d - | FileCheck %s
 
 ; Sign extend from 32 to 64 was creating nonsense opcodes
 
diff --git a/llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s b/llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s
index e58418f761fba..13b60ce9c6524 100644
--- a/llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s
+++ b/llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --filetype=obj -o - %s | \
-# RUN:   llvm-objdump -D  -r - | FileCheck -check-prefix=CHECK-BE %s
+# RUN:   llvm-objdump -D  -r - | FileCheck --check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --filetype=obj -o - %s | \
-# RUN:   llvm-objdump -D  -r - | FileCheck -check-prefix=CHECK-LE %s
+# RUN:   llvm-objdump -D  -r - | FileCheck --check-prefix=CHECK-LE %s
 
 # The purpose of this test is to check that when an alignment nop is added
 # it is added correctly with resepect to the labels in the .s file.
diff --git a/llvm/test/MC/PowerPC/ppc64-prefix-align.s b/llvm/test/MC/PowerPC/ppc64-prefix-align.s
index 6875e9dfb7a0f..80d2f0722a765 100644
--- a/llvm/test/MC/PowerPC/ppc64-prefix-align.s
+++ b/llvm/test/MC/PowerPC/ppc64-prefix-align.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --filetype=obj -o - %s | \
-# RUN:   llvm-objdump -D  -r - | FileCheck -check-prefix=CHECK-BE %s
+# RUN:   llvm-objdump -D  -r - | FileCheck --check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --filetype=obj -o - %s | \
-# RUN:   llvm-objdump -D  -r - | FileCheck -check-prefix=CHECK-LE %s
+# RUN:   llvm-objdump -D  -r - | FileCheck --check-prefix=CHECK-LE %s
 
 # The purpose of this test is to make sure that 8 byte instructions do not
 # cross 64 byte boundaries. If an 8 byte instruction is about to cross such
diff --git a/llvm/test/MC/RISCV/cnop.s b/llvm/test/MC/RISCV/cnop.s
index 20cd3724fe074..66f54d26e5e46 100644
--- a/llvm/test/MC/RISCV/cnop.s
+++ b/llvm/test/MC/RISCV/cnop.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
-# RUN:     | llvm-objdump -d -M no-aliases  - | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | llvm-objdump -d -M no-aliases  - | FileCheck --check-prefix=CHECK-INST %s
 
 # alpha and main are 8 byte alignment
 # but the alpha function's size is 6
diff --git a/llvm/test/MC/RISCV/compress-cjal.s b/llvm/test/MC/RISCV/compress-cjal.s
index 2313c3ef04a43..9e9cc52693dfb 100644
--- a/llvm/test/MC/RISCV/compress-cjal.s
+++ b/llvm/test/MC/RISCV/compress-cjal.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # c.jal is an rv32 only instruction.
diff --git a/llvm/test/MC/RISCV/compress-rv32d.s b/llvm/test/MC/RISCV/compress-rv32d.s
index 8cb11309715b3..c6e3085bfe1ff 100644
--- a/llvm/test/MC/RISCV/compress-rv32d.s
+++ b/llvm/test/MC/RISCV/compress-rv32d.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+d -d - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c,+d -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+d -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
@@ -14,10 +14,10 @@
 # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c,+d -d - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c,+d -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c,+d -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # Tests double precision floating point instructions available in rv32 and in rv64.
diff --git a/llvm/test/MC/RISCV/compress-rv32f.s b/llvm/test/MC/RISCV/compress-rv32f.s
index 69fc4f316938c..53bf8128e7d44 100644
--- a/llvm/test/MC/RISCV/compress-rv32f.s
+++ b/llvm/test/MC/RISCV/compress-rv32f.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+f -d - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c,+f -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+f -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c,+f -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # Instructions that are 32 bit only.
diff --git a/llvm/test/MC/RISCV/compress-rv32i.s b/llvm/test/MC/RISCV/compress-rv32i.s
index 909e49254209d..886b580db69c9 100644
--- a/llvm/test/MC/RISCV/compress-rv32i.s
+++ b/llvm/test/MC/RISCV/compress-rv32i.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \
@@ -14,10 +14,10 @@
 # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # CHECK-BYTES: 2e 85
diff --git a/llvm/test/MC/RISCV/compress-rv64i.s b/llvm/test/MC/RISCV/compress-rv64i.s
index 53cf7155a4ef4..6d45f398f670c 100644
--- a/llvm/test/MC/RISCV/compress-rv64i.s
+++ b/llvm/test/MC/RISCV/compress-rv64i.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # Tests compressed instructions available in rv64 and not in rv32.
diff --git a/llvm/test/MC/RISCV/csr-aliases.s b/llvm/test/MC/RISCV/csr-aliases.s
index 185448de6a66b..a7e935d75a12d 100644
--- a/llvm/test/MC/RISCV/csr-aliases.s
+++ b/llvm/test/MC/RISCV/csr-aliases.s
@@ -1,39 +1,39 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | llvm-objdump -d --mattr=-f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | llvm-objdump -d --mattr=-f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
-# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | llvm-objdump -d --mattr=-f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=-f - \
+# RUN:     | llvm-objdump -d --mattr=-f - \
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 
 
diff --git a/llvm/test/MC/RISCV/elf-header.s b/llvm/test/MC/RISCV/elf-header.s
index 29a7036f2fc6c..491d3bea4ce4b 100644
--- a/llvm/test/MC/RISCV/elf-header.s
+++ b/llvm/test/MC/RISCV/elf-header.s
@@ -3,7 +3,7 @@
 # RUN: llvm-mc %s -filetype=obj -triple=riscv64 | llvm-readobj -h \
 # RUN:     | FileCheck -check-prefix=RV64 %s
 
-# RV32: Format: ELF32-riscv
+# RV32: Format: elf32-littleriscv
 # RV32: Arch: riscv32
 # RV32: AddressSize: 32bit
 # RV32: ElfHeader {
@@ -22,7 +22,7 @@
 # RV32:   ]
 # RV32: }
 
-# RV64: Format: ELF64-riscv
+# RV64: Format: elf64-littleriscv
 # RV64: Arch: riscv64
 # RV64: AddressSize: 64bit
 # RV64: ElfHeader {
diff --git a/llvm/test/MC/RISCV/fixups-compressed.s b/llvm/test/MC/RISCV/fixups-compressed.s
index 3c39bf31952c9..5556b3d4eb2d1 100644
--- a/llvm/test/MC/RISCV/fixups-compressed.s
+++ b/llvm/test/MC/RISCV/fixups-compressed.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple riscv32 -mattr=+c -show-encoding \
 # RUN:     | FileCheck -check-prefix=CHECK-FIXUP %s
 # RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
-# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck -check-prefix=CHECK-INSTR %s
+# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=CHECK-INSTR %s
 # RUN: llvm-mc -filetype=obj -mattr=+c -triple=riscv32 %s \
 # RUN:     | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
 
diff --git a/llvm/test/MC/RISCV/function-call.s b/llvm/test/MC/RISCV/function-call.s
index d63db714b41d5..01cae43bf235f 100644
--- a/llvm/test/MC/RISCV/function-call.s
+++ b/llvm/test/MC/RISCV/function-call.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN:     | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 # RUN: llvm-mc -triple riscv32 < %s -show-encoding \
diff --git a/llvm/test/MC/RISCV/hilo-constaddr-expr.s b/llvm/test/MC/RISCV/hilo-constaddr-expr.s
index 48893757f8b55..6731ddd2b895a 100644
--- a/llvm/test/MC/RISCV/hilo-constaddr-expr.s
+++ b/llvm/test/MC/RISCV/hilo-constaddr-expr.s
@@ -1,9 +1,9 @@
 # RUN: not llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax %s 2>&1 \
 # RUN:     | FileCheck %s -check-prefix=CHECK-RELAX
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=-relax %s 2>&1 \
-# RUN:     | llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-INSTR
+# RUN:     | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INSTR
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=-relax %s 2>&1 \
-# RUN:     | llvm-objdump -r - | FileCheck %s -check-prefix=CHECK-REL
+# RUN:     | llvm-objdump -r - | FileCheck %s --check-prefix=CHECK-REL
 
 # Check the assembler rejects hi and lo expressions with constant expressions
 # involving labels when diff expressions are emitted as relocation pairs.
diff --git a/llvm/test/MC/RISCV/hilo-constaddr.s b/llvm/test/MC/RISCV/hilo-constaddr.s
index 9676d85bd9c34..7c7c03129ba59 100644
--- a/llvm/test/MC/RISCV/hilo-constaddr.s
+++ b/llvm/test/MC/RISCV/hilo-constaddr.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
-# RUN:  | llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-INSTR
+# RUN:  | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INSTR
 
 # RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
 # RUN:  | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
diff --git a/llvm/test/MC/RISCV/numeric-reg-names-d.s b/llvm/test/MC/RISCV/numeric-reg-names-d.s
index 97d3b58add9bc..44bbb0ee46097 100644
--- a/llvm/test/MC/RISCV/numeric-reg-names-d.s
+++ b/llvm/test/MC/RISCV/numeric-reg-names-d.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+f,+d < %s -riscv-arch-reg-names \
 # RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+d < %s \
-# RUN:     | llvm-objdump -mattr=+f,+d -d -M numeric - \
+# RUN:     | llvm-objdump --mattr=+f,+d -d -M numeric - \
 # RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
 
 # CHECK-NUMERIC: fsqrt.d f10, f0
diff --git a/llvm/test/MC/RISCV/numeric-reg-names-f.s b/llvm/test/MC/RISCV/numeric-reg-names-f.s
index 2f79648839e15..1bc984fdc3707 100644
--- a/llvm/test/MC/RISCV/numeric-reg-names-f.s
+++ b/llvm/test/MC/RISCV/numeric-reg-names-f.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+f < %s -riscv-arch-reg-names \
 # RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -mattr=+f -d -M numeric - \
+# RUN:     | llvm-objdump --mattr=+f -d -M numeric - \
 # RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
 
 # CHECK-NUMERIC: fsqrt.s f10, f0
diff --git a/llvm/test/MC/RISCV/option-mix.s b/llvm/test/MC/RISCV/option-mix.s
index a5f384ab0c5a5..30b9629f1d5e3 100644
--- a/llvm/test/MC/RISCV/option-mix.s
+++ b/llvm/test/MC/RISCV/option-mix.s
@@ -3,13 +3,13 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+relax | FileCheck -check-prefix=ASM %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+relax | FileCheck -check-prefix=ASM %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck -check-prefixes=DISASM,DISASM-NORELAX %s
+# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck --check-prefixes=DISASM,DISASM-NORELAX %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck -check-prefixes=DISASM,DISASM-NORELAX %s
+# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck --check-prefixes=DISASM,DISASM-NORELAX %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
-# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck -check-prefixes=DISASM,DISASM-RELAX %s
+# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck --check-prefixes=DISASM,DISASM-RELAX %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \
-# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck -check-prefixes=DISASM,DISASM-RELAX %s
+# RUN:   | llvm-objdump -d -M no-aliases - | FileCheck --check-prefixes=DISASM,DISASM-RELAX %s
 
 # Checks change of options does not cause error: could not find corresponding %pcrel_hi
 # when assembling pseudoinstruction and its extended form. Also checks that we
diff --git a/llvm/test/MC/RISCV/option-pushpop.s b/llvm/test/MC/RISCV/option-pushpop.s
index 230664ec40204..0754a74c58a38 100644
--- a/llvm/test/MC/RISCV/option-pushpop.s
+++ b/llvm/test/MC/RISCV/option-pushpop.s
@@ -3,7 +3,7 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
 # RUN: llvm-mc -triple riscv32 -filetype=obj < %s \
-# RUN:     | llvm-objdump  -triple riscv32 -mattr=+c -d - \
+# RUN:     | llvm-objdump  --triple=riscv32 --mattr=+c -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 
 # RUN: llvm-mc -triple riscv64 -mattr=-relax -riscv-no-aliases < %s \
@@ -11,7 +11,7 @@
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=CHECK-RELOC %s
 # RUN: llvm-mc -triple riscv64 -filetype=obj < %s \
-# RUN:     | llvm-objdump  -triple riscv64 -mattr=+c -d - \
+# RUN:     | llvm-objdump  --triple=riscv64 --mattr=+c -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 
 # Test the operation of the push and pop assembler directives when
diff --git a/llvm/test/MC/RISCV/option-rvc.s b/llvm/test/MC/RISCV/option-rvc.s
index e1762e7f2f16e..bb56367477606 100644
--- a/llvm/test/MC/RISCV/option-rvc.s
+++ b/llvm/test/MC/RISCV/option-rvc.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -triple riscv32 -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # RUN: llvm-mc -triple riscv64 -show-encoding < %s \
@@ -14,10 +14,10 @@
 # RUN: llvm-mc -triple riscv64 -show-encoding \
 # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
 # RUN: llvm-mc -triple riscv64 -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv64 -filetype=obj < %s \
-# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d -M no-aliases - \
+# RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d -M no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
 # CHECK-BYTES: 13 85 05 00
diff --git a/llvm/test/MC/RISCV/pseudo-jump.s b/llvm/test/MC/RISCV/pseudo-jump.s
index 48c5c830b2d24..1cc46cc0efa8a 100644
--- a/llvm/test/MC/RISCV/pseudo-jump.s
+++ b/llvm/test/MC/RISCV/pseudo-jump.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN:     | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 # RUN: llvm-mc -triple riscv32 < %s -show-encoding \
diff --git a/llvm/test/MC/RISCV/rv32-relaxation.s b/llvm/test/MC/RISCV/rv32-relaxation.s
index 5a54312ee67b3..a1a2172bf5a1e 100644
--- a/llvm/test/MC/RISCV/rv32-relaxation.s
+++ b/llvm/test/MC/RISCV/rv32-relaxation.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
-# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck -check-prefix=INSTR %s
+# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
-# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck -check-prefix=RELAX-INSTR %s
+# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
 
diff --git a/llvm/test/MC/RISCV/rv32a-valid.s b/llvm/test/MC/RISCV/rv32a-valid.s
index 55b11b2a33a24..2838b0d84fbff 100644
--- a/llvm/test/MC/RISCV/rv32a-valid.s
+++ b/llvm/test/MC/RISCV/rv32a-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
-# RUN:     | llvm-objdump -mattr=+a -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump -mattr=+a -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: lr.w t0, (t1)
diff --git a/llvm/test/MC/RISCV/rv32c-only-valid.s b/llvm/test/MC/RISCV/rv32c-only-valid.s
index f92c0232a6654..71de9448943ad 100644
--- a/llvm/test/MC/RISCV/rv32c-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-only-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
-# RUN:     | llvm-objdump -mattr=+c -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 \
diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s
index a13e0d279437b..ddfd6e01b1397 100644
--- a/llvm/test/MC/RISCV/rv32c-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-valid.s
@@ -1,12 +1,12 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
-# RUN:     | llvm-objdump -mattr=+c -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
-# RUN:     | llvm-objdump -mattr=+c -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # TODO: more exhaustive testing of immediate encoding.
diff --git a/llvm/test/MC/RISCV/rv32d-valid.s b/llvm/test/MC/RISCV/rv32d-valid.s
index 317e62116635d..be3e04503d6d3 100644
--- a/llvm/test/MC/RISCV/rv32d-valid.s
+++ b/llvm/test/MC/RISCV/rv32d-valid.s
@@ -1,12 +1,12 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+d -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+d < %s \
-# RUN:     | llvm-objdump -mattr=+d -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+d -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+d -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+d < %s \
-# RUN:     | llvm-objdump -mattr=+d -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+d -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # Support for the 'D' extension implies support for 'F'
diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s
index dd5c234f35753..0260c38ca1ba7 100644
--- a/llvm/test/MC/RISCV/rv32dc-valid.s
+++ b/llvm/test/MC/RISCV/rv32dc-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump -mattr=+c,+d -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c,+d -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 -mattr=+c \
diff --git a/llvm/test/MC/RISCV/rv32e-invalid.s b/llvm/test/MC/RISCV/rv32e-invalid.s
index efc5528904f2c..5e38c55818b9b 100644
--- a/llvm/test/MC/RISCV/rv32e-invalid.s
+++ b/llvm/test/MC/RISCV/rv32e-invalid.s
@@ -1,6 +1,6 @@
 # RUN: not llvm-mc -triple riscv32 -mattr=+e < %s 2>&1 | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \
-# RUN:     | llvm-objdump -mattr=+e -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+e -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefix=CHECK-DIS %s
 
 # Perform a simple sanity check that registers x16-x31 (and the equivalent
diff --git a/llvm/test/MC/RISCV/rv32f-valid.s b/llvm/test/MC/RISCV/rv32f-valid.s
index 64edbafdbd4ed..1d1e264433d6e 100644
--- a/llvm/test/MC/RISCV/rv32f-valid.s
+++ b/llvm/test/MC/RISCV/rv32f-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -mattr=+f -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+f -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -mattr=+f -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+f -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: flw ft0, 12(a0)
diff --git a/llvm/test/MC/RISCV/rv32fc-aliases-valid.s b/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
index c26b1de69b969..44e4153901d0c 100644
--- a/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+f < %s \
-# RUN:     | llvm-objdump -mattr=+c,+f -M no-aliases -d - \
+# RUN:     | llvm-objdump --mattr=+c,+f -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 
 # CHECK-EXPAND: c.flw fs0, 0(s1)
diff --git a/llvm/test/MC/RISCV/rv32fc-valid.s b/llvm/test/MC/RISCV/rv32fc-valid.s
index de2322ca3aa67..fcccb23ffebba 100644
--- a/llvm/test/MC/RISCV/rv32fc-valid.s
+++ b/llvm/test/MC/RISCV/rv32fc-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+f < %s \
-# RUN:     | llvm-objdump -mattr=+c,+f -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c,+f -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 -mattr=+c \
diff --git a/llvm/test/MC/RISCV/rv32m-valid.s b/llvm/test/MC/RISCV/rv32m-valid.s
index fcefdda034dd3..7dd9d94201b75 100644
--- a/llvm/test/MC/RISCV/rv32m-valid.s
+++ b/llvm/test/MC/RISCV/rv32m-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+m -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+m < %s \
-# RUN:     | llvm-objdump -mattr=+m -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+m -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m < %s \
-# RUN:     | llvm-objdump -mattr=+m -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+m -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: mul a4, ra, s0
diff --git a/llvm/test/MC/RISCV/rv64-relaxation.s b/llvm/test/MC/RISCV/rv64-relaxation.s
index 71ff34916d5d5..94d3e3379f54a 100644
--- a/llvm/test/MC/RISCV/rv64-relaxation.s
+++ b/llvm/test/MC/RISCV/rv64-relaxation.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
-# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck -check-prefix=INSTR %s
+# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
-# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck -check-prefix=RELAX-INSTR %s
+# RUN:     | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
 
diff --git a/llvm/test/MC/RISCV/rv64a-aliases-valid.s b/llvm/test/MC/RISCV/rv64a-aliases-valid.s
index fc14093a6a7f4..09999536af5a3 100644
--- a/llvm/test/MC/RISCV/rv64a-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64a-aliases-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+a \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump -d -mattr=+a -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+a -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump -d -mattr=+a - \
+# RUN:     | llvm-objdump -d --mattr=+a - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 # The below tests for lr.d, sc.d and amo*.d, using `0(reg)` are actually
diff --git a/llvm/test/MC/RISCV/rv64a-valid.s b/llvm/test/MC/RISCV/rv64a-valid.s
index 247903a93c5ea..7fe5d354685be 100644
--- a/llvm/test/MC/RISCV/rv64a-valid.s
+++ b/llvm/test/MC/RISCV/rv64a-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump -mattr=+a -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
diff --git a/llvm/test/MC/RISCV/rv64c-valid.s b/llvm/test/MC/RISCV/rv64c-valid.s
index 85933e96a83fe..b1868794f94d9 100644
--- a/llvm/test/MC/RISCV/rv64c-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
-# RUN:     | llvm-objdump -mattr=+c -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 #
diff --git a/llvm/test/MC/RISCV/rv64d-aliases-valid.s b/llvm/test/MC/RISCV/rv64d-aliases-valid.s
index fdadee87d4778..17a44b4f537eb 100644
--- a/llvm/test/MC/RISCV/rv64d-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64d-aliases-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+d \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
-# RUN:     | llvm-objdump -d -mattr=+d -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+d -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
-# RUN:     | llvm-objdump -d -mattr=+d - \
+# RUN:     | llvm-objdump -d --mattr=+d - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 ##===----------------------------------------------------------------------===##
diff --git a/llvm/test/MC/RISCV/rv64d-valid.s b/llvm/test/MC/RISCV/rv64d-valid.s
index 4b6062bb7b3ed..a8858ab770463 100644
--- a/llvm/test/MC/RISCV/rv64d-valid.s
+++ b/llvm/test/MC/RISCV/rv64d-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+d -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+d < %s \
-# RUN:     | llvm-objdump -mattr=+d -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+d -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 \
diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s
index 45b005ef73736..4a8aac967b3cc 100644
--- a/llvm/test/MC/RISCV/rv64dc-valid.s
+++ b/llvm/test/MC/RISCV/rv64dc-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump -mattr=+c,+d -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+c,+d -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv64 -mattr=+c \
diff --git a/llvm/test/MC/RISCV/rv64f-aliases-valid.s b/llvm/test/MC/RISCV/rv64f-aliases-valid.s
index 6076a19b24197..488d52fbb7f90 100644
--- a/llvm/test/MC/RISCV/rv64f-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64f-aliases-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+f \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 ##===----------------------------------------------------------------------===##
diff --git a/llvm/test/MC/RISCV/rv64f-valid.s b/llvm/test/MC/RISCV/rv64f-valid.s
index 43cac2847a34c..24e99a9876d02 100644
--- a/llvm/test/MC/RISCV/rv64f-valid.s
+++ b/llvm/test/MC/RISCV/rv64f-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -mattr=+f -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+f -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \
diff --git a/llvm/test/MC/RISCV/rv64m-valid.s b/llvm/test/MC/RISCV/rv64m-valid.s
index 4117a56ded5fb..ea99732e5e0c5 100644
--- a/llvm/test/MC/RISCV/rv64m-valid.s
+++ b/llvm/test/MC/RISCV/rv64m-valid.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+m -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m < %s \
-# RUN:     | llvm-objdump -mattr=+m -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+m -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: mulw ra, sp, gp
diff --git a/llvm/test/MC/RISCV/rva-aliases-valid.s b/llvm/test/MC/RISCV/rva-aliases-valid.s
index 705def5603794..a33b9ffd3cb4f 100644
--- a/llvm/test/MC/RISCV/rva-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rva-aliases-valid.s
@@ -7,16 +7,16 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+a \
 # RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+a < %s \
-# RUN:     | llvm-objdump -d -mattr=+a -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+a -M no-aliases - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+a < %s \
-# RUN:     | llvm-objdump -d -mattr=+a - \
+# RUN:     | llvm-objdump -d --mattr=+a - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump -d -mattr=+a -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+a -M no-aliases - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump -d -mattr=+a - \
+# RUN:     | llvm-objdump -d --mattr=+a - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
 
 # The following check prefixes are used in this test:
diff --git a/llvm/test/MC/RISCV/rvd-aliases-valid.s b/llvm/test/MC/RISCV/rvd-aliases-valid.s
index 4eab069507c2c..c46c0e3e2df17 100644
--- a/llvm/test/MC/RISCV/rvd-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvd-aliases-valid.s
@@ -7,16 +7,16 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+d \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \
-# RUN:     | llvm-objdump -d -mattr=+d -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+d -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \
-# RUN:     | llvm-objdump -d -mattr=+d - \
+# RUN:     | llvm-objdump -d --mattr=+d - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
-# RUN:     | llvm-objdump -d -mattr=+d -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+d -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
-# RUN:     | llvm-objdump -d -mattr=+d - \
+# RUN:     | llvm-objdump -d --mattr=+d - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 ##===----------------------------------------------------------------------===##
diff --git a/llvm/test/MC/RISCV/rvdc-aliases-valid.s b/llvm/test/MC/RISCV/rvdc-aliases-valid.s
index be3c3d9a2a04b..a1e0cc278776e 100644
--- a/llvm/test/MC/RISCV/rvdc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvdc-aliases-valid.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -riscv-no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump -mattr=+c,+d -M no-aliases -d - \
+# RUN:     | llvm-objdump --mattr=+c,+d -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump -mattr=+c,+d -M no-aliases -d - \
+# RUN:     | llvm-objdump --mattr=+c,+d -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 
 c.fld f8, (x9)
diff --git a/llvm/test/MC/RISCV/rvf-aliases-valid.s b/llvm/test/MC/RISCV/rvf-aliases-valid.s
index 0d8179ff31f92..3e34d88dc7b56 100644
--- a/llvm/test/MC/RISCV/rvf-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvf-aliases-valid.s
@@ -7,16 +7,16 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+f \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f -M no-aliases - \
+# RUN:     | llvm-objdump -d --mattr=+f -M no-aliases - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
 ##===----------------------------------------------------------------------===##
diff --git a/llvm/test/MC/RISCV/rvf-user-csr-names.s b/llvm/test/MC/RISCV/rvf-user-csr-names.s
index 3eca38468a36e..7b7569d4c6cd5 100644
--- a/llvm/test/MC/RISCV/rvf-user-csr-names.s
+++ b/llvm/test/MC/RISCV/rvf-user-csr-names.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
 # RUN:     | llvm-objdump -d - \
@@ -10,7 +10,7 @@
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | llvm-objdump -d --mattr=+f - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
 # RUN:     | llvm-objdump -d - \
diff --git a/llvm/test/MC/RISCV/tail-call.s b/llvm/test/MC/RISCV/tail-call.s
index 78c73c1dd3c1e..411ab7dd853b1 100644
--- a/llvm/test/MC/RISCV/tail-call.s
+++ b/llvm/test/MC/RISCV/tail-call.s
@@ -1,12 +1,12 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN:   | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN:   | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:   | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 # RUN: llvm-mc -triple riscv32 < %s -show-encoding \
 # RUN:   | FileCheck -check-prefix=FIXUP %s
 
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN:   | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN:   | llvm-objdump -d - | FileCheck --check-prefix=INSTR %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:   | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 # RUN: llvm-mc -triple riscv64 < %s -show-encoding \
diff --git a/llvm/test/MC/Sparc/sparc-relocations.s b/llvm/test/MC/Sparc/sparc-relocations.s
index 44e3cedc37d38..5c090a6f2edd4 100644
--- a/llvm/test/MC/Sparc/sparc-relocations.s
+++ b/llvm/test/MC/Sparc/sparc-relocations.s
@@ -1,7 +1,7 @@
 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=CHECK-OBJ
 
-        ! CHECK-OBJ: Format: ELF64-sparc
+        ! CHECK-OBJ: Format: elf64-sparc
         ! CHECK-OBJ: Relocations [
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_WDISP30 foo
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_LO10 sym
diff --git a/llvm/test/MC/SystemZ/directive-insn.s b/llvm/test/MC/SystemZ/directive-insn.s
index e647615efffce..f25082705c52e 100644
--- a/llvm/test/MC/SystemZ/directive-insn.s
+++ b/llvm/test/MC/SystemZ/directive-insn.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -triple s390x-linux-gnu -filetype=obj %s | \
-# RUN: llvm-objdump -mcpu=zEC12 -disassemble - | FileCheck %s
+# RUN: llvm-objdump --mcpu=zEC12 -d - | FileCheck %s
 
 # Test the .insn directive which provides a way of encoding an instruction
 # directly. It takes a format, encoding, and operands based on the format.
diff --git a/llvm/test/MC/WebAssembly/objdump.s b/llvm/test/MC/WebAssembly/objdump.s
index 947402a0a6143..99c8a32a20c49 100644
--- a/llvm/test/MC/WebAssembly/objdump.s
+++ b/llvm/test/MC/WebAssembly/objdump.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -o %t.o -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s
-# RUN: llvm-objdump -triple=wasm32-unknown-unknown -disassemble %t.o | FileCheck %s
+# RUN: llvm-objdump --triple=wasm32-unknown-unknown -d %t.o | FileCheck %s
 
 test0:
     .functype   test0 (i32, i64) -> (i32)
diff --git a/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s b/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s
index fbf5b5294460f..6dabafc394e99 100644
--- a/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s
+++ b/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - \
-# RUN:   | llvm-objdump -triple i386 -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump --triple=i386 -d --no-show-raw-insn - | FileCheck %s
 
 # !!! This test is auto-generated from utils/testgen/mc-bundling-x86-gen.py !!!
 #     It tests that bundle-aligned grouping works correctly in MC. Read the
diff --git a/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s b/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s
index 12786b34af72d..d486ec5fca00e 100644
--- a/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s
+++ b/llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s
@@ -1,5 +1,5 @@
 # RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - \
-# RUN:   | llvm-objdump -triple i386 -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump --triple=i386 -d --no-show-raw-insn - | FileCheck %s
 
 # !!! This test is auto-generated from utils/testgen/mc-bundling-x86-gen.py !!!
 #     It tests that bundle-aligned grouping works correctly in MC. Read the
diff --git a/llvm/test/MC/X86/AlignedBundling/different-sections.s b/llvm/test/MC/X86/AlignedBundling/different-sections.s
index 0af4a8f133e66..bc4f20132dbe7 100644
--- a/llvm/test/MC/X86/AlignedBundling/different-sections.s
+++ b/llvm/test/MC/X86/AlignedBundling/different-sections.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
 # Test two different executable sections with bundling.
 
diff --git a/llvm/test/MC/X86/AlignedBundling/labeloffset.s b/llvm/test/MC/X86/AlignedBundling/labeloffset.s
index 16c606bdda2b7..a3f0d4a40994e 100644
--- a/llvm/test/MC/X86/AlignedBundling/labeloffset.s
+++ b/llvm/test/MC/X86/AlignedBundling/labeloffset.s
@@ -1,9 +1,9 @@
 # RUN: llvm-mc -triple=i686-linux -filetype=obj %s -o - | \
-# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn -r - | FileCheck %s
 # RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \
-# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn -r - | FileCheck %s
 # RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \
-# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn -r - | FileCheck %s
 
         .bundle_align_mode 5
         .text
diff --git a/llvm/test/MC/X86/AlignedBundling/long-nop-pad.s b/llvm/test/MC/X86/AlignedBundling/long-nop-pad.s
index bd632f0206945..439915dfd0b5b 100644
--- a/llvm/test/MC/X86/AlignedBundling/long-nop-pad.s
+++ b/llvm/test/MC/X86/AlignedBundling/long-nop-pad.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
 # Test that long nops are generated for padding where possible.
 
diff --git a/llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s b/llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s
index 74a64739d51b1..3c86caa00ccef 100644
--- a/llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s
+++ b/llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s
@@ -1,8 +1,8 @@
 # RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
+# RUN:   | llvm-objdump -d --no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
 # RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
+# RUN:   | llvm-objdump -d --no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
 
         .text
diff --git a/llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s b/llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s
index 21e911d1ba1e5..d2aa92db71a79 100644
--- a/llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s
+++ b/llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s
@@ -1,8 +1,8 @@
 # RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
+# RUN:   | llvm-objdump -d --no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
 # RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
+# RUN:   | llvm-objdump -d --no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
 
         .text
diff --git a/llvm/test/MC/X86/AlignedBundling/nesting.s b/llvm/test/MC/X86/AlignedBundling/nesting.s
index dc433c926295b..e107a413521b3 100644
--- a/llvm/test/MC/X86/AlignedBundling/nesting.s
+++ b/llvm/test/MC/X86/AlignedBundling/nesting.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
 # Will be bundle-aligning to 16 byte boundaries
   .bundle_align_mode 4
diff --git a/llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s b/llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
index 8605b7c0137db..d725724f8fd44 100644
--- a/llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
+++ b/llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
 # Test some variations of padding to the end of a bundle.
 
diff --git a/llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s b/llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s
index 9b5393ab92b52..9e07b5994864b 100644
--- a/llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s
+++ b/llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
 # Test some variations of padding for bundle-locked groups.
 
diff --git a/llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s b/llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
index f59ecb08a3d1f..2c510f796e19f 100644
--- a/llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
+++ b/llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
 # Test that an instruction near a bundle end gets properly padded
 # after it is relaxed.
diff --git a/llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s b/llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
index 036249b906b45..2419a02f9ab74 100644
--- a/llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
+++ b/llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble - | FileCheck %s
+# RUN:   | llvm-objdump -d - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble - | FileCheck %s
+# RUN:   | llvm-objdump -d - | FileCheck %s
 
 # Test that instructions inside bundle-locked groups are relaxed even if their
 # fixup is short enough not to warrant relaxation on its own.
diff --git a/llvm/test/MC/X86/AlignedBundling/rodata-section.s b/llvm/test/MC/X86/AlignedBundling/rodata-section.s
index 21f2c735f8cb4..96871b4174a92 100644
--- a/llvm/test/MC/X86/AlignedBundling/rodata-section.s
+++ b/llvm/test/MC/X86/AlignedBundling/rodata-section.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - \
-# RUN:    | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:    | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - \
-# RUN:    | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+# RUN:    | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
 
   .bundle_align_mode 5
   .text
diff --git a/llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s b/llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s
index cb0ad8adba39b..f15a2b34d1847 100644
--- a/llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s
+++ b/llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-OPT %s
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - \
-# RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
+# RUN:   | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-RELAX %s
 
 # Test simple NOP insertion for single instructions.
 
diff --git a/llvm/test/MC/X86/Inputs/align-branch-64-1.s b/llvm/test/MC/X86/Inputs/align-branch-64-1.s
deleted file mode 100644
index e5ca17621d033..0000000000000
--- a/llvm/test/MC/X86/Inputs/align-branch-64-1.s
+++ /dev/null
@@ -1,43 +0,0 @@
-  .text
-  .globl  foo
-  .p2align  4
-foo:
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  cmp  %rax, %rbp
-  xorl %eax, %eax
-  cmp  %rax, %rbp
-  je  .L_2
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  xorl %eax, %eax
-  je  .L_2
-  popq  %rbp
-  je  .L_2
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  xorl %eax, %eax
-  jmp  .L_3
-  jmp  .L_3
-  jmp  .L_3
-  .rept 2
-  movl  %eax, %fs:0x1
-  .endr
-  movl  %eax, -4(%rbp)
-  popq  %rbp
-  cmp  %rax, %rbp
-  je  .L_2
-  jmp  .L_3
-.L_2:
-  movl  -12(%rbp), %eax
-  movl  %eax, -4(%rbp)
-.L_3:
-  .rept 10
-  movl  %esi, -1200(%rbp)
-  .endr
-  jmp  .L_3
-  retq
-
diff --git a/llvm/test/MC/X86/Inputs/align-branch-64-2.s b/llvm/test/MC/X86/Inputs/align-branch-64-2.s
deleted file mode 100644
index 16b854da71e29..0000000000000
--- a/llvm/test/MC/X86/Inputs/align-branch-64-2.s
+++ /dev/null
@@ -1,27 +0,0 @@
-  .text
-  .globl  foo
-  .p2align  4
-foo:
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  .rept 2
-  movl  %esi, -12(%rbp)
-  .endr
-  jmp  *%rax
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  movl  %esi, -12(%rbp)
-  pushq  %rbp
-  call *%rax
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  pushq  %rbp
-  call  foo
-  .rept 4
-  movl  %eax, %fs:0x1
-  .endr
-  call  *foo
-
diff --git a/llvm/test/MC/X86/align-branch-32-1a.s b/llvm/test/MC/X86/align-branch-32-1a.s
deleted file mode 100644
index ed11539d7d233..0000000000000
--- a/llvm/test/MC/X86/align-branch-32-1a.s
+++ /dev/null
@@ -1,38 +0,0 @@
-# Check NOP padding is disabled before instruction that has variant symbol operand.
-# RUN: llvm-mc -filetype=obj -triple i386-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 00000000 <foo>:
-# CHECK-COUNT-5:      : 64 a3 01 00 00 00                movl    %eax, %fs:1
-# CHECK:            1e: e8 fc ff ff ff                   calll   {{.*}}
-# CHECK-COUNT-4:      : 64 a3 01 00 00 00                movl    %eax, %fs:1
-# CHECK:            3b: 55                               pushl   %ebp
-# CHECK-NEXT:       3c: ff 91 00 00 00 00                calll   *(%ecx)
-# CHECK-COUNT-4:      : 64 a3 01 00 00 00                movl    %eax, %fs:1
-# CHECK:            5a: c1 e9 02                         shrl    $2, %ecx
-# CHECK-NEXT:       5d: 55                               pushl   %ebp
-# CHECK-NEXT:       5e: ff 10                            calll   *(%eax)
-# CHECK-COUNT-5:      : 64 a3 01 00 00 00                movl    %eax, %fs:1
-# CHECK-NEXT:       7e: ff 20                            jmpl    *(%eax)
-  .text
-  .globl  foo
-  .p2align  4
-foo:
-  .rept 5
-  movl  %eax, %fs:0x1
-  .endr
-  call    ___tls_get_addr@PLT
-  .rept 4
-  movl  %eax, %fs:0x1
-  .endr
-  pushl  %ebp
-  call *___tls_get_addr@GOT(%ecx)
-  .rept 4
-  movl  %eax, %fs:0x1
-  .endr
-  shrl  $2, %ecx
-  pushl %ebp
-  call *foo@tlscall(%eax)
-  .rept 5
-  movl  %eax, %fs:0x1
-  .endr
-  jmp  *foo@tlscall(%eax)
diff --git a/llvm/test/MC/X86/align-branch-32-work.s b/llvm/test/MC/X86/align-branch-32-work.s
new file mode 100644
index 0000000000000..44c13ef9d271c
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-32-work.s
@@ -0,0 +1,15 @@
+  # RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=jmp %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Check the branch align mechanism can work in 32-bit mode.
+
+  .text
+  .rept 31
+  int3
+  .endr
+  # CHECK:    20:          jmp
+  jmp bar
+
+
+  .type   bar,@function
+bar:
+  ret
diff --git a/llvm/test/MC/X86/align-branch-64-1a.s b/llvm/test/MC/X86/align-branch-64-1a.s
deleted file mode 100644
index 02818b295439f..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-1a.s
+++ /dev/null
@@ -1,43 +0,0 @@
-# Check only fused conditional jumps, conditional jumps and unconditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp %p/Inputs/align-branch-64-1.s -o %t1 && llvm-objdump -d %t1 | FileCheck %s
-
-# Check that -x86-branches-within-32B-boundaries matches the above command line
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-branches-within-32B-boundaries %p/Inputs/align-branch-64-1.s -o %t2
-# RUN: cmp %t1 %t2
-
-# Check no branches is aligned with option --x86-align-branch-boundary=0
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=0 --x86-align-branch=fused+jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - > %t3
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - > %t4
-# RUN: cmp %t3 %t4
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            18: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax
-# CHECK-COUNT-3:      : 90                               nop
-# CHECK:            20: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       23: 74 5d                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3d: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       3f: 90                               nop
-# CHECK-NEXT:       40: 74 40                            je      {{.*}}
-# CHECK-NEXT:       42: 5d                               popq    %rbp
-# CHECK-NEXT:       43: 74 3d                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            5d: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       5f: 90                               nop
-# CHECK-NEXT:       60: eb 26                            jmp     {{.*}}
-# CHECK-NEXT:       62: eb 24                            jmp     {{.*}}
-# CHECK-NEXT:       64: eb 22                            jmp     {{.*}}
-# CHECK-COUNT-2:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            76: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-NEXT:       79: 5d                               popq    %rbp
-# CHECK-NEXT:       7a: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       7d: 74 03                            je      {{.*}}
-# CHECK-NEXT:       7f: 90                               nop
-# CHECK-NEXT:       80: eb 06                            jmp     {{.*}}
-# CHECK-NEXT:       82: 8b 45 f4                         movl    -12(%rbp), %eax
-# CHECK-NEXT:       85: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-COUNT-10:     : 89 b5 50 fb ff ff                movl    %esi, -1200(%rbp)
-# CHECK:            c4: eb c2                            jmp     {{.*}}
-# CHECK-NEXT:       c6: c3                               retq
diff --git a/llvm/test/MC/X86/align-branch-64-1b.s b/llvm/test/MC/X86/align-branch-64-1b.s
deleted file mode 100644
index 73864ba89a87a..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-1b.s
+++ /dev/null
@@ -1,32 +0,0 @@
-# Check only fused conditional jumps and conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       18: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax
-# CHECK-COUNT-3:      : 90                               nop
-# CHECK-NEXT:       20: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       23: 74 5b                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3d: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       3f: 90                               nop
-# CHECK-NEXT:       40: 74 3e                            je      {{.*}}
-# CHECK-NEXT:       42: 5d                               popq    %rbp
-# CHECK-NEXT:       43: 74 3b                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            5d: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       5f: eb 25                            jmp     {{.*}}
-# CHECK-NEXT:       61: eb 23                            jmp     {{.*}}
-# CHECK-NEXT:       63: eb 21                            jmp     {{.*}}
-# CHECK-COUNT-2:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       75: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK:            78: 5d                               popq    %rbp
-# CHECK-NEXT:       79: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       7c: 74 02                            je      {{.*}}
-# CHECK-NEXT:       7e: eb 06                            jmp     {{.*}}
-# CHECK-NEXT:       80: 8b 45 f4                         movl    -12(%rbp), %eax
-# CHECK-NEXT:       83: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-COUNT-10:     : 89 b5 50 fb ff ff                movl    %esi, -1200(%rbp)
-# CHECK:            c2: eb c2                            jmp     {{.*}}
-# CHECK-NEXT:       c4: c3                               retq
diff --git a/llvm/test/MC/X86/align-branch-64-1c.s b/llvm/test/MC/X86/align-branch-64-1c.s
deleted file mode 100644
index 3207f540d2085..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-1c.s
+++ /dev/null
@@ -1,31 +0,0 @@
-# Check only conditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            18: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       1d: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       20: 74 5b                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3a: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       3c: 74 3f                            je      {{.*}}
-# CHECK-NEXT:       3e: 5d                               popq    %rbp
-# CHECK-NEXT:       3f: 90                               nop
-# CHECK-NEXT:       40: 74 3b                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            5a: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       5c: eb 25                            jmp     {{.*}}
-# CHECK-NEXT:       5e: eb 23                            jmp     {{.*}}
-# CHECK-NEXT:       60: eb 21                            jmp     {{.*}}
-# CHECK-COUNT-2:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            72: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-NEXT:       75: 5d                               popq    %rbp
-# CHECK-NEXT:       76: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       79: 74 02                            je      {{.*}}
-# CHECK-NEXT:       7b: eb 06                            jmp     {{.*}}
-# CHECK-NEXT:       7d: 8b 45 f4                         movl    -12(%rbp), %eax
-# CHECK-NEXT:       80: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-COUNT-10:     : 89 b5 50 fb ff ff                movl    %esi, -1200(%rbp)
-# CHECK:            bf: eb c2                            jmp     {{.*}}
-# CHECK-NEXT:       c1: c3                               retq
diff --git a/llvm/test/MC/X86/align-branch-64-1d.s b/llvm/test/MC/X86/align-branch-64-1d.s
deleted file mode 100644
index 902bb69fec168..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-1d.s
+++ /dev/null
@@ -1,38 +0,0 @@
-# Check only conditional jumps and unconditional jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - > %t1
-# RUN: FileCheck --input-file=%t1 %s --check-prefixes=CHECK,SHORT-NOP
-
-# Check long NOP can be emitted to align branch if the target cpu support long nop.
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 -mcpu=x86-64 --x86-align-branch=jcc+jmp %p/Inputs/align-branch-64-1.s | llvm-objdump -d  - >%t2
-# RUN: FileCheck --input-file=%t2 %s --check-prefixes=CHECK,LONG-NOP
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            18: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       1b: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       1d: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       20: 74 5d                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3a: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       3c: 74 41                            je      {{.*}}
-# CHECK-NEXT:       3e: 5d                               popq    %rbp
-# CHECK-NEXT:       3f: 90                               nop
-# CHECK-NEXT:       40: 74 3d                            je      {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            5a: 31 c0                            xorl    %eax, %eax
-# CHECK-NEXT:       5c: eb 27                            jmp     {{.*}}
-# SHORT-NOP-COUNT-2:  : 90                               nop
-# LONG-NOP:         5e: 66 90                            nop
-# CHECK-NEXT:       60: eb 23                            jmp     {{.*}}
-# CHECK-NEXT:       62: eb 21                            jmp     {{.*}}
-# CHECK-COUNT-2:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            74: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-NEXT:       77: 5d                               popq    %rbp
-# CHECK-NEXT:       78: 48 39 c5                         cmpq    %rax, %rbp
-# CHECK-NEXT:       7b: 74 02                            je      {{.*}}
-# CHECK-NEXT:       7d: eb 06                            jmp     {{.*}}
-# CHECK-NEXT:       7f: 8b 45 f4                         movl    -12(%rbp), %eax
-# CHECK-NEXT:       82: 89 45 fc                         movl    %eax, -4(%rbp)
-# CHECK-COUNT-10:     : 89 b5 50 fb ff ff                movl    %esi, -1200(%rbp)
-# CHECK:            c1: eb c2                            jmp     {{.*}}
-# CHECK-NEXT:       c3: c3                               retq
diff --git a/llvm/test/MC/X86/align-branch-64-2a.s b/llvm/test/MC/X86/align-branch-64-2a.s
deleted file mode 100644
index f7a61c3499f03..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-2a.s
+++ /dev/null
@@ -1,17 +0,0 @@
-# Check only indirect jumps are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect %p/Inputs/align-branch-64-2.s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-COUNT-2:      : 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-COUNT-2:      : 90                               nop
-# CHECK:            20: ff e0                            jmpq    *%rax
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3a: 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-NEXT:       3d: 55                               pushq   %rbp
-# CHECK-NEXT:       3e: ff d0                            callq   *%rax
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       58: 55                               pushq   %rbp
-# CHECK-NEXT:       59: e8 00 00 00 00                   callq   {{.*}}
-# CHECK-COUNT-4:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            7e: ff 14 25 00 00 00 00             callq   *0
diff --git a/llvm/test/MC/X86/align-branch-64-2b.s b/llvm/test/MC/X86/align-branch-64-2b.s
deleted file mode 100644
index d483cda996110..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-2b.s
+++ /dev/null
@@ -1,17 +0,0 @@
-# Check only calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=call
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=call %p/Inputs/align-branch-64-2.s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-COUNT-2:      : 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK:            1e: ff e0                            jmpq    *%rax
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            38: 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-NEXT:       3b: 55                               pushq    %rbp
-# CHECK-NEXT:       3c: ff d0                            callq    *%rax
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl     %eax, %fs:1
-# CHECK:            56: 55                               pushq    %rbp
-# CHECK-NEXT:       57: e8 00 00 00 00                   callq    {{.*}}
-# CHECK-COUNT-4:      : 64 89 04 25 01 00 00 00          movl     %eax, %fs:1
-# CHECK-COUNT-4:      : 90                               nop
-# CHECK:            80: ff 14 25 00 00 00 00             callq    *0
diff --git a/llvm/test/MC/X86/align-branch-64-2c.s b/llvm/test/MC/X86/align-branch-64-2c.s
deleted file mode 100644
index 9c047f0f6a246..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-2c.s
+++ /dev/null
@@ -1,19 +0,0 @@
-# Check only indirect jumps and calls are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=indirect+call
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=indirect+call %p/Inputs/align-branch-64-2.s  | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-COUNT-2:      : 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-COUNT-2:      : 90                               nop
-# CHECK:            20: ff e0                            jmpq    *%rax
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3a: 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-NEXT:       3d: 55                               pushq    %rbp
-# CHECK-COUNT-2:      : 90                               nop
-# CHECK:            40: ff d0                            callq    *%rax
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            5a: 55                               pushq    %rbp
-# CHECK-COUNT-5:      : 90                               nop
-# CHECK:            60: e8 00 00 00 00                   callq   {{.*}}
-# CHECK-COUNT-4:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            85: ff 14 25 00 00 00 00             callq    *0
diff --git a/llvm/test/MC/X86/align-branch-64-3a.s b/llvm/test/MC/X86/align-branch-64-3a.s
deleted file mode 100644
index 3df9347cad308..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-3a.s
+++ /dev/null
@@ -1,41 +0,0 @@
-# Check NOP padding is disabled before instruction that has variant symbol operand.
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=jmp+call %s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-COUNT-2:      : 48 89 e5                         movq    %rsp, %rbp
-# CHECK:            1e: e8 00 00 00 00                   callq   {{.*}}
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            3b: 55                               pushq   %rbp
-# CHECK-NEXT:       3c: 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-NEXT:       3f: ff 15 00 00 00 00                callq   *(%rip)
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            5d: ff 15 00 00 00 00                callq   *(%rip)
-# CHECK-NEXT-3:       : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            7b: ff 25 00 00 00 00                jmpq    *(%rip)
-
-  .text
-  .globl  foo
-  .p2align  4
-foo:
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  .rept 2
-  movq  %rsp, %rbp
-  .endr
-  call    __tls_get_addr@PLT
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  pushq  %rbp
-  movl  %esi, -12(%rbp)
-  call    *__tls_get_addr@GOTPCREL(%rip)
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  call *foo@GOTPCREL(%rip)
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  jmp  *foo@GOTPCREL(%rip)
diff --git a/llvm/test/MC/X86/align-branch-64-4a.s b/llvm/test/MC/X86/align-branch-64-4a.s
deleted file mode 100644
index e7b1e8c9d87b6..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-4a.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# Check only rets are aligned with option --x86-align-branch-boundary=32 --x86-align-branch=ret
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=ret %s | llvm-objdump -d  - | FileCheck %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-COUNT-2:      : 48 89 e5                         movq    %rsp, %rbp
-# CHECK:            1e: 5a                               popq    %rdx
-# CHECK-NEXT:       1f: 90                               nop
-# CHECK-NEXT:       20: c3                               retq
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            39: 89 75 f4                         movl    %esi, -12(%rbp)
-# CHECK-NEXT:       3c: 31 c0                            xorl    %eax, %eax
-# CHECK-COUNT-2:      : 90                               nop
-# CHECK:            40: c2 1e 00                         retq    $30
-
-  .text
-  .globl  foo
-  .p2align  4
-foo:
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  .rept 2
-  movq  %rsp, %rbp
-  .endr
-  popq  %rdx
-  ret
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  movl  %esi, -12(%rbp)
-  xorl %eax, %eax
-  ret $30
diff --git a/llvm/test/MC/X86/align-branch-64-5a.s b/llvm/test/MC/X86/align-branch-64-5a.s
deleted file mode 100644
index b78b743b88dad..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-5a.s
+++ /dev/null
@@ -1,43 +0,0 @@
-# Check no nop is inserted if no branch cross or is against the boundary
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret  %s | llvm-objdump -d  - > %t1
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %s | llvm-objdump -d  - > %t2
-# RUN: cmp %t1 %t2
-# RUN: FileCheck --input-file=%t1 %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-COUNT-3:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            18: c1 e9 02                         shrl    $2, %ecx
-# CHECK-NEXT:       1b: 89 d1                            movl    %edx, %ecx
-# CHECK-NEXT:       1d: 75 fc                            jne     {{.*}}
-# CHECK-NEXT:       1f: 55                               pushq   %rbp
-# CHECK-NEXT:       20: f6 c2 02                         testb   $2, %dl
-# CHECK-NEXT:       23: 75 fa                            jne     {{.*}}
-# CHECK-COUNT-2:      : 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK:            35: c1 e9 02                         shrl    $2, %ecx
-# CHECK-NEXT:       38: e8 c3 ff ff ff                   callq   {{.*}}
-# CHECK-NEXT:       3d: ff e0                            jmpq    *%rax
-# CHECK-NEXT:       3f: 55                               pushq   %rbp
-# CHECK-NEXT:       40: c2 63 00                         retq    $99
-
-    .text
-    .p2align 4
-foo:
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  shrl  $2, %ecx
-.L1:
-  movl  %edx, %ecx
-  jne   .L1
-.L2:
-  push  %rbp
-  testb $2, %dl
-  jne    .L2
-  .rept 2
-  movl  %eax, %fs:0x1
-  .endr
-  shrl  $2, %ecx
-  call  foo
-  jmp   *%rax
-  push  %rbp
-  ret   $99
diff --git a/llvm/test/MC/X86/align-branch-64-6a.s b/llvm/test/MC/X86/align-branch-64-6a.s
deleted file mode 100644
index 0a78eb556fa73..0000000000000
--- a/llvm/test/MC/X86/align-branch-64-6a.s
+++ /dev/null
@@ -1,50 +0,0 @@
-# Check option --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret can cowork with option --mc-relax-all
-# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp+indirect+call+ret --mc-relax-all %s | llvm-objdump -d  - > %t1
-# RUN: FileCheck --input-file=%t1 %s
-
-# CHECK: 0000000000000000 <foo>:
-# CHECK-NEXT:        0: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:        8: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       10: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       18: c1 e9 02                         shrl    $2, %ecx
-# CHECK-NEXT:       1b: 89 d1                            movl    %edx, %ecx
-# CHECK-NEXT:       1d: 90                               nop
-# CHECK-NEXT:       1e: 90                               nop
-# CHECK-NEXT:       1f: 90                               nop
-# CHECK-NEXT:       20: 0f 85 f5 ff ff ff                jne     {{.*}}
-# CHECK-NEXT:       26: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       2e: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       36: f6 c2 02                         testb   $2, %dl
-# CHECK-NEXT:       39: 0f 85 e7 ff ff ff                jne     {{.*}}
-# CHECK-NEXT:       3f: 90                               nop
-# CHECK-NEXT:       40: e9 d6 ff ff ff                   jmp     {{.*}}
-# CHECK-NEXT:       45: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       4d: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       55: 64 89 04 25 01 00 00 00          movl    %eax, %fs:1
-# CHECK-NEXT:       5d: 90                               nop
-# CHECK-NEXT:       5e: 90                               nop
-# CHECK-NEXT:       5f: 90                               nop
-# CHECK-NEXT:       60: e8 9b ff ff ff                   callq   {{.*}}
-# CHECK-NEXT:       65: e9 bc ff ff ff                   jmp     {{.*}}
-    .text
-    .p2align 4
-foo:
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  shrl  $2, %ecx
-.L1:
-  movl  %edx, %ecx
-  jne   .L1
-.L2:
-  .rept 2
-  movl  %eax, %fs:0x1
-  .endr
-  testb $2, %dl
-  jne   .L2
-  jmp   .L1
-  .rept 3
-  movl  %eax, %fs:0x1
-  .endr
-  call  foo
-  jmp   .L2
diff --git a/llvm/test/MC/X86/align-branch-64-align.s b/llvm/test/MC/X86/align-branch-64-align.s
new file mode 100644
index 0000000000000..d5bed5b4ab695
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-align.s
@@ -0,0 +1,26 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+call %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Exercise some corner cases related to align directive.
+
+  .text
+  # Check the align directive between the macro fused pair
+  # does not make code crazy.
+  # CHECK:     0:          cmpq    %rax, %rbp
+  # CHECK:     3:          nop
+  # CHECK:     4:          jne
+  cmp  %rax, %rbp
+  .p2align  1
+  jne bar
+
+  .rept 24
+  int3
+  .endr
+  .p2align  1
+  # Check we can ensure this call not cross or end at boundary when there
+  # is a align directive before it.
+  # CHECK:    20:          callq    *%rax
+  call  *%rax
+
+  .type   bar,@function
+bar:
+  retq
diff --git a/llvm/test/MC/X86/align-branch-64.s b/llvm/test/MC/X86/align-branch-64-basic.s
similarity index 100%
rename from llvm/test/MC/X86/align-branch-64.s
rename to llvm/test/MC/X86/align-branch-64-basic.s
diff --git a/llvm/test/MC/X86/align-branch-64-7a.s b/llvm/test/MC/X86/align-branch-64-bundle.s
similarity index 100%
rename from llvm/test/MC/X86/align-branch-64-7a.s
rename to llvm/test/MC/X86/align-branch-64-bundle.s
diff --git a/llvm/test/MC/X86/align-branch-64-fused.s b/llvm/test/MC/X86/align-branch-64-fused.s
new file mode 100644
index 0000000000000..750afd7137444
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-fused.s
@@ -0,0 +1,42 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Exercise cases where fused instructions need to be aligned.
+
+  .text
+  .globl  foo
+foo:
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # 'cmp  %rax, %rbp' is macro fused with 'jne foo',
+  # so we need to align the pair.
+  # CHECK:    20:          cmpq    %rax, %rbp
+  # CHECK:    23:          jne
+  cmp  %rax, %rbp
+  jne foo
+  int3
+
+  .p2align  5
+  .rept 28
+  int3
+  .endr
+  # 'cmp  %rax, %rbp' is fusible but can not fused with `jo foo`,
+  # so we only need to align 'jo foo'.
+  # CHECK:    5c:          cmpq    %rax, %rbp
+  cmp  %rax, %rbp
+  # CHECK:    60:          jo
+  jo foo
+  int3
+
+  .p2align  5
+  .rept 26
+  int3
+  .endr
+  # The second 'cmp  %rax, %rbp' is macro fused with 'jne foo'.
+  cmp  %rax, %rbp
+  # CHECK:    a0:          cmpq    %rax, %rbp
+  # CHECK:    a3:          jne
+  cmp  %rax, %rbp
+  jne foo
+  int3
diff --git a/llvm/test/MC/X86/align-branch-64-general.s b/llvm/test/MC/X86/align-branch-64-general.s
new file mode 100644
index 0000000000000..f354cc7c97205
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-general.s
@@ -0,0 +1,49 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp %s -o %t1
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-branches-within-32B-boundaries %s -o %t2
+  # RUN: cmp %t1 %t2
+
+  # Check the general option --x86-branches-within-32B-boundaries is equivelent
+  # to the fined options --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+jmp.
+
+  .text
+  .globl  foo
+  .p2align  5
+foo:
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  js foo
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  jmp foo
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  jmp  *%rcx
+
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  call  foo
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  ret $0
+
+
+  .p2align  5
+  .rept 29
+  int3
+  .endr
+  cmp  %rax, %rbp
+  je  foo
diff --git a/llvm/test/MC/X86/align-branch-64-hardcode.s b/llvm/test/MC/X86/align-branch-64-hardcode.s
new file mode 100644
index 0000000000000..103e90534762d
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-hardcode.s
@@ -0,0 +1,32 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=jmp+call %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Exercise cases where instructions to be aligned is after hardcode
+  # and thus can't add a nop in between without changing semantic.
+
+  .text
+
+  # CHECK: 1d:       int3
+  # CHECK: 1e:       jmp
+  # CHECK: 24:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  .byte 0x2e
+  jmp baz
+  int3
+
+  # CHECK: 5d:       int3
+  # CHECK: 5e:       call
+  # CHECK: 66:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  .byte 0x66
+  call *___tls_get_addr@GOT(%ecx)
+  int3
+
+  .section ".text.other"
+bar:
+  retq
diff --git a/llvm/test/MC/X86/align-branch-64-mixed.s b/llvm/test/MC/X86/align-branch-64-mixed.s
new file mode 100644
index 0000000000000..2fa46fe71e9ca
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-mixed.s
@@ -0,0 +1,51 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=jcc+jmp+indirect+call+ret %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Exercise cases where mixed kinds of branch are asked to be aligned.
+
+  .text
+  .globl  labeled_mixed_test1
+labeled_mixed_test1:
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # This call should have started at 0x1e and ends at 0x23, so two bytes of
+  # padding are inserted before it.
+  # CHECK:    20:          callq
+  call  bar
+  .rept 28
+  int3
+  .endr
+  # If the previous call was not aligned, this jmp should have started at 0x3f
+  # and need two bytes of padding. After the two bytes of padding are inserted
+  # for the call, this jmp starts at 0xa1 and does not need padding.
+  # CHECK:    41:          jmp
+  jmp  *%rax
+
+  .globl  labeled_mixed_test2
+labeled_mixed_test2:
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # This jne should have started at 0x7e, so two bytes of padding are inserted
+  # before it.
+  # CHECK:    80:          jne
+  jne bar
+  .rept 28
+  int3
+  .endr
+  # If the previous jne was not aligned, this jmp should have started at 0x3c.
+  # After the two bytes of padding are inserted for the jne, this jmp should
+  # have started at 0x9e, so two bytes of padding are inserted and it starts at
+  # 0xa0.
+  # CHECK:    a0:          jmp
+  jmp bar
+
+  .globl  labeled_mixed_test3
+labeled_mixed_test3:
+  .p2align 5
+  .type   bar,@function
+bar:
+  # CHECK:    c0:          retq
+  retq
diff --git a/llvm/test/MC/X86/align-branch-64-necessary.s b/llvm/test/MC/X86/align-branch-64-necessary.s
new file mode 100644
index 0000000000000..960bb92ed703c
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-necessary.s
@@ -0,0 +1,54 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc+indirect+call+ret %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Check if no instruction crosses or is against the boundary,
+  # there will be no extra padding.
+
+  .text
+  .globl  foo
+  .p2align  5
+foo:
+  .p2align  5
+  .rept 24
+  int3
+  .endr
+  # CHECK:    18:          js
+  js foo
+
+  .p2align  5
+  .rept 24
+  int3
+  .endr
+  # CHECK:    38:          jmp
+  jmp foo
+
+  .p2align  5
+  .rept 24
+  int3
+  .endr
+  # CHECK:    58:          jmpq    *%rcx
+  jmp  *%rcx
+
+
+  .p2align  5
+  .rept 24
+  int3
+  .endr
+  # CHECK:    78:          callq
+  call  foo
+
+  .p2align  5
+  .rept 27
+  int3
+  .endr
+  # CHECK:    9b:          retq    $0
+  ret $0
+
+
+  .p2align  5
+  .rept 21
+  int3
+  .endr
+  # CHECK:    b5:          cmpq    %rax, %rbp
+  # CHECK:    b8:          je
+  cmp  %rax, %rbp
+  je  foo
diff --git a/llvm/test/MC/X86/align-branch-64-relax-all.s b/llvm/test/MC/X86/align-branch-64-relax-all.s
new file mode 100644
index 0000000000000..112629608f2d9
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-relax-all.s
@@ -0,0 +1,42 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=fused+jcc --mc-relax-all %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Check instructions can be aligned correctly along with option --mc-relax-all
+
+  .text
+  .global foo
+foo:
+  .p2align  5
+  .rept 25
+  int3
+  .endr
+  # CHECK:    19:          jne
+  # CHECK:    1f:          int3
+  jne   foo
+  int3
+
+  .p2align  5
+  .rept 27
+  int3
+  .endr
+  # CHECK:    40:          jne
+  jne   foo
+
+  .p2align  5
+  .rept 22
+  int3
+  .endr
+  # CHECK:    76:          testb    $2, %dl
+  # CHECK:    79:          jne
+  # CHECK:    7f:          int3
+  testb $2, %dl
+  jne   foo
+  int3
+
+  .p2align  5
+  .rept 27
+  int3
+  .endr
+  # CHECK:    a0:          testb    $2, %dl
+  # CHECK:    a3:          jne
+  testb $2, %dl
+  jne   foo
diff --git a/llvm/test/MC/X86/align-branch-64-section-size.s b/llvm/test/MC/X86/align-branch-64-section-size.s
new file mode 100644
index 0000000000000..e4c9fbf3f0394
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-section-size.s
@@ -0,0 +1,20 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=ret %s | llvm-readobj -S | FileCheck %s
+
+  # Check the aligment of section that contains instructions to be aligned
+  # is correctly set.
+
+  # CHECK:  Name: text1
+  # CHECK:  AddressAlignment: 32
+  .section text1
+foo:
+  ret
+
+  # CHECK:  Name: text2
+  # CHECK:  AddressAlignment: 1
+  .section text2
+  nop
+
+  # CHECK:  Name: text3
+  # CHECK:  AddressAlignment: 1
+  .section text3
+  jmp foo
diff --git a/llvm/test/MC/X86/align-branch-64-single.s b/llvm/test/MC/X86/align-branch-64-single.s
new file mode 100644
index 0000000000000..54ac2e4ae5733
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-64-single.s
@@ -0,0 +1,93 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=jcc %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=JCC 
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=jmp %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=JMP
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=indirect %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=IND
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=CAL
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=ret %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=RET
+
+  # Exercise cases where only one kind of instruction is asked to be aligned.
+  # Fused instruction cases are excluded.
+
+  .text
+  .globl  foo
+  .p2align  5
+foo:
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # JCC:    20:          jne
+  # JMP:    1e:          jne
+  # IND:    1e:          jne
+  # CAL:    1e:          jne
+  # RET:    1e:          jne
+  jne foo
+  int3
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # JCC:    5e:          jmp
+  # JMP:    60:          jmp
+  # IND:    5e:          jmp
+  # CAL:    5e:          jmp
+  # RET:    5e:          jmp
+  jmp foo
+  int3
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # JCC:    9e:          jmpq    *%rax
+  # JMP:    9e:          jmpq    *%rax
+  # IND:    a0:          jmpq    *%rax
+  # CAL:    9e:          jmpq    *%rax
+  # RET:    9e:          jmpq    *%rax
+  jmp  *%rax
+  int3
+
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # JCC:    de:          callq    *%rax
+  # JMP:    de:          callq    *%rax
+  # IND:    de:          callq    *%rax
+  # CAL:    e0:          callq    *%rax
+  # RET:    de:          callq    *%rax
+  call  *%rax
+  int3
+
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # JCC:   11e:          retq
+  # JMP:   11e:          retq
+  # IND:   11e:          retq
+  # CAL:   11e:          retq
+  # RET:   120:          retq
+  ret $0
+  int3
+
+
+  .p2align  5
+  .rept 29
+  int3
+  .endr
+  # JCC:   15d:          cmpq    %rax, %rbp
+  # JCC:   160:          je
+  # JMP:   15d:          cmpq    %rax, %rbp
+  # JMP:   160:          je
+  # IND:   15d:          cmpq    %rax, %rbp
+  # IND:   160:          je
+  # CAL:   15d:          cmpq    %rax, %rbp
+  # CAL:   160:          je
+  # RET:   15d:          cmpq    %rax, %rbp
+  # RET:   160:          je
+  cmp  %rax, %rbp
+  je  foo
+  int3
diff --git a/llvm/test/CodeGen/X86/align-branch-boundary-default.s b/llvm/test/MC/X86/align-branch-boundary-default.s
similarity index 100%
rename from llvm/test/CodeGen/X86/align-branch-boundary-default.s
rename to llvm/test/MC/X86/align-branch-boundary-default.s
diff --git a/llvm/test/MC/X86/align-branch-variant-symbol.s b/llvm/test/MC/X86/align-branch-variant-symbol.s
new file mode 100644
index 0000000000000..e1cb7b52edc2c
--- /dev/null
+++ b/llvm/test/MC/X86/align-branch-variant-symbol.s
@@ -0,0 +1,57 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call+indirect %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=64BIT,CHECK
+
+  # RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=call+indirect %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefixes=32BIT,CHECK
+
+  # Exercise cases where the instruction to be aligned has a variant symbol
+  # operand, and we can't add before it since linker may rewrite it.
+
+  .text
+  .global foo
+
+foo:
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # CHECK:    1d:          int3
+  # 64BIT:    1e:          callq
+  # 32BIT:    1e:          calll
+  # CHECK:    23:          int3
+  call    ___tls_get_addr@PLT
+  int3
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # CHECK:    5d:          int3
+  # 64BIT:    5e:          callq    *(%ecx)
+  # 64BIT:    65:          int3
+  # 32BIT:    5e:          calll    *(%ecx)
+  # 32BIT:    64:          int3
+  call *___tls_get_addr@GOT(%ecx)
+  int3
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # CHECK:    9d:          int3
+  # 64BIT:    9e:          callq    *(%eax)
+  # 64BIT:    a1:          int3
+  # 32BIT:    9e:          calll    *(%eax)
+  # 32BIT:    a0:          int3
+  call *foo@tlscall(%eax)
+  int3
+
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  # CHECK:    dd:          int3
+  # 64BIT:    de:          jmpq    *(%eax)
+  # 64BIT:    e1:          int3
+  # 32BIT:    de:          jmpl    *(%eax)
+  # 32BIT:    e0:          int3
+  jmp  *foo@tlscall(%eax)
+  int3
diff --git a/llvm/test/MC/X86/align-via-padding.s b/llvm/test/MC/X86/align-via-padding.s
new file mode 100644
index 0000000000000..572af4b02961e
--- /dev/null
+++ b/llvm/test/MC/X86/align-via-padding.s
@@ -0,0 +1,76 @@
+# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s -x86-pad-max-prefix-size=5 | llvm-objdump -d --section=.text - | FileCheck %s
+
+# This test file highlights the interactions between prefix padding and
+# relaxation padding.
+
+  .file "test.c"
+  .text
+  .section  .text
+  # We can both relax and prefix for padding purposes, but the moment, we
+  # can't prefix without first having relaxed.
+  # CHECK: .text
+  # CHECK:  0: eb 1f                         jmp
+  # CHECK:  2: eb 1d                         jmp
+  # CHECK:  4: eb 1b                         jmp
+  # CHECK:  6: eb 19                         jmp
+  # CHECK:  8: eb 17                         jmp
+  # CHECK:  a: 2e 2e 2e 2e 2e e9 0d 00 00 00 jmp
+  # CHECK: 14: 2e 2e 2e 2e 2e e9 03 00 00 00 jmp
+  # CHECK: 1e: 66 90                         nop
+  # CHECK: 20: cc                            int3
+  .p2align 4
+  jmp foo
+  jmp foo
+  jmp foo
+  jmp foo
+  jmp foo
+  jmp foo
+  jmp foo
+  .p2align 5
+  int3
+foo:
+  ret
+
+  # Canonical toy loop to show benefit - we can align the loop header with
+  # fewer nops by relaxing the branch, even though we don't need to
+  # CHECK: <loop_preheader>:
+  # CHECK: 45: 48 85 c0                       testq %rax, %rax
+  # CHECK: 48: 2e 2e 2e 2e 0f 8e 1e 00 00 00  jle 30 <loop_exit>
+  # CHECK: 52: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00    	nopw	%cs:(%rax,%rax)
+  # CHECK: <loop_header>:
+  # CHECK: 60: 48 83 e8 01                    subq $1, %rax
+  # CHECK: 64: 48 85 c0                       testq %rax, %rax
+  # CHECK: 67: 7e 07                          jle 7 <loop_exit>
+  # CHECK: 69: 2e 2e e9 f0 ff ff ff           jmp
+  # CHECK: <loop_exit>:
+  # CHECK: 70: c3                             retq
+  .p2align 5
+  .skip 5
+loop_preheader:
+  testq %rax, %rax
+  jle loop_exit
+  .p2align 5
+loop_header:
+  subq $1, %rax
+  testq %rax, %rax
+  jle loop_exit
+  jmp loop_header
+  .p2align 4
+loop_exit:
+  ret
+
+  # Correctness cornercase - can't prefix pad jmp without having relaxed it
+  # first as doing so would make the relative offset too large
+  # CHECK: fd: cc                             int3
+  # CHECK: fe: eb 80                          jmp -128 <loop_exit+0x10>
+  # CHECK: 100: cc                           	int3
+.p2align 5
+.L1:
+.rept 126
+  int3
+.endr
+  jmp .L1
+.rept 30
+  int3
+.endr
+.p2align 5
diff --git a/llvm/test/MC/X86/align-via-relaxation.s b/llvm/test/MC/X86/align-via-relaxation.s
index f81e4c73e4f22..7f372bba0f20c 100644
--- a/llvm/test/MC/X86/align-via-relaxation.s
+++ b/llvm/test/MC/X86/align-via-relaxation.s
@@ -1,5 +1,7 @@
-# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s | llvm-objdump -d --section=.text - | FileCheck %s
+# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu -x86-pad-max-prefix-size=0 %s | llvm-objdump -d --section=.text - | FileCheck %s
 
+# This test exercises only the padding via relaxation logic.  The  interaction
+# etween prefix padding and relaxation logic can be seen in align-via-padding.s
 
   .file "test.c"
   .text
diff --git a/llvm/test/MC/X86/compact-unwind.s b/llvm/test/MC/X86/compact-unwind.s
index 03138c4034059..4f84a2abb4779 100644
--- a/llvm/test/MC/X86/compact-unwind.s
+++ b/llvm/test/MC/X86/compact-unwind.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -unwind-info - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin10.0 %s | llvm-objdump --unwind-info - | FileCheck %s
 
 	.section	__TEXT,__text,regular,pure_instructions
 	.macosx_version_min 10, 10
diff --git a/llvm/test/MC/X86/data-prefix16.s b/llvm/test/MC/X86/data-prefix16.s
index d90b9dc5a9342..16bd244f0fe80 100644
--- a/llvm/test/MC/X86/data-prefix16.s
+++ b/llvm/test/MC/X86/data-prefix16.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple i386-unknown-unknown-code16 -filetype=obj %s -o - | llvm-objdump -triple i386-unknown-unknown-code16 -d - | FileCheck %s
+# RUN: llvm-mc -triple i386-unknown-unknown-code16 -filetype=obj %s -o - | llvm-objdump --triple=i386-unknown-unknown-code16 -d - | FileCheck %s
 
 # CHECK: 66 0f 01 16 00 00
 # CHECK: lgdtl 0
diff --git a/llvm/test/MC/X86/data-prefix32.s b/llvm/test/MC/X86/data-prefix32.s
index 15a718b1a97c2..0d818885ca27a 100644
--- a/llvm/test/MC/X86/data-prefix32.s
+++ b/llvm/test/MC/X86/data-prefix32.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple=i386-unknown-unknown -filetype=obj %s -o - | llvm-objdump -triple=i386-unknown-unknown -d - | FileCheck %s
+# RUN: llvm-mc -triple=i386-unknown-unknown -filetype=obj %s -o - | llvm-objdump --triple=i386-unknown-unknown -d - | FileCheck %s
 
 # CHECK: 66 0f 01 15 00 00 00 00
 # CHECK: lgdtw 0
diff --git a/llvm/test/MC/X86/data-prefix64.s b/llvm/test/MC/X86/data-prefix64.s
index acd0db3ec1041..0553131839837 100644
--- a/llvm/test/MC/X86/data-prefix64.s
+++ b/llvm/test/MC/X86/data-prefix64.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple=x86_64-unknown-unknown -filetype=obj %s -o - | llvm-objdump -triple=x86_64-unknown-unknown -d - | FileCheck %s
+# RUN: llvm-mc -triple=x86_64-unknown-unknown -filetype=obj %s -o - | llvm-objdump --triple=x86_64-unknown-unknown -d - | FileCheck %s
 
 # CHECK: 66 0f 01 14 25 00 00 00 00
 # CHECK: lgdtq 0
diff --git a/llvm/test/MC/X86/faultmap-section-parsing.s b/llvm/test/MC/X86/faultmap-section-parsing.s
index 758e70fe685cf..78be403752681 100644
--- a/llvm/test/MC/X86/faultmap-section-parsing.s
+++ b/llvm/test/MC/X86/faultmap-section-parsing.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc < %s -triple=x86_64-apple-macosx -filetype=obj -o - | llvm-objdump -fault-map-section - | FileCheck %s
+// RUN: llvm-mc < %s -triple=x86_64-apple-macosx -filetype=obj -o - | llvm-objdump --fault-map-section - | FileCheck %s
 
 	.section	__LLVM_FAULTMAPS,__llvm_faultmaps
 __LLVM_FaultMaps:
diff --git a/llvm/test/MC/X86/prefix-padding-32.s b/llvm/test/MC/X86/prefix-padding-32.s
new file mode 100644
index 0000000000000..b975bd5783c08
--- /dev/null
+++ b/llvm/test/MC/X86/prefix-padding-32.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -x86-pad-max-prefix-size=15 | llvm-objdump -d --section=.text - | FileCheck %s
+
+# Check prefix padding generation for all cases on 32 bit x86.
+
+# CHECK:  1: 3e 3e 3e 3e 3e 3e 3e 3e 3e 81 e1 01 00 00 00 	andl	$1, %ecx
+# CHECK: 10: 3e 3e 3e 3e 3e 3e 3e 3e 3e 81 21 01 00 00 00 	andl	$1, %ds:(%ecx)
+# CHECK: 1f: 2e 2e 2e 2e 2e 2e 2e 2e 2e 81 21 01 00 00 00 	andl	$1, %cs:(%ecx)
+# CHECK: 2e: 3e 3e 3e 3e 3e 3e 3e 3e 3e 81 21 01 00 00 00 	andl	$1, %ds:(%ecx)
+# CHECK: 3d: 26 26 26 26 26 26 26 26 26 81 21 01 00 00 00 	andl	$1, %es:(%ecx)
+# CHECK: 4c: 64 64 64 64 64 64 64 64 64 81 21 01 00 00 00 	andl	$1, %fs:(%ecx)
+# CHECK: 5b: 65 65 65 65 65 65 65 65 65 81 21 01 00 00 00 	andl	$1, %gs:(%ecx)
+# CHECK: 6a: 36 36 36 36 36 36 36 36 36 81 21 01 00 00 00 	andl	$1, %ss:(%ecx)
+# CHECK: 79: 3e 3e 3e 3e 3e 81 a1 00 00 00 00 01 00 00 00 	andl	$1, %ds:(%ecx)
+# CHECK: 88: 3e 3e 3e 3e 3e 81 a1 00 00 00 00 01 00 00 00 	andl	$1, %ds:(%ecx)
+# CHECK: 97: 36 36 36 36 36 36 36 36 81 24 24 01 00 00 00 	andl	$1, %ss:(%esp)
+# CHECK: a6: 65 65 65 65 65 65 65 65 81 24 24 01 00 00 00 	andl	$1, %gs:(%esp)
+# CHECK: b5: 36 36 36 36 81 a4 24 00 00 00 00 01 00 00 00 	andl	$1, %ss:(%esp)
+# CHECK: c4: 36 36 36 36 36 36 36 36 81 65 00 01 00 00 00 	andl	$1, %ss:(%ebp)
+# CHECK: d3: 65 65 65 65 65 65 65 65 81 65 00 01 00 00 00 	andl	$1, %gs:(%ebp)
+# CHECK: e2: 36 36 36 36 36 81 a5 00 00 00 00 01 00 00 00 	andl	$1, %ss:(%ebp)
+  .text
+  .section  .text
+  .p2align 8
+bar:
+  int3  
+foo:
+  # non-memory
+  andl $foo, %ecx
+  # memory, non-esp/ebp
+  andl $foo, (%ecx)
+  andl $foo, %cs:(%ecx)
+  andl $foo, %ds:(%ecx)
+  andl $foo, %es:(%ecx)
+  andl $foo, %fs:(%ecx)
+  andl $foo, %gs:(%ecx)
+  andl $foo, %ss:(%ecx)
+  andl $foo, data16 (%ecx)
+  andl $foo, data32 (%ecx)
+  # esp w/o segment override
+  andl $foo, (%esp)
+  andl $foo, %gs:(%esp)
+  andl $foo, data32 (%esp)
+  # ebp w/o segment override
+  andl $foo, (%ebp)
+  andl $foo, %gs:(%ebp)
+  andl $foo, data32 (%ebp)
+
+  # Request enough padding to justify padding all of the above
+  .p2align 8
+  int3
diff --git a/llvm/test/MC/X86/prefix-padding-64.s b/llvm/test/MC/X86/prefix-padding-64.s
new file mode 100644
index 0000000000000..fcffc772d25bc
--- /dev/null
+++ b/llvm/test/MC/X86/prefix-padding-64.s
@@ -0,0 +1,53 @@
+# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s -x86-pad-max-prefix-size=15 | llvm-objdump -d --section=.text - | FileCheck %s
+
+# Check prefix padding generation for all cases on 64 bit x86.
+
+# CHECK:  0: 2e 2e 2e 2e 2e 2e 2e 2e 48 81 e1 00 00 00 00   andq  $0, %rcx
+# CHECK:  f: 2e 2e 2e 2e 2e 2e 2e 2e 48 81 21 00 00 00 00   andq  $0, %cs:(%rcx)
+# CHECK: 1e: 2e 2e 2e 2e 2e 2e 2e 2e 48 81 21 00 00 00 00   andq  $0, %cs:(%rcx)
+# CHECK: 2d: 3e 3e 3e 3e 3e 3e 3e 3e 48 81 21 00 00 00 00   andq  $0, %ds:(%rcx)
+# CHECK: 3c: 26 26 26 26 26 26 26 26 48 81 21 00 00 00 00   andq  $0, %es:(%rcx)
+# CHECK: 4b: 64 64 64 64 64 64 64 64 48 81 21 00 00 00 00   andq  $0, %fs:(%rcx)
+# CHECK: 5a: 65 65 65 65 65 65 65 65 48 81 21 00 00 00 00   andq  $0, %gs:(%rcx)
+# CHECK: 69: 36 36 36 36 36 36 36 36 48 81 21 00 00 00 00   andq  $0, %ss:(%rcx)
+# CHECK: 78: 2e 2e 2e 2e 48 81 a1 00 00 00 00 00 00 00 00   andq  $0, %cs:(%rcx)
+# CHECK: 87: 2e 2e 2e 2e 48 81 a1 00 00 00 00 00 00 00 00   andq  $0, %cs:(%rcx)
+# CHECK: 96: 2e 2e 2e 2e 2e 2e 2e 48 81 24 24 00 00 00 00   andq  $0, %cs:(%rsp)
+# CHECK: a5: 65 65 65 65 65 65 65 48 81 24 24 00 00 00 00   andq  $0, %gs:(%rsp)
+# CHECK: b4: 2e 2e 2e 48 81 a4 24 00 00 00 00 00 00 00 00   andq  $0, %cs:(%rsp)
+# CHECK: c3: 2e 2e 2e 2e 2e 2e 2e 48 81 65 00 00 00 00 00   andq  $0, %cs:(%rbp)
+# CHECK: d2: 65 65 65 65 65 65 65 48 81 65 00 00 00 00 00   andq  $0, %gs:(%rbp)
+# CHECK: e1: 2e 2e 2e 2e 48 81 a5 00 00 00 00 00 00 00 00   andq  $0, %cs:(%rbp)
+  .text
+  .section  .text
+  .p2align 8
+  # non-memory
+  andq $foo, %rcx
+  # memory, non-esp/ebp
+  andq $foo, (%rcx)
+  andq $foo, %cs:(%rcx)
+  andq $foo, %ds:(%rcx)
+  andq $foo, %es:(%rcx)
+  andq $foo, %fs:(%rcx)
+  andq $foo, %gs:(%rcx)
+  andq $foo, %ss:(%rcx)
+  andq $foo, data16 (%rcx)
+  andq $foo, data32 (%rcx)
+  # esp w/o segment override
+  andq $foo, (%rsp)
+  andq $foo, %gs:(%rsp)
+  andq $foo, data32 (%rsp)
+  # ebp w/o segment override
+  andq $foo, (%rbp)
+  andq $foo, %gs:(%rbp)
+  andq $foo, data32 (%rbp)
+
+  # Request enough padding to justify padding all of the above
+  .p2align 8
+  int3
+
+  .section "other"
+bar:
+  .p2align 3
+  int3  
+foo:
diff --git a/llvm/test/MC/X86/relax-offset.s b/llvm/test/MC/X86/relax-offset.s
new file mode 100644
index 0000000000000..78de255e9d6f3
--- /dev/null
+++ b/llvm/test/MC/X86/relax-offset.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -filetype=obj -triple=i386 %s | llvm-objdump - --headers | FileCheck %s
+
+  # CHECK: .text1        00000005 00000000
+  # CHECK: .text2        00000005 00000000
+
+  .section .text1
+ .skip after-before,0x0
+.Lint80_keep_stack:
+
+  .section .text2
+before:
+ jmp .Lint80_keep_stack
+after:
diff --git a/llvm/test/MC/X86/return-column.s b/llvm/test/MC/X86/return-column.s
index 37c51343a9f99..ad664beb60fad 100644
--- a/llvm/test/MC/X86/return-column.s
+++ b/llvm/test/MC/X86/return-column.s
@@ -1,6 +1,6 @@
 // REQUIRES: x86-registered-target
 // RUN: llvm-mc -triple i686-unknown-linux-gnu -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ASM-ROUNDTRIP
-// RUN: llvm-mc -triple i686-unknown-linux-gnu -filetype obj -o - %s | llvm-objdump -dwarf=frames - | FileCheck %s -check-prefix CHECK-EH_FRAME
+// RUN: llvm-mc -triple i686-unknown-linux-gnu -filetype obj -o - %s | llvm-objdump --dwarf=frames - | FileCheck %s --check-prefix=CHECK-EH_FRAME
 
 	.text
 
diff --git a/llvm/test/MC/X86/tlsdesc-32.s b/llvm/test/MC/X86/tlsdesc-32.s
index 866bda65b94ff..87f513caa6d8e 100644
--- a/llvm/test/MC/X86/tlsdesc-32.s
+++ b/llvm/test/MC/X86/tlsdesc-32.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple i386-pc-linux-musl %s -o %t
 # RUN: llvm-readelf -s %t | FileCheck --check-prefix=SYM %s
-# RUN: llvm-objdump -dr --no-show-raw-insn %t | FileCheck %s
+# RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck %s
 
 # PRINT:      leal a@tlsdesc(%ebx), %eax
 # PRINT-NEXT: calll *a@tlscall(%eax)
diff --git a/llvm/test/MC/X86/tlsdesc-64.s b/llvm/test/MC/X86/tlsdesc-64.s
index 374626cdfbeb9..5c4acd234244e 100644
--- a/llvm/test/MC/X86/tlsdesc-64.s
+++ b/llvm/test/MC/X86/tlsdesc-64.s
@@ -2,7 +2,7 @@
 
 # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-musl %s -o %t
 # RUN: llvm-readelf -s %t | FileCheck --check-prefix=SYM %s
-# RUN: llvm-objdump -dr --no-show-raw-insn %t | FileCheck --match-full-lines %s
+# RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck --match-full-lines %s
 
 # PRINT:      leaq a@tlsdesc(%rip), %rax
 # PRINT-NEXT: callq *a@tlscall(%rax)
diff --git a/llvm/test/MC/X86/x86-branch-relaxation.s b/llvm/test/MC/X86/x86-branch-relaxation.s
index 870374e685fd5..0bdeb667bbfb3 100644
--- a/llvm/test/MC/X86/x86-branch-relaxation.s
+++ b/llvm/test/MC/X86/x86-branch-relaxation.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc -filetype=obj -triple=i386-unknown-unknown %s -o %t
-# RUN: llvm-objdump -r -D -section .text.bar -triple i386-unknown-unknown-code16 %t | FileCheck --check-prefix=CHECK16 %s
-# RUN: llvm-objdump -r -D -section .text.baz -triple i386-unknown-unknown        %t | FileCheck --check-prefix=CHECK32 %s 	
+# RUN: llvm-objdump -r -D --section .text.bar --triple=i386-unknown-unknown-code16 %t | FileCheck --check-prefix=CHECK16 %s
+# RUN: llvm-objdump -r -D --section .text.baz --triple=i386-unknown-unknown        %t | FileCheck --check-prefix=CHECK32 %s 	
 	.text
 	.section	.text.foo,"",@progbits
 
diff --git a/llvm/test/MC/X86/x86_long_nop.s b/llvm/test/MC/X86/x86_long_nop.s
index 1676bde582559..981a38f759721 100644
--- a/llvm/test/MC/X86/x86_long_nop.s
+++ b/llvm/test/MC/X86/x86_long_nop.s
@@ -1,30 +1,30 @@
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=pentiumpro %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=pentiumpro | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 -mcpu=pentiumpro %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 -mcpu=pentiumpro %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=silvermont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=NOP1 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=bdver1 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP11
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=bdver1 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP11
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=btver1 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=btver1 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=btver2 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=btver2 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver1 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver1 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver2 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver2 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=nehalem %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=westmere %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=sandybridge %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=ivybridge %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=haswell %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=broadwell %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=skylake %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=skx %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=knl %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=knm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=pentiumpro %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=pentiumpro | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 -mcpu=pentiumpro %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 -mcpu=pentiumpro %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP10
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=silvermont %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=NOP1 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=bdver1 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP11
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=bdver1 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP11
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=btver1 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=btver1 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=btver2 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=btver2 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver1 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver1 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver2 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver2 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=nehalem %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=westmere %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=sandybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=ivybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=haswell %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=broadwell %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=skylake %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=skx %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=knl %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=knm %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
 
 # Ensure alignment directives also emit sequences of 10, 11 and 15-byte NOPs on processors
 # capable of using long NOPs.
diff --git a/llvm/test/Object/AMDGPU/elf32-unknown.yaml b/llvm/test/Object/AMDGPU/elf32-unknown.yaml
index 4c43401499c47..ae4ef71c2da78 100644
--- a/llvm/test/Object/AMDGPU/elf32-unknown.yaml
+++ b/llvm/test/Object/AMDGPU/elf32-unknown.yaml
@@ -1,7 +1,7 @@
 # RUN: yaml2obj %s -o %t.o
 # RUN: llvm-readobj -S --file-headers %t.o | FileCheck %s
 
-# CHECK: Format: ELF32-amdgpu
+# CHECK: Format: elf32-amdgpu
 
 --- !ELF
 FileHeader:
diff --git a/llvm/test/Object/AMDGPU/elf64-unknown.yaml b/llvm/test/Object/AMDGPU/elf64-unknown.yaml
index b991df62a555e..3d419f261724a 100644
--- a/llvm/test/Object/AMDGPU/elf64-unknown.yaml
+++ b/llvm/test/Object/AMDGPU/elf64-unknown.yaml
@@ -1,7 +1,7 @@
 # RUN: yaml2obj %s -o %t.o
 # RUN: llvm-readobj -S --file-headers %t.o | FileCheck %s
 
-# CHECK: Format: ELF64-amdgpu
+# CHECK: Format: elf64-amdgpu
 
 --- !ELF
 FileHeader:
diff --git a/llvm/test/Object/AMDGPU/objdump.s b/llvm/test/Object/AMDGPU/objdump.s
index 063124e3428b1..541a226475cd7 100644
--- a/llvm/test/Object/AMDGPU/objdump.s
+++ b/llvm/test/Object/AMDGPU/objdump.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s -mattr=-code-object-v3 -filetype=obj | llvm-objdump -disassemble -arch-name=amdgcn -mcpu=tonga - | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s -mattr=-code-object-v3 -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=tonga - | FileCheck %s
 
 	.text
 
diff --git a/llvm/test/Object/ARM/macho-data-in-code.test b/llvm/test/Object/ARM/macho-data-in-code.test
index 2bfb6c118644e..73d70ac6b68a7 100644
--- a/llvm/test/Object/ARM/macho-data-in-code.test
+++ b/llvm/test/Object/ARM/macho-data-in-code.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -triple thumbv7-apple-iOS -disassemble %p/../Inputs/macho-data-in-code.macho-thumbv7 -macho | FileCheck %s
+RUN: llvm-objdump --triple=thumbv7-apple-iOS -d %p/../Inputs/macho-data-in-code.macho-thumbv7 --macho | FileCheck %s
 
 CHECK:      12:	80 bd                                        	pop	{r7, pc}
 
diff --git a/llvm/test/Object/ARM/objdump-thumb.test b/llvm/test/Object/ARM/objdump-thumb.test
index 9c92a27782d43..470ca2a1b34b7 100644
--- a/llvm/test/Object/ARM/objdump-thumb.test
+++ b/llvm/test/Object/ARM/objdump-thumb.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -d -macho -triple=thumbv7-apple-ios \
+RUN: llvm-objdump -d --macho --triple=thumbv7-apple-ios \
 RUN: %p/../Inputs/macho-text.thumb | FileCheck %s
 
 CHECK: 0:	00 bf                                        	nop
diff --git a/llvm/test/Object/Mips/feature.test b/llvm/test/Object/Mips/feature.test
index 6363b82cd5080..eccd8a6757a2b 100644
--- a/llvm/test/Object/Mips/feature.test
+++ b/llvm/test/Object/Mips/feature.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -disassemble %p/../Inputs/dext-test.elf-mips64r2 | FileCheck %s
+RUN: llvm-objdump -d %p/../Inputs/dext-test.elf-mips64r2 | FileCheck %s
 
 CHECK: Disassembly of section .text:
 CHECK: <dext>:
diff --git a/llvm/test/Object/X86/macho-text-sections.test b/llvm/test/Object/X86/macho-text-sections.test
index 1b697dcadad6d..cb8808251c5ce 100644
--- a/llvm/test/Object/X86/macho-text-sections.test
+++ b/llvm/test/Object/X86/macho-text-sections.test
@@ -1,3 +1,3 @@
-RUN: llvm-objdump -disassemble %p/../Inputs/macho-text-sections.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump -d %p/../Inputs/macho-text-sections.macho-x86_64 | FileCheck %s
 
 CHECK: Disassembly of section __notext,__notext
diff --git a/llvm/test/Object/X86/objdump-disassembly-inline-relocations.test b/llvm/test/Object/X86/objdump-disassembly-inline-relocations.test
index 0ac9046b11e9f..34dedf9cefed5 100644
--- a/llvm/test/Object/X86/objdump-disassembly-inline-relocations.test
+++ b/llvm/test/Object/X86/objdump-disassembly-inline-relocations.test
@@ -70,7 +70,7 @@
 # MACHO-x86-64:       27:       c3                                              ret
 
 # RUN: yaml2obj --docnum=1 %s -o %t.elf-i386
-# RUN: llvm-objdump -d -r %t.elf-i386 | FileCheck %s -check-prefix ELF-i386
+# RUN: llvm-objdump -d -r %t.elf-i386 | FileCheck %s --check-prefix=ELF-i386
 
 # ELF-i386: file format elf32-i386
 # ELF-i386: Disassembly of section .text:
@@ -127,7 +127,7 @@ Symbols:
     Binding: STB_GLOBAL
 
 # RUN: yaml2obj --docnum=2 %s -o %t.elf-x86-64
-# RUN: llvm-objdump -d -r %t.elf-x86-64 | FileCheck %s -check-prefix ELF-x86-64
+# RUN: llvm-objdump -d -r %t.elf-x86-64 | FileCheck %s --check-prefix=ELF-x86-64
 
 --- !ELF
 FileHeader:
diff --git a/llvm/test/Object/X86/objdump-trivial-object.test b/llvm/test/Object/X86/objdump-trivial-object.test
index fda7251f5288a..c3e080c5f88fc 100644
--- a/llvm/test/Object/X86/objdump-trivial-object.test
+++ b/llvm/test/Object/X86/objdump-trivial-object.test
@@ -27,7 +27,7 @@
 # COFF-x86-64:       25: c3                           ret
 
 # RUN: yaml2obj --docnum=1 %s -o %t.elf-i386
-# RUN: llvm-objdump -d %t.elf-i386 | FileCheck %s -check-prefix ELF-i386
+# RUN: llvm-objdump -d %t.elf-i386 | FileCheck %s --check-prefix=ELF-i386
 
 # ELF-i386: file format elf32-i386
 # ELF-i386: Disassembly of section .text:
@@ -53,7 +53,7 @@ Sections:
     Content: 83EC0CC744240800000000C7042400000000E8FCFFFFFFE8FCFFFFFF8B44240883C40CC3
 
 # RUN: yaml2obj --docnum=2 %s -o %t.elf-x86-64
-# RUN: llvm-objdump -d %t.elf-x86-64 | FileCheck %s -check-prefix ELF-x86-64
+# RUN: llvm-objdump -d %t.elf-x86-64 | FileCheck %s --check-prefix=ELF-x86-64
 
 # ELF-x86-64: file format elf64-x86-64
 # ELF-x86-64: Disassembly of section .text:
diff --git a/llvm/test/Object/elf-invalid-phdr.test b/llvm/test/Object/elf-invalid-phdr.test
index 68a26788e118d..1b47f8d66cc41 100644
--- a/llvm/test/Object/elf-invalid-phdr.test
+++ b/llvm/test/Object/elf-invalid-phdr.test
@@ -20,7 +20,7 @@
 #       - Section: .text
 #
 # Then editing the e_phoff in with a hexeditor to set it to 0xffffff
-RUN: not --crash llvm-objdump -private-headers %p/Inputs/invalid-phdr.elf 2>&1 \
+RUN: not --crash llvm-objdump --private-headers %p/Inputs/invalid-phdr.elf 2>&1 \
 RUN:         | FileCheck %s
 
 CHECK: LLVM ERROR: program headers are longer than binary of size 4162: e_phoff = 0xffffff, e_phnum = 1, e_phentsize = 56
diff --git a/llvm/test/Object/invalid-alignment.test b/llvm/test/Object/invalid-alignment.test
index 66c5fed72a213..8a0079062669d 100644
--- a/llvm/test/Object/invalid-alignment.test
+++ b/llvm/test/Object/invalid-alignment.test
@@ -1,7 +1,7 @@
 # RUN: yaml2obj %s -o %t.o
 # RUN: llvm-readobj -r %t.o 2>&1 | FileCheck %s
 
-# CHECK:      Format: ELF64-x86-64
+# CHECK:      Format: elf64-x86-64
 # CHECK-NEXT: Arch: x86_64
 # CHECK-NEXT: AddressSize: 64bit
 # CHECK-NEXT: LoadName:
diff --git a/llvm/test/Object/invalid.test b/llvm/test/Object/invalid.test
index 2c80bd6f7453e..3a1ef2b3318c3 100644
--- a/llvm/test/Object/invalid.test
+++ b/llvm/test/Object/invalid.test
@@ -95,7 +95,7 @@ Sections:
 ## .strtab is not null-terminated.
 
 # RUN: yaml2obj %s --docnum=5 -o %t5
-# RUN: not llvm-objdump -syms %t5 2>&1 | FileCheck --check-prefix=NONULL %s
+# RUN: not llvm-objdump --syms %t5 2>&1 | FileCheck --check-prefix=NONULL %s
 
 # NONULL: error: {{.*}}: SHT_STRTAB string table section [index 1] is non-null terminated
 
@@ -596,7 +596,7 @@ FileHeader:
 ## symbol name and .strtab is empty.
 
 # RUN: yaml2obj %s --docnum=28 -o %t28
-# RUN: not llvm-objdump -syms %t28 2>&1 | FileCheck -DFILE=%t28 --check-prefix=STRTAB-EMPTY2 %s
+# RUN: not llvm-objdump --syms %t28 2>&1 | FileCheck -DFILE=%t28 --check-prefix=STRTAB-EMPTY2 %s
 
 # STRTAB-EMPTY2: error: '[[FILE]]': SHT_STRTAB string table section [index 1] is empty
 
diff --git a/llvm/test/Object/macho-invalid.test b/llvm/test/Object/macho-invalid.test
index 2206c678105be..c47e4d286ed1d 100644
--- a/llvm/test/Object/macho-invalid.test
+++ b/llvm/test/Object/macho-invalid.test
@@ -63,10 +63,10 @@ RUN: not llvm-objdump -t %p/Inputs/macho-bad-archive1.a 2>&1 \
 RUN:      | FileCheck -check-prefix NAME-PAST-EOF-ARCHIVE %s
 NAME-PAST-EOF-ARCHIVE: macho-bad-archive1.a(macho-invalid-symbol-name-past-eof): truncated or malformed object (bad string index: 4261412866 for symbol at index 0)
 
-RUN: not llvm-objdump --macho -arch all -t %p/Inputs/macho-universal-bad1.x86_64.i386 2>&1 \
+RUN: not llvm-objdump --macho --arch=all -t %p/Inputs/macho-universal-bad1.x86_64.i386 2>&1 \
 RUN:      | FileCheck -check-prefix NAME-PAST-EOF-FAT %s
 NAME-PAST-EOF-FAT: macho-universal-bad1.x86_64.i386' (for architecture x86_64): truncated or malformed object (bad string index: 4261412866 for symbol at index 0)
-RUN: not llvm-objdump --macho -arch all -t %p/Inputs/macho-universal-archive-bad1.x86_64.i386 2>&1 \
+RUN: not llvm-objdump --macho --arch=all -t %p/Inputs/macho-universal-archive-bad1.x86_64.i386 2>&1 \
 RUN:      | FileCheck -check-prefix NAME-PAST-EOF-FAT-ARCHIVE %s
 NAME-PAST-EOF-FAT-ARCHIVE: macho-universal-archive-bad1.x86_64.i386(macho-invalid-symbol-name-past-eof) (for architecture x86_64): truncated or malformed object (bad string index: 4261412866 for symbol at index 0)
 
@@ -83,28 +83,28 @@ RUN: not llvm-objdump -t %p/Inputs/macho-invalid-section-index-getSectionRawName
 RUN:      | FileCheck -check-prefix INVALID-SECTION-IDX-SYMBOL-SEC-objdump %s
 INVALID-SECTION-IDX-SYMBOL-SEC-objdump: truncated or malformed object (bad section index: 66 for symbol at index 8)
 
-RUN: llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-header 2>&1 | FileCheck -check-prefix INVALID-HEADER %s
+RUN: llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-header 2>&1 | FileCheck --check-prefix=INVALID-HEADER %s
 INVALID-HEADER: is not an object file
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho64-invalid-incomplete-segment-load-command 2>&1 | FileCheck -check-prefix INCOMPLETE-SEGMENT-LOADC %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho64-invalid-incomplete-segment-load-command 2>&1 | FileCheck --check-prefix=INCOMPLETE-SEGMENT-LOADC %s
 INCOMPLETE-SEGMENT-LOADC: truncated or malformed object (load commands extend past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-bad-archive2.a 2>&1 | FileCheck -check-prefix INCOMPLETE-SEGMENT-LOADC-ARCHIVE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-bad-archive2.a 2>&1 | FileCheck --check-prefix=INCOMPLETE-SEGMENT-LOADC-ARCHIVE %s
 INCOMPLETE-SEGMENT-LOADC-ARCHIVE: macho-bad-archive2.a(macho64-invalid-incomplete-segment-load-command): truncated or malformed object (load commands extend past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers -arch all %p/Inputs/macho-universal-bad2.x86_64.i386 2>&1 | FileCheck -check-prefix INCOMPLETE-SEGMENT-LOADC-FAT %s
+RUN: not llvm-objdump --macho --private-headers --arch=all %p/Inputs/macho-universal-bad2.x86_64.i386 2>&1 | FileCheck --check-prefix=INCOMPLETE-SEGMENT-LOADC-FAT %s
 INCOMPLETE-SEGMENT-LOADC-FAT: macho-universal-bad2.x86_64.i386' (for architecture x86_64): truncated or malformed object (load commands extend past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers -arch all %p/Inputs/macho-universal-archive-bad2.x86_64.i386 2>&1 | FileCheck -check-prefix INCOMPLETE-SEGMENT-LOADC-FAT-ARCHIVE %s
+RUN: not llvm-objdump --macho --private-headers --arch=all %p/Inputs/macho-universal-archive-bad2.x86_64.i386 2>&1 | FileCheck --check-prefix=INCOMPLETE-SEGMENT-LOADC-FAT-ARCHIVE %s
 INCOMPLETE-SEGMENT-LOADC-FAT-ARCHIVE: macho-universal-archive-bad2.x86_64.i386(macho64-invalid-incomplete-segment-load-command) (for architecture x86_64): truncated or malformed object (load commands extend past the end of the file)
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat 2>&1 | FileCheck -check-prefix INVALID-FAT %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat 2>&1 | FileCheck --check-prefix=INVALID-FAT %s
 INVALID-FAT: truncated or malformed fat file (fat_arch_64 structs would extend past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers -arch all %p/Inputs/macho-invalid-fat.obj.elf-x86_64 2>&1 | FileCheck -check-prefix INVALID-FAT-ELF %s
+RUN: not llvm-objdump --macho --private-headers --arch=all %p/Inputs/macho-invalid-fat.obj.elf-x86_64 2>&1 | FileCheck --check-prefix=INVALID-FAT-ELF %s
 INVALID-FAT-ELF: error: '{{.*}}/macho-invalid-fat.obj.elf-x86_64': Mach-O universal file for architecture x86_64 is not a Mach-O file or an archive file
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-segment-fileoff 2>&1 | FileCheck -check-prefix INVALID-SEGMENT-FILEOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-segment-fileoff 2>&1 | FileCheck --check-prefix=INVALID-SEGMENT-FILEOFF %s
 INVALID-SEGMENT-FILEOFF: macho-invalid-segment-fileoff': truncated or malformed object (load command 0 fileoff field in LC_SEGMENT extends past the end of the file)
 
 RUN: not llvm-nm %p/Inputs/macho-invalid-segment-fileoff 2>&1 | FileCheck -check-prefix INVALID-SEGMENT-FILEOFF-NM %s
@@ -113,401 +113,401 @@ INVALID-SEGMENT-FILEOFF-NM: macho-invalid-segment-fileoff truncated or malformed
 RUN: not llvm-size %p/Inputs/macho-invalid-segment-fileoff 2>&1 | FileCheck -DFILE=%p/Inputs/macho-invalid-segment-fileoff -check-prefix INVALID-SEGMENT-FILEOFF-SIZE %s
 INVALID-SEGMENT-FILEOFF-SIZE: error: '[[FILE]]': truncated or malformed object (load command 0 fileoff field in LC_SEGMENT extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-segment-filesize 2>&1 | FileCheck -check-prefix INVALID-SEGMENT-FILESIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-segment-filesize 2>&1 | FileCheck --check-prefix=INVALID-SEGMENT-FILESIZE %s
 INVALID-SEGMENT-FILESIZE: macho-invalid-segment-filesize': truncated or malformed object (load command 0 fileoff field plus filesize field in LC_SEGMENT extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-segment-vmsize 2>&1 | FileCheck -check-prefix INVALID-SEGMENT-VMSIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-segment-vmsize 2>&1 | FileCheck --check-prefix=INVALID-SEGMENT-VMSIZE %s
 INVALID-SEGMENT-VMSIZE: macho-invalid-segment-vmsize': truncated or malformed object (load command 0 filesize field in LC_SEGMENT greater than vmsize field)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-offset 2>&1 | FileCheck -check-prefix INVALID-SECTION-FILEOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-offset 2>&1 | FileCheck --check-prefix=INVALID-SECTION-FILEOFF %s
 INVALID-SECTION-FILEOFF: macho-invalid-section-offset': truncated or malformed object (offset field of section 0 in LC_SEGMENT command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-offset-in-headers 2>&1 | FileCheck -check-prefix INVALID-SECTION-FILEOFF-IN-HEADERS %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-offset-in-headers 2>&1 | FileCheck --check-prefix=INVALID-SECTION-FILEOFF-IN-HEADERS %s
 INVALID-SECTION-FILEOFF-IN-HEADERS: macho-invalid-section-offset-in-headers': truncated or malformed object (offset field of section 0 in LC_SEGMENT command 0 not past the headers of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-offset-size 2>&1 | FileCheck -check-prefix INVALID-SECTION-FILEOFF-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-offset-size 2>&1 | FileCheck --check-prefix=INVALID-SECTION-FILEOFF-SIZE %s
 INVALID-SECTION-FILEOFF-SIZE: macho-invalid-section-offset-size': truncated or malformed object (offset field plus size field of section 0 in LC_SEGMENT command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-size-filesize 2>&1 | FileCheck -check-prefix INVALID-SECTION-SIZE-FILESIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-size-filesize 2>&1 | FileCheck --check-prefix=INVALID-SECTION-SIZE-FILESIZE %s
 INVALID-SECTION-SIZE-FILESIZE: macho-invalid-section-size-filesize': truncated or malformed object (size field of section 0 in LC_SEGMENT command 0 greater than the segment)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-addr 2>&1 | FileCheck -check-prefix INVALID-SECTION-ADDR %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-addr 2>&1 | FileCheck --check-prefix=INVALID-SECTION-ADDR %s
 INVALID-SECTION-ADDR: macho-invalid-section-addr': truncated or malformed object (addr field of section 0 in LC_SEGMENT command 0 less than the segment's vmaddr)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-addr-size 2>&1 | FileCheck -check-prefix INVALID-SECTION-ADDR-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-addr-size 2>&1 | FileCheck --check-prefix=INVALID-SECTION-ADDR-SIZE %s
 INVALID-SECTION-ADDR-SIZE: macho-invalid-section-addr-size': truncated or malformed object (addr field plus size of section 0 in LC_SEGMENT command 0 greater than than the segment's vmaddr plus vmsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-reloff 2>&1 | FileCheck -check-prefix INVALID-SECTION-RELOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-reloff 2>&1 | FileCheck --check-prefix=INVALID-SECTION-RELOFF %s
 INVALID-SECTION-RELOFF: macho-invalid-section-reloff': truncated or malformed object (reloff field of section 0 in LC_SEGMENT command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-reloff-nrelocs 2>&1 | FileCheck -check-prefix INVALID-SECTION-RELOFF-NRELOCS %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-reloff-nrelocs 2>&1 | FileCheck --check-prefix=INVALID-SECTION-RELOFF-NRELOCS %s
 INVALID-SECTION-RELOFF-NRELOCS: macho-invalid-section-reloff-nrelocs': truncated or malformed object (reloff field plus nreloc field times sizeof(struct relocation_info) of section 0 in LC_SEGMENT command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-small 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-small 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-SMALL %s
 INVALID-SYMTAB-SMALL: macho-invalid-symtab-small': truncated or malformed object (load command 0 LC_SYMTAB cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-more-than-one 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-MORE-THAN-ONE %s
 INVALID-SYMTAB-MORE-THAN-ONE: macho-invalid-symtab-more-than-one': truncated or malformed object (more than one LC_SYMTAB command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-bad-size 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-bad-size 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-BAD-SIZE %s
 INVALID-SYMTAB-BAD-SIZE: macho-invalid-symtab-bad-size': truncated or malformed object (LC_SYMTAB command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-symoff 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-SYMOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-symoff 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-SYMOFF %s
 INVALID-SYMTAB-SYMOFF: macho-invalid-symtab-symoff': truncated or malformed object (symoff field of LC_SYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-symoff-nsyms 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-SYMOFF-NSYMS %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-symoff-nsyms 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-SYMOFF-NSYMS %s
 INVALID-SYMTAB-SYMOFF-NSYMS: macho-invalid-symtab-symoff-nsyms': truncated or malformed object (symoff field plus nsyms field times sizeof(struct nlist) of LC_SYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-stroff 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-STROFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-stroff 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-STROFF %s
 INVALID-SYMTAB-STROFF: macho-invalid-symtab-stroff': truncated or malformed object (stroff field of LC_SYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-stroff-strsize 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-STROFF-STRSIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-stroff-strsize 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-STROFF-STRSIZE %s
 INVALID-SYMTAB-STROFF-STRSIZE: macho-invalid-symtab-stroff-strsize': truncated or malformed object (stroff field plus strsize field of LC_SYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-small 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-small 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-SMALL %s
 INVALID-DYSYMTAB-SMALL: macho-invalid-dysymtab-small': truncated or malformed object (load command 0 LC_DYSYMTAB cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-more-than-one 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-MORE-THAN-ONE %s
 INVALID-DYSYMTAB-MORE-THAN-ONE: macho-invalid-dysymtab-more-than-one': truncated or malformed object (more than one LC_DYSYMTAB command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-bad-size 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-bad-size 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-BAD-SIZE %s
 INVALID-DYSYMTAB-BAD-SIZE: macho-invalid-dysymtab-bad-size': truncated or malformed object (LC_DYSYMTAB command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-tocoff 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-tocoff 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF %s
 INVALID-DYSYMTAB-TOCOFF: macho-invalid-dysymtab-tocoff': truncated or malformed object (tocoff field of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-tocoff-ntoc 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-NTOC %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-tocoff-ntoc 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-NTOC %s
 INVALID-DYSYMTAB-TOCOFF-NTOC: macho-invalid-dysymtab-tocoff-ntoc': truncated or malformed object (tocoff field plus ntoc field times sizeof(struct dylib_table_of_contents) of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-modtaboff 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-MODTABOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-modtaboff 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-MODTABOFF %s
 INVALID-DYSYMTAB-TOCOFF-MODTABOFF: macho-invalid-dysymtab-modtaboff': truncated or malformed object (modtaboff field of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-modtaboff-nmodtab 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-MODTABOFF-NMODTAB %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-modtaboff-nmodtab 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-MODTABOFF-NMODTAB %s
 INVALID-DYSYMTAB-TOCOFF-MODTABOFF-NMODTAB: macho-invalid-dysymtab-modtaboff-nmodtab': truncated or malformed object (modtaboff field plus nmodtab field times sizeof(struct dylib_module) of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extrefsymoff 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-EXTREFSYMOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extrefsymoff 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-EXTREFSYMOFF %s
 INVALID-DYSYMTAB-TOCOFF-EXTREFSYMOFF: macho-invalid-dysymtab-extrefsymoff': truncated or malformed object (extrefsymoff field of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extrefsymoff-nextrefsyms 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-EXTREFSYMOFF-NEXTREFSYMS %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extrefsymoff-nextrefsyms 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-EXTREFSYMOFF-NEXTREFSYMS %s
 INVALID-DYSYMTAB-TOCOFF-EXTREFSYMOFF-NEXTREFSYMS: macho-invalid-dysymtab-extrefsymoff-nextrefsyms': truncated or malformed object (extrefsymoff field plus nextrefsyms field times sizeof(struct dylib_reference) of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-indirectsymoff 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-INDIRECTSYMOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-indirectsymoff 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-INDIRECTSYMOFF %s
 INVALID-DYSYMTAB-TOCOFF-INDIRECTSYMOFF: macho-invalid-dysymtab-indirectsymoff': truncated or malformed object (indirectsymoff field of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-indirectsymoff-nindirectsyms 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-INDIRECTSYMOFF-NINDIRECTSYMS %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-indirectsymoff-nindirectsyms 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-INDIRECTSYMOFF-NINDIRECTSYMS %s
 INVALID-DYSYMTAB-TOCOFF-INDIRECTSYMOFF-NINDIRECTSYMS: macho-invalid-dysymtab-indirectsymoff-nindirectsyms': truncated or malformed object (indirectsymoff field plus nindirectsyms field times sizeof(uint32_t) of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extreloff 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-EXTRELOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extreloff 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-EXTRELOFF %s
 INVALID-DYSYMTAB-TOCOFF-EXTRELOFF: macho-invalid-dysymtab-extreloff': truncated or malformed object (extreloff field of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extreloff-nextrel 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-EXTRELOFF-NEXTREL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-extreloff-nextrel 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-EXTRELOFF-NEXTREL %s
 INVALID-DYSYMTAB-TOCOFF-EXTRELOFF-NEXTREL: macho-invalid-dysymtab-extreloff-nextrel': truncated or malformed object (extreloff field plus nextrel field times sizeof(struct relocation_info) of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-locreloff 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-LOCRELOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-locreloff 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-LOCRELOFF %s
 INVALID-DYSYMTAB-TOCOFF-LOCRELOFF: macho-invalid-dysymtab-locreloff': truncated or malformed object (locreloff field of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-locreloff-nlocrel 2>&1 | FileCheck -check-prefix INVALID-DYSYMTAB-TOCOFF-LOCRELOFF-NLOCREL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dysymtab-locreloff-nlocrel 2>&1 | FileCheck --check-prefix=INVALID-DYSYMTAB-TOCOFF-LOCRELOFF-NLOCREL %s
 INVALID-DYSYMTAB-TOCOFF-LOCRELOFF-NLOCREL: macho-invalid-dysymtab-locreloff-nlocrel': truncated or malformed object (locreloff field plus nlocrel field times sizeof(struct relocation_info) of LC_DYSYMTAB command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dataincode-more-than-one 2>&1 | FileCheck -check-prefix INVALID-DATAINCODE-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dataincode-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-DATAINCODE-MORE-THAN-ONE %s
 INVALID-DATAINCODE-MORE-THAN-ONE: macho-invalid-dataincode-more-than-one': truncated or malformed object (more than one LC_DATA_IN_CODE command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopthint-small 2>&1 | FileCheck -check-prefix INVALID-LINKOPTHINT-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopthint-small 2>&1 | FileCheck --check-prefix=INVALID-LINKOPTHINT-SMALL %s
 INVALID-LINKOPTHINT-SMALL: macho-invalid-linkopthint-small': truncated or malformed object (load command 0 LC_LINKER_OPTIMIZATION_HINT cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dataincode-bad-size 2>&1 | FileCheck -check-prefix INVALID-DATAINCODE-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dataincode-bad-size 2>&1 | FileCheck --check-prefix=INVALID-DATAINCODE-BAD-SIZE %s
 INVALID-DATAINCODE-BAD-SIZE: macho-invalid-dataincode-bad-size': truncated or malformed object (LC_DATA_IN_CODE command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopthint-dataoff 2>&1 | FileCheck -check-prefix INVALID-LINKOPTHINT-DATAOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopthint-dataoff 2>&1 | FileCheck --check-prefix=INVALID-LINKOPTHINT-DATAOFF %s
 INVALID-LINKOPTHINT-DATAOFF: macho-invalid-linkopthint-dataoff': truncated or malformed object (dataoff field of LC_LINKER_OPTIMIZATION_HINT command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dataincode-dataoff-datasize 2>&1 | FileCheck -check-prefix INVALID-DATAINCODE-DATAOFF-DATASIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dataincode-dataoff-datasize 2>&1 | FileCheck --check-prefix=INVALID-DATAINCODE-DATAOFF-DATASIZE %s
 INVALID-DATAINCODE-DATAOFF-DATASIZE: macho-invalid-dataincode-dataoff-datasize': truncated or malformed object (dataoff field plus datasize field of LC_DATA_IN_CODE command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-small 2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-small 2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-SMALL %s
 INVALID-DYLDINFO-SMALL: macho-invalid-dyldinfo-small': truncated or malformed object (load command 0 LC_DYLD_INFO cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-bad-size 2>&1 | FileCheck -check-prefix INVALID-DYLDINFOONLY-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-bad-size 2>&1 | FileCheck --check-prefix=INVALID-DYLDINFOONLY-BAD-SIZE %s
 INVALID-DYLDINFOONLY-BAD-SIZE: macho-invalid-dyldinfoonly-bad-size': truncated or malformed object (LC_DYLD_INFO_ONLY command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-rebase_off 2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-REBASE_OFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-rebase_off 2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-REBASE_OFF %s
 INVALID-DYLDINFO-REBASE_OFF: macho-invalid-dyldinfo-rebase_off': truncated or malformed object (rebase_off field of LC_DYLD_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-rebase_off-rebase_size 2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-REBASE_OFF-REBASE_SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-rebase_off-rebase_size 2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-REBASE_OFF-REBASE_SIZE %s
 INVALID-DYLDINFO-REBASE_OFF-REBASE_SIZE: macho-invalid-dyldinfo-rebase_off-rebase_size': truncated or malformed object (rebase_off field plus rebase_size field of LC_DYLD_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-bind_off  2>&1 | FileCheck -check-prefix INVALID-DYLDINFOONLY-BIND_OFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-bind_off  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFOONLY-BIND_OFF %s
 INVALID-DYLDINFOONLY-BIND_OFF: macho-invalid-dyldinfoonly-bind_off': truncated or malformed object (bind_off field of LC_DYLD_INFO_ONLY command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-bind_off-bind_size  2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-BIND_OFF-BIND_SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-bind_off-bind_size  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-BIND_OFF-BIND_SIZE %s
 INVALID-DYLDINFO-BIND_OFF-BIND_SIZE: macho-invalid-dyldinfo-bind_off-bind_size': truncated or malformed object (bind_off field plus bind_size field of LC_DYLD_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-weak_bind_off  2>&1 | FileCheck -check-prefix INVALID-DYLDINFOONLY-WEAK_BIND_OFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-weak_bind_off  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFOONLY-WEAK_BIND_OFF %s
 INVALID-DYLDINFOONLY-WEAK_BIND_OFF: macho-invalid-dyldinfoonly-weak_bind_off': truncated or malformed object (weak_bind_off field of LC_DYLD_INFO_ONLY command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-weak_bind_off-weak_bind_size  2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-WEAK_BIND_OFF-WEAK_BIND_SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-weak_bind_off-weak_bind_size  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-WEAK_BIND_OFF-WEAK_BIND_SIZE %s
 INVALID-DYLDINFO-WEAK_BIND_OFF-WEAK_BIND_SIZE: macho-invalid-dyldinfo-weak_bind_off-weak_bind_size': truncated or malformed object (weak_bind_off field plus weak_bind_size field of LC_DYLD_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-lazy_bind_off  2>&1 | FileCheck -check-prefix INVALID-DYLDINFOONLY-LAZY_BIND_OFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-lazy_bind_off  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFOONLY-LAZY_BIND_OFF %s
 INVALID-DYLDINFOONLY-LAZY_BIND_OFF: macho-invalid-dyldinfoonly-lazy_bind_off': truncated or malformed object (lazy_bind_off field of LC_DYLD_INFO_ONLY command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-lazy_bind_off-lazy_bind_size  2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-LAZY_BIND_OFF-LAZY_BIND_SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-lazy_bind_off-lazy_bind_size  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-LAZY_BIND_OFF-LAZY_BIND_SIZE %s
 INVALID-DYLDINFO-LAZY_BIND_OFF-LAZY_BIND_SIZE: macho-invalid-dyldinfo-lazy_bind_off-lazy_bind_size': truncated or malformed object (lazy_bind_off field plus lazy_bind_size field of LC_DYLD_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-export_off  2>&1 | FileCheck -check-prefix INVALID-DYLDINFOONLY-EXPORT_OFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfoonly-export_off  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFOONLY-EXPORT_OFF %s
 INVALID-DYLDINFOONLY-EXPORT_OFF: macho-invalid-dyldinfoonly-export_off': truncated or malformed object (export_off field of LC_DYLD_INFO_ONLY command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-export_off-export_size  2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-EXPORT_OFF-EXPORT_SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-export_off-export_size  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-EXPORT_OFF-EXPORT_SIZE %s
 INVALID-DYLDINFO-EXPORT_OFF-EXPORT_SIZE: macho-invalid-dyldinfo-export_off-export_size': truncated or malformed object (export_off field plus export_size field of LC_DYLD_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-more-than-one  2>&1 | FileCheck -check-prefix INVALID-DYLDINFO-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyldinfo-more-than-one  2>&1 | FileCheck --check-prefix=INVALID-DYLDINFO-MORE-THAN-ONE %s
 INVALID-DYLDINFO-MORE-THAN-ONE: macho-invalid-dyldinfo-more-than-one': truncated or malformed object (more than one LC_DYLD_INFO and or LC_DYLD_INFO_ONLY command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-small  2>&1 | FileCheck -check-prefix INVALID-DYLIB-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-small  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-SMALL %s
 INVALID-DYLIB-SMALL: macho-invalid-dylib-small': truncated or malformed object (load command 0 LC_LOAD_DYLIB cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-name_offset-toobig  2>&1 | FileCheck -check-prefix INVALID-DYLIB-NAME_OFFSET-TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-name_offset-toobig  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-NAME_OFFSET-TOOBIG %s
 INVALID-DYLIB-NAME_OFFSET-TOOBIG: macho-invalid-dylib-name_offset-toobig': truncated or malformed object (load command 0 LC_LOAD_WEAK_DYLIB name.offset field extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-name_toobig  2>&1 | FileCheck -check-prefix INVALID-DYLIB-NAME_TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-name_toobig  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-NAME_TOOBIG %s
 INVALID-DYLIB-NAME_TOOBIG: macho-invalid-dylib-name_toobig': truncated or malformed object (load command 0 LC_LAZY_LOAD_DYLIB library name extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-name_offset-toosmall  2>&1 | FileCheck -check-prefix INVALID-DYLIB-NAME_OFFSET-TOOSMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-name_offset-toosmall  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-NAME_OFFSET-TOOSMALL %s
 INVALID-DYLIB-NAME_OFFSET-TOOSMALL: macho-invalid-dylib-name_offset-toosmall': truncated or malformed object (load command 0 LC_LOAD_UPWARD_DYLIB name.offset field too small, not past the end of the dylib_command struct)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-id-more-than-one  2>&1 | FileCheck -check-prefix INVALID-DYLIB-ID-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-id-more-than-one  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-ID-MORE-THAN-ONE %s
 INVALID-DYLIB-ID-MORE-THAN-ONE: macho-invalid-dylib-id-more-than-one': truncated or malformed object (more than one LC_ID_DYLIB command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-wrong-filetype  2>&1 | FileCheck -check-prefix INVALID-DYLIB-WRONG-FILETYPE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-wrong-filetype  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-WRONG-FILETYPE %s
 INVALID-DYLIB-WRONG-FILETYPE: macho-invalid-dylib-wrong-filetype': truncated or malformed object (LC_ID_DYLIB load command in non-dynamic library file type)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-no-id  2>&1 | FileCheck -check-prefix INVALID-DYLIB-NO-ID %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-no-id  2>&1 | FileCheck --check-prefix=INVALID-DYLIB-NO-ID %s
 INVALID-DYLIB-NO-ID: macho-invalid-dylib-no-id': truncated or malformed object (no LC_ID_DYLIB load command in dynamic library filetype)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-cmdsize-past-eof 2>&1 | FileCheck -check-prefix INVALID-DYLIB-CMDSIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib-cmdsize-past-eof 2>&1 | FileCheck --check-prefix=INVALID-DYLIB-CMDSIZE %s
 INVALID-DYLIB-CMDSIZE: macho-invalid-dylib-cmdsize-past-eof': truncated or malformed object (load command 0 extends past end of file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-uuid-more-than-one  2>&1 | FileCheck -check-prefix INVALID-UUID-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-uuid-more-than-one  2>&1 | FileCheck --check-prefix=INVALID-UUID-MORE-THAN-ONE %s
 INVALID-UUID-MORE-THAN-ONE: macho-invalid-uuid-more-than-one': truncated or malformed object (more than one LC_UUID command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-uuid-bad-size  2>&1 | FileCheck -check-prefix INVALID-UUID-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-uuid-bad-size  2>&1 | FileCheck --check-prefix=INVALID-UUID-BAD-SIZE %s
 INVALID-UUID-BAD-SIZE: macho-invalid-uuid-bad-size': truncated or malformed object (LC_UUID command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-function_starts-dataoff  2>&1 | FileCheck -check-prefix INVALID-FUNCTION_STARTS-DATAOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-function_starts-dataoff  2>&1 | FileCheck --check-prefix=INVALID-FUNCTION_STARTS-DATAOFF %s
 INVALID-FUNCTION_STARTS-DATAOFF: macho-invalid-function_starts-dataoff': truncated or malformed object (dataoff field of LC_FUNCTION_STARTS command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-splitinfo-dataoff-datasize  2>&1 | FileCheck -check-prefix INVALID-SPLITINFO-DATAOFF-DATASIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-splitinfo-dataoff-datasize  2>&1 | FileCheck --check-prefix=INVALID-SPLITINFO-DATAOFF-DATASIZE %s
 INVALID-SPLITINFO-DATAOFF-DATASIZE: macho-invalid-splitinfo-dataoff-datasize': truncated or malformed object (dataoff field plus datasize field of LC_SEGMENT_SPLIT_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib_code_sign_drs-bad-size  2>&1 | FileCheck -check-prefix INVALID-DYLIB_CODE_SIGN_DRS-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dylib_code_sign_drs-bad-size  2>&1 | FileCheck --check-prefix=INVALID-DYLIB_CODE_SIGN_DRS-BAD-SIZE %s
 INVALID-DYLIB_CODE_SIGN_DRS-BAD-SIZE: macho-invalid-dylib_code_sign_drs-bad-size': truncated or malformed object (LC_DYLIB_CODE_SIGN_DRS command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyld-small  2>&1 | FileCheck -check-prefix INVALID-DYLD-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyld-small  2>&1 | FileCheck --check-prefix=INVALID-DYLD-SMALL %s
 INVALID-DYLD-SMALL: macho-invalid-dyld-small': truncated or malformed object (load command 0 LC_ID_DYLINKER cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyld-name_offset-toobig  2>&1 | FileCheck -check-prefix INVALID-DYLD-NAME_OFFSET-TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyld-name_offset-toobig  2>&1 | FileCheck --check-prefix=INVALID-DYLD-NAME_OFFSET-TOOBIG %s
 INVALID-DYLD-NAME_OFFSET-TOOBIG: macho-invalid-dyld-name_offset-toobig': truncated or malformed object (load command 0 LC_LOAD_DYLINKER name.offset field extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyld-name_toobig 2>&1 | FileCheck -check-prefix INVALID-DYLD-NAME_TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-dyld-name_toobig 2>&1 | FileCheck --check-prefix=INVALID-DYLD-NAME_TOOBIG %s
 INVALID-DYLD-NAME_TOOBIG: macho-invalid-dyld-name_toobig': truncated or malformed object (load command 0 LC_DYLD_ENVIRONMENT dyld name extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-vers-small 2>&1 | FileCheck -check-prefix INVALID-VERS-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-vers-small 2>&1 | FileCheck --check-prefix=INVALID-VERS-SMALL %s
 INVALID-VERS-SMALL: macho-invalid-vers-small': truncated or malformed object (load command 0 LC_VERSION_MIN_MACOSX has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-vers-more-than-one 2>&1 | FileCheck -check-prefix INVALID-VERS-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-vers-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-VERS-MORE-THAN-ONE %s
 INVALID-VERS-MORE-THAN-ONE: macho-invalid-vers-more-than-one': truncated or malformed object (more than one LC_VERSION_MIN_MACOSX, LC_VERSION_MIN_IPHONEOS, LC_VERSION_MIN_TVOS or LC_VERSION_MIN_WATCHOS command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rpath-small 2>&1 | FileCheck -check-prefix INVALID-RPATH-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rpath-small 2>&1 | FileCheck --check-prefix=INVALID-RPATH-SMALL %s
 INVALID-RPATH-SMALL: macho-invalid-rpath-small': truncated or malformed object (load command 0 LC_RPATH cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rpath-name_offset-toobig 2>&1 | FileCheck -check-prefix INVALID-RPATH-NAME_OFFSET-TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rpath-name_offset-toobig 2>&1 | FileCheck --check-prefix=INVALID-RPATH-NAME_OFFSET-TOOBIG %s
 INVALID-RPATH-NAME_OFFSET-TOOBIG: macho-invalid-rpath-name_offset-toobig': truncated or malformed object (load command 0 LC_RPATH path.offset field extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rpath-name_toobig 2>&1 | FileCheck -check-prefix INVALID-RPATH-NAME_TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rpath-name_toobig 2>&1 | FileCheck --check-prefix=INVALID-RPATH-NAME_TOOBIG %s
 INVALID-RPATH-NAME_TOOBIG: macho-invalid-rpath-name_toobig': truncated or malformed object (load command 0 LC_RPATH library name extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-source-bad-size 2>&1 | FileCheck -check-prefix INVALID-SOURCE-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-source-bad-size 2>&1 | FileCheck --check-prefix=INVALID-SOURCE-BAD-SIZE %s
 INVALID-SOURCE-BAD-SIZE: macho-invalid-source-bad-size': truncated or malformed object (LC_SOURCE_VERSION command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-source-more-than-one 2>&1 | FileCheck -check-prefix INVALID-SOURCE-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-source-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-SOURCE-MORE-THAN-ONE %s
 INVALID-SOURCE-MORE-THAN-ONE: macho-invalid-source-more-than-one': truncated or malformed object (more than one LC_SOURCE_VERSION command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-entry-bad-size 2>&1 | FileCheck -check-prefix INVALID-ENTRY-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-entry-bad-size 2>&1 | FileCheck --check-prefix=INVALID-ENTRY-BAD-SIZE %s
 INVALID-ENTRY-BAD-SIZE: macho-invalid-entry-bad-size': truncated or malformed object (LC_MAIN command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-entry-more-than-one 2>&1 | FileCheck -check-prefix INVALID-ENTRY-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-entry-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-ENTRY-MORE-THAN-ONE %s
 INVALID-ENTRY-MORE-THAN-ONE: macho-invalid-entry-more-than-one': truncated or malformed object (more than one LC_MAIN command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt-bad-size 2>&1 | FileCheck -check-prefix INVALID-ENCRYPT-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt-bad-size 2>&1 | FileCheck --check-prefix=INVALID-ENCRYPT-BAD-SIZE %s
 INVALID-ENCRYPT-BAD-SIZE: macho-invalid-encrypt-bad-size': truncated or malformed object (LC_ENCRYPTION_INFO command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt64-bad-size 2>&1 | FileCheck -check-prefix INVALID-ENCRYPT64-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt64-bad-size 2>&1 | FileCheck --check-prefix=INVALID-ENCRYPT64-BAD-SIZE %s
 INVALID-ENCRYPT64-BAD-SIZE: macho-invalid-encrypt64-bad-size': truncated or malformed object (LC_ENCRYPTION_INFO_64 command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt-more-than-one 2>&1 | FileCheck -check-prefix INVALID-ENCRYPT-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-ENCRYPT-MORE-THAN-ONE %s
 INVALID-ENCRYPT-MORE-THAN-ONE: macho-invalid-encrypt-more-than-one': truncated or malformed object (more than one LC_ENCRYPTION_INFO and or LC_ENCRYPTION_INFO_64 command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt-cryptoff 2>&1 | FileCheck -check-prefix INVALID-ENCRYPT-CRYPTOFF %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt-cryptoff 2>&1 | FileCheck --check-prefix=INVALID-ENCRYPT-CRYPTOFF %s
 INVALID-ENCRYPT-CRYPTOFF: macho-invalid-encrypt-cryptoff': truncated or malformed object (cryptoff field of LC_ENCRYPTION_INFO command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt64-cryptoff-cryptsize 2>&1 | FileCheck -check-prefix INVALID-ENCRYPT-CRYPTOFF-CRYPTSIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-encrypt64-cryptoff-cryptsize 2>&1 | FileCheck --check-prefix=INVALID-ENCRYPT-CRYPTOFF-CRYPTSIZE %s
 INVALID-ENCRYPT-CRYPTOFF-CRYPTSIZE: macho-invalid-encrypt64-cryptoff-cryptsize': truncated or malformed object (cryptoff field plus cryptsize field of LC_ENCRYPTION_INFO_64 command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopt-bad-size 2>&1 | FileCheck -check-prefix INVALID-LINKOPT-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopt-bad-size 2>&1 | FileCheck --check-prefix=INVALID-LINKOPT-BAD-SIZE %s
 INVALID-LINKOPT-BAD-SIZE: macho-invalid-linkopt-bad-size': truncated or malformed object (load command 0 LC_LINKER_OPTION cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopt-bad-count 2>&1 | FileCheck -check-prefix INVALID-LINKOPT-BAD-COUNT %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-linkopt-bad-count 2>&1 | FileCheck --check-prefix=INVALID-LINKOPT-BAD-COUNT %s
 INVALID-LINKOPT-BAD-COUNT: macho-invalid-linkopt-bad-count': truncated or malformed object (load command 0 LC_LINKER_OPTION string count 3 does not match number of strings)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-subframe-small 2>&1 | FileCheck -check-prefix INVALID-SUBFRAME-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-subframe-small 2>&1 | FileCheck --check-prefix=INVALID-SUBFRAME-SMALL %s
 INVALID-SUBFRAME-SMALL: macho-invalid-subframe-small': truncated or malformed object (load command 0 LC_SUB_FRAMEWORK cmdsize too small)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-subumbrella-offset-small 2>&1 | FileCheck -check-prefix INVALID-SUBUMBRELLA-OFFSET-SMALL %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-subumbrella-offset-small 2>&1 | FileCheck --check-prefix=INVALID-SUBUMBRELLA-OFFSET-SMALL %s
 INVALID-SUBUMBRELLA-OFFSET-SMALL: macho-invalid-subumbrella-offset-small': truncated or malformed object (load command 0 LC_SUB_UMBRELLA sub_umbrella.offset field too small, not past the end of the sub_umbrella_command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-sublibrary-name_offset-toobig 2>&1 | FileCheck -check-prefix INVALID-SUBLIB-NAME_OFFSET-TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-sublibrary-name_offset-toobig 2>&1 | FileCheck --check-prefix=INVALID-SUBLIB-NAME_OFFSET-TOOBIG %s
 INVALID-SUBLIB-NAME_OFFSET-TOOBIG: macho-invalid-sublibrary-name_offset-toobig': truncated or malformed object (load command 0 LC_SUB_LIBRARY sub_library.offset field extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-subclient-name_toobig 2>&1 | FileCheck -check-prefix INVALID-SUBCLIENT-NAME-TOOBIG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-subclient-name_toobig 2>&1 | FileCheck --check-prefix=INVALID-SUBCLIENT-NAME-TOOBIG %s
 INVALID-SUBCLIENT-NAME-TOOBIG: macho-invalid-subclient-name_toobig': truncated or malformed object (load command 0 LC_SUB_CLIENT client name extends past the end of the load command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-routines-bad-size 2>&1 | FileCheck -check-prefix INVALID-ROUTINES-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-routines-bad-size 2>&1 | FileCheck --check-prefix=INVALID-ROUTINES-BAD-SIZE %s
 INVALID-ROUTINES-BAD-SIZE: macho-invalid-routines-bad-size': truncated or malformed object (LC_ROUTINES command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-routines64-more-than-one 2>&1 | FileCheck -check-prefix INVALID-ROUTINES64-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-routines64-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-ROUTINES64-MORE-THAN-ONE %s
 INVALID-ROUTINES64-MORE-THAN-ONE: macho-invalid-routines64-more-than-one': truncated or malformed object (more than one LC_ROUTINES_64 and or LC_ROUTINES command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-codesign-bad-size 2>&1 | FileCheck -check-prefix INVALID-CODESIGN-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-codesign-bad-size 2>&1 | FileCheck --check-prefix=INVALID-CODESIGN-BAD-SIZE %s
 INVALID-CODESIGN-BAD-SIZE: macho-invalid-codesign-bad-size': truncated or malformed object (LC_CODE_SIGNATURE command 0 has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-count-pastend 2>&1 | FileCheck -check-prefix INVALID-THREAD-COUNT-PASTEND %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-count-pastend 2>&1 | FileCheck --check-prefix=INVALID-THREAD-COUNT-PASTEND %s
 INVALID-THREAD-COUNT-PASTEND: macho-invalid-thread-count-pastend': truncated or malformed object (load command 0 count in LC_UNIXTHREAD extends past end of command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-count-wrong 2>&1 | FileCheck -check-prefix INVALID-THREAD-COUNT-WRONG %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-count-wrong 2>&1 | FileCheck --check-prefix=INVALID-THREAD-COUNT-WRONG %s
 INVALID-THREAD-COUNT-WRONG: macho-invalid-thread-count-wrong': truncated or malformed object (load command 0 count not x86_THREAD_STATE64_COUNT for flavor number 0 which is a x86_THREAD_STATE64 flavor in LC_THREAD command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-flavor-unknown 2>&1 | FileCheck -check-prefix INVALID-THREAD-FLAVOR-UNKNOWN %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-flavor-unknown 2>&1 | FileCheck --check-prefix=INVALID-THREAD-FLAVOR-UNKNOWN %s
 INVALID-THREAD-FLAVOR-UNKNOWN: macho-invalid-thread-flavor-unknown': truncated or malformed object (load command 0 unknown flavor (507) for flavor number 0 in LC_THREAD command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-state-pastend 2>&1 | FileCheck -check-prefix INVALID-THREAD-PASTEND %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-state-pastend 2>&1 | FileCheck --check-prefix=INVALID-THREAD-PASTEND %s
 INVALID-THREAD-PASTEND: macho-invalid-thread-state-pastend': truncated or malformed object (load command 0 x86_THREAD_STATE64 extends past end of command in LC_THREAD command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-unknown-cputype 2>&1 | FileCheck -check-prefix INVALID-THREAD-UNKNOWN-CPUTYPE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-thread-unknown-cputype 2>&1 | FileCheck --check-prefix=INVALID-THREAD-UNKNOWN-CPUTYPE %s
 INVALID-THREAD-UNKNOWN-CPUTYPE: macho-invalid-thread-unknown-cputype': truncated or malformed object (unknown cputype (328) load command 0 for LC_THREAD command can't be checked)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-unixthread-more-than-one 2>&1 | FileCheck -check-prefix INVALID-UNIXTHREAD-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-unixthread-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-UNIXTHREAD-MORE-THAN-ONE %s
 INVALID-UNIXTHREAD-MORE-THAN-ONE: macho-invalid-unixthread-more-than-one': truncated or malformed object (more than one LC_UNIXTHREAD command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-bad-size 2>&1 | FileCheck -check-prefix INVALID-TWOLEVELHINTS-BAD-SIZE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-bad-size 2>&1 | FileCheck --check-prefix=INVALID-TWOLEVELHINTS-BAD-SIZE %s
 INVALID-TWOLEVELHINTS-BAD-SIZE: macho-invalid-twolevelhints-bad-size': truncated or malformed object (load command 0 LC_TWOLEVEL_HINTS has incorrect cmdsize)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-more-than-one 2>&1 | FileCheck -check-prefix INVALID-TWOLEVELHINTS-MORE-THAN-ONE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-more-than-one 2>&1 | FileCheck --check-prefix=INVALID-TWOLEVELHINTS-MORE-THAN-ONE %s
 INVALID-TWOLEVELHINTS-MORE-THAN-ONE: macho-invalid-twolevelhints-more-than-one': truncated or malformed object (more than one LC_TWOLEVEL_HINTS command)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-offset 2>&1 | FileCheck -check-prefix INVALID-TWOLEVELHINTS-OFFSET %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-offset 2>&1 | FileCheck --check-prefix=INVALID-TWOLEVELHINTS-OFFSET %s
 INVALID-TWOLEVELHINTS-OFFSET: macho-invalid-twolevelhints-offset': truncated or malformed object (offset field of LC_TWOLEVEL_HINTS command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-offset-nhints 2>&1 | FileCheck -check-prefix INVALID-TWOLEVELHINTS-OFFSET-HNINTS %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-twolevelhints-offset-nhints 2>&1 | FileCheck --check-prefix=INVALID-TWOLEVELHINTS-OFFSET-HNINTS %s
 INVALID-TWOLEVELHINTS-OFFSET-HNINTS: macho-invalid-twolevelhints-offset-nhints': truncated or malformed object (offset field plus nhints times sizeof(struct twolevel_hint) field of LC_TWOLEVEL_HINTS command 0 extends past the end of the file)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-fat_cputype 2>&1 | FileCheck -check-prefix INVALID-FAT-CPUTYPE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-fat_cputype 2>&1 | FileCheck --check-prefix=INVALID-FAT-CPUTYPE %s
 INVALID-FAT-CPUTYPE: macho-invalid-fat_cputype': truncated or malformed object (universal header architecture: 0's cputype does not match object file's mach header)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-prebind_cksum-obsolete 2>&1 | FileCheck -check-prefix INVALID-PREBIND_CKSUM-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-prebind_cksum-obsolete 2>&1 | FileCheck --check-prefix=INVALID-PREBIND_CKSUM-OBSOLETE %s
 INVALID-PREBIND_CKSUM-OBSOLETE: macho-invalid-prebind_cksum-obsolete': truncated or malformed object (load command 0 for cmd value of: 23 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symseg-obsolete 2>&1 | FileCheck -check-prefix INVALID-SYMSEG-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symseg-obsolete 2>&1 | FileCheck --check-prefix=INVALID-SYMSEG-OBSOLETE %s
 INVALID-SYMSEG-OBSOLETE: macho-invalid-symseg-obsolete': truncated or malformed object (load command 0 for cmd value of: 3 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-idfvmlib-obsolete 2>&1 | FileCheck -check-prefix INVALID-IDFVMLIB-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-idfvmlib-obsolete 2>&1 | FileCheck --check-prefix=INVALID-IDFVMLIB-OBSOLETE %s
 INVALID-IDFVMLIB-OBSOLETE: macho-invalid-idfvmlib-obsolete': truncated or malformed object (load command 0 for cmd value of: 7 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-loadfvmlib-obsolete 2>&1 | FileCheck -check-prefix INVALID-LOADFVMLIB-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-loadfvmlib-obsolete 2>&1 | FileCheck --check-prefix=INVALID-LOADFVMLIB-OBSOLETE %s
 INVALID-LOADFVMLIB-OBSOLETE: macho-invalid-loadfvmlib-obsolete': truncated or malformed object (load command 0 for cmd value of: 6 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-prebound_dylib-obsolete 2>&1 | FileCheck -check-prefix INVALID-PREBOUND_DYLIB-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-prebound_dylib-obsolete 2>&1 | FileCheck --check-prefix=INVALID-PREBOUND_DYLIB-OBSOLETE %s
 INVALID-PREBOUND_DYLIB-OBSOLETE: macho-invalid-prebound_dylib-obsolete': truncated or malformed object (load command 0 for cmd value of: 16 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-ident-obsolete 2>&1 | FileCheck -check-prefix INVALID-IDENT-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-ident-obsolete 2>&1 | FileCheck --check-prefix=INVALID-IDENT-OBSOLETE %s
 INVALID-IDENT-OBSOLETE: macho-invalid-ident-obsolete': truncated or malformed object (load command 0 for cmd value of: 8 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-fvmfile-obsolete 2>&1 | FileCheck -check-prefix INVALID-FVMFILE-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-fvmfile-obsolete 2>&1 | FileCheck --check-prefix=INVALID-FVMFILE-OBSOLETE %s
 INVALID-FVMFILE-OBSOLETE: macho-invalid-fvmfile-obsolete': truncated or malformed object (load command 0 for cmd value of: 9 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-prepage-obsolete 2>&1 | FileCheck -check-prefix INVALID-PREPAGE-OBSOLETE %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-prepage-obsolete 2>&1 | FileCheck --check-prefix=INVALID-PREPAGE-OBSOLETE %s
 INVALID-PREPAGE-OBSOLETE: macho-invalid-prepage-obsolete': truncated or malformed object (load command 0 for cmd value of: 10 is obsolete and not supported)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-overlap 2>&1 | FileCheck -check-prefix INVALID-SYMTAB-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-symtab-overlap 2>&1 | FileCheck --check-prefix=INVALID-SYMTAB-OVERLAP %s
 INVALID-SYMTAB-OVERLAP: macho-invalid-symtab-overlap': truncated or malformed object (symbol table at offset 8 with a size of 12, overlaps Mach-O headers at offset 0 with a size of 52)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-strtab-overlap 2>&1 | FileCheck -check-prefix INVALID-STRTAB-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-strtab-overlap 2>&1 | FileCheck --check-prefix=INVALID-STRTAB-OVERLAP %s
 INVALID-STRTAB-OVERLAP: macho-invalid-strtab-overlap': truncated or malformed object (string table at offset 60 with a size of 16, overlaps symbol table at offset 52 with a size of 12)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-overlap 2>&1 | FileCheck -check-prefix INVALID-SECTION-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-section-overlap 2>&1 | FileCheck --check-prefix=INVALID-SECTION-OVERLAP %s
 INVALID-SECTION-OVERLAP: macho-invalid-section-overlap': truncated or malformed object (symbol table at offset 208 with a size of 12, overlaps section contents at offset 184 with a size of 32)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-reloc-overlap 2>&1 | FileCheck -check-prefix INVALID-RELOC-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-reloc-overlap 2>&1 | FileCheck --check-prefix=INVALID-RELOC-OVERLAP %s
 INVALID-RELOC-OVERLAP: macho-invalid-reloc-overlap': truncated or malformed object (section relocation entries at offset 204 with a size of 8, overlaps section contents at offset 176 with a size of 32)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-toc-overlap 2>&1 | FileCheck -check-prefix INVALID-TOC-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-toc-overlap 2>&1 | FileCheck --check-prefix=INVALID-TOC-OVERLAP %s
 INVALID-TOC-OVERLAP: macho-invalid-toc-overlap': truncated or malformed object (table of contents at offset 292 with a size of 8, overlaps section relocation entries at offset 288 with a size of 8)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-modtab-overlap 2>&1 | FileCheck -check-prefix INVALID-MODTAB-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-modtab-overlap 2>&1 | FileCheck --check-prefix=INVALID-MODTAB-OVERLAP %s
 INVALID-MODTAB-OVERLAP: macho-invalid-modtab-overlap': truncated or malformed object (module table at offset 300 with a size of 52, overlaps table of contents at offset 296 with a size of 8)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-extrefsyms-overlap 2>&1 | FileCheck -check-prefix INVALID-EXTREFSYMS-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-extrefsyms-overlap 2>&1 | FileCheck --check-prefix=INVALID-EXTREFSYMS-OVERLAP %s
 INVALID-EXTREFSYMS-OVERLAP: macho-invalid-extrefsyms-overlap': truncated or malformed object (reference table at offset 352 with a size of 4, overlaps module table at offset 304 with a size of 52)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-indirectsyms-overlap 2>&1 | FileCheck -check-prefix INVALID-INDIRECTSYMS-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-indirectsyms-overlap 2>&1 | FileCheck --check-prefix=INVALID-INDIRECTSYMS-OVERLAP %s
 INVALID-INDIRECTSYMS-OVERLAP: macho-invalid-indirectsyms-overlap': truncated or malformed object (indirect table at offset 364 with a size of 4, overlaps section contents at offset 364 with a size of 4)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-extreloff-overlap 2>&1 | FileCheck -check-prefix INVALID-EXTRELOFF-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-extreloff-overlap 2>&1 | FileCheck --check-prefix=INVALID-EXTRELOFF-OVERLAP %s
 INVALID-EXTRELOFF-OVERLAP: macho-invalid-extreloff-overlap': truncated or malformed object (external relocation table at offset 424 with a size of 8, overlaps reference table at offset 424 with a size of 4)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-locreloff-overlap 2>&1 | FileCheck -check-prefix INVALID-LOCRELOFF-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-locreloff-overlap 2>&1 | FileCheck --check-prefix=INVALID-LOCRELOFF-OVERLAP %s
 INVALID-LOCRELOFF-OVERLAP: macho-invalid-locreloff-overlap': truncated or malformed object (local relocation table at offset 432 with a size of 8, overlaps external relocation table at offset 428 with a size of 8)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-hints-overlap 2>&1 | FileCheck -check-prefix INVALID-HINTS-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-hints-overlap 2>&1 | FileCheck --check-prefix=INVALID-HINTS-OVERLAP %s
 INVALID-HINTS-OVERLAP: macho-invalid-hints-overlap': truncated or malformed object (two level hints at offset 104 with a size of 4, overlaps Mach-O headers at offset 0 with a size of 108)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-codesig-overlap 2>&1 | FileCheck -check-prefix INVALID-CODESIG-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-codesig-overlap 2>&1 | FileCheck --check-prefix=INVALID-CODESIG-OVERLAP %s
 INVALID-CODESIG-OVERLAP: macho-invalid-codesig-overlap': truncated or malformed object (code signature data at offset 40 with a size of 32, overlaps Mach-O headers at offset 0 with a size of 48)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rebase-overlap 2>&1 | FileCheck -check-prefix INVALID-REBASE-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-rebase-overlap 2>&1 | FileCheck --check-prefix=INVALID-REBASE-OVERLAP %s
 INVALID-REBASE-OVERLAP: macho-invalid-rebase-overlap': truncated or malformed object (dyld rebase info at offset 72 with a size of 32, overlaps Mach-O headers at offset 0 with a size of 80)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-bind-overlap 2>&1 | FileCheck -check-prefix INVALID-BIND-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-bind-overlap 2>&1 | FileCheck --check-prefix=INVALID-BIND-OVERLAP %s
 INVALID-BIND-OVERLAP: macho-invalid-bind-overlap': truncated or malformed object (dyld bind info at offset 104 with a size of 32, overlaps dyld rebase info at offset 80 with a size of 32)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-weak_bind-overlap 2>&1 | FileCheck -check-prefix INVALID-WEAK_BIND-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-weak_bind-overlap 2>&1 | FileCheck --check-prefix=INVALID-WEAK_BIND-OVERLAP %s
 INVALID-WEAK_BIND-OVERLAP: macho-invalid-weak_bind-overlap': truncated or malformed object (dyld weak bind info at offset 136 with a size of 32, overlaps dyld bind info at offset 112 with a size of 32)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-lazy_bind-overlap 2>&1 | FileCheck -check-prefix INVALID-LAZY_BIND-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-lazy_bind-overlap 2>&1 | FileCheck --check-prefix=INVALID-LAZY_BIND-OVERLAP %s
 INVALID-LAZY_BIND-OVERLAP: macho-invalid-lazy_bind-overlap': truncated or malformed object (dyld lazy bind info at offset 168 with a size of 32, overlaps dyld weak bind info at offset 144 with a size of 32)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-export-overlap 2>&1 | FileCheck -check-prefix INVALID-EXPORT-OVERLAP %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-export-overlap 2>&1 | FileCheck --check-prefix=INVALID-EXPORT-OVERLAP %s
 INVALID-EXPORT-OVERLAP: macho-invalid-export-overlap': truncated or malformed object (dyld export info at offset 200 with a size of 32, overlaps dyld lazy bind info at offset 176 with a size of 32)
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-header 2>&1 | FileCheck -check-prefix INVALID-FAT-HEADER %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-header 2>&1 | FileCheck --check-prefix=INVALID-FAT-HEADER %s
 INVALID-FAT-HEADER: macho-invalid-fat-header': truncated or malformed fat file (contains zero architecture types)
 
-RUN: yaml2obj %p/Inputs/macho-invalid-fat-arch-size.yaml -o - | not llvm-objdump --macho --universal-headers - 2>&1 | FileCheck -check-prefix INVALID-FAT-ARCH-SIZE %s
+RUN: yaml2obj %p/Inputs/macho-invalid-fat-arch-size.yaml -o - | not llvm-objdump --macho --universal-headers - 2>&1 | FileCheck --check-prefix=INVALID-FAT-ARCH-SIZE %s
 INVALID-FAT-ARCH-SIZE: '-': truncated or malformed fat file (offset plus size of cputype (7) cpusubtype (3) extends past the end of the file)
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-bigalign 2>&1 | FileCheck -check-prefix INVALID-FAT-ARCH-BIGALIGN %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-bigalign 2>&1 | FileCheck --check-prefix=INVALID-FAT-ARCH-BIGALIGN %s
 INVALID-FAT-ARCH-BIGALIGN: macho-invalid-fat-arch-bigalign': truncated or malformed fat file (align (2^212) too large for cputype (7) cpusubtype (3) (maximum 2^15))
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-badalign 2>&1 | FileCheck -check-prefix INVALID-FAT-ARCH-BADALIGN %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-badalign 2>&1 | FileCheck --check-prefix=INVALID-FAT-ARCH-BADALIGN %s
 INVALID-FAT-ARCH-BADALIGN: macho-invalid-fat-arch-badalign': truncated or malformed fat file (offset: 28 for cputype (7) cpusubtype (3) not aligned on it's alignment (2^4))
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-twosame 2>&1 | FileCheck -check-prefix INVALID-FAT-ARCH-TWOSAME %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-twosame 2>&1 | FileCheck --check-prefix=INVALID-FAT-ARCH-TWOSAME %s
 INVALID-FAT-ARCH-TWOSAME: macho-invalid-fat-arch-twosame': truncated or malformed fat file (contains two of the same architecture (cputype (7) cpusubtype (3)))
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-overlap 2>&1 | FileCheck -check-prefix INVALID-FAT-ARCH-OVERLAP %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-overlap 2>&1 | FileCheck --check-prefix=INVALID-FAT-ARCH-OVERLAP %s
 INVALID-FAT-ARCH-OVERLAP: macho-invalid-fat-arch-overlap': truncated or malformed fat file (cputype (7) cpusubtype (5) at offset 48 with a size of 28, overlaps cputype (7) cpusubtype (3) at offset 52 with a size of 28)
 
-RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-overlapheaders 2>&1 | FileCheck -check-prefix INVALID-FAT-ARCH-OVERLAPHEADERS %s
+RUN: not llvm-objdump --macho --universal-headers %p/Inputs/macho-invalid-fat-arch-overlapheaders 2>&1 | FileCheck --check-prefix=INVALID-FAT-ARCH-OVERLAPHEADERS %s
 INVALID-FAT-ARCH-OVERLAPHEADERS: macho-invalid-fat-arch-overlapheaders': truncated or malformed fat file (cputype (7) cpusubtype (3) offset 12 overlaps universal headers)
 
-RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-note 2>&1 | FileCheck -check-prefix INVALID-NOTE-COMMAND %s
+RUN: not llvm-objdump --macho --private-headers %p/Inputs/macho-invalid-note 2>&1 | FileCheck --check-prefix=INVALID-NOTE-COMMAND %s
 INVALID-NOTE-COMMAND: macho-invalid-note': truncated or malformed object (size field plus offset field of LC_NOTE command 0 extends past the end of the file)
diff --git a/llvm/test/Object/objdump-export-list.test b/llvm/test/Object/objdump-export-list.test
index 1728f73d8b40c..1f8a0f6ae98a9 100644
--- a/llvm/test/Object/objdump-export-list.test
+++ b/llvm/test/Object/objdump-export-list.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -exports-trie %p/Inputs/macho-no-exports.dylib | FileCheck %s
+RUN: llvm-objdump --macho --exports-trie %p/Inputs/macho-no-exports.dylib | FileCheck %s
 
 ; Test that we don't crash with an empty export list.
 CHECK: macho-no-exports.dylib
diff --git a/llvm/test/Object/objdump-relocations.test b/llvm/test/Object/objdump-relocations.test
index 2674029559448..d402e4ae7e7cf 100644
--- a/llvm/test/Object/objdump-relocations.test
+++ b/llvm/test/Object/objdump-relocations.test
@@ -4,7 +4,7 @@
 # RUN:              | FileCheck %s -check-prefix COFF-x86-64
 
 # RUN: yaml2obj --docnum=1 %s -o %t-i386
-# RUN: llvm-objdump -r %t-i386 | FileCheck %s -check-prefix ELF-i386
+# RUN: llvm-objdump -r %t-i386 | FileCheck %s --check-prefix=ELF-i386
 
 # ELF-i386: .text
 # ELF-i386: R_386_32 .section
@@ -39,7 +39,7 @@ Symbols:
     Binding: STB_GLOBAL
 
 # RUN: yaml2obj --docnum=2 %s -o %t-x86-64
-# RUN: llvm-objdump -r %t-x86-64 | FileCheck %s -check-prefix ELF-x86-64
+# RUN: llvm-objdump -r %t-x86-64 | FileCheck %s --check-prefix=ELF-x86-64
 
 # ELF-x86-64: .text
 # ELF-x86-64: R_X86_64_32S .section
diff --git a/llvm/test/Object/objdump-section-content.test b/llvm/test/Object/objdump-section-content.test
index 53ef60928b38a..d4c2cd8190b7c 100644
--- a/llvm/test/Object/objdump-section-content.test
+++ b/llvm/test/Object/objdump-section-content.test
@@ -1,4 +1,4 @@
-# RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-objdump -s - | FileCheck %s -check-prefix COFF-i386
+# RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-objdump -s - | FileCheck %s --check-prefix=COFF-i386
 
 # COFF-i386: file format
 # COFF-i386: Contents of section .text:
@@ -9,7 +9,7 @@
 # COFF-i386:  0000 48656c6c 6f20576f 726c6421 00        Hello World!.
 
 # RUN: yaml2obj %s -o %t.elf-i386
-# RUN: llvm-objdump -s %t.elf-i386 | FileCheck %s -DFILE=%t.elf-i386 -check-prefix ELF-i386
+# RUN: llvm-objdump -s %t.elf-i386 | FileCheck %s -DFILE=%t.elf-i386 --check-prefix=ELF-i386
 
 # ELF-i386: [[FILE]]:     file format
 # ELF-i386: Contents of section .text:
diff --git a/llvm/test/Object/objdump-symbol-table.test b/llvm/test/Object/objdump-symbol-table.test
index 31aed81d68408..c1dab8befe8cb 100644
--- a/llvm/test/Object/objdump-symbol-table.test
+++ b/llvm/test/Object/objdump-symbol-table.test
@@ -13,7 +13,7 @@
 # COFF-i386: [  7](sec  0)(fl 0x00)(ty   0)(scl   2) (nx 0) 0x00000000 _SomeOtherFunction
 
 # RUN: yaml2obj %s -o %t.elf-i386
-# RUN: llvm-objdump -t %t.elf-i386 | FileCheck %s -check-prefix ELF-i386
+# RUN: llvm-objdump -t %t.elf-i386 | FileCheck %s --check-prefix=ELF-i386
 
 # ELF-i386: {{.*}}elf-i386:     file format
 # ELF-i386: SYMBOL TABLE:
diff --git a/llvm/test/ObjectYAML/CodeView/sections.yaml b/llvm/test/ObjectYAML/CodeView/sections.yaml
index 9d13e62f9e4f4..fbdf9bf8625f9 100644
--- a/llvm/test/ObjectYAML/CodeView/sections.yaml
+++ b/llvm/test/ObjectYAML/CodeView/sections.yaml
@@ -1,6 +1,6 @@
 # RUN: yaml2obj %s -o %t.obj
 # RUN: obj2yaml %t.obj | FileCheck --check-prefix=CHECK %s
-# RUN: llvm-objdump -section-headers %t.obj | FileCheck --check-prefix=HEADERS %s
+# RUN: llvm-objdump --section-headers %t.obj | FileCheck --check-prefix=HEADERS %s
 
 --- !COFF
 header:
diff --git a/llvm/test/ThinLTO/X86/empty-module.ll b/llvm/test/ThinLTO/X86/empty-module.ll
index 0f4543446d357..550be4df66573 100644
--- a/llvm/test/ThinLTO/X86/empty-module.ll
+++ b/llvm/test/ThinLTO/X86/empty-module.ll
@@ -5,7 +5,7 @@
 ; RUN: llvm-readobj -h %t2.0 | FileCheck %s
 ; RUN: llvm-nm %t2.0 2>&1 | count 0
 
-; CHECK: Format: ELF64-x86-64
+; CHECK: Format: elf64-x86-64
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/merge-range-and-undef.ll b/llvm/test/Transforms/CorrelatedValuePropagation/merge-range-and-undef.ll
index ffc92f5ab45cb..271c52af779dc 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/merge-range-and-undef.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/merge-range-and-undef.ll
@@ -199,7 +199,8 @@ define i64 @constant_range_and_undef_3_incoming_v2(i1 %c1, i1 %c2, i64 %a) {
 ; CHECK-NEXT:    br label [[BB4]]
 ; CHECK:       bb4:
 ; CHECK-NEXT:    [[P:%.*]] = phi i64 [ undef, [[BB1]] ], [ 10, [[BB2]] ], [ [[R]], [[BB3]] ]
-; CHECK-NEXT:    ret i64 [[P]]
+; CHECK-NEXT:    [[RES:%.*]] = and i64 [[P]], 255
+; CHECK-NEXT:    ret i64 [[RES]]
 ;
 entry:
   br i1 %c1, label %bb1, label %bb2
diff --git a/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll b/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
index a95dc518573b4..b8cfe04d43cb8 100644
--- a/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
+++ b/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
@@ -9,8 +9,25 @@ define i32 @cmp2(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL-LABEL: @cmp2(
 ; ALL-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i16*
 ; ALL-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i16*
-; ALL-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]]
-; ALL-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]]
+; ALL-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 1
+; ALL-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 1
+; ALL-NEXT:    [[TMP5:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP3]])
+; ALL-NEXT:    [[TMP6:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP4]])
+; ALL-NEXT:    [[TMP7:%.*]] = zext i16 [[TMP5]] to i32
+; ALL-NEXT:    [[TMP8:%.*]] = zext i16 [[TMP6]] to i32
+; ALL-NEXT:    [[TMP9:%.*]] = sub i32 [[TMP7]], [[TMP8]]
+; ALL-NEXT:    ret i32 [[TMP9]]
+;
+  %call = tail call i32 @memcmp(i8* %x, i8* %y, i64 2)
+  ret i32 %call
+}
+
+define i32 @cmp2_align2(i8* nocapture readonly align 2 %x, i8* nocapture readonly align 2 %y)  {
+; ALL-LABEL: @cmp2_align2(
+; ALL-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i16*
+; ALL-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i16*
+; ALL-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 2
+; ALL-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 2
 ; ALL-NEXT:    [[TMP5:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP3]])
 ; ALL-NEXT:    [[TMP6:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP4]])
 ; ALL-NEXT:    [[TMP7:%.*]] = zext i16 [[TMP5]] to i32
@@ -32,8 +49,8 @@ define i32 @cmp3(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL:       loadbb:
 ; ALL-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i16*
 ; ALL-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i16*
-; ALL-NEXT:    [[TMP5:%.*]] = load i16, i16* [[TMP3]]
-; ALL-NEXT:    [[TMP6:%.*]] = load i16, i16* [[TMP4]]
+; ALL-NEXT:    [[TMP5:%.*]] = load i16, i16* [[TMP3]], align 1
+; ALL-NEXT:    [[TMP6:%.*]] = load i16, i16* [[TMP4]], align 1
 ; ALL-NEXT:    [[TMP7]] = call i16 @llvm.bswap.i16(i16 [[TMP5]])
 ; ALL-NEXT:    [[TMP8]] = call i16 @llvm.bswap.i16(i16 [[TMP6]])
 ; ALL-NEXT:    [[TMP9:%.*]] = icmp eq i16 [[TMP7]], [[TMP8]]
@@ -41,8 +58,8 @@ define i32 @cmp3(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL:       loadbb1:
 ; ALL-NEXT:    [[TMP10:%.*]] = getelementptr i8, i8* [[X]], i64 2
 ; ALL-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 2
-; ALL-NEXT:    [[TMP12:%.*]] = load i8, i8* [[TMP10]]
-; ALL-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP11]]
+; ALL-NEXT:    [[TMP12:%.*]] = load i8, i8* [[TMP10]], align 1
+; ALL-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP11]], align 1
 ; ALL-NEXT:    [[TMP14:%.*]] = zext i8 [[TMP12]] to i32
 ; ALL-NEXT:    [[TMP15:%.*]] = zext i8 [[TMP13]] to i32
 ; ALL-NEXT:    [[TMP16:%.*]] = sub i32 [[TMP14]], [[TMP15]]
@@ -59,8 +76,8 @@ define i32 @cmp4(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL-LABEL: @cmp4(
 ; ALL-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; ALL-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; ALL-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; ALL-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; ALL-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; ALL-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; ALL-NEXT:    [[TMP5:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP3]])
 ; ALL-NEXT:    [[TMP6:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP4]])
 ; ALL-NEXT:    [[TMP7:%.*]] = icmp ugt i32 [[TMP5]], [[TMP6]]
@@ -84,8 +101,8 @@ define i32 @cmp5(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL:       loadbb:
 ; ALL-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; ALL-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; ALL-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]]
-; ALL-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP4]]
+; ALL-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 1
+; ALL-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP4]], align 1
 ; ALL-NEXT:    [[TMP7]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])
 ; ALL-NEXT:    [[TMP8]] = call i32 @llvm.bswap.i32(i32 [[TMP6]])
 ; ALL-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP7]], [[TMP8]]
@@ -93,8 +110,8 @@ define i32 @cmp5(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL:       loadbb1:
 ; ALL-NEXT:    [[TMP10:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; ALL-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 4
-; ALL-NEXT:    [[TMP12:%.*]] = load i8, i8* [[TMP10]]
-; ALL-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP11]]
+; ALL-NEXT:    [[TMP12:%.*]] = load i8, i8* [[TMP10]], align 1
+; ALL-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP11]], align 1
 ; ALL-NEXT:    [[TMP14:%.*]] = zext i8 [[TMP12]] to i32
 ; ALL-NEXT:    [[TMP15:%.*]] = zext i8 [[TMP13]] to i32
 ; ALL-NEXT:    [[TMP16:%.*]] = sub i32 [[TMP14]], [[TMP15]]
@@ -119,8 +136,8 @@ define i32 @cmp6(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL:       loadbb:
 ; ALL-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; ALL-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; ALL-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]]
-; ALL-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP4]]
+; ALL-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 1
+; ALL-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP4]], align 1
 ; ALL-NEXT:    [[TMP7]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])
 ; ALL-NEXT:    [[TMP8]] = call i32 @llvm.bswap.i32(i32 [[TMP6]])
 ; ALL-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP7]], [[TMP8]]
@@ -130,8 +147,8 @@ define i32 @cmp6(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 4
 ; ALL-NEXT:    [[TMP12:%.*]] = bitcast i8* [[TMP10]] to i16*
 ; ALL-NEXT:    [[TMP13:%.*]] = bitcast i8* [[TMP11]] to i16*
-; ALL-NEXT:    [[TMP14:%.*]] = load i16, i16* [[TMP12]]
-; ALL-NEXT:    [[TMP15:%.*]] = load i16, i16* [[TMP13]]
+; ALL-NEXT:    [[TMP14:%.*]] = load i16, i16* [[TMP12]], align 1
+; ALL-NEXT:    [[TMP15:%.*]] = load i16, i16* [[TMP13]], align 1
 ; ALL-NEXT:    [[TMP16:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP14]])
 ; ALL-NEXT:    [[TMP17:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP15]])
 ; ALL-NEXT:    [[TMP18]] = zext i16 [[TMP16]] to i32
@@ -167,8 +184,8 @@ define i32 @cmp8(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32:       loadbb:
 ; X32-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X32-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]]
-; X32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP4]]
+; X32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 1
+; X32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP4]], align 1
 ; X32-NEXT:    [[TMP7]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])
 ; X32-NEXT:    [[TMP8]] = call i32 @llvm.bswap.i32(i32 [[TMP6]])
 ; X32-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP7]], [[TMP8]]
@@ -178,8 +195,8 @@ define i32 @cmp8(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 4
 ; X32-NEXT:    [[TMP12:%.*]] = bitcast i8* [[TMP10]] to i32*
 ; X32-NEXT:    [[TMP13:%.*]] = bitcast i8* [[TMP11]] to i32*
-; X32-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP12]]
-; X32-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP13]]
+; X32-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP12]], align 1
+; X32-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP13]], align 1
 ; X32-NEXT:    [[TMP16]] = call i32 @llvm.bswap.i32(i32 [[TMP14]])
 ; X32-NEXT:    [[TMP17]] = call i32 @llvm.bswap.i32(i32 [[TMP15]])
 ; X32-NEXT:    [[TMP18:%.*]] = icmp eq i32 [[TMP16]], [[TMP17]]
@@ -191,8 +208,8 @@ define i32 @cmp8(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64-LABEL: @cmp8(
 ; X64-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64-NEXT:    [[TMP5:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP3]])
 ; X64-NEXT:    [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP4]])
 ; X64-NEXT:    [[TMP7:%.*]] = icmp ugt i64 [[TMP5]], [[TMP6]]
@@ -220,8 +237,8 @@ define i32 @cmp9(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64:       loadbb:
 ; X64-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]]
-; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]]
+; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]], align 1
+; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]], align 1
 ; X64-NEXT:    [[TMP7]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])
 ; X64-NEXT:    [[TMP8]] = call i64 @llvm.bswap.i64(i64 [[TMP6]])
 ; X64-NEXT:    [[TMP9:%.*]] = icmp eq i64 [[TMP7]], [[TMP8]]
@@ -229,8 +246,8 @@ define i32 @cmp9(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64:       loadbb1:
 ; X64-NEXT:    [[TMP10:%.*]] = getelementptr i8, i8* [[X]], i64 8
 ; X64-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 8
-; X64-NEXT:    [[TMP12:%.*]] = load i8, i8* [[TMP10]]
-; X64-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP11]]
+; X64-NEXT:    [[TMP12:%.*]] = load i8, i8* [[TMP10]], align 1
+; X64-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP11]], align 1
 ; X64-NEXT:    [[TMP14:%.*]] = zext i8 [[TMP12]] to i32
 ; X64-NEXT:    [[TMP15:%.*]] = zext i8 [[TMP13]] to i32
 ; X64-NEXT:    [[TMP16:%.*]] = sub i32 [[TMP14]], [[TMP15]]
@@ -259,8 +276,8 @@ define i32 @cmp10(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64:       loadbb:
 ; X64-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]]
-; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]]
+; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]], align 1
+; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]], align 1
 ; X64-NEXT:    [[TMP7]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])
 ; X64-NEXT:    [[TMP8]] = call i64 @llvm.bswap.i64(i64 [[TMP6]])
 ; X64-NEXT:    [[TMP9:%.*]] = icmp eq i64 [[TMP7]], [[TMP8]]
@@ -270,8 +287,8 @@ define i32 @cmp10(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64-NEXT:    [[TMP12:%.*]] = bitcast i8* [[TMP10]] to i16*
 ; X64-NEXT:    [[TMP13:%.*]] = bitcast i8* [[TMP11]] to i16*
-; X64-NEXT:    [[TMP14:%.*]] = load i16, i16* [[TMP12]]
-; X64-NEXT:    [[TMP15:%.*]] = load i16, i16* [[TMP13]]
+; X64-NEXT:    [[TMP14:%.*]] = load i16, i16* [[TMP12]], align 1
+; X64-NEXT:    [[TMP15:%.*]] = load i16, i16* [[TMP13]], align 1
 ; X64-NEXT:    [[TMP16:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP14]])
 ; X64-NEXT:    [[TMP17:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP15]])
 ; X64-NEXT:    [[TMP18]] = zext i16 [[TMP16]] to i64
@@ -311,8 +328,8 @@ define i32 @cmp12(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64:       loadbb:
 ; X64-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]]
-; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]]
+; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]], align 1
+; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]], align 1
 ; X64-NEXT:    [[TMP7]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])
 ; X64-NEXT:    [[TMP8]] = call i64 @llvm.bswap.i64(i64 [[TMP6]])
 ; X64-NEXT:    [[TMP9:%.*]] = icmp eq i64 [[TMP7]], [[TMP8]]
@@ -322,8 +339,8 @@ define i32 @cmp12(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64-NEXT:    [[TMP12:%.*]] = bitcast i8* [[TMP10]] to i32*
 ; X64-NEXT:    [[TMP13:%.*]] = bitcast i8* [[TMP11]] to i32*
-; X64-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP12]]
-; X64-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP13]]
+; X64-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP12]], align 1
+; X64-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP13]], align 1
 ; X64-NEXT:    [[TMP16:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP14]])
 ; X64-NEXT:    [[TMP17:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP15]])
 ; X64-NEXT:    [[TMP18]] = zext i32 [[TMP16]] to i64
@@ -381,8 +398,8 @@ define i32 @cmp16(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64:       loadbb:
 ; X64-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64-NEXT:    [[TMP4:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]]
-; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]]
+; X64-NEXT:    [[TMP5:%.*]] = load i64, i64* [[TMP3]], align 1
+; X64-NEXT:    [[TMP6:%.*]] = load i64, i64* [[TMP4]], align 1
 ; X64-NEXT:    [[TMP7]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])
 ; X64-NEXT:    [[TMP8]] = call i64 @llvm.bswap.i64(i64 [[TMP6]])
 ; X64-NEXT:    [[TMP9:%.*]] = icmp eq i64 [[TMP7]], [[TMP8]]
@@ -392,8 +409,8 @@ define i32 @cmp16(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64-NEXT:    [[TMP11:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64-NEXT:    [[TMP12:%.*]] = bitcast i8* [[TMP10]] to i64*
 ; X64-NEXT:    [[TMP13:%.*]] = bitcast i8* [[TMP11]] to i64*
-; X64-NEXT:    [[TMP14:%.*]] = load i64, i64* [[TMP12]]
-; X64-NEXT:    [[TMP15:%.*]] = load i64, i64* [[TMP13]]
+; X64-NEXT:    [[TMP14:%.*]] = load i64, i64* [[TMP12]], align 1
+; X64-NEXT:    [[TMP15:%.*]] = load i64, i64* [[TMP13]], align 1
 ; X64-NEXT:    [[TMP16]] = call i64 @llvm.bswap.i64(i64 [[TMP14]])
 ; X64-NEXT:    [[TMP17]] = call i64 @llvm.bswap.i64(i64 [[TMP15]])
 ; X64-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[TMP16]], [[TMP17]]
@@ -410,8 +427,8 @@ define i32 @cmp_eq2(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL-LABEL: @cmp_eq2(
 ; ALL-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i16*
 ; ALL-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i16*
-; ALL-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]]
-; ALL-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]]
+; ALL-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 1
+; ALL-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 1
 ; ALL-NEXT:    [[TMP5:%.*]] = icmp ne i16 [[TMP3]], [[TMP4]]
 ; ALL-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
 ; ALL-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP6]], 0
@@ -428,13 +445,13 @@ define i32 @cmp_eq3(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32-LABEL: @cmp_eq3(
 ; X32-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i16*
 ; X32-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i16*
-; X32-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]]
-; X32-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]]
+; X32-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 1
+; X32-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 1
 ; X32-NEXT:    [[TMP5:%.*]] = xor i16 [[TMP3]], [[TMP4]]
 ; X32-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 2
 ; X32-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 2
-; X32-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X32-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X32-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X32-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X32-NEXT:    [[TMP10:%.*]] = zext i8 [[TMP8]] to i16
 ; X32-NEXT:    [[TMP11:%.*]] = zext i8 [[TMP9]] to i16
 ; X32-NEXT:    [[TMP12:%.*]] = xor i16 [[TMP10]], [[TMP11]]
@@ -452,15 +469,15 @@ define i32 @cmp_eq3(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i16*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i16*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i16 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
 ; X64_1LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 2
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 2
-; X64_1LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X64_1LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X64_1LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X64_1LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X64_1LD-NEXT:    [[TMP10:%.*]] = icmp ne i8 [[TMP8]], [[TMP9]]
 ; X64_1LD-NEXT:    br i1 [[TMP10]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -472,13 +489,13 @@ define i32 @cmp_eq3(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq3(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i16*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i16*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i16 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 2
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 2
-; X64_2LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X64_2LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X64_2LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X64_2LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X64_2LD-NEXT:    [[TMP10:%.*]] = zext i8 [[TMP8]] to i16
 ; X64_2LD-NEXT:    [[TMP11:%.*]] = zext i8 [[TMP9]] to i16
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i16 [[TMP10]], [[TMP11]]
@@ -499,8 +516,8 @@ define i32 @cmp_eq4(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; ALL-LABEL: @cmp_eq4(
 ; ALL-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; ALL-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; ALL-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; ALL-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; ALL-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; ALL-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; ALL-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP3]], [[TMP4]]
 ; ALL-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
 ; ALL-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP6]], 0
@@ -517,13 +534,13 @@ define i32 @cmp_eq5(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32-LABEL: @cmp_eq5(
 ; X32-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X32-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X32-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X32-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; X32-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
-; X32-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X32-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X32-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X32-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X32-NEXT:    [[TMP10:%.*]] = zext i8 [[TMP8]] to i32
 ; X32-NEXT:    [[TMP11:%.*]] = zext i8 [[TMP9]] to i32
 ; X32-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], [[TMP11]]
@@ -541,15 +558,15 @@ define i32 @cmp_eq5(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
 ; X64_1LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
-; X64_1LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X64_1LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X64_1LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X64_1LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X64_1LD-NEXT:    [[TMP10:%.*]] = icmp ne i8 [[TMP8]], [[TMP9]]
 ; X64_1LD-NEXT:    br i1 [[TMP10]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -561,13 +578,13 @@ define i32 @cmp_eq5(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq5(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
-; X64_2LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X64_2LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X64_2LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X64_2LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X64_2LD-NEXT:    [[TMP10:%.*]] = zext i8 [[TMP8]] to i32
 ; X64_2LD-NEXT:    [[TMP11:%.*]] = zext i8 [[TMP9]] to i32
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], [[TMP11]]
@@ -588,15 +605,15 @@ define i32 @cmp_eq6(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32-LABEL: @cmp_eq6(
 ; X32-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X32-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X32-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X32-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; X32-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
 ; X32-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
 ; X32-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
-; X32-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]]
-; X32-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]]
+; X32-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 1
+; X32-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 1
 ; X32-NEXT:    [[TMP12:%.*]] = zext i16 [[TMP10]] to i32
 ; X32-NEXT:    [[TMP13:%.*]] = zext i16 [[TMP11]] to i32
 ; X32-NEXT:    [[TMP14:%.*]] = xor i32 [[TMP12]], [[TMP13]]
@@ -614,8 +631,8 @@ define i32 @cmp_eq6(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -623,8 +640,8 @@ define i32 @cmp_eq6(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i16 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -636,15 +653,92 @@ define i32 @cmp_eq6(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq6(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
+; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
+; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
+; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
+; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
+; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 1
+; X64_2LD-NEXT:    [[TMP12:%.*]] = zext i16 [[TMP10]] to i32
+; X64_2LD-NEXT:    [[TMP13:%.*]] = zext i16 [[TMP11]] to i32
+; X64_2LD-NEXT:    [[TMP14:%.*]] = xor i32 [[TMP12]], [[TMP13]]
+; X64_2LD-NEXT:    [[TMP15:%.*]] = or i32 [[TMP5]], [[TMP14]]
+; X64_2LD-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
+; X64_2LD-NEXT:    [[TMP17:%.*]] = zext i1 [[TMP16]] to i32
+; X64_2LD-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP17]], 0
+; X64_2LD-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; X64_2LD-NEXT:    ret i32 [[CONV]]
+;
+  %call = tail call i32 @memcmp(i8* %x, i8* %y, i64 6)
+  %cmp = icmp eq i32 %call, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define i32 @cmp_eq6_align4(i8* nocapture readonly align 4 %x, i8* nocapture readonly align 4 %y)  {
+; X32-LABEL: @cmp_eq6_align4(
+; X32-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
+; X32-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
+; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4
+; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4
+; X32-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
+; X32-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
+; X32-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
+; X32-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
+; X32-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
+; X32-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 4
+; X32-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 4
+; X32-NEXT:    [[TMP12:%.*]] = zext i16 [[TMP10]] to i32
+; X32-NEXT:    [[TMP13:%.*]] = zext i16 [[TMP11]] to i32
+; X32-NEXT:    [[TMP14:%.*]] = xor i32 [[TMP12]], [[TMP13]]
+; X32-NEXT:    [[TMP15:%.*]] = or i32 [[TMP5]], [[TMP14]]
+; X32-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
+; X32-NEXT:    [[TMP17:%.*]] = zext i1 [[TMP16]] to i32
+; X32-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP17]], 0
+; X32-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; X32-NEXT:    ret i32 [[CONV]]
+;
+; X64_1LD-LABEL: @cmp_eq6_align4(
+; X64_1LD-NEXT:    br label [[LOADBB:%.*]]
+; X64_1LD:       res_block:
+; X64_1LD-NEXT:    br label [[ENDBLOCK:%.*]]
+; X64_1LD:       loadbb:
+; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
+; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4
+; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP3]], [[TMP4]]
+; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
+; X64_1LD:       loadbb1:
+; X64_1LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
+; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
+; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
+; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 4
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 4
+; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i16 [[TMP10]], [[TMP11]]
+; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
+; X64_1LD:       endblock:
+; X64_1LD-NEXT:    [[PHI_RES:%.*]] = phi i32 [ 0, [[LOADBB1]] ], [ 1, [[RES_BLOCK]] ]
+; X64_1LD-NEXT:    [[CMP:%.*]] = icmp eq i32 [[PHI_RES]], 0
+; X64_1LD-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; X64_1LD-NEXT:    ret i32 [[CONV]]
+;
+; X64_2LD-LABEL: @cmp_eq6_align4(
+; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
+; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 4
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 4
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = zext i16 [[TMP10]] to i32
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = zext i16 [[TMP11]] to i32
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = xor i32 [[TMP12]], [[TMP13]]
@@ -665,15 +759,15 @@ define i32 @cmp_eq7(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32-LABEL: @cmp_eq7(
 ; X32-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X32-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X32-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X32-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 3
 ; X32-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 3
 ; X32-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i32*
 ; X32-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i32*
-; X32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]]
-; X32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]]
+; X32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 1
+; X32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 1
 ; X32-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], [[TMP11]]
 ; X32-NEXT:    [[TMP13:%.*]] = or i32 [[TMP5]], [[TMP12]]
 ; X32-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
@@ -689,8 +783,8 @@ define i32 @cmp_eq7(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -698,8 +792,8 @@ define i32 @cmp_eq7(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 3
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i32*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i32*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -711,15 +805,15 @@ define i32 @cmp_eq7(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq7(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 3
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 3
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i32*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i32*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], [[TMP11]]
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = or i32 [[TMP5]], [[TMP12]]
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
@@ -738,15 +832,15 @@ define i32 @cmp_eq8(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X32-LABEL: @cmp_eq8(
 ; X32-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; X32-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32*
-; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]]
-; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]]
+; X32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 1
+; X32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 1
 ; X32-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]]
 ; X32-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 4
 ; X32-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4
 ; X32-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i32*
 ; X32-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i32*
-; X32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]]
-; X32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]]
+; X32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 1
+; X32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 1
 ; X32-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], [[TMP11]]
 ; X32-NEXT:    [[TMP13:%.*]] = or i32 [[TMP5]], [[TMP12]]
 ; X32-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
@@ -758,8 +852,8 @@ define i32 @cmp_eq8(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64-LABEL: @cmp_eq8(
 ; X64-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
 ; X64-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP6]], 0
@@ -786,15 +880,15 @@ define i32 @cmp_eq9(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
 ; X64_1LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 8
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8
-; X64_1LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X64_1LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X64_1LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X64_1LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X64_1LD-NEXT:    [[TMP10:%.*]] = icmp ne i8 [[TMP8]], [[TMP9]]
 ; X64_1LD-NEXT:    br i1 [[TMP10]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -806,13 +900,13 @@ define i32 @cmp_eq9(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq9(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 8
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8
-; X64_2LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]]
-; X64_2LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]]
+; X64_2LD-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP6]], align 1
+; X64_2LD-NEXT:    [[TMP9:%.*]] = load i8, i8* [[TMP7]], align 1
 ; X64_2LD-NEXT:    [[TMP10:%.*]] = zext i8 [[TMP8]] to i64
 ; X64_2LD-NEXT:    [[TMP11:%.*]] = zext i8 [[TMP9]] to i64
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i64 [[TMP10]], [[TMP11]]
@@ -843,8 +937,8 @@ define i32 @cmp_eq10(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -852,8 +946,8 @@ define i32 @cmp_eq10(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i16 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -865,15 +959,15 @@ define i32 @cmp_eq10(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq10(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 8
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i16*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i16*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i16, i16* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = zext i16 [[TMP10]] to i64
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = zext i16 [[TMP11]] to i64
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = xor i64 [[TMP12]], [[TMP13]]
@@ -904,8 +998,8 @@ define i32 @cmp_eq11(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -913,8 +1007,8 @@ define i32 @cmp_eq11(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 3
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i64 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -926,15 +1020,15 @@ define i32 @cmp_eq11(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq11(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 3
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 3
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i64 [[TMP10]], [[TMP11]]
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = or i64 [[TMP5]], [[TMP12]]
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0
@@ -963,8 +1057,8 @@ define i32 @cmp_eq12(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -972,8 +1066,8 @@ define i32 @cmp_eq12(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i32*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i32*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -985,15 +1079,15 @@ define i32 @cmp_eq12(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq12(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 8
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i32*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i32*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP10]] to i64
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = zext i32 [[TMP11]] to i64
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = xor i64 [[TMP12]], [[TMP13]]
@@ -1024,8 +1118,8 @@ define i32 @cmp_eq13(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -1033,8 +1127,8 @@ define i32 @cmp_eq13(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 5
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i64 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -1046,15 +1140,15 @@ define i32 @cmp_eq13(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq13(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 5
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 5
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i64 [[TMP10]], [[TMP11]]
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = or i64 [[TMP5]], [[TMP12]]
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0
@@ -1083,8 +1177,8 @@ define i32 @cmp_eq14(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -1092,8 +1186,8 @@ define i32 @cmp_eq14(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 6
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i64 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -1105,15 +1199,15 @@ define i32 @cmp_eq14(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq14(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 6
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 6
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i64 [[TMP10]], [[TMP11]]
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = or i64 [[TMP5]], [[TMP12]]
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0
@@ -1142,8 +1236,8 @@ define i32 @cmp_eq15(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD:       loadbb:
 ; X64_1LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_1LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_1LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_1LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_1LD-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
 ; X64_1LD-NEXT:    br i1 [[TMP5]], label [[RES_BLOCK:%.*]], label [[LOADBB1:%.*]]
 ; X64_1LD:       loadbb1:
@@ -1151,8 +1245,8 @@ define i32 @cmp_eq15(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_1LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 7
 ; X64_1LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_1LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_1LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_1LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_1LD-NEXT:    [[TMP12:%.*]] = icmp ne i64 [[TMP10]], [[TMP11]]
 ; X64_1LD-NEXT:    br i1 [[TMP12]], label [[RES_BLOCK]], label [[ENDBLOCK]]
 ; X64_1LD:       endblock:
@@ -1164,15 +1258,15 @@ define i32 @cmp_eq15(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64_2LD-LABEL: @cmp_eq15(
 ; X64_2LD-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i64*
 ; X64_2LD-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i64*
-; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]]
-; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]]
+; X64_2LD-NEXT:    [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 1
+; X64_2LD-NEXT:    [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 1
 ; X64_2LD-NEXT:    [[TMP5:%.*]] = xor i64 [[TMP3]], [[TMP4]]
 ; X64_2LD-NEXT:    [[TMP6:%.*]] = getelementptr i8, i8* [[X]], i64 7
 ; X64_2LD-NEXT:    [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 7
 ; X64_2LD-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP6]] to i64*
 ; X64_2LD-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP7]] to i64*
-; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]]
-; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]]
+; X64_2LD-NEXT:    [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 1
+; X64_2LD-NEXT:    [[TMP11:%.*]] = load i64, i64* [[TMP9]], align 1
 ; X64_2LD-NEXT:    [[TMP12:%.*]] = xor i64 [[TMP10]], [[TMP11]]
 ; X64_2LD-NEXT:    [[TMP13:%.*]] = or i64 [[TMP5]], [[TMP12]]
 ; X64_2LD-NEXT:    [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0
@@ -1197,8 +1291,8 @@ define i32 @cmp_eq16(i8* nocapture readonly %x, i8* nocapture readonly %y)  {
 ; X64-LABEL: @cmp_eq16(
 ; X64-NEXT:    [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i128*
 ; X64-NEXT:    [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i128*
-; X64-NEXT:    [[TMP3:%.*]] = load i128, i128* [[TMP1]]
-; X64-NEXT:    [[TMP4:%.*]] = load i128, i128* [[TMP2]]
+; X64-NEXT:    [[TMP3:%.*]] = load i128, i128* [[TMP1]], align 1
+; X64-NEXT:    [[TMP4:%.*]] = load i128, i128* [[TMP2]], align 1
 ; X64-NEXT:    [[TMP5:%.*]] = icmp ne i128 [[TMP3]], [[TMP4]]
 ; X64-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
 ; X64-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP6]], 0
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
index 1fc6b55b664fd..39a8c3c923276 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
@@ -2674,6 +2674,122 @@ define <32 x i16> @avx512_psllv_w_512_undef(<32 x i16> %v) {
   ret <32 x i16> %2
 }
 
+;
+; Vector Masked Shift Amounts
+;
+
+define <4 x i32> @avx2_psrav_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psrav_d_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = and <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i32> @avx2_psrav_d_128_masked_shuffle(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psrav_d_128_masked_shuffle(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 undef, i32 undef, i32 15, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
+;
+  %1 = and <4 x i32> %a, <i32 undef, i32 undef, i32 15, i32 31>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+  %3 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %2)
+  ret <4 x i32> %3
+}
+
+define <8 x i32> @avx2_psrav_d_256_masked(<8 x i32> %v, <8 x i32> %a) {
+; CHECK-LABEL: @avx2_psrav_d_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i32> [[A:%.*]], <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <8 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = and <8 x i32> %a, <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <32 x i16> @avx512_psrav_w_512_masked(<32 x i16> %v, <32 x i16> %a) {
+; CHECK-LABEL: @avx512_psrav_w_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <32 x i16> [[A:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <32 x i16> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = and <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
+define <2 x i64> @avx2_psrlv_q_128_masked(<2 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx2_psrlv_q_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 32, i64 63>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <2 x i64> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+;
+  %1 = and <2 x i64> %a, <i64 32, i64 63>
+  %2 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <8 x i32> @avx2_psrlv_d_256_masked(<8 x i32> %v, <8 x i32> %a) {
+; CHECK-LABEL: @avx2_psrlv_d_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i32> [[A:%.*]], <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <8 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = and <8 x i32> %a, <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <8 x i64> @avx512_psrlv_q_512_masked(<8 x i64> %v, <8 x i64> %a) {
+; CHECK-LABEL: @avx512_psrlv_q_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i64> [[A:%.*]], <i64 0, i64 1, i64 4, i64 16, i64 32, i64 47, i64 62, i64 63>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <8 x i64> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP2]]
+;
+  %1 = and <8 x i64> %a, <i64 0, i64 1, i64 4, i64 16, i64 32, i64 47, i64 62, i64 63>
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <4 x i32> @avx2_psllv_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psllv_d_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 16, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <4 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = and <4 x i32> %a, <i32 0, i32 15, i32 16, i32 31>
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i64> @avx2_psllv_q_256_masked(<4 x i64> %v, <4 x i64> %a) {
+; CHECK-LABEL: @avx2_psllv_q_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i64> [[A:%.*]], <i64 0, i64 16, i64 32, i64 63>
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <4 x i64> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP2]]
+;
+  %1 = and <4 x i64> %a, <i64 0, i64 16, i64 32, i64 63>
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psllv_w_512_masked(<32 x i16> %v, <32 x i16> %a) {
+; CHECK-LABEL: @avx512_psllv_w_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <32 x i16> [[A:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <32 x i16> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = and <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
 ;
 ; Vector Demanded Bits
 ;
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 27438b3d86e6b..24fcae5cd870a 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -1181,3 +1181,129 @@ define i32 @lshr_add_use2(i1 %x, i1 %y, i32* %p) {
   %r = lshr i32 %sub, 31
   ret i32 %r
 }
+
+define i32 @lshr_add_sexts(i1 %x, i1 %y) {
+; CHECK-LABEL: @lshr_add_sexts(
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %xs = sext i1 %x to i32
+  %ys = sext i1 %y to i32
+  %sub = add i32 %xs, %ys
+  %r = lshr i32 %sub, 31
+  ret i32 %r
+}
+
+define i5 @and_add_sexts(i1 %x, i1 %y) {
+; CHECK-LABEL: @and_add_sexts(
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i5 -2, i5 0
+; CHECK-NEXT:    ret i5 [[R]]
+;
+  %xs = sext i1 %x to i5
+  %ys = sext i1 %y to i5
+  %sub = add i5 %xs, %ys
+  %r = and i5 %sub, 30
+  ret i5 %r
+}
+
+define <2 x i8> @ashr_add_sexts(<2 x i1> %x, <2 x i1> %y) {
+; CHECK-LABEL: @ashr_add_sexts(
+; CHECK-NEXT:    [[TMP1:%.*]] = or <2 x i1> [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i8>
+; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
+;
+  %xs = sext <2 x i1> %x to <2 x i8>
+  %ys = sext <2 x i1> %y to <2 x i8>
+  %sub = add nsw <2 x i8> %ys, %xs
+  %r = ashr <2 x i8> %sub, <i8 1, i8 1>
+  ret <2 x i8> %r
+}
+
+define i32 @cmp_math_sexts(i32 %x, i32 %y) {
+; CHECK-LABEL: @cmp_math_sexts(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %gt = icmp ugt i32 %x, %y
+  %lt = icmp ult i32 %x, %y
+  %xz = sext i1 %gt to i32
+  %yz = zext i1 %lt to i32
+  %s = sub i32 %xz, %yz
+  %r = lshr i32 %s, 31
+  ret i32 %r
+}
+
+; Negative test - wrong type
+
+define i32 @lshr_add_nonbool_sexts(i2 %x, i1 %y) {
+; CHECK-LABEL: @lshr_add_nonbool_sexts(
+; CHECK-NEXT:    [[XS:%.*]] = sext i2 [[X:%.*]] to i32
+; CHECK-NEXT:    [[YS:%.*]] = sext i1 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[XS]], [[YS]]
+; CHECK-NEXT:    [[R:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %xs = sext i2 %x to i32
+  %ys = sext i1 %y to i32
+  %sub = add i32 %xs, %ys
+  %r = lshr i32 %sub, 31
+  ret i32 %r
+}
+
+; Negative test - wrong demand
+
+define i32 @and31_add_sexts(i1 %x, i1 %y) {
+; CHECK-LABEL: @and31_add_sexts(
+; CHECK-NEXT:    [[XS:%.*]] = sext i1 [[X:%.*]] to i32
+; CHECK-NEXT:    [[YS:%.*]] = sext i1 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[XS]], [[YS]]
+; CHECK-NEXT:    [[R:%.*]] = and i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %xs = sext i1 %x to i32
+  %ys = sext i1 %y to i32
+  %sub = add i32 %xs, %ys
+  %r = and i32 %sub, 31
+  ret i32 %r
+}
+
+; Negative test - extra use
+
+define i32 @lshr_add_use_sexts(i1 %x, i1 %y, i32* %p) {
+; CHECK-LABEL: @lshr_add_use_sexts(
+; CHECK-NEXT:    [[XS:%.*]] = sext i1 [[X:%.*]] to i32
+; CHECK-NEXT:    store i32 [[XS]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[YS:%.*]] = sext i1 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[XS]], [[YS]]
+; CHECK-NEXT:    [[R:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %xs = sext i1 %x to i32
+  store i32 %xs, i32* %p
+  %ys = sext i1 %y to i32
+  %sub = add i32 %xs, %ys
+  %r = lshr i32 %sub, 31
+  ret i32 %r
+}
+
+; Negative test - extra use
+
+define i32 @lshr_add_use2_sexts(i1 %x, i1 %y, i32* %p) {
+; CHECK-LABEL: @lshr_add_use2_sexts(
+; CHECK-NEXT:    [[XS:%.*]] = sext i1 [[X:%.*]] to i32
+; CHECK-NEXT:    [[YS:%.*]] = sext i1 [[Y:%.*]] to i32
+; CHECK-NEXT:    store i32 [[YS]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[XS]], [[YS]]
+; CHECK-NEXT:    [[R:%.*]] = lshr i32 [[SUB]], 31
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %xs = sext i1 %x to i32
+  %ys = sext i1 %y to i32
+  store i32 %ys, i32* %p
+  %sub = add i32 %xs, %ys
+  %r = lshr i32 %sub, 31
+  ret i32 %r
+}
diff --git a/llvm/test/Transforms/InstCombine/align-attr.ll b/llvm/test/Transforms/InstCombine/align-attr.ll
index 2b004311cc8ea..16782dba2effc 100644
--- a/llvm/test/Transforms/InstCombine/align-attr.ll
+++ b/llvm/test/Transforms/InstCombine/align-attr.ll
@@ -20,7 +20,7 @@ define i32 @foo2(i32* align 32 %a) #0 {
 ; CHECK-LABEL: @foo2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[V:%.*]] = call i32* @func1(i32* [[A:%.*]])
-; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 32
+; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[V]], align 32
 ; CHECK-NEXT:    ret i32 [[TMP0]]
 ;
 entry:
diff --git a/llvm/test/Transforms/InstCombine/assume.ll b/llvm/test/Transforms/InstCombine/assume.ll
index 2d9f2a616e7f0..ff3bf5665ed9f 100644
--- a/llvm/test/Transforms/InstCombine/assume.ll
+++ b/llvm/test/Transforms/InstCombine/assume.ll
@@ -231,6 +231,27 @@ declare void @escape(i32* %a)
 
 ; Canonicalize a nonnull assumption on a load into metadata form.
 
+define i32 @bundle1(i32* %P) {
+; CHECK-LABEL: @bundle1(
+; CHECK-NEXT:    tail call void @llvm.assume(i1 true) [ "nonnull"(i32* [[P:%.*]]) ]
+; CHECK-NEXT:    [[LOAD:%.*]] = load i32, i32* [[P]], align 4
+; CHECK-NEXT:    ret i32 [[LOAD]]
+;
+  tail call void @llvm.assume(i1 true) ["nonnull"(i32* %P)]
+  %load = load i32, i32* %P
+  ret i32 %load
+}
+
+define i32 @bundle2(i32* %P) {
+; CHECK-LABEL: @bundle2(
+; CHECK-NEXT:    [[LOAD:%.*]] = load i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT:    ret i32 [[LOAD]]
+;
+  tail call void @llvm.assume(i1 true) ["ignore"(i32* undef)]
+  %load = load i32, i32* %P
+  ret i32 %load
+}
+
 define i1 @nonnull1(i32** %a) {
 ; CHECK-LABEL: @nonnull1(
 ; CHECK-NEXT:    [[LOAD:%.*]] = load i32*, i32** [[A:%.*]], align 8, !nonnull !6
diff --git a/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll b/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
index a49b4c7af7e39..42e2b131c0c05 100644
--- a/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
+++ b/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
@@ -415,4 +415,23 @@ define void @test_memcpy_loadstore_16(i8* %dest, i8* %src) {
   ret void
 }
 
+define void @test_undefined(i8* %dest, i8* %src) {
+; CHECK-LABEL: @test_undefined(
+entry:
+  br i1 undef, label %ok, label %undefined
+undefined:
+; CHECK: undefined:
+; CHECK-NEXT:    store i1 true, i1* undef
+; CHECK-NEXT:    br label %ok
+  call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 7, i32 4)
+  call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 -8, i32 4)
+  call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 7, i32 4)
+  call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %dest, i8* align 16 %src, i32 -8, i32 4)
+  call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %dest, i8 1, i32 7, i32 4)
+  call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %dest, i8 1, i32 -8, i32 4)
+  br label %ok
+ok:
+  ret void
+}
+
 declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i32) nounwind argmemonly
diff --git a/llvm/test/Transforms/InstCombine/expensive-combines.ll b/llvm/test/Transforms/InstCombine/expensive-combines.ll
index 96a45b05cfb59..28acb773bfd50 100644
--- a/llvm/test/Transforms/InstCombine/expensive-combines.ll
+++ b/llvm/test/Transforms/InstCombine/expensive-combines.ll
@@ -16,7 +16,7 @@ define void @test() {
 ;
 ; EXPENSIVE-OFF-LABEL: @test(
 ; EXPENSIVE-OFF-NEXT:    [[CALL:%.*]] = call i32 @passthru(i32 0)
-; EXPENSIVE-OFF-NEXT:    call void @sink(i32 0)
+; EXPENSIVE-OFF-NEXT:    call void @sink(i32 [[CALL]])
 ; EXPENSIVE-OFF-NEXT:    ret void
 ;
   %call = call i32 @passthru(i32 0)
diff --git a/llvm/test/Transforms/InstCombine/fortify-folding.ll b/llvm/test/Transforms/InstCombine/fortify-folding.ll
index b2171a44f57ef..ee81557615a54 100644
--- a/llvm/test/Transforms/InstCombine/fortify-folding.ll
+++ b/llvm/test/Transforms/InstCombine/fortify-folding.ll
@@ -82,7 +82,7 @@ define i32 @test_not_sprintf() {
 define i8* @test_strcat() {
 ; CHECK-LABEL: @test_strcat(
 ; CHECK-NEXT:    [[STRCAT:%.*]] = call i8* @strcat(i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @a, i64 0, i64 0), i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @b, i64 0, i64 0))
-; CHECK-NEXT:    ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i64 0, i64 0)
+; CHECK-NEXT:    ret i8* [[STRCAT]]
 ;
   %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
@@ -126,7 +126,7 @@ define i64 @test_not_strlcat() {
 define i8* @test_strncat() {
 ; CHECK-LABEL: @test_strncat(
 ; CHECK-NEXT:    [[STRNCAT:%.*]] = call i8* @strncat(i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @a, i64 0, i64 0), i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @b, i64 0, i64 0), i64 22)
-; CHECK-NEXT:    ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i64 0, i64 0)
+; CHECK-NEXT:    ret i8* [[STRNCAT]]
 ;
   %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
diff --git a/llvm/test/Transforms/InstCombine/gep-vector.ll b/llvm/test/Transforms/InstCombine/gep-vector.ll
index 432da0aed2dca..83b8697c3b28b 100644
--- a/llvm/test/Transforms/InstCombine/gep-vector.ll
+++ b/llvm/test/Transforms/InstCombine/gep-vector.ll
@@ -134,3 +134,24 @@ define i32 addrspace(3)* @inbounds_bitcast_vec_to_array_addrspace_matching_alloc
   %gep = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* %asc, i64 %y, i64 %z
   ret i32 addrspace(3)* %gep
 }
+
+; Negative test - avoid doing bitcast on i8*, because '16' should be scaled by 'vscale'.
+
+define i8* @test_accumulate_constant_offset_vscale_nonzero(<vscale x 16 x i1> %pg, i8* %base) {
+; CHECK-LABEL: @test_accumulate_constant_offset_vscale_nonzero
+; CHECK-NEXT:   %bc = bitcast i8* %base to <vscale x 16 x i8>*
+; CHECK-NEXT:   %gep = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %bc, i64 1, i64 4
+; CHECK-NEXT:   ret i8* %gep
+  %bc = bitcast i8* %base to <vscale x 16 x i8>*
+  %gep = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %bc, i64 1, i64 4
+  ret i8* %gep
+}
+
+define i8* @test_accumulate_constant_offset_vscale_zero(<vscale x 16 x i1> %pg, i8* %base) {
+; CHECK-LABEL: @test_accumulate_constant_offset_vscale_zero
+; CHECK-NEXT:   %[[RES:.*]] = getelementptr i8, i8* %base, i64 4
+; CHECK-NEXT:   ret i8* %[[RES]]
+  %bc = bitcast i8* %base to <vscale x 16 x i8>*
+  %gep = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %bc, i64 0, i64 4
+  ret i8* %gep
+}
diff --git a/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll b/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
index 67e393d1525be..02a4b5cbdeac2 100644
--- a/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
+++ b/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
@@ -53,7 +53,7 @@ define i8* @test_simplify3() {
 define i8* @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
 ; CHECK-NEXT:    [[STRCPY:%.*]] = call i8* @strcpy(i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0))
-; CHECK-NEXT:    ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT:    ret i8* [[STRCPY]]
 ;
   %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
diff --git a/llvm/test/Transforms/InstCombine/strncpy_chk-1.ll b/llvm/test/Transforms/InstCombine/strncpy_chk-1.ll
index 7601b16693599..ed90303b28080 100644
--- a/llvm/test/Transforms/InstCombine/strncpy_chk-1.ll
+++ b/llvm/test/Transforms/InstCombine/strncpy_chk-1.ll
@@ -39,7 +39,7 @@ define i8* @test_simplify2() {
 define i8* @test_simplify3() {
 ; CHECK-LABEL: @test_simplify3(
 ; CHECK-NEXT:    [[STRNCPY:%.*]] = call i8* @strncpy(i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0), i8* nonnull dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @b, i32 0, i32 0), i32 12)
-; CHECK-NEXT:    ret i8* getelementptr inbounds ([60 x i8], [60 x i8]* @a, i32 0, i32 0)
+; CHECK-NEXT:    ret i8* [[STRNCPY]]
 ;
   %dst = getelementptr inbounds [60 x i8], [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8], [60 x i8]* @b, i32 0, i32 0
diff --git a/llvm/test/Transforms/InstCombine/unused-nonnull.ll b/llvm/test/Transforms/InstCombine/unused-nonnull.ll
index 382d2634b86c5..0a1520ea73c20 100644
--- a/llvm/test/Transforms/InstCombine/unused-nonnull.ll
+++ b/llvm/test/Transforms/InstCombine/unused-nonnull.ll
@@ -12,8 +12,13 @@ define i32 @main(i32 %argc, i8** %argv) #0 {
 ; CHECK-SAME: (i32 [[ARGC:%.*]], i8** nocapture readnone [[ARGV:%.*]]) local_unnamed_addr #0
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = icmp slt i32 [[ARGC]], 2
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TMP0]], i32 0, i32 [[ARGC]]
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    br i1 [[TMP0]], label [[DONE:%.*]], label [[DO_WORK:%.*]]
+; CHECK:       do_work:
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @compute(i8* undef, i32 [[ARGC]])
+; CHECK-NEXT:    br label [[DONE]]
+; CHECK:       done:
+; CHECK-NEXT:    [[RETVAL:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP1]], [[DO_WORK]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL]]
 ;
 entry:
   %0 = getelementptr inbounds i8*, i8** %argv, i32 0
diff --git a/llvm/test/Transforms/InstSimplify/bitreverse.ll b/llvm/test/Transforms/InstSimplify/bitreverse.ll
index d87b68831fe5b..2194fd45418b6 100644
--- a/llvm/test/Transforms/InstSimplify/bitreverse.ll
+++ b/llvm/test/Transforms/InstSimplify/bitreverse.ll
@@ -1,31 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -S -instsimplify | FileCheck %s
 
 declare i32 @llvm.bitreverse.i32(i32)
+declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>)
 
-; CHECK-LABEL: @test1(
-; CHECK: ret i1 false
 define i1 @test1(i32 %arg) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    ret i1 false
+;
   %a = or i32 %arg, 1
   %b = call i32 @llvm.bitreverse.i32(i32 %a)
   %res = icmp eq i32 %b, 0
   ret i1 %res
 }
 
-; CHECK-LABEL: @test2(
-; CHECK: ret i1 false
+define i1 @test1v(<2 x i32> %arg) {
+; CHECK-LABEL: @test1v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = or <2 x i32> %arg, <i32 1, i32 0>
+  %b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
+  %c = extractelement <2 x i32> %b, i32 0
+  %res = icmp eq i32 %c, 0
+  ret i1 %res
+}
+
 define i1 @test2(i32 %arg) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    ret i1 false
+;
   %a = or i32 %arg, 1024
   %b = call i32 @llvm.bitreverse.i32(i32 %a)
   %res = icmp eq i32 %b, 0
   ret i1 %res
 }
 
-; CHECK-LABEL: @test3(
-; CHECK: ret i1 false
+define i1 @test2v(<2 x i32> %arg) {
+; CHECK-LABEL: @test2v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = or <2 x i32> %arg, <i32 0, i32 1024>
+  %b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
+  %c = extractelement <2 x i32> %b, i32 1
+  %res = icmp eq i32 %c, 0
+  ret i1 %res
+}
+
 define i1 @test3(i32 %arg) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    ret i1 false
+;
   %a = and i32 %arg, 1
   %b = call i32 @llvm.bitreverse.i32(i32 %a)
   %and = and i32 %b, 1
   %res = icmp eq i32 %and, 1
   ret i1 %res
 }
+
+define i1 @test3v(<2 x i32> %arg) {
+; CHECK-LABEL: @test3v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = and <2 x i32> %arg, <i32 1, i32 -1>
+  %b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
+  %and = and <2 x i32> %b, <i32 1, i32 -1>
+  %ext = extractelement <2 x i32> %and, i32 0
+  %res = icmp eq i32 %ext, 1
+  ret i1 %res
+}
diff --git a/llvm/test/Transforms/InstSimplify/bswap.ll b/llvm/test/Transforms/InstSimplify/bswap.ll
index 5c67aa0a7643f..3e7616c3bdc56 100644
--- a/llvm/test/Transforms/InstSimplify/bswap.ll
+++ b/llvm/test/Transforms/InstSimplify/bswap.ll
@@ -1,11 +1,12 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -S -instsimplify | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
+declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>)
 
 define i1 @test1(i16 %arg) {
 ; CHECK-LABEL: @test1(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %a = or i16 %arg, 1
   %b = call i16 @llvm.bswap.i16(i16 %a)
@@ -13,9 +14,20 @@ define i1 @test1(i16 %arg) {
   ret i1 %res
 }
 
+define i1 @test1v(<2 x i16> %arg) {
+; CHECK-LABEL: @test1v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = or <2 x i16> %arg, <i16 1, i16 0>
+  %b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
+  %c = extractelement <2 x i16> %b, i32 0
+  %res = icmp eq i16 %c, 0
+  ret i1 %res
+}
+
 define i1 @test2(i16 %arg) {
 ; CHECK-LABEL: @test2(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %a = or i16 %arg, 1024
   %b = call i16 @llvm.bswap.i16(i16 %a)
@@ -23,9 +35,20 @@ define i1 @test2(i16 %arg) {
   ret i1 %res
 }
 
+define i1 @test2v(<2 x i16> %arg) {
+; CHECK-LABEL: @test2v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = or <2 x i16> %arg, <i16 0, i16 1024>
+  %b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
+  %c = extractelement <2 x i16> %b, i32 1
+  %res = icmp eq i16 %c, 0
+  ret i1 %res
+}
+
 define i1 @test3(i16 %arg) {
 ; CHECK-LABEL: @test3(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %a = and i16 %arg, 1
   %b = call i16 @llvm.bswap.i16(i16 %a)
@@ -34,9 +57,21 @@ define i1 @test3(i16 %arg) {
   ret i1 %res
 }
 
+define i1 @test3v(<2 x i16> %arg) {
+; CHECK-LABEL: @test3v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = and <2 x i16> %arg, <i16 1, i16 -1>
+  %b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
+  %c = extractelement <2 x i16> %b, i32 0
+  %and = and i16 %c, 1
+  %res = icmp eq i16 %and, 1
+  ret i1 %res
+}
+
 define i1 @test4(i16 %arg) {
 ; CHECK-LABEL: @test4(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %a = and i16 %arg, 511
   %b = call i16 @llvm.bswap.i16(i16 %a)
@@ -44,3 +79,15 @@ define i1 @test4(i16 %arg) {
   %res = icmp eq i16 %and, 1
   ret i1 %res
 }
+
+define i1 @test4v(<2 x i16> %arg) {
+; CHECK-LABEL: @test4v(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = and <2 x i16> %arg, <i16 511, i16 511>
+  %b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
+  %and = and <2 x i16> %b, <i16 255, i16 256>
+  %ext = extractelement <2 x i16> %and, i32 1
+  %res = icmp eq i16 %ext, 1
+  ret i1 %res
+}
diff --git a/llvm/test/Transforms/InstSimplify/call.ll b/llvm/test/Transforms/InstSimplify/call.ll
index d744db6ddf766..108de9082a700 100644
--- a/llvm/test/Transforms/InstSimplify/call.ll
+++ b/llvm/test/Transforms/InstSimplify/call.ll
@@ -993,7 +993,7 @@ define i32 @returned_const_int_arg() {
 define i8* @returned_const_ptr_arg() {
 ; CHECK-LABEL: @returned_const_ptr_arg(
 ; CHECK-NEXT:    [[X:%.*]] = call i8* @passthru_p8(i8* null)
-; CHECK-NEXT:    ret i8* null
+; CHECK-NEXT:    ret i8* [[X]]
 ;
   %x = call i8* @passthru_p8(i8* null)
   ret i8* %x
@@ -1002,7 +1002,7 @@ define i8* @returned_const_ptr_arg() {
 define i32 @returned_var_arg(i32 %arg) {
 ; CHECK-LABEL: @returned_var_arg(
 ; CHECK-NEXT:    [[X:%.*]] = call i32 @passthru_i32(i32 [[ARG:%.*]])
-; CHECK-NEXT:    ret i32 [[ARG]]
+; CHECK-NEXT:    ret i32 [[X]]
 ;
   %x = call i32 @passthru_i32(i32 %arg)
   ret i32 %x
diff --git a/llvm/test/Transforms/InstSimplify/or.ll b/llvm/test/Transforms/InstSimplify/or.ll
index 20f67769eed7f..7369cddf2fbe9 100644
--- a/llvm/test/Transforms/InstSimplify/or.ll
+++ b/llvm/test/Transforms/InstSimplify/or.ll
@@ -3,7 +3,7 @@
 
 define i32 @test1(i32 %A) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    ret i32 %A
+; CHECK-NEXT:    ret i32 [[A:%.*]]
 ;
   %B = or i32 %A, 0
   ret i32 %B
@@ -27,7 +27,7 @@ define <3 x i8> @all_ones_vec_with_undef_elt(<3 x i8> %A) {
 
 define i1 @test3(i1 %A) {
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT:    ret i1 %A
+; CHECK-NEXT:    ret i1 [[A:%.*]]
 ;
   %B = or i1 %A, false
   ret i1 %B
@@ -43,7 +43,7 @@ define i1 @test4(i1 %A) {
 
 define i1 @test5(i1 %A) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:    ret i1 %A
+; CHECK-NEXT:    ret i1 [[A:%.*]]
 ;
   %B = or i1 %A, %A
   ret i1 %B
@@ -51,7 +51,7 @@ define i1 @test5(i1 %A) {
 
 define i32 @test6(i32 %A) {
 ; CHECK-LABEL: @test6(
-; CHECK-NEXT:    ret i32 %A
+; CHECK-NEXT:    ret i32 [[A:%.*]]
 ;
   %B = or i32 %A, %A
   ret i32 %B
@@ -87,110 +87,122 @@ define i8 @test9(i8 %A, i8 %B) {
   ret i8 %E
 }
 
+; (X & C1) | C2 --> (X | C2) & (C1|C2)
 define i8 @test10(i8 %A) {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT:    ret i8 -2
 ;
   %B = or i8 %A, 1
   %C = and i8 %B, -2
-  ; (X & C1) | C2 --> (X | C2) & (C1|C2)
   %D = or i8 %C, -2
   ret i8 %D
 }
 
+; (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2)
 define i8 @test11(i8 %A) {
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:    ret i8 -1
 ;
   %B = or i8 %A, -2
   %C = xor i8 %B, 13
-  ; (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2)
+  %D = or i8 %C, 1
+  %E = xor i8 %D, 12
+  ret i8 %E
+}
+
+define i8 @test11v(<2 x i8> %A) {
+; CHECK-LABEL: @test11v(
+; CHECK-NEXT:    ret i8 -1
+;
+  %B = or <2 x i8> %A, <i8 -2, i8 0>
+  %CV = xor <2 x i8> %B, <i8 13, i8 13>
+  %C = extractelement <2 x i8> %CV, i32 0
   %D = or i8 %C, 1
   %E = xor i8 %D, 12
   ret i8 %E
 }
 
 ; Test the case where integer BitWidth <= 64 && BitWidth % 2 != 0.
+; If we have: ((V + N) & C1) | (V & C2)
+; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
+; replace with V+N.
 define i39 @test1_apint(i39 %V, i39 %M) {
 ; CHECK-LABEL: @test1_apint(
-; CHECK:         [[N:%.*]] = and i39 %M, -274877906944
-; CHECK-NEXT:    [[A:%.*]] = add i39 %V, [[N]]
+; CHECK-NEXT:    [[N:%.*]] = and i39 [[M:%.*]], -274877906944
+; CHECK-NEXT:    [[A:%.*]] = add i39 [[V:%.*]], [[N]]
 ; CHECK-NEXT:    ret i39 [[A]]
 ;
-    ;; If we have: ((V + N) & C1) | (V & C2)
-    ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
-    ;; replace with V+N.
-    %C1 = xor i39 274877906943, -1 ;; C2 = 274877906943
-    %N = and i39 %M, 274877906944
-    %A = add i39 %V, %N
-    %B = and i39 %A, %C1
-    %D = and i39 %V, 274877906943
-    %R = or i39 %B, %D
-    ret i39 %R
+  %C1 = xor i39 274877906943, -1 ;; C2 = 274877906943
+  %N = and i39 %M, 274877906944
+  %A = add i39 %V, %N
+  %B = and i39 %A, %C1
+  %D = and i39 %V, 274877906943
+  %R = or i39 %B, %D
+  ret i39 %R
 }
 
 define i7 @test2_apint(i7 %X) {
 ; CHECK-LABEL: @test2_apint(
-; CHECK:         ret i7 %X
+; CHECK-NEXT:    ret i7 [[X:%.*]]
 ;
-    %Y = or i7 %X, 0
-    ret i7 %Y
+  %Y = or i7 %X, 0
+  ret i7 %Y
 }
 
 define i17 @test3_apint(i17 %X) {
 ; CHECK-LABEL: @test3_apint(
-; CHECK:         ret i17 -1
+; CHECK-NEXT:    ret i17 -1
 ;
-    %Y = or i17 %X, -1
-    ret i17 %Y
+  %Y = or i17 %X, -1
+  ret i17 %Y
 }
 
 ; Test the case where Integer BitWidth > 64 && BitWidth <= 1024.
+; If we have: ((V + N) & C1) | (V & C2)
+; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
+; replace with V+N.
 define i399 @test4_apint(i399 %V, i399 %M) {
 ; CHECK-LABEL: @test4_apint(
-; CHECK:         [[N:%.*]] = and i399 %M, 18446742974197923840
-; CHECK-NEXT:    [[A:%.*]] = add i399 %V, [[N]]
+; CHECK-NEXT:    [[N:%.*]] = and i399 [[M:%.*]], 18446742974197923840
+; CHECK-NEXT:    [[A:%.*]] = add i399 [[V:%.*]], [[N]]
 ; CHECK-NEXT:    ret i399 [[A]]
 ;
-    ;; If we have: ((V + N) & C1) | (V & C2)
-    ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
-    ;; replace with V+N.
-    %C1 = xor i399 274877906943, -1 ;; C2 = 274877906943
-    %N = and i399 %M, 18446742974197923840
-    %A = add i399 %V, %N
-    %B = and i399 %A, %C1
-    %D = and i399 %V, 274877906943
-    %R = or i399 %D, %B
-    ret i399 %R
+  %C1 = xor i399 274877906943, -1 ;; C2 = 274877906943
+  %N = and i399 %M, 18446742974197923840
+  %A = add i399 %V, %N
+  %B = and i399 %A, %C1
+  %D = and i399 %V, 274877906943
+  %R = or i399 %D, %B
+  ret i399 %R
 }
 
 define i777 @test5_apint(i777 %X) {
 ; CHECK-LABEL: @test5_apint(
-; CHECK:         ret i777 %X
+; CHECK-NEXT:    ret i777 [[X:%.*]]
 ;
-    %Y = or i777 %X, 0
-    ret i777 %Y
+  %Y = or i777 %X, 0
+  ret i777 %Y
 }
 
 define i117 @test6_apint(i117 %X) {
 ; CHECK-LABEL: @test6_apint(
-; CHECK:         ret i117 -1
+; CHECK-NEXT:    ret i117 -1
 ;
-    %Y = or i117 %X, -1
-    ret i117 %Y
+  %Y = or i117 %X, -1
+  ret i117 %Y
 }
 
 ; Test the case where integer BitWidth <= 64 && BitWidth % 2 != 0.
 ; Vector version of test1_apint with the add commuted
+; If we have: ((V + N) & C1) | (V & C2)
+; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
+; replace with V+N.
 define <2 x i39> @test7_apint(<2 x i39> %V, <2 x i39> %M) {
 ; CHECK-LABEL: @test7_apint(
 ; CHECK-NEXT:    [[N:%.*]] = and <2 x i39> [[M:%.*]], <i39 -274877906944, i39 -274877906944>
 ; CHECK-NEXT:    [[A:%.*]] = add <2 x i39> [[N]], [[V:%.*]]
 ; CHECK-NEXT:    ret <2 x i39> [[A]]
 ;
-  ;; If we have: ((V + N) & C1) | (V & C2)
-  ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
-  ;; replace with V+N.
   %C1 = xor <2 x i39> <i39 274877906943, i39 274877906943>, <i39 -1, i39 -1> ;; C2 = 274877906943
   %N = and <2 x i39> %M, <i39 274877906944, i39 274877906944>
   %A = add <2 x i39> %N, %V
@@ -202,15 +214,15 @@ define <2 x i39> @test7_apint(<2 x i39> %V, <2 x i39> %M) {
 
 ; Test the case where Integer BitWidth > 64 && BitWidth <= 1024.
 ; Vector version of test4_apint with the add and the or commuted
+; If we have: ((V + N) & C1) | (V & C2)
+; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
+; replace with V+N.
 define <2 x i399> @test8_apint(<2 x i399> %V, <2 x i399> %M) {
 ; CHECK-LABEL: @test8_apint(
 ; CHECK-NEXT:    [[N:%.*]] = and <2 x i399> [[M:%.*]], <i399 18446742974197923840, i399 18446742974197923840>
 ; CHECK-NEXT:    [[A:%.*]] = add <2 x i399> [[N]], [[V:%.*]]
 ; CHECK-NEXT:    ret <2 x i399> [[A]]
 ;
-  ;; If we have: ((V + N) & C1) | (V & C2)
-  ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0
-  ;; replace with V+N.
   %C1 = xor <2 x i399> <i399 274877906943, i399 274877906943>, <i399 -1, i399 -1> ;; C2 = 274877906943
   %N = and <2 x i399> %M, <i399 18446742974197923840, i399 18446742974197923840>
   %A = add <2 x i399> %N, %V
diff --git a/llvm/test/Transforms/InstSimplify/vscale.ll b/llvm/test/Transforms/InstSimplify/vscale.ll
index 5a6971c9e2929..608a093a40aa2 100644
--- a/llvm/test/Transforms/InstSimplify/vscale.ll
+++ b/llvm/test/Transforms/InstSimplify/vscale.ll
@@ -94,3 +94,52 @@ define i32 @insert_extract_element_same_vec_idx_2(<vscale x 4 x i32> %a) {
   ret i32 %r
 }
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Memory Access and Addressing Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; getelementptr
+
+define <vscale x 4 x i32*> @getelementptr_constant_foldable_1() {
+; CHECK-LABEL: @getelementptr_constant_foldable_1(
+; CHECK-NEXT:    ret <vscale x 4 x i32*> zeroinitializer
+;
+  %ptr = getelementptr i32, <vscale x 4 x i32*> zeroinitializer, <vscale x 4 x i64> undef
+  ret <vscale x 4 x i32*> %ptr
+}
+
+define <vscale x 4 x <vscale x 4 x i32>*> @getelementptr_constant_foldable_2() {
+; CHECK-LABEL: @getelementptr_constant_foldable_2(
+; CHECK-NEXT:    ret <vscale x 4 x <vscale x 4 x i32>*> zeroinitializer
+;
+  %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, <vscale x 4 x i64> undef
+  ret <vscale x 4 x <vscale x 4 x i32>*> %ptr
+}
+
+; fold getelementptr P, 0 -> P.
+define <vscale x 4 x i32>* @getelementptr_constant_foldable_3() {
+; CHECK-LABEL: @getelementptr_constant_foldable_3(
+; CHECK-NEXT:    ret <vscale x 4 x i32>* null
+;
+  %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, i64 0
+  ret <vscale x 4 x i32>* %ptr
+}
+
+define <vscale x 4 x i32>* @getelementptr_not_constant_foldable(i64 %x) {
+; CHECK-LABEL: @getelementptr_not_constant_foldable(
+; CHECK-NEXT:    [[PTR:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, i64 [[X:%.*]]
+; CHECK-NEXT:    ret <vscale x 4 x i32>* [[PTR]]
+;
+  %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, i64 %x
+  ret <vscale x 4 x i32>* %ptr
+}
+
+; Check GEP's result is known to be non-null.
+define i1 @getelementptr_check_non_null(<vscale x 16 x i8>* %ptr) {
+; CHECK-LABEL: @getelementptr_check_non_null(
+; CHECK-NEXT:    ret i1 false
+;
+  %x = getelementptr inbounds <vscale x 16 x i8>, <vscale x 16 x i8>* %ptr, i32 1
+  %cmp = icmp eq <vscale x 16 x i8>* %x, null
+  ret i1 %cmp
+}
diff --git a/llvm/test/Transforms/JumpThreading/select.ll b/llvm/test/Transforms/JumpThreading/select.ll
index 08598f84c1fd1..4309a1babd736 100644
--- a/llvm/test/Transforms/JumpThreading/select.ll
+++ b/llvm/test/Transforms/JumpThreading/select.ll
@@ -441,3 +441,31 @@ sw.default:                                       ; preds = %if.end, %sw.bb9
 ; CHECK: i32 2, label [[DEST1]]
 ; CHECK: i32 4, label [[DEST2]]
 }
+
+; FIXME: This is an invalid transform. If %b is false and %x is poison,
+; then the select produces poison (the result of the program is poison).
+; But with this transform, we may be branching on poison, and that is UB.
+
+define i32 @TryToUnfoldSelectInCurrBB(i1 %b, i1 %ui, i32 %s, i1 %x) {
+; CHECK-LABEL: @TryToUnfoldSelectInCurrBB(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[B:%.*]], label [[IF_END_THREAD:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.end:
+; CHECK-NEXT:    br i1 [[X:%.*]], label [[TMP0:%.*]], label [[IF_END_THREAD]]
+; CHECK:       0:
+; CHECK-NEXT:    br label [[IF_END_THREAD]]
+; CHECK:       if.end.thread:
+; CHECK-NEXT:    [[TMP1:%.*]] = phi i32 [ [[S:%.*]], [[TMP0]] ], [ 42, [[IF_END]] ], [ 42, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
+entry:
+  br i1 %b, label %if.end, label %if.else
+
+if.else:
+  br label %if.end
+
+if.end:
+  %v = phi i1 [ %x, %if.else ], [ false, %entry ]
+  %v1 = select i1 %v, i32 %s, i32 42
+  ret i32 %v1
+}
diff --git a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
index 27998230abe4a..aa0ead18ba3cd 100644
--- a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
+++ b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -S -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -loop-unroll | FileCheck %s
 ; RUN: opt < %s -S -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -loop-unroll | FileCheck %s
 
@@ -6,6 +7,195 @@ target triple = "powerpc64le-unknown-linux-gnu"
 
 ; Function Attrs: norecurse nounwind
 define i8* @f(i8* returned %s, i32 zeroext %x, i32 signext %k) local_unnamed_addr #0 {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[K:%.*]], 0
+; CHECK-NEXT:    br i1 [[CMP10]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]]
+; CHECK:       for.body.lr.ph:
+; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[K]] to i64
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[K]], 16
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967280
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i32> undef, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i32> [[BROADCAST_SPLATINSERT]], <16 x i32> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP0:%.*]] = add nsw i64 [[N_VEC]], -16
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 4
+; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT:    [[XTRAITER1:%.*]] = and i64 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i64 [[TMP1]], 1
+; CHECK-NEXT:    br i1 [[TMP3]], label [[MIDDLE_BLOCK_UNR_LCSSA:%.*]], label [[VECTOR_PH_NEW:%.*]]
+; CHECK:       vector.ph.new:
+; CHECK-NEXT:    [[UNROLL_ITER:%.*]] = sub i64 [[TMP2]], [[XTRAITER1]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[INDEX_NEXT_1:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND12:%.*]] = phi <16 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, [[VECTOR_PH_NEW]] ], [ [[VEC_IND_NEXT13_1:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[VECTOR_PH_NEW]] ], [ [[NITER_NSUB_1:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12]]
+; CHECK-NEXT:    [[TMP5:%.*]] = and <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq <16 x i32> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i8, i8* [[S:%.*]], i64 [[INDEX]]
+; CHECK-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP8]] to <16 x i8>*
+; CHECK-NEXT:    store <16 x i8> [[TMP7]], <16 x i8>* [[TMP9]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT:%.*]] = add nuw nsw i64 [[INDEX]], 16
+; CHECK-NEXT:    [[VEC_IND_NEXT13:%.*]] = add <16 x i32> [[VEC_IND12]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[NITER_NSUB:%.*]] = sub i64 [[NITER]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND_NEXT13]]
+; CHECK-NEXT:    [[TMP11:%.*]] = and <16 x i32> [[TMP10]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq <16 x i32> [[TMP11]], zeroinitializer
+; CHECK-NEXT:    [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDEX_NEXT]]
+; CHECK-NEXT:    [[TMP15:%.*]] = bitcast i8* [[TMP14]] to <16 x i8>*
+; CHECK-NEXT:    store <16 x i8> [[TMP13]], <16 x i8>* [[TMP15]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT_1]] = add i64 [[INDEX_NEXT]], 16
+; CHECK-NEXT:    [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND_NEXT13]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[NITER_NSUB_1]] = sub i64 [[NITER_NSUB]], 1
+; CHECK-NEXT:    [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NSUB_1]], 0
+; CHECK-NEXT:    br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK:       middle.block.unr-lcssa.loopexit:
+; CHECK-NEXT:    [[INDEX_UNR_PH:%.*]] = phi i64 [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND12_UNR_PH:%.*]] = phi <16 x i32> [ [[VEC_IND_NEXT13_1]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    br label [[MIDDLE_BLOCK_UNR_LCSSA]]
+; CHECK:       middle.block.unr-lcssa:
+; CHECK-NEXT:    [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ]
+; CHECK-NEXT:    [[VEC_IND12_UNR:%.*]] = phi <16 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, [[VECTOR_PH]] ], [ [[VEC_IND12_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ]
+; CHECK-NEXT:    [[LCMP_MOD2:%.*]] = icmp ne i64 [[XTRAITER1]], 0
+; CHECK-NEXT:    br i1 [[LCMP_MOD2]], label [[VECTOR_BODY_EPIL_PREHEADER:%.*]], label [[MIDDLE_BLOCK:%.*]]
+; CHECK:       vector.body.epil.preheader:
+; CHECK-NEXT:    br label [[VECTOR_BODY_EPIL:%.*]]
+; CHECK:       vector.body.epil:
+; CHECK-NEXT:    [[INDEX_EPIL:%.*]] = phi i64 [ [[INDEX_UNR]], [[VECTOR_BODY_EPIL_PREHEADER]] ]
+; CHECK-NEXT:    [[VEC_IND12_EPIL:%.*]] = phi <16 x i32> [ [[VEC_IND12_UNR]], [[VECTOR_BODY_EPIL_PREHEADER]] ]
+; CHECK-NEXT:    [[TMP16:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12_EPIL]]
+; CHECK-NEXT:    [[TMP17:%.*]] = and <16 x i32> [[TMP16]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq <16 x i32> [[TMP17]], zeroinitializer
+; CHECK-NEXT:    [[TMP19:%.*]] = select <16 x i1> [[TMP18]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+; CHECK-NEXT:    [[TMP20:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDEX_EPIL]]
+; CHECK-NEXT:    [[TMP21:%.*]] = bitcast i8* [[TMP20]] to <16 x i8>*
+; CHECK-NEXT:    store <16 x i8> [[TMP19]], <16 x i8>* [[TMP21]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT_EPIL:%.*]] = add i64 [[INDEX_EPIL]], 16
+; CHECK-NEXT:    [[VEC_IND_NEXT13_EPIL:%.*]] = add <16 x i32> [[VEC_IND12_EPIL]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT_EPIL]], [[N_VEC]]
+; CHECK-NEXT:    br label [[MIDDLE_BLOCK_EPILOG_LCSSA:%.*]]
+; CHECK:       middle.block.epilog-lcssa:
+; CHECK-NEXT:    br label [[MIDDLE_BLOCK]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY_PREHEADER]]
+; CHECK:       for.body.preheader:
+; CHECK-NEXT:    [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    [[TMP23:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[INDVARS_IV_PH]]
+; CHECK-NEXT:    [[TMP24:%.*]] = add i64 [[WIDE_TRIP_COUNT]], -1
+; CHECK-NEXT:    [[TMP25:%.*]] = sub i64 [[TMP24]], [[INDVARS_IV_PH]]
+; CHECK-NEXT:    [[XTRAITER:%.*]] = and i64 [[TMP23]], 7
+; CHECK-NEXT:    [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
+; CHECK-NEXT:    br i1 [[LCMP_MOD]], label [[FOR_BODY_PROL_PREHEADER:%.*]], label [[FOR_BODY_PROL_LOOPEXIT:%.*]]
+; CHECK:       for.body.prol.preheader:
+; CHECK-NEXT:    br label [[FOR_BODY_PROL:%.*]]
+; CHECK:       for.body.prol:
+; CHECK-NEXT:    [[INDVARS_IV_PROL:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL:%.*]], [[FOR_BODY_PROL]] ], [ [[INDVARS_IV_PH]], [[FOR_BODY_PROL_PREHEADER]] ]
+; CHECK-NEXT:    [[PROL_ITER:%.*]] = phi i64 [ [[XTRAITER]], [[FOR_BODY_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[FOR_BODY_PROL]] ]
+; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[INDVARS_IV_PROL]] to i32
+; CHECK-NEXT:    [[SHL_PROL:%.*]] = shl i32 1, [[TMP26]]
+; CHECK-NEXT:    [[AND_PROL:%.*]] = and i32 [[SHL_PROL]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_PROL:%.*]] = icmp eq i32 [[AND_PROL]], 0
+; CHECK-NEXT:    [[CONV_PROL:%.*]] = select i1 [[TOBOOL_PROL]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_PROL:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_PROL]]
+; CHECK-NEXT:    store i8 [[CONV_PROL]], i8* [[ARRAYIDX_PROL]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_PROL]] = add nuw nsw i64 [[INDVARS_IV_PROL]], 1
+; CHECK-NEXT:    [[EXITCOND_PROL:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_PROL]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    [[PROL_ITER_SUB]] = sub i64 [[PROL_ITER]], 1
+; CHECK-NEXT:    [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_SUB]], 0
+; CHECK-NEXT:    br i1 [[PROL_ITER_CMP]], label [[FOR_BODY_PROL]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop !0
+; CHECK:       for.body.prol.loopexit.unr-lcssa:
+; CHECK-NEXT:    [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[FOR_BODY_PROL]] ]
+; CHECK-NEXT:    br label [[FOR_BODY_PROL_LOOPEXIT]]
+; CHECK:       for.body.prol.loopexit:
+; CHECK-NEXT:    [[INDVARS_IV_UNR:%.*]] = phi i64 [ [[INDVARS_IV_PH]], [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_UNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-NEXT:    [[TMP27:%.*]] = icmp ult i64 [[TMP25]], 7
+; CHECK-NEXT:    br i1 [[TMP27]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_PREHEADER_NEW:%.*]]
+; CHECK:       for.body.preheader.new:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[INDVARS_IV]] to i32
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 1, [[TMP28]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], [[X]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    [[CONV:%.*]] = select i1 [[TOBOOL]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV]]
+; CHECK-NEXT:    store i8 [[CONV]], i8* [[ARRAYIDX]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT:    [[TMP29:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
+; CHECK-NEXT:    [[SHL_1:%.*]] = shl i32 1, [[TMP29]]
+; CHECK-NEXT:    [[AND_1:%.*]] = and i32 [[SHL_1]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_1:%.*]] = icmp eq i32 [[AND_1]], 0
+; CHECK-NEXT:    [[CONV_1:%.*]] = select i1 [[TOBOOL_1]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT:    store i8 [[CONV_1]], i8* [[ARRAYIDX_1]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1
+; CHECK-NEXT:    [[TMP30:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32
+; CHECK-NEXT:    [[SHL_2:%.*]] = shl i32 1, [[TMP30]]
+; CHECK-NEXT:    [[AND_2:%.*]] = and i32 [[SHL_2]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_2:%.*]] = icmp eq i32 [[AND_2]], 0
+; CHECK-NEXT:    [[CONV_2:%.*]] = select i1 [[TOBOOL_2]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_1]]
+; CHECK-NEXT:    store i8 [[CONV_2]], i8* [[ARRAYIDX_2]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1
+; CHECK-NEXT:    [[TMP31:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32
+; CHECK-NEXT:    [[SHL_3:%.*]] = shl i32 1, [[TMP31]]
+; CHECK-NEXT:    [[AND_3:%.*]] = and i32 [[SHL_3]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_3:%.*]] = icmp eq i32 [[AND_3]], 0
+; CHECK-NEXT:    [[CONV_3:%.*]] = select i1 [[TOBOOL_3]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_2]]
+; CHECK-NEXT:    store i8 [[CONV_3]], i8* [[ARRAYIDX_3]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1
+; CHECK-NEXT:    [[TMP32:%.*]] = trunc i64 [[INDVARS_IV_NEXT_3]] to i32
+; CHECK-NEXT:    [[SHL_4:%.*]] = shl i32 1, [[TMP32]]
+; CHECK-NEXT:    [[AND_4:%.*]] = and i32 [[SHL_4]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_4:%.*]] = icmp eq i32 [[AND_4]], 0
+; CHECK-NEXT:    [[CONV_4:%.*]] = select i1 [[TOBOOL_4]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_3]]
+; CHECK-NEXT:    store i8 [[CONV_4]], i8* [[ARRAYIDX_4]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1
+; CHECK-NEXT:    [[TMP33:%.*]] = trunc i64 [[INDVARS_IV_NEXT_4]] to i32
+; CHECK-NEXT:    [[SHL_5:%.*]] = shl i32 1, [[TMP33]]
+; CHECK-NEXT:    [[AND_5:%.*]] = and i32 [[SHL_5]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_5:%.*]] = icmp eq i32 [[AND_5]], 0
+; CHECK-NEXT:    [[CONV_5:%.*]] = select i1 [[TOBOOL_5]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_4]]
+; CHECK-NEXT:    store i8 [[CONV_5]], i8* [[ARRAYIDX_5]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1
+; CHECK-NEXT:    [[TMP34:%.*]] = trunc i64 [[INDVARS_IV_NEXT_5]] to i32
+; CHECK-NEXT:    [[SHL_6:%.*]] = shl i32 1, [[TMP34]]
+; CHECK-NEXT:    [[AND_6:%.*]] = and i32 [[SHL_6]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_6:%.*]] = icmp eq i32 [[AND_6]], 0
+; CHECK-NEXT:    [[CONV_6:%.*]] = select i1 [[TOBOOL_6]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_5]]
+; CHECK-NEXT:    store i8 [[CONV_6]], i8* [[ARRAYIDX_6]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1
+; CHECK-NEXT:    [[TMP35:%.*]] = trunc i64 [[INDVARS_IV_NEXT_6]] to i32
+; CHECK-NEXT:    [[SHL_7:%.*]] = shl i32 1, [[TMP35]]
+; CHECK-NEXT:    [[AND_7:%.*]] = and i32 [[SHL_7]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_7:%.*]] = icmp eq i32 [[AND_7]], 0
+; CHECK-NEXT:    [[CONV_7:%.*]] = select i1 [[TOBOOL_7]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_6]]
+; CHECK-NEXT:    store i8 [[CONV_7]], i8* [[ARRAYIDX_7]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV_NEXT_6]], 1
+; CHECK-NEXT:    [[EXITCOND_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    br i1 [[EXITCOND_7]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY]]
+; CHECK:       for.end.loopexit.unr-lcssa:
+; CHECK-NEXT:    br label [[FOR_END_LOOPEXIT]]
+; CHECK:       for.end.loopexit:
+; CHECK-NEXT:    br label [[FOR_END]]
+; CHECK:       for.end:
+; CHECK-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[K]] to i64
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[IDXPROM1]]
+; CHECK-NEXT:    store i8 0, i8* [[ARRAYIDX2]], align 1
+; CHECK-NEXT:    ret i8* [[S]]
+;
 entry:
   %cmp10 = icmp sgt i32 %k, 0
   br i1 %cmp10, label %for.body.lr.ph, label %for.end
@@ -64,11 +254,3 @@ for.end:                                          ; preds = %for.body, %middle.b
   ret i8* %s
 }
 
-
-; CHECK-LABEL: vector.body
-; CHECK:      shl
-; CHECK-NEXT: and
-; CHECK: shl
-; CHECK-NEXT: and
-; CHECK: label %vector.body
-
diff --git a/llvm/test/Transforms/SCCP/binaryops-range-special-cases.ll b/llvm/test/Transforms/SCCP/binaryops-range-special-cases.ll
new file mode 100644
index 0000000000000..a354ae0d4d5d1
--- /dev/null
+++ b/llvm/test/Transforms/SCCP/binaryops-range-special-cases.ll
@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -ipsccp -S | FileCheck %s
+
+declare void @use(i1)
+define void @sdiv1_cmp_constants(i32 %x) {
+; CHECK-LABEL: @sdiv1_cmp_constants(
+; CHECK-NEXT:    [[D:%.*]] = sdiv i32 1, [[X:%.*]]
+; CHECK-NEXT:    [[C_0:%.*]] = icmp slt i32 0, [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_0]])
+; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i32 1, [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_1]])
+; CHECK-NEXT:    [[C_2:%.*]] = icmp slt i32 2, [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_2]])
+; CHECK-NEXT:    [[C_3:%.*]] = icmp eq i32 1, [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_3]])
+; CHECK-NEXT:    [[C_4:%.*]] = icmp eq i32 0, [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_4]])
+; CHECK-NEXT:    [[C_5:%.*]] = icmp eq i32 2, [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_5]])
+; CHECK-NEXT:    ret void
+;
+  %d = sdiv i32 1, %x
+  %c.0 = icmp slt i32 0, %d
+  call void @use(i1 %c.0)
+  %c.1 = icmp slt i32 1, %d
+  call void @use(i1 %c.1)
+  %c.2 = icmp slt i32 2, %d
+  call void @use(i1 %c.2)
+
+  %c.3 = icmp eq i32 1, %d
+  call void @use(i1 %c.3)
+  %c.4 = icmp eq i32 0, %d
+  call void @use(i1 %c.4)
+  %c.5 = icmp eq i32 2, %d
+  call void @use(i1 %c.5)
+
+  ret void
+}
+
+define void @sdiv1_cmp_range_1(i32 %x, i1 %c) {
+; CHECK-LABEL: @sdiv1_cmp_range_1(
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    br label [[BB3:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 1, [[BB1]] ], [ 2, [[BB2]] ]
+; CHECK-NEXT:    [[D:%.*]] = sdiv i32 1, [[X:%.*]]
+; CHECK-NEXT:    [[C_0:%.*]] = icmp slt i32 [[P]], [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_0]])
+; CHECK-NEXT:    [[C_1:%.*]] = icmp eq i32 [[P]], [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_1]])
+; CHECK-NEXT:    ret void
+;
+  br i1 %c, label %bb1, label %bb2
+bb1:
+  br label %bb3
+bb2:
+  br label %bb3
+
+bb3:
+  %p = phi i32 [1, %bb1], [2, %bb2]
+  %d = sdiv i32 1, %x
+  %c.0 = icmp slt i32 %p, %d
+  call void @use(i1 %c.0)
+  %c.1 = icmp eq i32 %p, %d
+  call void @use(i1 %c.1)
+  ret void
+}
+
+
+define void @sdiv1_cmp_range_2(i32 %x, i1 %c) {
+; CHECK-LABEL: @sdiv1_cmp_range_2(
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    br label [[BB3:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 3, [[BB1]] ], [ 2, [[BB2]] ]
+; CHECK-NEXT:    [[D:%.*]] = sdiv i32 1, [[X:%.*]]
+; CHECK-NEXT:    [[C_0:%.*]] = icmp slt i32 [[P]], [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_0]])
+; CHECK-NEXT:    [[C_1:%.*]] = icmp eq i32 [[P]], [[D]]
+; CHECK-NEXT:    call void @use(i1 [[C_1]])
+; CHECK-NEXT:    ret void
+;
+  br i1 %c, label %bb1, label %bb2
+bb1:
+  br label %bb3
+bb2:
+  br label %bb3
+
+bb3:
+  %p = phi i32 [3, %bb1], [2, %bb2]
+  %d = sdiv i32 1, %x
+  %c.0 = icmp slt i32 %p, %d
+  call void @use(i1 %c.0)
+  %c.1 = icmp eq i32 %p, %d
+  call void @use(i1 %c.1)
+  ret void
+}
diff --git a/llvm/test/Transforms/SCCP/ip-ranges-select.ll b/llvm/test/Transforms/SCCP/ip-ranges-select.ll
new file mode 100644
index 0000000000000..f1f2b032ac46f
--- /dev/null
+++ b/llvm/test/Transforms/SCCP/ip-ranges-select.ll
@@ -0,0 +1,132 @@
+; RUN: opt -ipsccp -S %s -o -| FileCheck %s
+
+define void @caller.1(i8* %arg) {
+; CHECK-LABEL: define void @caller.1(i8* %arg) {
+; CHECK-NEXT:    %r.1 = tail call i32 @callee.1(i32 4)
+; CHECK-NEXT:    %r.2 = tail call i32 @callee.1(i32 2)
+; CHECK-NEXT:    call void @use(i32 20)
+; CHECK-NEXT:    ret void
+;
+  %r.1 = tail call i32 @callee.1(i32 4)
+  %r.2 = tail call i32 @callee.1(i32 2)
+  %r.3 = add i32 %r.1, %r.2
+  call void @use(i32 %r.3)
+  ret void
+}
+
+define internal i32 @callee.1(i32 %arg) {
+; CHECK-LABEL: define internal i32 @callee.1(i32 %arg) {
+; CHECK-NEXT:    %sel = select i1 false, i32 16, i32 %arg
+; CHECK-NEXT:    br label %bb10
+;
+; CHECK-LABEL: bb10:
+; CHECK-NEXT:    ret i32 undef
+;
+  %c.1 = icmp slt i32 %arg, 0
+  %sel = select i1 %c.1, i32 16, i32 %arg
+  %c.2 = icmp eq i32 %sel, 0
+  br i1 %c.2, label %bb12, label %bb10
+
+bb10:                                             ; preds = %bb8
+  ret i32 10
+
+bb12:                                             ; preds = %bb8, %bb3, %bb
+  ret i32 12
+}
+
+declare void @use(i32)
+
+define internal i1 @f1(i32 %x, i32 %y, i1 %cmp) {
+; CHECK-LABEL: define internal i1 @f1(i32 %x, i32 %y, i1 %cmp) {
+; CHECK-NEXT:    %sel.1 = select i1 %cmp, i32 %x, i32 %y
+; CHECK-NEXT:    %c.2 = icmp sgt i32 %sel.1, 100
+; CHECK-NEXT:    %c.3 = icmp eq i32 %sel.1, 50
+; CHECK-NEXT:    %res.1 = add i1 false, %c.2
+; CHECK-NEXT:    %res.2 = add i1 %res.1, %c.3
+; CHECK-NEXT:    %res.3 = add i1 %res.2, false
+; CHECK-NEXT:    ret i1 %res.3
+;
+  %sel.1 = select i1 %cmp, i32 %x, i32 %y
+  %c.1 = icmp sgt i32 %sel.1, 300
+  %c.2 = icmp sgt i32 %sel.1, 100
+  %c.3 = icmp eq i32 %sel.1, 50
+  %c.4 = icmp slt i32 %sel.1, 9
+  %res.1 = add i1 %c.1, %c.2
+  %res.2 = add i1 %res.1, %c.3
+  %res.3 = add i1 %res.2, %c.4
+  ret i1 %res.3
+}
+
+define i1 @caller1(i1 %cmp) {
+; CHECK-LABEL:  define i1 @caller1(i1 %cmp) {
+; CHECK-NEXT:    %call.1 = tail call i1 @f1(i32 10, i32 100, i1 %cmp)
+; CHECK-NEXT:    %call.2 = tail call i1 @f1(i32 20, i32 200, i1 %cmp)
+; CHECK-NEXT:    %res = and i1 %call.1, %call.2
+; CHECK-NEXT:    ret i1 %res
+;
+  %call.1 = tail call i1 @f1(i32 10, i32 100, i1 %cmp)
+  %call.2 = tail call i1 @f1(i32 20, i32 200, i1 %cmp)
+  %res = and i1 %call.1, %call.2
+  ret i1 %res
+}
+
+
+define i1 @f2(i32 %x, i32 %y, i1 %cmp) {
+; CHECK-LABEL: define i1 @f2(i32 %x, i32 %y, i1 %cmp) {
+; CHECK-NEXT:    %sel.1 = select i1 %cmp, i32 %x, i32 %y
+; CHECK-NEXT:    %c.1 = icmp sgt i32 %sel.1, 300
+; CHECK-NEXT:    %c.2 = icmp sgt i32 %sel.1, 100
+; CHECK-NEXT:    %c.3 = icmp eq i32 %sel.1, 50
+; CHECK-NEXT:    %c.4 = icmp slt i32 %sel.1, 9
+; CHECK-NEXT:    %res.1 = add i1 %c.1, %c.2
+; CHECK-NEXT:    %res.2 = add i1 %res.1, %c.3
+; CHECK-NEXT:    %res.3 = add i1 %res.2, %c.4
+; CHECK-NEXT:    ret i1 %res.3
+;
+  %sel.1 = select i1 %cmp, i32 %x, i32 %y
+  %c.1 = icmp sgt i32 %sel.1, 300
+  %c.2 = icmp sgt i32 %sel.1, 100
+  %c.3 = icmp eq i32 %sel.1, 50
+  %c.4 = icmp slt i32 %sel.1, 9
+  %res.1 = add i1 %c.1, %c.2
+  %res.2 = add i1 %res.1, %c.3
+  %res.3 = add i1 %res.2, %c.4
+  ret i1 %res.3
+}
+
+define i1 @caller2(i32 %y, i1 %cmp) {
+; CHECK-LABEL:  define i1 @caller2(i32 %y, i1 %cmp) {
+; CHECK-NEXT:    %call.1 = tail call i1 @f2(i32 10, i32 %y, i1 %cmp)
+; CHECK-NEXT:    %call.2 = tail call i1 @f2(i32 20, i32 %y, i1 %cmp)
+; CHECK-NEXT:    %res = and i1 %call.1, %call.2
+; CHECK-NEXT:    ret i1 %res
+;
+  %call.1 = tail call i1 @f2(i32 10, i32 %y, i1 %cmp)
+  %call.2 = tail call i1 @f2(i32 20, i32 %y, i1 %cmp)
+  %res = and i1 %call.1, %call.2
+  ret i1 %res
+}
+
+@GV = external global i32
+
+define i32 @f3_constantexpr_cond(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @f3_constantexpr_cond(i32 %x, i32 %y)
+; CHECK-NEXT:   %sel.1 = select i1 icmp eq (i32* bitcast (i32 (i32, i32)* @f3_constantexpr_cond to i32*), i32* @GV), i32 %x, i32 %y
+; CHECK-NEXT:   ret i32 %sel.1
+;
+  %sel.1 = select i1 icmp eq (i32* bitcast (i32 (i32, i32)* @f3_constantexpr_cond to i32*), i32* @GV), i32 %x, i32 %y
+  ret i32 %sel.1
+}
+
+define i32 @caller3(i32 %y) {
+; CHECK-LABEL:  define i32 @caller3(i32 %y) {
+; CHECK-NEXT:    %call.1 = tail call i32 @f3_constantexpr_cond(i32 10, i32 %y)
+; CHECK-NEXT:    %call.2 = tail call i32 @f3_constantexpr_cond(i32 20, i32 %y)
+; CHECK-NEXT:    %res = and i32 %call.1, %call.2
+; CHECK-NEXT:    ret i32 %res
+;
+  %call.1 = tail call i32 @f3_constantexpr_cond(i32 10, i32 %y)
+  %call.2 = tail call i32 @f3_constantexpr_cond(i32 20, i32 %y)
+  %res = and i32 %call.1, %call.2
+  ret i32 %res
+}
diff --git a/llvm/test/Transforms/SCCP/ipsccp-range-crashes.ll b/llvm/test/Transforms/SCCP/ipsccp-range-crashes.ll
new file mode 100644
index 0000000000000..117eed78064ee
--- /dev/null
+++ b/llvm/test/Transforms/SCCP/ipsccp-range-crashes.ll
@@ -0,0 +1,195 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -ipsccp -S %s | FileCheck %s
+
+; A few test cases exposing crashes with the initial range implementation.
+
+@global.2 = external dso_local unnamed_addr constant [25 x i8], align 1
+@global = internal local_unnamed_addr global i32 0, align 4
+@global.3 = internal local_unnamed_addr global i32 0, align 4
+
+define void @main(i8** %arg) {
+; CHECK-LABEL: @main(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds i8*, i8** [[ARG:%.*]], i64 undef
+; CHECK-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[TMP]], align 8
+; CHECK-NEXT:    [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
+; CHECK-NEXT:    [[TMP3:%.*]] = sext i8 [[TMP2]] to i32
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 45
+; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i32 2, i32 4
+; CHECK-NEXT:    ret void
+;
+bb:
+  %tmp = getelementptr inbounds i8*, i8** %arg, i64 undef
+  %tmp1 = load i8*, i8** %tmp, align 8
+  %tmp2 = load i8, i8* %tmp1, align 1
+  %tmp3 = sext i8 %tmp2 to i32
+  %tmp4 = icmp ne i32 %tmp3, 45
+  %tmp5 = select i1 %tmp4, i32 2, i32 4
+  ret void
+}
+
+define void @ham() local_unnamed_addr {
+; CHECK-LABEL: @ham(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    br label [[BB1:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[TMP:%.*]] = icmp slt i32 undef, 40
+; CHECK-NEXT:    br i1 [[TMP]], label [[BB2:%.*]], label [[BB4:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    br label [[BB7:%.*]]
+; CHECK:       bb3:
+; CHECK-NEXT:    br label [[BB4]]
+; CHECK:       bb4:
+; CHECK-NEXT:    [[TMP5:%.*]] = phi i64 [ 0, [[BB1]] ], [ 15, [[BB3:%.*]] ]
+; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[TMP5]], add (i64 xor (i64 ptrtoint ([25 x i8]* @global.2 to i64), i64 -1), i64 1)
+; CHECK-NEXT:    unreachable
+; CHECK:       bb7:
+; CHECK-NEXT:    br label [[BB3]]
+;
+bb:
+  br label %bb1
+
+bb1:                                              ; preds = %bb
+  %tmp = icmp slt i32 undef, 40
+  br i1 %tmp, label %bb2, label %bb4
+
+bb2:                                              ; preds = %bb1
+  br label %bb7
+
+bb3:                                              ; preds = %bb7
+  br label %bb4
+
+bb4:                                              ; preds = %bb3, %bb1
+  %tmp5 = phi i64 [ 0, %bb1 ], [ %tmp10, %bb3 ]
+  %tmp6 = add i64 %tmp5, add (i64 xor (i64 ptrtoint ([25 x i8]* @global.2 to i64), i64 -1), i64 1)
+  unreachable
+
+bb7:                                              ; preds = %bb2
+  %tmp8 = add i64 0, 15
+  %tmp9 = add i64 %tmp8, 0
+  %tmp10 = add i64 %tmp9, 0
+  br label %bb3
+}
+
+declare i32 @barney.4()
+
+define void @wobble() {
+; CHECK-LABEL: @wobble(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = load i32, i32* @global, align 4
+; CHECK-NEXT:    store i32 [[TMP]], i32* @global.3, align 4
+; CHECK-NEXT:    ret void
+;
+bb:
+  %tmp = load i32, i32* @global, align 4
+  store i32 %tmp, i32* @global.3, align 4
+  ret void
+}
+
+define i32 @wobble.5(i32 %arg) {
+bb:
+  %tmp = load i32, i32* @global.3, align 4
+  %tmp1 = sdiv i32 0, %tmp
+  ret i32 %tmp1
+}
+
+define void @eggs() {
+; CHECK-LABEL: @eggs(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    br label [[BB1:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[TMP:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ [[TMP2:%.*]], [[BB1]] ]
+; CHECK-NEXT:    [[TMP2]] = add nsw i32 [[TMP]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @barney.4()
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 1
+; CHECK-NEXT:    br i1 [[TMP4]], label [[BB1]], label [[BB5:%.*]]
+; CHECK:       bb5:
+; CHECK-NEXT:    store i32 [[TMP2]], i32* @global, align 4
+; CHECK-NEXT:    ret void
+;
+bb:
+  br label %bb1
+
+bb1:                                              ; preds = %bb1, %bb
+  %tmp = phi i32 [ 0, %bb ], [ %tmp2, %bb1 ]
+  %tmp2 = add nsw i32 %tmp, 1
+  %tmp3 = call i32 @barney.4()
+  %tmp4 = icmp eq i32 %tmp3, 1
+  br i1 %tmp4, label %bb1, label %bb5
+
+bb5:                                              ; preds = %bb1
+  store i32 %tmp2, i32* @global, align 4
+  ret void
+}
+
+declare i32* @bar(i32) local_unnamed_addr #3
+
+; Function Attrs: nounwind ssp uwtable
+define { i8, i32* } @struct_crash(i32 %BitWidth) local_unnamed_addr #0 align 2 {
+; CHECK-LABEL: @struct_crash(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[BITWIDTH:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 1, label [[CLEANUP:%.*]]
+; CHECK-NEXT:    i32 8, label [[SW_BB1_I:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       sw.bb1.i:
+; CHECK-NEXT:    br label [[CLEANUP]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[CALL_I:%.*]] = tail call i32* @bar(i32 [[BITWIDTH]])
+; CHECK-NEXT:    br label [[CLEANUP]]
+; CHECK:       cleanup:
+; CHECK-NEXT:    [[V1:%.*]] = phi i32* [ [[CALL_I]], [[IF_END]] ], [ null, [[SW_BB1_I]] ], [ null, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[V2:%.*]] = phi i8 [ 0, [[IF_END]] ], [ 3, [[SW_BB1_I]] ], [ 2, [[ENTRY]] ]
+; CHECK-NEXT:    [[DOTFCA_0_INSERT:%.*]] = insertvalue { i8, i32* } undef, i8 [[V2]], 0
+; CHECK-NEXT:    [[DOTFCA_1_INSERT:%.*]] = insertvalue { i8, i32* } [[DOTFCA_0_INSERT]], i32* [[V1]], 1
+; CHECK-NEXT:    ret { i8, i32* } [[DOTFCA_1_INSERT]]
+;
+entry:
+  switch i32 %BitWidth, label %if.end [
+  i32 1, label %cleanup
+  i32 8, label %sw.bb1.i
+  ]
+
+sw.bb1.i:                                         ; preds = %entry
+  br label %cleanup
+
+if.end:                                           ; preds = %entry
+  %call.i = tail call i32* @bar(i32 %BitWidth)
+  br label %cleanup
+
+cleanup:                                          ; preds = %entry, %sw.bb1.i, %sw.bb2.i, %sw.bb3.i, %sw.bb4.i, %sw.bb5.i, %if.end
+  %v1 = phi i32* [ %call.i, %if.end ], [ null, %sw.bb1.i ], [ null, %entry ]
+  %v2 = phi i8 [ 0, %if.end ], [ 3, %sw.bb1.i ], [ 2, %entry ]
+  %.fca.0.insert = insertvalue { i8, i32* } undef, i8 %v2, 0
+  %.fca.1.insert = insertvalue { i8, i32* } %.fca.0.insert, i32* %v1, 1
+  ret { i8, i32* } %.fca.1.insert
+}
+
+define i64 @crash_ctpop(i1 %cond, i32* %addr) {
+; CHECK-LABEL: @crash_ctpop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    ret i64 0
+; CHECK:       if.else:
+; CHECK-NEXT:    [[LV:%.*]] = load i32, i32* [[ADDR:%.*]], align 8
+; CHECK-NEXT:    [[ANDV:%.*]] = and i32 [[LV]], 16777215
+; CHECK-NEXT:    [[TRUNCV:%.*]] = zext i32 [[ANDV]] to i64
+; CHECK-NEXT:    [[RES:%.*]] = tail call i64 @llvm.ctpop.i64(i64 [[TRUNCV]])
+; CHECK-NEXT:    ret i64 [[RES]]
+;
+entry:
+  br i1 %cond, label %if.then, label %if.else
+
+if.then:                                        ; preds = %entry
+  ret i64 0
+
+if.else:                                        ; preds = %entry
+  %lv = load i32, i32* %addr, align 8
+  %andv = and i32 %lv, 16777215
+  %truncv = zext i32 %andv to i64
+  %res = tail call i64 @llvm.ctpop.i64(i64 %truncv)
+  ret i64 %res
+}
+
+declare i64 @llvm.ctpop.i64(i64)
diff --git a/llvm/test/Transforms/SCCP/range-and.ll b/llvm/test/Transforms/SCCP/range-and.ll
index 1ca089f4aa8c9..e948274dd8f14 100644
--- a/llvm/test/Transforms/SCCP/range-and.ll
+++ b/llvm/test/Transforms/SCCP/range-and.ll
@@ -1,7 +1,42 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --verbose
 ; RUN: opt -S -sccp %s | FileCheck %s
 
-; Test case for PR44949.
+declare void @use(i1)
+
+define void @and_range_limit(i64 %a) {
+; CHECK-LABEL: @and_range_limit(
+; CHECK-NEXT:    [[R:%.*]] = and i64 [[A:%.*]], 255
+; CHECK-NEXT:    [[C_0:%.*]] = icmp slt i64 [[R]], 15
+; CHECK-NEXT:    call void @use(i1 [[C_0]])
+; CHECK-NEXT:    [[C_1:%.*]] = icmp slt i64 [[R]], 256
+; CHECK-NEXT:    call void @use(i1 [[C_1]])
+; CHECK-NEXT:    [[C_2:%.*]] = icmp eq i64 [[R]], 100
+; CHECK-NEXT:    call void @use(i1 [[C_2]])
+; CHECK-NEXT:    [[C_3:%.*]] = icmp eq i64 [[R]], 300
+; CHECK-NEXT:    call void @use(i1 [[C_3]])
+; CHECK-NEXT:    [[C_4:%.*]] = icmp ne i64 [[R]], 100
+; CHECK-NEXT:    call void @use(i1 [[C_4]])
+; CHECK-NEXT:    [[C_5:%.*]] = icmp ne i64 [[R]], 300
+; CHECK-NEXT:    call void @use(i1 [[C_5]])
+; CHECK-NEXT:    ret void
+;
+  %r = and i64 %a, 255
+  %c.0 = icmp slt i64 %r, 15
+  call void @use(i1 %c.0)
+  %c.1 = icmp slt i64 %r, 256
+  call void @use(i1 %c.1)
+  %c.2 = icmp eq i64 %r, 100
+  call void @use(i1 %c.2)
+  %c.3 = icmp eq i64 %r, 300
+  call void @use(i1 %c.3)
+  %c.4 = icmp ne i64 %r, 100
+  call void @use(i1 %c.4)
+  %c.5 = icmp ne i64 %r, 300
+  call void @use(i1 %c.5)
+  ret void
+}
+
+; Below are test cases for PR44949.
 
 ; We can remove `%res = and i64 %p, 255`, because %r = 0 and we can eliminate
 ; %p as well.
diff --git a/llvm/test/Transforms/SCCP/select.ll b/llvm/test/Transforms/SCCP/select.ll
index b2f1dd2d0f231..9cd700760ec76 100644
--- a/llvm/test/Transforms/SCCP/select.ll
+++ b/llvm/test/Transforms/SCCP/select.ll
@@ -1,12 +1,40 @@
-; RUN: opt < %s -sccp -S | not grep select
+; RUN: opt < %s -sccp -S | FileCheck %s
 
 define i32 @test1(i1 %C) {
+; CHECK-LABEL: define i32 @test1(
+; CHECK-NEXT:   ret i32 0
+;
 	%X = select i1 %C, i32 0, i32 0		; <i32> [#uses=1]
 	ret i32 %X
 }
 
 define i32 @test2(i1 %C) {
+; CHECK-LABEL: define i32 @test2(
+; CHECK-NEXT:   ret i32 0
+;
 	%X = select i1 %C, i32 0, i32 undef		; <i32> [#uses=1]
 	ret i32 %X
 }
 
+define i1 @f2(i32 %x, i1 %cmp) {
+; CHECK-LABEL: define i1 @f2(i32 %x, i1 %cmp) {
+; CHECK-NEXT:    %sel.1 = select i1 %cmp, i32 %x, i32 10
+; CHECK-NEXT:    %c.1 = icmp sgt i32 %sel.1, 300
+; CHECK-NEXT:    %c.2 = icmp sgt i32 %sel.1, 100
+; CHECK-NEXT:    %c.3 = icmp eq i32 %sel.1, 50
+; CHECK-NEXT:    %c.4 = icmp slt i32 %sel.1, 9
+; CHECK-NEXT:    %res.1 = add i1 %c.1, %c.2
+; CHECK-NEXT:    %res.2 = add i1 %res.1, %c.3
+; CHECK-NEXT:    %res.3 = add i1 %res.2, %c.4
+; CHECK-NEXT:    ret i1 %res.3
+;
+  %sel.1 = select i1 %cmp, i32 %x, i32 10
+  %c.1 = icmp sgt i32 %sel.1, 300
+  %c.2 = icmp sgt i32 %sel.1, 100
+  %c.3 = icmp eq i32 %sel.1, 50
+  %c.4 = icmp slt i32 %sel.1, 9
+  %res.1 = add i1 %c.1, %c.2
+  %res.2 = add i1 %res.1, %c.3
+  %res.3 = add i1 %res.2, %c.4
+  ret i1 %res.3
+}
diff --git a/llvm/test/Transforms/SimplifyCFG/PowerPC/prefer-fma.ll b/llvm/test/Transforms/SimplifyCFG/PowerPC/prefer-fma.ll
new file mode 100644
index 0000000000000..e72413e8b308b
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/PowerPC/prefer-fma.ll
@@ -0,0 +1,102 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=powerpc64le-unknown-linux-gnu -simplifycfg -enable-unsafe-fp-math -S | \
+; RUN: FileCheck %s
+
+; This case is copied from test/Transforms/SimplifyCFG/AArch64/
+; Function Attrs: nounwind
+define double @_Z3fooRdS_S_S_(double* dereferenceable(8) %x, double* dereferenceable(8) %y, double* dereferenceable(8) %a) {
+; CHECK-LABEL: @_Z3fooRdS_S_S_(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[Y:%.*]], align 8
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq double [[TMP0]], 0.000000e+00
+; CHECK-NEXT:    [[TMP1:%.*]] = load double, double* [[X:%.*]], align 8
+; CHECK-NEXT:    [[TMP2:%.*]] = load double, double* [[A:%.*]], align 8
+; CHECK-NEXT:    [[TMP3:%.*]] = fmul fast double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[MUL:%.*]] = fadd fast double 1.000000e+00, [[TMP3]]
+; CHECK-NEXT:    store double [[MUL]], double* [[Y]], align 8
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[SUB1:%.*]] = fsub fast double [[TMP3]], [[TMP0]]
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr double, double* [[Y]], i32 1
+; CHECK-NEXT:    store double [[SUB1]], double* [[GEP1]], align 8
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[TMP4:%.*]] = load double, double* [[Y]], align 8
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp oeq double [[TMP4]], 2.000000e+00
+; CHECK-NEXT:    [[TMP5:%.*]] = load double, double* [[X]], align 8
+; CHECK-NEXT:    br i1 [[CMP2]], label [[IF_THEN2:%.*]], label [[IF_ELSE2:%.*]]
+; CHECK:       if.then2:
+; CHECK-NEXT:    [[TMP6:%.*]] = load double, double* [[A]], align 8
+; CHECK-NEXT:    [[TMP7:%.*]] = fmul fast double [[TMP5]], 3.000000e+00
+; CHECK-NEXT:    [[MUL2:%.*]] = fsub fast double [[TMP6]], [[TMP7]]
+; CHECK-NEXT:    store double [[MUL2]], double* [[Y]], align 8
+; CHECK-NEXT:    br label [[IF_END2:%.*]]
+; CHECK:       if.else2:
+; CHECK-NEXT:    [[MUL3:%.*]] = fmul fast double [[TMP5]], 3.000000e+00
+; CHECK-NEXT:    [[NEG:%.*]] = fsub fast double 0.000000e+00, [[MUL3]]
+; CHECK-NEXT:    [[SUB2:%.*]] = fsub fast double [[NEG]], 3.000000e+00
+; CHECK-NEXT:    store double [[SUB2]], double* [[Y]], align 8
+; CHECK-NEXT:    br label [[IF_END2]]
+; CHECK:       if.end2:
+; CHECK-NEXT:    [[TMP8:%.*]] = load double, double* [[X]], align 8
+; CHECK-NEXT:    [[TMP9:%.*]] = load double, double* [[Y]], align 8
+; CHECK-NEXT:    [[ADD:%.*]] = fadd fast double [[TMP8]], [[TMP9]]
+; CHECK-NEXT:    [[TMP10:%.*]] = load double, double* [[A]], align 8
+; CHECK-NEXT:    [[ADD2:%.*]] = fadd fast double [[ADD]], [[TMP10]]
+; CHECK-NEXT:    ret double [[ADD2]]
+;
+entry:
+  %0 = load double, double* %y, align 8
+  %cmp = fcmp oeq double %0, 0.000000e+00
+  %1 = load double, double* %x, align 8
+  br i1 %cmp, label %if.then, label %if.else
+
+; fadd (const, (fmul x, y))
+if.then:                                          ; preds = %entry
+  %2 = load double, double* %a, align 8
+  %3 = fmul fast double %1, %2
+  %mul = fadd fast double 1.000000e+00, %3
+  store double %mul, double* %y, align 8
+  br label %if.end
+
+; fsub ((fmul x, y), z)
+if.else:                                          ; preds = %entry
+  %4 = load double, double* %a, align 8
+  %mul1 = fmul fast double %1, %4
+  %sub1 = fsub fast double %mul1, %0
+  %gep1 = getelementptr double, double* %y, i32 1
+  store double %sub1, double* %gep1, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %5 = load double, double* %y, align 8
+  %cmp2 = fcmp oeq double %5, 2.000000e+00
+  %6 = load double, double* %x, align 8
+  br i1 %cmp2, label %if.then2, label %if.else2
+
+; fsub (x, (fmul y, z))
+if.then2:                                         ; preds = %entry
+  %7 = load double, double* %a, align 8
+  %8 = fmul fast double %6, 3.0000000e+00
+  %mul2 = fsub fast double %7, %8
+  store double %mul2, double* %y, align 8
+  br label %if.end2
+
+; fsub (fneg((fmul x, y)), const)
+if.else2:                                         ; preds = %entry
+  %mul3 = fmul fast double %6, 3.0000000e+00
+  %neg = fsub fast double 0.0000000e+00, %mul3
+  %sub2 = fsub fast double %neg, 3.0000000e+00
+  store double %sub2, double* %y, align 8
+  br label %if.end2
+
+if.end2:                                           ; preds = %if.else, %if.then
+  %9 = load double, double* %x, align 8
+  %10 = load double, double* %y, align 8
+  %add = fadd fast double %9, %10
+  %11 = load double, double* %a, align 8
+  %add2 = fadd fast double %add, %11
+  ret double %add2
+}
diff --git a/llvm/test/Verifier/element-wise-atomic-memory-intrinsics.ll b/llvm/test/Verifier/element-wise-atomic-memory-intrinsics.ll
index f22f8eecbcc04..3912cef37fd4f 100644
--- a/llvm/test/Verifier/element-wise-atomic-memory-intrinsics.ll
+++ b/llvm/test/Verifier/element-wise-atomic-memory-intrinsics.ll
@@ -9,7 +9,6 @@ define void @test_memcpy(i8* %P, i8* %Q, i32 %A, i32 %E) {
   ; CHECK: element size of the element-wise atomic memory intrinsic must be a power of 2
   call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1, i32 3)
 
-  ; CHECK: constant length must be a multiple of the element size in the element-wise atomic memory intrinsic
   call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 7, i32 4)
 
   ; CHECK: incorrect alignment of the destination argument
@@ -36,7 +35,6 @@ define void @test_memmove(i8* %P, i8* %Q, i32 %A, i32 %E) {
   ; CHECK: element size of the element-wise atomic memory intrinsic must be a power of 2
   call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1, i32 3)
 
-  ; CHECK: constant length must be a multiple of the element size in the element-wise atomic memory intrinsic
   call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 7, i32 4)
 
   ; CHECK: incorrect alignment of the destination argument
@@ -63,7 +61,6 @@ define void @test_memset(i8* %P, i8 %V, i32 %A, i32 %E) {
   ; CHECK: element size of the element-wise atomic memory intrinsic must be a power of 2
   call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 1, i32 3)
 
-  ; CHECK: constant length must be a multiple of the element size in the element-wise atomic memory intrinsic
   call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 7, i32 4)
 
   ; CHECK: incorrect alignment of the destination argument
diff --git a/llvm/test/tools/dsymutil/Inputs/op-convert.ll b/llvm/test/tools/dsymutil/Inputs/op-convert.ll
index 10dd3febfeb18..a53599ff95e52 100644
--- a/llvm/test/tools/dsymutil/Inputs/op-convert.ll
+++ b/llvm/test/tools/dsymutil/Inputs/op-convert.ll
@@ -9,6 +9,7 @@ entry:
   call void @llvm.dbg.value(metadata i8 42, metadata !17, metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)), !dbg !12
   call void @llvm.dbg.value(metadata i8 %x, metadata !11, metadata !DIExpression()), !dbg !12
   call void @llvm.dbg.value(metadata i8 %x, metadata !13, metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)), !dbg !15
+  call void @llvm.dbg.value(metadata i8 51, metadata !18, metadata !DIExpression(DW_OP_LLVM_convert_generic, DW_OP_stack_value)), !dbg !15
   ret i8 %x, !dbg !16
 }
 
@@ -43,3 +44,4 @@ attributes #1 = { nounwind readnone speculatable }
 !15 = !DILocation(line: 3, column: 14, scope: !7)
 !16 = !DILocation(line: 4, column: 3, scope: !7)
 !17 = !DILocalVariable(name: "c", scope: !7, file: !1, line: 3, type: !14)
+!18 = !DILocalVariable(name: "d", scope: !7, file: !1, line: 3, type: !14)
diff --git a/llvm/test/tools/dsymutil/Inputs/op-convert.macho.x86_64 b/llvm/test/tools/dsymutil/Inputs/op-convert.macho.x86_64
index c4d85a312359b..e0866fb1e001b 100644
Binary files a/llvm/test/tools/dsymutil/Inputs/op-convert.macho.x86_64 and b/llvm/test/tools/dsymutil/Inputs/op-convert.macho.x86_64 differ
diff --git a/llvm/test/tools/dsymutil/X86/op-convert.test b/llvm/test/tools/dsymutil/X86/op-convert.test
index 638b2249619c5..a03869865599d 100644
--- a/llvm/test/tools/dsymutil/X86/op-convert.test
+++ b/llvm/test/tools/dsymutil/X86/op-convert.test
@@ -26,6 +26,10 @@ CHECK-NEXT:     [0x0000000000001000,  0x0000000000001002): DW_OP_breg5 RDI+0, DW
 CHECK-NEXT:     [0x0000000000001002,  0x0000000000001003): DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_convert (0x0000002a) "DW_ATE_signed_8", DW_OP_convert (0x00000031) "DW_ATE_signed_32", DW_OP_stack_value)
 CHECK-NEXT:     DW_AT_name	("y")
 
+CHECK:     DW_TAG_variable
+CHECK-NEXT:     DW_AT_location	(DW_OP_constu 0x33, DW_OP_convert 0x0, DW_OP_stack_value)
+CHECK-NEXT:     DW_AT_name	("d")
+
 CHECK:     DW_TAG_variable
 CHECK-NEXT:     DW_AT_location	(DW_OP_constu 0x2a, DW_OP_convert (0x00000031) "DW_ATE_signed_32", DW_OP_stack_value)
 CHECK-NEXT:     DW_AT_name	("c")
diff --git a/llvm/test/tools/gold/X86/thinlto.ll b/llvm/test/tools/gold/X86/thinlto.ll
index 9a81618aad7ea..ebe9b56a2f85c 100644
--- a/llvm/test/tools/gold/X86/thinlto.ll
+++ b/llvm/test/tools/gold/X86/thinlto.ll
@@ -87,7 +87,7 @@
 
 ; NM: T f
 ; NM2: T {{f|g}}
-; FORMAT: Format: ELF64-x86-64
+; FORMAT: Format: elf64-x86-64
 
 ; The backend index for this module contains summaries from itself and
 ; Inputs/thinlto.ll, as it imports from the latter.
diff --git a/llvm/test/tools/gold/X86/v1.16/wrap-2.ll b/llvm/test/tools/gold/X86/v1.16/wrap-2.ll
index 67948fafef572..95eeef14b7198 100644
--- a/llvm/test/tools/gold/X86/v1.16/wrap-2.ll
+++ b/llvm/test/tools/gold/X86/v1.16/wrap-2.ll
@@ -15,7 +15,7 @@
 ; RUN: opt -module-summary %s -o %t.o
 ; RUN: opt -module-summary %S/Inputs/wrap-bar.ll -o %t1.o
 ; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext %t.o %t1.o -shared -o %t.so -wrap=bar
-; RUN: llvm-objdump -d %t.so | FileCheck %s -check-prefix=THIN
+; RUN: llvm-objdump -d %t.so | FileCheck %s --check-prefix=THIN
 ; RUN: llvm-readobj --symbols %t.so | FileCheck -check-prefix=BIND %s
 
 ; Make sure that calls in foo() are not eliminated and that bar is
diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_expr_convert_generic.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_expr_convert_generic.s
new file mode 100644
index 0000000000000..59545e60cad62
--- /dev/null
+++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_expr_convert_generic.s
@@ -0,0 +1,181 @@
+# RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -dwarf-version=5 -o %t.o
+# RUN: llvm-dwarfdump %t.o | FileCheck %s
+# RUN: llvm-dwarfdump -verify %t.o
+
+# CHECK: DW_AT_location  (DW_OP_constu 0x7b, DW_OP_convert 0x0, DW_OP_stack_value)
+
+	.text
+	.file	"const.ll"
+	.globl	foo                     # -- Begin function foo
+	.p2align	4, 0x90
+	.type	foo,@function
+foo:                                    # @foo
+.Lfoo$local:
+.Lfunc_begin0:
+	.file	0 "/const.c"
+	.loc	0 1 0                   # const.c:1:0
+	.cfi_startproc
+# %bb.0:                                # %entry
+	.loc	0 3 1 prologue_end      # const.c:3:1
+	retq
+.Ltmp0:
+.Lfunc_end0:
+	.size	foo, .Lfunc_end0-foo
+	.cfi_endproc
+                                        # -- End function
+	.section	.debug_abbrev,"",@progbits
+	.byte	1                       # Abbreviation Code
+	.byte	17                      # DW_TAG_compile_unit
+	.byte	1                       # DW_CHILDREN_yes
+	.byte	37                      # DW_AT_producer
+	.byte	37                      # DW_FORM_strx1
+	.byte	19                      # DW_AT_language
+	.byte	5                       # DW_FORM_data2
+	.byte	3                       # DW_AT_name
+	.byte	37                      # DW_FORM_strx1
+	.byte	114                     # DW_AT_str_offsets_base
+	.byte	23                      # DW_FORM_sec_offset
+	.byte	16                      # DW_AT_stmt_list
+	.byte	23                      # DW_FORM_sec_offset
+	.byte	27                      # DW_AT_comp_dir
+	.byte	37                      # DW_FORM_strx1
+	.byte	17                      # DW_AT_low_pc
+	.byte	27                      # DW_FORM_addrx
+	.byte	18                      # DW_AT_high_pc
+	.byte	6                       # DW_FORM_data4
+	.byte	115                     # DW_AT_addr_base
+	.byte	23                      # DW_FORM_sec_offset
+	.byte	0                       # EOM(1)
+	.byte	0                       # EOM(2)
+	.byte	2                       # Abbreviation Code
+	.byte	46                      # DW_TAG_subprogram
+	.byte	1                       # DW_CHILDREN_yes
+	.byte	17                      # DW_AT_low_pc
+	.byte	27                      # DW_FORM_addrx
+	.byte	18                      # DW_AT_high_pc
+	.byte	6                       # DW_FORM_data4
+	.byte	64                      # DW_AT_frame_base
+	.byte	24                      # DW_FORM_exprloc
+	.byte	122                     # DW_AT_call_all_calls
+	.byte	25                      # DW_FORM_flag_present
+	.byte	3                       # DW_AT_name
+	.byte	37                      # DW_FORM_strx1
+	.byte	58                      # DW_AT_decl_file
+	.byte	11                      # DW_FORM_data1
+	.byte	59                      # DW_AT_decl_line
+	.byte	11                      # DW_FORM_data1
+	.byte	63                      # DW_AT_external
+	.byte	25                      # DW_FORM_flag_present
+	.byte	0                       # EOM(1)
+	.byte	0                       # EOM(2)
+	.byte	3                       # Abbreviation Code
+	.byte	52                      # DW_TAG_variable
+	.byte	0                       # DW_CHILDREN_no
+	.byte	2                       # DW_AT_location
+	.byte	24                      # DW_FORM_exprloc
+	.byte	3                       # DW_AT_name
+	.byte	37                      # DW_FORM_strx1
+	.byte	58                      # DW_AT_decl_file
+	.byte	11                      # DW_FORM_data1
+	.byte	59                      # DW_AT_decl_line
+	.byte	11                      # DW_FORM_data1
+	.byte	73                      # DW_AT_type
+	.byte	19                      # DW_FORM_ref4
+	.byte	0                       # EOM(1)
+	.byte	0                       # EOM(2)
+	.byte	4                       # Abbreviation Code
+	.byte	36                      # DW_TAG_base_type
+	.byte	0                       # DW_CHILDREN_no
+	.byte	3                       # DW_AT_name
+	.byte	37                      # DW_FORM_strx1
+	.byte	62                      # DW_AT_encoding
+	.byte	11                      # DW_FORM_data1
+	.byte	11                      # DW_AT_byte_size
+	.byte	11                      # DW_FORM_data1
+	.byte	0                       # EOM(1)
+	.byte	0                       # EOM(2)
+	.byte	0                       # EOM(3)
+	.section	.debug_info,"",@progbits
+.Lcu_begin0:
+	.long	.Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit
+.Ldebug_info_start0:
+	.short	5                       # DWARF version number
+	.byte	1                       # DWARF Unit Type
+	.byte	8                       # Address Size (in bytes)
+	.long	.debug_abbrev           # Offset Into Abbrev. Section
+	.byte	1                       # Abbrev [1] 0xc:0x36 DW_TAG_compile_unit
+	.byte	0                       # DW_AT_producer
+	.short	12                      # DW_AT_language
+	.byte	1                       # DW_AT_name
+	.long	.Lstr_offsets_base0     # DW_AT_str_offsets_base
+	.long	.Lline_table_start0     # DW_AT_stmt_list
+	.byte	2                       # DW_AT_comp_dir
+	.byte	0                       # DW_AT_low_pc
+	.long	.Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc
+	.long	.Laddr_table_base0      # DW_AT_addr_base
+	.byte	2                       # Abbrev [2] 0x23:0x1a DW_TAG_subprogram
+	.byte	0                       # DW_AT_low_pc
+	.long	.Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc
+	.byte	1                       # DW_AT_frame_base
+	.byte	87
+                                        # DW_AT_call_all_calls
+	.byte	3                       # DW_AT_name
+	.byte	0                       # DW_AT_decl_file
+	.byte	1                       # DW_AT_decl_line
+                                        # DW_AT_external
+	.byte	3                       # Abbrev [3] 0x2e:0xe DW_TAG_variable
+	.byte	5                       # DW_AT_location
+	.byte	16
+	.byte	123
+	.byte	168
+	.byte	0
+	.byte	159
+	.byte	4                       # DW_AT_name
+	.byte	0                       # DW_AT_decl_file
+	.byte	2                       # DW_AT_decl_line
+	.long	61                      # DW_AT_type
+	.byte	0                       # End Of Children Mark
+	.byte	4                       # Abbrev [4] 0x3d:0x4 DW_TAG_base_type
+	.byte	5                       # DW_AT_name
+	.byte	5                       # DW_AT_encoding
+	.byte	4                       # DW_AT_byte_size
+	.byte	0                       # End Of Children Mark
+.Ldebug_info_end0:
+	.section	.debug_str_offsets,"",@progbits
+	.long	28
+	.short	5
+	.short	0
+.Lstr_offsets_base0:
+	.section	.debug_str,"MS",@progbits,1
+.Linfo_string0:
+	.asciz	"clang version 11.0.0"  # string offset=0
+.Linfo_string1:
+	.asciz	"const.c"               # string offset=21
+.Linfo_string2:
+	.asciz	"/"                     # string offset=29
+.Linfo_string3:
+	.asciz	"foo"                   # string offset=31
+.Linfo_string4:
+	.asciz	"local"                 # string offset=35
+.Linfo_string5:
+	.asciz	"int"                   # string offset=41
+	.section	.debug_str_offsets,"",@progbits
+	.long	.Linfo_string0
+	.long	.Linfo_string1
+	.long	.Linfo_string2
+	.long	.Linfo_string3
+	.long	.Linfo_string4
+	.long	.Linfo_string5
+	.section	.debug_addr,"",@progbits
+	.long	.Ldebug_addr_end0-.Ldebug_addr_start0 # Length of contribution
+.Ldebug_addr_start0:
+	.short	5                       # DWARF version number
+	.byte	8                       # Address size
+	.byte	0                       # Segment selector size
+.Laddr_table_base0:
+	.quad	.Lfunc_begin0
+.Ldebug_addr_end0:
+	.ident	"clang version 11.0.0"
+	.section	".note.GNU-stack","",@progbits
+	.section	.debug_line,"",@progbits
+.Lline_table_start0:
diff --git a/llvm/test/tools/llvm-objcopy/COFF/remove-section.test b/llvm/test/tools/llvm-objcopy/COFF/remove-section.test
index 064929191436f..c5eecbf7f5d27 100644
--- a/llvm/test/tools/llvm-objcopy/COFF/remove-section.test
+++ b/llvm/test/tools/llvm-objcopy/COFF/remove-section.test
@@ -1,23 +1,23 @@
 # RUN: yaml2obj %s -o %t.in.o
 #
-# RUN: llvm-objdump -section-headers %t.in.o | FileCheck %s --check-prefixes=SECTIONS-PRE
+# RUN: llvm-objdump --section-headers %t.in.o | FileCheck %s --check-prefixes=SECTIONS-PRE
 # RUN: llvm-objdump -t %t.in.o | FileCheck %s --check-prefixes=SYMBOLS-PRE
 #
 # RUN: llvm-objcopy -R .bss %t.in.o %t.remove-bss.o
-# RUN: llvm-objdump -section-headers %t.remove-bss.o | FileCheck %s --check-prefix=SECTIONS-REMOVE-BSS
+# RUN: llvm-objdump --section-headers %t.remove-bss.o | FileCheck %s --check-prefix=SECTIONS-REMOVE-BSS
 # RUN: llvm-objdump -t %t.remove-bss.o | FileCheck %s --check-prefix=SYMBOLS-REMOVE-BSS
 #
 # RUN: llvm-objcopy --remove-section .bss %t.in.o %t.cmp.o
 # RUN: cmp %t.remove-bss.o %t.cmp.o
 #
 # RUN: llvm-objcopy -R .text %t.in.o %t.remove-text.o
-# RUN: llvm-objdump -section-headers %t.remove-text.o | FileCheck %s --check-prefix=SECTIONS-REMOVE-TEXT
+# RUN: llvm-objdump --section-headers %t.remove-text.o | FileCheck %s --check-prefix=SECTIONS-REMOVE-TEXT
 # RUN: llvm-objdump -t %t.remove-text.o | FileCheck %s --check-prefix=SYMBOLS-REMOVE-TEXT
 #
 # RUN: not llvm-objcopy -R .comdat %t.in.o %t.remove-comdat.o 2>&1 | FileCheck %s --check-prefix=ERROR-RELOC
 #
 # RUN: llvm-objcopy -R .text -R .comdat %t.in.o %t.remove-text-comdat.o
-# RUN: llvm-objdump -section-headers %t.remove-text-comdat.o | FileCheck %s --check-prefix=SECTIONS-REMOVE-TEXT-COMDAT
+# RUN: llvm-objdump --section-headers %t.remove-text-comdat.o | FileCheck %s --check-prefix=SECTIONS-REMOVE-TEXT-COMDAT
 # RUN: llvm-objdump -t %t.remove-text-comdat.o | FileCheck %s --check-prefix=SYMBOLS-REMOVE-TEXT-COMDAT
 #
 #
diff --git a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
index 4af2d0514bf49..1ca911a640129 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
@@ -31,16 +31,16 @@
 # RUN: llvm-readobj --file-headers %t.sparcel.o | FileCheck %s --check-prefixes=CHECK,LE,SPARCEL,32
 
 # CHECK: Format:
-# 32-SAME:      ELF32-
-# 64-SAME:      ELF64-
-# AARCH64-SAME: aarch64-little
-# ARM-SAME:     arm-little
+# 32-SAME:      elf32-
+# 64-SAME:      elf64-
+# AARCH64-SAME: littleaarch64
+# ARM-SAME:     littlearm
 # I386-SAME:    i386
 # MIPS-SAME:    mips{{$}}
 # RISCV32-SAME: riscv{{$}}
 # RISCV64-SAME: riscv{{$}}
-# PPC-SAME:     ppc{{$}}
-# PPC64le-SAME: ppc64
+# PPC-SAME:     powerpc{{$}}
+# PPC64le-SAME: powerpc{{$}}
 # SPARC-SAME:   sparc
 # SPARCEL-SAME: sparc
 # X86-64-SAME:  x86-64
diff --git a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
index 720dcbfa99b8f..f2c37392fc9be 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
@@ -133,16 +133,16 @@ Symbols:
     Binding:  STB_GLOBAL
 
 # CHECK: Format:
-# 32-SAME:      ELF32-
-# 64-SAME:      ELF64-
+# 32-SAME:      elf32-
+# 64-SAME:      elf64-
 # I386-SAME:    i386
 # IAMCU-SAME:   iamcu
 # AARCH-SAME:   aarch64
-# ARM-SAME:     arm-little
+# ARM-SAME:     littlearm
 # MIPS-SAME:    mips
-# PPC-SAME:     ppc{{$}}
-# PPC64BE-SAME: ppc64{{$}}
-# PPC64LE-SAME: ppc64{{$}}
+# PPC-SAME:     powerpc{{$}}
+# PPC64BE-SAME: powerpc{{$}}
+# PPC64LE-SAME: powerpc{{$}}
 # RISCV32-SAME: riscv{{$}}
 # RISCV64-SAME: riscv{{$}}
 # SPARC-SAME:   sparc
diff --git a/llvm/test/tools/llvm-objcopy/ELF/many-sections.test b/llvm/test/tools/llvm-objcopy/ELF/many-sections.test
index 906fb3a6fbba1..41e237a377717 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/many-sections.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/many-sections.test
@@ -5,7 +5,7 @@ RUN: llvm-readobj --sections %t2 | FileCheck --check-prefix=SECS %s
 RUN: llvm-readobj --symbols %t2 | grep "Symbol {" | wc -l | FileCheck --check-prefix=SYMS %s
 RUN: llvm-readobj --symbols %t2 | FileCheck %s --check-prefix=SYM_SEC_IDS
 
-EHDR:      Format: ELF64-x86-64
+EHDR:      Format: elf64-x86-64
 EHDR-NEXT: Arch: x86_64
 EHDR-NEXT: AddressSize: 64bit
 EHDR-NEXT: LoadName:
diff --git a/llvm/test/tools/llvm-objdump/AArch64/mach-print-armv8crypto.test b/llvm/test/tools/llvm-objdump/AArch64/mach-print-armv8crypto.test
deleted file mode 100644
index e5ac0cb453e4e..0000000000000
--- a/llvm/test/tools/llvm-objdump/AArch64/mach-print-armv8crypto.test
+++ /dev/null
@@ -1,3 +0,0 @@
-RUN: llvm-objdump -d -m -no-show-raw-insn %p/Inputs/print-armv8crypto.obj.macho-aarch64 | FileCheck %s
-
-CHECK: 0:	sha1su0.4s	v0, v1, v2
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-print-mrs.test b/llvm/test/tools/llvm-objdump/AArch64/macho-print-mrs.test
deleted file mode 100644
index c629a4de38768..0000000000000
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-print-mrs.test
+++ /dev/null
@@ -1,3 +0,0 @@
-RUN: llvm-objdump -d -m -no-show-raw-insn %p/Inputs/print-mrs.obj.macho-aarch64 | FileCheck %s
-
-CHECK: 0:  mrs x0, CPM_IOACC_CTL_EL3
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-symbolized-disassembly.test b/llvm/test/tools/llvm-objdump/ARM/macho-symbolized-disassembly.test
deleted file mode 100644
index 2b7e44e940bb3..0000000000000
--- a/llvm/test/tools/llvm-objdump/ARM/macho-symbolized-disassembly.test
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.obj.macho-arm | FileCheck %s -check-prefix=OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.exe.macho-arm | FileCheck %s -check-prefix=EXE
-
-OBJ: 00000006	40 f2 24 03 	movw	r3, :lower16:((54-14)-4)
-OBJ: 0000000a	c0 f2 00 03 	movt	r3, :upper16:((54-14)-4)
-OBJ: 00000024	ff f7 ec ff 	bl	_printf
-
-EXE: 0000bfa8	00 f0 28 e8 	blx	0xbffc @ symbol stub for: _printf
diff --git a/llvm/test/tools/llvm-objdump/COFF/eh_frame.test b/llvm/test/tools/llvm-objdump/COFF/eh_frame.test
index ad37ebc119920..ff48331ffa2a7 100644
--- a/llvm/test/tools/llvm-objdump/COFF/eh_frame.test
+++ b/llvm/test/tools/llvm-objdump/COFF/eh_frame.test
@@ -1,4 +1,4 @@
-# RUN: yaml2obj %p/Inputs/eh_frame-coff.yaml | llvm-objdump -dwarf=frames - 2>/dev/null | FileCheck %s
+# RUN: yaml2obj %p/Inputs/eh_frame-coff.yaml | llvm-objdump --dwarf=frames - 2>/dev/null | FileCheck %s
 
 # CHECK: .eh_frame contents:
 
diff --git a/llvm/test/tools/llvm-objdump/COFF/file-headers.test b/llvm/test/tools/llvm-objdump/COFF/file-headers.test
index bdfc3248e1470..60f7bd5ce3334 100644
--- a/llvm/test/tools/llvm-objdump/COFF/file-headers.test
+++ b/llvm/test/tools/llvm-objdump/COFF/file-headers.test
@@ -1,6 +1,6 @@
 # RUN: yaml2obj %s -o %t
 # RUN: llvm-objdump -f %t | FileCheck %s -DFILE=%t
-# RUN: llvm-objdump -file-headers %t | FileCheck %s -DFILE=%t
+# RUN: llvm-objdump --file-headers %t | FileCheck %s -DFILE=%t
 
 !COFF
 header: !Header
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/cfi.elf-aarch64 b/llvm/test/tools/llvm-objdump/ELF/AArch64/Inputs/cfi.elf-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/cfi.elf-aarch64
rename to llvm/test/tools/llvm-objdump/ELF/AArch64/Inputs/cfi.elf-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/elf-aarch64-mapping-symbols.test b/llvm/test/tools/llvm-objdump/ELF/AArch64/elf-aarch64-mapping-symbols.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/elf-aarch64-mapping-symbols.test
rename to llvm/test/tools/llvm-objdump/ELF/AArch64/elf-aarch64-mapping-symbols.test
diff --git a/llvm/test/tools/llvm-objdump/AArch64/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/AArch64/lit.local.cfg
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/lit.local.cfg
rename to llvm/test/tools/llvm-objdump/ELF/AArch64/lit.local.cfg
diff --git a/llvm/test/tools/llvm-objdump/AArch64/plt.test b/llvm/test/tools/llvm-objdump/ELF/AArch64/plt.test
similarity index 97%
rename from llvm/test/tools/llvm-objdump/AArch64/plt.test
rename to llvm/test/tools/llvm-objdump/ELF/AArch64/plt.test
index c08ff1ccca681..6238cf5565f72 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/plt.test
+++ b/llvm/test/tools/llvm-objdump/ELF/AArch64/plt.test
@@ -6,7 +6,7 @@
 # CHECK: bl {{.*}} <__cfi_slowpath@plt>
 
 # RUN: yaml2obj %s -o %t.aarch64
-# RUN: llvm-objdump -d -mattr=+bti %t.aarch64 | \
+# RUN: llvm-objdump -d --mattr=+bti %t.aarch64 | \
 # RUN:   FileCheck --check-prefix=CHECK-BTI %s
 # CHECK-BTI: bl {{.*}} <f1@plt>
 # CHECK-BTI: bl {{.*}} <f2@plt>
diff --git a/llvm/test/tools/llvm-objdump/AMDGPU/Inputs/source-lines.cl b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/Inputs/source-lines.cl
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AMDGPU/Inputs/source-lines.cl
rename to llvm/test/tools/llvm-objdump/ELF/AMDGPU/Inputs/source-lines.cl
diff --git a/llvm/test/tools/llvm-objdump/AMDGPU/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/lit.local.cfg
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AMDGPU/lit.local.cfg
rename to llvm/test/tools/llvm-objdump/ELF/AMDGPU/lit.local.cfg
diff --git a/llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
similarity index 95%
rename from llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll
rename to llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
index 0fbed0a8178e8..6258d48748e25 100644
--- a/llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll
+++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
@@ -1,7 +1,7 @@
 ; RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %s > %t.ll
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -O0 -o %t.o %t.ll
-; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx802 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll
-; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx802 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll
+; RUN: llvm-objdump --triple=amdgcn-amd-amdhsa --mcpu=gfx802 -d -l %t.o | FileCheck --check-prefix=LINE %t.ll
+; RUN: llvm-objdump --triple=amdgcn-amd-amdhsa --mcpu=gfx802 -d -S %t.o | FileCheck --check-prefix=SOURCE %t.ll
 
 ; Prologue.
 ; LINE:      source_lines_test{{>?}}:
diff --git a/llvm/test/tools/llvm-objdump/ARM/disassemble-code-data-mix.s b/llvm/test/tools/llvm-objdump/ELF/ARM/disassemble-code-data-mix.s
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/disassemble-code-data-mix.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/disassemble-code-data-mix.s
diff --git a/llvm/test/tools/llvm-objdump/ARM/invalid-instruction.s b/llvm/test/tools/llvm-objdump/ELF/ARM/invalid-instruction.s
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/invalid-instruction.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/invalid-instruction.s
diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/ARM/lit.local.cfg
new file mode 100644
index 0000000000000..236e1d3441665
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'ARM' in config.root.targets:
+    config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/ARM/reg-names.s b/llvm/test/tools/llvm-objdump/ELF/ARM/reg-names.s
similarity index 95%
rename from llvm/test/tools/llvm-objdump/ARM/reg-names.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/reg-names.s
index e1e12d8ba5993..3ba7acf86671b 100644
--- a/llvm/test/tools/llvm-objdump/ARM/reg-names.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/reg-names.s
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc %s -triple armv5-unknown-linux -filetype=obj -o %t
-@ RUN: llvm-objdump -d %t | FileCheck -check-prefix=STD %s
+@ RUN: llvm-objdump -d %t | FileCheck --check-prefix=STD %s
 @ RUN: llvm-objdump -d -Mreg-names-std %t \
 @ RUN:   | FileCheck -check-prefix=STD %s
 @ RUN: llvm-objdump -d --disassembler-options=reg-names-raw %t \
diff --git a/llvm/test/tools/llvm-objdump/ARM/unknown-instr.test b/llvm/test/tools/llvm-objdump/ELF/ARM/unknown-instr.test
similarity index 86%
rename from llvm/test/tools/llvm-objdump/ARM/unknown-instr.test
rename to llvm/test/tools/llvm-objdump/ELF/ARM/unknown-instr.test
index 8055e63c18740..cb990b85dfce5 100644
--- a/llvm/test/tools/llvm-objdump/ARM/unknown-instr.test
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/unknown-instr.test
@@ -1,5 +1,5 @@
 # RUN: yaml2obj %s -o %t
-# RUN: llvm-objdump -D -triple=thumbv8.1m.main-none-eabi %t | FileCheck %s
+# RUN: llvm-objdump -D --triple=thumbv8.1m.main-none-eabi %t | FileCheck %s
 
 ## This is a test case with "random" data/instructions, checking that
 ## llvm-objdump handles such instructions cleanly. Disassembly of instructions
@@ -10,7 +10,7 @@
 ##
 ## and disassembly is attempted with:
 ##
-##   llvm-objdump -mattr=+ext1
+##   llvm-objdump --mattr=+ext1
 
 # CHECK:        00000000 <.text>:
 # CHECK-NEXT:       0: cb              <unknown>
diff --git a/llvm/test/tools/llvm-objdump/ARM/v5t-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5t-subarch.s
similarity index 78%
rename from llvm/test/tools/llvm-objdump/ARM/v5t-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v5t-subarch.s
index c9ce2cf6cebd6..9013e189ec60b 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v5t-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5t-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv5t-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv5t-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .arch armv5t
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v5te-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
similarity index 81%
rename from llvm/test/tools/llvm-objdump/ARM/v5te-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
index 87e8548fb0144..3ccfed21fd5c5 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v5te-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv5te-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv5te-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .arch armv5te
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v5tej-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5tej-subarch.s
similarity index 76%
rename from llvm/test/tools/llvm-objdump/ARM/v5tej-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v5tej-subarch.s
index 42dc87389a341..32b3f8280521b 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v5tej-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5tej-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv5tej-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv5tej-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 bxj:
 bxj r0
diff --git a/llvm/test/tools/llvm-objdump/ARM/v6-neg-subfeatures.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v6-neg-subfeatures.s
similarity index 82%
rename from llvm/test/tools/llvm-objdump/ARM/v6-neg-subfeatures.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v6-neg-subfeatures.s
index 1a8d8f283336d..db262a35803cd 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v6-neg-subfeatures.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v6-neg-subfeatures.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv6 -mattr=+vfp2 -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv6 -mattr=+vfp2 -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .eabi_attribute Tag_FP_arch, 1 // VFP2
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v6-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v6-subarch.s
similarity index 82%
rename from llvm/test/tools/llvm-objdump/ARM/v6-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v6-subarch.s
index c70761e7c8c52..8297c10f8dbc2 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v6-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v6-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv6-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv6-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .arch armv6
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v6-subfeatures.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v6-subfeatures.s
similarity index 81%
rename from llvm/test/tools/llvm-objdump/ARM/v6-subfeatures.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v6-subfeatures.s
index e8e806740d198..a00f5dc22f92e 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v6-subfeatures.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v6-subfeatures.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv6 -mattr=+vfp2 -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv6 -mattr=+vfp2 -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .eabi_attribute Tag_FP_arch, 2 // VFP2
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v6k-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v6k-subarch.s
similarity index 79%
rename from llvm/test/tools/llvm-objdump/ARM/v6k-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v6k-subarch.s
index 8df4ce5e25766..09241bd5be53d 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v6k-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v6k-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv6k-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv6k-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .arch armv6k
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v6m-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v6m-subarch.s
similarity index 77%
rename from llvm/test/tools/llvm-objdump/ARM/v6m-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v6m-subarch.s
index f4c56989c17ec..d09badfce457a 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v6m-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v6m-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv6m-elf -filetype=obj | llvm-objdump -triple=thumb -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv6m-elf -filetype=obj | llvm-objdump --triple=thumb -d - | FileCheck %s
 
 .arch armv6m
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v6t2-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v6t2-subarch.s
similarity index 82%
rename from llvm/test/tools/llvm-objdump/ARM/v6t2-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v6t2-subarch.s
index 36e134342972c..748b63258038c 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v6t2-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v6t2-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv6t2-elf -filetype=obj | llvm-objdump -triple=thumb -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv6t2-elf -filetype=obj | llvm-objdump --triple=thumb -d - | FileCheck %s
 
 .arch armv6t2
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v7a-neg-subfeature.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v7a-neg-subfeature.s
similarity index 81%
rename from llvm/test/tools/llvm-objdump/ARM/v7a-neg-subfeature.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v7a-neg-subfeature.s
index 8083e5b0eee0e..37226b671d885 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v7a-neg-subfeature.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v7a-neg-subfeature.s
@@ -1,5 +1,5 @@
-@ RUN: llvm-mc < %s -triple armv7a -mattr=+vfp3,+neon,+fp16,+hwdiv-arm,+hwdiv -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
-@ RUN: llvm-mc < %s -triple armv7a -mattr=+vfp3,+neon,+fp16,+hwdiv-arm,+hwdiv -filetype=obj | llvm-objdump -triple=thumb -d - | FileCheck %s --check-prefix=CHECK-THUMB
+@ RUN: llvm-mc < %s -triple armv7a -mattr=+vfp3,+neon,+fp16,+hwdiv-arm,+hwdiv -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv7a -mattr=+vfp3,+neon,+fp16,+hwdiv-arm,+hwdiv -filetype=obj | llvm-objdump --triple=thumb -d - | FileCheck %s --check-prefix=CHECK-THUMB
 
 .eabi_attribute Tag_FP_arch, 0 // disallow vfp
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v7a-subfeature.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v7a-subfeature.s
similarity index 90%
rename from llvm/test/tools/llvm-objdump/ARM/v7a-subfeature.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v7a-subfeature.s
index f43554579a362..be29cd83f1110 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v7a-subfeature.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v7a-subfeature.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv7a -mattr=+vfp3,+neon,+fp16,+hwdiv-arm -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv7a -mattr=+vfp3,+neon,+fp16,+hwdiv-arm -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .eabi_attribute Tag_FP_arch, 3 // VFP3
 .eabi_attribute Tag_Advanced_SIMD_arch, 2 // SIMDv1 with fp16
diff --git a/llvm/test/tools/llvm-objdump/ARM/v7m-neg-subfeatures.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v7m-neg-subfeatures.s
similarity index 87%
rename from llvm/test/tools/llvm-objdump/ARM/v7m-neg-subfeatures.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v7m-neg-subfeatures.s
index b3a79c7d5c2b0..03388362d935f 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v7m-neg-subfeatures.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v7m-neg-subfeatures.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv7m -mattr=+vfp4 -filetype=obj | llvm-objdump -triple=thumb -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv7m -mattr=+vfp4 -filetype=obj | llvm-objdump --triple=thumb -d - | FileCheck %s
 
 .eabi_attribute Tag_CPU_arch, 10 // v7
 .eabi_attribute Tag_FP_arch, 0 // VFP4
diff --git a/llvm/test/tools/llvm-objdump/ARM/v7m-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v7m-subarch.s
similarity index 81%
rename from llvm/test/tools/llvm-objdump/ARM/v7m-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v7m-subarch.s
index 8f6ff57e0ff30..3635cb6ca1fff 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v7m-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v7m-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv7m-elf -filetype=obj | llvm-objdump -triple=thumb -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv7m-elf -filetype=obj | llvm-objdump --triple=thumb -d - | FileCheck %s
 
 .arch armv7m
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v7m-subfeatures.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v7m-subfeatures.s
similarity index 90%
rename from llvm/test/tools/llvm-objdump/ARM/v7m-subfeatures.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v7m-subfeatures.s
index c7a40af8ae90e..e27158301b4f4 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v7m-subfeatures.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v7m-subfeatures.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv7m -mattr=+vfp4 -filetype=obj | llvm-objdump -triple=thumb -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv7m -mattr=+vfp4 -filetype=obj | llvm-objdump --triple=thumb -d - | FileCheck %s
 
 .eabi_attribute Tag_CPU_arch, 10 // v7
 .eabi_attribute Tag_CPU_arch_profile, 0x4D // 'M' profile
diff --git a/llvm/test/tools/llvm-objdump/ARM/v7r-subfeatures.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v7r-subfeatures.s
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/v7r-subfeatures.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v7r-subfeatures.s
diff --git a/llvm/test/tools/llvm-objdump/ARM/v8a-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v8a-subarch.s
similarity index 80%
rename from llvm/test/tools/llvm-objdump/ARM/v8a-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v8a-subarch.s
index de3ce59a0d4ae..d62c7dc97ccb1 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v8a-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v8a-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv8a-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv8a-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .arch armv8a
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/v8r-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v8r-subarch.s
similarity index 87%
rename from llvm/test/tools/llvm-objdump/ARM/v8r-subarch.s
rename to llvm/test/tools/llvm-objdump/ELF/ARM/v8r-subarch.s
index fd58544b3a5d8..a969a14c25cff 100644
--- a/llvm/test/tools/llvm-objdump/ARM/v8r-subarch.s
+++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v8r-subarch.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv8r-elf -filetype=obj | llvm-objdump -triple=arm -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv8r-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .eabi_attribute Tag_CPU_arch, 15 // v8_R
 .eabi_attribute Tag_CPU_arch_profile, 0x52 // 'R' profile
diff --git a/llvm/test/tools/llvm-objdump/Hexagon/Inputs/source-interleave-hexagon.c b/llvm/test/tools/llvm-objdump/ELF/Hexagon/Inputs/source-interleave-hexagon.c
similarity index 100%
rename from llvm/test/tools/llvm-objdump/Hexagon/Inputs/source-interleave-hexagon.c
rename to llvm/test/tools/llvm-objdump/ELF/Hexagon/Inputs/source-interleave-hexagon.c
diff --git a/llvm/test/tools/llvm-objdump/Hexagon/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/Hexagon/lit.local.cfg
similarity index 100%
rename from llvm/test/tools/llvm-objdump/Hexagon/lit.local.cfg
rename to llvm/test/tools/llvm-objdump/ELF/Hexagon/lit.local.cfg
diff --git a/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll b/llvm/test/tools/llvm-objdump/ELF/Hexagon/source-interleave-hexagon.ll
similarity index 100%
rename from llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll
rename to llvm/test/tools/llvm-objdump/ELF/Hexagon/source-interleave-hexagon.ll
diff --git a/llvm/test/tools/llvm-objdump/Mips/disassemble-all.test b/llvm/test/tools/llvm-objdump/ELF/Mips/disassemble-all.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/Mips/disassemble-all.test
rename to llvm/test/tools/llvm-objdump/ELF/Mips/disassemble-all.test
diff --git a/llvm/test/tools/llvm-objdump/Mips/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/Mips/lit.local.cfg
similarity index 100%
rename from llvm/test/tools/llvm-objdump/Mips/lit.local.cfg
rename to llvm/test/tools/llvm-objdump/ELF/Mips/lit.local.cfg
diff --git a/llvm/test/tools/llvm-objdump/PowerPC/branch-offset.s b/llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s
similarity index 100%
rename from llvm/test/tools/llvm-objdump/PowerPC/branch-offset.s
rename to llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s
diff --git a/llvm/test/tools/llvm-objdump/ELF/PowerPC/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/PowerPC/lit.local.cfg
new file mode 100644
index 0000000000000..b77510721e100
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/ELF/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'PowerPC' in config.root.targets:
+      config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/ELF/call-absolute-symbol.test b/llvm/test/tools/llvm-objdump/ELF/call-absolute-symbol.test
index 0968dbb354a08..f1c6ff025d706 100644
--- a/llvm/test/tools/llvm-objdump/ELF/call-absolute-symbol.test
+++ b/llvm/test/tools/llvm-objdump/ELF/call-absolute-symbol.test
@@ -1,3 +1,3 @@
 // REQUIRES: x86_64-linux
-// RUN: llvm-objdump --disassemble %p/Inputs/call-absolute-symbol.elf-x86_64 | FileCheck %s
+// RUN: llvm-objdump -d %p/Inputs/call-absolute-symbol.elf-x86_64 | FileCheck %s
 CHECK: 201000:	e8 fb f0 df ff 	callq	-2100997 <foo>
diff --git a/llvm/test/tools/llvm-objdump/ELF/file-headers.test b/llvm/test/tools/llvm-objdump/ELF/file-headers.test
index 237818bab2db4..57f9f1d50c3d0 100644
--- a/llvm/test/tools/llvm-objdump/ELF/file-headers.test
+++ b/llvm/test/tools/llvm-objdump/ELF/file-headers.test
@@ -1,6 +1,6 @@
 # RUN: yaml2obj --docnum=1 %s -o %t
-# RUN: llvm-objdump -f %t | FileCheck %s -DFILE=%t -check-prefix ELF64
-# RUN: llvm-objdump -file-headers %t | FileCheck %s -DFILE=%t -check-prefix ELF64
+# RUN: llvm-objdump -f %t | FileCheck %s -DFILE=%t --check-prefix ELF64
+# RUN: llvm-objdump --file-headers %t | FileCheck %s -DFILE=%t --check-prefix ELF64
 
 !ELF
 FileHeader:
@@ -15,8 +15,8 @@ FileHeader:
 # ELF64: start address: 0x00123456789abcde
 
 # RUN: yaml2obj --docnum=2 %s -o %t-i386
-# RUN: llvm-objdump -f %t-i386 | FileCheck -DFILE=%t-i386 %s -check-prefix ELF32
-# RUN: llvm-objdump -file-headers %t-i386 | FileCheck %s -DFILE=%t-i386 -check-prefix ELF32
+# RUN: llvm-objdump -f %t-i386 | FileCheck -DFILE=%t-i386 %s --check-prefix ELF32
+# RUN: llvm-objdump --file-headers %t-i386 | FileCheck %s -DFILE=%t-i386 --check-prefix ELF32
 
 # ELF32: [[FILE]]: file format elf32-i386
 # ELF32: architecture: i386
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/ObjC.exe.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/ObjC.exe.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/ObjC.exe.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/ObjC.exe.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/ObjC.obj.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/ObjC.obj.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/ObjC.obj.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/ObjC.obj.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/arm64_32-fat.o b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/arm64_32-fat.o
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/arm64_32-fat.o
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/arm64_32-fat.o
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/arm64e.macho.yaml b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/arm64e.macho.yaml
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/arm64e.macho.yaml
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/arm64e.macho.yaml
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/fat.macho-armv7s-arm64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/fat.macho-armv7s-arm64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/fat.macho-armv7s-arm64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/fat.macho-armv7s-arm64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/hello.exe.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/hello.exe.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/hello.exe.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/hello.exe.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/hello.obj.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/hello.obj.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/hello.obj.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/hello.obj.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/kextbundle.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/kextbundle.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/kextbundle.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/kextbundle.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/link-opt-hints.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/link-opt-hints.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/link-opt-hints.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/link-opt-hints.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/print-armv8crypto.obj.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-armv8crypto.obj.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/print-armv8crypto.obj.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-armv8crypto.obj.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/print-mrs.obj.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-mrs.obj.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/print-mrs.obj.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/print-mrs.obj.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/reloc-addend.obj.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/reloc-addend.obj.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/reloc-addend.obj.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/reloc-addend.obj.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/thread.macho-aarch64 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/thread.macho-aarch64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/thread.macho-aarch64
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/thread.macho-aarch64
diff --git a/llvm/test/tools/llvm-objdump/AArch64/Inputs/thread.macho-arm64_32 b/llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/thread.macho-arm64_32
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/Inputs/thread.macho-arm64_32
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/Inputs/thread.macho-arm64_32
diff --git a/llvm/test/tools/llvm-objdump/AArch64/arm64_32-fat.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/arm64_32-fat.test
similarity index 64%
rename from llvm/test/tools/llvm-objdump/AArch64/arm64_32-fat.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/arm64_32-fat.test
index dc9b319e3c45c..898c3e6d6c5a5 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/arm64_32-fat.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/arm64_32-fat.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -universal-headers %p/Inputs/arm64_32-fat.o | FileCheck %s
+RUN: llvm-objdump --macho --universal-headers %p/Inputs/arm64_32-fat.o | FileCheck %s
 
 CHECK: cputype CPU_TYPE_ARM64_32
 CHECK-NEXT: cpusubtype CPU_SUBTYPE_ARM64_32_V8
diff --git a/llvm/test/tools/llvm-objdump/AArch64/arm64_32.s b/llvm/test/tools/llvm-objdump/MachO/AArch64/arm64_32.s
similarity index 50%
rename from llvm/test/tools/llvm-objdump/AArch64/arm64_32.s
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/arm64_32.s
index 050719d90515c..69d01ee0c267d 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/arm64_32.s
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/arm64_32.s
@@ -1,6 +1,6 @@
 // RUN: llvm-mc -triple arm64_32-apple-watchos %s -filetype=obj -o %t
-// RUN: llvm-objdump -macho -d %t | FileCheck %s
-// RUN: llvm-objdump -macho -private-headers %t | FileCheck %s --check-prefix=CHECK-HEADERS
+// RUN: llvm-objdump --macho -d %t | FileCheck %s
+// RUN: llvm-objdump --macho --private-headers %t | FileCheck %s --check-prefix=CHECK-HEADERS
 
 // CHECK: ldr x0, [x2]
 ldr x0, [x2]
diff --git a/llvm/test/tools/llvm-objdump/MachO/AArch64/lit.local.cfg b/llvm/test/tools/llvm-objdump/MachO/AArch64/lit.local.cfg
new file mode 100644
index 0000000000000..7184443994b69
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'AArch64' in config.root.targets:
+    config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/MachO/AArch64/mach-print-armv8crypto.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/mach-print-armv8crypto.test
new file mode 100644
index 0000000000000..b470c9c425216
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/mach-print-armv8crypto.test
@@ -0,0 +1,3 @@
+RUN: llvm-objdump -d -m --no-show-raw-insn %p/Inputs/print-armv8crypto.obj.macho-aarch64 | FileCheck %s
+
+CHECK: 0:	sha1su0.4s	v0, v1, v2
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-arm64e.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64e.test
similarity index 78%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-arm64e.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64e.test
index cd001cf7815ff..e40a96b770e20 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-arm64e.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64e.test
@@ -1,5 +1,5 @@
 // RUN: yaml2obj %p/Inputs/arm64e.macho.yaml -o %tarm64e.o
-// RUN: llvm-objdump -p %tarm64e.o | FileCheck -strict-whitespace %s
+// RUN: llvm-objdump -p %tarm64e.o | FileCheck --strict-whitespace %s
 
 CHECK:      Mach header
 CHECK-NEXT:       magic cputype cpusubtype  caps    filetype ncmds sizeofcmds      flags
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-fat-arm-disasm.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-fat-arm-disasm.test
similarity index 50%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-fat-arm-disasm.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-fat-arm-disasm.test
index 31acba8dbcbd3..5ef09eff8cdf4 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-fat-arm-disasm.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-fat-arm-disasm.test
@@ -1,5 +1,5 @@
-RUN: llvm-objdump -d -m -no-show-raw-insn -arch all %p/Inputs/fat.macho-armv7s-arm64 >%t0
-RUN: llvm-objdump -dm -no-show-raw-insn -arch all %p/Inputs/fat.macho-armv7s-arm64 >%t1
+RUN: llvm-objdump -d -m --no-show-raw-insn --arch all %p/Inputs/fat.macho-armv7s-arm64 >%t0
+RUN: llvm-objdump -dm --no-show-raw-insn --arch all %p/Inputs/fat.macho-armv7s-arm64 >%t1
 RUN: cmp %t0 %t1
 RUN: FileCheck --input-file %t0 %s
 REQUIRES: arm-registered-target
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-kextbundle.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-kextbundle.test
similarity index 69%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-kextbundle.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-kextbundle.test
index 89194554e9cb8..60429f10b7b9c 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-kextbundle.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-kextbundle.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -d -m -no-show-raw-insn %p/Inputs/kextbundle.macho-aarch64 | FileCheck %s
+RUN: llvm-objdump -d -m --no-show-raw-insn %p/Inputs/kextbundle.macho-aarch64 | FileCheck %s
 
 CHECK: (__TEXT_EXEC,__text) section
 CHECK: _foo:
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-link-opt-hints.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-link-opt-hints.test
similarity index 72%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-link-opt-hints.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-link-opt-hints.test
index 932bc4fa83800..2f39aba92af97 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-link-opt-hints.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-link-opt-hints.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -m -link-opt-hints %p/Inputs/link-opt-hints.macho-aarch64 | FileCheck %s
+RUN: llvm-objdump -m --link-opt-hints %p/Inputs/link-opt-hints.macho-aarch64 | FileCheck %s
 
 CHECK: Linker optimiztion hints (8 total bytes)
 CHECK:     identifier 8 AdrpLdrGot
diff --git a/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test
new file mode 100644
index 0000000000000..cd40f0e849c5e
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-mrs.test
@@ -0,0 +1,3 @@
+RUN: llvm-objdump -d -m --no-show-raw-insn %p/Inputs/print-mrs.obj.macho-aarch64 | FileCheck %s
+
+CHECK: 0:  mrs x0, CPM_IOACC_CTL_EL3
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-print-thread-arm64_32.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-thread-arm64_32.test
similarity index 92%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-print-thread-arm64_32.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-thread-arm64_32.test
index 7bacb54ae80ff..16c719b261c6a 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-print-thread-arm64_32.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-thread-arm64_32.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -private-headers %p/Inputs/thread.macho-arm64_32 | FileCheck %s
+RUN: llvm-objdump --macho --private-headers %p/Inputs/thread.macho-arm64_32 | FileCheck %s
 
 CHECK: Load command 0
 CHECK:         cmd LC_UNIXTHREAD
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-print-thread.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-thread.test
similarity index 92%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-print-thread.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-thread.test
index 86f5569a03b7f..a76197620c856 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-print-thread.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-print-thread.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -private-headers %p/Inputs/thread.macho-aarch64 | FileCheck %s
+RUN: llvm-objdump --macho --private-headers %p/Inputs/thread.macho-aarch64 | FileCheck %s
 
 CHECK: Load command 0
 CHECK:         cmd LC_THREAD
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-private-headers.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-private-headers.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-private-headers.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-private-headers.test
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-reloc-addend.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-reloc-addend.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-reloc-addend.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-reloc-addend.test
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-symbolized-disassembly.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-symbolized-disassembly.test
similarity index 60%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-symbolized-disassembly.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-symbolized-disassembly.test
index 4c88b94396bb7..f26f06793f7e7 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-symbolized-disassembly.test
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-symbolized-disassembly.test
@@ -1,7 +1,7 @@
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.obj.macho-aarch64 | FileCheck %s -check-prefix=OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.exe.macho-aarch64 | FileCheck %s -check-prefix=EXE
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/ObjC.obj.macho-aarch64 | FileCheck %s -check-prefix=ObjC-OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/ObjC.exe.macho-aarch64 | FileCheck %s -check-prefix=ObjC-EXE
+// RUN: llvm-objdump -d -m --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.obj.macho-aarch64 | FileCheck %s --check-prefix=OBJ
+// RUN: llvm-objdump -d -m --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.exe.macho-aarch64 | FileCheck %s --check-prefix=EXE
+// RUN: llvm-objdump -d -m --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/ObjC.obj.macho-aarch64 | FileCheck %s --check-prefix=ObjC-OBJ
+// RUN: llvm-objdump -d -m --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/ObjC.exe.macho-aarch64 | FileCheck %s --check-prefix=ObjC-EXE
 
 OBJ: 000000000000001c	adrp	x0, L_.str@PAGE
 OBJ: 0000000000000020	add	x0, x0, L_.str@PAGEOFF
diff --git a/llvm/test/tools/llvm-objdump/AArch64/macho-zerofill.s b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-zerofill.s
similarity index 85%
rename from llvm/test/tools/llvm-objdump/AArch64/macho-zerofill.s
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/macho-zerofill.s
index dec8514e4425d..37141a0683ba1 100644
--- a/llvm/test/tools/llvm-objdump/AArch64/macho-zerofill.s
+++ b/llvm/test/tools/llvm-objdump/MachO/AArch64/macho-zerofill.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc < %s -triple aarch64-macho -filetype=obj | llvm-objdump -triple=aarch64-- -D - | FileCheck %s
+// RUN: llvm-mc < %s -triple aarch64-macho -filetype=obj | llvm-objdump --triple=aarch64-- -D - | FileCheck %s
 
 
 // Check that we don't print garbage when we dump zerofill sections.
diff --git a/llvm/test/tools/llvm-objdump/AArch64/pc-rel-targets.test b/llvm/test/tools/llvm-objdump/MachO/AArch64/pc-rel-targets.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/AArch64/pc-rel-targets.test
rename to llvm/test/tools/llvm-objdump/MachO/AArch64/pc-rel-targets.test
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/data-in-code.macho-arm b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/data-in-code.macho-arm
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/data-in-code.macho-arm
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/data-in-code.macho-arm
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/divs.macho-armv7s b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/divs.macho-armv7s
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/divs.macho-armv7s
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/divs.macho-armv7s
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/fat-armv7m.o b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/fat-armv7m.o
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/fat-armv7m.o
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/fat-armv7m.o
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/hello.exe.macho-arm b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/hello.exe.macho-arm
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/hello.exe.macho-arm
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/hello.exe.macho-arm
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/hello.obj.macho-arm b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/hello.obj.macho-arm
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/hello.obj.macho-arm
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/hello.obj.macho-arm
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/it-nv.o b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/it-nv.o
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/it-nv.o
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/it-nv.o
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/mh_dylib_header.macho-arm b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/mh_dylib_header.macho-arm
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/mh_dylib_header.macho-arm
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/mh_dylib_header.macho-arm
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/reloc-half.obj.macho-arm b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/reloc-half.obj.macho-arm
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/reloc-half.obj.macho-arm
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/reloc-half.obj.macho-arm
diff --git a/llvm/test/tools/llvm-objdump/ARM/Inputs/thumb.armv7m b/llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/thumb.armv7m
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/Inputs/thumb.armv7m
rename to llvm/test/tools/llvm-objdump/MachO/ARM/Inputs/thumb.armv7m
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-arch-armv7m-flag.test b/llvm/test/tools/llvm-objdump/MachO/ARM/arch-armv7m-flag.test
similarity index 51%
rename from llvm/test/tools/llvm-objdump/ARM/macho-arch-armv7m-flag.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/arch-armv7m-flag.test
index 6a19e30666642..c88ba9bc2f493 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-arch-armv7m-flag.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/arch-armv7m-flag.test
@@ -1,4 +1,4 @@
-@ RUN: llvm-objdump -macho -d -arch armv7m %p/Inputs/fat-armv7m.o | FileCheck %s
+@ RUN: llvm-objdump --macho -d --arch armv7m %p/Inputs/fat-armv7m.o | FileCheck %s
 @ CHECK: fat-armv7m.o:
 @ CHECK: (__TEXT,__text) section
 @ CHECK: foo:
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-arm-and-thumb.test b/llvm/test/tools/llvm-objdump/MachO/ARM/arm-and-thumb.test
similarity index 88%
rename from llvm/test/tools/llvm-objdump/ARM/macho-arm-and-thumb.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/arm-and-thumb.test
index fab64f549ef4d..57e8879701e19 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-arm-and-thumb.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/arm-and-thumb.test
@@ -1,5 +1,5 @@
 @ RUN: llvm-mc < %s -triple armv7-apple-darwin -filetype=obj | llvm-objdump -m -d - | FileCheck %s
-@ RUN: llvm-mc < %s -triple armv7-apple-darwin -filetype=obj | llvm-objdump -arch armv7 -m -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv7-apple-darwin -filetype=obj | llvm-objdump --arch armv7 -m -d - | FileCheck %s
 
 .thumb
 .thumb_func _t
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-data-in-code.test b/llvm/test/tools/llvm-objdump/MachO/ARM/data-in-code.test
similarity index 68%
rename from llvm/test/tools/llvm-objdump/ARM/macho-data-in-code.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/data-in-code.test
index c7a6da1d9504b..b2f2b3e09a20f 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-data-in-code.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/data-in-code.test
@@ -1,5 +1,5 @@
-RUN: llvm-objdump -m -data-in-code %p/Inputs/data-in-code.macho-arm | FileCheck %s
-RUN: llvm-objdump -m -data-in-code -non-verbose %p/Inputs/data-in-code.macho-arm | FileCheck %s -check-prefix=NON_VERBOSE
+RUN: llvm-objdump -m --data-in-code %p/Inputs/data-in-code.macho-arm | FileCheck %s
+RUN: llvm-objdump -m --data-in-code --non-verbose %p/Inputs/data-in-code.macho-arm | FileCheck %s --check-prefix=NON_VERBOSE
 
 CHECK: Data in code table (4 entries)
 CHECK: offset     length kind
diff --git a/llvm/test/tools/llvm-objdump/ARM/it-nv.txt b/llvm/test/tools/llvm-objdump/MachO/ARM/it-nv.txt
similarity index 80%
rename from llvm/test/tools/llvm-objdump/ARM/it-nv.txt
rename to llvm/test/tools/llvm-objdump/MachO/ARM/it-nv.txt
index 561f97bbb8b12..394ecb8156f24 100644
--- a/llvm/test/tools/llvm-objdump/ARM/it-nv.txt
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/it-nv.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -macho -d %p/Inputs/it-nv.o | FileCheck %s
+# RUN: llvm-objdump --macho -d %p/Inputs/it-nv.o | FileCheck %s
 
 # CHECK: ite	al @ unpredictable IT predicate sequence
 # CHECK: itet	al @ unpredictable IT predicate sequence
diff --git a/llvm/test/tools/llvm-objdump/MachO/ARM/lit.local.cfg b/llvm/test/tools/llvm-objdump/MachO/ARM/lit.local.cfg
new file mode 100644
index 0000000000000..236e1d3441665
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'ARM' in config.root.targets:
+    config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-mattr-arm.test b/llvm/test/tools/llvm-objdump/MachO/ARM/mattr-arm.test
similarity index 62%
rename from llvm/test/tools/llvm-objdump/ARM/macho-mattr-arm.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/mattr-arm.test
index 1b1714640c89a..824260b13981b 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-mattr-arm.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/mattr-arm.test
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple armv8-apple-darwin10 -mattr=+fp-armv8 -filetype=obj -o - | llvm-objdump -d -m -mattr=+fp-armv8 - | FileCheck %s
+@ RUN: llvm-mc < %s -triple armv8-apple-darwin10 -mattr=+fp-armv8 -filetype=obj -o - | llvm-objdump -d -m --mattr=+fp-armv8 - | FileCheck %s
 
 vcvtt.f64.f16 d3, s1
 
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-mcpu-arm.test b/llvm/test/tools/llvm-objdump/MachO/ARM/mcpu-arm.test
similarity index 66%
rename from llvm/test/tools/llvm-objdump/ARM/macho-mcpu-arm.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/mcpu-arm.test
index 7a3432d9e1a84..fed00c5fdb917 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-mcpu-arm.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/mcpu-arm.test
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc < %s -triple thumbv7-apple-darwin -mcpu=cortex-a7 -filetype=obj | llvm-objdump -triple thumbv7-apple-darwin10 -m -d -mcpu=cortex-a7 - | FileCheck %s
+@ RUN: llvm-mc < %s -triple thumbv7-apple-darwin -mcpu=cortex-a7 -filetype=obj | llvm-objdump --triple thumbv7-apple-darwin10 -m -d --mcpu=cortex-a7 - | FileCheck %s
 
 .thumb
 .thumb_func _t
diff --git a/llvm/test/tools/llvm-objdump/ARM/mh_dylib_header.test b/llvm/test/tools/llvm-objdump/MachO/ARM/mh_dylib_header.test
similarity index 51%
rename from llvm/test/tools/llvm-objdump/ARM/mh_dylib_header.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/mh_dylib_header.test
index 474080392c83f..c68d2ddffa7c9 100644
--- a/llvm/test/tools/llvm-objdump/ARM/mh_dylib_header.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/mh_dylib_header.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -d -macho %p/Inputs/mh_dylib_header.macho-arm
+RUN: llvm-objdump -d --macho %p/Inputs/mh_dylib_header.macho-arm
 
 CHECK: _t1:
 CHECK:     movw r0, #4133
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-nomcpu-armv7s.test b/llvm/test/tools/llvm-objdump/MachO/ARM/nomcpu-armv7s.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/macho-nomcpu-armv7s.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/nomcpu-armv7s.test
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-private-headers.test b/llvm/test/tools/llvm-objdump/MachO/ARM/private-headers.test
similarity index 99%
rename from llvm/test/tools/llvm-objdump/ARM/macho-private-headers.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/private-headers.test
index 53004c72e37cf..96b1759ed35fe 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-private-headers.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/private-headers.test
@@ -1,7 +1,7 @@
 // RUN: llvm-objdump -p %p/Inputs/hello.obj.macho-arm | FileCheck %s
 // RUN: llvm-objdump -p %p/Inputs/hello.exe.macho-arm \
 // RUN:     | FileCheck %s -check-prefix=EXE
-// RUN: llvm-objdump -macho -private-headers %p/Inputs/thumb.armv7m \
+// RUN: llvm-objdump --macho --private-headers %p/Inputs/thumb.armv7m \
 // RUN:     | FileCheck %s -check-prefix=THREAD
 
 CHECK: Mach header
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-reloc-half.test b/llvm/test/tools/llvm-objdump/MachO/ARM/reloc-half.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/macho-reloc-half.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/reloc-half.test
diff --git a/llvm/test/tools/llvm-objdump/MachO/ARM/symbolized-disassembly.test b/llvm/test/tools/llvm-objdump/MachO/ARM/symbolized-disassembly.test
new file mode 100644
index 0000000000000..730a000a373ff
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/symbolized-disassembly.test
@@ -0,0 +1,8 @@
+// RUN: llvm-objdump -d -m --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.obj.macho-arm | FileCheck %s --check-prefix=OBJ
+// RUN: llvm-objdump -d -m --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.exe.macho-arm | FileCheck %s --check-prefix=EXE
+
+OBJ: 00000006	40 f2 24 03 	movw	r3, :lower16:((54-14)-4)
+OBJ: 0000000a	c0 f2 00 03 	movt	r3, :upper16:((54-14)-4)
+OBJ: 00000024	ff f7 ec ff 	bl	_printf
+
+EXE: 0000bfa8	00 f0 28 e8 	blx	0xbffc @ symbol stub for: _printf
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-symbolized-subtractor.test b/llvm/test/tools/llvm-objdump/MachO/ARM/symbolized-subtractor.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/ARM/macho-symbolized-subtractor.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/symbolized-subtractor.test
diff --git a/llvm/test/tools/llvm-objdump/ARM/macho-v7m.test b/llvm/test/tools/llvm-objdump/MachO/ARM/v7m.test
similarity index 81%
rename from llvm/test/tools/llvm-objdump/ARM/macho-v7m.test
rename to llvm/test/tools/llvm-objdump/MachO/ARM/v7m.test
index 3ba1122056159..1f7bf69863673 100644
--- a/llvm/test/tools/llvm-objdump/ARM/macho-v7m.test
+++ b/llvm/test/tools/llvm-objdump/MachO/ARM/v7m.test
@@ -1,5 +1,5 @@
-@ RUN: llvm-mc < %s -triple thumbv7m-apple-macho -filetype=obj | llvm-objdump -macho -d - | FileCheck %s
-@ RUN: llvm-mc < %s -triple thumbv7em-apple-macho -filetype=obj | llvm-objdump -macho -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple thumbv7m-apple-macho -filetype=obj | llvm-objdump --macho -d - | FileCheck %s
+@ RUN: llvm-mc < %s -triple thumbv7em-apple-macho -filetype=obj | llvm-objdump --macho -d - | FileCheck %s
 
         .thumb
         .thumb_func _t
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/ObjC.exe.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/ObjC.exe.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/ObjC.exe.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/ObjC.exe.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/ObjC.obj.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/ObjC.obj.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/ObjC.obj.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/ObjC.obj.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.exe.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc1.32bit.exe.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.exe.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc1.32bit.exe.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.obj.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc1.32bit.obj.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc1.32bit.obj.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc1.32bit.obj.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.exe.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.32bit.exe.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.exe.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.32bit.exe.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.obj.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.32bit.obj.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.32bit.obj.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.32bit.obj.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.exe.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.64bit.exe.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.exe.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.64bit.exe.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.dylib-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.64bit.obj.dylib-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.dylib-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.64bit.obj.dylib-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.64bit.obj.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/Objc2.64bit.obj.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/Objc2.64bit.obj.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/codesig.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/codesig.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/codesig.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/codesig.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibLoadKinds.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibLoadKinds.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibLoadKinds.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibLoadKinds.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibModInit.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibModInit.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibModInit.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibModInit.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibRoutines.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibRoutines.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibRoutines.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibRoutines.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubClient.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubClient.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubClient.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubClient.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubFramework.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubFramework.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubFramework.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubFramework.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubLibrary.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubLibrary.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubLibrary.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubLibrary.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubUmbrella.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubUmbrella.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/dylibSubUmbrella.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/dylibSubUmbrella.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/exeThread.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/exeThread.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/exeThread.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/exeThread.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-fat b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-fat
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-fat
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-fat
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-fat.dwarf b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-fat.dwarf
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-fat.dwarf
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-fat.dwarf
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-thin b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-thin
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-thin
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-thin
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-thin.dwarf b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-thin.dwarf
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello-macho-thin.dwarf
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello-macho-thin.dwarf
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello.exe.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello.exe.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello.exe.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello.exe.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello.exe.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello.exe.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello.exe.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello.exe.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello.exe.stripped.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello.exe.stripped.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello.exe.stripped.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello.exe.stripped.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello.obj.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello.obj.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello.obj.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello.obj.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello.obj.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello.obj.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello.obj.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello.obj.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/hello_cpp.exe.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/hello_cpp.exe.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/hello_cpp.exe.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/hello_cpp.exe.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/kextbundle.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/kextbundle.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/kextbundle.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/kextbundle.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/linkerOption.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/linkerOption.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/linkerOption.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/linkerOption.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-disassemble-stab-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-disassemble-stab-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-disassemble-stab-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-disassemble-stab-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-bind-entry b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-bind-entry
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-bind-entry
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-bind-entry
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-linker-command b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-linker-command
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-linker-command
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-linker-command
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-reloc-section-index b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-reloc-section-index
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-reloc-section-index
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-reloc-section-index
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-indr b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-indr
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-indr
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-indr
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-indr-archive-universal b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-indr-archive-universal
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-indr-archive-universal
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-indr-archive-universal
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-lib_ordinal b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-lib_ordinal
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-lib_ordinal
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-lib_ordinal
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-nsect b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-nsect
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-nsect
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-nsect
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-nsect-archive b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-nsect-archive
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-nsect-archive
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-nsect-archive
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-strx b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-strx
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-strx
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-strx
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-strx-universal b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-strx-universal
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-invalid-symbol-strx-universal
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-invalid-symbol-strx-universal
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-multiple-text b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-multiple-text
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-multiple-text
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-multiple-text
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-preload-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-preload-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-preload-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-preload-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-universal-archive.x86_64.i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-universal-archive.x86_64.i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-universal-archive.x86_64.i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-universal-archive.x86_64.i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-universal.x86_64.i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-universal.x86_64.i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-universal.x86_64.i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-universal.x86_64.i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/macho-universal64.x86_64.i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/macho-universal64.x86_64.i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/macho-universal64.x86_64.i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/macho-universal64.x86_64.i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/00000031.a b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/00000031.a
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/00000031.a
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/00000031.a
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0001.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0001.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0001.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0001.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0006.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0006.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0006.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0006.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0010.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0010.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0010.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0010.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0040.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0040.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0040.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0040.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0080.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0080.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0080.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0080.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0261.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0261.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0261.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0261.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0337.macho b/llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0337.macho
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/malformed-machos/mem-crup-0337.macho
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/malformed-machos/mem-crup-0337.macho
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/nofirst-symbol.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/nofirst-symbol.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/nofirst-symbol.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/nofirst-symbol.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/note.macho-x86 b/llvm/test/tools/llvm-objdump/MachO/Inputs/note.macho-x86
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/note.macho-x86
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/note.macho-x86
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/objModInit.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/objModInit.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/objModInit.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/objModInit.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/stub-nosyms.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/stub-nosyms.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/stub-nosyms.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/stub-nosyms.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/stubbed.dylib.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/stubbed.dylib.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/stubbed.dylib.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/stubbed.dylib.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/thread.macho-i386 b/llvm/test/tools/llvm-objdump/MachO/Inputs/thread.macho-i386
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/thread.macho-i386
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/thread.macho-i386
diff --git a/llvm/test/tools/llvm-objdump/X86/Inputs/truncated-section.dylib.macho-x86_64 b/llvm/test/tools/llvm-objdump/MachO/Inputs/truncated-section.dylib.macho-x86_64
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/Inputs/truncated-section.dylib.macho-x86_64
rename to llvm/test/tools/llvm-objdump/MachO/Inputs/truncated-section.dylib.macho-x86_64
diff --git a/llvm/test/tools/llvm-objdump/MachO/LLVM-bundle.test b/llvm/test/tools/llvm-objdump/MachO/LLVM-bundle.test
index 778f77d31348c..9314f1126cec6 100644
--- a/llvm/test/tools/llvm-objdump/MachO/LLVM-bundle.test
+++ b/llvm/test/tools/llvm-objdump/MachO/LLVM-bundle.test
@@ -1,5 +1,5 @@
 # REQUIRES: xar
-# RUN: env ASAN_OPTIONS=detect_leaks=0 llvm-objdump -macho -archive-headers -section __LLVM,__bundle %p/Inputs/LLVM-bundle.macho-x86_64 | FileCheck %s
+# RUN: env ASAN_OPTIONS=detect_leaks=0 llvm-objdump --macho --archive-headers --section __LLVM,__bundle %p/Inputs/LLVM-bundle.macho-x86_64 | FileCheck %s
 
 # CHECK: For (__LLVM,__bundle) section: xar header
 # CHECK:                   magic XAR_HEADER_MAGIC
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-archive-headers.test b/llvm/test/tools/llvm-objdump/MachO/archive-headers.test
similarity index 90%
rename from llvm/test/tools/llvm-objdump/X86/macho-archive-headers.test
rename to llvm/test/tools/llvm-objdump/MachO/archive-headers.test
index 1253b46529b9b..946671a53dfdf 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-archive-headers.test
+++ b/llvm/test/tools/llvm-objdump/MachO/archive-headers.test
@@ -1,8 +1,8 @@
-RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -macho -archive-headers -arch all \
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 --macho --archive-headers --arch all \
 RUN: | FileCheck %s
-RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -macho -archive-headers -arch all -archive-member-offsets \
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 --macho --archive-headers --arch all --archive-member-offsets \
 RUN: | FileCheck %s -check-prefix=OFFSETS
-RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -macho -archive-headers -arch all -non-verbose \
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 --macho --archive-headers --arch all --non-verbose \
 RUN: | FileCheck %s -check-prefix=NON-VERBOSE
 
 # Note the date as printed by ctime(3) is time zone dependent and not checked.
diff --git a/llvm/test/tools/llvm-objdump/MachO/bad-bind.test b/llvm/test/tools/llvm-objdump/MachO/bad-bind.test
index fe089d4292903..d11c4fb883954 100644
--- a/llvm/test/tools/llvm-objdump/MachO/bad-bind.test
+++ b/llvm/test/tools/llvm-objdump/MachO/bad-bind.test
@@ -1,101 +1,101 @@
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-dylib-ordinal-uleb 2>&1 | FileCheck -check-prefix DYLIB-ORDINAL-ULEB %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-dylib-ordinal-uleb 2>&1 | FileCheck --check-prefix DYLIB-ORDINAL-ULEB %s
 DYLIB-ORDINAL-ULEB: macho-bind-dylib-ordinal-uleb': truncated or malformed object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB bad library ordinal: 355 (max 1) for opcode at: 0x0)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-dylib-ordinal-uleb-malformed-uleb128 2>&1 | FileCheck -check-prefix DYLIB-ORDINAL-ULEB-MALFORMED-ULEB128 %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-dylib-ordinal-uleb-malformed-uleb128 2>&1 | FileCheck --check-prefix DYLIB-ORDINAL-ULEB-MALFORMED-ULEB128 %s
 DYLIB-ORDINAL-ULEB-MALFORMED-ULEB128: macho-bind-dylib-ordinal-uleb-malformed-uleb128': truncated or malformed object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB malformed uleb128, extends past end for opcode at: 0x0)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-dylib-ordinal-uleb-too-big 2>&1 | FileCheck -check-prefix DYLIB-ORDINAL-ULEB-TOO-BIG %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-dylib-ordinal-uleb-too-big 2>&1 | FileCheck --check-prefix DYLIB-ORDINAL-ULEB-TOO-BIG %s
 DYLIB-ORDINAL-ULEB-TOO-BIG: macho-bind-dylib-ordinal-uleb-too-big': truncated or malformed object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB uleb128 too big for uint64 for opcode at: 0x0)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-dylib-special-imm 2>&1 | FileCheck -check-prefix DYLIB-SPECIAL-IMM %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-dylib-special-imm 2>&1 | FileCheck --check-prefix DYLIB-SPECIAL-IMM %s
 DYLIB-SPECIAL-IMM: macho-bind-dylib-special-imm': truncated or malformed object (for BIND_OPCODE_SET_DYLIB_SPECIAL_IMM unknown special ordinal: -5 for opcode at: 0x0)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-set-symbol 2>&1 | FileCheck -check-prefix BIND-SET-SYMBOL %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-set-symbol 2>&1 | FileCheck --check-prefix BIND-SET-SYMBOL %s
 BIND-SET-SYMBOL: macho-bind-set-symbol': truncated or malformed object (for BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM symbol name extends past opcodes for opcode at: 0x2)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-set-type-imm 2>&1 | FileCheck -check-prefix SET-TYPE-IMM %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-set-type-imm 2>&1 | FileCheck --check-prefix SET-TYPE-IMM %s
 SET-TYPE-IMM: macho-bind-set-type-imm': truncated or malformed object (for BIND_OPCODE_SET_TYPE_IMM bad bind type: 5 for opcode at: 0x14)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-set-addend-sleb 2>&1 | FileCheck -check-prefix SET-ADDEND-SLEB %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-set-addend-sleb 2>&1 | FileCheck --check-prefix SET-ADDEND-SLEB %s
 SET-ADDEND-SLEB: macho-bind-set-addend-sleb': truncated or malformed object (for BIND_OPCODE_SET_ADDEND_SLEB malformed sleb128, extends past end for opcode at: 0x14)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-seg-too-big 2>&1 | FileCheck -check-prefix SEG-TOO-BIG %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-seg-too-big 2>&1 | FileCheck --check-prefix SEG-TOO-BIG %s
 SEG-TOO-BIG: macho-bind-seg-too-big': truncated or malformed object (for BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad segIndex (too large) for opcode at: 0x15)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-segoff-too-big 2>&1 | FileCheck -check-prefix SEGOFF-TOO-BIG %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-segoff-too-big 2>&1 | FileCheck --check-prefix SEGOFF-TOO-BIG %s
 SEGOFF-TOO-BIG: macho-bind-segoff-too-big': truncated or malformed object (for BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad offset, not in section for opcode at: 0x15)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-add_addr_uleb 2>&1 | FileCheck -check-prefix ADD_ADDR_ULEB %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-add_addr_uleb 2>&1 | FileCheck --check-prefix ADD_ADDR_ULEB %s
 ADD_ADDR_ULEB: macho-bind-add_addr_uleb': truncated or malformed object (for BIND_OPCODE_ADD_ADDR_ULEB bad offset, not in section for opcode at: 0x17)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-do-bind-no-segIndex 2>&1 | FileCheck -check-prefix BIND-NO-SEGINDEX %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-do-bind-no-segIndex 2>&1 | FileCheck --check-prefix BIND-NO-SEGINDEX %s
 BIND-NO-SEGINDEX: macho-bind-do-bind-no-segIndex': truncated or malformed object (for BIND_OPCODE_DO_BIND missing preceding *_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB for opcode at: 0x15)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-bind-add-addr-uleb 2>&1 | FileCheck -check-prefix ADD-ADDR-ULEB %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-bind-add-addr-uleb 2>&1 | FileCheck --check-prefix ADD-ADDR-ULEB %s
 ADD-ADDR-ULEB: macho-bind-bind-add-addr-uleb': truncated or malformed object (for BIND_OPCODE_ADD_ADDR_ULEB (after adding ULEB) bad offset, not in section for opcode at: 0x18)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-add-addr-imm-scaled 2>&1 | FileCheck -check-prefix ADD-ADDR-IMM-SCALED %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-add-addr-imm-scaled 2>&1 | FileCheck --check-prefix ADD-ADDR-IMM-SCALED %s
 ADD-ADDR-IMM-SCALED: macho-bind-add-addr-imm-scaled': truncated or malformed object (for BIND_OPCODE_DO_BIND_ADD_ADDR_IMM_SCALED bad offset, not in section for opcode at: 0x17)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-uleb-times-skipping-uleb 2>&1 | FileCheck -check-prefix ULEB-TIMES-SKIPPING-ULEB %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-uleb-times-skipping-uleb 2>&1 | FileCheck --check-prefix ULEB-TIMES-SKIPPING-ULEB %s
 ULEB-TIMES-SKIPPING-ULEB: macho-bind-uleb-times-skipping-uleb': truncated or malformed object (for BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB bad offset, not in section for opcode at: 0x17)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-do-bind-no-symbol 2>&1 | FileCheck -check-prefix DO-BIND-NO-SYMBOL %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-do-bind-no-symbol 2>&1 | FileCheck --check-prefix DO-BIND-NO-SYMBOL %s
 DO-BIND-NO-SYMBOL: macho-do-bind-no-symbol': truncated or malformed object (for BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB missing preceding BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM for opcode at: 0x5)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-do-bind-no-dylib-ordinal 2>&1 | FileCheck -check-prefix DO-BIND-NO-DYLIB-ORDINAL %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-do-bind-no-dylib-ordinal 2>&1 | FileCheck --check-prefix DO-BIND-NO-DYLIB-ORDINAL %s
 DO-BIND-NO-DYLIB-ORDINAL: macho-do-bind-no-dylib-ordinal': truncated or malformed object (for BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB missing preceding BIND_OPCODE_SET_DYLIB_ORDINAL_* for opcode at: 0x15)
 
-RUN: not llvm-objdump -macho -bind %p/Inputs/macho-bind-bad-opcode-value 2>&1 | FileCheck -check-prefix BAD-OPCODE-VALUE %s
+RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-bad-opcode-value 2>&1 | FileCheck --check-prefix BAD-OPCODE-VALUE %s
 BAD-OPCODE-VALUE: macho-bind-bad-opcode-value': truncated or malformed object (bad bind info (bad opcode value 0xd0 for opcode at: 0x18)
 
-RUN: not llvm-objdump -macho -lazy-bind %p/Inputs/macho-lazy-do_bind_add_addr_uleb 2>&1 | FileCheck -check-prefix LAZY_DO_BIND_ADD_ADDR_ULEB %s
+RUN: not llvm-objdump --macho --lazy-bind %p/Inputs/macho-lazy-do_bind_add_addr_uleb 2>&1 | FileCheck --check-prefix LAZY_DO_BIND_ADD_ADDR_ULEB %s
 LAZY_DO_BIND_ADD_ADDR_ULEB: macho-lazy-do_bind_add_addr_uleb': truncated or malformed object (BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB not allowed in lazy bind table for opcode at: 0xc)
 
-RUN: not llvm-objdump -macho -lazy-bind %p/Inputs/macho-lazy-do-bind-add-addr-imm-scaled 2>&1 | FileCheck -check-prefix LAZY-DO-BIND-ADD-ADDR-IMM-SCALED %s
+RUN: not llvm-objdump --macho --lazy-bind %p/Inputs/macho-lazy-do-bind-add-addr-imm-scaled 2>&1 | FileCheck --check-prefix LAZY-DO-BIND-ADD-ADDR-IMM-SCALED %s
 LAZY-DO-BIND-ADD-ADDR-IMM-SCALED: macho-lazy-do-bind-add-addr-imm-scaled': truncated or malformed object (BIND_OPCODE_DO_BIND_ADD_ADDR_IMM_SCALED not allowed in lazy bind table for opcode at: 0xc)
 
-RUN: not llvm-objdump -macho -lazy-bind %p/Inputs/macho-lazy-do-bind-uleb-times-skipping-uleb 2>&1 | FileCheck -check-prefix LAZY-DO-BIND-ULEB-TIMES-SKIPPING-ULEB %s
+RUN: not llvm-objdump --macho --lazy-bind %p/Inputs/macho-lazy-do-bind-uleb-times-skipping-uleb 2>&1 | FileCheck --check-prefix LAZY-DO-BIND-ULEB-TIMES-SKIPPING-ULEB %s
 LAZY-DO-BIND-ULEB-TIMES-SKIPPING-ULEB: macho-lazy-do-bind-uleb-times-skipping-uleb': truncated or malformed object (BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB not allowed in lazy bind table for opcode at: 0xc)
 
-RUN: not llvm-objdump -macho -weak-bind %p/Inputs/macho-weak-bind-set-dylib-ordinal-imm 2>&1 | FileCheck -check-prefix WEAK-BIND-SET-DYLIB-ORDINAL-IMM %s
+RUN: not llvm-objdump --macho --weak-bind %p/Inputs/macho-weak-bind-set-dylib-ordinal-imm 2>&1 | FileCheck --check-prefix WEAK-BIND-SET-DYLIB-ORDINAL-IMM %s
 WEAK-BIND-SET-DYLIB-ORDINAL-IMM: macho-weak-bind-set-dylib-ordinal-imm': truncated or malformed object (BIND_OPCODE_SET_DYLIB_ORDINAL_IMM not allowed in weak bind table for opcode at: 0x2)
 
-RUN: not llvm-objdump -macho -weak-bind %p/Inputs/macho-weak-bind-set-dylib-ordinal-uleb 2>&1 | FileCheck -check-prefix WEAK-BIND-SET-DYLIB-ORDINAL-ULEB %s
+RUN: not llvm-objdump --macho --weak-bind %p/Inputs/macho-weak-bind-set-dylib-ordinal-uleb 2>&1 | FileCheck --check-prefix WEAK-BIND-SET-DYLIB-ORDINAL-ULEB %s
 WEAK-BIND-SET-DYLIB-ORDINAL-ULEB: macho-weak-bind-set-dylib-ordinal-uleb': truncated or malformed object (BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB not allowed in weak bind table for opcode at: 0x2)
 
-RUN: not llvm-objdump -macho -weak-bind %p/Inputs/macho-weak-bind-set-dylib-special-imm 2>&1 | FileCheck -check-prefix WEAK-BIND-SET-DYLIB-SPECIAL-IMM %s
+RUN: not llvm-objdump --macho --weak-bind %p/Inputs/macho-weak-bind-set-dylib-special-imm 2>&1 | FileCheck --check-prefix WEAK-BIND-SET-DYLIB-SPECIAL-IMM %s
 WEAK-BIND-SET-DYLIB-SPECIAL-IMM: macho-weak-bind-set-dylib-special-imm': truncated or malformed object (BIND_OPCODE_SET_DYLIB_SPECIAL_IMM not allowed in weak bind table for opcode at: 0x2)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-set-type-imm 2>&1 | FileCheck -check-prefix REBASE-SET-TYPE-IMM %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-set-type-imm 2>&1 | FileCheck --check-prefix REBASE-SET-TYPE-IMM %s
 REBASE-SET-TYPE-IMM: macho-rebase-set-type-imm': truncated or malformed object (for REBASE_OPCODE_SET_TYPE_IMM bad bind type: 5 for opcode at: 0x0)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-uleb-malformed-uleb128 2>&1 | FileCheck -check-prefix REBASE-ULEB-MALFORMED-ULEB128 %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-uleb-malformed-uleb128 2>&1 | FileCheck --check-prefix REBASE-ULEB-MALFORMED-ULEB128 %s
 REBASE-ULEB-MALFORMED-ULEB128: macho-rebase-uleb-malformed-uleb128': truncated or malformed object (for REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB malformed uleb128, extends past end for opcode at: 0x1)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-seg-too-big 2>&1 | FileCheck -check-prefix REBASE-SEG-TOO-BIG %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-seg-too-big 2>&1 | FileCheck --check-prefix REBASE-SEG-TOO-BIG %s
 REBASE-SEG-TOO-BIG: macho-rebase-seg-too-big': truncated or malformed object (for REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad segIndex (too large) for opcode at: 0x1)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-segoff-too-big 2>&1 | FileCheck -check-prefix REBASE-SEGOFF-TOO-BIG %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-segoff-too-big 2>&1 | FileCheck --check-prefix REBASE-SEGOFF-TOO-BIG %s
 REBASE-SEGOFF-TOO-BIG: macho-rebase-segoff-too-big': truncated or malformed object (for REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad offset, not in section for opcode at: 0x1)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-add-addr-uleb 2>&1 | FileCheck -check-prefix REBASE-ADD-ADDR-ULEB %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-add-addr-uleb 2>&1 | FileCheck --check-prefix REBASE-ADD-ADDR-ULEB %s
 REBASE-ADD-ADDR-ULEB: macho-rebase-add-addr-uleb': truncated or malformed object (for REBASE_OPCODE_ADD_ADDR_ULEB bad offset, not in section for opcode at: 0x3)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-add-addr-imm-scaled 2>&1 | FileCheck -check-prefix REBASE-ADD-ADDR-IMM-SCALED %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-add-addr-imm-scaled 2>&1 | FileCheck --check-prefix REBASE-ADD-ADDR-IMM-SCALED %s
 REBASE-ADD-ADDR-IMM-SCALED: macho-rebase-add-addr-imm-scaled': truncated or malformed object (for REBASE_OPCODE_ADD_ADDR_IMM_SCALED bad offset, not in section for opcode at: 0x3)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-imm-times 2>&1 | FileCheck -check-prefix REBASE-IMM-TIMES %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-imm-times 2>&1 | FileCheck --check-prefix REBASE-IMM-TIMES %s
 REBASE-IMM-TIMES: macho-rebase-imm-times': truncated or malformed object (for REBASE_OPCODE_DO_REBASE_IMM_TIMES bad offset, not in section for opcode at: 0x3)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-uleb-times 2>&1 | FileCheck -check-prefix REBASE-ULEB-TIMES %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-uleb-times 2>&1 | FileCheck --check-prefix REBASE-ULEB-TIMES %s
 REBASE-ULEB-TIMES: macho-rebase-uleb-times': truncated or malformed object (for REBASE_OPCODE_DO_REBASE_ULEB_TIMES bad offset, not in section for opcode at: 0x3)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-add-addr-uleb-too-big 2>&1 | FileCheck -check-prefix REBASE-ADD-ADDR-ULEB-TOO-BIG %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-add-addr-uleb-too-big 2>&1 | FileCheck --check-prefix REBASE-ADD-ADDR-ULEB-TOO-BIG %s
 REBASE-ADD-ADDR-ULEB-TOO-BIG: macho-rebase-add-addr-uleb-too-big': truncated or malformed object (for REBASE_OPCODE_DO_REBASE_IMM_TIMES bad offset, not in section for opcode at: 0x6)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-uleb-times-skipping-uleb 2>&1 | FileCheck -check-prefix REBASE-ULEB-TIMES-SKIPPING-ULEB %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-uleb-times-skipping-uleb 2>&1 | FileCheck --check-prefix REBASE-ULEB-TIMES-SKIPPING-ULEB %s
 REBASE-ULEB-TIMES-SKIPPING-ULEB: macho-rebase-uleb-times-skipping-uleb': truncated or malformed object (for REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB bad offset, not in section for opcode at: 0x3)
 
-RUN: not llvm-objdump -macho -rebase %p/Inputs/macho-rebase-bad-opcode-value 2>&1 | FileCheck -check-prefix REBASE-BAD-OPCODE-VALUE %s
+RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-bad-opcode-value 2>&1 | FileCheck --check-prefix REBASE-BAD-OPCODE-VALUE %s
 REBASE-BAD-OPCODE-VALUE: macho-rebase-bad-opcode-value': truncated or malformed object (bad rebase info (bad opcode value 0xd0 for opcode at: 0x4)
diff --git a/llvm/test/tools/llvm-objdump/MachO/bad-ordinal.test b/llvm/test/tools/llvm-objdump/MachO/bad-ordinal.test
index fb49f77f0751d..d289805842ec9 100644
--- a/llvm/test/tools/llvm-objdump/MachO/bad-ordinal.test
+++ b/llvm/test/tools/llvm-objdump/MachO/bad-ordinal.test
@@ -1,4 +1,4 @@
-# RUN: not llvm-objdump -macho -lazy-bind %p/Inputs/bad-ordinal.macho-x86_64 \
+# RUN: not llvm-objdump --macho --lazy-bind %p/Inputs/bad-ordinal.macho-x86_64 \
 # RUN: 2>&1 | FileCheck %s 
 
 # CHECK: bad-ordinal.macho-x86_64': truncated or malformed object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB bad library ordinal: 2 (max 1) for opcode at: 0x2)
diff --git a/llvm/test/tools/llvm-objdump/MachO/bad-trie.test b/llvm/test/tools/llvm-objdump/MachO/bad-trie.test
index 9477f228aaaf7..69e572c3c0297 100644
--- a/llvm/test/tools/llvm-objdump/MachO/bad-trie.test
+++ b/llvm/test/tools/llvm-objdump/MachO/bad-trie.test
@@ -1,35 +1,35 @@
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-bad-kind 2>&1 | FileCheck -check-prefix BAD_KIND %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-bad-kind 2>&1 | FileCheck --check-prefix BAD_KIND %s 
 BAD_KIND: macho-trie-bad-kind': truncated or malformed object (unsupported exported symbol kind: 3 in flags: 0x13 in export trie data at node: 0x53)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-bad-export-info-malformed-uleb128 2>&1 | FileCheck -check-prefix MALFORMED_ULEB128 %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-bad-export-info-malformed-uleb128 2>&1 | FileCheck --check-prefix MALFORMED_ULEB128 %s 
 MALFORMED_ULEB128: macho-trie-bad-export-info-malformed-uleb128': truncated or malformed object (export info size malformed uleb128, extends past end in export trie data at node: 0x5a)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-bad-export-info-malformed-uleb128_too_big 2>&1 | FileCheck -check-prefix MALFORMED_ULEB128_TOO_BIG %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-bad-export-info-malformed-uleb128_too_big 2>&1 | FileCheck --check-prefix MALFORMED_ULEB128_TOO_BIG %s 
 MALFORMED_ULEB128_TOO_BIG: macho-trie-bad-export-info-malformed-uleb128_too_big': truncated or malformed object (export info size uleb128 too big for uint64 in export trie data at node: 0x5a)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-export-info-size-too-big 2>&1 | FileCheck -check-prefix EXPORT_INFO_SIZE_TOO_BIG %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-export-info-size-too-big 2>&1 | FileCheck --check-prefix EXPORT_INFO_SIZE_TOO_BIG %s 
 EXPORT_INFO_SIZE_TOO_BIG: macho-trie-export-info-size-too-big': truncated or malformed object (export info size: 0x1234 in export trie data at node: 0x33 too big and extends past end of trie data)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-children-count-byte 2>&1 | FileCheck -check-prefix CHILDREN_COUNT_BYTE %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-children-count-byte 2>&1 | FileCheck --check-prefix CHILDREN_COUNT_BYTE %s 
 CHILDREN_COUNT_BYTE: macho-trie-children-count-byte': truncated or malformed object (byte for count of childern in export trie data at node: 0x5 extends past end of trie data)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-import-name-start 2>&1 | FileCheck -check-prefix IMPORT_NAME_START %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-import-name-start 2>&1 | FileCheck --check-prefix IMPORT_NAME_START %s 
 IMPORT_NAME_START: macho-trie-import-name-start': truncated or malformed object (import name of re-export in export trie data at node: 0x33 starts past end of trie data)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-import-name-end 2>&1 | FileCheck -check-prefix IMPORT_NAME_END %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-import-name-end 2>&1 | FileCheck --check-prefix IMPORT_NAME_END %s 
 IMPORT_NAME_END: macho-trie-import-name-end': truncated or malformed object (import name of re-export in export trie data at node: 0x33 extends past end of trie data)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-edge-string-end 2>&1 | FileCheck -check-prefix EDGE_STRING_END %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-edge-string-end 2>&1 | FileCheck --check-prefix EDGE_STRING_END %s 
 EDGE_STRING_END: macho-trie-edge-string-end': truncated or malformed object (edge sub-string in export trie data at node: 0x42 for child #0 extends past end of trie data)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-not-export-node 2>&1 | FileCheck -check-prefix NOT_EXPORT_NODE %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-not-export-node 2>&1 | FileCheck --check-prefix NOT_EXPORT_NODE %s 
 NOT_EXPORT_NODE: macho-trie-not-export-node': truncated or malformed object (node is not an export node in export trie data at node: 0x5a)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-node-loop 2>&1 | FileCheck -check-prefix LOOP_OF_CHILDERN %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-node-loop 2>&1 | FileCheck --check-prefix LOOP_OF_CHILDERN %s 
 LOOP_OF_CHILDERN: macho-trie-node-loop': truncated or malformed object (loop in childern in export trie data at node: 0x42 back to node: 0x5)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-trie-bad-library-ordinal 2>&1 | FileCheck -check-prefix BAD_LIBRARY_ORDINAL %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-trie-bad-library-ordinal 2>&1 | FileCheck --check-prefix BAD_LIBRARY_ORDINAL %s 
 BAD_LIBRARY_ORDINAL: macho-trie-bad-library-ordinal': truncated or malformed object (bad library ordinal: 69 (max 3) in export trie data at node: 0x33)
 
-RUN: not llvm-objdump -macho -exports-trie %p/Inputs/macho-inconsistant-export 2>&1 | FileCheck -check-prefix INCONSISTANT_EXPORT_SIZE %s 
+RUN: not llvm-objdump --macho --exports-trie %p/Inputs/macho-inconsistant-export 2>&1 | FileCheck --check-prefix INCONSISTANT_EXPORT_SIZE %s 
 INCONSISTANT_EXPORT_SIZE: macho-inconsistant-export': truncated or malformed object (inconsistant export info size: 0x9 where actual size was: 0x5 in export trie data at node: 0x53)
diff --git a/llvm/test/tools/llvm-objdump/MachO/bind.test b/llvm/test/tools/llvm-objdump/MachO/bind.test
index 5527bfa83638d..3d36785f23a1e 100644
--- a/llvm/test/tools/llvm-objdump/MachO/bind.test
+++ b/llvm/test/tools/llvm-objdump/MachO/bind.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -macho -bind %p/Inputs/bind.macho-x86_64 \
+# RUN: llvm-objdump --macho --bind %p/Inputs/bind.macho-x86_64 \
 # RUN:   | FileCheck %s  
 
 
diff --git a/llvm/test/tools/llvm-objdump/MachO/bind2.test b/llvm/test/tools/llvm-objdump/MachO/bind2.test
index 2eee2fcb60b38..edf83591a249c 100644
--- a/llvm/test/tools/llvm-objdump/MachO/bind2.test
+++ b/llvm/test/tools/llvm-objdump/MachO/bind2.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -macho -bind %p/Inputs/bind2.macho-x86_64 | FileCheck %s  
+# RUN: llvm-objdump --macho --bind %p/Inputs/bind2.macho-x86_64 | FileCheck %s  
 
 # CHECK: __DATA   __data             0x00001008 pointer         0 libSystem        _malloc
 # CHECK: __DATA   __data             0x00001050 pointer         0 libSystem        _malloc
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-build-version.yaml b/llvm/test/tools/llvm-objdump/MachO/build-version.yaml
similarity index 94%
rename from llvm/test/tools/llvm-objdump/X86/macho-build-version.yaml
rename to llvm/test/tools/llvm-objdump/MachO/build-version.yaml
index ef70774b56a5f..a7e7f64e4e5a4 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-build-version.yaml
+++ b/llvm/test/tools/llvm-objdump/MachO/build-version.yaml
@@ -1,4 +1,4 @@
-# RUN: yaml2obj %s | llvm-objdump -macho -private-headers - | FileCheck %s
+# RUN: yaml2obj %s | llvm-objdump --macho --private-headers - | FileCheck %s
 
 --- !mach-o
 FileHeader:
diff --git a/llvm/test/tools/llvm-objdump/MachO/compact-unwind-i386.test b/llvm/test/tools/llvm-objdump/MachO/compact-unwind-i386.test
index 9a14c2044c017..dc65ea117205e 100644
--- a/llvm/test/tools/llvm-objdump/MachO/compact-unwind-i386.test
+++ b/llvm/test/tools/llvm-objdump/MachO/compact-unwind-i386.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -unwind-info %p/Inputs/compact-unwind.macho-i386 | FileCheck %s
+# RUN: llvm-objdump --unwind-info %p/Inputs/compact-unwind.macho-i386 | FileCheck %s
 
 # CHECK: Contents of __compact_unwind section:
 # CHECK:   Entry at offset 0x0:
diff --git a/llvm/test/tools/llvm-objdump/MachO/compact-unwind-x86_64.test b/llvm/test/tools/llvm-objdump/MachO/compact-unwind-x86_64.test
index 852800d357f2c..6a81f5e104f15 100644
--- a/llvm/test/tools/llvm-objdump/MachO/compact-unwind-x86_64.test
+++ b/llvm/test/tools/llvm-objdump/MachO/compact-unwind-x86_64.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -unwind-info %p/Inputs/compact-unwind.macho-x86_64 | FileCheck %s
+# RUN: llvm-objdump --unwind-info %p/Inputs/compact-unwind.macho-x86_64 | FileCheck %s
 
 # CHECK: Contents of __compact_unwind section:
 # CHECK:   Entry at offset 0x0:
diff --git a/llvm/test/tools/llvm-objdump/MachO/cstring-dump.test b/llvm/test/tools/llvm-objdump/MachO/cstring-dump.test
new file mode 100644
index 0000000000000..7dd9d766b197a
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/cstring-dump.test
@@ -0,0 +1,18 @@
+RUN: llvm-objdump --macho --section __TEXT,__cstring %p/Inputs/hello.obj.macho-x86_64 2>&1 | FileCheck %s --implicit-check-not="warning:"
+RUN: llvm-objdump --macho --section __TEXT,__cstring --no-leading-addr %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s --check-prefix=NO_ADDR --implicit-check-not="warning:"
+RUN: llvm-objdump --macho --section __TEXT,__cstring --no-leading-headers %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s --check-prefix=NO_HEADERS --implicit-check-not="warning:"
+RUN: llvm-objdump --macho --section __TEXT,__cstring --non-verbose %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s --check-prefix=NON_VERBOSE --implicit-check-not="warning:"
+
+CHECK: Contents of (__TEXT,__cstring) section
+CHECK-NEXT: 000000000000003b  Hello world\n
+
+NO_ADDR: Contents of (__TEXT,__cstring) section
+NO_ADDR: Hello world\n
+NO_ADDR-NOT: 000000000000003b
+
+NO_HEADERS-NOT: Inputs/hello.obj.macho-x86_64:
+NO_HEADERS-NOT: Contents of (__TEXT,__cstring) section
+NO_HEADERS: 000000000000003b	Hello world\n
+
+NON_VERBOSE: Contents of (__TEXT,__cstring) section
+NON_VERBOSE: 000000000000003b	48 65 6c 6c 6f 20 77 6f 72 6c 64 0a 00
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-data-in-code.ll b/llvm/test/tools/llvm-objdump/MachO/data-in-code.ll
similarity index 84%
rename from llvm/test/tools/llvm-objdump/X86/macho-data-in-code.ll
rename to llvm/test/tools/llvm-objdump/MachO/data-in-code.ll
index 57877da09f35d..de78203c98cf5 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-data-in-code.ll
+++ b/llvm/test/tools/llvm-objdump/MachO/data-in-code.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple x86_64-apple-darwin -filetype=obj -O0 %s -o %t.o
-; RUN: llvm-objdump -macho -disassemble -no-show-raw-insn %t.o | FileCheck %s
+; RUN: llc --mtriple x86_64-apple-darwin -filetype=obj -O0 %s -o %t.o
+; RUN: llvm-objdump --macho -d --no-show-raw-insn %t.o | FileCheck %s
 
 ; CHECK: .long {{[0-9]+}}	@ KIND_JUMP_TABLE32
 ; CHECK: .long {{[0-9]+}}	@ KIND_JUMP_TABLE32
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-dis-no-leading-addr.test b/llvm/test/tools/llvm-objdump/MachO/dis-no-leading-addr.test
similarity index 81%
rename from llvm/test/tools/llvm-objdump/X86/macho-dis-no-leading-addr.test
rename to llvm/test/tools/llvm-objdump/MachO/dis-no-leading-addr.test
index df4618dc4681e..57d328ea3a25c 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-dis-no-leading-addr.test
+++ b/llvm/test/tools/llvm-objdump/MachO/dis-no-leading-addr.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -m -d %p/Inputs/hello.obj.macho-x86_64 -no-show-raw-insn -print-imm-hex -no-leading-addr | FileCheck %s
+# RUN: llvm-objdump --macho -d %p/Inputs/hello.obj.macho-x86_64 --no-show-raw-insn --print-imm-hex --no-leading-addr | FileCheck %s
 
 # CHECK: (__TEXT,__text) section
 # CHECK: _main:
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-dis-symname.test b/llvm/test/tools/llvm-objdump/MachO/dis-symname.test
similarity index 61%
rename from llvm/test/tools/llvm-objdump/X86/macho-dis-symname.test
rename to llvm/test/tools/llvm-objdump/MachO/dis-symname.test
index 9e4f2e3c71f28..9c7a341e33b86 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-dis-symname.test
+++ b/llvm/test/tools/llvm-objdump/MachO/dis-symname.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -m -d %p/Inputs/exeThread.macho-x86_64 -dis-symname start -no-show-raw-insn -full-leading-addr -print-imm-hex | FileCheck %s
+# RUN: llvm-objdump --macho -d %p/Inputs/exeThread.macho-x86_64 --dis-symname start --no-show-raw-insn --full-leading-addr --print-imm-hex | FileCheck %s
 
 # CHECK: (__TEXT,__text) section
 # CHECK: start:
@@ -18,8 +18,8 @@
 # CHECK-NOT: 0000000100000d22
 # CHECK-NOT: _main:
 
-# not RUN: llvm-objdump -m -d %p/Inputs/exeThread.macho-x86_64 -dis-symname _environ 2>&1 | FileCheck -check-prefix BAD-SYMAME-1 %s
+# not RUN: llvm-objdump --macho -d %p/Inputs/exeThread.macho-x86_64 --dis-symname _environ 2>&1 | FileCheck --check-prefix BAD-SYMAME-1 %s
 BAD-SYMAME-1: -dis-symname: _environ not in the section
 
-# not RUN: llvm-objdump -m -d %p/Inputs/exeThread.macho-x86_64 -dis-symname __mh_execute_header 2>&1 | FileCheck -check-prefix BAD-SYMAME-2 %s
+# not RUN: llvm-objdump --macho -d %p/Inputs/exeThread.macho-x86_64 --dis-symname __mh_execute_header 2>&1 | FileCheck --check-prefix BAD-SYMAME-2 %s
 BAD-SYMAME-2: -dis-symname: __mh_execute_header not in any section
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-all.test b/llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
similarity index 82%
rename from llvm/test/tools/llvm-objdump/X86/macho-disassemble-all.test
rename to llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
index ce22d740087d3..05d4a5d9ca9e6 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-all.test
+++ b/llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
@@ -1,4 +1,4 @@
-// RUN: llvm-objdump -m -d -full-leading-addr -print-imm-hex -no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s -check-prefix=TEXT
+// RUN: llvm-objdump --macho -d --full-leading-addr --print-imm-hex --no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s --check-prefix=TEXT
 
 TEXT:      (__TEXT,__text) section
 TEXT_NEXT: _main:
@@ -12,7 +12,7 @@ TEXT_NEXT: 0000000100000f76	addq	$0x10, %rsp
 TEXT_NEXT: 0000000100000f7a	popq	%rbp
 TEXT_NEXT: 0000000100000f7b	retq
 
-// RUN: llvm-objdump -m -D -full-leading-addr -print-imm-hex -no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s -check-prefix=ALL
+// RUN: llvm-objdump --macho -D --full-leading-addr --print-imm-hex --no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s --check-prefix=ALL
 
 ALL:      (__TEXT,__text) section
 ALL_NEXT: _main:
diff --git a/llvm/test/tools/llvm-objdump/MachO/disassemble-g-dsym.test b/llvm/test/tools/llvm-objdump/MachO/disassemble-g-dsym.test
new file mode 100644
index 0000000000000..5481e1f367346
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/disassemble-g-dsym.test
@@ -0,0 +1,17 @@
+// RUN: dsymutil -f -oso-prepend-path=%p/../../dsymutil/ %p/../../dsymutil/Inputs/basic.macho.x86_64 -o %t1.dSYM
+// RUN: llvm-objdump -d -g --dsym=%t1.dSYM %p/../../dsymutil/Inputs/basic.macho.x86_64 >%t0
+// RUN: llvm-objdump -dg --dsym=%t1.dSYM %p/../../dsymutil/Inputs/basic.macho.x86_64 >%t1
+// RUN: cmp %t0 %t1
+// RUN: FileCheck --input-file %t0 %s
+
+CHECK: Disassembly of section __TEXT,__text:
+
+// RUN: llvm-objdump --macho -d -g --dsym %p/Inputs/hello-macho-fat.dwarf %p/Inputs/hello-macho-fat | FileCheck --check-prefix MACHO_DSYM %s
+// RUN: llvm-objdump --macho -d -g --dsym %p/Inputs/hello-macho-fat.dwarf %p/Inputs/hello-macho-thin | FileCheck --check-prefix MACHO_DSYM %s
+// RUN: llvm-objdump --macho -d -g --dsym %p/Inputs/hello-macho-thin.dwarf %p/Inputs/hello-macho-thin | FileCheck --check-prefix MACHO_DSYM %s
+
+MACHO_DSYM: (__TEXT,__text) section
+
+// RUN: llvm-objdump --macho -d -g --dsym %p/../Inputs/libbogus11.a %p/../../dsymutil/Inputs/basic.macho.x86_64 2>&1 | FileCheck --check-prefix BAD_INPUT %s
+
+BAD_INPUT: is not a Mach-O or Universal file type.
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-kextbundle.test b/llvm/test/tools/llvm-objdump/MachO/disassemble-kextbundle.test
similarity index 61%
rename from llvm/test/tools/llvm-objdump/X86/macho-disassemble-kextbundle.test
rename to llvm/test/tools/llvm-objdump/MachO/disassemble-kextbundle.test
index b6c53a22f0c2e..024cfdf62b011 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-kextbundle.test
+++ b/llvm/test/tools/llvm-objdump/MachO/disassemble-kextbundle.test
@@ -1,4 +1,4 @@
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/kextbundle.macho-x86_64 | FileCheck %s
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/kextbundle.macho-x86_64 | FileCheck %s
 
 CHECK: (__TEXT,__text) section
 CHECK: _foo:
diff --git a/llvm/test/tools/llvm-objdump/MachO/disassemble-stab.test b/llvm/test/tools/llvm-objdump/MachO/disassemble-stab.test
new file mode 100644
index 0000000000000..bd9b04cf00990
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/disassemble-stab.test
@@ -0,0 +1,3 @@
+# RUN: llvm-objdump --macho -d %p/Inputs/macho-disassemble-stab-x86_64 | FileCheck %s
+
+CHECK: (__TEXT,__text) section
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-stripped.test b/llvm/test/tools/llvm-objdump/MachO/disassemble-stripped.test
similarity index 50%
rename from llvm/test/tools/llvm-objdump/X86/macho-disassemble-stripped.test
rename to llvm/test/tools/llvm-objdump/MachO/disassemble-stripped.test
index fab86f8b9794a..ec7715c949905 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-stripped.test
+++ b/llvm/test/tools/llvm-objdump/MachO/disassemble-stripped.test
@@ -1,4 +1,4 @@
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.exe.stripped.macho-x86_64 | FileCheck %s
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.exe.stripped.macho-x86_64 | FileCheck %s
 
 CHECK: (__TEXT,__text) section
 CHECK: 0000000100000f30	pushq	%rbp
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-dylib.test b/llvm/test/tools/llvm-objdump/MachO/dylib.test
similarity index 59%
rename from llvm/test/tools/llvm-objdump/X86/macho-dylib.test
rename to llvm/test/tools/llvm-objdump/MachO/dylib.test
index 7454de013d03c..32c64f019c476 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-dylib.test
+++ b/llvm/test/tools/llvm-objdump/MachO/dylib.test
@@ -1,13 +1,13 @@
-RUN: llvm-objdump -m -dylibs-used %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s -check-prefix=USED
+RUN: llvm-objdump --macho --dylibs-used %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s --check-prefix=USED
 USED: /usr/lib/foo1.dylib (compatibility version 0.0.0, current version 0.0.0)
 USED: /usr/lib/foo2.dylib (compatibility version 0.0.0, current version 0.0.0, weak)
 USED: /usr/lib/foo3.dylib (compatibility version 0.0.0, current version 0.0.0, reexport)
 USED: /usr/lib/foo4.dylib (compatibility version 0.0.0, current version 0.0.0, lazy)
 USED: /usr/lib/libSystem.B.dylib (compatibility version 1.0.0, current version 1197.1.1)
 
-RUN: llvm-objdump -m -dylib-id %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s -check-prefix=ID
+RUN: llvm-objdump --macho --dylib-id %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s --check-prefix=ID
 ID: /usr/lib/foo.dylib
 
-RUN: llvm-objdump -m -dylib-id -no-leading-headers %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s -check-prefix=IDNOHEADERS
+RUN: llvm-objdump --macho --dylib-id --no-leading-headers %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s --check-prefix=IDNOHEADERS
 IDNOHEADERS-NOT: dylibLoadKinds.macho-x86_64:
 IDNOHEADERS: /usr/lib/foo.dylib
diff --git a/llvm/test/tools/llvm-objdump/MachO/eh_frame-arm64.test b/llvm/test/tools/llvm-objdump/MachO/eh_frame-arm64.test
index c04de089f9b04..1768d019597a5 100644
--- a/llvm/test/tools/llvm-objdump/MachO/eh_frame-arm64.test
+++ b/llvm/test/tools/llvm-objdump/MachO/eh_frame-arm64.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -dwarf=frames %p/Inputs/eh_frame.macho-arm64 2>/dev/null | FileCheck %s
+# RUN: llvm-objdump --dwarf=frames %p/Inputs/eh_frame.macho-arm64 2>/dev/null | FileCheck %s
 
 # CHECK: .eh_frame contents:
 
diff --git a/llvm/test/tools/llvm-objdump/MachO/exports-trie.test b/llvm/test/tools/llvm-objdump/MachO/exports-trie.test
index 3b081f5f975f7..20d3d04517be9 100644
--- a/llvm/test/tools/llvm-objdump/MachO/exports-trie.test
+++ b/llvm/test/tools/llvm-objdump/MachO/exports-trie.test
@@ -1,6 +1,6 @@
-# RUN: llvm-objdump -macho -exports-trie -arch x86_64 \
+# RUN: llvm-objdump --macho --exports-trie --arch x86_64 \
 # RUN:   %p/Inputs/exports-trie.macho-x86_64 2>/dev/null | FileCheck %s
-# RUN: llvm-objdump -macho -exports-trie -arch x86_64 \
+# RUN: llvm-objdump --macho --exports-trie --arch x86_64 \
 # RUN:   %p/Inputs/weak-bind.macho-x86_64 2>/dev/null | FileCheck --check-prefix=EXE %s
 
 
diff --git a/llvm/test/tools/llvm-objdump/X86/hex-displacement.test b/llvm/test/tools/llvm-objdump/MachO/hex-displacement.test
similarity index 100%
rename from llvm/test/tools/llvm-objdump/X86/hex-displacement.test
rename to llvm/test/tools/llvm-objdump/MachO/hex-displacement.test
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-image-info.test b/llvm/test/tools/llvm-objdump/MachO/image-info.test
similarity index 56%
rename from llvm/test/tools/llvm-objdump/X86/macho-image-info.test
rename to llvm/test/tools/llvm-objdump/MachO/image-info.test
index dbb864f84dcca..688393e2f053d 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-image-info.test
+++ b/llvm/test/tools/llvm-objdump/MachO/image-info.test
@@ -1,4 +1,4 @@
-# RUN: llvm-mc < %s -triple x86_64-darwin -filetype=obj | llvm-objdump -m -objc-meta-data - | FileCheck %s
+# RUN: llvm-mc < %s --triple x86_64-darwin -filetype=obj | llvm-objdump --macho --objc-meta-data - | FileCheck %s
 
 .section	__DATA,__objc_imageinfo,regular,no_dead_strip
 .long	0
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-indirect-symbols.test b/llvm/test/tools/llvm-objdump/MachO/indirect-symbols.test
similarity index 80%
rename from llvm/test/tools/llvm-objdump/X86/macho-indirect-symbols.test
rename to llvm/test/tools/llvm-objdump/MachO/indirect-symbols.test
index fdc465ad54258..dcdb068e711f1 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-indirect-symbols.test
+++ b/llvm/test/tools/llvm-objdump/MachO/indirect-symbols.test
@@ -1,5 +1,5 @@
-RUN: llvm-objdump -macho -indirect-symbols %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s
-RUN: llvm-objdump -macho -indirect-symbols -non-verbose %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s -check-prefix=NON_VERBOSE
+RUN: llvm-objdump --macho --indirect-symbols %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho --indirect-symbols --non-verbose %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s --check-prefix=NON_VERBOSE
 
 CHECK: Indirect symbols for (__TEXT,__stubs) 1 entries
 CHECK: address            index name
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-info-plist-nofollow.test b/llvm/test/tools/llvm-objdump/MachO/info-plist-nofollow.test
similarity index 73%
rename from llvm/test/tools/llvm-objdump/X86/macho-info-plist-nofollow.test
rename to llvm/test/tools/llvm-objdump/MachO/info-plist-nofollow.test
index 12ad166c5a2f0..db9704c8c54e2 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-info-plist-nofollow.test
+++ b/llvm/test/tools/llvm-objdump/MachO/info-plist-nofollow.test
@@ -1,4 +1,4 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -info-plist - | FileCheck %s
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --info-plist - | FileCheck %s
 
 .section  __TEXT, __info_plist
 .ascii "This is the (__TEXT,__info_plist) section\n"
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-info-plist.test b/llvm/test/tools/llvm-objdump/MachO/info-plist.test
similarity index 51%
rename from llvm/test/tools/llvm-objdump/X86/macho-info-plist.test
rename to llvm/test/tools/llvm-objdump/MachO/info-plist.test
index 7550af905b7e6..8370b6b3e3921 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-info-plist.test
+++ b/llvm/test/tools/llvm-objdump/MachO/info-plist.test
@@ -1,5 +1,5 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -info-plist - | FileCheck %s
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -info-plist -no-leading-headers - | FileCheck --check-prefix=NOHEADER %s
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --info-plist - | FileCheck %s
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --info-plist --no-leading-headers - | FileCheck --check-prefix=NOHEADER %s
 
 .section __TEXT, __info_plist
 .asciz "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
diff --git a/llvm/test/tools/llvm-objdump/MachO/lazy-bind.test b/llvm/test/tools/llvm-objdump/MachO/lazy-bind.test
index 088ea0641f0bf..d16d2a80f3255 100644
--- a/llvm/test/tools/llvm-objdump/MachO/lazy-bind.test
+++ b/llvm/test/tools/llvm-objdump/MachO/lazy-bind.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -macho -lazy-bind %p/Inputs/lazy-bind.macho-x86_64 \
+# RUN: llvm-objdump --macho --lazy-bind %p/Inputs/lazy-bind.macho-x86_64 \
 # RUN:   | FileCheck %s 
 
 
diff --git a/llvm/test/tools/llvm-objdump/MachO/lit.local.cfg b/llvm/test/tools/llvm-objdump/MachO/lit.local.cfg
new file mode 100644
index 0000000000000..c8625f4d9d248
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'X86' in config.root.targets:
+    config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-literal-pointers-i386.test b/llvm/test/tools/llvm-objdump/MachO/literal-pointers-i386.test
similarity index 73%
rename from llvm/test/tools/llvm-objdump/X86/macho-literal-pointers-i386.test
rename to llvm/test/tools/llvm-objdump/MachO/literal-pointers-i386.test
index 62ed607c8ee54..adced92a020e0 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-literal-pointers-i386.test
+++ b/llvm/test/tools/llvm-objdump/MachO/literal-pointers-i386.test
@@ -1,5 +1,5 @@
-# RUN: llvm-mc < %s -triple i386-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp - | FileCheck %s
-# RUN: llvm-mc < %s -triple i386-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE
+# RUN: llvm-mc < %s --triple i386-apple-darwin -filetype=obj | llvm-objdump --macho --section __DATA,__litp - | FileCheck %s
+# RUN: llvm-mc < %s --triple i386-apple-darwin -filetype=obj | llvm-objdump --macho --section __DATA,__litp --non-verbose - | FileCheck %s --check-prefix=NON-VERBOSE
 
 .cstring
 L1: .asciz "Hello world\n"
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-literal-pointers-x86_64.test b/llvm/test/tools/llvm-objdump/MachO/literal-pointers-x86_64.test
similarity index 76%
rename from llvm/test/tools/llvm-objdump/X86/macho-literal-pointers-x86_64.test
rename to llvm/test/tools/llvm-objdump/MachO/literal-pointers-x86_64.test
index f1912e8861cbe..d123b97d12eb2 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-literal-pointers-x86_64.test
+++ b/llvm/test/tools/llvm-objdump/MachO/literal-pointers-x86_64.test
@@ -1,5 +1,5 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp - | FileCheck %s
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __DATA,__litp -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __DATA,__litp - | FileCheck %s
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __DATA,__litp --non-verbose - | FileCheck %s --check-prefix=NON-VERBOSE
 
 .cstring
 L1: .asciz "Hello world\n"
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-literals.test b/llvm/test/tools/llvm-objdump/MachO/literals.test
similarity index 63%
rename from llvm/test/tools/llvm-objdump/X86/macho-literals.test
rename to llvm/test/tools/llvm-objdump/MachO/literals.test
index d93ae679f348b..6d622e0ab93f5 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-literals.test
+++ b/llvm/test/tools/llvm-objdump/MachO/literals.test
@@ -1,9 +1,9 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal4 - | FileCheck %s -check-prefix=CHECK-LIT4
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal4 -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE-LIT4
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal8 - | FileCheck %s -check-prefix=CHECK-LIT8
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal8 -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE-LIT8
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal16 - | FileCheck %s -check-prefix=CHECK-LIT16
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __TEXT,__literal16 -non-verbose - | FileCheck %s -check-prefix=NON-VERBOSE-LIT16
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __TEXT,__literal4 - | FileCheck %s --check-prefix=CHECK-LIT4
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __TEXT,__literal4 --non-verbose - | FileCheck %s --check-prefix=NON-VERBOSE-LIT4
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __TEXT,__literal8 - | FileCheck %s --check-prefix=CHECK-LIT8
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __TEXT,__literal8 --non-verbose - | FileCheck %s --check-prefix=NON-VERBOSE-LIT8
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __TEXT,__literal16 - | FileCheck %s --check-prefix=CHECK-LIT16
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __TEXT,__literal16 --non-verbose - | FileCheck %s --check-prefix=NON-VERBOSE-LIT16
 
 .literal4
 .float 2.5
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-maccatalyst-build-version.yaml b/llvm/test/tools/llvm-objdump/MachO/maccatalyst-build-version.yaml
similarity index 94%
rename from llvm/test/tools/llvm-objdump/X86/macho-maccatalyst-build-version.yaml
rename to llvm/test/tools/llvm-objdump/MachO/maccatalyst-build-version.yaml
index b143aea31fab1..8ff27a89b14e1 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-maccatalyst-build-version.yaml
+++ b/llvm/test/tools/llvm-objdump/MachO/maccatalyst-build-version.yaml
@@ -1,4 +1,4 @@
-# RUN: yaml2obj %s | llvm-objdump -macho -private-headers - | FileCheck %s
+# RUN: yaml2obj %s | llvm-objdump --macho --private-headers - | FileCheck %s
 
 --- !mach-o
 FileHeader:
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-objc-meta-data.test b/llvm/test/tools/llvm-objdump/MachO/macho-objc-meta-data.test
similarity index 98%
rename from llvm/test/tools/llvm-objdump/X86/macho-objc-meta-data.test
rename to llvm/test/tools/llvm-objdump/MachO/macho-objc-meta-data.test
index 0c38a649c5ae6..566bde6f45815 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-objc-meta-data.test
+++ b/llvm/test/tools/llvm-objdump/MachO/macho-objc-meta-data.test
@@ -1,11 +1,11 @@
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.64bit.exe.macho-x86_64 | FileCheck %s -check-prefix=OBJC2_64BIT_EXE
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.64bit.obj.macho-x86_64 | FileCheck %s -check-prefix=OBJC2_64BIT_OBJ
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.32bit.exe.macho-i386 | FileCheck %s -check-prefix=OBJC2_32BIT_EXE
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.32bit.obj.macho-i386 | FileCheck %s -check-prefix=OBJC2_32BIT_OBJ
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc1.32bit.exe.macho-i386 | FileCheck %s -check-prefix=OBJC1_32BIT_EXE
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc1.32bit.obj.macho-i386 | FileCheck %s -check-prefix=OBJC1_32BIT_OBJ
-# RUN: llvm-objdump -m -section __OBJC,__protocol %p/Inputs/Objc1.32bit.exe.macho-i386 | FileCheck %s -check-prefix=PROTOCOL
-# RUN: llvm-objdump -m -objc-meta-data %p/Inputs/Objc2.64bit.obj.dylib-x86_64 | FileCheck %s -check-prefix=OBJC2_64BIT_DYLIB
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc2.64bit.exe.macho-x86_64 | FileCheck %s --check-prefix=OBJC2_64BIT_EXE
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc2.64bit.obj.macho-x86_64 | FileCheck %s --check-prefix=OBJC2_64BIT_OBJ
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc2.32bit.exe.macho-i386 | FileCheck %s --check-prefix=OBJC2_32BIT_EXE
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc2.32bit.obj.macho-i386 | FileCheck %s --check-prefix=OBJC2_32BIT_OBJ
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc1.32bit.exe.macho-i386 | FileCheck %s --check-prefix=OBJC1_32BIT_EXE
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc1.32bit.obj.macho-i386 | FileCheck %s --check-prefix=OBJC1_32BIT_OBJ
+# RUN: llvm-objdump --macho --section __OBJC,__protocol %p/Inputs/Objc1.32bit.exe.macho-i386 | FileCheck %s --check-prefix=PROTOCOL
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/Objc2.64bit.obj.dylib-x86_64 | FileCheck %s --check-prefix=OBJC2_64BIT_DYLIB
 
 OBJC2_64BIT_EXE: Contents of (__DATA,__objc_classlist) section
 OBJC2_64BIT_EXE: 0000000100002028 0x1000029f0
diff --git a/llvm/test/tools/llvm-objdump/X86/malformed-machos.test b/llvm/test/tools/llvm-objdump/MachO/malformed-machos.test
similarity index 65%
rename from llvm/test/tools/llvm-objdump/X86/malformed-machos.test
rename to llvm/test/tools/llvm-objdump/MachO/malformed-machos.test
index ecf39866a95b9..c64f8bf9f9e3a 100644
--- a/llvm/test/tools/llvm-objdump/X86/malformed-machos.test
+++ b/llvm/test/tools/llvm-objdump/MachO/malformed-machos.test
@@ -1,74 +1,74 @@
 // These test checks that llvm-objdump will not crash with malformed Mach-O
 // files.  So the check line is not all that important but the bug fixes to
 // make sure llvm-objdump is robust is what matters.
-# RUN: not llvm-objdump -macho -objc-meta-data \
+# RUN: not llvm-objdump --macho --objc-meta-data \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0001.macho 2>&1 \
 # RUN:   | FileCheck -check-prefix=m0001 %s
 
 # m0001: mem-crup-0001.macho': truncated or malformed object (addr field plus size of section 2 in LC_SEGMENT_64 command 0 greater than than the segment's vmaddr plus vmsize)
 
-# RUN: not llvm-objdump -macho -objc-meta-data \
+# RUN: not llvm-objdump --macho --objc-meta-data \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0006.macho 2>&1 \
 # RUN:   | FileCheck -check-prefix=m0006 %s
 
 # m0006: malformed-machos/mem-crup-0006.macho': truncated or malformed object (section contents at offset 4128 with a size of 176, overlaps section contents at offset 4128 with a size of 8)
 
-# RUN: not llvm-objdump -macho -objc-meta-data \
+# RUN: not llvm-objdump --macho --objc-meta-data \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0010.macho 2>&1 \
 # RUN:   | FileCheck -check-prefix=m0010 %s
 
 # m0010: mem-crup-0010.macho': truncated or malformed object (section contents at offset 4320 with a size of 80, overlaps section contents at offset 4320 with a size of 8)
 
-# RUN: not llvm-objdump -macho -objc-meta-data \
+# RUN: not llvm-objdump --macho --objc-meta-data \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0040.macho 2>&1 \
 # RUN:   | FileCheck -check-prefix=m0040 %s
 
 # m0040: mem-crup-0040.macho': truncated or malformed object (offset field plus size field of section 2 in LC_SEGMENT_64 command 1 extends past the end of the file)
 
-# RUN: not llvm-objdump -macho -objc-meta-data \
+# RUN: not llvm-objdump --macho --objc-meta-data \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0080.macho 2>&1 \
 # RUN:   | FileCheck -check-prefix=m0080 %s
 
 # m0080: mem-crup-0080.macho': truncated or malformed object (addr field plus size of section 2 in LC_SEGMENT_64 command 1 greater than than the segment's vmaddr plus vmsize)
 
-# RUN: llvm-objdump -macho -objc-meta-data \
+# RUN: llvm-objdump --macho --objc-meta-data \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0261.macho
 
-# RUN: not llvm-objdump -macho -disassemble \
+# RUN: not llvm-objdump --macho -d \
 # RUN:   %p/Inputs/malformed-machos/mem-crup-0337.macho 2>&1 \
 # RUN:   | FileCheck -check-prefix=m0337 %s
 
 # m0337: mem-crup-0337.macho': truncated or malformed object (section relocation entries at offset 0 with a size of 512, overlaps Mach-O headers at offset 0 with a size of 2048)
 
-RUN: not llvm-objdump -macho -disassemble %p/Inputs/macho-invalid-symbol-nsect 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-NSECT %s
+RUN: not llvm-objdump --macho -d %p/Inputs/macho-invalid-symbol-nsect 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-NSECT %s
 INVALID-SYMBOL-NSECT: macho-invalid-symbol-nsect': truncated or malformed object (bad section index: 97 for symbol at index 1)
 
-RUN: not llvm-objdump -macho -disassemble %p/Inputs/macho-invalid-symbol-nsect-archive 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-NSECT-ARCHIVE %s
+RUN: not llvm-objdump --macho -d %p/Inputs/macho-invalid-symbol-nsect-archive 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-NSECT-ARCHIVE %s
 INVALID-SYMBOL-NSECT-ARCHIVE: macho-invalid-symbol-nsect-archive(macho-invalid-symbol-nsect): truncated or malformed object (bad section index: 97 for symbol at index 1)
 
-RUN: not llvm-objdump -macho -disassemble %p/Inputs/macho-invalid-symbol-indr 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-INDR %s
+RUN: not llvm-objdump --macho -d %p/Inputs/macho-invalid-symbol-indr 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-INDR %s
 INVALID-SYMBOL-INDR: macho-invalid-symbol-indr': truncated or malformed object (bad n_value: 22 past the end of string table, for N_INDR symbol at index 1)
 
-RUN: not llvm-objdump -macho -disassemble -arch all %p/Inputs/macho-invalid-symbol-indr-archive-universal 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-INDR-ARCHIVE-UNIVERSAL %s
+RUN: not llvm-objdump --macho -d --arch all %p/Inputs/macho-invalid-symbol-indr-archive-universal 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-INDR-ARCHIVE-UNIVERSAL %s
 INVALID-SYMBOL-INDR-ARCHIVE-UNIVERSAL: macho-invalid-symbol-indr-archive-universal(macho-invalid-symbol-indr) (for architecture i386): truncated or malformed object (bad n_value: 22 past the end of string table, for N_INDR symbol at index 1)
 
-RUN: not llvm-objdump -macho -disassemble %p/Inputs/macho-invalid-symbol-strx 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-STRX %s
+RUN: not llvm-objdump --macho -d %p/Inputs/macho-invalid-symbol-strx 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-STRX %s
 INVALID-SYMBOL-STRX: macho-invalid-symbol-strx': truncated or malformed object (bad string table index: 22 past the end of string table, for symbol at index 1)
 
-RUN: not llvm-objdump -disassemble %p/Inputs/macho-invalid-symbol-strx 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-STRX-NO-MACHO-FLAG %s
+RUN: not llvm-objdump -d %p/Inputs/macho-invalid-symbol-strx 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-STRX-NO-MACHO-FLAG %s
 INVALID-SYMBOL-STRX-NO-MACHO-FLAG: macho-invalid-symbol-strx': truncated or malformed object (bad string index: 22 for symbol at index 1)
 
-RUN: not llvm-objdump -macho -disassemble -arch all %p/Inputs/macho-invalid-symbol-strx-universal 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-STRX-UNIVERSAL %s
+RUN: not llvm-objdump --macho -d --arch all %p/Inputs/macho-invalid-symbol-strx-universal 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-STRX-UNIVERSAL %s
 INVALID-SYMBOL-STRX-UNIVERSAL: macho-invalid-symbol-strx-universal' (for architecture i386): truncated or malformed object (bad string table index: 22 past the end of string table, for symbol at index 1)
 
-RUN: not llvm-objdump -macho -disassemble %p/Inputs/macho-invalid-symbol-lib_ordinal 2>&1 | FileCheck -check-prefix INVALID-SYMBOL-LIB_ORDINAL %s
+RUN: not llvm-objdump --macho -d %p/Inputs/macho-invalid-symbol-lib_ordinal 2>&1 | FileCheck --check-prefix INVALID-SYMBOL-LIB_ORDINAL %s
 INVALID-SYMBOL-LIB_ORDINAL: macho-invalid-symbol-lib_ordinal': truncated or malformed object (bad library ordinal: 7 for symbol at index 2)
 
-RUN: not llvm-objdump -macho -objc-meta-data %p/Inputs/macho-invalid-bind-entry 2>&1 | FileCheck -check-prefix INVALID-BIND-ENTRY %s
+RUN: not llvm-objdump --macho --objc-meta-data %p/Inputs/macho-invalid-bind-entry 2>&1 | FileCheck --check-prefix INVALID-BIND-ENTRY %s
 INVALID-BIND-ENTRY: macho-invalid-bind-entry': truncated or malformed object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB bad library ordinal: 83 (max 0) for opcode at: 0x0)
 
-RUN: llvm-objdump -macho -r -arch x86_64 %p/Inputs/macho-invalid-reloc-section-index 2>&1 | FileCheck -check-prefix INVALID-RELOC-SECTION-INDEX %s
+RUN: llvm-objdump --macho -r --arch x86_64 %p/Inputs/macho-invalid-reloc-section-index 2>&1 | FileCheck --check-prefix INVALID-RELOC-SECTION-INDEX %s
 INVALID-RELOC-SECTION-INDEX: 00000021 False byte   False  UNSIGND False     8388613 (?,?)
 
-RUN: not llvm-objdump -bind -g -macho -r -rebase -s -section-headers -t -unwind-info %p/Inputs/macho-invalid-linker-command 2>&1 | FileCheck -check-prefix INVALID-LINKCMD %s
+RUN: not llvm-objdump --bind -g --macho -r --rebase -s --section-headers -t --unwind-info %p/Inputs/macho-invalid-linker-command 2>&1 | FileCheck --check-prefix INVALID-LINKCMD %s
 INVALID-LINKCMD: truncated or malformed object (load command 4 LC_LINKER_OPTION string #2 is not NULL terminated)
diff --git a/llvm/test/tools/llvm-objdump/MachO/malformed-unwind-x86_64.test b/llvm/test/tools/llvm-objdump/MachO/malformed-unwind-x86_64.test
index 26984a3485eca..b3db5378c0743 100644
--- a/llvm/test/tools/llvm-objdump/MachO/malformed-unwind-x86_64.test
+++ b/llvm/test/tools/llvm-objdump/MachO/malformed-unwind-x86_64.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -unwind-info %p/Inputs/malformed-unwind.macho-x86_64 | FileCheck %s
+# RUN: llvm-objdump --unwind-info %p/Inputs/malformed-unwind.macho-x86_64 | FileCheck %s
 
 # CHECK: Contents of __unwind_info section:
 # [...]
diff --git a/llvm/test/tools/llvm-objdump/MachO/malformed.test b/llvm/test/tools/llvm-objdump/MachO/malformed.test
index 924d58a1df246..31d68b83537e1 100644
--- a/llvm/test/tools/llvm-objdump/MachO/malformed.test
+++ b/llvm/test/tools/llvm-objdump/MachO/malformed.test
@@ -1,3 +1,3 @@
-RUN: llvm-objdump -macho -private-header %p/Inputs/malformed-macho.bin %p/Inputs/empty.macho-armv7 2>&1 | FileCheck %s -check-prefix=MALFORMED
+RUN: llvm-objdump --macho --private-header %p/Inputs/malformed-macho.bin %p/Inputs/empty.macho-armv7 2>&1 | FileCheck %s --check-prefix=MALFORMED
 MALFORMED: is not an object file
 MALFORMED-NEXT: Mach header
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-nofirst-symbol-disassembly.test b/llvm/test/tools/llvm-objdump/MachO/nofirst-symbol-disassembly.test
similarity index 60%
rename from llvm/test/tools/llvm-objdump/X86/macho-nofirst-symbol-disassembly.test
rename to llvm/test/tools/llvm-objdump/MachO/nofirst-symbol-disassembly.test
index 98964ac8047a4..a5e8b7487afdb 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-nofirst-symbol-disassembly.test
+++ b/llvm/test/tools/llvm-objdump/MachO/nofirst-symbol-disassembly.test
@@ -1,4 +1,4 @@
-// RUN: llvm-objdump -d -m %p/Inputs/nofirst-symbol.macho-x86_64 | FileCheck %s
+// RUN: llvm-objdump -d --macho %p/Inputs/nofirst-symbol.macho-x86_64 | FileCheck %s
 
 CHECK:        0:	90 	nop
 CHECK: _foo:
diff --git a/llvm/test/tools/llvm-objdump/MachO/nontext-disasm.test b/llvm/test/tools/llvm-objdump/MachO/nontext-disasm.test
new file mode 100644
index 0000000000000..75ef3afe15f95
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/nontext-disasm.test
@@ -0,0 +1,9 @@
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho --section __FOO,__bar --full-leading-addr --print-imm-hex --no-show-raw-insn - | FileCheck %s
+
+.section __FOO, __bar
+_foo:
+	nop
+
+# CHECK: Contents of (__FOO,__bar) section
+# CHECK: _foo:
+# CHECK: 0000000000000000	nop
diff --git a/llvm/test/tools/llvm-objdump/MachO/objc-meta-data.test b/llvm/test/tools/llvm-objdump/MachO/objc-meta-data.test
index e659e7e577115..a91569adda2fa 100644
--- a/llvm/test/tools/llvm-objdump/MachO/objc-meta-data.test
+++ b/llvm/test/tools/llvm-objdump/MachO/objc-meta-data.test
@@ -1,3 +1,3 @@
-# RUN: llvm-objdump -macho -objc-meta-data %p/Inputs/empty.macho-armv7 | FileCheck %s
+# RUN: llvm-objdump --macho --objc-meta-data %p/Inputs/empty.macho-armv7 | FileCheck %s
 
 # CHECK: empty.macho-armv7:
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-preload-relocations.test b/llvm/test/tools/llvm-objdump/MachO/preload-relocations.test
similarity index 71%
rename from llvm/test/tools/llvm-objdump/X86/macho-preload-relocations.test
rename to llvm/test/tools/llvm-objdump/MachO/preload-relocations.test
index dda0b2b465bb7..ed4b82b196ff7 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-preload-relocations.test
+++ b/llvm/test/tools/llvm-objdump/MachO/preload-relocations.test
@@ -1,4 +1,4 @@
-// RUN: llvm-objdump -macho -r %p/Inputs/macho-preload-x86_64 | FileCheck %s
+// RUN: llvm-objdump --macho -r %p/Inputs/macho-preload-x86_64 | FileCheck %s
 
 CHECK: Local relocation information 1 entries
 CHECK: address  pcrel length extern type    scattered symbolnum/value
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-print-thread.test b/llvm/test/tools/llvm-objdump/MachO/print-thread.test
similarity index 84%
rename from llvm/test/tools/llvm-objdump/X86/macho-print-thread.test
rename to llvm/test/tools/llvm-objdump/MachO/print-thread.test
index 12f71de1db2f9..982eb1e9cfea2 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-print-thread.test
+++ b/llvm/test/tools/llvm-objdump/MachO/print-thread.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -private-headers %p/Inputs/thread.macho-i386 | FileCheck %s
+RUN: llvm-objdump --macho --private-headers %p/Inputs/thread.macho-i386 | FileCheck %s
 
 CHECK: Load command 9
 CHECK:         cmd LC_UNIXTHREAD
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-private-header.test b/llvm/test/tools/llvm-objdump/MachO/private-header.test
similarity index 70%
rename from llvm/test/tools/llvm-objdump/X86/macho-private-header.test
rename to llvm/test/tools/llvm-objdump/MachO/private-header.test
index b904bbcf5ec02..a416fefd8c823 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-private-header.test
+++ b/llvm/test/tools/llvm-objdump/MachO/private-header.test
@@ -1,4 +1,4 @@
-// RUN: llvm-objdump -macho -private-header %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+// RUN: llvm-objdump --macho --private-header %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
 
 CHECK: Mach header
 CHECK:       magic cputype cpusubtype  caps    filetype ncmds sizeofcmds      flags
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-private-headers.test b/llvm/test/tools/llvm-objdump/MachO/private-headers.test
similarity index 98%
rename from llvm/test/tools/llvm-objdump/X86/macho-private-headers.test
rename to llvm/test/tools/llvm-objdump/MachO/private-headers.test
index b8642fcf6e058..8ca13a383c795 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-private-headers.test
+++ b/llvm/test/tools/llvm-objdump/MachO/private-headers.test
@@ -17,11 +17,11 @@
 // RUN:     | FileCheck %s -check-prefix=ROUTINE
 // RUN: llvm-objdump -p %p/Inputs/exeThread.macho-x86_64 \
 // RUN:     | FileCheck %s -check-prefix=THREAD
-// RUN: llvm-objdump -macho -p -arch i386 %p/Inputs/macho-universal.x86_64.i386 \
+// RUN: llvm-objdump --macho -p --arch i386 %p/Inputs/macho-universal.x86_64.i386 \
 // RUN:     | FileCheck %s -check-prefix=FATi386
-// RUN: llvm-objdump -p -arch i386 %p/Inputs/macho-universal.x86_64.i386 \
+// RUN: llvm-objdump -p --arch i386 %p/Inputs/macho-universal.x86_64.i386 \
 // RUN:     | FileCheck %s -check-prefix=FATi386
-// RUN: llvm-objdump -p -non-verbose %p/Inputs/hello.obj.macho-x86_64 \
+// RUN: llvm-objdump -p --non-verbose %p/Inputs/hello.obj.macho-x86_64 \
 // RUN:     | FileCheck %s -check-prefix=NON_VERBOSE
 // RUN: llvm-objdump -p %p/Inputs/codesig.macho-x86_64 \
 // RUN:     | FileCheck %s -check-prefix=CODESIG
diff --git a/llvm/test/tools/llvm-objdump/MachO/rebase.test b/llvm/test/tools/llvm-objdump/MachO/rebase.test
index 96df390589591..0283a9dbdf3f1 100644
--- a/llvm/test/tools/llvm-objdump/MachO/rebase.test
+++ b/llvm/test/tools/llvm-objdump/MachO/rebase.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -macho -rebase -arch x86_64 \
+# RUN: llvm-objdump --macho --rebase --arch x86_64 \
 # RUN:   %p/Inputs/rebase.macho-x86_64 | FileCheck %s
 
 
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-relocations.test b/llvm/test/tools/llvm-objdump/MachO/relocations.test
similarity index 85%
rename from llvm/test/tools/llvm-objdump/X86/macho-relocations.test
rename to llvm/test/tools/llvm-objdump/MachO/relocations.test
index 111cf0cc95b7c..95db5ec1ab242 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-relocations.test
+++ b/llvm/test/tools/llvm-objdump/MachO/relocations.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -r %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho -r %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
 
 CHECK: Relocation information (__TEXT,__text) 2 entries
 CHECK: address  pcrel length extern type    scattered symbolnum/value
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-section-contents.test b/llvm/test/tools/llvm-objdump/MachO/section-contents.test
similarity index 92%
rename from llvm/test/tools/llvm-objdump/X86/macho-section-contents.test
rename to llvm/test/tools/llvm-objdump/MachO/section-contents.test
index f62b5a7b52dbb..cd68e1fa550b4 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-section-contents.test
+++ b/llvm/test/tools/llvm-objdump/MachO/section-contents.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -s %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho -s %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
 
 CHECK: Contents of section __text:
 CHECK:  0000 554889e5 4883ec20 488d0500 000000c7  UH..H.. H.......
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-section-headers.test b/llvm/test/tools/llvm-objdump/MachO/section-headers.test
similarity index 79%
rename from llvm/test/tools/llvm-objdump/X86/macho-section-headers.test
rename to llvm/test/tools/llvm-objdump/MachO/section-headers.test
index 770b25b22ba52..3012620fcb39d 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-section-headers.test
+++ b/llvm/test/tools/llvm-objdump/MachO/section-headers.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -h %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho -h %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
 
 CHECK: Sections:
 CHECK: Idx Name          Size     VMA              Type
diff --git a/llvm/test/tools/llvm-objdump/MachO/section.test b/llvm/test/tools/llvm-objdump/MachO/section.test
new file mode 100644
index 0000000000000..3425e6050ef0c
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/section.test
@@ -0,0 +1,12 @@
+// RUN: llvm-objdump --macho --section __DATA,__mod_init_func %p/Inputs/dylibModInit.macho-x86_64 | FileCheck %s --check-prefix=MODINIT
+// RUN: llvm-objdump --macho --section __DATA,__mod_init_func --non-verbose %p/Inputs/dylibModInit.macho-x86_64 | FileCheck %s --check-prefix=NON_VERBOSE
+// RUN: llvm-objdump --macho --section __DATA,__mod_init_func %p/Inputs/objModInit.macho-x86_64 | FileCheck %s --check-prefix=OBJ_MODINIT
+
+MODINIT: Contents of (__DATA,__mod_init_func) section
+MODINIT: 0x0000000000001000 0x0000000000000f30 _libinit
+
+NON_VERBOSE: Contents of (__DATA,__mod_init_func) section
+NON_VERBOSE: 0000000000001000	30 0f 00 00 00 00 00 00 
+
+OBJ_MODINIT: Contents of (__DATA,__mod_init_func) section
+OBJ_MODINIT: 0x0000000000000018 0x0000000000000000 _constructor_func
diff --git a/llvm/test/tools/llvm-objdump/MachO/sections.test b/llvm/test/tools/llvm-objdump/MachO/sections.test
index 7b0d89ce50530..2bed7871b49fa 100644
--- a/llvm/test/tools/llvm-objdump/MachO/sections.test
+++ b/llvm/test/tools/llvm-objdump/MachO/sections.test
@@ -1,11 +1,11 @@
-# RUN: llvm-objdump -macho -section=__data %p/Inputs/bind2.macho-x86_64 | FileCheck %s
+# RUN: llvm-objdump --macho --section=__data %p/Inputs/bind2.macho-x86_64 | FileCheck %s
 
 # CHECK: bind2.macho-x86_64:
 
-# RUN: llvm-objdump -macho -section=__data %p/Inputs/section.macho-armv7 | FileCheck -check-prefix CHECK-ADDR %s
+# RUN: llvm-objdump --macho --section=__data %p/Inputs/section.macho-armv7 | FileCheck --check-prefix CHECK-ADDR %s
 
 #  CHECK-ADDR: 00000004	00000001 00000002
 
-# RUN: llvm-objdump -macho -section=__const %p/Inputs/section.macho-armv7 | FileCheck -check-prefix CHECK-BYTES %s
+# RUN: llvm-objdump --macho --section=__const %p/Inputs/section.macho-armv7 | FileCheck --check-prefix CHECK-BYTES %s
 
 #  CHECK-BYTES: 0000000c	00000003 04 05 06
diff --git a/llvm/test/tools/llvm-objdump/MachO/stub-nosyms-disassembly.test b/llvm/test/tools/llvm-objdump/MachO/stub-nosyms-disassembly.test
new file mode 100644
index 0000000000000..4c2f583d73322
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/stub-nosyms-disassembly.test
@@ -0,0 +1,3 @@
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/stub-nosyms.macho-x86_64 | FileCheck %s
+
+CHECK: 0000000000000001	callq	0x7 ## symbol stub for: _foo
diff --git a/llvm/test/tools/llvm-objdump/MachO/stubbed-dylib.test b/llvm/test/tools/llvm-objdump/MachO/stubbed-dylib.test
new file mode 100644
index 0000000000000..115f97b7fca15
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/stubbed-dylib.test
@@ -0,0 +1,5 @@
+RUN: llvm-objdump --macho -d %p/Inputs/stubbed.dylib.macho-x86_64 | FileCheck %s
+
+CHECK: (__TEXT,__text) section
+CHECK-NOT: func
+CHECK-NOT: func2
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-symbol-table.test b/llvm/test/tools/llvm-objdump/MachO/symbol-table.test
similarity index 81%
rename from llvm/test/tools/llvm-objdump/X86/macho-symbol-table.test
rename to llvm/test/tools/llvm-objdump/MachO/symbol-table.test
index 663edc926a944..06368a265dc8d 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-symbol-table.test
+++ b/llvm/test/tools/llvm-objdump/MachO/symbol-table.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -t %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho -t %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
 
 CHECK:      SYMBOL TABLE:
 CHECK-NEXT: 000000000000003b l     O __TEXT,__cstring	L_.str
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test b/llvm/test/tools/llvm-objdump/MachO/symbolized-disassembly.test
similarity index 59%
rename from llvm/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test
rename to llvm/test/tools/llvm-objdump/MachO/symbolized-disassembly.test
index 699a416a9835c..31016a2c1073c 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-symbolized-disassembly.test
+++ b/llvm/test/tools/llvm-objdump/MachO/symbolized-disassembly.test
@@ -1,14 +1,14 @@
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s -check-prefix=EXE
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/ObjC.obj.macho-x86_64 | FileCheck %s -check-prefix=ObjC-OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/ObjC.exe.macho-x86_64 | FileCheck %s -check-prefix=ObjC-EXE
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello_cpp.exe.macho-x86_64 | FileCheck %s -check-prefix=CXX-EXE
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s --check-prefix=OBJ
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s --check-prefix=EXE
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/ObjC.obj.macho-x86_64 | FileCheck %s --check-prefix=ObjC-OBJ
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/ObjC.exe.macho-x86_64 | FileCheck %s --check-prefix=ObjC-EXE
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello_cpp.exe.macho-x86_64 | FileCheck %s --check-prefix=CXX-EXE
 
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.obj.macho-i386 | FileCheck %s -check-prefix=i386-OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/hello.exe.macho-i386 | FileCheck %s -check-prefix=i386-EXE
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.obj.macho-i386 | FileCheck %s --check-prefix=i386-OBJ
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex %p/Inputs/hello.exe.macho-i386 | FileCheck %s --check-prefix=i386-EXE
 
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex -no-symbolic-operands %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NO-SYM-OPS-OBJ
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex -no-symbolic-operands %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s -check-prefix=NO-SYM-OPS-EXE
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex --no-symbolic-operands %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s --check-prefix=NO-SYM-OPS-OBJ
+// RUN: llvm-objdump -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex --no-symbolic-operands %p/Inputs/hello.exe.macho-x86_64 | FileCheck %s --check-prefix=NO-SYM-OPS-EXE
 
 OBJ: 0000000000000008	leaq	L_.str(%rip), %rax      ## literal pool for: "Hello world\n"
 OBJ: 0000000000000026	callq	_printf
diff --git a/llvm/test/tools/llvm-objdump/MachO/symbolized-subtractor-i386.test b/llvm/test/tools/llvm-objdump/MachO/symbolized-subtractor-i386.test
new file mode 100644
index 0000000000000..bcace1788608c
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/symbolized-subtractor-i386.test
@@ -0,0 +1,10 @@
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho -d - | FileCheck %s
+
+nop
+x:
+leal	x-y(%eax), %ebx
+.data
+y:
+.quad 0
+
+# CHECK: leal	x-y(%eax), %ebx
diff --git a/llvm/test/tools/llvm-objdump/MachO/symbolized-subtractor.test b/llvm/test/tools/llvm-objdump/MachO/symbolized-subtractor.test
new file mode 100644
index 0000000000000..a1cdd99a64cb3
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/MachO/symbolized-subtractor.test
@@ -0,0 +1,10 @@
+# RUN: llvm-mc < %s --triple x86_64-apple-darwin -filetype=obj | llvm-objdump --macho -d - | FileCheck %s
+
+nop
+x:
+leaq	x-y(%rax), %rbx
+.data
+y:
+.quad 0
+
+# CHECK: leaq	x-y(%rax), %rbx
diff --git a/llvm/test/tools/llvm-objdump/X86/truncated-section.test b/llvm/test/tools/llvm-objdump/MachO/truncated-section.test
similarity index 53%
rename from llvm/test/tools/llvm-objdump/X86/truncated-section.test
rename to llvm/test/tools/llvm-objdump/MachO/truncated-section.test
index e9fe75da71afd..16d56295e4589 100644
--- a/llvm/test/tools/llvm-objdump/X86/truncated-section.test
+++ b/llvm/test/tools/llvm-objdump/MachO/truncated-section.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -d %p/Inputs/truncated-section.dylib.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho -d %p/Inputs/truncated-section.dylib.macho-x86_64 | FileCheck %s
 
 CHECK: _func:
 CHECK:     retq
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test b/llvm/test/tools/llvm-objdump/MachO/universal-x86_64.i386.test
similarity index 67%
rename from llvm/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test
rename to llvm/test/tools/llvm-objdump/MachO/universal-x86_64.i386.test
index 6de7e18e437ba..331f97e1ae892 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-universal-x86_64.i386.test
+++ b/llvm/test/tools/llvm-objdump/MachO/universal-x86_64.i386.test
@@ -1,15 +1,15 @@
-RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex -arch all \
-RUN: | FileCheck %s -check-prefix UEXE-all
-RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -d -no-show-raw-insn -full-leading-addr -print-imm-hex -arch all \
-RUN: | FileCheck %s -check-prefix UEXE-all
-RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex -arch i386 \
-RUN: | FileCheck %s -check-prefix UArchive-i386
-RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -universal-headers -m \
-RUN: | FileCheck %s -check-prefix FAT
-RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -universal-headers -m \
-RUN: -non-verbose | FileCheck %s -check-prefix NON-VERBOSE
-RUN: llvm-objdump %p/Inputs/macho-universal64.x86_64.i386 -universal-headers \
-RUN: -m | FileCheck %s -check-prefix FAT-64
+RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex --arch all \
+RUN: | FileCheck %s --check-prefix UEXE-all
+RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 -d --no-show-raw-insn --full-leading-addr --print-imm-hex --arch all \
+RUN: | FileCheck %s --check-prefix UEXE-all
+RUN: llvm-objdump %p/Inputs/macho-universal-archive.x86_64.i386 -d --macho --no-show-raw-insn --full-leading-addr --print-imm-hex --arch i386 \
+RUN: | FileCheck %s --check-prefix UArchive-i386
+RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 --universal-headers --macho \
+RUN: | FileCheck %s --check-prefix FAT
+RUN: llvm-objdump %p/Inputs/macho-universal.x86_64.i386 --universal-headers --macho \
+RUN: --non-verbose | FileCheck %s --check-prefix NON-VERBOSE
+RUN: llvm-objdump %p/Inputs/macho-universal64.x86_64.i386 --universal-headers \
+RUN: --macho | FileCheck %s --check-prefix FAT-64
 
 UEXE-all: macho-universal.x86_64.i386 (architecture x86_64):
 UEXE-all: (__TEXT,__text) section
diff --git a/llvm/test/tools/llvm-objdump/MachO/unwind-info-arm64.test b/llvm/test/tools/llvm-objdump/MachO/unwind-info-arm64.test
index 712edef50bd8f..2b376615e0b37 100644
--- a/llvm/test/tools/llvm-objdump/MachO/unwind-info-arm64.test
+++ b/llvm/test/tools/llvm-objdump/MachO/unwind-info-arm64.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -unwind-info %p/Inputs/unwind-info.macho-arm64 2>/dev/null | FileCheck %s
+# RUN: llvm-objdump --unwind-info %p/Inputs/unwind-info.macho-arm64 2>/dev/null | FileCheck %s
 
 # The 2nd level index here is "regular", including all offsets & encodings in
 # full.
diff --git a/llvm/test/tools/llvm-objdump/MachO/unwind-info-no-relocs.test b/llvm/test/tools/llvm-objdump/MachO/unwind-info-no-relocs.test
index 3adad658c0878..4246502c05809 100644
--- a/llvm/test/tools/llvm-objdump/MachO/unwind-info-no-relocs.test
+++ b/llvm/test/tools/llvm-objdump/MachO/unwind-info-no-relocs.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -unwind-info %p/Inputs/unwind-info-no-relocs.macho-x86_64 2>/dev/null | FileCheck %s
+# RUN: llvm-objdump --unwind-info %p/Inputs/unwind-info-no-relocs.macho-x86_64 2>/dev/null | FileCheck %s
 
 # Make sure we can deal with __compact_unwind sections that don't have helpful
 # relocations.
diff --git a/llvm/test/tools/llvm-objdump/MachO/unwind-info-x86_64.test b/llvm/test/tools/llvm-objdump/MachO/unwind-info-x86_64.test
index 1333d9a4cdb93..05ad3009c6dba 100644
--- a/llvm/test/tools/llvm-objdump/MachO/unwind-info-x86_64.test
+++ b/llvm/test/tools/llvm-objdump/MachO/unwind-info-x86_64.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -unwind-info %p/Inputs/unwind-info.macho-x86_64 2>/dev/null | FileCheck %s
+# RUN: llvm-objdump --unwind-info %p/Inputs/unwind-info.macho-x86_64 2>/dev/null | FileCheck %s
 
 # The 2nd level index in this file is in compressed form, referring to both
 # common and packed encodings.
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-unwind-info.test b/llvm/test/tools/llvm-objdump/MachO/unwind-info.test
similarity index 72%
rename from llvm/test/tools/llvm-objdump/X86/macho-unwind-info.test
rename to llvm/test/tools/llvm-objdump/MachO/unwind-info.test
index 33db84fc07d10..c7503d9e6518b 100644
--- a/llvm/test/tools/llvm-objdump/X86/macho-unwind-info.test
+++ b/llvm/test/tools/llvm-objdump/MachO/unwind-info.test
@@ -1,4 +1,4 @@
-RUN: llvm-objdump -macho -u %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
+RUN: llvm-objdump --macho -u %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
 
 CHECK: Contents of __compact_unwind section:
 CHECK:   Entry at offset 0x0:
diff --git a/llvm/test/tools/llvm-objdump/MachO/weak-bind.test b/llvm/test/tools/llvm-objdump/MachO/weak-bind.test
index 1013132a75061..777b44c79228b 100644
--- a/llvm/test/tools/llvm-objdump/MachO/weak-bind.test
+++ b/llvm/test/tools/llvm-objdump/MachO/weak-bind.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -macho -weak-bind  %p/Inputs/weak-bind.macho-x86_64 \
+# RUN: llvm-objdump --macho --weak-bind  %p/Inputs/weak-bind.macho-x86_64 \
 # RUN:   | FileCheck %s
 
 
diff --git a/llvm/test/tools/llvm-objdump/PowerPC/lit.local.cfg b/llvm/test/tools/llvm-objdump/PowerPC/lit.local.cfg
index b77510721e100..091332439b186 100644
--- a/llvm/test/tools/llvm-objdump/PowerPC/lit.local.cfg
+++ b/llvm/test/tools/llvm-objdump/PowerPC/lit.local.cfg
@@ -1,2 +1,2 @@
 if not 'PowerPC' in config.root.targets:
-      config.unsupported = True
+    config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-align.s b/llvm/test/tools/llvm-objdump/X86/disassemble-align.s
index 8062256becb02..09366c9b6b645 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-align.s
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-align.s
@@ -1,9 +1,9 @@
 # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t
 
 # Use '|' to show where the tabs line up.
-# RUN: llvm-objdump -d -print-imm-hex %t | tr '\t' '|' | FileCheck -strict-whitespace %s
+# RUN: llvm-objdump -d --print-imm-hex %t | tr '\t' '|' | FileCheck --strict-whitespace %s
 
-# RUN: llvm-objdump -d -print-imm-hex -no-show-raw-insn %t | tr '\t' '|' | \
+# RUN: llvm-objdump -d --print-imm-hex --no-show-raw-insn %t | tr '\t' '|' | \
 # RUN:   FileCheck -check-prefix=NORAW -strict-whitespace %s
 
 # Instructions are expected to be aligned if the instruction in hex is not too long.
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-show-raw.test b/llvm/test/tools/llvm-objdump/X86/disassemble-show-raw.test
index e9956a5ebe4b5..30722c0db7fdc 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-show-raw.test
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-show-raw.test
@@ -1,6 +1,6 @@
 // RUN: llvm-objdump -d %p/Inputs/trivial.obj.elf-i386 \
 // RUN:     | FileCheck %s -check-prefix=WITHRAW
-// RUN: llvm-objdump -d -no-show-raw-insn %p/Inputs/trivial.obj.elf-i386 \
+// RUN: llvm-objdump -d --no-show-raw-insn %p/Inputs/trivial.obj.elf-i386 \
 // RUN:     | FileCheck %s -check-prefix=NORAW
 
 // Expect to find the raw incoding when run with raw output (default), but not
diff --git a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test
index a690328085e40..a7d77f863eb70 100644
--- a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test
+++ b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test
@@ -45,7 +45,7 @@ Symbols:
 ## sh_info field of a relocation section is invalid.
 
 # RUN: yaml2obj %s --docnum=2 -o %t2.o
-# RUN: not llvm-objdump %t2.o --disassemble --reloc 2>&1 | FileCheck %s -DFILE=%t2.o --check-prefix=ERR
+# RUN: not llvm-objdump %t2.o -d --reloc 2>&1 | FileCheck %s -DFILE=%t2.o --check-prefix=ERR
 
 # ERR: error: '[[FILE]]': section (1): failed to get a relocated section: invalid section index: 255
 
diff --git a/llvm/test/tools/llvm-objdump/X86/elf-disassemble.test b/llvm/test/tools/llvm-objdump/X86/elf-disassemble.test
index d0d919a3b40d9..2028f7fefd758 100644
--- a/llvm/test/tools/llvm-objdump/X86/elf-disassemble.test
+++ b/llvm/test/tools/llvm-objdump/X86/elf-disassemble.test
@@ -1,6 +1,6 @@
 ## Show that disassembly is printed correctly, for only the desired sections.
 # RUN: yaml2obj %s -o %t.o
-# RUN: llvm-objdump %t.o --disassemble | FileCheck %s --implicit-check-not=Disassembly
+# RUN: llvm-objdump %t.o -d | FileCheck %s --implicit-check-not=Disassembly
 # RUN: llvm-objdump %t.o --disassemble-all | FileCheck %s --check-prefixes=CHECK,ALL
 
 # CHECK:       Disassembly of section .executable:
diff --git a/llvm/test/tools/llvm-objdump/X86/function-sections-line-numbers.s b/llvm/test/tools/llvm-objdump/X86/function-sections-line-numbers.s
index f3243bc27cdfd..018529ffba3f1 100644
--- a/llvm/test/tools/llvm-objdump/X86/function-sections-line-numbers.s
+++ b/llvm/test/tools/llvm-objdump/X86/function-sections-line-numbers.s
@@ -8,7 +8,7 @@
 # clang -gdwarf-5 -ffunction-sections test.cpp -o test.s -S
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux -dwarf-version=5 %s -o %t.o
-# RUN: llvm-objdump -disassemble -line-numbers -r -s -section-headers -t %t.o | FileCheck %s
+# RUN: llvm-objdump -d --line-numbers -r -s --section-headers -t %t.o | FileCheck %s
 
 
 # CHECK: 0000000000000000 <_Z2f1v>
diff --git a/llvm/test/tools/llvm-objdump/X86/invalid-macho-build-version.yaml b/llvm/test/tools/llvm-objdump/X86/invalid-macho-build-version.yaml
index a81bb2dea600c..adca65419aa11 100644
--- a/llvm/test/tools/llvm-objdump/X86/invalid-macho-build-version.yaml
+++ b/llvm/test/tools/llvm-objdump/X86/invalid-macho-build-version.yaml
@@ -1,4 +1,4 @@
-# RUN: yaml2obj %s | not llvm-objdump -macho -private-headers -
+# RUN: yaml2obj %s | not llvm-objdump --macho --private-headers -
 
 --- !mach-o
 FileHeader:
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-cstring-dump.test b/llvm/test/tools/llvm-objdump/X86/macho-cstring-dump.test
deleted file mode 100644
index 9ced9c60121c9..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-cstring-dump.test
+++ /dev/null
@@ -1,18 +0,0 @@
-RUN: llvm-objdump -m -section __TEXT,__cstring %p/Inputs/hello.obj.macho-x86_64 2>&1 | FileCheck %s --implicit-check-not="warning:"
-RUN: llvm-objdump -m -section __TEXT,__cstring -no-leading-addr %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NO_ADDR --implicit-check-not="warning:"
-RUN: llvm-objdump -m -section __TEXT,__cstring -no-leading-headers %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NO_HEADERS --implicit-check-not="warning:"
-RUN: llvm-objdump -m -section __TEXT,__cstring -non-verbose %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s -check-prefix=NON_VERBOSE --implicit-check-not="warning:"
-
-CHECK: Contents of (__TEXT,__cstring) section
-CHECK-NEXT: 000000000000003b  Hello world\n
-
-NO_ADDR: Contents of (__TEXT,__cstring) section
-NO_ADDR: Hello world\n
-NO_ADDR-NOT: 000000000000003b
-
-NO_HEADERS-NOT: Inputs/hello.obj.macho-x86_64:
-NO_HEADERS-NOT: Contents of (__TEXT,__cstring) section
-NO_HEADERS: 000000000000003b	Hello world\n
-
-NON_VERBOSE: Contents of (__TEXT,__cstring) section
-NON_VERBOSE: 000000000000003b	48 65 6c 6c 6f 20 77 6f 72 6c 64 0a 00
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-g-dsym.test b/llvm/test/tools/llvm-objdump/X86/macho-disassemble-g-dsym.test
deleted file mode 100644
index 94ef98ab9f68f..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-g-dsym.test
+++ /dev/null
@@ -1,17 +0,0 @@
-// RUN: dsymutil -f -oso-prepend-path=%p/../../dsymutil/ %p/../../dsymutil/Inputs/basic.macho.x86_64 -o %t1.dSYM
-// RUN: llvm-objdump -d -g -dsym=%t1.dSYM %p/../../dsymutil/Inputs/basic.macho.x86_64 >%t0
-// RUN: llvm-objdump -dg -dsym=%t1.dSYM %p/../../dsymutil/Inputs/basic.macho.x86_64 >%t1
-// RUN: cmp %t0 %t1
-// RUN: FileCheck --input-file %t0 %s
-
-CHECK: Disassembly of section __TEXT,__text:
-
-// RUN: llvm-objdump -m -d -g -dsym %p/Inputs/hello-macho-fat.dwarf %p/Inputs/hello-macho-fat | FileCheck -check-prefix MACHO_DSYM %s
-// RUN: llvm-objdump -m -d -g -dsym %p/Inputs/hello-macho-fat.dwarf %p/Inputs/hello-macho-thin | FileCheck -check-prefix MACHO_DSYM %s
-// RUN: llvm-objdump -m -d -g -dsym %p/Inputs/hello-macho-thin.dwarf %p/Inputs/hello-macho-thin | FileCheck -check-prefix MACHO_DSYM %s
-
-MACHO_DSYM: (__TEXT,__text) section
-
-// RUN: llvm-objdump -m -d -g -dsym %p/../Inputs/libbogus11.a %p/../../dsymutil/Inputs/basic.macho.x86_64 2>&1 | FileCheck -check-prefix BAD_INPUT %s
-
-BAD_INPUT: is not a Mach-O or Universal file type.
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-stab.test b/llvm/test/tools/llvm-objdump/X86/macho-disassemble-stab.test
deleted file mode 100644
index 050b350e447f6..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-disassemble-stab.test
+++ /dev/null
@@ -1,3 +0,0 @@
-# RUN: llvm-objdump -m -disassemble %p/Inputs/macho-disassemble-stab-x86_64 | FileCheck %s
-
-CHECK: (__TEXT,__text) section
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-nontext-disasm.test b/llvm/test/tools/llvm-objdump/X86/macho-nontext-disasm.test
deleted file mode 100644
index 27b7bb441520f..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-nontext-disasm.test
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -section __FOO,__bar -full-leading-addr -print-imm-hex -no-show-raw-insn - | FileCheck %s
-
-.section __FOO, __bar
-_foo:
-	nop
-
-# CHECK: Contents of (__FOO,__bar) section
-# CHECK: _foo:
-# CHECK: 0000000000000000	nop
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-section.test b/llvm/test/tools/llvm-objdump/X86/macho-section.test
deleted file mode 100644
index a8eaa49d88de3..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-section.test
+++ /dev/null
@@ -1,12 +0,0 @@
-// RUN: llvm-objdump -m -section __DATA,__mod_init_func %p/Inputs/dylibModInit.macho-x86_64 | FileCheck %s -check-prefix=MODINIT
-// RUN: llvm-objdump -m -section __DATA,__mod_init_func -non-verbose %p/Inputs/dylibModInit.macho-x86_64 | FileCheck %s -check-prefix=NON_VERBOSE
-// RUN: llvm-objdump -m -section __DATA,__mod_init_func %p/Inputs/objModInit.macho-x86_64 | FileCheck %s -check-prefix=OBJ_MODINIT
-
-MODINIT: Contents of (__DATA,__mod_init_func) section
-MODINIT: 0x0000000000001000 0x0000000000000f30 _libinit
-
-NON_VERBOSE: Contents of (__DATA,__mod_init_func) section
-NON_VERBOSE: 0000000000001000	30 0f 00 00 00 00 00 00 
-
-OBJ_MODINIT: Contents of (__DATA,__mod_init_func) section
-OBJ_MODINIT: 0x0000000000000018 0x0000000000000000 _constructor_func
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-stub-nosyms-disassembly.test b/llvm/test/tools/llvm-objdump/X86/macho-stub-nosyms-disassembly.test
deleted file mode 100644
index af66b0e7a63f6..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-stub-nosyms-disassembly.test
+++ /dev/null
@@ -1,3 +0,0 @@
-// RUN: llvm-objdump -d -m -no-show-raw-insn -full-leading-addr -print-imm-hex %p/Inputs/stub-nosyms.macho-x86_64 | FileCheck %s
-
-CHECK: 0000000000000001	callq	0x7 ## symbol stub for: _foo
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-symbolized-subtractor-i386.test b/llvm/test/tools/llvm-objdump/X86/macho-symbolized-subtractor-i386.test
deleted file mode 100644
index a0f753bdb7ad7..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-symbolized-subtractor-i386.test
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -d - | FileCheck %s
-
-nop
-x:
-leal	x-y(%eax), %ebx
-.data
-y:
-.quad 0
-
-# CHECK: leal	x-y(%eax), %ebx
diff --git a/llvm/test/tools/llvm-objdump/X86/macho-symbolized-subtractor.test b/llvm/test/tools/llvm-objdump/X86/macho-symbolized-subtractor.test
deleted file mode 100644
index a730b5c65fa4f..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/macho-symbolized-subtractor.test
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc < %s -triple x86_64-apple-darwin -filetype=obj | llvm-objdump -m -d - | FileCheck %s
-
-nop
-x:
-leaq	x-y(%rax), %rbx
-.data
-y:
-.quad 0
-
-# CHECK: leaq	x-y(%rax), %rbx
diff --git a/llvm/test/tools/llvm-objdump/X86/plt.test b/llvm/test/tools/llvm-objdump/X86/plt.test
index 4bd8883a718d9..d4847f021a181 100644
--- a/llvm/test/tools/llvm-objdump/X86/plt.test
+++ b/llvm/test/tools/llvm-objdump/X86/plt.test
@@ -1,6 +1,6 @@
-// RUN: llvm-objdump -d %p/Inputs/stripped-elf.so | FileCheck -check-prefix=64 %s
-// RUN: llvm-objdump -d %p/Inputs/hello.exe.elf-i386 | FileCheck -check-prefix=32 %s
-// RUN: llvm-objdump -d %p/Inputs/hello.exe.nopie.elf-i386 | FileCheck -check-prefix=32 %s
+// RUN: llvm-objdump -d %p/Inputs/stripped-elf.so | FileCheck --check-prefix=64 %s
+// RUN: llvm-objdump -d %p/Inputs/hello.exe.elf-i386 | FileCheck --check-prefix=32 %s
+// RUN: llvm-objdump -d %p/Inputs/hello.exe.nopie.elf-i386 | FileCheck --check-prefix=32 %s
 
 # 64: Disassembly of section .plt:
 # 64: <__gmon_start__@plt>:
diff --git a/llvm/test/tools/llvm-objdump/X86/section-index.s b/llvm/test/tools/llvm-objdump/X86/section-index.s
index 6ca86ea19b571..5ba1f4bdc8305 100644
--- a/llvm/test/tools/llvm-objdump/X86/section-index.s
+++ b/llvm/test/tools/llvm-objdump/X86/section-index.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc %s -filetype=obj -triple=x86_64-pc-linux -o %t
 
-# RUN: llvm-objdump -section-headers %t | FileCheck %s
+# RUN: llvm-objdump --section-headers %t | FileCheck %s
 # CHECK:     Idx Name
 # CHECK:      3  .foo
 # CHECK-NEXT: 4  .bar
@@ -8,7 +8,7 @@
 
 ## Check we report the valid section index
 ## when requesting a specific section.
-# RUN: llvm-objdump -section-headers -section=.bar %t \
+# RUN: llvm-objdump --section-headers --section=.bar %t \
 # RUN:   | FileCheck %s --check-prefix=BAR
 # BAR:      Idx Name
 # BAR-NEXT:  4  .bar
diff --git a/llvm/test/tools/llvm-objdump/X86/stubbed-dylib.test b/llvm/test/tools/llvm-objdump/X86/stubbed-dylib.test
deleted file mode 100644
index 6f7f7221eb166..0000000000000
--- a/llvm/test/tools/llvm-objdump/X86/stubbed-dylib.test
+++ /dev/null
@@ -1,5 +0,0 @@
-RUN: llvm-objdump -macho -d %p/Inputs/stubbed.dylib.macho-x86_64 | FileCheck %s
-
-CHECK: (__TEXT,__text) section
-CHECK-NOT: func
-CHECK-NOT: func2
diff --git a/llvm/test/tools/llvm-objdump/archive-headers.test b/llvm/test/tools/llvm-objdump/archive-headers.test
index bb649a657a16a..9cdc68416da69 100644
--- a/llvm/test/tools/llvm-objdump/archive-headers.test
+++ b/llvm/test/tools/llvm-objdump/archive-headers.test
@@ -1,5 +1,5 @@
 # RUN: llvm-objdump -a %p/Inputs/liblong_filenames.a | FileCheck %s
-# RUN: llvm-objdump -archive-headers %p/Inputs/liblong_filenames.a | FileCheck %s
+# RUN: llvm-objdump --archive-headers %p/Inputs/liblong_filenames.a | FileCheck %s
 
 # CHECK: {{.*}}liblong_filenames.a(1.o): file format elf64-x86-64
 # CHECK: rw-r--r-- 204299/200  1416 {{.*}} 1.o
diff --git a/llvm/test/tools/llvm-objdump/eh_frame-mipsel.test b/llvm/test/tools/llvm-objdump/eh_frame-mipsel.test
index 76143248ef855..67d2408269146 100644
--- a/llvm/test/tools/llvm-objdump/eh_frame-mipsel.test
+++ b/llvm/test/tools/llvm-objdump/eh_frame-mipsel.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -dwarf=frames %p/Inputs/eh_frame.elf-mipsel | FileCheck %s
+# RUN: llvm-objdump --dwarf=frames %p/Inputs/eh_frame.elf-mipsel | FileCheck %s
 
 # CHECK: .eh_frame contents:
 
diff --git a/llvm/test/tools/llvm-objdump/eh_frame_zero_cie.test b/llvm/test/tools/llvm-objdump/eh_frame_zero_cie.test
index 652fd0a4e191f..4702162a749bd 100644
--- a/llvm/test/tools/llvm-objdump/eh_frame_zero_cie.test
+++ b/llvm/test/tools/llvm-objdump/eh_frame_zero_cie.test
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -dwarf=frames %p/Inputs/eh_frame_zero_cie.o 2>/dev/null | FileCheck %s
+# RUN: llvm-objdump --dwarf=frames %p/Inputs/eh_frame_zero_cie.o 2>/dev/null | FileCheck %s
 
 # CHECK: .eh_frame contents:
 
diff --git a/llvm/test/tools/llvm-objdump/embedded-source.test b/llvm/test/tools/llvm-objdump/embedded-source.test
index fd1ce71686c3c..b0de4d9c2300e 100644
--- a/llvm/test/tools/llvm-objdump/embedded-source.test
+++ b/llvm/test/tools/llvm-objdump/embedded-source.test
@@ -1,5 +1,5 @@
-; RUN: llvm-objdump -disassemble -line-numbers %p/Inputs/embedded-source | FileCheck --check-prefix=LINE %s
-; RUN: llvm-objdump -disassemble -source       %p/Inputs/embedded-source | FileCheck --check-prefix=SOURCE %s
+; RUN: llvm-objdump -d --line-numbers %p/Inputs/embedded-source | FileCheck --check-prefix=LINE %s
+; RUN: llvm-objdump -d --source       %p/Inputs/embedded-source | FileCheck --check-prefix=SOURCE %s
 ; REQUIRES: x86-registered-target
 
 ; Source for embedded-source.c
diff --git a/llvm/test/tools/llvm-objdump/file-headers-pe.test b/llvm/test/tools/llvm-objdump/file-headers-pe.test
index b0146226d68ad..6609a9f83e6c2 100644
--- a/llvm/test/tools/llvm-objdump/file-headers-pe.test
+++ b/llvm/test/tools/llvm-objdump/file-headers-pe.test
@@ -1,6 +1,6 @@
 # RUN: yaml2obj %s -o %t
 # RUN: llvm-objdump -f %t | FileCheck %s
-# RUN: llvm-objdump -file-headers %t | FileCheck %s
+# RUN: llvm-objdump --file-headers %t | FileCheck %s
 
 !COFF
 header: !Header
diff --git a/llvm/test/tools/llvm-objdump/invalid-input.test b/llvm/test/tools/llvm-objdump/invalid-input.test
index 20a901d0b2ded..582abc668b9fe 100644
--- a/llvm/test/tools/llvm-objdump/invalid-input.test
+++ b/llvm/test/tools/llvm-objdump/invalid-input.test
@@ -1,6 +1,6 @@
-RUN: not llvm-objdump -t %p/missing-file 2>&1 | FileCheck %s -check-prefix=NO_SUCH_FILE
+RUN: not llvm-objdump -t %p/missing-file 2>&1 | FileCheck %s --check-prefix=NO_SUCH_FILE
 # Don't check the OS-dependent message "No such file or directory".
 NO_SUCH_FILE: '{{.*}}missing-file':
 
-RUN: not llvm-objdump -t %s 2>&1 | FileCheck %s -check-prefix=UNKNOWN_FILE_TYPE
+RUN: not llvm-objdump -t %s 2>&1 | FileCheck %s --check-prefix=UNKNOWN_FILE_TYPE
 UNKNOWN_FILE_TYPE: '{{.*}}invalid-input.test': The file was not recognized as a valid object file
diff --git a/llvm/test/tools/llvm-objdump/malformed-archives.test b/llvm/test/tools/llvm-objdump/malformed-archives.test
index 00c264ed1392e..4508c0baca06c 100644
--- a/llvm/test/tools/llvm-objdump/malformed-archives.test
+++ b/llvm/test/tools/llvm-objdump/malformed-archives.test
@@ -1,49 +1,49 @@
 // These test checks that llvm-objdump will not crash with malformed Archive
 // files.  So the check line is not all that important but the bug fixes to
 // make sure llvm-objdump is robust is what matters.
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus1.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus1 %s 
 
 # bogus1: libbogus1.a': truncated or malformed archive (characters in size field in archive header are not all decimal numbers: '10%' for archive member header at offset 8)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus2.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus2 %s 
 
 # bogus2: libbogus2.a': truncated or malformed archive (characters in size field in archive header are not all decimal numbers: '1%' for archive member header at offset 170)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus3.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus3 %s 
 
 # bogus3: libbogus3.a': truncated or malformed archive (offset to next archive member past the end of the archive after member foo.c)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus4.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus4 %s 
 
 # bogus4: libbogus4.a': truncated or malformed archive (remaining size of archive too small for next archive member header for foo.c)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus5.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus5 %s 
 
 # bogus5: libbogus5.a': truncated or malformed archive (terminator characters in archive member "@\n" not the correct "`\n" values for the archive member header for hello.c)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus6.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus6 %s 
 
 # bogus6: libbogus6.a': truncated or malformed archive (name contains a leading space for archive member header at offset 96)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus7.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus7 %s 
 
 # bogus7: libbogus7.a': truncated or malformed archive (long name length characters after the #1/ are not all decimal numbers: '@123$' for archive member header at offset 8)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus8.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus8 %s 
 
@@ -59,25 +59,25 @@
 
 # bogus10: libbogus10.a(<file index: 0>): truncated or malformed archive (long name offset 507 past the end of the string table for archive member header at offset 94)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus11.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus11 %s 
 
 # bogus11: libbogus11.a(hello.c): truncated or malformed archive (characters in UID field in archive header are not all decimal numbers: '~97&' for the archive member header at offset 8)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus12.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus12 %s 
 
 # bogus12: libbogus12.a(hello.c): truncated or malformed archive (characters in GID field in archive header are not all decimal numbers: '#55!' for the archive member header at offset 8)
 
-# RUN: not llvm-objdump -macho -archive-headers \
+# RUN: not llvm-objdump --macho --archive-headers \
 # RUN:   %p/Inputs/libbogus13.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus13 %s 
 
 # bogus13: libbogus13.a(hello.c): truncated or malformed archive (characters in AccessMode field in archive header are not all decimal numbers: 'Feed' for the archive member header at offset 8)
 
-# RUN: llvm-objdump -macho -archive-headers %p/Inputs/libbogus14.a \
+# RUN: llvm-objdump --macho --archive-headers %p/Inputs/libbogus14.a \
 # RUN:   2>&1 | FileCheck -check-prefix=bogus14 %s 
 
 # bogus14: -rw-r--r--124/0     102 (date: "1foobar273" contains non-decimal chars) hello.c
diff --git a/llvm/test/tools/llvm-objdump/wasm/file-headers-unsupported.test b/llvm/test/tools/llvm-objdump/wasm/file-headers-unsupported.test
index f9fc118842088..75574f16829be 100644
--- a/llvm/test/tools/llvm-objdump/wasm/file-headers-unsupported.test
+++ b/llvm/test/tools/llvm-objdump/wasm/file-headers-unsupported.test
@@ -1,3 +1,3 @@
-# RUN: not llvm-objdump -file-headers %p/Inputs/trivial.obj.wasm 2>&1 | FileCheck %s
+# RUN: not llvm-objdump --file-headers %p/Inputs/trivial.obj.wasm 2>&1 | FileCheck %s
 
 # CHECK: Invalid/Unsupported object file format
diff --git a/llvm/test/tools/llvm-objdump/wasm/wasm.txt b/llvm/test/tools/llvm-objdump/wasm/wasm.txt
index 6c4deacdf9f2e..dbe8f7652bf73 100644
--- a/llvm/test/tools/llvm-objdump/wasm/wasm.txt
+++ b/llvm/test/tools/llvm-objdump/wasm/wasm.txt
@@ -10,12 +10,12 @@
 # CHECK-NEXT:   5 linking       0000006d 00000000
 # CHECK-NEXT:   6 reloc.CODE    0000000f 00000000
 
-# RUN: llvm-objdump -p %p/Inputs/trivial.obj.wasm | FileCheck %s -check-prefix CHECK-HEADER
+# RUN: llvm-objdump -p %p/Inputs/trivial.obj.wasm | FileCheck %s --check-prefix CHECK-HEADER
 
 # CHECK-HEADER: Program Header:
 # CHECK-HEADER: Version: 0x1
 
-# RUN: llvm-objdump -s --section=CODE %p/Inputs/trivial.obj.wasm | FileCheck %s -check-prefix CHECK-SECTIONS
+# RUN: llvm-objdump -s --section=CODE %p/Inputs/trivial.obj.wasm | FileCheck %s --check-prefix CHECK-SECTIONS
 
 # CHECK-SECTIONS: Contents of section CODE:
 # CHECK-SECTIONS: 0000 02170041 80808080 00108080 8080001a  ...A............
diff --git a/llvm/test/tools/llvm-readobj/COFF/Inputs/has-cet.exe b/llvm/test/tools/llvm-readobj/COFF/Inputs/has-cet.exe
new file mode 100644
index 0000000000000..c77060d976d2f
Binary files /dev/null and b/llvm/test/tools/llvm-readobj/COFF/Inputs/has-cet.exe differ
diff --git a/llvm/test/tools/llvm-readobj/COFF/cetcompat.test b/llvm/test/tools/llvm-readobj/COFF/cetcompat.test
new file mode 100644
index 0000000000000..a973b5c0a2080
--- /dev/null
+++ b/llvm/test/tools/llvm-readobj/COFF/cetcompat.test
@@ -0,0 +1,16 @@
+# To regenerate has-cet.exe
+# $ echo int main() { return 0; } > has-cet.c
+# $ cl has-cet.c /link /cetcompat
+RUN: llvm-readobj --coff-debug-directory %p/Inputs/has-cet.exe | FileCheck %s
+
+CHECK:  DebugEntry {
+CHECK:    Characteristics: 0x0
+CHECK:    Type: ExtendedDLLCharacteristics (0x14)
+CHECK:    ExtendedCharacteristics [ (0x1)
+CHECK:      IMAGE_DLL_CHARACTERISTICS_EX_CET_COMPAT (0x1)
+CHECK:    ]
+CHECK:    RawData (
+CHECK:      0000: 01000000                             |....|
+CHECK:    )
+CHECK:  }
+
diff --git a/llvm/test/tools/llvm-readobj/ELF/all.test b/llvm/test/tools/llvm-readobj/ELF/all.test
index f792143b9537c..39783613e789c 100644
--- a/llvm/test/tools/llvm-readobj/ELF/all.test
+++ b/llvm/test/tools/llvm-readobj/ELF/all.test
@@ -2,7 +2,7 @@
 # RUN: llvm-readobj -a %t.o | FileCheck %s --check-prefix LLVM-ALL
 # RUN: llvm-readobj --all %t.o | FileCheck %s --check-prefix LLVM-ALL
 
-# LLVM-ALL: Format: ELF32-i386
+# LLVM-ALL: Format: elf32-i386
 # LLVM-ALL: Arch: i386
 # LLVM-ALL: AddressSize: 32bit
 # LLVM-ALL: LoadName:
diff --git a/llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-definitions.test b/llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-definitions.test
index 24dcc7c052beb..cb0e6213cafd1 100644
--- a/llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-definitions.test
+++ b/llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-definitions.test
@@ -1,6 +1,6 @@
 RUN: llvm-readobj --file-headers -l -S --symbols %p/Inputs/trivial.obj.elf-amdhsa-gfx803 | FileCheck %s
 
-CHECK: Format: ELF64-amdgpu
+CHECK: Format: elf64-amdgpu
 CHECK: Arch: unknown
 CHECK: ElfHeader {
 CHECK:   Ident {
diff --git a/llvm/test/tools/llvm-readobj/ELF/basic.test b/llvm/test/tools/llvm-readobj/ELF/basic.test
index 1d273b8b927ff..608ad34e2b493 100644
--- a/llvm/test/tools/llvm-readobj/ELF/basic.test
+++ b/llvm/test/tools/llvm-readobj/ELF/basic.test
@@ -5,7 +5,7 @@
 # RUN: llvm-readelf %t.trivial.obj.elf-x86-64 | FileCheck --check-prefix=NO-OUTPUT --allow-empty %s
 
 # HEADER: File: {{.*}}trivial.obj.elf-x86-64
-# HEADER: Format: ELF64-x86-64
+# HEADER: Format: elf64-x86-64
 # HEADER: Arch: x86_64
 # HEADER: AddressSize: 64bit
 
diff --git a/llvm/test/tools/llvm-readobj/ELF/dynamic-no-pt-dynamic.test b/llvm/test/tools/llvm-readobj/ELF/dynamic-no-pt-dynamic.test
index 8fa7f655249f6..f5c95d7d66d0e 100644
--- a/llvm/test/tools/llvm-readobj/ELF/dynamic-no-pt-dynamic.test
+++ b/llvm/test/tools/llvm-readobj/ELF/dynamic-no-pt-dynamic.test
@@ -5,7 +5,7 @@
 # RUN: llvm-readelf --dynamic-table %t.no-phdr | FileCheck %s --check-prefix=GNU
 
 # LLVM:      File: {{.*}}.no-phdr
-# LLVM-NEXT: Format: ELF64-x86-64
+# LLVM-NEXT: Format: elf64-x86-64
 # LLVM-NEXT: Arch: x86_64
 # LLVM-NEXT: AddressSize: 64bit
 # LLVM-NEXT: LoadName:{{ *}}
diff --git a/llvm/test/tools/llvm-readobj/ELF/file-headers.test b/llvm/test/tools/llvm-readobj/ELF/file-headers.test
index d3282c804cc40..99cbfdf5e8c7e 100644
--- a/llvm/test/tools/llvm-readobj/ELF/file-headers.test
+++ b/llvm/test/tools/llvm-readobj/ELF/file-headers.test
@@ -4,7 +4,7 @@
 # RUN: llvm-readobj --file-headers %t.i386 | FileCheck %s --strict-whitespace --match-full-lines -DFILE=%t.i386 --check-prefix I386
 
 #      I386:File: [[FILE]]
-# I386-NEXT:Format: ELF32-i386
+# I386-NEXT:Format: elf32-i386
 # I386-NEXT:Arch: i386
 # I386-NEXT:AddressSize: 32bit
 # I386-NEXT:LoadName: <Not found>
@@ -52,7 +52,7 @@ FileHeader:
 # RUN:  | FileCheck %s --strict-whitespace --match-full-lines -DFILE=%t.x86-64 --check-prefix X86-64
 
 #      X86-64:File: [[FILE]]
-# X86-64-NEXT:Format: ELF64-x86-64
+# X86-64-NEXT:Format: elf64-x86-64
 # X86-64-NEXT:Arch: x86_64
 # X86-64-NEXT:AddressSize: 64bit
 # X86-64-NEXT:LoadName: <Not found>
@@ -107,7 +107,7 @@ FileHeader:
   Machine: EM_LANAI
 
 #      LANAI:File: [[FILE]]
-# LANAI-NEXT:Format: ELF32-lanai
+# LANAI-NEXT:Format: elf32-lanai
 # LANAI-NEXT:Arch: lanai
 # LANAI-NEXT:AddressSize: 32bit
 # LANAI-NEXT:LoadName: <Not found>
diff --git a/llvm/test/tools/llvm-readobj/ELF/loadname.test b/llvm/test/tools/llvm-readobj/ELF/loadname.test
index c29ee33ae7e64..7bd64fd27fa7f 100644
--- a/llvm/test/tools/llvm-readobj/ELF/loadname.test
+++ b/llvm/test/tools/llvm-readobj/ELF/loadname.test
@@ -4,7 +4,7 @@
 # RUN: llvm-readobj %t.o | FileCheck %s --check-prefix LLVM
 # RUN: llvm-readelf --dynamic-table %t.o | FileCheck %s --check-prefix GNU
 
-# LLVM:      Format: ELF64-x86-64
+# LLVM:      Format: elf64-x86-64
 # LLVM-NEXT: Arch: x86_64
 # LLVM-NEXT: AddressSize: 64bit
 # LLVM-NEXT: LoadName: test.so
diff --git a/llvm/test/tools/llvm-readobj/ELF/no-action.test b/llvm/test/tools/llvm-readobj/ELF/no-action.test
index 964db74bf3067..b18c900438542 100644
--- a/llvm/test/tools/llvm-readobj/ELF/no-action.test
+++ b/llvm/test/tools/llvm-readobj/ELF/no-action.test
@@ -7,7 +7,7 @@
 # RUN: llvm-readelf %t.exe | FileCheck %s -DFILE=%t.exe --check-prefix GNU --allow-empty
 
 # LLVM: File: [[FILE]]
-# LLVM: Format: ELF64-x86-64
+# LLVM: Format: elf64-x86-64
 # LLVM: Arch: x86_64
 # LLVM: AddressSize: 64bit
 # LLVM: LoadName: <Not found>{{$}}
diff --git a/llvm/test/tools/llvm-readobj/ELF/ppc64-glink.test b/llvm/test/tools/llvm-readobj/ELF/ppc64-glink.test
index ac361784e06da..d173c985b5f27 100644
--- a/llvm/test/tools/llvm-readobj/ELF/ppc64-glink.test
+++ b/llvm/test/tools/llvm-readobj/ELF/ppc64-glink.test
@@ -2,7 +2,7 @@
 
 RUN: llvm-readobj --dynamic-table %p/Inputs/ppc64.exe | FileCheck %s
 
-CHECK: Format: ELF64-ppc64
+CHECK: Format: elf64-powerpc
 CHECK: Arch: powerpc64le
 CHECK: AddressSize: 64bit
 
diff --git a/llvm/test/tools/llvm-readobj/ELF/program-headers.test b/llvm/test/tools/llvm-readobj/ELF/program-headers.test
index 119b3a4d9f0d0..8ab5f65c02ce7 100644
--- a/llvm/test/tools/llvm-readobj/ELF/program-headers.test
+++ b/llvm/test/tools/llvm-readobj/ELF/program-headers.test
@@ -79,7 +79,7 @@
 # RUN: llvm-readobj -l %p/../../../Object/Inputs/program-headers.mips \
 # RUN:     | FileCheck %s -check-prefix ELF-MIPS
 
-# ELF-MIPS:      Format: ELF32-mips
+# ELF-MIPS:      Format: elf32-mips
 # ELF-MIPS-NEXT: Arch: mips
 # ELF-MIPS-NEXT: AddressSize: 32bit
 # ELF-MIPS-NEXT: LoadName:
@@ -126,7 +126,7 @@
 # RUN: llvm-readobj -l %p/../../../Object/Inputs/program-headers.mips64 \
 # RUN:     | FileCheck %s -check-prefix ELF-MIPS64
 
-# ELF-MIPS64:      Format: ELF64-mips
+# ELF-MIPS64:      Format: elf64-mips
 # ELF-MIPS64-NEXT: Arch: mips64
 # ELF-MIPS64-NEXT: AddressSize: 64bit
 # ELF-MIPS64-NEXT: LoadName:
diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-aarch64.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-aarch64.test
index 8245a1564c11c..c95265d520a17 100644
--- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-aarch64.test
+++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-aarch64.test
@@ -144,248 +144,126 @@ Sections:
     EntSize:      0x0000000000000018
     Info:         .text
     Relocations:
-      - Type:   R_AARCH64_NONE
-      - Offset: 0x0000000000000004
-        Type:   R_AARCH64_ABS64
-      - Offset: 0x0000000000000008
-        Type:   R_AARCH64_ABS32
-      - Offset: 0x000000000000000C
-        Type:   R_AARCH64_ABS16
-      - Offset: 0x0000000000000010
-        Type:   R_AARCH64_PREL64
-      - Offset: 0x0000000000000014
-        Type:   R_AARCH64_PREL32
-      - Offset: 0x0000000000000018
-        Type:   R_AARCH64_PREL16
-      - Offset: 0x000000000000001C
-        Type:   R_AARCH64_MOVW_UABS_G0
-      - Offset: 0x0000000000000020
-        Type:   R_AARCH64_MOVW_UABS_G0_NC
-      - Offset: 0x0000000000000024
-        Type:   R_AARCH64_MOVW_UABS_G1
-      - Offset: 0x0000000000000028
-        Type:   R_AARCH64_MOVW_UABS_G1_NC
-      - Offset: 0x000000000000002C
-        Type:   R_AARCH64_MOVW_UABS_G2
-      - Offset: 0x0000000000000030
-        Type:   R_AARCH64_MOVW_UABS_G2_NC
-      - Offset: 0x0000000000000034
-        Type:   R_AARCH64_MOVW_UABS_G3
-      - Offset: 0x0000000000000038
-        Type:   R_AARCH64_MOVW_SABS_G0
-      - Offset: 0x000000000000003C
-        Type:   R_AARCH64_MOVW_SABS_G1
-      - Offset: 0x0000000000000040
-        Type:   R_AARCH64_MOVW_SABS_G2
-      - Offset: 0x0000000000000044
-        Type:   R_AARCH64_LD_PREL_LO19
-      - Offset: 0x0000000000000048
-        Type:   R_AARCH64_ADR_PREL_LO21
-      - Offset: 0x000000000000004C
-        Type:   R_AARCH64_ADR_PREL_PG_HI21
-      - Offset: 0x0000000000000050
-        Type:   R_AARCH64_ADR_PREL_PG_HI21_NC
-      - Offset: 0x0000000000000054
-        Type:   R_AARCH64_ADD_ABS_LO12_NC
-      - Offset: 0x0000000000000058
-        Type:   R_AARCH64_LDST8_ABS_LO12_NC
-      - Offset: 0x000000000000005C
-        Type:   R_AARCH64_TSTBR14
-      - Offset: 0x0000000000000060
-        Type:   R_AARCH64_CONDBR19
-      - Offset: 0x0000000000000064
-        Type:   R_AARCH64_JUMP26
-      - Offset: 0x0000000000000068
-        Type:   R_AARCH64_CALL26
-      - Offset: 0x000000000000006C
-        Type:   R_AARCH64_LDST16_ABS_LO12_NC
-      - Offset: 0x0000000000000070
-        Type:   R_AARCH64_LDST32_ABS_LO12_NC
-      - Offset: 0x0000000000000074
-        Type:   R_AARCH64_LDST64_ABS_LO12_NC
-      - Offset: 0x0000000000000078
-        Type:   R_AARCH64_MOVW_PREL_G0
-      - Offset: 0x000000000000007C
-        Type:   R_AARCH64_MOVW_PREL_G0_NC
-      - Offset: 0x0000000000000080
-        Type:   R_AARCH64_MOVW_PREL_G1
-      - Offset: 0x0000000000000084
-        Type:   R_AARCH64_MOVW_PREL_G1_NC
-      - Offset: 0x0000000000000088
-        Type:   R_AARCH64_MOVW_PREL_G2
-      - Offset: 0x000000000000008C
-        Type:   R_AARCH64_MOVW_PREL_G2_NC
-      - Offset: 0x0000000000000090
-        Type:   R_AARCH64_MOVW_PREL_G3
-      - Offset: 0x0000000000000094
-        Type:   R_AARCH64_LDST128_ABS_LO12_NC
-      - Offset: 0x0000000000000098
-        Type:   R_AARCH64_MOVW_GOTOFF_G0
-      - Offset: 0x000000000000009C
-        Type:   R_AARCH64_MOVW_GOTOFF_G0_NC
-      - Offset: 0x00000000000000A0
-        Type:   R_AARCH64_MOVW_GOTOFF_G1
-      - Offset: 0x00000000000000A4
-        Type:   R_AARCH64_MOVW_GOTOFF_G1_NC
-      - Offset: 0x00000000000000A8
-        Type:   R_AARCH64_MOVW_GOTOFF_G2
-      - Offset: 0x00000000000000AC
-        Type:   R_AARCH64_MOVW_GOTOFF_G2_NC
-      - Offset: 0x00000000000000B0
-        Type:   R_AARCH64_MOVW_GOTOFF_G3
-      - Offset: 0x00000000000000B4
-        Type:   R_AARCH64_GOTREL64
-      - Offset: 0x00000000000000B8
-        Type:   R_AARCH64_GOTREL32
-      - Offset: 0x00000000000000BC
-        Type:   R_AARCH64_GOT_LD_PREL19
-      - Offset: 0x00000000000000C0
-        Type:   R_AARCH64_LD64_GOTOFF_LO15
-      - Offset: 0x00000000000000C4
-        Type:   R_AARCH64_ADR_GOT_PAGE
-      - Offset: 0x00000000000000C8
-        Type:   R_AARCH64_LD64_GOT_LO12_NC
-      - Offset: 0x00000000000000CC
-        Type:   R_AARCH64_LD64_GOTPAGE_LO15
-      - Offset: 0x00000000000000D0
-        Type:   R_AARCH64_TLSGD_ADR_PREL21
-      - Offset: 0x00000000000000D4
-        Type:   R_AARCH64_TLSGD_ADR_PAGE21
-      - Offset: 0x00000000000000D8
-        Type:   R_AARCH64_TLSGD_ADD_LO12_NC
-      - Offset: 0x00000000000000DC
-        Type:   R_AARCH64_TLSGD_MOVW_G1
-      - Offset: 0x00000000000000E0
-        Type:   R_AARCH64_TLSGD_MOVW_G0_NC
-      - Offset: 0x00000000000000E4
-        Type:   R_AARCH64_TLSLD_ADR_PREL21
-      - Offset: 0x00000000000000E8
-        Type:   R_AARCH64_TLSLD_ADR_PAGE21
-      - Offset: 0x00000000000000EC
-        Type:   R_AARCH64_TLSLD_ADD_LO12_NC
-      - Offset: 0x00000000000000F0
-        Type:   R_AARCH64_TLSLD_MOVW_G1
-      - Offset: 0x00000000000000F4
-        Type:   R_AARCH64_TLSLD_MOVW_G0_NC
-      - Offset: 0x00000000000000F8
-        Type:   R_AARCH64_TLSLD_LD_PREL19
-      - Offset: 0x00000000000000FC
-        Type:   R_AARCH64_TLSLD_MOVW_DTPREL_G2
-      - Offset: 0x0000000000000100
-        Type:   R_AARCH64_TLSLD_MOVW_DTPREL_G1
-      - Offset: 0x0000000000000104
-        Type:   R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
-      - Offset: 0x0000000000000108
-        Type:   R_AARCH64_TLSLD_MOVW_DTPREL_G0
-      - Offset: 0x000000000000010C
-        Type:   R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
-      - Offset: 0x0000000000000110
-        Type:   R_AARCH64_TLSLD_ADD_DTPREL_HI12
-      - Offset: 0x0000000000000114
-        Type:   R_AARCH64_TLSLD_ADD_DTPREL_LO12
-      - Offset: 0x0000000000000118
-        Type:   R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
-      - Offset: 0x000000000000011C
-        Type:   R_AARCH64_TLSLD_LDST8_DTPREL_LO12
-      - Offset: 0x0000000000000120
-        Type:   R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
-      - Offset: 0x0000000000000124
-        Type:   R_AARCH64_TLSLD_LDST16_DTPREL_LO12
-      - Offset: 0x0000000000000128
-        Type:   R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
-      - Offset: 0x000000000000012C
-        Type:   R_AARCH64_TLSLD_LDST32_DTPREL_LO12
-      - Offset: 0x0000000000000130
-        Type:   R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
-      - Offset: 0x0000000000000134
-        Type:   R_AARCH64_TLSLD_LDST64_DTPREL_LO12
-      - Offset: 0x0000000000000138
-        Type:   R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
-      - Offset: 0x000000000000013C
-        Type:   R_AARCH64_TLSIE_MOVW_GOTTPREL_G1
-      - Offset: 0x0000000000000140
-        Type:   R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
-      - Offset: 0x0000000000000144
-        Type:   R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
-      - Offset: 0x0000000000000148
-        Type:   R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
-      - Offset: 0x000000000000014C
-        Type:   R_AARCH64_TLSIE_LD_GOTTPREL_PREL19
-      - Offset: 0x0000000000000150
-        Type:   R_AARCH64_TLSLE_MOVW_TPREL_G2
-      - Offset: 0x0000000000000154
-        Type:   R_AARCH64_TLSLE_MOVW_TPREL_G1
-      - Offset: 0x0000000000000158
-        Type:   R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
-      - Offset: 0x000000000000015C
-        Type:   R_AARCH64_TLSLE_MOVW_TPREL_G0
-      - Offset: 0x0000000000000160
-        Type:   R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
-      - Offset: 0x0000000000000164
-        Type:   R_AARCH64_TLSLE_ADD_TPREL_HI12
-      - Offset: 0x0000000000000168
-        Type:   R_AARCH64_TLSLE_ADD_TPREL_LO12
-      - Offset: 0x000000000000016C
-        Type:   R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
-      - Offset: 0x0000000000000170
-        Type:   R_AARCH64_TLSLE_LDST8_TPREL_LO12
-      - Offset: 0x0000000000000174
-        Type:   R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
-      - Offset: 0x0000000000000178
-        Type:   R_AARCH64_TLSLE_LDST16_TPREL_LO12
-      - Offset: 0x000000000000017C
-        Type:   R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
-      - Offset: 0x0000000000000180
-        Type:   R_AARCH64_TLSLE_LDST32_TPREL_LO12
-      - Offset: 0x0000000000000184
-        Type:   R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
-      - Offset: 0x0000000000000188
-        Type:   R_AARCH64_TLSLE_LDST64_TPREL_LO12
-      - Offset: 0x000000000000018C
-        Type:   R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
-      - Offset: 0x0000000000000190
-        Type:   R_AARCH64_TLSDESC_LD_PREL19
-      - Offset: 0x0000000000000194
-        Type:   R_AARCH64_TLSDESC_ADR_PREL21
-      - Offset: 0x0000000000000198
-        Type:   R_AARCH64_TLSDESC_ADR_PAGE21
-      - Offset: 0x000000000000019C
-        Type:   R_AARCH64_TLSDESC_LD64_LO12
-      - Offset: 0x00000000000001A0
-        Type:   R_AARCH64_TLSDESC_ADD_LO12
-      - Offset: 0x00000000000001A4
-        Type:   R_AARCH64_TLSDESC_OFF_G1
-      - Offset: 0x00000000000001A8
-        Type:   R_AARCH64_TLSDESC_OFF_G0_NC
-      - Offset: 0x00000000000001AC
-        Type:   R_AARCH64_TLSDESC_LDR
-      - Offset: 0x00000000000001B0
-        Type:   R_AARCH64_TLSDESC_ADD
-      - Offset: 0x00000000000001B4
-        Type:   R_AARCH64_TLSDESC_CALL
-      - Offset: 0x00000000000001B8
-        Type:   R_AARCH64_TLSLE_LDST128_TPREL_LO12
-      - Offset: 0x00000000000001BC
-        Type:   R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC
-      - Offset: 0x00000000000001C0
-        Type:   R_AARCH64_TLSLD_LDST128_DTPREL_LO12
-      - Offset: 0x00000000000001C4
-        Type:   R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC
-      - Offset: 0x00000000000001C8
-        Type:   R_AARCH64_COPY
-      - Offset: 0x00000000000001CC
-        Type:   R_AARCH64_GLOB_DAT
-      - Offset: 0x00000000000001D0
-        Type:   R_AARCH64_JUMP_SLOT
-      - Offset: 0x00000000000001D4
-        Type:   R_AARCH64_RELATIVE
-      - Offset: 0x00000000000001D8
-        Type:   R_AARCH64_TLS_DTPMOD64
-      - Offset: 0x00000000000001DC
-        Type:   R_AARCH64_TLS_DTPREL64
-      - Offset: 0x00000000000001E0
-        Type:   R_AARCH64_TLS_TPREL64
-      - Offset: 0x00000000000001E4
-        Type:   R_AARCH64_TLSDESC
-      - Offset: 0x00000000000001E8
-        Type:   R_AARCH64_IRELATIVE
+      - Type: R_AARCH64_NONE
+      - Type: R_AARCH64_ABS64
+      - Type: R_AARCH64_ABS32
+      - Type: R_AARCH64_ABS16
+      - Type: R_AARCH64_PREL64
+      - Type: R_AARCH64_PREL32
+      - Type: R_AARCH64_PREL16
+      - Type: R_AARCH64_MOVW_UABS_G0
+      - Type: R_AARCH64_MOVW_UABS_G0_NC
+      - Type: R_AARCH64_MOVW_UABS_G1
+      - Type: R_AARCH64_MOVW_UABS_G1_NC
+      - Type: R_AARCH64_MOVW_UABS_G2
+      - Type: R_AARCH64_MOVW_UABS_G2_NC
+      - Type: R_AARCH64_MOVW_UABS_G3
+      - Type: R_AARCH64_MOVW_SABS_G0
+      - Type: R_AARCH64_MOVW_SABS_G1
+      - Type: R_AARCH64_MOVW_SABS_G2
+      - Type: R_AARCH64_LD_PREL_LO19
+      - Type: R_AARCH64_ADR_PREL_LO21
+      - Type: R_AARCH64_ADR_PREL_PG_HI21
+      - Type: R_AARCH64_ADR_PREL_PG_HI21_NC
+      - Type: R_AARCH64_ADD_ABS_LO12_NC
+      - Type: R_AARCH64_LDST8_ABS_LO12_NC
+      - Type: R_AARCH64_TSTBR14
+      - Type: R_AARCH64_CONDBR19
+      - Type: R_AARCH64_JUMP26
+      - Type: R_AARCH64_CALL26
+      - Type: R_AARCH64_LDST16_ABS_LO12_NC
+      - Type: R_AARCH64_LDST32_ABS_LO12_NC
+      - Type: R_AARCH64_LDST64_ABS_LO12_NC
+      - Type: R_AARCH64_MOVW_PREL_G0
+      - Type: R_AARCH64_MOVW_PREL_G0_NC
+      - Type: R_AARCH64_MOVW_PREL_G1
+      - Type: R_AARCH64_MOVW_PREL_G1_NC
+      - Type: R_AARCH64_MOVW_PREL_G2
+      - Type: R_AARCH64_MOVW_PREL_G2_NC
+      - Type: R_AARCH64_MOVW_PREL_G3
+      - Type: R_AARCH64_LDST128_ABS_LO12_NC
+      - Type: R_AARCH64_MOVW_GOTOFF_G0
+      - Type: R_AARCH64_MOVW_GOTOFF_G0_NC
+      - Type: R_AARCH64_MOVW_GOTOFF_G1
+      - Type: R_AARCH64_MOVW_GOTOFF_G1_NC
+      - Type: R_AARCH64_MOVW_GOTOFF_G2
+      - Type: R_AARCH64_MOVW_GOTOFF_G2_NC
+      - Type: R_AARCH64_MOVW_GOTOFF_G3
+      - Type: R_AARCH64_GOTREL64
+      - Type: R_AARCH64_GOTREL32
+      - Type: R_AARCH64_GOT_LD_PREL19
+      - Type: R_AARCH64_LD64_GOTOFF_LO15
+      - Type: R_AARCH64_ADR_GOT_PAGE
+      - Type: R_AARCH64_LD64_GOT_LO12_NC
+      - Type: R_AARCH64_LD64_GOTPAGE_LO15
+      - Type: R_AARCH64_TLSGD_ADR_PREL21
+      - Type: R_AARCH64_TLSGD_ADR_PAGE21
+      - Type: R_AARCH64_TLSGD_ADD_LO12_NC
+      - Type: R_AARCH64_TLSGD_MOVW_G1
+      - Type: R_AARCH64_TLSGD_MOVW_G0_NC
+      - Type: R_AARCH64_TLSLD_ADR_PREL21
+      - Type: R_AARCH64_TLSLD_ADR_PAGE21
+      - Type: R_AARCH64_TLSLD_ADD_LO12_NC
+      - Type: R_AARCH64_TLSLD_MOVW_G1
+      - Type: R_AARCH64_TLSLD_MOVW_G0_NC
+      - Type: R_AARCH64_TLSLD_LD_PREL19
+      - Type: R_AARCH64_TLSLD_MOVW_DTPREL_G2
+      - Type: R_AARCH64_TLSLD_MOVW_DTPREL_G1
+      - Type: R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
+      - Type: R_AARCH64_TLSLD_MOVW_DTPREL_G0
+      - Type: R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
+      - Type: R_AARCH64_TLSLD_ADD_DTPREL_HI12
+      - Type: R_AARCH64_TLSLD_ADD_DTPREL_LO12
+      - Type: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
+      - Type: R_AARCH64_TLSLD_LDST8_DTPREL_LO12
+      - Type: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
+      - Type: R_AARCH64_TLSLD_LDST16_DTPREL_LO12
+      - Type: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
+      - Type: R_AARCH64_TLSLD_LDST32_DTPREL_LO12
+      - Type: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
+      - Type: R_AARCH64_TLSLD_LDST64_DTPREL_LO12
+      - Type: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
+      - Type: R_AARCH64_TLSIE_MOVW_GOTTPREL_G1
+      - Type: R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
+      - Type: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
+      - Type: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
+      - Type: R_AARCH64_TLSIE_LD_GOTTPREL_PREL19
+      - Type: R_AARCH64_TLSLE_MOVW_TPREL_G2
+      - Type: R_AARCH64_TLSLE_MOVW_TPREL_G1
+      - Type: R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+      - Type: R_AARCH64_TLSLE_MOVW_TPREL_G0
+      - Type: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
+      - Type: R_AARCH64_TLSLE_ADD_TPREL_HI12
+      - Type: R_AARCH64_TLSLE_ADD_TPREL_LO12
+      - Type: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
+      - Type: R_AARCH64_TLSLE_LDST8_TPREL_LO12
+      - Type: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
+      - Type: R_AARCH64_TLSLE_LDST16_TPREL_LO12
+      - Type: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
+      - Type: R_AARCH64_TLSLE_LDST32_TPREL_LO12
+      - Type: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
+      - Type: R_AARCH64_TLSLE_LDST64_TPREL_LO12
+      - Type: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
+      - Type: R_AARCH64_TLSDESC_LD_PREL19
+      - Type: R_AARCH64_TLSDESC_ADR_PREL21
+      - Type: R_AARCH64_TLSDESC_ADR_PAGE21
+      - Type: R_AARCH64_TLSDESC_LD64_LO12
+      - Type: R_AARCH64_TLSDESC_ADD_LO12
+      - Type: R_AARCH64_TLSDESC_OFF_G1
+      - Type: R_AARCH64_TLSDESC_OFF_G0_NC
+      - Type: R_AARCH64_TLSDESC_LDR
+      - Type: R_AARCH64_TLSDESC_ADD
+      - Type: R_AARCH64_TLSDESC_CALL
+      - Type: R_AARCH64_TLSLE_LDST128_TPREL_LO12
+      - Type: R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC
+      - Type: R_AARCH64_TLSLD_LDST128_DTPREL_LO12
+      - Type: R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC
+      - Type: R_AARCH64_COPY
+      - Type: R_AARCH64_GLOB_DAT
+      - Type: R_AARCH64_JUMP_SLOT
+      - Type: R_AARCH64_RELATIVE
+      - Type: R_AARCH64_TLS_DTPMOD64
+      - Type: R_AARCH64_TLS_DTPREL64
+      - Type: R_AARCH64_TLS_TPREL64
+      - Type: R_AARCH64_TLSDESC
+      - Type: R_AARCH64_IRELATIVE
diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-arm.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-arm.test
index 2bd08c9f7f6e8..f72d7cdd89138 100644
--- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-arm.test
+++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-arm.test
@@ -153,266 +153,135 @@ Sections:
     EntSize:      0x0000000000000008
     Info:         .text
     Relocations:
-      - Type:   R_ARM_NONE
-      - Offset: 0x0000000000000004
-        Type:   R_ARM_PC24
-      - Offset: 0x0000000000000008
-        Type:   R_ARM_ABS32
-      - Offset: 0x000000000000000C
-        Type:   R_ARM_REL32
-      - Offset: 0x0000000000000010
-        Type:   R_ARM_LDR_PC_G0
-      - Offset: 0x0000000000000014
-        Type:   R_ARM_ABS16
-      - Offset: 0x0000000000000018
-        Type:   R_ARM_ABS12
-      - Offset: 0x000000000000001C
-        Type:   R_ARM_THM_ABS5
-      - Offset: 0x0000000000000020
-        Type:   R_ARM_ABS8
-      - Offset: 0x0000000000000024
-        Type:   R_ARM_SBREL32
-      - Offset: 0x0000000000000028
-        Type:   R_ARM_THM_CALL
-      - Offset: 0x000000000000002C
-        Type:   R_ARM_THM_PC8
-      - Offset: 0x0000000000000030
-        Type:   R_ARM_BREL_ADJ
-      - Offset: 0x0000000000000034
-        Type:   R_ARM_TLS_DESC
-      - Offset: 0x0000000000000038
-        Type:   R_ARM_THM_SWI8
-      - Offset: 0x000000000000003C
-        Type:   R_ARM_XPC25
-      - Offset: 0x0000000000000040
-        Type:   R_ARM_THM_XPC22
-      - Offset: 0x0000000000000044
-        Type:   R_ARM_TLS_DTPMOD32
-      - Offset: 0x0000000000000048
-        Type:   R_ARM_TLS_DTPOFF32
-      - Offset: 0x000000000000004C
-        Type:   R_ARM_TLS_TPOFF32
-      - Offset: 0x0000000000000050
-        Type:   R_ARM_COPY
-      - Offset: 0x0000000000000054
-        Type:   R_ARM_GLOB_DAT
-      - Offset: 0x0000000000000058
-        Type:   R_ARM_JUMP_SLOT
-      - Offset: 0x000000000000005C
-        Type:   R_ARM_RELATIVE
-      - Offset: 0x0000000000000060
-        Type:   R_ARM_GOTOFF32
-      - Offset: 0x0000000000000064
-        Type:   R_ARM_BASE_PREL
-      - Offset: 0x0000000000000068
-        Type:   R_ARM_GOT_BREL
-      - Offset: 0x000000000000006C
-        Type:   R_ARM_PLT32
-      - Offset: 0x0000000000000070
-        Type:   R_ARM_CALL
-      - Offset: 0x0000000000000074
-        Type:   R_ARM_JUMP24
-      - Offset: 0x0000000000000078
-        Type:   R_ARM_THM_JUMP24
-      - Offset: 0x000000000000007C
-        Type:   R_ARM_BASE_ABS
-      - Offset: 0x0000000000000080
-        Type:   R_ARM_ALU_PCREL_7_0
-      - Offset: 0x0000000000000084
-        Type:   R_ARM_ALU_PCREL_15_8
-      - Offset: 0x0000000000000088
-        Type:   R_ARM_ALU_PCREL_23_15
-      - Offset: 0x000000000000008C
-        Type:   R_ARM_LDR_SBREL_11_0_NC
-      - Offset: 0x0000000000000090
-        Type:   R_ARM_ALU_SBREL_19_12_NC
-      - Offset: 0x0000000000000094
-        Type:   R_ARM_ALU_SBREL_27_20_CK
-      - Offset: 0x0000000000000098
-        Type:   R_ARM_TARGET1
-      - Offset: 0x000000000000009C
-        Type:   R_ARM_SBREL31
-      - Offset: 0x00000000000000A0
-        Type:   R_ARM_V4BX
-      - Offset: 0x00000000000000A4
-        Type:   R_ARM_TARGET2
-      - Offset: 0x00000000000000A8
-        Type:   R_ARM_PREL31
-      - Offset: 0x00000000000000AC
-        Type:   R_ARM_MOVW_ABS_NC
-      - Offset: 0x00000000000000B0
-        Type:   R_ARM_MOVT_ABS
-      - Offset: 0x00000000000000B4
-        Type:   R_ARM_MOVW_PREL_NC
-      - Offset: 0x00000000000000B8
-        Type:   R_ARM_MOVT_PREL
-      - Offset: 0x00000000000000BC
-        Type:   R_ARM_THM_MOVW_ABS_NC
-      - Offset: 0x00000000000000C0
-        Type:   R_ARM_THM_MOVT_ABS
-      - Offset: 0x00000000000000C4
-        Type:   R_ARM_THM_MOVW_PREL_NC
-      - Offset: 0x00000000000000C8
-        Type:   R_ARM_THM_MOVT_PREL
-      - Offset: 0x00000000000000CC
-        Type:   R_ARM_THM_JUMP19
-      - Offset: 0x00000000000000D0
-        Type:   R_ARM_THM_JUMP6
-      - Offset: 0x00000000000000D4
-        Type:   R_ARM_THM_ALU_PREL_11_0
-      - Offset: 0x00000000000000D8
-        Type:   R_ARM_THM_PC12
-      - Offset: 0x00000000000000DC
-        Type:   R_ARM_ABS32_NOI
-      - Offset: 0x00000000000000E0
-        Type:   R_ARM_REL32_NOI
-      - Offset: 0x00000000000000E4
-        Type:   R_ARM_ALU_PC_G0_NC
-      - Offset: 0x00000000000000E8
-        Type:   R_ARM_ALU_PC_G0
-      - Offset: 0x00000000000000EC
-        Type:   R_ARM_ALU_PC_G1_NC
-      - Offset: 0x00000000000000F0
-        Type:   R_ARM_ALU_PC_G1
-      - Offset: 0x00000000000000F4
-        Type:   R_ARM_ALU_PC_G2
-      - Offset: 0x00000000000000F8
-        Type:   R_ARM_LDR_PC_G1
-      - Offset: 0x00000000000000FC
-        Type:   R_ARM_LDR_PC_G2
-      - Offset: 0x0000000000000100
-        Type:   R_ARM_LDRS_PC_G0
-      - Offset: 0x0000000000000104
-        Type:   R_ARM_LDRS_PC_G1
-      - Offset: 0x0000000000000108
-        Type:   R_ARM_LDRS_PC_G2
-      - Offset: 0x000000000000010C
-        Type:   R_ARM_LDC_PC_G0
-      - Offset: 0x0000000000000110
-        Type:   R_ARM_LDC_PC_G1
-      - Offset: 0x0000000000000114
-        Type:   R_ARM_LDC_PC_G2
-      - Offset: 0x0000000000000118
-        Type:   R_ARM_ALU_SB_G0_NC
-      - Offset: 0x000000000000011C
-        Type:   R_ARM_ALU_SB_G0
-      - Offset: 0x0000000000000120
-        Type:   R_ARM_ALU_SB_G1_NC
-      - Offset: 0x0000000000000124
-        Type:   R_ARM_ALU_SB_G1
-      - Offset: 0x0000000000000128
-        Type:   R_ARM_ALU_SB_G2
-      - Offset: 0x000000000000012C
-        Type:   R_ARM_LDR_SB_G0
-      - Offset: 0x0000000000000130
-        Type:   R_ARM_LDR_SB_G1
-      - Offset: 0x0000000000000134
-        Type:   R_ARM_LDR_SB_G2
-      - Offset: 0x0000000000000138
-        Type:   R_ARM_LDRS_SB_G0
-      - Offset: 0x000000000000013C
-        Type:   R_ARM_LDRS_SB_G1
-      - Offset: 0x0000000000000140
-        Type:   R_ARM_LDRS_SB_G2
-      - Offset: 0x0000000000000144
-        Type:   R_ARM_LDC_SB_G0
-      - Offset: 0x0000000000000148
-        Type:   R_ARM_LDC_SB_G1
-      - Offset: 0x000000000000014C
-        Type:   R_ARM_LDC_SB_G2
-      - Offset: 0x0000000000000150
-        Type:   R_ARM_MOVW_BREL_NC
-      - Offset: 0x0000000000000154
-        Type:   R_ARM_MOVT_BREL
-      - Offset: 0x0000000000000158
-        Type:   R_ARM_MOVW_BREL
-      - Offset: 0x000000000000015C
-        Type:   R_ARM_THM_MOVW_BREL_NC
-      - Offset: 0x0000000000000160
-        Type:   R_ARM_THM_MOVT_BREL
-      - Offset: 0x0000000000000164
-        Type:   R_ARM_THM_MOVW_BREL
-      - Offset: 0x0000000000000168
-        Type:   R_ARM_TLS_GOTDESC
-      - Offset: 0x000000000000016C
-        Type:   R_ARM_TLS_CALL
-      - Offset: 0x0000000000000170
-        Type:   R_ARM_TLS_DESCSEQ
-      - Offset: 0x0000000000000174
-        Type:   R_ARM_THM_TLS_CALL
-      - Offset: 0x0000000000000178
-        Type:   R_ARM_PLT32_ABS
-      - Offset: 0x000000000000017C
-        Type:   R_ARM_GOT_ABS
-      - Offset: 0x0000000000000180
-        Type:   R_ARM_GOT_PREL
-      - Offset: 0x0000000000000184
-        Type:   R_ARM_GOT_BREL12
-      - Offset: 0x0000000000000188
-        Type:   R_ARM_GOTOFF12
-      - Offset: 0x000000000000018C
-        Type:   R_ARM_GOTRELAX
-      - Offset: 0x0000000000000190
-        Type:   R_ARM_GNU_VTENTRY
-      - Offset: 0x0000000000000194
-        Type:   R_ARM_GNU_VTINHERIT
-      - Offset: 0x0000000000000198
-        Type:   R_ARM_THM_JUMP11
-      - Offset: 0x000000000000019C
-        Type:   R_ARM_THM_JUMP8
-      - Offset: 0x00000000000001A0
-        Type:   R_ARM_TLS_GD32
-      - Offset: 0x00000000000001A4
-        Type:   R_ARM_TLS_LDM32
-      - Offset: 0x00000000000001A8
-        Type:   R_ARM_TLS_LDO32
-      - Offset: 0x00000000000001AC
-        Type:   R_ARM_TLS_IE32
-      - Offset: 0x00000000000001B0
-        Type:   R_ARM_TLS_LE32
-      - Offset: 0x00000000000001B4
-        Type:   R_ARM_TLS_LDO12
-      - Offset: 0x00000000000001B8
-        Type:   R_ARM_TLS_LE12
-      - Offset: 0x00000000000001BC
-        Type:   R_ARM_TLS_IE12GP
-      - Offset: 0x00000000000001C0
-        Type:   R_ARM_PRIVATE_0
-      - Offset: 0x00000000000001C4
-        Type:   R_ARM_PRIVATE_1
-      - Offset: 0x00000000000001C8
-        Type:   R_ARM_PRIVATE_2
-      - Offset: 0x00000000000001CC
-        Type:   R_ARM_PRIVATE_3
-      - Offset: 0x00000000000001D0
-        Type:   R_ARM_PRIVATE_4
-      - Offset: 0x00000000000001D4
-        Type:   R_ARM_PRIVATE_5
-      - Offset: 0x00000000000001D8
-        Type:   R_ARM_PRIVATE_6
-      - Offset: 0x00000000000001DC
-        Type:   R_ARM_PRIVATE_7
-      - Offset: 0x00000000000001E0
-        Type:   R_ARM_PRIVATE_8
-      - Offset: 0x00000000000001E4
-        Type:   R_ARM_PRIVATE_9
-      - Offset: 0x00000000000001E8
-        Type:   R_ARM_PRIVATE_10
-      - Offset: 0x00000000000001EC
-        Type:   R_ARM_PRIVATE_11
-      - Offset: 0x00000000000001F0
-        Type:   R_ARM_PRIVATE_12
-      - Offset: 0x00000000000001F4
-        Type:   R_ARM_PRIVATE_13
-      - Offset: 0x00000000000001F8
-        Type:   R_ARM_PRIVATE_14
-      - Offset: 0x00000000000001FC
-        Type:   R_ARM_PRIVATE_15
-      - Offset: 0x0000000000000200
-        Type:   R_ARM_ME_TOO
-      - Offset: 0x0000000000000204
-        Type:   R_ARM_THM_TLS_DESCSEQ16
-      - Offset: 0x0000000000000208
-        Type:   R_ARM_THM_TLS_DESCSEQ32
-      - Offset: 0x000000000000020C
-        Type:   R_ARM_IRELATIVE
+      - Type: R_ARM_NONE
+      - Type: R_ARM_PC24
+      - Type: R_ARM_ABS32
+      - Type: R_ARM_REL32
+      - Type: R_ARM_LDR_PC_G0
+      - Type: R_ARM_ABS16
+      - Type: R_ARM_ABS12
+      - Type: R_ARM_THM_ABS5
+      - Type: R_ARM_ABS8
+      - Type: R_ARM_SBREL32
+      - Type: R_ARM_THM_CALL
+      - Type: R_ARM_THM_PC8
+      - Type: R_ARM_BREL_ADJ
+      - Type: R_ARM_TLS_DESC
+      - Type: R_ARM_THM_SWI8
+      - Type: R_ARM_XPC25
+      - Type: R_ARM_THM_XPC22
+      - Type: R_ARM_TLS_DTPMOD32
+      - Type: R_ARM_TLS_DTPOFF32
+      - Type: R_ARM_TLS_TPOFF32
+      - Type: R_ARM_COPY
+      - Type: R_ARM_GLOB_DAT
+      - Type: R_ARM_JUMP_SLOT
+      - Type: R_ARM_RELATIVE
+      - Type: R_ARM_GOTOFF32
+      - Type: R_ARM_BASE_PREL
+      - Type: R_ARM_GOT_BREL
+      - Type: R_ARM_PLT32
+      - Type: R_ARM_CALL
+      - Type: R_ARM_JUMP24
+      - Type: R_ARM_THM_JUMP24
+      - Type: R_ARM_BASE_ABS
+      - Type: R_ARM_ALU_PCREL_7_0
+      - Type: R_ARM_ALU_PCREL_15_8
+      - Type: R_ARM_ALU_PCREL_23_15
+      - Type: R_ARM_LDR_SBREL_11_0_NC
+      - Type: R_ARM_ALU_SBREL_19_12_NC
+      - Type: R_ARM_ALU_SBREL_27_20_CK
+      - Type: R_ARM_TARGET1
+      - Type: R_ARM_SBREL31
+      - Type: R_ARM_V4BX
+      - Type: R_ARM_TARGET2
+      - Type: R_ARM_PREL31
+      - Type: R_ARM_MOVW_ABS_NC
+      - Type: R_ARM_MOVT_ABS
+      - Type: R_ARM_MOVW_PREL_NC
+      - Type: R_ARM_MOVT_PREL
+      - Type: R_ARM_THM_MOVW_ABS_NC
+      - Type: R_ARM_THM_MOVT_ABS
+      - Type: R_ARM_THM_MOVW_PREL_NC
+      - Type: R_ARM_THM_MOVT_PREL
+      - Type: R_ARM_THM_JUMP19
+      - Type: R_ARM_THM_JUMP6
+      - Type: R_ARM_THM_ALU_PREL_11_0
+      - Type: R_ARM_THM_PC12
+      - Type: R_ARM_ABS32_NOI
+      - Type: R_ARM_REL32_NOI
+      - Type: R_ARM_ALU_PC_G0_NC
+      - Type: R_ARM_ALU_PC_G0
+      - Type: R_ARM_ALU_PC_G1_NC
+      - Type: R_ARM_ALU_PC_G1
+      - Type: R_ARM_ALU_PC_G2
+      - Type: R_ARM_LDR_PC_G1
+      - Type: R_ARM_LDR_PC_G2
+      - Type: R_ARM_LDRS_PC_G0
+      - Type: R_ARM_LDRS_PC_G1
+      - Type: R_ARM_LDRS_PC_G2
+      - Type: R_ARM_LDC_PC_G0
+      - Type: R_ARM_LDC_PC_G1
+      - Type: R_ARM_LDC_PC_G2
+      - Type: R_ARM_ALU_SB_G0_NC
+      - Type: R_ARM_ALU_SB_G0
+      - Type: R_ARM_ALU_SB_G1_NC
+      - Type: R_ARM_ALU_SB_G1
+      - Type: R_ARM_ALU_SB_G2
+      - Type: R_ARM_LDR_SB_G0
+      - Type: R_ARM_LDR_SB_G1
+      - Type: R_ARM_LDR_SB_G2
+      - Type: R_ARM_LDRS_SB_G0
+      - Type: R_ARM_LDRS_SB_G1
+      - Type: R_ARM_LDRS_SB_G2
+      - Type: R_ARM_LDC_SB_G0
+      - Type: R_ARM_LDC_SB_G1
+      - Type: R_ARM_LDC_SB_G2
+      - Type: R_ARM_MOVW_BREL_NC
+      - Type: R_ARM_MOVT_BREL
+      - Type: R_ARM_MOVW_BREL
+      - Type: R_ARM_THM_MOVW_BREL_NC
+      - Type: R_ARM_THM_MOVT_BREL
+      - Type: R_ARM_THM_MOVW_BREL
+      - Type: R_ARM_TLS_GOTDESC
+      - Type: R_ARM_TLS_CALL
+      - Type: R_ARM_TLS_DESCSEQ
+      - Type: R_ARM_THM_TLS_CALL
+      - Type: R_ARM_PLT32_ABS
+      - Type: R_ARM_GOT_ABS
+      - Type: R_ARM_GOT_PREL
+      - Type: R_ARM_GOT_BREL12
+      - Type: R_ARM_GOTOFF12
+      - Type: R_ARM_GOTRELAX
+      - Type: R_ARM_GNU_VTENTRY
+      - Type: R_ARM_GNU_VTINHERIT
+      - Type: R_ARM_THM_JUMP11
+      - Type: R_ARM_THM_JUMP8
+      - Type: R_ARM_TLS_GD32
+      - Type: R_ARM_TLS_LDM32
+      - Type: R_ARM_TLS_LDO32
+      - Type: R_ARM_TLS_IE32
+      - Type: R_ARM_TLS_LE32
+      - Type: R_ARM_TLS_LDO12
+      - Type: R_ARM_TLS_LE12
+      - Type: R_ARM_TLS_IE12GP
+      - Type: R_ARM_PRIVATE_0
+      - Type: R_ARM_PRIVATE_1
+      - Type: R_ARM_PRIVATE_2
+      - Type: R_ARM_PRIVATE_3
+      - Type: R_ARM_PRIVATE_4
+      - Type: R_ARM_PRIVATE_5
+      - Type: R_ARM_PRIVATE_6
+      - Type: R_ARM_PRIVATE_7
+      - Type: R_ARM_PRIVATE_8
+      - Type: R_ARM_PRIVATE_9
+      - Type: R_ARM_PRIVATE_10
+      - Type: R_ARM_PRIVATE_11
+      - Type: R_ARM_PRIVATE_12
+      - Type: R_ARM_PRIVATE_13
+      - Type: R_ARM_PRIVATE_14
+      - Type: R_ARM_PRIVATE_15
+      - Type: R_ARM_ME_TOO
+      - Type: R_ARM_THM_TLS_DESCSEQ16
+      - Type: R_ARM_THM_TLS_DESCSEQ32
+      - Type: R_ARM_IRELATIVE
diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-lanai.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-lanai.test
index 101c0a8e7a97e..6bbe1a839b509 100644
--- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-lanai.test
+++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-lanai.test
@@ -30,16 +30,10 @@ Sections:
     EntSize:      0x000000000000000C
     Info:         .text
     Relocations:
-      - Type:   R_LANAI_NONE
-      - Offset: 0x0000000000000004
-        Type:   R_LANAI_21
-      - Offset: 0x0000000000000008
-        Type:   R_LANAI_21_F
-      - Offset: 0x000000000000000C
-        Type:   R_LANAI_25
-      - Offset: 0x0000000000000010
-        Type:   R_LANAI_32
-      - Offset: 0x0000000000000014
-        Type:   R_LANAI_HI16
-      - Offset: 0x0000000000000018
-        Type:   R_LANAI_LO16
+      - Type: R_LANAI_NONE
+      - Type: R_LANAI_21
+      - Type: R_LANAI_21_F
+      - Type: R_LANAI_25
+      - Type: R_LANAI_32
+      - Type: R_LANAI_HI16
+      - Type: R_LANAI_LO16
diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips.test
index 1bfe2f4aba72f..59793c512b35a 100644
--- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips.test
+++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips.test
@@ -74,106 +74,55 @@ Sections:
     EntSize:      0x0000000000000008
     Info:         .text
     Relocations:
-      - Type:   R_MIPS_NONE
-      - Offset: 0x0000000000000004
-        Type:   R_MIPS_16
-      - Offset: 0x0000000000000008
-        Type:   R_MIPS_32
-      - Offset: 0x000000000000000C
-        Type:   R_MIPS_REL32
-      - Offset: 0x0000000000000010
-        Type:   R_MIPS_26
-      - Offset: 0x0000000000000014
-        Type:   R_MIPS_HI16
-      - Offset: 0x0000000000000018
-        Type:   R_MIPS_LO16
-      - Offset: 0x000000000000001C
-        Type:   R_MIPS_GPREL16
-      - Offset: 0x0000000000000020
-        Type:   R_MIPS_LITERAL
-      - Offset: 0x0000000000000024
-        Type:   R_MIPS_GOT16
-      - Offset: 0x0000000000000028
-        Type:   R_MIPS_PC16
-      - Offset: 0x000000000000002C
-        Type:   R_MIPS_CALL16
-      - Offset: 0x0000000000000030
-        Type:   R_MIPS_GPREL32
-      - Offset: 0x0000000000000034
-        Type:   R_MIPS_SHIFT5
-      - Offset: 0x0000000000000038
-        Type:   R_MIPS_SHIFT6
-      - Offset: 0x000000000000003C
-        Type:   R_MIPS_64
-      - Offset: 0x0000000000000040
-        Type:   R_MIPS_GOT_DISP
-      - Offset: 0x0000000000000044
-        Type:   R_MIPS_GOT_PAGE
-      - Offset: 0x0000000000000048
-        Type:   R_MIPS_GOT_OFST
-      - Offset: 0x000000000000004C
-        Type:   R_MIPS_GOT_HI16
-      - Offset: 0x0000000000000050
-        Type:   R_MIPS_GOT_LO16
-      - Offset: 0x0000000000000054
-        Type:   R_MIPS_SUB
-      - Offset: 0x0000000000000058
-        Type:   R_MIPS_INSERT_A
-      - Offset: 0x000000000000005C
-        Type:   R_MIPS_INSERT_B
-      - Offset: 0x0000000000000060
-        Type:   R_MIPS_DELETE
-      - Offset: 0x0000000000000064
-        Type:   R_MIPS_HIGHER
-      - Offset: 0x0000000000000068
-        Type:   R_MIPS_HIGHEST
-      - Offset: 0x000000000000006C
-        Type:   R_MIPS_CALL_HI16
-      - Offset: 0x0000000000000070
-        Type:   R_MIPS_CALL_LO16
-      - Offset: 0x0000000000000074
-        Type:   R_MIPS_SCN_DISP
-      - Offset: 0x0000000000000078
-        Type:   R_MIPS_REL16
-      - Offset: 0x000000000000007C
-        Type:   R_MIPS_ADD_IMMEDIATE
-      - Offset: 0x0000000000000080
-        Type:   R_MIPS_PJUMP
-      - Offset: 0x0000000000000084
-        Type:   R_MIPS_RELGOT
-      - Offset: 0x0000000000000088
-        Type:   R_MIPS_JALR
-      - Offset: 0x000000000000008C
-        Type:   R_MIPS_TLS_DTPMOD32
-      - Offset: 0x0000000000000090
-        Type:   R_MIPS_TLS_DTPREL32
-      - Offset: 0x0000000000000094
-        Type:   R_MIPS_TLS_DTPMOD64
-      - Offset: 0x0000000000000098
-        Type:   R_MIPS_TLS_DTPREL64
-      - Offset: 0x000000000000009C
-        Type:   R_MIPS_TLS_GD
-      - Offset: 0x00000000000000A0
-        Type:   R_MIPS_TLS_LDM
-      - Offset: 0x00000000000000A4
-        Type:   R_MIPS_TLS_DTPREL_HI16
-      - Offset: 0x00000000000000A8
-        Type:   R_MIPS_TLS_DTPREL_LO16
-      - Offset: 0x00000000000000AC
-        Type:   R_MIPS_TLS_GOTTPREL
-      - Offset: 0x00000000000000B0
-        Type:   R_MIPS_TLS_TPREL32
-      - Offset: 0x00000000000000B4
-        Type:   R_MIPS_TLS_TPREL64
-      - Offset: 0x00000000000000B8
-        Type:   R_MIPS_TLS_TPREL_HI16
-      - Offset: 0x00000000000000BC
-        Type:   R_MIPS_TLS_TPREL_LO16
-      - Offset: 0x00000000000000C0
-        Type:   R_MIPS_GLOB_DAT
-      - Offset: 0x00000000000000C4
-        Type:   R_MIPS_COPY
-      - Offset: 0x00000000000000C8
-        Type:   R_MIPS_JUMP_SLOT
-      - Offset: 0x00000000000000CC
-        Type:   R_MIPS_NUM
+      - Type: R_MIPS_NONE
+      - Type: R_MIPS_16
+      - Type: R_MIPS_32
+      - Type: R_MIPS_REL32
+      - Type: R_MIPS_26
+      - Type: R_MIPS_HI16
+      - Type: R_MIPS_LO16
+      - Type: R_MIPS_GPREL16
+      - Type: R_MIPS_LITERAL
+      - Type: R_MIPS_GOT16
+      - Type: R_MIPS_PC16
+      - Type: R_MIPS_CALL16
+      - Type: R_MIPS_GPREL32
+      - Type: R_MIPS_SHIFT5
+      - Type: R_MIPS_SHIFT6
+      - Type: R_MIPS_64
+      - Type: R_MIPS_GOT_DISP
+      - Type: R_MIPS_GOT_PAGE
+      - Type: R_MIPS_GOT_OFST
+      - Type: R_MIPS_GOT_HI16
+      - Type: R_MIPS_GOT_LO16
+      - Type: R_MIPS_SUB
+      - Type: R_MIPS_INSERT_A
+      - Type: R_MIPS_INSERT_B
+      - Type: R_MIPS_DELETE
+      - Type: R_MIPS_HIGHER
+      - Type: R_MIPS_HIGHEST
+      - Type: R_MIPS_CALL_HI16
+      - Type: R_MIPS_CALL_LO16
+      - Type: R_MIPS_SCN_DISP
+      - Type: R_MIPS_REL16
+      - Type: R_MIPS_ADD_IMMEDIATE
+      - Type: R_MIPS_PJUMP
+      - Type: R_MIPS_RELGOT
+      - Type: R_MIPS_JALR
+      - Type: R_MIPS_TLS_DTPMOD32
+      - Type: R_MIPS_TLS_DTPREL32
+      - Type: R_MIPS_TLS_DTPMOD64
+      - Type: R_MIPS_TLS_DTPREL64
+      - Type: R_MIPS_TLS_GD
+      - Type: R_MIPS_TLS_LDM
+      - Type: R_MIPS_TLS_DTPREL_HI16
+      - Type: R_MIPS_TLS_DTPREL_LO16
+      - Type: R_MIPS_TLS_GOTTPREL
+      - Type: R_MIPS_TLS_TPREL32
+      - Type: R_MIPS_TLS_TPREL64
+      - Type: R_MIPS_TLS_TPREL_HI16
+      - Type: R_MIPS_TLS_TPREL_LO16
+      - Type: R_MIPS_GLOB_DAT
+      - Type: R_MIPS_COPY
+      - Type: R_MIPS_JUMP_SLOT
+      - Type: R_MIPS_NUM
diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips64.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips64.test
index 8c303d46b728d..fc72edd29d2c0 100644
--- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips64.test
+++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-mips64.test
@@ -74,208 +74,157 @@ Sections:
     EntSize:      0x0000000000000018
     Info:         .text
     Relocations:
-      - Type:   R_MIPS_NONE
-      - Offset: 0x0000000000000004
-        Type:   R_MIPS_16
-        Type2:  R_MIPS_16
-        Type3:  R_MIPS_16
-      - Offset: 0x0000000000000008
-        Type:   R_MIPS_32
-        Type2:  R_MIPS_32
-        Type3:  R_MIPS_32
-      - Offset: 0x000000000000000C
-        Type:   R_MIPS_REL32
-        Type2:  R_MIPS_REL32
-        Type3:  R_MIPS_REL32
-      - Offset: 0x0000000000000010
-        Type:   R_MIPS_26
-        Type2:  R_MIPS_26
-        Type3:  R_MIPS_26
-      - Offset: 0x0000000000000014
-        Type:   R_MIPS_HI16
-        Type2:  R_MIPS_HI16
-        Type3:  R_MIPS_HI16
-      - Offset: 0x0000000000000018
-        Type:   R_MIPS_LO16
-        Type2:  R_MIPS_LO16
-        Type3:  R_MIPS_LO16
-      - Offset: 0x000000000000001C
-        Type:   R_MIPS_GPREL16
-        Type2:  R_MIPS_GPREL16
-        Type3:  R_MIPS_GPREL16
-      - Offset: 0x0000000000000020
-        Type:   R_MIPS_LITERAL
-        Type2:  R_MIPS_LITERAL
-        Type3:  R_MIPS_LITERAL
-      - Offset: 0x0000000000000024
-        Type:   R_MIPS_GOT16
-        Type2:  R_MIPS_GOT16
-        Type3:  R_MIPS_GOT16
-      - Offset: 0x0000000000000028
-        Type:   R_MIPS_PC16
-        Type2:  R_MIPS_PC16
-        Type3:  R_MIPS_PC16
-      - Offset: 0x000000000000002C
-        Type:   R_MIPS_CALL16
-        Type2:  R_MIPS_CALL16
-        Type3:  R_MIPS_CALL16
-      - Offset: 0x0000000000000030
-        Type:   R_MIPS_GPREL32
-        Type2:  R_MIPS_GPREL32
-        Type3:  R_MIPS_GPREL32
-      - Offset: 0x0000000000000034
-        Type:   R_MIPS_SHIFT5
-        Type2:  R_MIPS_SHIFT5
-        Type3:  R_MIPS_SHIFT5
-      - Offset: 0x0000000000000038
-        Type:   R_MIPS_SHIFT6
-        Type2:  R_MIPS_SHIFT6
-        Type3:  R_MIPS_SHIFT6
-      - Offset: 0x000000000000003C
-        Type:   R_MIPS_64
-        Type2:  R_MIPS_64
-        Type3:  R_MIPS_64
-      - Offset: 0x0000000000000040
-        Type:   R_MIPS_GOT_DISP
-        Type2:  R_MIPS_GOT_DISP
-        Type3:  R_MIPS_GOT_DISP
-      - Offset: 0x0000000000000044
-        Type:   R_MIPS_GOT_PAGE
-        Type2:  R_MIPS_GOT_PAGE
-        Type3:  R_MIPS_GOT_PAGE
-      - Offset: 0x0000000000000048
-        Type:   R_MIPS_GOT_OFST
-        Type2:  R_MIPS_GOT_OFST
-        Type3:  R_MIPS_GOT_OFST
-      - Offset: 0x000000000000004C
-        Type:   R_MIPS_GOT_HI16
-        Type2:  R_MIPS_GOT_HI16
-        Type3:  R_MIPS_GOT_HI16
-      - Offset: 0x0000000000000050
-        Type:   R_MIPS_GOT_LO16
-        Type2:  R_MIPS_GOT_LO16
-        Type3:  R_MIPS_GOT_LO16
-      - Offset: 0x0000000000000054
-        Type:   R_MIPS_SUB
-        Type2:  R_MIPS_SUB
-        Type3:  R_MIPS_SUB
-      - Offset: 0x0000000000000058
-        Type:   R_MIPS_INSERT_A
-        Type2:  R_MIPS_INSERT_A
-        Type3:  R_MIPS_INSERT_A
-      - Offset: 0x000000000000005C
-        Type:   R_MIPS_INSERT_B
-        Type2:  R_MIPS_INSERT_B
-        Type3:  R_MIPS_INSERT_B
-      - Offset: 0x0000000000000060
-        Type:   R_MIPS_DELETE
-        Type2:  R_MIPS_DELETE
-        Type3:  R_MIPS_DELETE
-      - Offset: 0x0000000000000064
-        Type:   R_MIPS_HIGHER
-        Type2:  R_MIPS_HIGHER
-        Type3:  R_MIPS_HIGHER
-      - Offset: 0x0000000000000068
-        Type:   R_MIPS_HIGHEST
-        Type2:  R_MIPS_HIGHEST
-        Type3:  R_MIPS_HIGHEST
-      - Offset: 0x000000000000006C
-        Type:   R_MIPS_CALL_HI16
-        Type2:  R_MIPS_CALL_HI16
-        Type3:  R_MIPS_CALL_HI16
-      - Offset: 0x0000000000000070
-        Type:   R_MIPS_CALL_LO16
-        Type2:  R_MIPS_CALL_LO16
-        Type3:  R_MIPS_CALL_LO16
-      - Offset: 0x0000000000000074
-        Type:   R_MIPS_SCN_DISP
-        Type2:  R_MIPS_SCN_DISP
-        Type3:  R_MIPS_SCN_DISP
-      - Offset: 0x0000000000000078
-        Type:   R_MIPS_REL16
-        Type2:  R_MIPS_REL16
-        Type3:  R_MIPS_REL16
-      - Offset: 0x000000000000007C
-        Type:   R_MIPS_ADD_IMMEDIATE
-        Type2:  R_MIPS_ADD_IMMEDIATE
-        Type3:  R_MIPS_ADD_IMMEDIATE
-      - Offset: 0x0000000000000080
-        Type:   R_MIPS_PJUMP
-        Type2:  R_MIPS_PJUMP
-        Type3:  R_MIPS_PJUMP
-      - Offset: 0x0000000000000084
-        Type:   R_MIPS_RELGOT
-        Type2:  R_MIPS_RELGOT
-        Type3:  R_MIPS_RELGOT
-      - Offset: 0x0000000000000088
-        Type:   R_MIPS_JALR
-        Type2:  R_MIPS_JALR
-        Type3:  R_MIPS_JALR
-      - Offset: 0x000000000000008C
-        Type:   R_MIPS_TLS_DTPMOD32
-        Type2:  R_MIPS_TLS_DTPMOD32
-        Type3:  R_MIPS_TLS_DTPMOD32
-      - Offset: 0x0000000000000090
-        Type:   R_MIPS_TLS_DTPREL32
-        Type2:  R_MIPS_TLS_DTPREL32
-        Type3:  R_MIPS_TLS_DTPREL32
-      - Offset: 0x0000000000000094
-        Type:   R_MIPS_TLS_DTPMOD64
-        Type2:  R_MIPS_TLS_DTPMOD64
-        Type3:  R_MIPS_TLS_DTPMOD64
-      - Offset: 0x0000000000000098
-        Type:   R_MIPS_TLS_DTPREL64
-        Type2:  R_MIPS_TLS_DTPREL64
-        Type3:  R_MIPS_TLS_DTPREL64
-      - Offset: 0x000000000000009C
-        Type:   R_MIPS_TLS_GD
-        Type2:  R_MIPS_TLS_GD
-        Type3:  R_MIPS_TLS_GD
-      - Offset: 0x00000000000000A0
-        Type:   R_MIPS_TLS_LDM
-        Type2:  R_MIPS_TLS_LDM
-        Type3:  R_MIPS_TLS_LDM
-      - Offset: 0x00000000000000A4
-        Type:   R_MIPS_TLS_DTPREL_HI16
-        Type2:  R_MIPS_TLS_DTPREL_HI16
-        Type3:  R_MIPS_TLS_DTPREL_HI16
-      - Offset: 0x00000000000000A8
-        Type:   R_MIPS_TLS_DTPREL_LO16
-        Type2:  R_MIPS_TLS_DTPREL_LO16
-        Type3:  R_MIPS_TLS_DTPREL_LO16
-      - Offset: 0x00000000000000AC
-        Type:   R_MIPS_TLS_GOTTPREL
-        Type2:  R_MIPS_TLS_GOTTPREL
-        Type3:  R_MIPS_TLS_GOTTPREL
-      - Offset: 0x00000000000000B0
-        Type:   R_MIPS_TLS_TPREL32
-        Type2:  R_MIPS_TLS_TPREL32
-        Type3:  R_MIPS_TLS_TPREL32
-      - Offset: 0x00000000000000B4
-        Type:   R_MIPS_TLS_TPREL64
-        Type2:  R_MIPS_TLS_TPREL64
-        Type3:  R_MIPS_TLS_TPREL64
-      - Offset: 0x00000000000000B8
-        Type:   R_MIPS_TLS_TPREL_HI16
-        Type2:  R_MIPS_TLS_TPREL_HI16
-        Type3:  R_MIPS_TLS_TPREL_HI16
-      - Offset: 0x00000000000000BC
-        Type:   R_MIPS_TLS_TPREL_LO16
-        Type2:  R_MIPS_TLS_TPREL_LO16
-        Type3:  R_MIPS_TLS_TPREL_LO16
-      - Offset: 0x00000000000000C0
-        Type:   R_MIPS_GLOB_DAT
-        Type2:  R_MIPS_GLOB_DAT
-        Type3:  R_MIPS_GLOB_DAT
-      - Offset: 0x00000000000000C4
-        Type:   R_MIPS_COPY
-        Type2:  R_MIPS_COPY
-        Type3:  R_MIPS_COPY
-      - Offset: 0x00000000000000C8
-        Type:   R_MIPS_JUMP_SLOT
-        Type2:  R_MIPS_JUMP_SLOT
-        Type3:  R_MIPS_JUMP_SLOT
-      - Offset: 0x00000000000000CC
-        Type:   R_MIPS_NUM
-        Type2:  R_MIPS_NUM
-        Type3:  R_MIPS_NUM
+      - Type:  R_MIPS_NONE
+      - Type:  R_MIPS_16
+        Type2: R_MIPS_16
+        Type3: R_MIPS_16
+      - Type:  R_MIPS_32
+        Type2: R_MIPS_32
+        Type3: R_MIPS_32
+      - Type:  R_MIPS_REL32
+        Type2: R_MIPS_REL32
+        Type3: R_MIPS_REL32
+      - Type:  R_MIPS_26
+        Type2: R_MIPS_26
+        Type3: R_MIPS_26
+      - Type:  R_MIPS_HI16
+        Type2: R_MIPS_HI16
+        Type3: R_MIPS_HI16
+      - Type:  R_MIPS_LO16
+        Type2: R_MIPS_LO16
+        Type3: R_MIPS_LO16
+      - Type:  R_MIPS_GPREL16
+        Type2: R_MIPS_GPREL16
+        Type3: R_MIPS_GPREL16
+      - Type:  R_MIPS_LITERAL
+        Type2: R_MIPS_LITERAL
+        Type3: R_MIPS_LITERAL
+      - Type:  R_MIPS_GOT16
+        Type2: R_MIPS_GOT16
+        Type3: R_MIPS_GOT16
+      - Type:  R_MIPS_PC16
+        Type2: R_MIPS_PC16
+        Type3: R_MIPS_PC16
+      - Type:  R_MIPS_CALL16
+        Type2: R_MIPS_CALL16
+        Type3: R_MIPS_CALL16
+      - Type:  R_MIPS_GPREL32
+        Type2: R_MIPS_GPREL32
+        Type3: R_MIPS_GPREL32
+      - Type:  R_MIPS_SHIFT5
+        Type2: R_MIPS_SHIFT5
+        Type3: R_MIPS_SHIFT5
+      - Type:  R_MIPS_SHIFT6
+        Type2: R_MIPS_SHIFT6
+        Type3: R_MIPS_SHIFT6
+      - Type:  R_MIPS_64
+        Type2: R_MIPS_64
+        Type3: R_MIPS_64
+      - Type:  R_MIPS_GOT_DISP
+        Type2: R_MIPS_GOT_DISP
+        Type3: R_MIPS_GOT_DISP
+      - Type:  R_MIPS_GOT_PAGE
+        Type2: R_MIPS_GOT_PAGE
+        Type3: R_MIPS_GOT_PAGE
+      - Type:  R_MIPS_GOT_OFST
+        Type2: R_MIPS_GOT_OFST
+        Type3: R_MIPS_GOT_OFST
+      - Type:  R_MIPS_GOT_HI16
+        Type2: R_MIPS_GOT_HI16
+        Type3: R_MIPS_GOT_HI16
+      - Type:  R_MIPS_GOT_LO16
+        Type2: R_MIPS_GOT_LO16
+        Type3: R_MIPS_GOT_LO16
+      - Type:  R_MIPS_SUB
+        Type2: R_MIPS_SUB
+        Type3: R_MIPS_SUB
+      - Type:  R_MIPS_INSERT_A
+        Type2: R_MIPS_INSERT_A
+        Type3: R_MIPS_INSERT_A
+      - Type:  R_MIPS_INSERT_B
+        Type2: R_MIPS_INSERT_B
+        Type3: R_MIPS_INSERT_B
+      - Type:  R_MIPS_DELETE
+        Type2: R_MIPS_DELETE
+        Type3: R_MIPS_DELETE
+      - Type:  R_MIPS_HIGHER
+        Type2: R_MIPS_HIGHER
+        Type3: R_MIPS_HIGHER
+      - Type:  R_MIPS_HIGHEST
+        Type2: R_MIPS_HIGHEST
+        Type3: R_MIPS_HIGHEST
+      - Type:  R_MIPS_CALL_HI16
+        Type2: R_MIPS_CALL_HI16
+        Type3: R_MIPS_CALL_HI16
+      - Type:  R_MIPS_CALL_LO16
+        Type2: R_MIPS_CALL_LO16
+        Type3: R_MIPS_CALL_LO16
+      - Type:  R_MIPS_SCN_DISP
+        Type2: R_MIPS_SCN_DISP
+        Type3: R_MIPS_SCN_DISP
+      - Type:  R_MIPS_REL16
+        Type2: R_MIPS_REL16
+        Type3: R_MIPS_REL16
+      - Type:  R_MIPS_ADD_IMMEDIATE
+        Type2: R_MIPS_ADD_IMMEDIATE
+        Type3: R_MIPS_ADD_IMMEDIATE
+      - Type:  R_MIPS_PJUMP
+        Type2: R_MIPS_PJUMP
+        Type3: R_MIPS_PJUMP
+      - Type:  R_MIPS_RELGOT
+        Type2: R_MIPS_RELGOT
+        Type3: R_MIPS_RELGOT
+      - Type:  R_MIPS_JALR
+        Type2: R_MIPS_JALR
+        Type3: R_MIPS_JALR
+      - Type:  R_MIPS_TLS_DTPMOD32
+        Type2: R_MIPS_TLS_DTPMOD32
+        Type3: R_MIPS_TLS_DTPMOD32
+      - Type:  R_MIPS_TLS_DTPREL32
+        Type2: R_MIPS_TLS_DTPREL32
+        Type3: R_MIPS_TLS_DTPREL32
+      - Type:  R_MIPS_TLS_DTPMOD64
+        Type2: R_MIPS_TLS_DTPMOD64
+        Type3: R_MIPS_TLS_DTPMOD64
+      - Type:  R_MIPS_TLS_DTPREL64
+        Type2: R_MIPS_TLS_DTPREL64
+        Type3: R_MIPS_TLS_DTPREL64
+      - Type:  R_MIPS_TLS_GD
+        Type2: R_MIPS_TLS_GD
+        Type3: R_MIPS_TLS_GD
+      - Type:  R_MIPS_TLS_LDM
+        Type2: R_MIPS_TLS_LDM
+        Type3: R_MIPS_TLS_LDM
+      - Type:  R_MIPS_TLS_DTPREL_HI16
+        Type2: R_MIPS_TLS_DTPREL_HI16
+        Type3: R_MIPS_TLS_DTPREL_HI16
+      - Type:  R_MIPS_TLS_DTPREL_LO16
+        Type2: R_MIPS_TLS_DTPREL_LO16
+        Type3: R_MIPS_TLS_DTPREL_LO16
+      - Type:  R_MIPS_TLS_GOTTPREL
+        Type2: R_MIPS_TLS_GOTTPREL
+        Type3: R_MIPS_TLS_GOTTPREL
+      - Type:  R_MIPS_TLS_TPREL32
+        Type2: R_MIPS_TLS_TPREL32
+        Type3: R_MIPS_TLS_TPREL32
+      - Type:  R_MIPS_TLS_TPREL64
+        Type2: R_MIPS_TLS_TPREL64
+        Type3: R_MIPS_TLS_TPREL64
+      - Type:  R_MIPS_TLS_TPREL_HI16
+        Type2: R_MIPS_TLS_TPREL_HI16
+        Type3: R_MIPS_TLS_TPREL_HI16
+      - Type:  R_MIPS_TLS_TPREL_LO16
+        Type2: R_MIPS_TLS_TPREL_LO16
+        Type3: R_MIPS_TLS_TPREL_LO16
+      - Type:  R_MIPS_GLOB_DAT
+        Type2: R_MIPS_GLOB_DAT
+        Type3: R_MIPS_GLOB_DAT
+      - Type:  R_MIPS_COPY
+        Type2: R_MIPS_COPY
+        Type3: R_MIPS_COPY
+      - Type:  R_MIPS_JUMP_SLOT
+        Type2: R_MIPS_JUMP_SLOT
+        Type3: R_MIPS_JUMP_SLOT
+      - Type:  R_MIPS_NUM
+        Type2: R_MIPS_NUM
+        Type3: R_MIPS_NUM
diff --git a/llvm/test/tools/llvm-readobj/archive.test b/llvm/test/tools/llvm-readobj/archive.test
index a06a917a5875a..5b61320d0a58f 100644
--- a/llvm/test/tools/llvm-readobj/archive.test
+++ b/llvm/test/tools/llvm-readobj/archive.test
@@ -13,7 +13,7 @@
 
 # LLVM: {{^$}}
 # LLVM-NEXT: File: [[ARFILE]](trivial.obj.elf-x86-64)
-# LLVM: Format: ELF64-x86-64
+# LLVM: Format: elf64-x86-64
 # LLVM: ElfHeader {
 # LLVM:   Machine: EM_X86_64
 # LLVM: Sections [
@@ -33,7 +33,7 @@
 
 # LLVM-EMPTY:
 # LLVM-NEXT: File: [[ARFILE]](trivial.obj.elf-i386)
-# LLVM: Format: ELF32-i386
+# LLVM: Format: elf32-i386
 # LLVM: ElfHeader {
 # LLVM:   Machine: EM_386
 # LLVM: Sections [
diff --git a/llvm/test/tools/llvm-readobj/thin-archive.test b/llvm/test/tools/llvm-readobj/thin-archive.test
index f0c26bf914d5c..d13ae23e1b89e 100644
--- a/llvm/test/tools/llvm-readobj/thin-archive.test
+++ b/llvm/test/tools/llvm-readobj/thin-archive.test
@@ -11,7 +11,7 @@
 # RUN: llvm-readelf --all %t.a | FileCheck %s --check-prefixes=GNU,COFF
 
 # LLVM: File: {{.*}}1.o
-# LLVM: Format: ELF64-x86-64
+# LLVM: Format: elf64-x86-64
 # LLVM: ElfHeader {
 # LLVM:   SectionHeaderCount: 3
 # LLVM: Sections [
@@ -23,7 +23,7 @@
 # GNU: Section Headers:
 
 # LLVM: File: {{.*}}2.o
-# LLVM: Format: ELF32-i386
+# LLVM: Format: elf32-i386
 # LLVM: ElfHeader {
 # LLVM:   SectionHeaderCount: 4
 # LLVM: Sections [
@@ -48,9 +48,9 @@
 # RUN: llvm-readobj --file-headers %t.a | FileCheck %s --check-prefix=RESIZED
 
 # RESIZED: File: {{.*}}1.o
-# RESIZED: Format: ELF64-x86-64
+# RESIZED: Format: elf64-x86-64
 # RESIZED: File: {{.*}}2.o
-# RESIZED: Format: ELF64-x86-64
+# RESIZED: Format: elf64-x86-64
 
 # Remove the second member and show that the first can still be dumped, but that the last isn't.
 # RUN: rm %t/2.o
@@ -58,7 +58,7 @@
 # RUN: FileCheck %s --check-prefix=ERR --input-file=%t.err
 
 # MISSING:     File: {{.*}}1.o
-# MISSING:     Format: ELF64-x86-64
+# MISSING:     Format: elf64-x86-64
 # MISSING-NOT: File: {{.*}}3.o
 # ERR: error: '{{.*}}.a': '{{.*}}2.o': {{[Nn]}}o such file or directory
 
diff --git a/llvm/test/tools/obj2yaml/Inputs/crt1.o b/llvm/test/tools/obj2yaml/Inputs/crt1.o
deleted file mode 100755
index 2b000ab9ae836..0000000000000
Binary files a/llvm/test/tools/obj2yaml/Inputs/crt1.o and /dev/null differ
diff --git a/llvm/test/tools/obj2yaml/call-graph-profile-section.yaml b/llvm/test/tools/obj2yaml/call-graph-profile-section.yaml
index 0608bb4f0b9fa..60e31bbdd1365 100644
--- a/llvm/test/tools/obj2yaml/call-graph-profile-section.yaml
+++ b/llvm/test/tools/obj2yaml/call-graph-profile-section.yaml
@@ -2,13 +2,13 @@
 
 ## Test we use the "Entries" property when it is possible to dump values correctly.
 
-# RUN: yaml2obj --docnum=1 %s -o %t.le64
+# RUN: yaml2obj -D BITS=64 -D ENCODE=LSB %s -o %t.le64
 # RUN: obj2yaml %t.le64 | FileCheck %s --check-prefix=BASIC
-# RUN: yaml2obj --docnum=2 %s -o %t.be64
+# RUN: yaml2obj -D BITS=64 -D ENCODE=MSB %s -o %t.be64
 # RUN: obj2yaml %t.be64 | FileCheck %s --check-prefix=BASIC
-# RUN: yaml2obj --docnum=3 %s -o %t.le32
+# RUN: yaml2obj -D BITS=32 -D ENCODE=LSB %s -o %t.le32
 # RUN: obj2yaml %t.le32 | FileCheck %s --check-prefix=BASIC
-# RUN: yaml2obj --docnum=4 %s -o %t.be32
+# RUN: yaml2obj -D BITS=32 -D ENCODE=MSB %s -o %t.be32
 # RUN: obj2yaml %t.be32 | FileCheck %s --check-prefix=BASIC
 
 # BASIC:      Sections:
@@ -25,75 +25,12 @@
 # BASIC-NEXT:         Weight: 98
 # BASIC-NEXT: Symbols:
 
-## TODO: we should really improve yaml2obj somehow to be able to collapse
-##       the following four YAML descriptions into a single one.
-
---- !ELF
-FileHeader:
-  Class:   ELFCLASS64
-  Data:    ELFDATA2LSB
-  Type:    ET_DYN
-  Machine: EM_X86_64
-Sections:
-  - Name: .llvm.call-graph-profile
-    Type: SHT_LLVM_CALL_GRAPH_PROFILE
-    Entries:
-      - From:   1
-        To:     2
-        Weight: 89
-      - From:   2
-        To:     1
-        Weight: 98
-Symbols:
-  - Name: foo
-  - Name: bar
-
---- !ELF
-FileHeader:
-  Class:   ELFCLASS64
-  Data:    ELFDATA2MSB
-  Type:    ET_DYN
-  Machine: EM_X86_64
-Sections:
-  - Name: .llvm.call-graph-profile
-    Type: SHT_LLVM_CALL_GRAPH_PROFILE
-    Entries:
-      - From:   1
-        To:     2
-        Weight: 89
-      - From:   2
-        To:     1
-        Weight: 98
-Symbols:
-  - Name: foo
-  - Name: bar
-
 --- !ELF
 FileHeader:
-  Class:   ELFCLASS32
-  Data:    ELFDATA2LSB
+  Class:   ELFCLASS[[BITS]]
+  Data:    ELFDATA2[[ENCODE]]
   Type:    ET_DYN
-  Machine: EM_386
-Sections:
-  - Name: .llvm.call-graph-profile
-    Type: SHT_LLVM_CALL_GRAPH_PROFILE
-    Entries:
-      - From:   1
-        To:     2
-        Weight: 89
-      - From:   2
-        To:     1
-        Weight: 98
-Symbols:
-  - Name: foo
-  - Name: bar
-
---- !ELF
-FileHeader:
-  Class:   ELFCLASS32
-  Data:    ELFDATA2MSB
-  Type:    ET_DYN
-  Machine: EM_386
+  Machine: EM_NONE
 Sections:
   - Name: .llvm.call-graph-profile
     Type: SHT_LLVM_CALL_GRAPH_PROFILE
@@ -110,7 +47,7 @@ Symbols:
 
 ## Check how we handle broken cases.
 
-# RUN: yaml2obj --docnum=5 %s -o %t.invalid
+# RUN: yaml2obj --docnum=2 %s -o %t.invalid
 # RUN: obj2yaml %t.invalid | FileCheck %s --check-prefix=INVALID
 
 # INVALID:      --- !ELF
diff --git a/llvm/test/tools/obj2yaml/missing_symtab.test b/llvm/test/tools/obj2yaml/missing_symtab.test
deleted file mode 100644
index f61712c9b2afb..0000000000000
--- a/llvm/test/tools/obj2yaml/missing_symtab.test
+++ /dev/null
@@ -1,5 +0,0 @@
-# RUN: obj2yaml %S/Inputs/crt1.o | FileCheck %s
-# test that we don't crash when passed object files without a symbol table
-# CHECK-LABEL: FileHeader:
-# CHECK-LABEL: Sections:
-# CHECK-NOT: Symbols:
diff --git a/llvm/test/tools/yaml2obj/ELF/dynamic-section.yaml b/llvm/test/tools/yaml2obj/ELF/dynamic-section.yaml
index 035d97094dfef..9dadf63b16f00 100644
--- a/llvm/test/tools/yaml2obj/ELF/dynamic-section.yaml
+++ b/llvm/test/tools/yaml2obj/ELF/dynamic-section.yaml
@@ -1,18 +1,29 @@
 ## Ensures that dynamic section has sh_entsize correctly set.
 
-# RUN: yaml2obj %s -o %t
-# RUN: llvm-readobj --sections %t | FileCheck %s --check-prefix=SECTION
+# RUN: yaml2obj -DBITS=64 %s -o %t.64
+# RUN: llvm-readobj --sections %t.64 | FileCheck %s -DENTSIZE=16
+# RUN: yaml2obj -DBITS=32 %s -o %t.32
+# RUN: llvm-readobj --sections %t.32 | FileCheck %s -DENTSIZE=8
 
 !ELF
 FileHeader:
-  Class:           ELFCLASS64
-  Data:            ELFDATA2LSB
-  Type:            ET_DYN
-  Machine:         EM_X86_64
+  Class:   ELFCLASS[[BITS]]
+  Data:    ELFDATA2LSB
+  Type:    ET_DYN
+  Machine: EM_X86_64
 Sections:
-  - Name: .dynamic
-    Type: SHT_DYNAMIC
+## Test default values set by yaml2obj.
+  - Name:  .dynamic
+    Type:  SHT_DYNAMIC
     Flags: [ SHF_ALLOC, SHF_WRITE ]
+## Test we can use an arbitrary value for sh_entsize.
+  - Name:    .mydynamic
+    Type:    SHT_DYNAMIC
+    EntSize: 0xFE
 
-# SECTION: Name: .dynamic
-# SECTION: EntrySize: 16
+# CHECK:      Name:      .dynamic
+# CHECK:      EntrySize:
+# CHECK-SAME:           {{^}} [[ENTSIZE]]{{$}}
+# CHECK:      Name:      .mydynamic
+# CHECK:      EntrySize:
+# CHECK-SAME:           {{^}} 254{{$}}
diff --git a/llvm/test/tools/yaml2obj/ELF/program-header-address.yaml b/llvm/test/tools/yaml2obj/ELF/program-header-address.yaml
index a1e5460e2972a..4aa5aacfa8e29 100644
--- a/llvm/test/tools/yaml2obj/ELF/program-header-address.yaml
+++ b/llvm/test/tools/yaml2obj/ELF/program-header-address.yaml
@@ -27,20 +27,21 @@ Sections:
     Size:    0x1
     Address: 0x1234
 ProgramHeaders:
-## Show addresses we emit by default for a case when a program header
-## has no sections included.
+## Show what virtual and physical address we set by default for the case where
+## a program header has no sections.
   - Type:     PT_LOAD
     Flags:    [ PF_X, PF_R ]
     Sections: []
-## Show addresses we emit by default for a case when a program header
-## includes a section with a virtual address that is explicitly set.
+## Show what virtual and physical address we set by default for the case
+## where a program header includes a section with a virtual address that
+## is explicitly set.
   - Type:     PT_LOAD
     Flags:    [ PF_X, PF_R ]
     Sections:
       - Section: .foo
-## Now we have a program header that has a virtual address different from
-## a address of the section included. Show that the default physical address
-## is equal to virtual address.
+## Now we have a program header that has a virtual address different to
+## the address of the section included. Show that the default physical address
+## is equal to the program header's virtual address.
   - Type:  PT_LOAD
     Flags: [ PF_X, PF_R ]
     VAddr: 0xAAAA1000
diff --git a/llvm/test/tools/yaml2obj/ELF/relocation-addend.yaml b/llvm/test/tools/yaml2obj/ELF/relocation-addend.yaml
index 53396765fb59a..f4ed870357f46 100644
--- a/llvm/test/tools/yaml2obj/ELF/relocation-addend.yaml
+++ b/llvm/test/tools/yaml2obj/ELF/relocation-addend.yaml
@@ -2,36 +2,50 @@
 
 ## Case 1: Check a 64-bit object.
 
-## Case 1.1: Document we accept an addend with the
-## value INT64_MAX = 2^63-1 = 0x7FFFFFFFFFFFFFFF = 9223372036854775807.
+## Case 1.1: Document we accept any hex/decimal addends in [INT64_MIN, UINT64_MAX].
 
-# RUN: yaml2obj %s -o %t1 -D ADDEND=9223372036854775807
-# RUN: llvm-readobj -r %t1 | FileCheck %s --check-prefix=MAX64
-# RUN: yaml2obj %s -o %t2 -D ADDEND=0x7FFFFFFFFFFFFFFF
-# RUN: llvm-readobj -r %t2 | FileCheck %s --check-prefix=MAX64
+## INT64_MIN   == -9223372036854775808
+## UINT64_MAX  == 0xffffffffffffffff
 
-# MAX64: 0x0 R_X86_64_PC32 foo 0x7FFFFFFFFFFFFFFF
+## Addend == UINT64_MAX.
+# RUN: yaml2obj %s -o %t64.decimal.max -DADDEND=18446744073709551615
+# RUN: llvm-readobj -r %t64.decimal.max | FileCheck %s --check-prefix=TEST -DADDEND=0xFFFFFFFFFFFFFFFF
+# RUN: yaml2obj %s -o %t64.hex.max -DADDEND=0xFFFFFFFFFFFFFFFF
+# RUN: llvm-readobj -r %t64.hex.max | FileCheck %s --check-prefix=TEST -DADDEND=0xFFFFFFFFFFFFFFFF
 
-## Case 1.2: Check we report an error when an addend is greater than INT64_MAX and
-## it is in decimal form. We use (INT64_MAX + 1).
-# RUN: not yaml2obj %s -o %t3 -D ADDEND=9223372036854775808 2>&1 | FileCheck %s --check-prefix=OVERFLOW64
+## Addend == first positive integer.
+# RUN: yaml2obj %s -o %t64.decimal.first.pos -DADDEND=1
+# RUN: llvm-readobj -r %t64.decimal.first.pos | FileCheck %s --check-prefix=TEST -DADDEND=0x1
+# RUN: yaml2obj %s -o %t64.hex.first.pos -DADDEND=0x1
+# RUN: llvm-readobj -r %t64.hex.first.pos | FileCheck %s --check-prefix=TEST -DADDEND=0x1
 
-# OVERFLOW64: error: invalid number
+## Addend == 0.
+# RUN: yaml2obj %s -o %t64.decimal.null -DADDEND=0
+# RUN: llvm-readobj -r %t64.decimal.null | FileCheck %s --check-prefix=TEST -DADDEND=0x0
+# RUN: yaml2obj %s -o %t64.hex.null -DADDEND=0x0
+# RUN: llvm-readobj -r %t64.hex.null | FileCheck %s --check-prefix=TEST -DADDEND=0x0
 
-## Case 1.3: Document we accept an addend with the
-## value INT64_MIN = -2^63 = 0x8000000000000000 = -9223372036854775808.
+## Addend == first negative integer.
+# RUN: yaml2obj %s -o %t64.decimal.first.neg -DADDEND=-1
+# RUN: llvm-readobj -r %t64.decimal.first.neg | FileCheck %s --check-prefix=TEST -DADDEND=0xFFFFFFFFFFFFFFFF
+## We do not accept negative hex addends.
+# RUN: not yaml2obj %s -o /dev/null -DADDEND=-0x1 2>&1 | FileCheck %s --check-prefix=ERR
 
-# RUN: yaml2obj %s -o %t3 -D ADDEND=-9223372036854775808
-# RUN: llvm-readobj -r %t3 | FileCheck %s --check-prefix=MIN64
+## Addend == INT64_MIN.
+# RUN: yaml2obj %s -o %t64.decimal.min -DADDEND=-9223372036854775808
+# RUN: llvm-readobj -r %t64.decimal.min | FileCheck %s --check-prefix=TEST -DADDEND=0x8000000000000000
+# TEST: 0x0 R_{{.*}}_PC32 foo [[ADDEND]]
 
-# MIN64: 0x0 R_X86_64_PC32 foo 0x8000000000000000
+# Case 1.2: Document we do not accept any hex/decimal addends outside of the range specified.
 
-## FIXME: We should support the following case instead.
-# RUN: not yaml2obj %s -o /dev/null -D ADDEND=0x8000000000000000 2>&1 | FileCheck %s --check-prefix=OVERFLOW64
+## Addend == 2^64.
+# RUN: not yaml2obj %s -o /dev/null -DADDEND=18446744073709551616 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -o /dev/null -DADDEND=0x10000000000000000 2>&1 | FileCheck %s --check-prefix=ERR
 
-## Case 1.4: Check we report an error when an addend is less than INT64_MIN and
-## it is in decimal form. We use (INT64_MIN - 1).
-# RUN: not yaml2obj %s -o /dev/null -D ADDEND=-9223372036854775809 2>&1 | FileCheck %s --check-prefix=OVERFLOW64
+## Addend == INT64_MIN - 1.
+# RUN: not yaml2obj %s -o /dev/null -DADDEND=-9223372036854775809 2>&1 | FileCheck %s --check-prefix=ERR
+
+# ERR: invalid number
 
 --- !ELF
 FileHeader:
@@ -55,43 +69,47 @@ Symbols:
 
 ## Case 2: Check a 32-bit object.
 
-## Case 2.1: Document we accept an addend with the
-## value INT32_MAX = 2^31-1 = 0x7FFFFFFF = 2,147,483,647.
-
-# RUN: yaml2obj --docnum=2 %s -o %t4 -D ADDEND=2147483647
-# RUN: llvm-readobj -r %t4 | FileCheck %s --check-prefix=MAX32
-# RUN: yaml2obj --docnum=2 %s -o %t5 -D ADDEND=0x7FFFFFFF
-# RUN: cmp %t4 %t5
+## INT32_MIN   == -2147483648
+## UINT32_MAX  == 0xffffffff
 
-# MAX32: 0x0 R_386_PC32 foo 0x7FFFFFFF{{$}}
+## Case 2.1: Document we accept any hex/decimal addends in [INT32_MIN, UINT32_MAX].
 
-## Case 2.2: Check we report an error when an addend is greater than INT32_MAX and
-## it is specified in decimal form. We use (INT32_MAX + 1).
+## Addend == UINT32_MAX.
+# RUN: yaml2obj --docnum=2 %s -o %t32.decimal.max -DADDEND=4294967295
+# RUN: llvm-readobj -r %t32.decimal.max | FileCheck %s --check-prefix=TEST -DADDEND=0xFFFFFFFF
+# RUN: yaml2obj --docnum=2 %s -o %t32.hex.max -DADDEND=0xFFFFFFFF
+# RUN: llvm-readobj -r %t32.hex.max | FileCheck %s --check-prefix=TEST -DADDEND=0xFFFFFFFF
 
-## FIXME: The following case should fail, see OVERFLOW64.
-# RUN: yaml2obj --docnum=2 %s -o %t6 -D ADDEND=2147483648
-# RUN: llvm-readobj -r %t6 | FileCheck %s --check-prefix=OVERFLOW32-1
+## Addend == first positive integer.
+# RUN: yaml2obj --docnum=2 %s -o %t32.decimal.first.pos -DADDEND=1
+# RUN: llvm-readobj -r %t32.decimal.first.pos | FileCheck %s --check-prefix=TEST -DADDEND=0x1
+# RUN: yaml2obj --docnum=2 %s -o %t32.hex.first.pos -DADDEND=0x1
+# RUN: llvm-readobj -r %t32.hex.first.pos | FileCheck %s --check-prefix=TEST -DADDEND=0x1
 
-# OVERFLOW32-1: 0x0 R_386_PC32 foo 0x80000000{{$}}
+## Addend == 0.
+# RUN: yaml2obj --docnum=2 %s -o %t32.decimal.null -DADDEND=0
+# RUN: llvm-readobj -r %t32.decimal.null | FileCheck %s --check-prefix=TEST -DADDEND=0x0
+# RUN: yaml2obj --docnum=2 %s -o %t32.hex.null -DADDEND=0x0
+# RUN: llvm-readobj -r %t32.hex.null | FileCheck %s --check-prefix=TEST -DADDEND=0x0
 
-## Case 2.3: Document we accept an addend with the
-## value INT32_MIN = -2^31 = 0x80000000 = -2,147,483,648.
+## Addend == first negative integer.
+# RUN: yaml2obj --docnum=2 %s -o %t32.decimal.first.neg -DADDEND=-1
+# RUN: llvm-readobj -r %t32.decimal.first.neg | FileCheck %s --check-prefix=TEST -DADDEND=0xFFFFFFFF
+## We do not accept negative hex addends.
+# RUN: not yaml2obj --docnum=2 %s -o /dev/null -DADDEND=-0x1 2>&1 | FileCheck %s --check-prefix=ERR
 
-# RUN: yaml2obj --docnum=2 %s -o %t7 -D ADDEND=-2147483648
-# RUN: llvm-readobj -r %t7 | FileCheck %s --check-prefix=MIN32
-# RUN: yaml2obj --docnum=2 %s -o %t8 -D ADDEND=0x80000000
-# RUN: cmp %t7 %t8
+## Addend == INT32_MIN
+# RUN: yaml2obj --docnum=2 %s -o %t32.decimal.min -DADDEND=-2147483648
+# RUN: llvm-readobj -r %t32.decimal.min | FileCheck %s --check-prefix=TEST -DADDEND=0x80000000
 
-# MIN32: 0x0 R_386_PC32 foo 0x80000000{{$}}
+# Case 2.2: Document we do not accept any hex/decimal addends outside of the range specified.
 
-## Case 2.4: Check we report an error when an addend is less than INT32_MIN and
-## it is in decimal form. We use (INT32_MIN - 1).
+## Addend == 2^32.
+# RUN: not yaml2obj --docnum=2 %s -o /dev/null -DADDEND=4294967296 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj --docnum=2 %s -o /dev/null -DADDEND=0x100000000 2>&1 | FileCheck %s --check-prefix=ERR
 
-## FIXME: The following case should fail, see OVERFLOW64.
-# RUN: yaml2obj --docnum=2 %s -o %t9 -D ADDEND=-2147483649
-# RUN: llvm-readobj -r %t9 | FileCheck %s --check-prefix=OVERFLOW32-2
-
-# OVERFLOW32-2: 0x0 R_386_PC32 foo 0x7FFFFFFF{{$}}
+## Addend == INT32_MIN - 1.
+# RUN: not yaml2obj --docnum=2 %s -o /dev/null -DADDEND=-2147483649 2>&1 | FileCheck %s --check-prefix=ERR
 
 --- !ELF
 FileHeader:
@@ -112,3 +130,12 @@ Sections:
         Addend: [[ADDEND]]
 Symbols:
   - Name: foo
+
+## Case 3: Check we do not allow invalid values.
+# RUN: not yaml2obj %s -D ADDEND=0x1122GGEE 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -D ADDEND=-0x1122GGEE 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -D ADDEND=1234G5 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -D ADDEND=-1234G5 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -D ADDEND=foo 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -D ADDEND=- 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not yaml2obj %s -D ADDEND=--1234 2>&1 | FileCheck %s --check-prefix=ERR
diff --git a/llvm/tools/dsymutil/DwarfStreamer.cpp b/llvm/tools/dsymutil/DwarfStreamer.cpp
index 8719054f40dbd..c53d5d566e4f7 100644
--- a/llvm/tools/dsymutil/DwarfStreamer.cpp
+++ b/llvm/tools/dsymutil/DwarfStreamer.cpp
@@ -13,13 +13,16 @@
 #include "llvm/DWARFLinker/DWARFLinkerCompileUnit.h"
 #include "llvm/DebugInfo/DWARF/DWARFContext.h"
 #include "llvm/MC/MCTargetOptions.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 namespace llvm {
+
+static mc::RegisterMCTargetOptionsFlags MOF;
+
 namespace dsymutil {
 
 bool DwarfStreamer::init(Triple TheTriple) {
@@ -39,7 +42,7 @@ bool DwarfStreamer::init(Triple TheTriple) {
   if (!MRI)
     return error(Twine("no register info for target ") + TripleName, Context);
 
-  MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
   if (!MAI)
     return error("no asm info for target " + TripleName, Context);
diff --git a/llvm/tools/gold/gold-plugin.cpp b/llvm/tools/gold/gold-plugin.cpp
index 2a9398fed9f35..2db5716171816 100644
--- a/llvm/tools/gold/gold-plugin.cpp
+++ b/llvm/tools/gold/gold-plugin.cpp
@@ -14,7 +14,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Bitcode/BitcodeReader.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/Config/config.h" // plugin-api.h requires HAVE_STDINT_H
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DiagnosticPrinter.h"
@@ -50,6 +50,8 @@
 using namespace llvm;
 using namespace lto;
 
+static codegen::RegisterCodeGenFlags CodeGenFlags;
+
 // FIXME: Remove when binutils 2.31 (containing gold 1.16) is the minimum
 // required version.
 typedef enum ld_plugin_status (*ld_plugin_get_wrap_symbols)(
@@ -854,21 +856,21 @@ static std::unique_ptr<LTO> createLTO(IndexWriteCallback OnIndexWrite,
   ThinBackend Backend;
 
   Conf.CPU = options::mcpu;
-  Conf.Options = InitTargetOptionsFromCodeGenFlags();
+  Conf.Options = codegen::InitTargetOptionsFromCodeGenFlags();
 
   // Disable the new X86 relax relocations since gold might not support them.
   // FIXME: Check the gold version or add a new option to enable them.
   Conf.Options.RelaxELFRelocations = false;
 
   // Toggle function/data sections.
-  if (FunctionSections.getNumOccurrences() == 0)
+  if (!codegen::getExplicitFunctionSections())
     Conf.Options.FunctionSections = SplitSections;
-  if (DataSections.getNumOccurrences() == 0)
+  if (!codegen::getExplicitDataSections())
     Conf.Options.DataSections = SplitSections;
 
-  Conf.MAttrs = MAttrs;
+  Conf.MAttrs = codegen::getMAttrs();
   Conf.RelocModel = RelocationModel;
-  Conf.CodeModel = getCodeModel();
+  Conf.CodeModel = codegen::getExplicitCodeModel();
   Conf.CGOptLevel = getCGOptLevel();
   Conf.DisableVerify = options::DisableVerify;
   Conf.OptLevel = options::OptLevel;
diff --git a/llvm/tools/llc/CMakeLists.txt b/llvm/tools/llc/CMakeLists.txt
index 880deefa539c5..479bc6b55b27f 100644
--- a/llvm/tools/llc/CMakeLists.txt
+++ b/llvm/tools/llc/CMakeLists.txt
@@ -26,4 +26,5 @@ add_llvm_tool(llc
   intrinsics_gen
   SUPPORT_PLUGINS
   )
+
 export_executable_symbols(llc)
diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp
index 66102f0d795fd..a97d87d739a53 100644
--- a/llvm/tools/llc/llc.cpp
+++ b/llvm/tools/llc/llc.cpp
@@ -15,7 +15,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/LinkAllAsmWriterComponents.h"
 #include "llvm/CodeGen/LinkAllCodegenComponents.h"
 #include "llvm/CodeGen/MIRParser/MIRParser.h"
@@ -55,6 +55,8 @@
 #include <memory>
 using namespace llvm;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 // General options for llc.  Other pass-specific options are specified
 // within the corresponding llc passes, and target-specific options
 // and back-end code generation options are specified with the target machine.
@@ -202,7 +204,7 @@ static std::unique_ptr<ToolOutputFile> GetOutputStream(const char *TargetName,
       else
         OutputFilename = std::string(IFN);
 
-      switch (FileType) {
+      switch (codegen::getFileType()) {
       case CGFT_AssemblyFile:
         if (TargetName[0] == 'c') {
           if (TargetName[1] == 0)
@@ -229,7 +231,7 @@ static std::unique_ptr<ToolOutputFile> GetOutputStream(const char *TargetName,
 
   // Decide if we need "binary" output.
   bool Binary = false;
-  switch (FileType) {
+  switch (codegen::getFileType()) {
   case CGFT_AssemblyFile:
     break;
   case CGFT_ObjectFile:
@@ -395,14 +397,16 @@ static int compileModule(char **argv, LLVMContext &Context) {
   std::unique_ptr<Module> M;
   std::unique_ptr<MIRParser> MIR;
   Triple TheTriple;
-  std::string CPUStr = getCPUStr(), FeaturesStr = getFeaturesStr();
+  std::string CPUStr = codegen::getCPUStr(),
+              FeaturesStr = codegen::getFeaturesStr();
 
   // Set attributes on functions as loaded from MIR from command line arguments.
   auto setMIRFunctionAttributes = [&CPUStr, &FeaturesStr](Function &F) {
-    setFunctionAttributes(CPUStr, FeaturesStr, F);
+    codegen::setFunctionAttributes(CPUStr, FeaturesStr, F);
   };
 
-  bool SkipModule = MCPU == "help" ||
+  auto MAttrs = codegen::getMAttrs();
+  bool SkipModule = codegen::getMCPU() == "help" ||
                     (!MAttrs.empty() && MAttrs.front() == "help");
 
   // If user just wants to list available options, skip module loading
@@ -433,8 +437,8 @@ static int compileModule(char **argv, LLVMContext &Context) {
 
   // Get the target specific parser.
   std::string Error;
-  const Target *TheTarget = TargetRegistry::lookupTarget(MArch, TheTriple,
-                                                         Error);
+  const Target *TheTarget =
+      TargetRegistry::lookupTarget(codegen::getMArch(), TheTriple, Error);
   if (!TheTarget) {
     WithColor::error(errs(), argv[0]) << Error;
     return 1;
@@ -452,7 +456,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
   case '3': OLvl = CodeGenOpt::Aggressive; break;
   }
 
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   Options.DisableIntegratedAS = NoIntegratedAssembler;
   Options.MCOptions.ShowMCEncoding = ShowMCEncoding;
   Options.MCOptions.MCUseDwarfDirectory = EnableDwarfDirectory;
@@ -463,7 +467,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
 
   // On AIX, setting the relocation model to anything other than PIC is considered
   // a user error.
-  Optional<Reloc::Model> RM = getRelocModel();
+  Optional<Reloc::Model> RM = codegen::getExplicitRelocModel();
   if (TheTriple.isOSAIX() && RM.hasValue() && *RM != Reloc::PIC_) {
     WithColor::error(errs(), argv[0])
         << "invalid relocation model, AIX only supports PIC.\n";
@@ -472,7 +476,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
 
   std::unique_ptr<TargetMachine> Target(TheTarget->createTargetMachine(
       TheTriple.getTriple(), CPUStr, FeaturesStr, Options, RM,
-      getCodeModel(), OLvl));
+      codegen::getExplicitCodeModel(), OLvl));
 
   assert(Target && "Could not allocate target machine!");
 
@@ -483,8 +487,8 @@ static int compileModule(char **argv, LLVMContext &Context) {
     return 0;
 
   assert(M && "Should have exited if we didn't have a module!");
-  if (FloatABIForCalls != FloatABI::Default)
-    Options.FloatABIType = FloatABIForCalls;
+  if (codegen::getFloatABIForCalls() != FloatABI::Default)
+    Options.FloatABIType = codegen::getFloatABIForCalls();
 
   // Figure out where we are going to send the output.
   std::unique_ptr<ToolOutputFile> Out =
@@ -531,10 +535,9 @@ static int compileModule(char **argv, LLVMContext &Context) {
 
   // Override function attributes based on CPUStr, FeaturesStr, and command line
   // flags.
-  setFunctionAttributes(CPUStr, FeaturesStr, *M);
+  codegen::setFunctionAttributes(CPUStr, FeaturesStr, *M);
 
-  if (RelaxAll.getNumOccurrences() > 0 &&
-      FileType != CGFT_ObjectFile)
+  if (mc::getExplicitRelaxAll() && codegen::getFileType() != CGFT_ObjectFile)
     WithColor::warning(errs(), argv[0])
         << ": warning: ignoring -mc-relax-all because filetype != obj";
 
@@ -545,7 +548,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
     // so we can memcmp the contents in CompileTwice mode
     SmallVector<char, 0> Buffer;
     std::unique_ptr<raw_svector_ostream> BOS;
-    if ((FileType != CGFT_AssemblyFile &&
+    if ((codegen::getFileType() != CGFT_AssemblyFile &&
          !Out->os().supportsSeeking()) ||
         CompileTwice) {
       BOS = std::make_unique<raw_svector_ostream>(Buffer);
@@ -584,9 +587,9 @@ static int compileModule(char **argv, LLVMContext &Context) {
       TPC.setInitialized();
       PM.add(createPrintMIRPass(*OS));
       PM.add(createFreeMachineFunctionPass());
-    } else if (Target->addPassesToEmitFile(PM, *OS,
-                                           DwoOut ? &DwoOut->os() : nullptr,
-                                           FileType, NoVerify, MMIWP)) {
+    } else if (Target->addPassesToEmitFile(
+                   PM, *OS, DwoOut ? &DwoOut->os() : nullptr,
+                   codegen::getFileType(), NoVerify, MMIWP)) {
       WithColor::warning(errs(), argv[0])
           << "target does not support generation of this"
           << " file type!\n";
diff --git a/llvm/tools/lli/CMakeLists.txt b/llvm/tools/lli/CMakeLists.txt
index db163ad131e85..bc6ef213b8fd5 100644
--- a/llvm/tools/lli/CMakeLists.txt
+++ b/llvm/tools/lli/CMakeLists.txt
@@ -53,4 +53,5 @@ add_llvm_tool(lli
   DEPENDS
   intrinsics_gen
   )
+
 export_executable_symbols(lli)
diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp
index 80e08f0a94ff5..f7a0022b68c4f 100644
--- a/llvm/tools/lli/lli.cpp
+++ b/llvm/tools/lli/lli.cpp
@@ -16,7 +16,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Bitcode/BitcodeReader.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/LinkAllCodegenComponents.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/ExecutionEngine/GenericValue.h"
@@ -69,6 +69,8 @@
 
 using namespace llvm;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 #define DEBUG_TYPE "lli"
 
 namespace {
@@ -435,13 +437,13 @@ int main(int argc, char **argv, char * const *envp) {
 
   std::string ErrorMsg;
   EngineBuilder builder(std::move(Owner));
-  builder.setMArch(MArch);
-  builder.setMCPU(getCPUStr());
-  builder.setMAttrs(getFeatureList());
-  if (RelocModel.getNumOccurrences())
-    builder.setRelocationModel(RelocModel);
-  if (CMModel.getNumOccurrences())
-    builder.setCodeModel(CMModel);
+  builder.setMArch(codegen::getMArch());
+  builder.setMCPU(codegen::getCPUStr());
+  builder.setMAttrs(codegen::getFeatureList());
+  if (auto RM = codegen::getExplicitRelocModel())
+    builder.setRelocationModel(RM.getValue());
+  if (auto CM = codegen::getExplicitCodeModel())
+    builder.setCodeModel(CM.getValue());
   builder.setErrorStr(&ErrorMsg);
   builder.setEngineKind(ForceInterpreter
                         ? EngineKind::Interpreter
@@ -473,9 +475,9 @@ int main(int argc, char **argv, char * const *envp) {
 
   builder.setOptLevel(getOptLevel());
 
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
-  if (FloatABIForCalls != FloatABI::Default)
-    Options.FloatABIType = FloatABIForCalls;
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
+  if (codegen::getFloatABIForCalls() != FloatABI::Default)
+    Options.FloatABIType = codegen::getFloatABIForCalls();
 
   builder.setTargetOptions(Options);
 
@@ -827,18 +829,15 @@ int runOrcLazyJIT(const char *ProgName) {
   if (DL)
     Builder.setDataLayout(DL);
 
-  if (!MArch.empty())
-    Builder.getJITTargetMachineBuilder()->getTargetTriple().setArchName(MArch);
+  if (!codegen::getMArch().empty())
+    Builder.getJITTargetMachineBuilder()->getTargetTriple().setArchName(
+        codegen::getMArch());
 
   Builder.getJITTargetMachineBuilder()
-      ->setCPU(getCPUStr())
-      .addFeatures(getFeatureList())
-      .setRelocationModel(RelocModel.getNumOccurrences()
-                              ? Optional<Reloc::Model>(RelocModel)
-                              : None)
-      .setCodeModel(CMModel.getNumOccurrences()
-                        ? Optional<CodeModel::Model>(CMModel)
-                        : None);
+      ->setCPU(codegen::getCPUStr())
+      .addFeatures(codegen::getFeatureList())
+      .setRelocationModel(codegen::getExplicitRelocModel())
+      .setCodeModel(codegen::getExplicitCodeModel());
 
   Builder.setLazyCompileFailureAddr(
       pointerToJITTargetAddress(exitOnLazyCallThroughFailure));
diff --git a/llvm/tools/llvm-dwp/llvm-dwp.cpp b/llvm/tools/llvm-dwp/llvm-dwp.cpp
index 4eff8476d61f5..df524ad0a2e8f 100644
--- a/llvm/tools/llvm-dwp/llvm-dwp.cpp
+++ b/llvm/tools/llvm-dwp/llvm-dwp.cpp
@@ -27,7 +27,7 @@
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/Object/Decompressor.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/DataExtractor.h"
@@ -46,6 +46,8 @@
 using namespace llvm;
 using namespace llvm::object;
 
+static mc::RegisterMCTargetOptionsFlags MCTargetOptionsFlags;
+
 cl::OptionCategory DwpCategory("Specific Options");
 static cl::list<std::string> InputFiles(cl::Positional, cl::ZeroOrMore,
                                         cl::desc("<input files>"),
@@ -686,7 +688,7 @@ int main(int argc, char **argv) {
   if (!MRI)
     return error(Twine("no register info for target ") + TripleName, Context);
 
-  MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  MCTargetOptions MCOptions = llvm::mc::InitMCTargetOptionsFromFlags();
   std::unique_ptr<MCAsmInfo> MAI(
       TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
   if (!MAI)
diff --git a/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp b/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp
index b71ed4a705667..627e9ab4c03fb 100644
--- a/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp
+++ b/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp
@@ -14,7 +14,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Bitcode/BitcodeReader.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/FuzzMutate/FuzzerCLI.h"
 #include "llvm/FuzzMutate/IRMutator.h"
 #include "llvm/FuzzMutate/Operations.h"
@@ -35,6 +35,8 @@
 
 using namespace llvm;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 static cl::opt<char>
 OptLevel("O",
          cl::desc("Optimization level. [-O0, -O1, -O2, or -O3] "
@@ -133,14 +135,15 @@ extern "C" LLVM_ATTRIBUTE_USED int LLVMFuzzerInitialize(int *argc,
   // Get the target specific parser.
   std::string Error;
   const Target *TheTarget =
-      TargetRegistry::lookupTarget(MArch, TheTriple, Error);
+      TargetRegistry::lookupTarget(codegen::getMArch(), TheTriple, Error);
   if (!TheTarget) {
     errs() << argv[0] << ": " << Error;
     return 1;
   }
 
   // Set up the pipeline like llc does.
-  std::string CPUStr = getCPUStr(), FeaturesStr = getFeaturesStr();
+  std::string CPUStr = codegen::getCPUStr(),
+              FeaturesStr = codegen::getFeaturesStr();
 
   CodeGenOpt::Level OLvl = CodeGenOpt::Default;
   switch (OptLevel) {
@@ -154,10 +157,10 @@ extern "C" LLVM_ATTRIBUTE_USED int LLVMFuzzerInitialize(int *argc,
   case '3': OLvl = CodeGenOpt::Aggressive; break;
   }
 
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
-  TM.reset(TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr,
-                                          FeaturesStr, Options, getRelocModel(),
-                                          getCodeModel(), OLvl));
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
+  TM.reset(TheTarget->createTargetMachine(
+      TheTriple.getTriple(), CPUStr, FeaturesStr, Options,
+      codegen::getExplicitRelocModel(), codegen::getExplicitCodeModel(), OLvl));
   assert(TM && "Could not allocate target machine!");
 
   // Make sure we print the summary and the current unit when LLVM errors out.
diff --git a/llvm/tools/llvm-lto/CMakeLists.txt b/llvm/tools/llvm-lto/CMakeLists.txt
index 69868fb870c04..5128e713eecfd 100644
--- a/llvm/tools/llvm-lto/CMakeLists.txt
+++ b/llvm/tools/llvm-lto/CMakeLists.txt
@@ -5,6 +5,7 @@ set(LLVM_LINK_COMPONENTS
   AllTargetsInfos
   BitReader
   BitWriter
+  CodeGen
   Core
   IRReader
   LTO
@@ -17,7 +18,5 @@ set(LLVM_LINK_COMPONENTS
 add_llvm_tool(llvm-lto
   llvm-lto.cpp
 
-  DEPENDS
-  intrinsics_gen
+  DEPENDS intrinsics_gen
   )
-
diff --git a/llvm/tools/llvm-lto/llvm-lto.cpp b/llvm/tools/llvm-lto/llvm-lto.cpp
index af3fa0acc39cf..0bd9078f2d8ca 100644
--- a/llvm/tools/llvm-lto/llvm-lto.cpp
+++ b/llvm/tools/llvm-lto/llvm-lto.cpp
@@ -21,7 +21,7 @@
 #include "llvm/ADT/Twine.h"
 #include "llvm/Bitcode/BitcodeReader.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/LLVMContext.h"
@@ -62,6 +62,8 @@
 
 using namespace llvm;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 static cl::opt<char>
     OptLevel("O", cl::desc("Optimization level. [-O0, -O1, -O2, or -O3] "
                            "(default = '-O2')"),
@@ -412,7 +414,7 @@ static void printMachOCPUOnly() {
   LLVMContext Context;
   Context.setDiagnosticHandler(std::make_unique<LLVMLTODiagnosticHandler>(),
                                true);
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   for (auto &Filename : InputFilenames) {
     ErrorOr<std::unique_ptr<LTOModule>> ModuleOrErr =
         LTOModule::createFromFile(Context, Filename, Options);
@@ -549,7 +551,7 @@ class ThinLTOProcessing {
   ThinLTOCodeGenerator ThinGenerator;
 
   ThinLTOProcessing(const TargetOptions &Options) {
-    ThinGenerator.setCodePICModel(getRelocModel());
+    ThinGenerator.setCodePICModel(codegen::getExplicitRelocModel());
     ThinGenerator.setTargetOptions(Options);
     ThinGenerator.setCacheDir(ThinLTOCacheDir);
     ThinGenerator.setCachePruningInterval(ThinLTOCachePruningInterval);
@@ -901,7 +903,7 @@ int main(int argc, char **argv) {
   InitializeAllAsmParsers();
 
   // set up the TargetOptions for the machine
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
 
   if (ListSymbolsOnly) {
     listSymbols(Options);
@@ -962,7 +964,7 @@ int main(int argc, char **argv) {
   if (UseDiagnosticHandler)
     CodeGen.setDiagnosticHandler(handleDiagnostics, nullptr);
 
-  CodeGen.setCodePICModel(getRelocModel());
+  CodeGen.setCodePICModel(codegen::getExplicitRelocModel());
   CodeGen.setFreestanding(EnableFreestanding);
 
   CodeGen.setDebugInfo(LTO_DEBUG_MODEL_DWARF);
@@ -1013,22 +1015,18 @@ int main(int argc, char **argv) {
     CodeGen.addMustPreserveSymbol(KeptDSOSyms[i]);
 
   // Set cpu and attrs strings for the default target/subtarget.
-  CodeGen.setCpu(MCPU.c_str());
+  CodeGen.setCpu(codegen::getMCPU().c_str());
 
   CodeGen.setOptLevel(OptLevel - '0');
 
-  std::string attrs;
-  for (unsigned i = 0; i < MAttrs.size(); ++i) {
-    if (i > 0)
-      attrs.append(",");
-    attrs.append(MAttrs[i]);
-  }
-
-  if (!attrs.empty())
+  auto MAttrs = codegen::getMAttrs();
+  if (!MAttrs.empty()) {
+    std::string attrs = join(MAttrs, ",");
     CodeGen.setAttr(attrs);
+  }
 
-  if (FileType.getNumOccurrences())
-    CodeGen.setFileType(FileType);
+  if (auto FT = codegen::getExplicitFileType())
+    CodeGen.setFileType(FT.getValue());
 
   if (!OutputFilename.empty()) {
     if (!CodeGen.optimize(DisableVerify, DisableInline, DisableGVNLoadPRE,
diff --git a/llvm/tools/llvm-lto2/CMakeLists.txt b/llvm/tools/llvm-lto2/CMakeLists.txt
index fa2d8624fd94e..4d3364175b049 100644
--- a/llvm/tools/llvm-lto2/CMakeLists.txt
+++ b/llvm/tools/llvm-lto2/CMakeLists.txt
@@ -4,6 +4,7 @@ set(LLVM_LINK_COMPONENTS
   AllTargetsDescs
   AllTargetsInfos
   BitReader
+  CodeGen
   Core
   Linker
   LTO
diff --git a/llvm/tools/llvm-lto2/llvm-lto2.cpp b/llvm/tools/llvm-lto2/llvm-lto2.cpp
index ee16a473dbc2c..dda596be0ce66 100644
--- a/llvm/tools/llvm-lto2/llvm-lto2.cpp
+++ b/llvm/tools/llvm-lto2/llvm-lto2.cpp
@@ -16,7 +16,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Bitcode/BitcodeReader.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/LTO/Caching.h"
 #include "llvm/LTO/LTO.h"
@@ -29,6 +29,8 @@
 using namespace llvm;
 using namespace lto;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 static cl::opt<char>
     OptLevel("O", cl::desc("Optimization level. [-O0, -O1, -O2, or -O3] "
                            "(default = '-O2')"),
@@ -220,12 +222,12 @@ static int run(int argc, char **argv) {
       exit(1);
   };
 
-  Conf.CPU = MCPU;
-  Conf.Options = InitTargetOptionsFromCodeGenFlags();
-  Conf.MAttrs = MAttrs;
-  if (auto RM = getRelocModel())
-    Conf.RelocModel = *RM;
-  Conf.CodeModel = getCodeModel();
+  Conf.CPU = codegen::getMCPU();
+  Conf.Options = codegen::InitTargetOptionsFromCodeGenFlags();
+  Conf.MAttrs = codegen::getMAttrs();
+  if (auto RM = codegen::getExplicitRelocModel())
+    Conf.RelocModel = RM.getValue();
+  Conf.CodeModel = codegen::getExplicitCodeModel();
 
   Conf.DebugPassManager = DebugPassManager;
 
@@ -267,8 +269,8 @@ static int run(int argc, char **argv) {
     return 1;
   }
 
-  if (FileType.getNumOccurrences())
-    Conf.CGFileType = FileType;
+  if (auto FT = codegen::getExplicitFileType())
+    Conf.CGFileType = FT.getValue();
 
   Conf.OverrideTriple = OverrideTriple;
   Conf.DefaultTriple = DefaultTriple;
diff --git a/llvm/tools/llvm-mc-assemble-fuzzer/CMakeLists.txt b/llvm/tools/llvm-mc-assemble-fuzzer/CMakeLists.txt
index d92fdb6137ac5..d7835c830674f 100644
--- a/llvm/tools/llvm-mc-assemble-fuzzer/CMakeLists.txt
+++ b/llvm/tools/llvm-mc-assemble-fuzzer/CMakeLists.txt
@@ -6,6 +6,7 @@ set(LLVM_LINK_COMPONENTS
     MCParser
     Support
 )
+
 add_llvm_fuzzer(llvm-mc-assemble-fuzzer
   llvm-mc-assemble-fuzzer.cpp
   )
diff --git a/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp b/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
index 6c5961f7027c7..29699c634bfa4 100644
--- a/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
+++ b/llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
@@ -9,7 +9,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm-c/Target.h"
-#include "llvm/MC/SubtargetFeature.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCCodeEmitter.h"
@@ -24,15 +23,16 @@
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
-#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
+#include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FileUtilities.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
-#include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/ToolOutputFile.h"
+#include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
@@ -161,7 +161,7 @@ int AssembleOneInput(const uint8_t *Data, size_t Size) {
     abort();
   }
 
-  MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   std::unique_ptr<MCAsmInfo> MAI(
       TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
   if (!MAI) {
diff --git a/llvm/tools/llvm-mc/CMakeLists.txt b/llvm/tools/llvm-mc/CMakeLists.txt
index a18783e828b85..87df3c3b51478 100644
--- a/llvm/tools/llvm-mc/CMakeLists.txt
+++ b/llvm/tools/llvm-mc/CMakeLists.txt
@@ -3,6 +3,7 @@ set(LLVM_LINK_COMPONENTS
   AllTargetsDescs
   AllTargetsDisassemblers
   AllTargetsInfos
+  CodeGen
   MC
   MCParser
   Support
diff --git a/llvm/tools/llvm-mc/llvm-mc.cpp b/llvm/tools/llvm-mc/llvm-mc.cpp
index dadb7f5ca22f9..eee51a5179e98 100644
--- a/llvm/tools/llvm-mc/llvm-mc.cpp
+++ b/llvm/tools/llvm-mc/llvm-mc.cpp
@@ -25,7 +25,7 @@
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/FileUtilities.h"
@@ -41,6 +41,8 @@
 
 using namespace llvm;
 
+static mc::RegisterMCTargetOptionsFlags MOF;
+
 static cl::opt<std::string>
 InputFilename(cl::Positional, cl::desc("<input file>"), cl::init("-"));
 
@@ -317,7 +319,7 @@ int main(int argc, char **argv) {
   cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
 
   cl::ParseCommandLineOptions(argc, argv, "llvm machine code playground\n");
-  const MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  const MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   setDwarfDebugFlags(argc, argv);
 
   setDwarfDebugProducer();
diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp
index 06c1ce957f74c..9f3bf41ff3f8b 100644
--- a/llvm/tools/llvm-mca/llvm-mca.cpp
+++ b/llvm/tools/llvm-mca/llvm-mca.cpp
@@ -39,7 +39,7 @@
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/MCA/CodeEmitter.h"
 #include "llvm/MCA/Context.h"
 #include "llvm/MCA/InstrBuilder.h"
@@ -62,6 +62,8 @@
 
 using namespace llvm;
 
+static mc::RegisterMCTargetOptionsFlags MOF;
+
 static cl::OptionCategory ToolOptions("Tool Options");
 static cl::OptionCategory ViewOptions("View Options");
 
@@ -353,7 +355,7 @@ int main(int argc, char **argv) {
   std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
   assert(MRI && "Unable to create target register info!");
 
-  MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   std::unique_ptr<MCAsmInfo> MAI(
       TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
   assert(MAI && "Unable to create target asm info!");
@@ -443,7 +445,7 @@ int main(int argc, char **argv) {
       TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
 
   std::unique_ptr<MCAsmBackend> MAB(TheTarget->createMCAsmBackend(
-      *STI, *MRI, InitMCTargetOptionsFromFlags()));
+      *STI, *MRI, mc::InitMCTargetOptionsFromFlags()));
 
   for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
     // Skip empty code regions.
diff --git a/llvm/tools/llvm-ml/llvm-ml.cpp b/llvm/tools/llvm-ml/llvm-ml.cpp
index 5eefc1e518fdc..2d4a3afdc1f93 100644
--- a/llvm/tools/llvm-ml/llvm-ml.cpp
+++ b/llvm/tools/llvm-ml/llvm-ml.cpp
@@ -25,7 +25,7 @@
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/FileUtilities.h"
@@ -41,6 +41,8 @@
 
 using namespace llvm;
 
+static mc::RegisterMCTargetOptionsFlags MOF;
+
 static cl::opt<std::string>
 InputFilename(cl::Positional, cl::desc("<input file>"), cl::init("-"));
 
@@ -222,7 +224,7 @@ int main(int argc, char **argv) {
   cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
 
   cl::ParseCommandLineOptions(argc, argv, "llvm machine code playground\n");
-  MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   MCOptions.AssemblyLanguage = "masm";
 
   const char *ProgName = argv[0];
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 69f437fcc0638..1cfd06d2cef5e 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2339,7 +2339,9 @@ int main(int argc, char **argv) {
   // Register the target printer for --version.
   cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
 
-  cl::ParseCommandLineOptions(argc, argv, "llvm object file dumper\n");
+  cl::ParseCommandLineOptions(argc, argv, "llvm object file dumper\n", nullptr,
+                              /*EnvVar=*/nullptr,
+                              /*LongOptionsUseDoubleDash=*/true);
 
   if (StartAddress >= StopAddress)
     reportCmdLineError("start address should be less than stop address");
diff --git a/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp b/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
index cd6c7d380cc6c..e353e333f5805 100644
--- a/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
+++ b/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
@@ -12,7 +12,7 @@
 
 #include "llvm/Bitcode/BitcodeReader.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/FuzzMutate/FuzzerCLI.h"
 #include "llvm/FuzzMutate/IRMutator.h"
 #include "llvm/IR/Verifier.h"
@@ -24,6 +24,8 @@
 
 using namespace llvm;
 
+static codegen::RegisterCodeGenFlags CGF;
+
 static cl::opt<std::string>
     TargetTripleStr("mtriple", cl::desc("Override target triple for module"));
 
@@ -124,7 +126,8 @@ extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
 
   M->setTargetTriple(TM->getTargetTriple().normalize());
   M->setDataLayout(TM->createDataLayout());
-  setFunctionAttributes(TM->getTargetCPU(), TM->getTargetFeatureString(), *M);
+  codegen::setFunctionAttributes(TM->getTargetCPU(),
+                                 TM->getTargetFeatureString(), *M);
 
   // Create pass pipeline
   //
@@ -214,16 +217,17 @@ extern "C" LLVM_ATTRIBUTE_USED int LLVMFuzzerInitialize(
 
   std::string Error;
   const Target *TheTarget =
-      TargetRegistry::lookupTarget(MArch, TargetTriple, Error);
+      TargetRegistry::lookupTarget(codegen::getMArch(), TargetTriple, Error);
   if (!TheTarget) {
     errs() << *argv[0] << ": " << Error;
     exit(1);
   }
 
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   TM.reset(TheTarget->createTargetMachine(
-      TargetTriple.getTriple(), getCPUStr(), getFeaturesStr(),
-     Options, getRelocModel(), getCodeModel(), CodeGenOpt::Default));
+      TargetTriple.getTriple(), codegen::getCPUStr(), codegen::getFeaturesStr(),
+      Options, codegen::getExplicitRelocModel(),
+      codegen::getExplicitCodeModel(), CodeGenOpt::Default));
   assert(TM && "Could not allocate target machine!");
 
   // Check that pass pipeline is specified and correct
diff --git a/llvm/tools/llvm-readobj/COFFDumper.cpp b/llvm/tools/llvm-readobj/COFFDumper.cpp
index ffe331a3d240c..bd4ab0e7dec97 100644
--- a/llvm/tools/llvm-readobj/COFFDumper.cpp
+++ b/llvm/tools/llvm-readobj/COFFDumper.cpp
@@ -104,6 +104,7 @@ class COFFDumper : public ObjDumper {
                           bool GHash) override;
   void printStackMap() const override;
   void printAddrsig() override;
+
 private:
   void printSymbols() override;
   void printDynamicSymbols() override;
@@ -409,6 +410,11 @@ static const EnumEntry<COFF::DLLCharacteristics> PEDLLCharacteristics[] = {
   LLVM_READOBJ_ENUM_ENT(COFF, IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE),
 };
 
+static const EnumEntry<COFF::ExtendedDLLCharacteristics>
+    PEExtendedDLLCharacteristics[] = {
+        LLVM_READOBJ_ENUM_ENT(COFF, IMAGE_DLL_CHARACTERISTICS_EX_CET_COMPAT),
+};
+
 static const EnumEntry<COFF::SectionCharacteristics>
 ImageSectionCharacteristics[] = {
   LLVM_READOBJ_ENUM_ENT(COFF, IMAGE_SCN_TYPE_NOLOAD           ),
@@ -516,23 +522,25 @@ static const EnumEntry<COFF::COMDATType> ImageCOMDATSelect[] = {
 };
 
 static const EnumEntry<COFF::DebugType> ImageDebugType[] = {
-  { "Unknown"    , COFF::IMAGE_DEBUG_TYPE_UNKNOWN       },
-  { "COFF"       , COFF::IMAGE_DEBUG_TYPE_COFF          },
-  { "CodeView"   , COFF::IMAGE_DEBUG_TYPE_CODEVIEW      },
-  { "FPO"        , COFF::IMAGE_DEBUG_TYPE_FPO           },
-  { "Misc"       , COFF::IMAGE_DEBUG_TYPE_MISC          },
-  { "Exception"  , COFF::IMAGE_DEBUG_TYPE_EXCEPTION     },
-  { "Fixup"      , COFF::IMAGE_DEBUG_TYPE_FIXUP         },
-  { "OmapToSrc"  , COFF::IMAGE_DEBUG_TYPE_OMAP_TO_SRC   },
-  { "OmapFromSrc", COFF::IMAGE_DEBUG_TYPE_OMAP_FROM_SRC },
-  { "Borland"    , COFF::IMAGE_DEBUG_TYPE_BORLAND       },
-  { "Reserved10" , COFF::IMAGE_DEBUG_TYPE_RESERVED10    },
-  { "CLSID"      , COFF::IMAGE_DEBUG_TYPE_CLSID         },
-  { "VCFeature"  , COFF::IMAGE_DEBUG_TYPE_VC_FEATURE    },
-  { "POGO"       , COFF::IMAGE_DEBUG_TYPE_POGO          },
-  { "ILTCG"      , COFF::IMAGE_DEBUG_TYPE_ILTCG         },
-  { "MPX"        , COFF::IMAGE_DEBUG_TYPE_MPX           },
-  { "Repro"      , COFF::IMAGE_DEBUG_TYPE_REPRO         },
+    {"Unknown", COFF::IMAGE_DEBUG_TYPE_UNKNOWN},
+    {"COFF", COFF::IMAGE_DEBUG_TYPE_COFF},
+    {"CodeView", COFF::IMAGE_DEBUG_TYPE_CODEVIEW},
+    {"FPO", COFF::IMAGE_DEBUG_TYPE_FPO},
+    {"Misc", COFF::IMAGE_DEBUG_TYPE_MISC},
+    {"Exception", COFF::IMAGE_DEBUG_TYPE_EXCEPTION},
+    {"Fixup", COFF::IMAGE_DEBUG_TYPE_FIXUP},
+    {"OmapToSrc", COFF::IMAGE_DEBUG_TYPE_OMAP_TO_SRC},
+    {"OmapFromSrc", COFF::IMAGE_DEBUG_TYPE_OMAP_FROM_SRC},
+    {"Borland", COFF::IMAGE_DEBUG_TYPE_BORLAND},
+    {"Reserved10", COFF::IMAGE_DEBUG_TYPE_RESERVED10},
+    {"CLSID", COFF::IMAGE_DEBUG_TYPE_CLSID},
+    {"VCFeature", COFF::IMAGE_DEBUG_TYPE_VC_FEATURE},
+    {"POGO", COFF::IMAGE_DEBUG_TYPE_POGO},
+    {"ILTCG", COFF::IMAGE_DEBUG_TYPE_ILTCG},
+    {"MPX", COFF::IMAGE_DEBUG_TYPE_MPX},
+    {"Repro", COFF::IMAGE_DEBUG_TYPE_REPRO},
+    {"ExtendedDLLCharacteristics",
+     COFF::IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS},
 };
 
 static const EnumEntry<COFF::WeakExternalCharacteristics>
@@ -736,12 +744,19 @@ void COFFDumper::printCOFFDebugDirectory() {
         W.printString("PDBFileName", PDBFileName);
       }
     } else if (D.SizeOfData != 0) {
-      // FIXME: Type values of 12 and 13 are commonly observed but are not in
-      // the documented type enum.  Figure out what they mean.
+      // FIXME: Data visualization for IMAGE_DEBUG_TYPE_VC_FEATURE and
+      // IMAGE_DEBUG_TYPE_POGO?
       ArrayRef<uint8_t> RawData;
       if (std::error_code EC = Obj->getRvaAndSizeAsBytes(D.AddressOfRawData,
                                                          D.SizeOfData, RawData))
         reportError(errorCodeToError(EC), Obj->getFileName());
+      if (D.Type == COFF::IMAGE_DEBUG_TYPE_EX_DLLCHARACTERISTICS) {
+        // FIXME right now the only possible value would fit in 8 bits,
+        // but that might change in the future
+        uint16_t Characteristics = RawData[0];
+        W.printFlags("ExtendedCharacteristics", Characteristics,
+                     makeArrayRef(PEExtendedDLLCharacteristics));
+      }
       W.printBinaryBlock("RawData", RawData);
     }
   }
diff --git a/llvm/tools/lto/CMakeLists.txt b/llvm/tools/lto/CMakeLists.txt
index b86e4abd01a79..2963f97cad887 100644
--- a/llvm/tools/lto/CMakeLists.txt
+++ b/llvm/tools/lto/CMakeLists.txt
@@ -6,6 +6,7 @@ set(LLVM_LINK_COMPONENTS
   AllTargetsInfos
   BitReader
   Core
+  CodeGen
   LTO
   MC
   MCDisassembler
@@ -20,7 +21,8 @@ set(SOURCES
 
 set(LLVM_EXPORTED_SYMBOL_FILE ${CMAKE_CURRENT_SOURCE_DIR}/lto.exports)
 
-add_llvm_library(LTO SHARED INSTALL_WITH_TOOLCHAIN ${SOURCES} DEPENDS intrinsics_gen)
+add_llvm_library(LTO SHARED INSTALL_WITH_TOOLCHAIN ${SOURCES} DEPENDS
+    intrinsics_gen)
 
 install(FILES ${LLVM_MAIN_INCLUDE_DIR}/llvm-c/lto.h
   DESTINATION include/llvm-c
diff --git a/llvm/tools/lto/lto.cpp b/llvm/tools/lto/lto.cpp
index 683c2b2ae3003..d48580606c4b2 100644
--- a/llvm/tools/lto/lto.cpp
+++ b/llvm/tools/lto/lto.cpp
@@ -15,7 +15,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Bitcode/BitcodeReader.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/LLVMContext.h"
@@ -28,6 +28,10 @@
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/raw_ostream.h"
 
+using namespace llvm;
+
+static codegen::RegisterCodeGenFlags CGF;
+
 // extra command-line flags needed for LTOCodeGenerator
 static cl::opt<char>
 OptLevel("O",
@@ -154,14 +158,9 @@ DEFINE_SIMPLE_CONVERSION_FUNCTIONS(LTOModule, lto_module_t)
 // Convert the subtarget features into a string to pass to LTOCodeGenerator.
 static void lto_add_attrs(lto_code_gen_t cg) {
   LTOCodeGenerator *CG = unwrap(cg);
-  if (MAttrs.size()) {
-    std::string attrs;
-    for (unsigned i = 0; i < MAttrs.size(); ++i) {
-      if (i > 0)
-        attrs.append(",");
-      attrs.append(MAttrs[i]);
-    }
-
+  auto MAttrs = codegen::getMAttrs();
+  if (!MAttrs.empty()) {
+    std::string attrs = join(MAttrs, ",");
     CG->setAttr(attrs);
   }
 
@@ -219,7 +218,7 @@ lto_module_is_object_file_in_memory_for_target(const void* mem,
 
 lto_module_t lto_module_create(const char* path) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   ErrorOr<std::unique_ptr<LTOModule>> M =
       LTOModule::createFromFile(*LTOContext, StringRef(path), Options);
   if (!M)
@@ -229,7 +228,7 @@ lto_module_t lto_module_create(const char* path) {
 
 lto_module_t lto_module_create_from_fd(int fd, const char *path, size_t size) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   ErrorOr<std::unique_ptr<LTOModule>> M = LTOModule::createFromOpenFile(
       *LTOContext, fd, StringRef(path), size, Options);
   if (!M)
@@ -242,7 +241,7 @@ lto_module_t lto_module_create_from_fd_at_offset(int fd, const char *path,
                                                  size_t map_size,
                                                  off_t offset) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   ErrorOr<std::unique_ptr<LTOModule>> M = LTOModule::createFromOpenFileSlice(
       *LTOContext, fd, StringRef(path), map_size, offset, Options);
   if (!M)
@@ -252,7 +251,7 @@ lto_module_t lto_module_create_from_fd_at_offset(int fd, const char *path,
 
 lto_module_t lto_module_create_from_memory(const void* mem, size_t length) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   ErrorOr<std::unique_ptr<LTOModule>> M =
       LTOModule::createFromBuffer(*LTOContext, mem, length, Options);
   if (!M)
@@ -264,7 +263,7 @@ lto_module_t lto_module_create_from_memory_with_path(const void* mem,
                                                      size_t length,
                                                      const char *path) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   ErrorOr<std::unique_ptr<LTOModule>> M = LTOModule::createFromBuffer(
       *LTOContext, mem, length, Options, StringRef(path));
   if (!M)
@@ -275,7 +274,7 @@ lto_module_t lto_module_create_from_memory_with_path(const void* mem,
 lto_module_t lto_module_create_in_local_context(const void *mem, size_t length,
                                                 const char *path) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
 
   // Create a local context. Ownership will be transferred to LTOModule.
   std::unique_ptr<LLVMContext> Context = std::make_unique<LLVMContext>();
@@ -294,7 +293,7 @@ lto_module_t lto_module_create_in_codegen_context(const void *mem,
                                                   const char *path,
                                                   lto_code_gen_t cg) {
   lto_initialize();
-  llvm::TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  llvm::TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
   ErrorOr<std::unique_ptr<LTOModule>> M = LTOModule::createFromBuffer(
       unwrap(cg)->getContext(), mem, length, Options, StringRef(path));
   return wrap(M->release());
@@ -357,7 +356,7 @@ void lto_codegen_set_diagnostic_handler(lto_code_gen_t cg,
 static lto_code_gen_t createCodeGen(bool InLocalContext) {
   lto_initialize();
 
-  TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
 
   LibLTOCodeGenerator *CodeGen =
       InLocalContext ? new LibLTOCodeGenerator(std::make_unique<LLVMContext>())
@@ -505,7 +504,7 @@ void lto_codegen_set_should_embed_uselists(lto_code_gen_t cg,
 thinlto_code_gen_t thinlto_create_codegen(void) {
   lto_initialize();
   ThinLTOCodeGenerator *CodeGen = new ThinLTOCodeGenerator();
-  CodeGen->setTargetOptions(InitTargetOptionsFromCodeGenFlags());
+  CodeGen->setTargetOptions(codegen::InitTargetOptionsFromCodeGenFlags());
   CodeGen->setFreestanding(EnableFreestanding);
 
   if (OptLevel.getNumOccurrences()) {
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index 91522c170e49b..8a4726053aa92 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -22,7 +22,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriterPass.h"
-#include "llvm/CodeGen/CommandFlags.inc"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/IR/DataLayout.h"
@@ -62,6 +62,8 @@
 using namespace llvm;
 using namespace opt_tool;
 
+static codegen::RegisterCodeGenFlags CFG;
+
 // The OptimizationList is automatically populated with registered Passes by the
 // PassNameParser.
 //
@@ -485,16 +487,17 @@ static TargetMachine* GetTargetMachine(Triple TheTriple, StringRef CPUStr,
                                        StringRef FeaturesStr,
                                        const TargetOptions &Options) {
   std::string Error;
-  const Target *TheTarget = TargetRegistry::lookupTarget(MArch, TheTriple,
-                                                         Error);
+  const Target *TheTarget =
+      TargetRegistry::lookupTarget(codegen::getMArch(), TheTriple, Error);
   // Some modules don't specify a triple, and this is okay.
   if (!TheTarget) {
     return nullptr;
   }
 
-  return TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr,
-                                        FeaturesStr, Options, getRelocModel(),
-                                        getCodeModel(), GetCodeGenOptLevel());
+  return TheTarget->createTargetMachine(
+      TheTriple.getTriple(), codegen::getCPUStr(), codegen::getFeaturesStr(),
+      Options, codegen::getExplicitRelocModel(),
+      codegen::getExplicitCodeModel(), GetCodeGenOptLevel());
 }
 
 #ifdef BUILD_EXAMPLES
@@ -702,11 +705,11 @@ int main(int argc, char **argv) {
   Triple ModuleTriple(M->getTargetTriple());
   std::string CPUStr, FeaturesStr;
   TargetMachine *Machine = nullptr;
-  const TargetOptions Options = InitTargetOptionsFromCodeGenFlags();
+  const TargetOptions Options = codegen::InitTargetOptionsFromCodeGenFlags();
 
   if (ModuleTriple.getArch()) {
-    CPUStr = getCPUStr();
-    FeaturesStr = getFeaturesStr();
+    CPUStr = codegen::getCPUStr();
+    FeaturesStr = codegen::getFeaturesStr();
     Machine = GetTargetMachine(ModuleTriple, CPUStr, FeaturesStr, Options);
   } else if (ModuleTriple.getArchName() != "unknown" &&
              ModuleTriple.getArchName() != "") {
@@ -719,7 +722,7 @@ int main(int argc, char **argv) {
 
   // Override function attributes based on CPUStr, FeaturesStr, and command line
   // flags.
-  setFunctionAttributes(CPUStr, FeaturesStr, *M);
+  codegen::setFunctionAttributes(CPUStr, FeaturesStr, *M);
 
   // If the output is set to be emitted to standard out, and standard out is a
   // console, print out a warning message and refuse to do it.  We don't
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index d359ab203a78c..9407a9437bcc9 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -2341,4 +2341,179 @@ TEST_F(GISelMITest, NarrowScalarExtract) {
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
+
+TEST_F(GISelMITest, LowerInsert) {
+  setUp();
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(A, { getActionDefinitionsBuilder(G_INSERT).lower(); });
+
+  LLT S32{LLT::scalar(32)};
+  LLT S64{LLT::scalar(64)};
+  LLT P0{LLT::pointer(0, 64)};
+  LLT P1{LLT::pointer(1, 32)};
+  LLT V2S32{LLT::vector(2, 32)};
+
+  auto TruncS32 = B.buildTrunc(S32, Copies[0]);
+  auto IntToPtrP0 = B.buildIntToPtr(P0, Copies[0]);
+  auto IntToPtrP1 = B.buildIntToPtr(P1, TruncS32);
+  auto BitcastV2S32 = B.buildBitcast(V2S32, Copies[0]);
+
+  auto InsertS64S32 = B.buildInsert(S64, Copies[0], TruncS32, 0);
+  auto InsertS64P1 = B.buildInsert(S64, Copies[0], IntToPtrP1, 8);
+  auto InsertP0S32 = B.buildInsert(P0, IntToPtrP0, TruncS32, 16);
+  auto InsertP0P1 = B.buildInsert(P0, IntToPtrP0, IntToPtrP1, 4);
+  auto InsertV2S32S32 = B.buildInsert(V2S32, BitcastV2S32, TruncS32, 32);
+  auto InsertV2S32P1 = B.buildInsert(V2S32, BitcastV2S32, IntToPtrP1, 0);
+
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*InsertS64S32, 0, LLT{}));
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*InsertS64P1, 0, LLT{}));
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*InsertP0S32, 0, LLT{}));
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*InsertP0P1, 0, LLT{}));
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*InsertV2S32S32, 0, LLT{}));
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
+            Helper.lower(*InsertV2S32P1, 0, LLT{}));
+
+  const auto *CheckStr = R"(
+  CHECK: [[S64:%[0-9]+]]:_(s64) = COPY
+  CHECK: [[S32:%[0-9]+]]:_(s32) = G_TRUNC [[S64]]
+  CHECK: [[P0:%[0-9]+]]:_(p0) = G_INTTOPTR [[S64]]
+  CHECK: [[P1:%[0-9]+]]:_(p1) = G_INTTOPTR [[S32]]
+  CHECK: [[V2S32:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[S64]]
+  CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[S32]]
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[S64]]:_, [[C]]:_
+  CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]]:_, [[ZEXT]]:_
+
+  CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[P1]]
+  CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[PTRTOINT]]
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]]:_, [[C]]:_(s64)
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[S64]]:_, [[C]]:_
+  CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]]:_, [[SHL]]:_
+
+  CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[P0]]
+  CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[S32]]
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]]:_, [[C]]:_(s64)
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]]:_, [[C]]:_
+  CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]]:_, [[SHL]]:_
+  CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]]
+
+  CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[P0]]
+  CHECK: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[P1]]
+  CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[PTRTOINT1]]
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]]:_, [[C]]:_(s64)
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[PTRTOINT]]:_, [[C]]:_
+  CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]]:_, [[SHL]]:_
+  CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[OR]]
+
+  CHECK: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[V2S32]]
+  CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[S32]]
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]]:_, [[C]]:_(s64)
+  CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT
+  CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[BITCAST]]:_, [[C]]:_
+  CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]]:_, [[SHL]]:_
+  CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[OR]]
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
+// Test lowering of G_FFLOOR
+TEST_F(GISelMITest, LowerFFloor) {
+  setUp();
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(A, {});
+  // Build Instr
+  auto Floor = B.buildFFloor(LLT::scalar(64), Copies[0], MachineInstr::MIFlag::FmNoInfs);
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  // Perform Legalization
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*Floor, 0, LLT()));
+
+  auto CheckStr = R"(
+  CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY
+  CHECK: [[TRUNC:%[0-9]+]]:_(s64) = ninf G_INTRINSIC_TRUNC [[COPY]]
+  CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+  CHECK: [[CMP0:%[0-9]+]]:_(s1) = ninf G_FCMP floatpred(olt), [[COPY]]:_(s64), [[ZERO]]:_
+  CHECK: [[CMP1:%[0-9]+]]:_(s1) = ninf G_FCMP floatpred(one), [[COPY]]:_(s64), [[TRUNC]]:_
+  CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[CMP0]]:_, [[CMP1]]:_
+  CHECK: [[ITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[AND]]
+  = ninf G_FADD [[TRUNC]]:_, [[ITOFP]]:_
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
+// Test lowering of G_BSWAP
+TEST_F(GISelMITest, LowerBSWAP) {
+  setUp();
+  if (!TM)
+    return;
+
+  DefineLegalizerInfo(A, {});
+
+  // Make sure vector lowering doesn't assert.
+  auto Cast = B.buildBitcast(LLT::vector(2, 32), Copies[0]);
+  auto BSwap = B.buildBSwap(LLT::vector(2, 32), Cast);
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  // Perform Legalization
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*BSwap, 0, LLT()));
+
+  auto CheckStr = R"(
+  CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY
+  CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]]
+  CHECK: [[K24:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+  CHECK: [[SPLAT24:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[K24]]:_(s32), [[K24]]:_(s32)
+  CHECK: [[SHL0:%[0-9]+]]:_(<2 x s32>) = G_SHL [[VEC]]:_, [[SPLAT24]]
+  CHECK: [[SHR0:%[0-9]+]]:_(<2 x s32>) = G_LSHR [[VEC]]:_, [[SPLAT24]]
+  CHECK: [[OR0:%[0-9]+]]:_(<2 x s32>) = G_OR [[SHR0]]:_, [[SHL0]]:_
+  CHECK: [[KMASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
+  CHECK: [[SPLATMASK:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[KMASK]]:_(s32), [[KMASK]]:_(s32)
+  CHECK: [[K8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+  CHECK: [[SPLAT8:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[K8]]:_(s32), [[K8]]:_(s32)
+  CHECK: [[AND0:%[0-9]+]]:_(<2 x s32>) = G_AND [[VEC]]:_, [[SPLATMASK]]:_
+  CHECK: [[SHL1:%[0-9]+]]:_(<2 x s32>) = G_SHL [[AND0]]:_, [[SPLAT8]]
+  CHECK: [[OR1:%[0-9]+]]:_(<2 x s32>) = G_OR [[OR0]]:_, [[SHL1]]:_
+  CHECK: [[SHR1:%[0-9]+]]:_(<2 x s32>) = G_LSHR [[VEC]]:_, [[SPLAT8]]
+  CHECK: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[SHR1]]:_, [[SPLATMASK]]:_
+  CHECK: [[BSWAP:%[0-9]+]]:_(<2 x s32>) = G_OR [[OR1]]:_, [[AND1]]:_
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
 } // namespace
diff --git a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
index 3c0b03e495a3e..23aff8de68e40 100644
--- a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
+++ b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
@@ -25,7 +25,7 @@
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCTargetOptionsCommandFlags.inc"
+#include "llvm/MC/MCTargetOptionsCommandFlags.h"
 #include "llvm/PassAnalysisSupport.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -37,6 +37,8 @@
 using namespace llvm;
 using namespace dwarf;
 
+mc::RegisterMCTargetOptionsFlags MOF;
+
 namespace {} // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
@@ -433,7 +435,7 @@ llvm::Error dwarfgen::Generator::init(Triple TheTriple, uint16_t V) {
                                        TripleName,
                                    inconvertibleErrorCode());
 
-  MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
+  MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
   MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
   if (!MAI)
     return make_error<StringError>("no asm info for target " + TripleName,
diff --git a/llvm/unittests/Support/AlignmentTest.cpp b/llvm/unittests/Support/AlignmentTest.cpp
index 07694cec6832a..58f3fb100bbdd 100644
--- a/llvm/unittests/Support/AlignmentTest.cpp
+++ b/llvm/unittests/Support/AlignmentTest.cpp
@@ -125,6 +125,13 @@ TEST(AlignmentTest, AlignTo) {
   }
 }
 
+TEST(AlignmentTest, AlignToWithSkew) {
+  EXPECT_EQ(alignTo(5, Align(8), 0), alignTo(5, Align(8)));
+  EXPECT_EQ(alignTo(5, Align(8), 7), 7U);
+  EXPECT_EQ(alignTo(17, Align(8), 1), 17U);
+  EXPECT_EQ(alignTo(~0LL, Align(8), 3), 3U);
+}
+
 TEST(AlignmentTest, Log2) {
   for (uint64_t Value : getValidAlignments()) {
     EXPECT_EQ(Log2(Align(Value)), Log2_64(Value));
diff --git a/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
index 3a25620f744a6..debf7b9561013 100644
--- a/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
+++ b/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
@@ -10,6 +10,7 @@
 #include "../lib/Transforms/Vectorize/VPlanTransforms.h"
 #include "VPlanTestBase.h"
 #include "gtest/gtest.h"
+#include <string>
 
 namespace llvm {
 namespace {
@@ -88,6 +89,42 @@ TEST_F(VPlanHCFGTest, testBuildHCFGInnerLoop) {
   EXPECT_EQ(IndvarAdd, ICmp->getOperand(0));
   EXPECT_EQ(VecBB->getCondBit(), ICmp);
 
+  std::string FullDump;
+  raw_string_ostream(FullDump) << *Plan;
+  EXPECT_EQ(R"(digraph VPlan {
+graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
+node [shape=rect, fontname=Courier, fontsize=30]
+edge [fontname=Courier, fontsize=30]
+compound=true
+  subgraph cluster_N0 {
+    fontname=Courier
+    label="\<x1\> TopRegion"
+    N1 [label =
+      "entry:\n"
+    ]
+    N1 -> N2 [ label=""]
+    N2 [label =
+      "for.body:\n" +
+        "EMIT ir<%indvars.iv> = phi ir<0> ir<%indvars.iv.next>\l" +
+        "EMIT ir<%arr.idx> = getelementptr ir<%A> ir<%indvars.iv>\l" +
+        "EMIT ir<%l1> = load ir<%arr.idx>\l" +
+        "EMIT ir<%res> = add ir<%l1> ir<10>\l" +
+        "EMIT store ir<%res> ir<%arr.idx>\l" +
+        "EMIT ir<%indvars.iv.next> = add ir<%indvars.iv> ir<1>\l" +
+        "EMIT ir<%exitcond> = icmp ir<%indvars.iv.next> ir<%N>\l" +
+         "CondBit: ir<%exitcond> (for.body)\l"
+    ]
+    N2 -> N2 [ label="T"]
+    N2 -> N3 [ label="F"]
+    N3 [label =
+      "for.end:\n" +
+        "EMIT ret\l"
+    ]
+  }
+}
+)",
+            FullDump);
+
   LoopVectorizationLegality::InductionList Inductions;
   SmallPtrSet<Instruction *, 1> DeadInstructions;
   VPlanTransforms::VPInstructionsToVPRecipes(LI->getLoopFor(LoopHeader), Plan,
diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
index 61df1f6288ceb..ce0e0017fa85e 100644
--- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
@@ -178,17 +178,17 @@ TEST(VPBasicBlockTest, getPlan) {
 }
 
 TEST(VPBasicBlockTest, print) {
-  VPInstruction *I1 = new VPInstruction(10, {});
-  VPInstruction *I2 = new VPInstruction(1, {I1});
-  VPInstruction *I3 = new VPInstruction(2, {I1, I2});
+  VPInstruction *I1 = new VPInstruction(Instruction::Add, {});
+  VPInstruction *I2 = new VPInstruction(Instruction::Sub, {I1});
+  VPInstruction *I3 = new VPInstruction(Instruction::Br, {I1, I2});
 
   VPBasicBlock *VPBB1 = new VPBasicBlock();
   VPBB1->appendRecipe(I1);
   VPBB1->appendRecipe(I2);
   VPBB1->appendRecipe(I3);
 
-  VPInstruction *I4 = new VPInstruction(4, {I3, I2});
-  VPInstruction *I5 = new VPInstruction(5, {I1});
+  VPInstruction *I4 = new VPInstruction(Instruction::Mul, {I2, I1});
+  VPInstruction *I5 = new VPInstruction(Instruction::Ret, {I4});
   VPBasicBlock *VPBB2 = new VPBasicBlock();
   VPBB2->appendRecipe(I4);
   VPBB2->appendRecipe(I5);
@@ -201,7 +201,7 @@ TEST(VPBasicBlockTest, print) {
     raw_string_ostream OS(I3Dump);
     I3->print(OS);
     OS.flush();
-    EXPECT_EQ("<badref> = br <badref> <badref>", I3Dump);
+    EXPECT_EQ("br <badref> <badref>", I3Dump);
   }
 
   VPlan Plan;
@@ -216,15 +216,15 @@ edge [fontname=Courier, fontsize=30]
 compound=true
   N0 [label =
     ":\n" +
-      "EMIT %vp0 = catchswitch\l" +
-      "EMIT %vp1 = ret %vp0\l" +
-      "EMIT %vp2 = br %vp0 %vp1\l"
+      "EMIT vp<%0> = add\l" +
+      "EMIT vp<%1> = sub vp<%0>\l" +
+      "EMIT br vp<%0> vp<%1>\l"
   ]
   N0 -> N1 [ label=""]
   N1 [label =
     ":\n" +
-      "EMIT %vp3 = indirectbr %vp2 %vp1\l" +
-      "EMIT %vp4 = invoke %vp0\l"
+      "EMIT vp<%2> = mul vp<%1> vp<%0>\l" +
+      "EMIT ret vp<%2>\l"
   ]
 }
 )",
@@ -235,15 +235,15 @@ compound=true
     raw_string_ostream OS(I3Dump);
     I3->print(OS);
     OS.flush();
-    EXPECT_EQ("%vp2 = br %vp0 %vp1", I3Dump);
+    EXPECT_EQ("br vp<%0> vp<%1>", I3Dump);
   }
 
   {
-    std::string I2Dump;
-    raw_string_ostream OS(I2Dump);
-    OS << *I2;
+    std::string I4Dump;
+    raw_string_ostream OS(I4Dump);
+    OS << *I4;
     OS.flush();
-    EXPECT_EQ("%vp1 = ret %vp0", I2Dump);
+    EXPECT_EQ("vp<%2> = mul vp<%1> vp<%0>", I4Dump);
   }
 }
 
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index bebee0d685d73..4584bc7cfae32 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -1275,8 +1275,8 @@ CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
   return &RegClasses.back();
 }
 
-CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
-  if (CodeGenRegisterClass *RC = Def2RC[Def])
+CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
+  if (CodeGenRegisterClass *RC = Def2RC.lookup(Def))
     return RC;
 
   PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index f15138b04b012..2b200adef3124 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -719,7 +719,7 @@ namespace llvm {
     }
 
     // Find a register class from its def.
-    CodeGenRegisterClass *getRegClass(Record*);
+    CodeGenRegisterClass *getRegClass(const Record *) const;
 
     /// getRegisterClassForRegister - Find the register class that contains the
     /// specified physical register.  If the register is not in a register
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 7f6b3931d3dea..5d0751d144516 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -19,6 +19,7 @@
 
 #include "CodeGenHwModes.h"
 #include "CodeGenRegisters.h"
+#include "CodeGenTarget.h"
 
 #define DEBUG_TYPE "register-bank-emitter"
 
@@ -36,12 +37,12 @@ class RegisterBank {
   /// The register classes that are covered by the register bank.
   RegisterClassesTy RCs;
 
-  /// The register class with the largest register size.
-  const CodeGenRegisterClass *RCWithLargestRegsSize;
+  /// The register classes with the largest register size for each HwMode.
+  std::vector<const CodeGenRegisterClass *> RCsWithLargestRegSize;
 
 public:
-  RegisterBank(const Record &TheDef)
-      : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
+  RegisterBank(const Record &TheDef, unsigned NumModeIds)
+      : TheDef(TheDef), RCs(), RCsWithLargestRegSize(NumModeIds) {}
 
   /// Get the human-readable name for the bank.
   StringRef getName() const { return TheDef.getValueAsString("Name"); }
@@ -53,6 +54,10 @@ class RegisterBank {
     return (TheDef.getName() + "CoverageData").str();
   }
 
+  std::string getSizesArrayName() const {
+    return (TheDef.getName() + "Sizes").str();
+  }
+
   /// Get the name of the global instance variable.
   StringRef getInstanceVarName() const { return TheDef.getName(); }
 
@@ -60,10 +65,10 @@ class RegisterBank {
 
   /// Get the register classes listed in the RegisterBank.RegisterClasses field.
   std::vector<const CodeGenRegisterClass *>
-  getExplictlySpecifiedRegisterClasses(
-      CodeGenRegBank &RegisterClassHierarchy) const {
+  getExplicitlySpecifiedRegisterClasses(
+      const CodeGenRegBank &RegisterClassHierarchy) const {
     std::vector<const CodeGenRegisterClass *> RCs;
-    for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
+    for (const auto *RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
       RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
     return RCs;
   }
@@ -82,18 +87,20 @@ class RegisterBank {
     //        register size anywhere (we could sum the sizes of the subregisters
     //        but there may be additional bits too) and we can't derive it from
     //        the VT's reliably due to Untyped.
-    if (RCWithLargestRegsSize == nullptr)
-      RCWithLargestRegsSize = RC;
-    else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize <
-             RC->RSI.get(DefaultMode).SpillSize)
-      RCWithLargestRegsSize = RC;
-    assert(RCWithLargestRegsSize && "RC was nullptr?");
-
+    unsigned NumModeIds = RCsWithLargestRegSize.size();
+    for (unsigned M = 0; M < NumModeIds; ++M) {
+      if (RCsWithLargestRegSize[M] == nullptr)
+        RCsWithLargestRegSize[M] = RC;
+      else if (RCsWithLargestRegSize[M]->RSI.get(M).SpillSize <
+              RC->RSI.get(M).SpillSize)
+        RCsWithLargestRegSize[M] = RC;
+      assert(RCsWithLargestRegSize[M] && "RC was nullptr?");
+    }
     RCs.emplace_back(RC);
   }
 
-  const CodeGenRegisterClass *getRCWithLargestRegsSize() const {
-    return RCWithLargestRegsSize;
+  const CodeGenRegisterClass *getRCWithLargestRegsSize(unsigned HwMode) const {
+    return RCsWithLargestRegSize[HwMode];
   }
 
   iterator_range<typename RegisterClassesTy::const_iterator>
@@ -104,8 +111,8 @@ class RegisterBank {
 
 class RegisterBankEmitter {
 private:
+  CodeGenTarget Target;
   RecordKeeper &Records;
-  CodeGenRegBank RegisterClassHierarchy;
 
   void emitHeader(raw_ostream &OS, const StringRef TargetName,
                   const std::vector<RegisterBank> &Banks);
@@ -115,8 +122,7 @@ class RegisterBankEmitter {
                                    std::vector<RegisterBank> &Banks);
 
 public:
-  RegisterBankEmitter(RecordKeeper &R)
-      : Records(R), RegisterClassHierarchy(Records, CodeGenHwModes(R)) {}
+  RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
 
   void run(raw_ostream &OS);
 };
@@ -147,7 +153,7 @@ void RegisterBankEmitter::emitBaseClassDefinition(
   OS << "private:\n"
      << "  static RegisterBank *RegBanks[];\n\n"
      << "protected:\n"
-     << "  " << TargetName << "GenRegisterBankInfo();\n"
+     << "  " << TargetName << "GenRegisterBankInfo(unsigned HwMode = 0);\n"
      << "\n";
 }
 
@@ -167,8 +173,8 @@ void RegisterBankEmitter::emitBaseClassDefinition(
 ///                multiple times for a given class if there are multiple paths
 ///                to the class.
 static void visitRegisterBankClasses(
-    CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
-    const Twine Kind,
+    const CodeGenRegBank &RegisterClassHierarchy,
+    const CodeGenRegisterClass *RC, const Twine Kind,
     std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
     SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
 
@@ -212,6 +218,8 @@ static void visitRegisterBankClasses(
 void RegisterBankEmitter::emitBaseClassImplementation(
     raw_ostream &OS, StringRef TargetName,
     std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+  const CodeGenHwModes &CGH = Target.getHwModes();
 
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n";
@@ -239,14 +247,30 @@ void RegisterBankEmitter::emitBaseClassImplementation(
   }
   OS << "\n";
 
+  unsigned NumModeIds = CGH.getNumModeIds();
+  for (const auto &Bank : Banks) {
+    OS << "const unsigned " << Bank.getSizesArrayName() << "[] = {\n";
+    for (unsigned M = 0; M < NumModeIds; ++M) {
+      const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(M);
+      unsigned Size = RC.RSI.get(M).SpillSize;
+      OS << "    // Mode = " << M << " (";
+      if (M == 0)
+        OS << "Default";
+      else
+        OS << CGH.getMode(M).Name;
+      OS << ")\n";
+      OS << "    " << Size << ",\n";
+    }
+    OS << "};\n";
+  }
+  OS << "\n";
+
   for (const auto &Bank : Banks) {
     std::string QualifiedBankID =
         (TargetName + "::" + Bank.getEnumeratorName()).str();
-    const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize();
-    unsigned Size = RC.RSI.get(DefaultMode).SpillSize;
     OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
        << QualifiedBankID << ", /* Name */ \"" << Bank.getName()
-       << "\", /* Size */ " << Size << ", "
+       << "\", /* Sizes */ " << Bank.getInstanceVarName() << "Sizes, "
        << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
        << ", /* NumRegClasses */ "
        << RegisterClassHierarchy.getRegClasses().size() << ");\n";
@@ -261,9 +285,9 @@ void RegisterBankEmitter::emitBaseClassImplementation(
   OS << "};\n\n";
 
   OS << TargetName << "GenRegisterBankInfo::" << TargetName
-     << "GenRegisterBankInfo()\n"
+     << "GenRegisterBankInfo(unsigned HwMode)\n"
      << "    : RegisterBankInfo(RegBanks, " << TargetName
-     << "::NumRegisterBanks) {\n"
+     << "::NumRegisterBanks, HwMode) {\n"
      << "  // Assert that RegBank indices match their ID's\n"
      << "#ifndef NDEBUG\n"
      << "  unsigned Index = 0;\n"
@@ -275,18 +299,17 @@ void RegisterBankEmitter::emitBaseClassImplementation(
 }
 
 void RegisterBankEmitter::run(raw_ostream &OS) {
-  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
-  if (Targets.size() != 1)
-    PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
-  StringRef TargetName = Targets[0]->getName();
+  StringRef TargetName = Target.getName();
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+  const CodeGenHwModes &CGH = Target.getHwModes();
 
   std::vector<RegisterBank> Banks;
   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
     SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
-    RegisterBank Bank(*V);
+    RegisterBank Bank(*V, CGH.getNumModeIds());
 
     for (const CodeGenRegisterClass *RC :
-         Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
       visitRegisterBankClasses(
           RegisterClassHierarchy, RC, "explicit",
           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
@@ -301,14 +324,14 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
   }
 
   // Warn about ambiguous MIR caused by register bank/class name clashes.
-  for (const auto &Class : Records.getAllDerivedDefinitions("RegisterClass")) {
+  for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
     for (const auto &Bank : Banks) {
-      if (Bank.getName().lower() == Class->getName().lower()) {
+      if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {
         PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
                                              "distinct from register classes "
                                              "to avoid ambiguous MIR");
         PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
-        PrintNote(Class->getLoc(), "RegisterClass was declared here");
+        PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here");
       }
     }
   }
diff --git a/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
index 1a96d603de47e..0e556cdcbfeba 100644
--- a/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
@@ -119,6 +119,21 @@ clang_tablegen("arm_mve_builtin_aliases") {
   td_file = "arm_mve.td"
 }
 
+clang_tablegen("arm_sve_builtins") {
+  args = [ "-gen-arm-sve-builtins" ]
+  td_file = "arm_sve.td"
+}
+
+clang_tablegen("arm_sve_builtin_cg") {
+  args = [ "-gen-arm-sve-builtin-codegen" ]
+  td_file = "arm_sve.td"
+}
+
+clang_tablegen("arm_sve_typeflags") {
+  args = [ "-gen-arm-sve-typeflags" ]
+  td_file = "arm_sve.td"
+}
+
 clang_tablegen("arm_cde_builtins") {
   args = [ "-gen-arm-cde-builtin-def" ]
   td_file = "arm_cde.td"
diff --git a/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
index eb635fa453d85..4d645799dbf65 100644
--- a/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
@@ -60,6 +60,7 @@ static_library("AST") {
     "CommentParser.cpp",
     "CommentSema.cpp",
     "ComparisonCategories.cpp",
+    "ComputeDependence.cpp",
     "DataCollection.cpp",
     "Decl.cpp",
     "DeclBase.cpp",
diff --git a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
index c505a698052a8..522edfe982547 100644
--- a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
@@ -26,6 +26,8 @@ static_library("Basic") {
     "//clang/include/clang/Basic:DiagnosticGroups",
     "//clang/include/clang/Basic:arm_cde_builtins",
     "//clang/include/clang/Basic:arm_mve_builtins",
+    "//clang/include/clang/Basic:arm_sve_builtins",
+    "//clang/include/clang/Basic:arm_sve_typeflags",
     "//clang/include/clang/Basic:diags_tablegen",
     "//clang/include/clang/Basic:version",
   ]
diff --git a/llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
index f4e275b25305b..84dbfb0a5540c 100644
--- a/llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
@@ -4,6 +4,7 @@ static_library("CodeGen") {
   deps = [
     "//clang/include/clang/Basic:arm_cde_builtin_cg",
     "//clang/include/clang/Basic:arm_mve_builtin_cg",
+    "//clang/include/clang/Basic:arm_sve_builtin_cg",
     "//clang/lib/AST",
     "//clang/lib/Analysis",
     "//clang/lib/Basic",
diff --git a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
index e46a29227d192..aa1fc8fbb39b9 100644
--- a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
@@ -15,6 +15,13 @@ clang_tablegen("arm_fp16") {
   output_name = "arm_fp16.h"
 }
 
+# Generate arm_sve.h
+clang_tablegen("arm_sve") {
+  args = [ "-gen-arm-sve-header" ]
+  td_file = "//clang/include/clang/Basic/arm_sve.td"
+  output_name = "arm_sve.h"
+}
+
 # Generate arm_mve.h
 clang_tablegen("arm_mve") {
   args = [ "-gen-arm-mve-header" ]
@@ -36,9 +43,12 @@ copy("arm_headers") {
     ":arm_fp16",
     ":arm_mve",
     ":arm_neon",
+    ":arm_sve",
   ]
-  sources = get_target_outputs(":arm_neon") + get_target_outputs(":arm_fp16") +
-            get_target_outputs(":arm_mve")  + get_target_outputs(":arm_cde")
+  sources = []
+  foreach (dep, deps) {
+    sources += get_target_outputs(dep)
+  }
   outputs = [ "$clang_resource_dir/include/{{source_file_part}}" ]
 }
 
diff --git a/llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn b/llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
index c0772036abad5..a0e35cc11ef6c 100644
--- a/llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
@@ -20,6 +20,7 @@ executable("clang-tblgen") {
     "ClangTypeNodesEmitter.cpp",
     "MveEmitter.cpp",
     "NeonEmitter.cpp",
+    "SveEmitter.cpp",
     "TableGen.cpp",
   ]
 }
diff --git a/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
index 2663df98170f8..19021806f32f6 100644
--- a/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
@@ -21,6 +21,7 @@ static_library("CodeGen") {
     "AllocationOrder.cpp",
     "Analysis.cpp",
     "AtomicExpandPass.cpp",
+    "BBSectionsPrepare.cpp",
     "BasicTargetTransformInfo.cpp",
     "BranchFolding.cpp",
     "BranchRelaxation.cpp",
@@ -32,6 +33,7 @@ static_library("CodeGen") {
     "CallingConvLower.cpp",
     "CodeGen.cpp",
     "CodeGenPrepare.cpp",
+    "CommandFlags.cpp",
     "CriticalAntiDepBreaker.cpp",
     "DFAPacketizer.cpp",
     "DeadMachineInstructionElim.cpp",
@@ -136,6 +138,9 @@ static_library("CodeGen") {
     "ProcessImplicitDefs.cpp",
     "PrologEpilogInserter.cpp",
     "PseudoSourceValue.cpp",
+    "RDFGraph.cpp",
+    "RDFLiveness.cpp",
+    "RDFRegisters.cpp",
     "ReachingDefAnalysis.cpp",
     "RegAllocBase.cpp",
     "RegAllocBasic.cpp",
diff --git a/llvm/utils/gn/secondary/llvm/lib/MC/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/MC/BUILD.gn
index aa71f4963dad1..bac3549860fb8 100644
--- a/llvm/utils/gn/secondary/llvm/lib/MC/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/MC/BUILD.gn
@@ -55,6 +55,7 @@ static_library("MC") {
     "MCSymbol.cpp",
     "MCSymbolELF.cpp",
     "MCTargetOptions.cpp",
+    "MCTargetOptionsCommandFlags.cpp",
     "MCValue.cpp",
     "MCWasmObjectTargetWriter.cpp",
     "MCWasmStreamer.cpp",
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn
index 1cfee43e7005d..8703408119233 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn
@@ -89,9 +89,6 @@ static_library("LLVMHexagonCodeGen") {
     "HexagonVectorPrint.cpp",
     "RDFCopy.cpp",
     "RDFDeadCode.cpp",
-    "RDFGraph.cpp",
-    "RDFLiveness.cpp",
-    "RDFRegisters.cpp",
   ]
 }
 
diff --git a/llvm/utils/lit/lit/main.py b/llvm/utils/lit/lit/main.py
index 0f0c76bb6bfff..c530d3485ffba 100755
--- a/llvm/utils/lit/lit/main.py
+++ b/llvm/utils/lit/lit/main.py
@@ -40,7 +40,7 @@ def main(builtin_params={}):
 
     discovered_tests = lit.discovery.find_tests_for_inputs(lit_config, opts.test_paths)
     if not discovered_tests:
-        sys.stderr.write('error: did not disover any tests for provided path(s)\n')
+        sys.stderr.write('error: did not discover any tests for provided path(s)\n')
         sys.exit(2)
 
     # Command line overrides configuration for maxIndividualTestTime.
diff --git a/llvm/utils/lit/tests/selecting.py b/llvm/utils/lit/tests/selecting.py
index 9340b7db37edc..f5adb3228ea83 100644
--- a/llvm/utils/lit/tests/selecting.py
+++ b/llvm/utils/lit/tests/selecting.py
@@ -6,7 +6,7 @@
 #
 # RUN: not %{lit} %{inputs}/nonexistent                    2>&1 | FileCheck --check-prefix=CHECK-BAD-PATH %s
 # RUN: not %{lit} %{inputs}/nonexistent --allow-empty-runs 2>&1 | FileCheck --check-prefix=CHECK-BAD-PATH %s
-# CHECK-BAD-PATH: error: did not disover any tests for provided path(s)
+# CHECK-BAD-PATH: error: did not discover any tests for provided path(s)
 
 # Check that we exit with an error if we filter out all tests, but allow it with --allow-empty-runs.
 #
diff --git a/mlir/cmake/modules/CMakeLists.txt b/mlir/cmake/modules/CMakeLists.txt
index 36ae28d78faae..588de5495db64 100644
--- a/mlir/cmake/modules/CMakeLists.txt
+++ b/mlir/cmake/modules/CMakeLists.txt
@@ -1,7 +1,7 @@
 # Generate a list of CMake library targets so that other CMake projects can
 # link against them. LLVM calls its version of this file LLVMExports.cmake, but
 # the usual CMake convention seems to be ${Project}Targets.cmake.
-set(MLIR_INSTALL_PACKAGE_DIR lib${LLVM_LIBDIR_SUFFIX}/cmake/llvm)
+set(MLIR_INSTALL_PACKAGE_DIR lib${LLVM_LIBDIR_SUFFIX}/cmake/mlir)
 set(mlir_cmake_builddir "${CMAKE_BINARY_DIR}/${MLIR_INSTALL_PACKAGE_DIR}")
 
 # Keep this in sync with llvm/cmake/CMakeLists.txt!
@@ -9,23 +9,41 @@ set(LLVM_INSTALL_PACKAGE_DIR lib${LLVM_LIBDIR_SUFFIX}/cmake/llvm)
 set(llvm_cmake_builddir "${LLVM_BINARY_DIR}/${LLVM_INSTALL_PACKAGE_DIR}")
 
 get_property(MLIR_EXPORTS GLOBAL PROPERTY MLIR_EXPORTS)
-export(TARGETS ${MLIR_EXPORTS} FILE ${mlir_cmake_builddir}/MlirTargets.cmake)
+export(TARGETS ${MLIR_EXPORTS} FILE ${mlir_cmake_builddir}/MLIRTargets.cmake)
+
+get_property(MLIR_ALL_LIBS GLOBAL PROPERTY MLIR_ALL_LIBS)
+get_property(MLIR_DIALECT_LIBS GLOBAL PROPERTY MLIR_DIALECT_LIBS)
+get_property(MLIR_CONVERSION_LIBS GLOBAL PROPERTY MLIR_CONVERSION_LIBS)
 
 # Generate MlirConfig.cmake for the build tree.
 set(MLIR_CONFIG_CMAKE_DIR "${mlir_cmake_builddir}")
 set(MLIR_CONFIG_LLVM_CMAKE_DIR "${llvm_cmake_builddir}")
-set(MLIR_CONFIG_EXPORTS_FILE "${mlir_cmake_builddir}/MlirTargets.cmake")
+set(MLIR_CONFIG_EXPORTS_FILE "\${MLIR_CMAKE_DIR}/MLIRTargets.cmake")
 set(MLIR_CONFIG_INCLUDE_DIRS
   "${MLIR_SOURCE_DIR}/include"
   "${MLIR_BINARY_DIR}/include"
   )
+configure_file(
+  ${CMAKE_CURRENT_SOURCE_DIR}/MLIRConfig.cmake.in
+  ${mlir_cmake_builddir}/MLIRConfig.cmake
+  @ONLY)
 set(MLIR_CONFIG_CMAKE_DIR)
 set(MLIR_CONFIG_LLVM_CMAKE_DIR)
 set(MLIR_CONFIG_EXPORTS_FILE)
+set(MLIR_CONFIG_INCLUDE_DIRS)
+
+# For compatibility with projects that include(MLIRConfig)
+# via CMAKE_MODULE_PATH, place API modules next to it.
+# This should be removed in the future.
+file(COPY .
+  DESTINATION ${mlir_cmake_builddir}
+  FILES_MATCHING PATTERN *.cmake
+  PATTERN CMakeFiles EXCLUDE
+  )
 
-# Generate MlirConfig.cmake for the install tree.
+# Generate MLIRConfig.cmake for the install tree.
 set(MLIR_CONFIG_CODE "
-# Compute the installation prefix from this LLVMConfig.cmake file location.
+# Compute the installation prefix from this MLIRConfig.cmake file location.
 get_filename_component(MLIR_INSTALL_PREFIX \"\${CMAKE_CURRENT_LIST_FILE}\" PATH)")
 # Construct the proper number of get_filename_component(... PATH)
 # calls to compute the installation prefix.
@@ -36,24 +54,31 @@ get_filename_component(MLIR_INSTALL_PREFIX \"\${MLIR_INSTALL_PREFIX}\" PATH)")
 endforeach(p)
 set(MLIR_CONFIG_CMAKE_DIR "\${MLIR_INSTALL_PREFIX}/${MLIR_INSTALL_PACKAGE_DIR}")
 set(MLIR_CONFIG_LLVM_CMAKE_DIR "\${MLIR_INSTALL_PREFIX}/${LLVM_INSTALL_PACKAGE_DIR}")
-set(MLIR_CONFIG_EXPORTS_FILE "\${MLIR_CMAKE_DIR}/MlirTargets.cmake")
+set(MLIR_CONFIG_EXPORTS_FILE "\${MLIR_CMAKE_DIR}/MLIRTargets.cmake")
 set(MLIR_CONFIG_INCLUDE_DIRS
   "\${MLIR_INSTALL_PREFIX}/include"
   )
+configure_file(
+  ${CMAKE_CURRENT_SOURCE_DIR}/MLIRConfig.cmake.in
+  ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/MLIRConfig.cmake
+  @ONLY)
 set(MLIR_CONFIG_CODE)
 set(MLIR_CONFIG_CMAKE_DIR)
+set(MLIR_CONFIG_LLVM_CMAKE_DIR)
 set(MLIR_CONFIG_EXPORTS_FILE)
+set(MLIR_CONFIG_INCLUDE_DIRS)
 
 if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY)
   # Not TOOLCHAIN ONLY, so install the MLIR parts as well
   # Include the cmake files so other tools can use mlir-tblgen, etc.
   get_property(mlir_has_exports GLOBAL PROPERTY MLIR_HAS_EXPORTS)
   if(mlir_has_exports)
-    install(EXPORT MlirTargets DESTINATION ${MLIR_INSTALL_PACKAGE_DIR}
+    install(EXPORT MLIRTargets DESTINATION ${MLIR_INSTALL_PACKAGE_DIR}
             COMPONENT mlir-cmake-exports)
   endif()
 
-  install(FILES #${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/MlirConfig.cmake
+  install(FILES
+    ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/MLIRConfig.cmake
     ${CMAKE_CURRENT_SOURCE_DIR}/AddMLIR.cmake
     DESTINATION ${MLIR_INSTALL_PACKAGE_DIR}
     COMPONENT mlir-cmake-exports)
diff --git a/mlir/cmake/modules/MLIRConfig.cmake.in b/mlir/cmake/modules/MLIRConfig.cmake.in
new file mode 100644
index 0000000000000..190aa193d1db9
--- /dev/null
+++ b/mlir/cmake/modules/MLIRConfig.cmake.in
@@ -0,0 +1,35 @@
+# This file allows users to call find_package(MLIR) and pick up our targets.
+
+@MLIR_CONFIG_CODE@
+
+find_package(LLVM REQUIRED CONFIG
+             HINTS "@MLIR_CONFIG_LLVM_CMAKE_DIR@")
+
+set(MLIR_EXPORTED_TARGETS "@MLIR_EXPORTS@")
+set(MLIR_CMAKE_DIR "@MLIR_CONFIG_CMAKE_DIR@")
+set(MLIR_INCLUDE_DIRS "@MLIR_CONFIG_INCLUDE_DIRS@")
+set(MLIR_TABLEGEN_EXE "@MLIR_TABLEGEN_EXE@")
+
+# For mlir_tablegen()
+set(MLIR_INCLUDE_DIR "@MLIR_INCLUDE_DIR@")
+set(MLIR_MAIN_SRC_DIR "@MLIR_MAIN_SRC_DIR@")
+
+set_property(GLOBAL PROPERTY MLIR_ALL_LIBS "@MLIR_ALL_LIBS@")
+set_property(GLOBAL PROPERTY MLIR_DIALECT_LIBS "@MLIR_DIALECT_LIBS@")
+set_property(GLOBAL PROPERTY MLIR_CONVERSION_LIBS "@MLIR_CONVERSION_LIBS@")
+
+# Provide all our library targets to users.
+include("@MLIR_CONFIG_EXPORTS_FILE@")
+
+# By creating these targets here, subprojects that depend on MLIR's
+# tablegen-generated headers can always depend on these targets whether building
+# in-tree with MLIR or not.
+if(NOT TARGET mlir-tablegen-targets)
+  add_custom_target(mlir-tablegen-targets)
+endif()
+if(NOT TARGET mlir-headers)
+  add_custom_target(mlir-headers)
+endif()
+if(NOT TARGET mlir-doc)
+  add_custom_target(mlir-doc)
+endif()
diff --git a/mlir/docs/CreatingADialect.md b/mlir/docs/CreatingADialect.md
index 8c8d3a9bc0ebf..8757bf5e2a906 100644
--- a/mlir/docs/CreatingADialect.md
+++ b/mlir/docs/CreatingADialect.md
@@ -105,7 +105,7 @@ new targets with the same sources.
 # Dialect Conversions
 
 Conversions from “X” to “Y” live in mlir/include/mlir/Conversion/XToY,
-mlir/lib/Convresion/XToY and mlir/test/Conversion/XToY, respectively.
+mlir/lib/Conversion/XToY and mlir/test/Conversion/XToY, respectively.
 
 Default file names for conversion should omit “Convert” from their
 name, e.g. lib/VectorToLLVM/VectorToLLVM.cpp.
diff --git a/mlir/docs/DialectConversion.md b/mlir/docs/DialectConversion.md
index 8af0e4fb0b255..ec02b7274a461 100644
--- a/mlir/docs/DialectConversion.md
+++ b/mlir/docs/DialectConversion.md
@@ -247,7 +247,7 @@ struct MyConversionPattern : public ConversionPattern {
   /// The `matchAndRewrite` hooks on ConversionPatterns take an additional
   /// `operands` parameter, containing the remapped operands of the original
   /// operation.
-  virtual PatternMatchResult
+  virtual LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const;
 };
diff --git a/mlir/docs/Dialects/SPIR-V.md b/mlir/docs/Dialects/SPIR-V.md
index 0cb6281777503..e1e772b43a71a 100644
--- a/mlir/docs/Dialects/SPIR-V.md
+++ b/mlir/docs/Dialects/SPIR-V.md
@@ -934,7 +934,7 @@ proper hooks to check the dynamic legality of SPIR-V ops. Users can further
 register other legality constraints into the returned `SPIRVConversionTarget`.
 
 `spirv::lookupTargetEnvOrDefault()` is a handy utility function to query an
-`spv.target_env` attached in the input IR or use the feault to construct a
+`spv.target_env` attached in the input IR or use the default to construct a
 `SPIRVConversionTarget`.
 
 ### `SPIRVTypeConverter`
diff --git a/mlir/docs/Dialects/Vector.md b/mlir/docs/Dialects/Vector.md
index 1c00269c615a2..5650607950830 100644
--- a/mlir/docs/Dialects/Vector.md
+++ b/mlir/docs/Dialects/Vector.md
@@ -91,7 +91,7 @@ captured by LLVM peephole optimizations of on different types that core MLIR
 supports (e.g. Scalable Vectors) are welcome future extensions.
 
 ### Virtual Vector Ops
-Some existing Standard and VectorOps Dialect on `n-D` `vector` types comprise:
+Some existing Standard and Vector Dialect on `n-D` `vector` types comprise:
 ```
 %2 = std.addf %0, %1 : vector<3x7x8xf32>  // -> vector<3x7x8xf32>
 %2 = std.mulf %0, %1 : vector<3x7x8xf32>  // -> vector<3x7x8xf32>
@@ -112,9 +112,9 @@ vector.transfer_write %f1, %A[%i0, %i1, %i2, %i3]
     vector<5x4x3xf32>, memref<?x?x?x?xf32>
 ```
 
-The list of VectorOps is currently undergoing evolutions and is best kept
+The list of Vector is currently undergoing evolutions and is best kept
 track of by following the evolution of the
-[VectorOps.td](https://github.com/llvm/llvm-project/blob/master/mlir/include/mlir/Dialect/VectorOps/VectorOps.td)
+[VectorOps.td](https://github.com/llvm/llvm-project/blob/master/mlir/include/mlir/Dialect/Vector/VectorOps.td)
 ODS file (markdown documentation is automatically generated locally when
 building and populates the [Vector
 doc](https://github.com/llvm/llvm-project/blob/master/mlir/docs/Dialects/Vector.md)). Recent
diff --git a/mlir/docs/LangRef.md b/mlir/docs/LangRef.md
index d59e552e32c7b..a3e5738b49b51 100644
--- a/mlir/docs/LangRef.md
+++ b/mlir/docs/LangRef.md
@@ -902,7 +902,7 @@ memref<16x32xf32, #identity, memspace0>
 %T = alloc(%M, %N) [%B1, %B2] : memref<?x?xf32, #tiled_dynamic>
 
 // A memref that has a two-element padding at either end. The allocation size
-// will fit 16 * 68 float elements of data.
+// will fit 16 * 64 float elements of data.
 %P = alloc() : memref<16x64xf32, #padded>
 
 // Affine map with symbol 's0' used as offset for the first dimension.
diff --git a/mlir/docs/OpDefinitions.md b/mlir/docs/OpDefinitions.md
index 30406b7e4e834..cc8761eccb158 100644
--- a/mlir/docs/OpDefinitions.md
+++ b/mlir/docs/OpDefinitions.md
@@ -654,7 +654,7 @@ value type is buildable. In those cases, the type of the attribute is elided.
 #### Optional Groups
 
 In certain situations operations may have "optional" information, e.g.
-attributes or an empty set of variadic operands. In these situtations a section
+attributes or an empty set of variadic operands. In these situations a section
 of the assembly format can be marked as `optional` based on the presence of this
 information. An optional group is defined by wrapping a set of elements within
 `()` followed by a `?` and has the following requirements:
diff --git a/mlir/docs/QuickstartRewrites.md b/mlir/docs/QuickstartRewrites.md
index e0370e4871815..71e8f0164fc9e 100644
--- a/mlir/docs/QuickstartRewrites.md
+++ b/mlir/docs/QuickstartRewrites.md
@@ -171,8 +171,8 @@ struct ConvertTFLeakyRelu : public RewritePattern {
   ConvertTFLeakyRelu(MLIRContext *context)
       : RewritePattern("tf.LeakyRelu", 1, context) {}
 
-  PatternMatchResult match(Operation *op) const override {
-    return matchSuccess();
+  LogicalResult match(Operation *op) const override {
+    return success();
   }
 
   void rewrite(Operation *op, PatternRewriter &rewriter) const override {
@@ -188,12 +188,12 @@ struct ConvertTFLeakyRelu : public RewritePattern {
   ConvertTFLeakyRelu(MLIRContext *context)
       : RewritePattern("tf.LeakyRelu", 1, context) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
+  LogicalResult matchAndRewrite(Operation *op,
                                      PatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<TFL::LeakyReluOp>(
         op, op->getResult(0).getType(), op->getOperand(0),
         /*alpha=*/op->getAttrOfType<FloatAttr>("alpha"));
-    return matchSuccess();
+    return success();
   }
 };
 ```
diff --git a/mlir/docs/RationaleLinalgDialect.md b/mlir/docs/RationaleLinalgDialect.md
index 2c07502a9fb30..0085e1ff7a09d 100644
--- a/mlir/docs/RationaleLinalgDialect.md
+++ b/mlir/docs/RationaleLinalgDialect.md
@@ -288,7 +288,7 @@ promotion to deeper levels of the memory hierarchy.
 Tensor Comprehensions showed that, fixing a few predefined strategies
 with parametric transformations and tuning knobs, can already provide
 great results. In that previous work, simple
-genetic search combined with an autotining framework was sufficient
+genetic search combined with an autotuning framework was sufficient
 to find good implementations in the ***non-compute bound regime***.
 This requires code versions obtainable by the
 various transformations to encompass versions that get close to the
@@ -309,7 +309,7 @@ problems than could be solved with a small tactical investment.
 - Tensor Comprehensions emitted CUDA code which was then JIT compiled
 with NVCC from a textual representation. While this was a pragmatic
 short-term solution it made it hard to perform low-level rewrites that
-would have helped with register reuse in the ***comput-bound regime***.
+would have helped with register reuse in the ***compute-bound regime***.
 - The same reliance on emitting CUDA code made it difficult to
 create cost models when time came. This made it artifically harder to
 prune out bad solutions than necessary. This resulted in excessive
diff --git a/mlir/docs/Tutorials/Toy/Ch-3.md b/mlir/docs/Tutorials/Toy/Ch-3.md
index 9d59117612631..f8c8357442c84 100644
--- a/mlir/docs/Tutorials/Toy/Ch-3.md
+++ b/mlir/docs/Tutorials/Toy/Ch-3.md
@@ -86,7 +86,7 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
   /// This method is attempting to match a pattern and rewrite it. The rewriter
   /// argument is the orchestrator of the sequence of rewrites. It is expected
   /// to interact with it to perform any changes to the IR from here.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(TransposeOp op,
                   mlir::PatternRewriter &rewriter) const override {
     // Look through the input of the current transpose.
@@ -96,11 +96,11 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
 
     // Input defined by another transpose? If not, no match.
     if (!transposeInputOp)
-      return matchFailure();
+      return failure();
 
     // Otherwise, we have a redundant transpose. Use the rewriter.
     rewriter.replaceOp(op, {transposeInputOp.getOperand()}, {transposeInputOp});
-    return matchSuccess();
+    return success();
   }
 };
 ```
diff --git a/mlir/docs/Tutorials/Toy/Ch-5.md b/mlir/docs/Tutorials/Toy/Ch-5.md
index 57a7baf48c973..dbc545c492067 100644
--- a/mlir/docs/Tutorials/Toy/Ch-5.md
+++ b/mlir/docs/Tutorials/Toy/Ch-5.md
@@ -106,7 +106,7 @@ struct TransposeOpLowering : public mlir::ConversionPattern {
 
   /// Match and rewrite the given `toy.transpose` operation, with the given
   /// operands that have been remapped from `tensor<...>` to `memref<...>`.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(mlir::Operation *op, ArrayRef<mlir::Value> operands,
                   mlir::ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -132,7 +132,7 @@ struct TransposeOpLowering : public mlir::ConversionPattern {
           SmallVector<mlir::Value, 2> reverseIvs(llvm::reverse(loopIvs));
           return rewriter.create<mlir::AffineLoadOp>(loc, input, reverseIvs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 ```
diff --git a/mlir/examples/toy/Ch3/mlir/ToyCombine.cpp b/mlir/examples/toy/Ch3/mlir/ToyCombine.cpp
index da1c36311765f..8529ea0f24eea 100644
--- a/mlir/examples/toy/Ch3/mlir/ToyCombine.cpp
+++ b/mlir/examples/toy/Ch3/mlir/ToyCombine.cpp
@@ -35,7 +35,7 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
   /// This method attempts to match a pattern and rewrite it. The rewriter
   /// argument is the orchestrator of the sequence of rewrites. The pattern is
   /// expected to interact with it to perform any changes to the IR from here.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(TransposeOp op,
                   mlir::PatternRewriter &rewriter) const override {
     // Look through the input of the current transpose.
@@ -45,11 +45,11 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
 
     // Input defined by another transpose? If not, no match.
     if (!transposeInputOp)
-      return matchFailure();
+      return failure();
 
     // Otherwise, we have a redundant transpose. Use the rewriter.
     rewriter.replaceOp(op, {transposeInputOp.getOperand()});
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch4/mlir/ToyCombine.cpp b/mlir/examples/toy/Ch4/mlir/ToyCombine.cpp
index 82a1ee0b7e40f..0dd38b2c31a4e 100644
--- a/mlir/examples/toy/Ch4/mlir/ToyCombine.cpp
+++ b/mlir/examples/toy/Ch4/mlir/ToyCombine.cpp
@@ -40,7 +40,7 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
   /// This method attempts to match a pattern and rewrite it. The rewriter
   /// argument is the orchestrator of the sequence of rewrites. The pattern is
   /// expected to interact with it to perform any changes to the IR from here.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(TransposeOp op,
                   mlir::PatternRewriter &rewriter) const override {
     // Look through the input of the current transpose.
@@ -50,11 +50,11 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
 
     // Input defined by another transpose? If not, no match.
     if (!transposeInputOp)
-      return matchFailure();
+      return failure();
 
     // Otherwise, we have a redundant transpose. Use the rewriter.
     rewriter.replaceOp(op, {transposeInputOp.getOperand()});
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch4/toyc.cpp b/mlir/examples/toy/Ch4/toyc.cpp
index 51ff330cce677..6a89d0006239f 100644
--- a/mlir/examples/toy/Ch4/toyc.cpp
+++ b/mlir/examples/toy/Ch4/toyc.cpp
@@ -119,7 +119,6 @@ int dumpMLIR() {
 
     // Inline all functions into main and then delete them.
     pm.addPass(mlir::createInlinerPass());
-    pm.addPass(mlir::createSymbolDCEPass());
 
     // Now that there is only one function, we can infer the shapes of each of
     // the operations.
diff --git a/mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp b/mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
index 28531e600ffc5..9559402708c8e 100644
--- a/mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
+++ b/mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
@@ -103,7 +103,7 @@ struct BinaryOpLowering : public ConversionPattern {
   BinaryOpLowering(MLIRContext *ctx)
       : ConversionPattern(BinaryOp::getOperationName(), 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -126,7 +126,7 @@ struct BinaryOpLowering : public ConversionPattern {
           // Create the binary operation performed on the loaded values.
           return rewriter.create<LoweredBinaryOp>(loc, loadedLhs, loadedRhs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 using AddOpLowering = BinaryOpLowering<toy::AddOp, AddFOp>;
@@ -139,8 +139,8 @@ using MulOpLowering = BinaryOpLowering<toy::MulOp, MulFOp>;
 struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
   using OpRewritePattern<toy::ConstantOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(toy::ConstantOp op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(toy::ConstantOp op,
+                                PatternRewriter &rewriter) const final {
     DenseElementsAttr constantValue = op.value();
     Location loc = op.getLoc();
 
@@ -189,7 +189,7 @@ struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
 
     // Replace this operation with the generated alloc.
     rewriter.replaceOp(op, alloc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -200,16 +200,16 @@ struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
 struct ReturnOpLowering : public OpRewritePattern<toy::ReturnOp> {
   using OpRewritePattern<toy::ReturnOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(toy::ReturnOp op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(toy::ReturnOp op,
+                                PatternRewriter &rewriter) const final {
     // During this lowering, we expect that all function calls have been
     // inlined.
     if (op.hasOperand())
-      return matchFailure();
+      return failure();
 
     // We lower "toy.return" directly to "std.return".
     rewriter.replaceOpWithNewOp<ReturnOp>(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -221,7 +221,7 @@ struct TransposeOpLowering : public ConversionPattern {
   TransposeOpLowering(MLIRContext *ctx)
       : ConversionPattern(toy::TransposeOp::getOperationName(), 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -240,7 +240,7 @@ struct TransposeOpLowering : public ConversionPattern {
           SmallVector<Value, 2> reverseIvs(llvm::reverse(loopIvs));
           return rewriter.create<AffineLoadOp>(loc, input, reverseIvs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch5/mlir/ToyCombine.cpp b/mlir/examples/toy/Ch5/mlir/ToyCombine.cpp
index 82a1ee0b7e40f..0dd38b2c31a4e 100644
--- a/mlir/examples/toy/Ch5/mlir/ToyCombine.cpp
+++ b/mlir/examples/toy/Ch5/mlir/ToyCombine.cpp
@@ -40,7 +40,7 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
   /// This method attempts to match a pattern and rewrite it. The rewriter
   /// argument is the orchestrator of the sequence of rewrites. The pattern is
   /// expected to interact with it to perform any changes to the IR from here.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(TransposeOp op,
                   mlir::PatternRewriter &rewriter) const override {
     // Look through the input of the current transpose.
@@ -50,11 +50,11 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
 
     // Input defined by another transpose? If not, no match.
     if (!transposeInputOp)
-      return matchFailure();
+      return failure();
 
     // Otherwise, we have a redundant transpose. Use the rewriter.
     rewriter.replaceOp(op, {transposeInputOp.getOperand()});
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch5/toyc.cpp b/mlir/examples/toy/Ch5/toyc.cpp
index c9a52c606b213..4bc2af2ff899e 100644
--- a/mlir/examples/toy/Ch5/toyc.cpp
+++ b/mlir/examples/toy/Ch5/toyc.cpp
@@ -125,7 +125,6 @@ int dumpMLIR() {
   if (enableOpt || isLoweringToAffine) {
     // Inline all functions into main and then delete them.
     pm.addPass(mlir::createInlinerPass());
-    pm.addPass(mlir::createSymbolDCEPass());
 
     // Now that there is only one function, we can infer the shapes of each of
     // the operations.
diff --git a/mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp b/mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
index 28531e600ffc5..9559402708c8e 100644
--- a/mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
+++ b/mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
@@ -103,7 +103,7 @@ struct BinaryOpLowering : public ConversionPattern {
   BinaryOpLowering(MLIRContext *ctx)
       : ConversionPattern(BinaryOp::getOperationName(), 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -126,7 +126,7 @@ struct BinaryOpLowering : public ConversionPattern {
           // Create the binary operation performed on the loaded values.
           return rewriter.create<LoweredBinaryOp>(loc, loadedLhs, loadedRhs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 using AddOpLowering = BinaryOpLowering<toy::AddOp, AddFOp>;
@@ -139,8 +139,8 @@ using MulOpLowering = BinaryOpLowering<toy::MulOp, MulFOp>;
 struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
   using OpRewritePattern<toy::ConstantOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(toy::ConstantOp op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(toy::ConstantOp op,
+                                PatternRewriter &rewriter) const final {
     DenseElementsAttr constantValue = op.value();
     Location loc = op.getLoc();
 
@@ -189,7 +189,7 @@ struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
 
     // Replace this operation with the generated alloc.
     rewriter.replaceOp(op, alloc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -200,16 +200,16 @@ struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
 struct ReturnOpLowering : public OpRewritePattern<toy::ReturnOp> {
   using OpRewritePattern<toy::ReturnOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(toy::ReturnOp op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(toy::ReturnOp op,
+                                PatternRewriter &rewriter) const final {
     // During this lowering, we expect that all function calls have been
     // inlined.
     if (op.hasOperand())
-      return matchFailure();
+      return failure();
 
     // We lower "toy.return" directly to "std.return".
     rewriter.replaceOpWithNewOp<ReturnOp>(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -221,7 +221,7 @@ struct TransposeOpLowering : public ConversionPattern {
   TransposeOpLowering(MLIRContext *ctx)
       : ConversionPattern(toy::TransposeOp::getOperationName(), 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -240,7 +240,7 @@ struct TransposeOpLowering : public ConversionPattern {
           SmallVector<Value, 2> reverseIvs(llvm::reverse(loopIvs));
           return rewriter.create<AffineLoadOp>(loc, input, reverseIvs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp b/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
index 439009acd8866..5455738dff2a8 100644
--- a/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
+++ b/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
@@ -41,7 +41,7 @@ class PrintOpLowering : public ConversionPattern {
   explicit PrintOpLowering(MLIRContext *context)
       : ConversionPattern(toy::PrintOp::getOperationName(), 1, context) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto memRefType = (*op->operand_type_begin()).cast<MemRefType>();
@@ -91,7 +91,7 @@ class PrintOpLowering : public ConversionPattern {
 
     // Notify the rewriter that this operation has been removed.
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 
 private:
diff --git a/mlir/examples/toy/Ch6/mlir/ToyCombine.cpp b/mlir/examples/toy/Ch6/mlir/ToyCombine.cpp
index 82a1ee0b7e40f..0dd38b2c31a4e 100644
--- a/mlir/examples/toy/Ch6/mlir/ToyCombine.cpp
+++ b/mlir/examples/toy/Ch6/mlir/ToyCombine.cpp
@@ -40,7 +40,7 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
   /// This method attempts to match a pattern and rewrite it. The rewriter
   /// argument is the orchestrator of the sequence of rewrites. The pattern is
   /// expected to interact with it to perform any changes to the IR from here.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(TransposeOp op,
                   mlir::PatternRewriter &rewriter) const override {
     // Look through the input of the current transpose.
@@ -50,11 +50,11 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
 
     // Input defined by another transpose? If not, no match.
     if (!transposeInputOp)
-      return matchFailure();
+      return failure();
 
     // Otherwise, we have a redundant transpose. Use the rewriter.
     rewriter.replaceOp(op, {transposeInputOp.getOperand()});
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch6/toyc.cpp b/mlir/examples/toy/Ch6/toyc.cpp
index 3c54f731ff429..558141c2ca890 100644
--- a/mlir/examples/toy/Ch6/toyc.cpp
+++ b/mlir/examples/toy/Ch6/toyc.cpp
@@ -139,7 +139,6 @@ int loadAndProcessMLIR(mlir::MLIRContext &context,
   if (enableOpt || isLoweringToAffine) {
     // Inline all functions into main and then delete them.
     pm.addPass(mlir::createInlinerPass());
-    pm.addPass(mlir::createSymbolDCEPass());
 
     // Now that there is only one function, we can infer the shapes of each of
     // the operations.
diff --git a/mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp b/mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
index 28531e600ffc5..9559402708c8e 100644
--- a/mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
+++ b/mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
@@ -103,7 +103,7 @@ struct BinaryOpLowering : public ConversionPattern {
   BinaryOpLowering(MLIRContext *ctx)
       : ConversionPattern(BinaryOp::getOperationName(), 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -126,7 +126,7 @@ struct BinaryOpLowering : public ConversionPattern {
           // Create the binary operation performed on the loaded values.
           return rewriter.create<LoweredBinaryOp>(loc, loadedLhs, loadedRhs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 using AddOpLowering = BinaryOpLowering<toy::AddOp, AddFOp>;
@@ -139,8 +139,8 @@ using MulOpLowering = BinaryOpLowering<toy::MulOp, MulFOp>;
 struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
   using OpRewritePattern<toy::ConstantOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(toy::ConstantOp op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(toy::ConstantOp op,
+                                PatternRewriter &rewriter) const final {
     DenseElementsAttr constantValue = op.value();
     Location loc = op.getLoc();
 
@@ -189,7 +189,7 @@ struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
 
     // Replace this operation with the generated alloc.
     rewriter.replaceOp(op, alloc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -200,16 +200,16 @@ struct ConstantOpLowering : public OpRewritePattern<toy::ConstantOp> {
 struct ReturnOpLowering : public OpRewritePattern<toy::ReturnOp> {
   using OpRewritePattern<toy::ReturnOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(toy::ReturnOp op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(toy::ReturnOp op,
+                                PatternRewriter &rewriter) const final {
     // During this lowering, we expect that all function calls have been
     // inlined.
     if (op.hasOperand())
-      return matchFailure();
+      return failure();
 
     // We lower "toy.return" directly to "std.return".
     rewriter.replaceOpWithNewOp<ReturnOp>(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -221,7 +221,7 @@ struct TransposeOpLowering : public ConversionPattern {
   TransposeOpLowering(MLIRContext *ctx)
       : ConversionPattern(toy::TransposeOp::getOperationName(), 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     auto loc = op->getLoc();
@@ -240,7 +240,7 @@ struct TransposeOpLowering : public ConversionPattern {
           SmallVector<Value, 2> reverseIvs(llvm::reverse(loopIvs));
           return rewriter.create<AffineLoadOp>(loc, input, reverseIvs);
         });
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp b/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
index 439009acd8866..5455738dff2a8 100644
--- a/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
+++ b/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
@@ -41,7 +41,7 @@ class PrintOpLowering : public ConversionPattern {
   explicit PrintOpLowering(MLIRContext *context)
       : ConversionPattern(toy::PrintOp::getOperationName(), 1, context) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto memRefType = (*op->operand_type_begin()).cast<MemRefType>();
@@ -91,7 +91,7 @@ class PrintOpLowering : public ConversionPattern {
 
     // Notify the rewriter that this operation has been removed.
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 
 private:
diff --git a/mlir/examples/toy/Ch7/mlir/ToyCombine.cpp b/mlir/examples/toy/Ch7/mlir/ToyCombine.cpp
index 9f0795f936cde..fafc3876db27c 100644
--- a/mlir/examples/toy/Ch7/mlir/ToyCombine.cpp
+++ b/mlir/examples/toy/Ch7/mlir/ToyCombine.cpp
@@ -58,7 +58,7 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
   /// This method attempts to match a pattern and rewrite it. The rewriter
   /// argument is the orchestrator of the sequence of rewrites. The pattern is
   /// expected to interact with it to perform any changes to the IR from here.
-  mlir::PatternMatchResult
+  mlir::LogicalResult
   matchAndRewrite(TransposeOp op,
                   mlir::PatternRewriter &rewriter) const override {
     // Look through the input of the current transpose.
@@ -68,11 +68,11 @@ struct SimplifyRedundantTranspose : public mlir::OpRewritePattern<TransposeOp> {
 
     // Input defined by another transpose? If not, no match.
     if (!transposeInputOp)
-      return matchFailure();
+      return failure();
 
     // Otherwise, we have a redundant transpose. Use the rewriter.
     rewriter.replaceOp(op, {transposeInputOp.getOperand()});
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/examples/toy/Ch7/toyc.cpp b/mlir/examples/toy/Ch7/toyc.cpp
index 1f5f988caca3c..f3e12fb986cf0 100644
--- a/mlir/examples/toy/Ch7/toyc.cpp
+++ b/mlir/examples/toy/Ch7/toyc.cpp
@@ -139,7 +139,6 @@ int loadAndProcessMLIR(mlir::MLIRContext &context,
   if (enableOpt || isLoweringToAffine) {
     // Inline all functions into main and then delete them.
     pm.addPass(mlir::createInlinerPass());
-    pm.addPass(mlir::createSymbolDCEPass());
 
     // Now that there is only one function, we can infer the shapes of each of
     // the operations.
diff --git a/mlir/include/mlir/Analysis/CallGraph.h b/mlir/include/mlir/Analysis/CallGraph.h
index cd25151da4c07..b4ef04969b5af 100644
--- a/mlir/include/mlir/Analysis/CallGraph.h
+++ b/mlir/include/mlir/Analysis/CallGraph.h
@@ -192,6 +192,9 @@ class CallGraph {
   /// external node if a valid node was not resolved.
   CallGraphNode *resolveCallable(CallOpInterface call) const;
 
+  /// Erase the given node from the callgraph.
+  void eraseNode(CallGraphNode *node);
+
   /// An iterator over the nodes of the graph.
   using iterator = NodeIterator;
   iterator begin() const { return nodes.begin(); }
diff --git a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h
index 7d2a076aeb25b..dd815b381cc93 100644
--- a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h
+++ b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h
@@ -61,15 +61,6 @@ std::unique_ptr<OpPassBase<ModuleOp>>
 createLowerToLLVMPass(bool useAlloca = false, bool useBarePtrCallConv = false,
                       bool emitCWrappers = false);
 
-namespace LLVM {
-/// Make argument-taking successors of each block distinct.  PHI nodes in LLVM
-/// IR use the predecessor ID to identify which value to take.  They do not
-/// support different values coming from the same predecessor.  If a block has
-/// another block as a successor more than once with different values, insert
-/// a new dummy block for LLVM PHI nodes to tell the sources apart.
-void ensureDistinctSuccessors(ModuleOp m);
-} // namespace LLVM
-
 } // namespace mlir
 
 #endif // MLIR_CONVERSION_STANDARDTOLLVM_CONVERTSTANDARDTOLLVMPASS_H_
diff --git a/mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h b/mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
index 8c95d13a29221..a92906d0c2c3a 100644
--- a/mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
+++ b/mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
@@ -26,7 +26,7 @@ void populateVectorToLLVMConversionPatterns(LLVMTypeConverter &converter,
                                             OwningRewritePatternList &patterns);
 
 /// Create a pass to convert vector operations to the LLVMIR dialect.
-OpPassBase<ModuleOp> *createLowerVectorToLLVMPass();
+std::unique_ptr<OpPassBase<ModuleOp>> createConvertVectorToLLVMPass();
 
 } // namespace mlir
 
diff --git a/mlir/include/mlir/Dialect/CMakeLists.txt b/mlir/include/mlir/Dialect/CMakeLists.txt
index db9de7b7ea3ab..27cbe93783469 100644
--- a/mlir/include/mlir/Dialect/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/CMakeLists.txt
@@ -5,8 +5,8 @@ add_subdirectory(Linalg)
 add_subdirectory(LLVMIR)
 add_subdirectory(LoopOps)
 add_subdirectory(OpenMP)
-add_subdirectory(QuantOps)
+add_subdirectory(Quant)
 add_subdirectory(Shape)
 add_subdirectory(SPIRV)
 add_subdirectory(StandardOps)
-add_subdirectory(VectorOps)
+add_subdirectory(Vector)
diff --git a/mlir/include/mlir/Dialect/FxpMathOps/FxpMathOps.td b/mlir/include/mlir/Dialect/FxpMathOps/FxpMathOps.td
index 7e6625d04ef45..ea93f3b16f12c 100644
--- a/mlir/include/mlir/Dialect/FxpMathOps/FxpMathOps.td
+++ b/mlir/include/mlir/Dialect/FxpMathOps/FxpMathOps.td
@@ -15,7 +15,7 @@
 #define DIALECT_FXPMATHOPS_FXPMATH_OPS_
 
 include "mlir/IR/OpBase.td"
-include "mlir/Dialect/QuantOps/QuantOpsBase.td"
+include "mlir/Dialect/Quant/QuantOpsBase.td"
 include "mlir/Interfaces/SideEffects.td"
 
 def FxpMathOps_Dialect : Dialect {
diff --git a/mlir/include/mlir/Dialect/GPU/GPUOps.td b/mlir/include/mlir/Dialect/GPU/GPUOps.td
index 1ff0a8b57f5d2..659c10142e815 100644
--- a/mlir/include/mlir/Dialect/GPU/GPUOps.td
+++ b/mlir/include/mlir/Dialect/GPU/GPUOps.td
@@ -28,6 +28,8 @@ def IntLikeOrLLVMInt : TypeConstraint<
 
 def GPU_Dialect : Dialect {
   let name = "gpu";
+  let hasOperationAttrVerify = 1;
+
   let extraClassDeclaration = [{
     /// Get the name of the attribute used to annotate the modules that contain
     /// kernel modules.
@@ -57,9 +59,6 @@ def GPU_Dialect : Dialect {
     /// Returns the numeric value used to identify the private memory address
     /// space.
     static unsigned getPrivateAddressSpace() { return 5; }
-
-    LogicalResult verifyOperationAttribute(Operation *op,
-                                           NamedAttribute attr) override;
   }];
 }
 
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
index b2d1e57c0f110..20ed573ab8bda 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
@@ -19,17 +19,12 @@ include "mlir/IR/OpBase.td"
 def LLVM_Dialect : Dialect {
   let name = "llvm";
   let cppNamespace = "LLVM";
+  let hasRegionArgAttrVerify = 1;
   let extraClassDeclaration = [{
     ~LLVMDialect();
     llvm::LLVMContext &getLLVMContext();
     llvm::Module &getLLVMModule();
 
-    /// Verify a region argument attribute registered to this dialect.
-    /// Returns failure if the verification failed, success otherwise.
-    LogicalResult verifyRegionArgAttribute(Operation *op, unsigned regionIdx,
-                                           unsigned argIdx,
-                                           NamedAttribute argAttr) override;
-
   private:
     friend LLVMType;
 
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
index c702ed8d2fca5..c734526ce9430 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
@@ -862,6 +862,37 @@ def LLVM_MatrixTranposeOp
   let assemblyFormat = "$matrix attr-dict `:` type($matrix) `into` type($res)";
 }
 
+//
+// LLVM masked operations.
+//
+
+/// Create a call to Masked Load intrinsic.
+def LLVM_MaskedLoadOp
+    : LLVM_OneResultOp<"intr.masked.load">,
+      Arguments<(ins LLVM_Type:$data, LLVM_Type:$mask,
+                 Variadic<LLVM_Type>:$pass_thru, I32Attr:$alignment)> {
+  string llvmBuilder = [{
+    $res = $pass_thru.empty() ? builder.CreateMaskedLoad(
+      $data, llvm::Align($alignment.getZExtValue()), $mask) :
+      builder.CreateMaskedLoad(
+        $data, llvm::Align($alignment.getZExtValue()), $mask, $pass_thru[0]);
+  }];
+  let assemblyFormat =
+    "operands attr-dict `:` functional-type(operands, results)";
+}
+
+/// Create a call to Masked Store intrinsic.
+def LLVM_MaskedStoreOp
+    : LLVM_ZeroResultOp<"intr.masked.store">,
+      Arguments<(ins LLVM_Type:$value, LLVM_Type:$data, LLVM_Type:$mask,
+                 I32Attr:$alignment)> {
+  string llvmBuilder = [{
+    builder.CreateMaskedStore(
+      $value, $data, llvm::Align($alignment.getZExtValue()), $mask);
+  }];
+  let assemblyFormat = "$value `,` $data `,` $mask attr-dict `:` "
+    "type($value) `,` type($mask) `into` type($data)";
+}
 //
 // Atomic operations.
 //
@@ -943,4 +974,16 @@ def LLVM_AssumeOp : LLVM_Op<"intr.assume", []>,
   }];
 }
 
+def LLVM_FenceOp : LLVM_ZeroResultOp<"fence", []>,
+                   Arguments<(ins AtomicOrdering:$ordering,
+                    StrAttr:$syncscope)> {
+  let llvmBuilder = [{
+    llvm::LLVMContext &llvmContext = builder.getContext();
+    builder.CreateFence(getLLVMAtomicOrdering($ordering),
+      llvmContext.getOrInsertSyncScopeID($syncscope));
+  }];
+  let parser = [{ return parseFenceOp(parser, result); }];
+  let printer = [{ printFenceOp(p, *this); }];
+  let verifier = "return ::verify(*this);";
+}
 #endif // LLVMIR_OPS
diff --git a/mlir/include/mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h b/mlir/include/mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h
new file mode 100644
index 0000000000000..7d6ec0165d4af
--- /dev/null
+++ b/mlir/include/mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h
@@ -0,0 +1,34 @@
+//===- LegalizeForExport.h - Prepare for translation to LLVM IR -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_LLVMIR_TRANSFORMS_LEGALIZE_FOR_EXPORT_H
+#define MLIR_DIALECT_LLVMIR_TRANSFORMS_LEGALIZE_FOR_EXPORT_H
+
+#include <memory>
+
+namespace mlir {
+class Operation;
+class Pass;
+
+namespace LLVM {
+
+/// Make argument-taking successors of each block distinct.  PHI nodes in LLVM
+/// IR use the predecessor ID to identify which value to take. They do not
+/// support different values coming from the same predecessor. If a block has
+/// another block as a successor more than once with different values, insert
+/// a new dummy block for LLVM PHI nodes to tell the sources apart.
+void ensureDistinctSuccessors(Operation *op);
+
+/// Creates a pass that legalizes the LLVM dialect operations so that they can
+/// be translated to LLVM IR.
+std::unique_ptr<Pass> createLegalizeForExportPass();
+
+} // namespace LLVM
+} // namespace mlir
+
+#endif // MLIR_DIALECT_LLVMIR_TRANSFORMS_LEGALIZE_FOR_EXPORT_H
diff --git a/mlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td b/mlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td
index 6470f21a5c8ed..c080ff2066d02 100644
--- a/mlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td
+++ b/mlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td
@@ -53,7 +53,7 @@ class TileAndFuseLinalgOp<
   "if (failed(tileAndFuseLinalgOpAndSetMarker($_builder, op, {" #
   StrJoinInt<sizes>.result # "}, {" # StrJoinInt<operandIndices>.result # "}," #
       " \"" # value # "\")))" #
-  "  return matchFailure();">;
+  "  return failure();">;
 
 //===----------------------------------------------------------------------===//
 // Linalg tiling patterns.
@@ -70,22 +70,22 @@ class TileLinalgOp<list<int> sizes, string value, list<int> permutation=[]> :
     "if (failed(tileLinalgOpAndSetMarker($_builder, op, {" #
     StrJoinInt<sizes>.result # "}, \"" # value # "\", {" #
     StrJoinInt<permutation>.result # "})))" #
-    "  return matchFailure();">;
+    "  return failure();">;
 
 //===----------------------------------------------------------------------===//
 // Linalg to loop patterns.
 //===----------------------------------------------------------------------===//
 class LinalgOpToLoops<string OpType> : NativeCodeCall<
   "if (failed(linalgOpToLoops<" # OpType # ">($_builder, op))) " #
-  "  return matchFailure();">;
+  "  return failure();">;
 
 class LinalgOpToParallelLoops<string OpType> : NativeCodeCall<
   "if (failed(linalgOpToParallelLoops<" # OpType # ">($_builder, op))) " #
-  "  return matchFailure();">;
+  "  return failure();">;
 
 class LinalgOpToAffineLoops<string OpType> : NativeCodeCall<
   "if (failed(linalgOpToAffineLoops<" # OpType # ">($_builder, op))) " #
-  "  return matchFailure();">;
+  "  return failure();">;
 
 //===----------------------------------------------------------------------===//
 // Linalg to vector patterns precondition and DRR.
diff --git a/mlir/include/mlir/Dialect/QuantOps/CMakeLists.txt b/mlir/include/mlir/Dialect/Quant/CMakeLists.txt
similarity index 100%
rename from mlir/include/mlir/Dialect/QuantOps/CMakeLists.txt
rename to mlir/include/mlir/Dialect/Quant/CMakeLists.txt
diff --git a/mlir/include/mlir/Dialect/QuantOps/FakeQuantSupport.h b/mlir/include/mlir/Dialect/Quant/FakeQuantSupport.h
similarity index 94%
rename from mlir/include/mlir/Dialect/QuantOps/FakeQuantSupport.h
rename to mlir/include/mlir/Dialect/Quant/FakeQuantSupport.h
index d4d9c3987ea92..367d468b2acf1 100644
--- a/mlir/include/mlir/Dialect/QuantOps/FakeQuantSupport.h
+++ b/mlir/include/mlir/Dialect/Quant/FakeQuantSupport.h
@@ -34,10 +34,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_QUANTOPS_FAKEQUANTSUPPORT_H_
-#define MLIR_DIALECT_QUANTOPS_FAKEQUANTSUPPORT_H_
+#ifndef MLIR_DIALECT_QUANT_FAKEQUANTSUPPORT_H_
+#define MLIR_DIALECT_QUANT_FAKEQUANTSUPPORT_H_
 
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 
 namespace mlir {
 namespace quant {
@@ -64,4 +64,4 @@ fakeQuantAttrsToType(Location loc, unsigned numBits, int32_t quantizedDimension,
 } // namespace quant
 } // namespace mlir
 
-#endif // MLIR_DIALECT_QUANTOPS_FAKEQUANTSUPPORT_H_
+#endif // MLIR_DIALECT_QUANT_FAKEQUANTSUPPORT_H_
diff --git a/mlir/include/mlir/Dialect/QuantOps/Passes.h b/mlir/include/mlir/Dialect/Quant/Passes.h
similarity index 92%
rename from mlir/include/mlir/Dialect/QuantOps/Passes.h
rename to mlir/include/mlir/Dialect/Quant/Passes.h
index 6b2d6c72e6b9c..34c7c1f011a74 100644
--- a/mlir/include/mlir/Dialect/QuantOps/Passes.h
+++ b/mlir/include/mlir/Dialect/Quant/Passes.h
@@ -13,8 +13,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_QUANTOPS_PASSES_H
-#define MLIR_DIALECT_QUANTOPS_PASSES_H
+#ifndef MLIR_DIALECT_QUANT_PASSES_H
+#define MLIR_DIALECT_QUANT_PASSES_H
 
 #include <memory>
 
@@ -38,4 +38,4 @@ std::unique_ptr<OpPassBase<FuncOp>> createConvertConstPass();
 } // namespace quant
 } // namespace mlir
 
-#endif // MLIR_DIALECT_QUANTOPS_PASSES_H
+#endif // MLIR_DIALECT_QUANT_PASSES_H
diff --git a/mlir/include/mlir/Dialect/QuantOps/QuantOps.h b/mlir/include/mlir/Dialect/Quant/QuantOps.h
similarity index 76%
rename from mlir/include/mlir/Dialect/QuantOps/QuantOps.h
rename to mlir/include/mlir/Dialect/Quant/QuantOps.h
index 802be083e30a0..fba6203cf2f31 100644
--- a/mlir/include/mlir/Dialect/QuantOps/QuantOps.h
+++ b/mlir/include/mlir/Dialect/Quant/QuantOps.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_QUANTOPS_QUANTOPS_H_
-#define MLIR_DIALECT_QUANTOPS_QUANTOPS_H_
+#ifndef MLIR_DIALECT_QUANT_QUANTOPS_H_
+#define MLIR_DIALECT_QUANT_QUANTOPS_H_
 
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Builders.h"
@@ -21,12 +21,12 @@
 namespace mlir {
 namespace quant {
 
-#include "mlir/Dialect/QuantOps/QuantOpsDialect.h.inc"
+#include "mlir/Dialect/Quant/QuantOpsDialect.h.inc"
 
 #define GET_OP_CLASSES
-#include "mlir/Dialect/QuantOps/QuantOps.h.inc"
+#include "mlir/Dialect/Quant/QuantOps.h.inc"
 
 } // namespace quant
 } // namespace mlir
 
-#endif // MLIR_DIALECT_QUANTOPS_QUANTOPS_H_
+#endif // MLIR_DIALECT_QUANT_QUANTOPS_H_
diff --git a/mlir/include/mlir/Dialect/QuantOps/QuantOps.td b/mlir/include/mlir/Dialect/Quant/QuantOps.td
similarity index 88%
rename from mlir/include/mlir/Dialect/QuantOps/QuantOps.td
rename to mlir/include/mlir/Dialect/Quant/QuantOps.td
index 92e1e1d813edd..57e37534efb72 100644
--- a/mlir/include/mlir/Dialect/QuantOps/QuantOps.td
+++ b/mlir/include/mlir/Dialect/Quant/QuantOps.td
@@ -10,10 +10,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef DIALECT_QUANTOPS_QUANT_OPS_
-#define DIALECT_QUANTOPS_QUANT_OPS_
+#ifndef DIALECT_QUANT_QUANT_OPS_
+#define DIALECT_QUANT_QUANT_OPS_
 
-include "mlir/Dialect/QuantOps/QuantOpsBase.td"
+include "mlir/Dialect/Quant/QuantOpsBase.td"
 include "mlir/Interfaces/SideEffects.td"
 
 //===----------------------------------------------------------------------===//
@@ -83,6 +83,36 @@ def quant_StorageCastOp : quant_Op<"scast", [NoSideEffect]> {
   let hasFolder = 1;
 }
 
+// A QuantizeRegion (region) represents a quantization unit which wraps
+// high-precision ops with quantization specifications for all the inputs
+// and outputs. Some quantization specifications can be undetermined and
+// derived from other ports by the target specification of the kernel.
+def quant_QuantizeRegionOp : quant_Op<"region", [
+    NoSideEffect,
+    IsolatedFromAbove,
+    SingleBlockImplicitTerminator<"ReturnOp">]> {
+  let summary = [{
+    The `region operation wraps high-precision ops as a logical low-precision
+    quantized kernel.
+  }];
+
+  let arguments = (ins Variadic<AnyType>:$inputs,
+                    TypeArrayAttr:$input_specs,
+                    TypeArrayAttr:$output_specs,
+                    StrAttr:$logical_kernel);
+  let results = (outs Variadic<AnyType>:$outputs);
+  let regions = (region SizedRegion<1>:$body);
+  let verifier = [{ return verifyRegionOp(*this); }];
+}
+
+def quant_ReturnOp : quant_Op<"return", [Terminator]> {
+  let summary = [{
+    The `return` operation terminates a quantize region and returns values.
+  }];
+
+  let arguments = (ins Variadic<AnyTensor>:$results);
+}
+
 //===----------------------------------------------------------------------===//
 // Training integration and instrumentation ops
 //===----------------------------------------------------------------------===//
@@ -251,4 +281,4 @@ def quant_CoupledRefOp : quant_Op<"coupled_ref", [SameOperandsAndResultType]> {
   let results = (outs quant_RealValueType);
 }
 
-#endif // DIALECT_QUANTOPS_QUANT_OPS_
+#endif // DIALECT_QUANT_QUANT_OPS_
diff --git a/mlir/include/mlir/Dialect/QuantOps/QuantOpsBase.td b/mlir/include/mlir/Dialect/Quant/QuantOpsBase.td
similarity index 95%
rename from mlir/include/mlir/Dialect/QuantOps/QuantOpsBase.td
rename to mlir/include/mlir/Dialect/Quant/QuantOpsBase.td
index 84efcc1c8fc0f..aa7c311e20a3f 100644
--- a/mlir/include/mlir/Dialect/QuantOps/QuantOpsBase.td
+++ b/mlir/include/mlir/Dialect/Quant/QuantOpsBase.td
@@ -10,8 +10,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef DIALECT_QUANTOPS_QUANT_OPS_BASE_
-#define DIALECT_QUANTOPS_QUANT_OPS_BASE_
+#ifndef DIALECT_QUANT_QUANT_OPS_BASE_
+#define DIALECT_QUANT_QUANT_OPS_BASE_
 
 include "mlir/IR/OpBase.td"
 
@@ -68,4 +68,4 @@ def quant_UniformQuantizedType :
 def quant_UniformQuantizedValueType :
     quant_TypedPrimitiveOrContainer<quant_UniformQuantizedType>;
 
-#endif // DIALECT_QUANTOPS_QUANT_OPS_BASE_
+#endif // DIALECT_QUANT_QUANT_OPS_BASE_
diff --git a/mlir/include/mlir/Dialect/QuantOps/QuantTypes.h b/mlir/include/mlir/Dialect/Quant/QuantTypes.h
similarity index 99%
rename from mlir/include/mlir/Dialect/QuantOps/QuantTypes.h
rename to mlir/include/mlir/Dialect/Quant/QuantTypes.h
index b533198ef0781..6062da0a0d5b6 100644
--- a/mlir/include/mlir/Dialect/QuantOps/QuantTypes.h
+++ b/mlir/include/mlir/Dialect/Quant/QuantTypes.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_QUANTOPS_QUANT_TYPES_H_
-#define MLIR_DIALECT_QUANTOPS_QUANT_TYPES_H_
+#ifndef MLIR_DIALECT_QUANT_QUANT_TYPES_H_
+#define MLIR_DIALECT_QUANT_QUANT_TYPES_H_
 
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Builders.h"
@@ -399,4 +399,4 @@ class UniformQuantizedPerAxisType
 } // namespace quant
 } // namespace mlir
 
-#endif // MLIR_DIALECT_QUANTOPS_QUANT_TYPES_H_
+#endif // MLIR_DIALECT_QUANT_QUANT_TYPES_H_
diff --git a/mlir/include/mlir/Dialect/QuantOps/QuantizeUtils.h b/mlir/include/mlir/Dialect/Quant/QuantizeUtils.h
similarity index 94%
rename from mlir/include/mlir/Dialect/QuantOps/QuantizeUtils.h
rename to mlir/include/mlir/Dialect/Quant/QuantizeUtils.h
index 3847695ce692e..4f4714f3aadf4 100644
--- a/mlir/include/mlir/Dialect/QuantOps/QuantizeUtils.h
+++ b/mlir/include/mlir/Dialect/Quant/QuantizeUtils.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_QUANTOPS_QUANTIZEUTILS_H_
-#define MLIR_DIALECT_QUANTOPS_QUANTIZEUTILS_H_
+#ifndef MLIR_DIALECT_QUANT_QUANTIZEUTILS_H_
+#define MLIR_DIALECT_QUANT_QUANTIZEUTILS_H_
 
 namespace mlir {
 class Attribute;
@@ -58,4 +58,4 @@ Attribute quantizeAttrUniform(Attribute realValue,
 } // namespace quant
 } // namespace mlir
 
-#endif // MLIR_DIALECT_QUANTOPS_QUANTIZEUTILS_H_
+#endif // MLIR_DIALECT_QUANT_QUANTIZEUTILS_H_
diff --git a/mlir/include/mlir/Dialect/QuantOps/UniformSupport.h b/mlir/include/mlir/Dialect/Quant/UniformSupport.h
similarity index 97%
rename from mlir/include/mlir/Dialect/QuantOps/UniformSupport.h
rename to mlir/include/mlir/Dialect/Quant/UniformSupport.h
index 23d900b7367e2..30c4db0abc8e7 100644
--- a/mlir/include/mlir/Dialect/QuantOps/UniformSupport.h
+++ b/mlir/include/mlir/Dialect/Quant/UniformSupport.h
@@ -6,10 +6,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_QUANTOPS_UNIFORMSUPPORT_H_
-#define MLIR_DIALECT_QUANTOPS_UNIFORMSUPPORT_H_
+#ifndef MLIR_DIALECT_QUANT_UNIFORMSUPPORT_H_
+#define MLIR_DIALECT_QUANT_UNIFORMSUPPORT_H_
 
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/StandardTypes.h"
 #include "mlir/IR/Types.h"
 #include "llvm/ADT/APFloat.h"
@@ -215,4 +215,4 @@ class UniformQuantizedPerAxisValueConverter {
 } // namespace quant
 } // namespace mlir
 
-#endif // MLIR_DIALECT_QUANTOPS_UNIFORMSUPPORT_H_
+#endif // MLIR_DIALECT_QUANT_UNIFORMSUPPORT_H_
diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
index 4dc1886fae2d7..26d8f1401c32e 100644
--- a/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
@@ -47,6 +47,10 @@ def SPIRV_Dialect : Dialect {
 
   let cppNamespace = "spirv";
   let hasConstantMaterializer = 1;
+  let hasOperationAttrVerify = 1;
+  let hasRegionArgAttrVerify = 1;
+  let hasRegionResultAttrVerify = 1;
+
   let extraClassDeclaration = [{
     //===------------------------------------------------------------------===//
     // Type
@@ -65,23 +69,6 @@ def SPIRV_Dialect : Dialect {
     /// Returns the attribute name to use when specifying decorations on results
     /// of operations.
     static std::string getAttributeName(Decoration decoration);
-
-    /// Provides a hook for verifying SPIR-V dialect attributes attached to the
-    /// given op.
-    LogicalResult verifyOperationAttribute(Operation *op,
-                                           NamedAttribute attribute) override;
-
-    /// Provides a hook for verifying SPIR-V dialect attributes attached to the
-    /// given op's region argument.
-    LogicalResult verifyRegionArgAttribute(Operation *op, unsigned regionIndex,
-                                           unsigned argIndex,
-                                           NamedAttribute attribute) override;
-
-    /// Provides a hook for verifying SPIR-V dialect attributes attached to the
-    /// given op's region result.
-    LogicalResult verifyRegionResultAttribute(
-        Operation *op, unsigned regionIndex, unsigned resultIndex,
-        NamedAttribute attribute) override;
   }];
 }
 
diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td
index d5bbedb9559d2..f3af975ee52ee 100644
--- a/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file contains cast ops for the SPIR-V dialect. It corresponds
-// to "3.32.11. Convertion Instructions" of the SPIR-V specification.
+// to "3.32.11. Conversion Instructions" of the SPIR-V specification.
 //
 //===----------------------------------------------------------------------===//
 
diff --git a/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt b/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt
index 702ec621f486d..6f4d28c339c8a 100644
--- a/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt
@@ -1 +1,5 @@
-add_mlir_dialect(ShapeOps shape ShapeOps)
+set(LLVM_TARGET_DEFINITIONS ShapeOps.td)
+mlir_tablegen(ShapeOps.h.inc -gen-op-decls)
+mlir_tablegen(ShapeOps.cpp.inc -gen-op-defs)
+mlir_tablegen(ShapeOpsDialect.h.inc -gen-dialect-decls)
+add_public_tablegen_target(MLIRShapeOpsIncGen)
diff --git a/mlir/include/mlir/Dialect/Shape/IR/Shape.h b/mlir/include/mlir/Dialect/Shape/IR/Shape.h
index fe302e62e9c8a..37ea17e2bfec4 100644
--- a/mlir/include/mlir/Dialect/Shape/IR/Shape.h
+++ b/mlir/include/mlir/Dialect/Shape/IR/Shape.h
@@ -27,7 +27,8 @@ enum Kind {
   Element,
   Shape,
   Size,
-  ValueShape
+  ValueShape,
+  LAST_SHAPE_TYPE = ValueShape
 };
 } // namespace ShapeTypes
 
diff --git a/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td b/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
index 105677fd08e1b..da2b964ce6aaf 100644
--- a/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
+++ b/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
@@ -14,6 +14,7 @@
 #define SHAPE_OPS
 
 include "mlir/IR/OpBase.td"
+include "mlir/Interfaces/SideEffects.td"
 
 // TODO(jpienaar): Move to base.
 def AnyShaped: ShapedContainerType<[AnyType], IsShapedTypePred, "shaped">;
@@ -40,20 +41,24 @@ def ShapeDialect : Dialect {
   let cppNamespace = "shape";
 }
 
-def Shape_SizeType : DialectType<ShapeDialect,
-    CPred<"$_self.isa<DimType>()">, "dim"> {
+def Shape_ComponentType : DialectType<ShapeDialect,
+    CPred<"$_self.isa<::mlir::shape::ComponentType>()">, "component type"> {
   let typeDescription = [{
-    `shape.size` represents a non-negative integer with support for being
-    unknown and invalid.
+    `shape.element_type` represents the element type of the ShapedType. It may
+    be unknown, error or regular element type supported by ShapedType.
+  }];
+}
 
-    Operations on `shape.size` types are specialized to handle unknown/dynamic
-    value. So, for example, `<unknown> + x == <unknown>` for all non-error `x :
-    !shape.size` (e.g., an unknown value does not become known due to addition).
+def Shape_ElementType : DialectType<ShapeDialect,
+    CPred<"$_self.isa<::mlir::shape::ElementType>()">, "element type"> {
+  let typeDescription = [{
+    `shape.element_type` represents the element type of the ShapedType. It may
+    be unknown, error or regular element type supported by ShapedType.
   }];
 }
 
 def Shape_ShapeType : DialectType<ShapeDialect,
-    CPred<"$_self.isa<ShapeType>()">, "shape"> {
+    CPred<"$_self.isa<::mlir::shape::ShapeType>()">, "shape"> {
   let typeDescription = [{
     `shape.type` represents either an unranked shape, a ranked shape with
     possibly unknown dimensions or an invalid shape. The rank is of type
@@ -70,24 +75,20 @@ def Shape_ShapeType : DialectType<ShapeDialect,
   }];
 }
 
-def Shape_ElementType : DialectType<ShapeDialect,
-    CPred<"$_self.isa<ElementType>()">, "element type"> {
+def Shape_SizeType : DialectType<ShapeDialect,
+    CPred<"$_self.isa<::mlir::shape::SizeType>()">, "size"> {
   let typeDescription = [{
-    `shape.element_type` represents the element type of the ShapedType. It may
-    be unknown, error or regular element type supported by ShapedType.
-  }];
-}
+    `shape.size` represents a non-negative integer with support for being
+    unknown and invalid.
 
-def Shape_ComponentType : DialectType<ShapeDialect,
-    CPred<"$_self.isa<ComponentType>()">, "component type"> {
-  let typeDescription = [{
-    `shape.element_type` represents the element type of the ShapedType. It may
-    be unknown, error or regular element type supported by ShapedType.
+    Operations on `shape.size` types are specialized to handle unknown/dynamic
+    value. So, for example, `<unknown> + x == <unknown>` for all non-error `x :
+    !shape.size` (e.g., an unknown value does not become known due to addition).
   }];
 }
 
 def Shape_ValueShapeType : DialectType<ShapeDialect,
-    CPred<"$_self.isa<ValueShapeType>()">, "value shape"> {
+    CPred<"$_self.isa<::mlir::shape::ValueShapeType>()">, "value shape"> {
   let typeDescription = [{
     `shape.value_shape` represents the value produced by an operation (this
     corresponds to `Value` in the compiler) and a shape. Conceptually this is a
@@ -116,8 +117,8 @@ def Shape_AddOp : Shape_Op<"add", [SameOperandsAndResultType]> {
     * lhs + rhs = (int)lhs + (int)rhs if known;
   }];
 
-  let arguments = (ins Shape_ShapeType:$lhs, Shape_ShapeType:$rhs);
-  let results = (outs Shape_ShapeType:$result);
+  let arguments = (ins Shape_SizeType:$lhs, Shape_SizeType:$rhs);
+  let results = (outs Shape_SizeType:$result);
 }
 
 def Shape_BroadcastOp : Shape_Op<"broadcast", []> {
@@ -158,8 +159,13 @@ def Shape_ConstantOp : Shape_Op<"constant", []> {
 
   // TODO(jpienaar): Change to a more specialized attribute that would
   // encapsulate the unknown parsing while using denser packing.
-  let arguments = (ins ArrayAttr:$value);
+  let arguments = (ins AnyAttr:$value);
   let results = (outs Shape_ShapeOrSizeType:$result);
+
+  // TODO: Move this to main so that all shape ops implement these.
+  let printer = [{ return ::print(p, *this); }];
+  let verifier = [{ return ::verify(*this); }];
+  let parser = [{ return ::parse$cppClass(parser, result); }];
 }
 
 def Shape_CreateShapeOp : Shape_Op<"create_shape", []> {
@@ -214,8 +220,8 @@ def Shape_MulOp : Shape_Op<"mul", [SameOperandsAndResultType]> {
     - lhs * rhs = (int)lhs * (int)rhs if both known;
   }];
 
-  let arguments = (ins Shape_ShapeType:$lhs, Shape_ShapeType:$rhs);
-  let results = (outs Shape_ShapeType:$result);
+  let arguments = (ins Shape_SizeType:$lhs, Shape_SizeType:$rhs);
+  let results = (outs Shape_SizeType:$result);
 }
 
 def Shape_ReduceOp : Shape_Op<"reduce", []> {
@@ -244,7 +250,7 @@ def Shape_ReduceOp : Shape_Op<"reduce", []> {
         ^bb0(%index: i32, %dim: !shape.size, %lci: !shape.size):
           %acc = "shape.mul"(%lci, %dim) :
             (!shape.size, !shape.size) -> !shape.size
-          "shape.return"(%acc) : (!shape.size) -> ()
+          shape.yield %acc : !shape.size
         }) : (!shape.type, !shape.size) -> (!shape.size)
       return %1 : !shape.size
     }
@@ -266,6 +272,18 @@ def Shape_ShapeOfOp : Shape_Op<"shape_of", []> {
   let results = (outs Shape_ShapeType:$result);
 }
 
+def Shape_YieldOp : Shape_Op<"yield", [NoSideEffect, Terminator]> {
+  let summary = "Returns the value to parent op";
+
+  let arguments = (ins Variadic<AnyType>:$operands);
+
+  let builders = [OpBuilder<
+    "Builder *b, OperationState &result", [{ build(b, result, llvm::None); }]
+  >];
+
+  let assemblyFormat = "attr-dict ($operands^ `:` type($operands))?";
+}
+
 // TODO: Add Ops: if_static, if_ranked
 
 // For testing usage.
diff --git a/mlir/include/mlir/Dialect/VectorOps/CMakeLists.txt b/mlir/include/mlir/Dialect/Vector/CMakeLists.txt
similarity index 100%
rename from mlir/include/mlir/Dialect/VectorOps/CMakeLists.txt
rename to mlir/include/mlir/Dialect/Vector/CMakeLists.txt
diff --git a/mlir/include/mlir/Dialect/VectorOps/EDSC/Builders.h b/mlir/include/mlir/Dialect/Vector/EDSC/Builders.h
similarity index 97%
rename from mlir/include/mlir/Dialect/VectorOps/EDSC/Builders.h
rename to mlir/include/mlir/Dialect/Vector/EDSC/Builders.h
index ba6e6b1ebc9e3..024ae93a8f326 100644
--- a/mlir/include/mlir/Dialect/VectorOps/EDSC/Builders.h
+++ b/mlir/include/mlir/Dialect/Vector/EDSC/Builders.h
@@ -14,7 +14,7 @@
 #define MLIR_DIALECT_VECTOR_EDSC_BUILDERS_H_
 
 #include "mlir/Dialect/Utils/StructuredOpsUtils.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/EDSC/Builders.h"
 #include "mlir/EDSC/Intrinsics.h"
 #include "mlir/IR/AffineExpr.h"
diff --git a/mlir/include/mlir/Dialect/VectorOps/EDSC/Intrinsics.h b/mlir/include/mlir/Dialect/Vector/EDSC/Intrinsics.h
similarity index 69%
rename from mlir/include/mlir/Dialect/VectorOps/EDSC/Intrinsics.h
rename to mlir/include/mlir/Dialect/Vector/EDSC/Intrinsics.h
index afa830dc19c98..c307721607df7 100644
--- a/mlir/include/mlir/Dialect/VectorOps/EDSC/Intrinsics.h
+++ b/mlir/include/mlir/Dialect/Vector/EDSC/Intrinsics.h
@@ -1,14 +1,14 @@
-//===- Intrinsics.h - MLIR EDSC Intrinsics for VectorOps --------*- C++ -*-===//
+//===- Intrinsics.h - MLIR EDSC Intrinsics for Vector -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
-#ifndef MLIR_DIALECT_VECTOROPS_EDSC_INTRINSICS_H_
-#define MLIR_DIALECT_VECTOROPS_EDSC_INTRINSICS_H_
+#ifndef MLIR_DIALECT_VECTOR_EDSC_INTRINSICS_H_
+#define MLIR_DIALECT_VECTOR_EDSC_INTRINSICS_H_
 
-#include "mlir/Dialect/VectorOps/EDSC/Builders.h"
+#include "mlir/Dialect/Vector/EDSC/Builders.h"
 
 namespace mlir {
 namespace edsc {
@@ -22,4 +22,4 @@ using vector_print = OperationBuilder<vector::PrintOp>;
 } // namespace edsc
 } // namespace mlir
 
-#endif // MLIR_DIALECT_VECTOROPS_EDSC_INTRINSICS_H_
+#endif // MLIR_DIALECT_VECTOR_EDSC_INTRINSICS_H_
diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorOps.h b/mlir/include/mlir/Dialect/Vector/VectorOps.h
similarity index 79%
rename from mlir/include/mlir/Dialect/VectorOps/VectorOps.h
rename to mlir/include/mlir/Dialect/Vector/VectorOps.h
index e13d480b7a9fc..50fa0150ba537 100644
--- a/mlir/include/mlir/Dialect/VectorOps/VectorOps.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorOps.h
@@ -10,8 +10,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_VECTOROPS_VECTOROPS_H
-#define MLIR_DIALECT_VECTOROPS_VECTOROPS_H
+#ifndef MLIR_DIALECT_VECTOR_VECTOROPS_H
+#define MLIR_DIALECT_VECTOR_VECTOROPS_H
 
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Dialect.h"
@@ -24,6 +24,13 @@ class MLIRContext;
 class OwningRewritePatternList;
 namespace vector {
 
+/// Structure to control the behavior of vector transform patterns.
+struct VectorTransformsOptions {
+  /// Let vector.contract lower to vector.matrix_multiply and LLVM matrix
+  /// intrinsics.
+  bool lowerToLLVMMatrixIntrinsics = false;
+};
+
 /// Collect a set of vector-to-vector canonicalization patterns.
 void populateVectorToVectorCanonicalizationPatterns(
     OwningRewritePatternList &patterns, MLIRContext *context);
@@ -50,8 +57,9 @@ void populateVectorSlicesLoweringPatterns(OwningRewritePatternList &patterns,
 ///   OuterproductOpLowering
 /// These transformation express higher level vector ops in terms of more
 /// elementary extraction, insertion, reduction, product, and broadcast ops.
-void populateVectorContractLoweringPatterns(OwningRewritePatternList &patterns,
-                                            MLIRContext *context);
+void populateVectorContractLoweringPatterns(
+    OwningRewritePatternList &patterns, MLIRContext *context,
+    VectorTransformsOptions vectorTransformOptions = VectorTransformsOptions());
 
 /// Returns the integer type required for subscripts in the vector dialect.
 IntegerType getVectorSubscriptType(Builder &builder);
@@ -61,11 +69,11 @@ IntegerType getVectorSubscriptType(Builder &builder);
 ArrayAttr getVectorSubscriptAttr(Builder &b, ArrayRef<int64_t> values);
 
 #define GET_OP_CLASSES
-#include "mlir/Dialect/VectorOps/VectorOps.h.inc"
+#include "mlir/Dialect/Vector/VectorOps.h.inc"
 
-#include "mlir/Dialect/VectorOps/VectorOpsDialect.h.inc"
+#include "mlir/Dialect/Vector/VectorOpsDialect.h.inc"
 
 } // end namespace vector
 } // end namespace mlir
 
-#endif // MLIR_DIALECT_VECTOROPS_VECTOROPS_H
+#endif // MLIR_DIALECT_VECTOR_VECTOROPS_H
diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorOps.td b/mlir/include/mlir/Dialect/Vector/VectorOps.td
similarity index 99%
rename from mlir/include/mlir/Dialect/VectorOps/VectorOps.td
rename to mlir/include/mlir/Dialect/Vector/VectorOps.td
index 88b6e1e993e61..2a791365db4fa 100644
--- a/mlir/include/mlir/Dialect/VectorOps/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/VectorOps.td
@@ -16,7 +16,7 @@
 include "mlir/Dialect/AffineOps/AffineOpsBase.td"
 include "mlir/Interfaces/SideEffects.td"
 
-def VectorOps_Dialect : Dialect {
+def Vector_Dialect : Dialect {
   let name = "vector";
   let cppNamespace = "vector";
   let hasConstantMaterializer = 1;
@@ -24,7 +24,7 @@ def VectorOps_Dialect : Dialect {
 
 // Base class for Vector dialect ops.
 class Vector_Op<string mnemonic, list<OpTrait> traits = []> :
-    Op<VectorOps_Dialect, mnemonic, traits> {
+    Op<Vector_Dialect, mnemonic, traits> {
   // For every vector op, there needs to be a:
   //   * void print(OpAsmPrinter &p, ${C++ class of Op} op)
   //   * LogicalResult verify(${C++ class of Op} op)
@@ -433,7 +433,7 @@ def Vector_ExtractSlicesOp :
 }
 
 def Vector_FMAOp :
-  Op<VectorOps_Dialect, "fma", [NoSideEffect,
+  Op<Vector_Dialect, "fma", [NoSideEffect,
                              AllTypesMatch<["lhs", "rhs", "acc", "result"]>]>,
     Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, AnyVector:$acc)>,
     Results<(outs AnyVector:$result)> {
diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorTransformPatterns.td b/mlir/include/mlir/Dialect/Vector/VectorTransformPatterns.td
similarity index 100%
rename from mlir/include/mlir/Dialect/VectorOps/VectorTransformPatterns.td
rename to mlir/include/mlir/Dialect/Vector/VectorTransformPatterns.td
diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorTransforms.h b/mlir/include/mlir/Dialect/Vector/VectorTransforms.h
similarity index 95%
rename from mlir/include/mlir/Dialect/VectorOps/VectorTransforms.h
rename to mlir/include/mlir/Dialect/Vector/VectorTransforms.h
index 91cbad4f412bc..aa2a94cdfbb0c 100644
--- a/mlir/include/mlir/Dialect/VectorOps/VectorTransforms.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorTransforms.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef DIALECT_VECTOROPS_VECTORTRANSFORMS_H_
-#define DIALECT_VECTOROPS_VECTORTRANSFORMS_H_
+#ifndef DIALECT_VECTOR_VECTORTRANSFORMS_H_
+#define DIALECT_VECTOR_VECTORTRANSFORMS_H_
 
 #include "mlir/IR/PatternMatch.h"
 
@@ -71,4 +71,4 @@ unrollSingleResultOpMatchingType(PatternRewriter &builder, Operation *op,
 } // namespace vector
 } // namespace mlir
 
-#endif // DIALECT_VECTOROPS_VECTORTRANSFORMS_H_
+#endif // DIALECT_VECTOR_VECTORTRANSFORMS_H_
diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorUtils.h b/mlir/include/mlir/Dialect/Vector/VectorUtils.h
similarity index 97%
rename from mlir/include/mlir/Dialect/VectorOps/VectorUtils.h
rename to mlir/include/mlir/Dialect/Vector/VectorUtils.h
index 6d1942837d535..4bc03e4943fd6 100644
--- a/mlir/include/mlir/Dialect/VectorOps/VectorUtils.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorUtils.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_VECTOROPS_VECTORUTILS_H_
-#define MLIR_DIALECT_VECTOROPS_VECTORUTILS_H_
+#ifndef MLIR_DIALECT_VECTOR_VECTORUTILS_H_
+#define MLIR_DIALECT_VECTOR_VECTORUTILS_H_
 
 #include "mlir/Support/LLVM.h"
 
@@ -155,4 +155,4 @@ bool operatesOnSuperVectorsOf(Operation &op, VectorType subVectorType);
 } // end namespace matcher
 } // end namespace mlir
 
-#endif // MLIR_DIALECT_VECTOROPS_VECTORUTILS_H_
+#endif // MLIR_DIALECT_VECTOR_VECTORUTILS_H_
diff --git a/mlir/include/mlir/IR/AffineExpr.h b/mlir/include/mlir/IR/AffineExpr.h
index 21318114d4ca3..5d3e86bc9ba18 100644
--- a/mlir/include/mlir/IR/AffineExpr.h
+++ b/mlir/include/mlir/IR/AffineExpr.h
@@ -187,7 +187,7 @@ class AffineSymbolExpr : public AffineExpr {
 class AffineConstantExpr : public AffineExpr {
 public:
   using ImplType = detail::AffineConstantExprStorage;
-  /* implicit */ AffineConstantExpr(AffineExpr::ImplType *ptr);
+  /* implicit */ AffineConstantExpr(AffineExpr::ImplType *ptr = nullptr);
   int64_t getValue() const;
 };
 
diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td
index 159a3c5eae54a..d76c9d5476ef8 100644
--- a/mlir/include/mlir/IR/OpBase.td
+++ b/mlir/include/mlir/IR/OpBase.td
@@ -260,6 +260,16 @@ class Dialect {
 
   // If this dialect overrides the hook for materializing constants.
   bit hasConstantMaterializer = 0;
+
+  // If this dialect overrides the hook for verifying operation attributes.
+  bit hasOperationAttrVerify = 0;
+
+  // If this dialect overrides the hook for verifying region argument
+  // attributes.
+  bit hasRegionArgAttrVerify = 0;
+
+  // If this dialect overrides the hook for verifying region result attributes.
+  bit hasRegionResultAttrVerify = 0;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/include/mlir/IR/PatternMatch.h b/mlir/include/mlir/IR/PatternMatch.h
index aa17952b79c43..bab479bfbb618 100644
--- a/mlir/include/mlir/IR/PatternMatch.h
+++ b/mlir/include/mlir/IR/PatternMatch.h
@@ -54,23 +54,6 @@ class PatternBenefit {
   unsigned short representation;
 };
 
-/// Pattern state is used by patterns that want to maintain state between their
-/// match and rewrite phases.  Patterns can define a pattern-specific subclass
-/// of this.
-class PatternState {
-public:
-  virtual ~PatternState() {}
-
-protected:
-  // Must be subclassed.
-  PatternState() {}
-};
-
-/// This is the type returned by a pattern match.  A match failure returns a
-/// None value.  A match success returns a Some value with any state the pattern
-/// may need to maintain (but may also be null).
-using PatternMatchResult = Optional<std::unique_ptr<PatternState>>;
-
 //===----------------------------------------------------------------------===//
 // Pattern class
 //===----------------------------------------------------------------------===//
@@ -97,26 +80,11 @@ class Pattern {
   //===--------------------------------------------------------------------===//
 
   /// Attempt to match against code rooted at the specified operation,
-  /// which is the same operation code as getRootKind().  On failure, this
-  /// returns a None value.  On success it returns a (possibly null)
-  /// pattern-specific state wrapped in an Optional.
-  virtual PatternMatchResult match(Operation *op) const = 0;
+  /// which is the same operation code as getRootKind().
+  virtual LogicalResult match(Operation *op) const = 0;
 
   virtual ~Pattern() {}
 
-  //===--------------------------------------------------------------------===//
-  // Helper methods to simplify pattern implementations
-  //===--------------------------------------------------------------------===//
-
-  /// This method indicates that no match was found.
-  static PatternMatchResult matchFailure() { return None; }
-
-  /// This method indicates that a match was found and has the specified cost.
-  PatternMatchResult
-  matchSuccess(std::unique_ptr<PatternState> state = {}) const {
-    return PatternMatchResult(std::move(state));
-  }
-
 protected:
   /// Patterns must specify the root operation name they match against, and can
   /// also specify the benefit of the pattern matching.
@@ -136,19 +104,10 @@ class Pattern {
 ///       separate the concerns of matching and rewriting.
 ///   * Single-step RewritePattern with "matchAndRewrite"
 ///     - By overloading the "matchAndRewrite" function, the user can perform
-///       the rewrite in the same call as the match. This removes the need for
-///       any PatternState.
+///       the rewrite in the same call as the match.
 ///
 class RewritePattern : public Pattern {
 public:
-  /// Rewrite the IR rooted at the specified operation with the result of
-  /// this pattern, generating any new operations with the specified
-  /// rewriter.  If an unexpected error is encountered (an internal
-  /// compiler error), it is emitted through the normal MLIR diagnostic
-  /// hooks and the IR is left in a valid state.
-  virtual void rewrite(Operation *op, std::unique_ptr<PatternState> state,
-                       PatternRewriter &rewriter) const;
-
   /// Rewrite the IR rooted at the specified operation with the result of
   /// this pattern, generating any new operations with the specified
   /// builder.  If an unexpected error is encountered (an internal
@@ -157,22 +116,19 @@ class RewritePattern : public Pattern {
   virtual void rewrite(Operation *op, PatternRewriter &rewriter) const;
 
   /// Attempt to match against code rooted at the specified operation,
-  /// which is the same operation code as getRootKind().  On failure, this
-  /// returns a None value.  On success, it returns a (possibly null)
-  /// pattern-specific state wrapped in an Optional.  This state is passed back
-  /// into the rewrite function if this match is selected.
-  PatternMatchResult match(Operation *op) const override;
+  /// which is the same operation code as getRootKind().
+  LogicalResult match(Operation *op) const override;
 
   /// Attempt to match against code rooted at the specified operation,
   /// which is the same operation code as getRootKind(). If successful, this
   /// function will automatically perform the rewrite.
-  virtual PatternMatchResult matchAndRewrite(Operation *op,
-                                             PatternRewriter &rewriter) const {
-    if (auto matchResult = match(op)) {
-      rewrite(op, std::move(*matchResult), rewriter);
-      return matchSuccess();
+  virtual LogicalResult matchAndRewrite(Operation *op,
+                                        PatternRewriter &rewriter) const {
+    if (succeeded(match(op))) {
+      rewrite(op, rewriter);
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 
   /// Return a list of operations that may be generated when rewriting an
@@ -206,40 +162,32 @@ template <typename SourceOp> struct OpRewritePattern : public RewritePattern {
       : RewritePattern(SourceOp::getOperationName(), benefit, context) {}
 
   /// Wrappers around the RewritePattern methods that pass the derived op type.
-  void rewrite(Operation *op, std::unique_ptr<PatternState> state,
-               PatternRewriter &rewriter) const final {
-    rewrite(cast<SourceOp>(op), std::move(state), rewriter);
-  }
   void rewrite(Operation *op, PatternRewriter &rewriter) const final {
     rewrite(cast<SourceOp>(op), rewriter);
   }
-  PatternMatchResult match(Operation *op) const final {
+  LogicalResult match(Operation *op) const final {
     return match(cast<SourceOp>(op));
   }
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const final {
     return matchAndRewrite(cast<SourceOp>(op), rewriter);
   }
 
   /// Rewrite and Match methods that operate on the SourceOp type. These must be
   /// overridden by the derived pattern class.
-  virtual void rewrite(SourceOp op, std::unique_ptr<PatternState> state,
-                       PatternRewriter &rewriter) const {
-    rewrite(op, rewriter);
-  }
   virtual void rewrite(SourceOp op, PatternRewriter &rewriter) const {
-    llvm_unreachable("must override matchAndRewrite or a rewrite method");
+    llvm_unreachable("must override rewrite or matchAndRewrite");
   }
-  virtual PatternMatchResult match(SourceOp op) const {
+  virtual LogicalResult match(SourceOp op) const {
     llvm_unreachable("must override match or matchAndRewrite");
   }
-  virtual PatternMatchResult matchAndRewrite(SourceOp op,
-                                             PatternRewriter &rewriter) const {
-    if (auto matchResult = match(op)) {
-      rewrite(op, std::move(*matchResult), rewriter);
-      return matchSuccess();
+  virtual LogicalResult matchAndRewrite(SourceOp op,
+                                        PatternRewriter &rewriter) const {
+    if (succeeded(match(op))) {
+      rewrite(op, rewriter);
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 };
 
@@ -369,6 +317,28 @@ class PatternRewriter : public OpBuilder {
     finalizeRootUpdate(root);
   }
 
+  /// Notify the pattern rewriter that the pattern is failing to match the given
+  /// operation, and provide a callback to populate a diagnostic with the reason
+  /// why the failure occurred. This method allows for derived rewriters to
+  /// optionally hook into the reason why a pattern failed, and display it to
+  /// users.
+  template <typename CallbackT>
+  std::enable_if_t<!std::is_convertible<CallbackT, Twine>::value, LogicalResult>
+  notifyMatchFailure(Operation *op, CallbackT &&reasonCallback) {
+#ifndef NDEBUG
+    return notifyMatchFailure(op,
+                              function_ref<void(Diagnostic &)>(reasonCallback));
+#else
+    return failure();
+#endif
+  }
+  LogicalResult notifyMatchFailure(Operation *op, const Twine &msg) {
+    return notifyMatchFailure(op, [&](Diagnostic &diag) { diag << msg; });
+  }
+  LogicalResult notifyMatchFailure(Operation *op, const char *msg) {
+    return notifyMatchFailure(op, Twine(msg));
+  }
+
 protected:
   explicit PatternRewriter(MLIRContext *ctx) : OpBuilder(ctx) {}
   virtual ~PatternRewriter();
@@ -386,6 +356,17 @@ class PatternRewriter : public OpBuilder {
   /// uses.
   virtual void notifyOperationRemoved(Operation *op) {}
 
+  /// Notify the pattern rewriter that the pattern is failing to match the given
+  /// operation, and provide a callback to populate a diagnostic with the reason
+  /// why the failure occurred. This method allows for derived rewriters to
+  /// optionally hook into the reason why a pattern failed, and display it to
+  /// users.
+  virtual LogicalResult
+  notifyMatchFailure(Operation *op,
+                     function_ref<void(Diagnostic &)> reasonCallback) {
+    return failure();
+  }
+
 private:
   /// 'op' and 'newOp' are known to have the same number of results, replace the
   /// uses of op with uses of newOp.
diff --git a/mlir/include/mlir/InitAllDialects.h b/mlir/include/mlir/InitAllDialects.h
index 2d0099af23b8e..c0a7ca04081f8 100644
--- a/mlir/include/mlir/InitAllDialects.h
+++ b/mlir/include/mlir/InitAllDialects.h
@@ -23,11 +23,12 @@
 #include "mlir/Dialect/Linalg/IR/LinalgOps.h"
 #include "mlir/Dialect/LoopOps/LoopOps.h"
 #include "mlir/Dialect/OpenMP/OpenMPDialect.h"
-#include "mlir/Dialect/QuantOps/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
 #include "mlir/Dialect/SDBM/SDBMDialect.h"
 #include "mlir/Dialect/SPIRV/SPIRVDialect.h"
+#include "mlir/Dialect/Shape/IR/Shape.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/IR/Dialect.h"
 
 namespace mlir {
@@ -46,10 +47,11 @@ inline void registerAllDialects() {
     registerDialect<quant::QuantizationDialect>();
     registerDialect<spirv::SPIRVDialect>();
     registerDialect<StandardOpsDialect>();
-    registerDialect<vector::VectorOpsDialect>();
+    registerDialect<vector::VectorDialect>();
     registerDialect<NVVM::NVVMDialect>();
     registerDialect<ROCDL::ROCDLDialect>();
     registerDialect<SDBMDialect>();
+    registerDialect<shape::ShapeDialect>();
     return true;
   }();
   (void)init_once;
diff --git a/mlir/include/mlir/InitAllPasses.h b/mlir/include/mlir/InitAllPasses.h
index 009cc7309cffd..b358cfa8802ed 100644
--- a/mlir/include/mlir/InitAllPasses.h
+++ b/mlir/include/mlir/InitAllPasses.h
@@ -26,9 +26,10 @@
 #include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h"
 #include "mlir/Dialect/FxpMathOps/Passes.h"
 #include "mlir/Dialect/GPU/Passes.h"
+#include "mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h"
 #include "mlir/Dialect/Linalg/Passes.h"
 #include "mlir/Dialect/LoopOps/Passes.h"
-#include "mlir/Dialect/QuantOps/Passes.h"
+#include "mlir/Dialect/Quant/Passes.h"
 #include "mlir/Dialect/SPIRV/Passes.h"
 #include "mlir/Quantizer/Transforms/Passes.h"
 #include "mlir/Transforms/LocationSnapshot.h"
@@ -107,6 +108,9 @@ inline void registerAllPasses() {
   createConvertLinalgToAffineLoopsPass();
   createConvertLinalgToLLVMPass();
 
+  // LLVM
+  LLVM::createLegalizeForExportPass();
+
   // LoopOps
   createParallelLoopFusionPass();
   createParallelLoopSpecializationPass();
diff --git a/mlir/include/mlir/Quantizer/Support/Configuration.h b/mlir/include/mlir/Quantizer/Support/Configuration.h
index 1d70b40f6cd46..3ca5aa334a632 100644
--- a/mlir/include/mlir/Quantizer/Support/Configuration.h
+++ b/mlir/include/mlir/Quantizer/Support/Configuration.h
@@ -17,7 +17,7 @@
 
 #include <functional>
 
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/Identifier.h"
 #include "mlir/Quantizer/Support/ConstraintAnalysisGraph.h"
 #include "mlir/Quantizer/Support/Metadata.h"
diff --git a/mlir/include/mlir/Quantizer/Support/Metadata.h b/mlir/include/mlir/Quantizer/Support/Metadata.h
index 1a80ac036215d..7f16670748ec9 100644
--- a/mlir/include/mlir/Quantizer/Support/Metadata.h
+++ b/mlir/include/mlir/Quantizer/Support/Metadata.h
@@ -17,7 +17,7 @@
 
 #include <limits>
 
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/MLIRContext.h"
 #include "mlir/Quantizer/Support/Rules.h"
 #include "llvm/ADT/SmallBitVector.h"
diff --git a/mlir/include/mlir/TableGen/Dialect.h b/mlir/include/mlir/TableGen/Dialect.h
index 7cf5760b6817b..5e85806f377f4 100644
--- a/mlir/include/mlir/TableGen/Dialect.h
+++ b/mlir/include/mlir/TableGen/Dialect.h
@@ -13,6 +13,7 @@
 #define MLIR_TABLEGEN_DIALECT_H_
 
 #include "mlir/Support/LLVM.h"
+#include <string>
 
 namespace llvm {
 class Record;
@@ -48,6 +49,15 @@ class Dialect {
   // Returns if this dialect has a constant materializer or not.
   bool hasConstantMaterializer() const;
 
+  /// Returns if this dialect has an operation attribute verifier.
+  bool hasOperationAttrVerify() const;
+
+  /// Returns if this dialect has a region argument attribute verifier.
+  bool hasRegionArgAttrVerify() const;
+
+  /// Returns if this dialect has a region result attribute verifier.
+  bool hasRegionResultAttrVerify() const;
+
   // Returns whether two dialects are equal by checking the equality of the
   // underlying record.
   bool operator==(const Dialect &other) const;
diff --git a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
index d7cd0d2186aea..f6b299dbd1aec 100644
--- a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
+++ b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
@@ -15,6 +15,7 @@
 #define MLIR_TARGET_LLVMIR_MODULETRANSLATION_H
 
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h"
 #include "mlir/IR/Block.h"
 #include "mlir/IR/Module.h"
 #include "mlir/IR/Value.h"
@@ -57,6 +58,8 @@ class ModuleTranslation {
     if (!llvmModule)
       return nullptr;
 
+    LLVM::ensureDistinctSuccessors(m);
+
     T translator(m, std::move(llvmModule));
     if (failed(translator.convertGlobals()))
       return nullptr;
diff --git a/mlir/include/mlir/Transforms/DialectConversion.h b/mlir/include/mlir/Transforms/DialectConversion.h
index 48ce470b88dd5..776007347c5e7 100644
--- a/mlir/include/mlir/Transforms/DialectConversion.h
+++ b/mlir/include/mlir/Transforms/DialectConversion.h
@@ -235,18 +235,18 @@ class ConversionPattern : public RewritePattern {
   }
 
   /// Hook for derived classes to implement combined matching and rewriting.
-  virtual PatternMatchResult
+  virtual LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const {
-    if (!match(op))
-      return matchFailure();
+    if (failed(match(op)))
+      return failure();
     rewrite(op, operands, rewriter);
-    return matchSuccess();
+    return success();
   }
 
   /// Attempt to match and rewrite the IR root at the specified operation.
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const final;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const final;
 
 private:
   using RewritePattern::rewrite;
@@ -266,7 +266,7 @@ struct OpConversionPattern : public ConversionPattern {
                ConversionPatternRewriter &rewriter) const final {
     rewrite(cast<SourceOp>(op), operands, rewriter);
   }
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     return matchAndRewrite(cast<SourceOp>(op), operands, rewriter);
@@ -282,13 +282,13 @@ struct OpConversionPattern : public ConversionPattern {
     llvm_unreachable("must override matchAndRewrite or a rewrite method");
   }
 
-  virtual PatternMatchResult
+  virtual LogicalResult
   matchAndRewrite(SourceOp op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const {
-    if (!match(op))
-      return matchFailure();
+    if (failed(match(op)))
+      return failure();
     rewrite(op, operands, rewriter);
-    return matchSuccess();
+    return success();
   }
 
 private:
@@ -379,6 +379,12 @@ class ConversionPatternRewriter final : public PatternRewriter {
   /// PatternRewriter hook for updating the root operation in-place.
   void cancelRootUpdate(Operation *op) override;
 
+  /// PatternRewriter hook for notifying match failure reasons.
+  LogicalResult
+  notifyMatchFailure(Operation *op,
+                     function_ref<void(Diagnostic &)> reasonCallback) override;
+  using PatternRewriter::notifyMatchFailure;
+
   /// Return a reference to the internal implementation.
   detail::ConversionPatternRewriterImpl &getImpl();
 
diff --git a/mlir/include/mlir/Transforms/LoopUtils.h b/mlir/include/mlir/Transforms/LoopUtils.h
index 72db5e625aa2f..479b7ce81a42c 100644
--- a/mlir/include/mlir/Transforms/LoopUtils.h
+++ b/mlir/include/mlir/Transforms/LoopUtils.h
@@ -79,13 +79,14 @@ void getCleanupLoopLowerBound(AffineForOp forOp, unsigned unrollFactor,
                               AffineMap *map, SmallVectorImpl<Value> *operands,
                               OpBuilder &builder);
 
-/// Skew the operations in the body of a 'affine.for' operation with the
+/// Skew the operations in the body of an affine.for operation with the
 /// specified operation-wise shifts. The shifts are with respect to the
 /// original execution order, and are multiplied by the loop 'step' before being
-/// applied.
+/// applied. If `unrollPrologueEpilogue` is set, fully unroll the prologue and
+/// epilogue loops when possible.
 LLVM_NODISCARD
-LogicalResult instBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts,
-                           bool unrollPrologueEpilogue = false);
+LogicalResult affineForOpBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts,
+                                  bool unrollPrologueEpilogue = false);
 
 /// Tiles the specified band of perfectly nested loops creating tile-space loops
 /// and intra-tile loops. A band is a contiguous set of loops.
diff --git a/mlir/lib/Analysis/CallGraph.cpp b/mlir/lib/Analysis/CallGraph.cpp
index 1a31f13471353..e31641a87e054 100644
--- a/mlir/lib/Analysis/CallGraph.cpp
+++ b/mlir/lib/Analysis/CallGraph.cpp
@@ -143,6 +143,23 @@ CallGraphNode *CallGraph::resolveCallable(CallOpInterface call) const {
   return getExternalNode();
 }
 
+/// Erase the given node from the callgraph.
+void CallGraph::eraseNode(CallGraphNode *node) {
+  // Erase any children of this node first.
+  if (node->hasChildren()) {
+    for (const CallGraphNode::Edge &edge : llvm::make_early_inc_range(*node))
+      if (edge.isChild())
+        eraseNode(edge.getTarget());
+  }
+  // Erase any edges to this node from any other nodes.
+  for (auto &it : nodes) {
+    it.second->edges.remove_if([node](const CallGraphNode::Edge &edge) {
+      return edge.getTarget() == node;
+    });
+  }
+  nodes.erase(node->getCallableRegion());
+}
+
 //===----------------------------------------------------------------------===//
 // Printing
 
diff --git a/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp b/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
index 6c84268df8d78..9c100a280a64c 100644
--- a/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
+++ b/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
@@ -297,15 +297,15 @@ class AffineMinLowering : public OpRewritePattern<AffineMinOp> {
 public:
   using OpRewritePattern<AffineMinOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineMinOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineMinOp op,
+                                PatternRewriter &rewriter) const override {
     Value reduced =
         lowerAffineMapMin(rewriter, op.getLoc(), op.map(), op.operands());
     if (!reduced)
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOp(op, reduced);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -313,15 +313,15 @@ class AffineMaxLowering : public OpRewritePattern<AffineMaxOp> {
 public:
   using OpRewritePattern<AffineMaxOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineMaxOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineMaxOp op,
+                                PatternRewriter &rewriter) const override {
     Value reduced =
         lowerAffineMapMax(rewriter, op.getLoc(), op.map(), op.operands());
     if (!reduced)
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOp(op, reduced);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -330,10 +330,10 @@ class AffineTerminatorLowering : public OpRewritePattern<AffineTerminatorOp> {
 public:
   using OpRewritePattern<AffineTerminatorOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineTerminatorOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineTerminatorOp op,
+                                PatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<loop::YieldOp>(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -341,8 +341,8 @@ class AffineForLowering : public OpRewritePattern<AffineForOp> {
 public:
   using OpRewritePattern<AffineForOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineForOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineForOp op,
+                                PatternRewriter &rewriter) const override {
     Location loc = op.getLoc();
     Value lowerBound = lowerAffineLowerBound(op, rewriter);
     Value upperBound = lowerAffineUpperBound(op, rewriter);
@@ -351,7 +351,7 @@ class AffineForLowering : public OpRewritePattern<AffineForOp> {
     f.region().getBlocks().clear();
     rewriter.inlineRegionBefore(op.region(), f.region(), f.region().end());
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -359,8 +359,8 @@ class AffineIfLowering : public OpRewritePattern<AffineIfOp> {
 public:
   using OpRewritePattern<AffineIfOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineIfOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineIfOp op,
+                                PatternRewriter &rewriter) const override {
     auto loc = op.getLoc();
 
     // Now we just have to handle the condition logic.
@@ -381,7 +381,7 @@ class AffineIfLowering : public OpRewritePattern<AffineIfOp> {
                                          operandsRef.take_front(numDims),
                                          operandsRef.drop_front(numDims));
       if (!affResult)
-        return matchFailure();
+        return failure();
       auto pred = isEquality ? CmpIPredicate::eq : CmpIPredicate::sge;
       Value cmpVal =
           rewriter.create<CmpIOp>(loc, pred, affResult, zeroConstant);
@@ -402,7 +402,7 @@ class AffineIfLowering : public OpRewritePattern<AffineIfOp> {
 
     // Ok, we're done!
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -412,15 +412,15 @@ class AffineApplyLowering : public OpRewritePattern<AffineApplyOp> {
 public:
   using OpRewritePattern<AffineApplyOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineApplyOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineApplyOp op,
+                                PatternRewriter &rewriter) const override {
     auto maybeExpandedMap =
         expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(),
                         llvm::to_vector<8>(op.getOperands()));
     if (!maybeExpandedMap)
-      return matchFailure();
+      return failure();
     rewriter.replaceOp(op, *maybeExpandedMap);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -431,18 +431,18 @@ class AffineLoadLowering : public OpRewritePattern<AffineLoadOp> {
 public:
   using OpRewritePattern<AffineLoadOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineLoadOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineLoadOp op,
+                                PatternRewriter &rewriter) const override {
     // Expand affine map from 'affineLoadOp'.
     SmallVector<Value, 8> indices(op.getMapOperands());
     auto resultOperands =
         expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
     if (!resultOperands)
-      return matchFailure();
+      return failure();
 
     // Build std.load memref[expandedMap.results].
     rewriter.replaceOpWithNewOp<LoadOp>(op, op.getMemRef(), *resultOperands);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -453,20 +453,20 @@ class AffinePrefetchLowering : public OpRewritePattern<AffinePrefetchOp> {
 public:
   using OpRewritePattern<AffinePrefetchOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffinePrefetchOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffinePrefetchOp op,
+                                PatternRewriter &rewriter) const override {
     // Expand affine map from 'affinePrefetchOp'.
     SmallVector<Value, 8> indices(op.getMapOperands());
     auto resultOperands =
         expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
     if (!resultOperands)
-      return matchFailure();
+      return failure();
 
     // Build std.prefetch memref[expandedMap.results].
     rewriter.replaceOpWithNewOp<PrefetchOp>(
         op, op.memref(), *resultOperands, op.isWrite(),
         op.localityHint().getZExtValue(), op.isDataCache());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -477,19 +477,19 @@ class AffineStoreLowering : public OpRewritePattern<AffineStoreOp> {
 public:
   using OpRewritePattern<AffineStoreOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineStoreOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineStoreOp op,
+                                PatternRewriter &rewriter) const override {
     // Expand affine map from 'affineStoreOp'.
     SmallVector<Value, 8> indices(op.getMapOperands());
     auto maybeExpandedMap =
         expandAffineMap(rewriter, op.getLoc(), op.getAffineMap(), indices);
     if (!maybeExpandedMap)
-      return matchFailure();
+      return failure();
 
     // Build std.store valueToStore, memref[expandedMap.results].
     rewriter.replaceOpWithNewOp<StoreOp>(op, op.getValueToStore(),
                                          op.getMemRef(), *maybeExpandedMap);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -500,8 +500,8 @@ class AffineDmaStartLowering : public OpRewritePattern<AffineDmaStartOp> {
 public:
   using OpRewritePattern<AffineDmaStartOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineDmaStartOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineDmaStartOp op,
+                                PatternRewriter &rewriter) const override {
     SmallVector<Value, 8> operands(op.getOperands());
     auto operandsRef = llvm::makeArrayRef(operands);
 
@@ -510,26 +510,26 @@ class AffineDmaStartLowering : public OpRewritePattern<AffineDmaStartOp> {
         rewriter, op.getLoc(), op.getSrcMap(),
         operandsRef.drop_front(op.getSrcMemRefOperandIndex() + 1));
     if (!maybeExpandedSrcMap)
-      return matchFailure();
+      return failure();
     // Expand affine map for DMA destination memref.
     auto maybeExpandedDstMap = expandAffineMap(
         rewriter, op.getLoc(), op.getDstMap(),
         operandsRef.drop_front(op.getDstMemRefOperandIndex() + 1));
     if (!maybeExpandedDstMap)
-      return matchFailure();
+      return failure();
     // Expand affine map for DMA tag memref.
     auto maybeExpandedTagMap = expandAffineMap(
         rewriter, op.getLoc(), op.getTagMap(),
         operandsRef.drop_front(op.getTagMemRefOperandIndex() + 1));
     if (!maybeExpandedTagMap)
-      return matchFailure();
+      return failure();
 
     // Build std.dma_start operation with affine map results.
     rewriter.replaceOpWithNewOp<DmaStartOp>(
         op, op.getSrcMemRef(), *maybeExpandedSrcMap, op.getDstMemRef(),
         *maybeExpandedDstMap, op.getNumElements(), op.getTagMemRef(),
         *maybeExpandedTagMap, op.getStride(), op.getNumElementsPerStride());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -540,19 +540,19 @@ class AffineDmaWaitLowering : public OpRewritePattern<AffineDmaWaitOp> {
 public:
   using OpRewritePattern<AffineDmaWaitOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineDmaWaitOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineDmaWaitOp op,
+                                PatternRewriter &rewriter) const override {
     // Expand affine map for DMA tag memref.
     SmallVector<Value, 8> indices(op.getTagIndices());
     auto maybeExpandedTagMap =
         expandAffineMap(rewriter, op.getLoc(), op.getTagMap(), indices);
     if (!maybeExpandedTagMap)
-      return matchFailure();
+      return failure();
 
     // Build std.dma_wait operation with affine map results.
     rewriter.replaceOpWithNewOp<DmaWaitOp>(
         op, op.getTagMemRef(), *maybeExpandedTagMap, op.getNumElements());
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h b/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
index f925481ae7a05..3ab1fc48cf72a 100644
--- a/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
+++ b/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
@@ -46,7 +46,7 @@ struct GPUIndexIntrinsicOpLowering : public ConvertToLLVMPattern {
         indexBitwidth(getIndexBitWidth(lowering_)) {}
 
   // Convert the kernel arguments to an LLVM type, preserve the rest.
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -63,7 +63,7 @@ struct GPUIndexIntrinsicOpLowering : public ConvertToLLVMPattern {
       newOp = rewriter.create<ZOp>(loc, LLVM::LLVMType::getInt32Ty(dialect));
       break;
     default:
-      return matchFailure();
+      return failure();
     }
 
     if (indexBitwidth > 32) {
@@ -75,7 +75,7 @@ struct GPUIndexIntrinsicOpLowering : public ConvertToLLVMPattern {
     }
 
     rewriter.replaceOp(op, {newOp});
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
index fafdb9d1b90e3..eb5628d18e46f 100644
--- a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
+++ b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
@@ -34,7 +34,7 @@ struct OpToFuncCallLowering : public ConvertToLLVMPattern {
                              lowering_.getDialect()->getContext(), lowering_),
         f32Func(f32Func), f64Func(f64Func) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     using LLVM::LLVMFuncOp;
@@ -49,13 +49,13 @@ struct OpToFuncCallLowering : public ConvertToLLVMPattern {
     LLVMType funcType = getFunctionType(resultType, operands);
     StringRef funcName = getFunctionName(resultType);
     if (funcName.empty())
-      return matchFailure();
+      return failure();
 
     LLVMFuncOp funcOp = appendOrGetFuncOp(funcName, funcType, op);
     auto callOp = rewriter.create<LLVM::CallOp>(
         op->getLoc(), resultType, rewriter.getSymbolRefAttr(funcOp), operands);
     rewriter.replaceOp(op, {callOp.getResult(0)});
-    return matchSuccess();
+    return success();
   }
 
 private:
diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
index 67c335e629fe0..e929caac6133f 100644
--- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
+++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
@@ -51,7 +51,7 @@ struct GPUShuffleOpLowering : public ConvertToLLVMPattern {
   ///         !llvm<"{ float, i1 }">
   ///     %shfl_pred = llvm.extractvalue %shfl[1 : index] :
   ///         !llvm<"{ float, i1 }">
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     Location loc = op->getLoc();
@@ -84,7 +84,7 @@ struct GPUShuffleOpLowering : public ConvertToLLVMPattern {
         loc, predTy, shfl, rewriter.getIndexArrayAttr(1));
 
     rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -94,7 +94,7 @@ struct GPUFuncOpLowering : ConvertToLLVMPattern {
                              typeConverter.getDialect()->getContext(),
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     assert(operands.empty() && "func op is not expected to have operands");
@@ -219,7 +219,7 @@ struct GPUFuncOpLowering : ConvertToLLVMPattern {
                                       signatureConversion);
 
     rewriter.eraseOp(gpuFuncOp);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -229,11 +229,11 @@ struct GPUReturnOpLowering : public ConvertToLLVMPattern {
                              typeConverter.getDialect()->getContext(),
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(op, operands);
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp b/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
index 3c07097db542a..533ef7f53b92c 100644
--- a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
+++ b/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
@@ -26,7 +26,7 @@ class ForOpConversion final : public SPIRVOpLowering<loop::ForOp> {
 public:
   using SPIRVOpLowering<loop::ForOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(loop::ForOp forOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -37,7 +37,7 @@ class IfOpConversion final : public SPIRVOpLowering<loop::IfOp> {
 public:
   using SPIRVOpLowering<loop::IfOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(loop::IfOp IfOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -47,11 +47,11 @@ class TerminatorOpConversion final : public SPIRVOpLowering<loop::YieldOp> {
 public:
   using SPIRVOpLowering<loop::YieldOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(loop::YieldOp terminatorOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.eraseOp(terminatorOp);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -62,7 +62,7 @@ class LaunchConfigConversion : public SPIRVOpLowering<SourceOp> {
 public:
   using SPIRVOpLowering<SourceOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(SourceOp op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -75,7 +75,7 @@ class WorkGroupSizeConversion : public SPIRVOpLowering<gpu::BlockDimOp> {
 public:
   using SPIRVOpLowering<gpu::BlockDimOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(gpu::BlockDimOp op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -85,7 +85,7 @@ class GPUFuncOpConversion final : public SPIRVOpLowering<gpu::GPUFuncOp> {
 public:
   using SPIRVOpLowering<gpu::GPUFuncOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(gpu::GPUFuncOp funcOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 
@@ -98,7 +98,7 @@ class GPUModuleConversion final : public SPIRVOpLowering<gpu::GPUModuleOp> {
 public:
   using SPIRVOpLowering<gpu::GPUModuleOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(gpu::GPUModuleOp moduleOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -109,7 +109,7 @@ class GPUReturnOpConversion final : public SPIRVOpLowering<gpu::ReturnOp> {
 public:
   using SPIRVOpLowering<gpu::ReturnOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(gpu::ReturnOp returnOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -120,7 +120,7 @@ class GPUReturnOpConversion final : public SPIRVOpLowering<gpu::ReturnOp> {
 // loop::ForOp.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 ForOpConversion::matchAndRewrite(loop::ForOp forOp, ArrayRef<Value> operands,
                                  ConversionPatternRewriter &rewriter) const {
   // loop::ForOp can be lowered to the structured control flow represented by
@@ -186,14 +186,14 @@ ForOpConversion::matchAndRewrite(loop::ForOp forOp, ArrayRef<Value> operands,
   rewriter.create<spirv::BranchOp>(loc, header, updatedIndVar);
 
   rewriter.eraseOp(forOp);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // loop::IfOp.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 IfOpConversion::matchAndRewrite(loop::IfOp ifOp, ArrayRef<Value> operands,
                                 ConversionPatternRewriter &rewriter) const {
   // When lowering `loop::IfOp` we explicitly create a selection header block
@@ -238,7 +238,7 @@ IfOpConversion::matchAndRewrite(loop::IfOp ifOp, ArrayRef<Value> operands,
                                               elseBlock, ArrayRef<Value>());
 
   rewriter.eraseOp(ifOp);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
@@ -261,36 +261,36 @@ static Optional<int32_t> getLaunchConfigIndex(Operation *op) {
 }
 
 template <typename SourceOp, spirv::BuiltIn builtin>
-PatternMatchResult LaunchConfigConversion<SourceOp, builtin>::matchAndRewrite(
+LogicalResult LaunchConfigConversion<SourceOp, builtin>::matchAndRewrite(
     SourceOp op, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   auto index = getLaunchConfigIndex(op);
   if (!index)
-    return this->matchFailure();
+    return failure();
 
   // SPIR-V invocation builtin variables are a vector of type <3xi32>
   auto spirvBuiltin = spirv::getBuiltinVariableValue(op, builtin, rewriter);
   rewriter.replaceOpWithNewOp<spirv::CompositeExtractOp>(
       op, rewriter.getIntegerType(32), spirvBuiltin,
       rewriter.getI32ArrayAttr({index.getValue()}));
-  return this->matchSuccess();
+  return success();
 }
 
-PatternMatchResult WorkGroupSizeConversion::matchAndRewrite(
+LogicalResult WorkGroupSizeConversion::matchAndRewrite(
     gpu::BlockDimOp op, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   auto index = getLaunchConfigIndex(op);
   if (!index)
-    return matchFailure();
+    return failure();
 
   auto workGroupSizeAttr = spirv::lookupLocalWorkGroupSize(op);
   auto val = workGroupSizeAttr.getValue<int32_t>(index.getValue());
   auto convertedType = typeConverter.convertType(op.getResult().getType());
   if (!convertedType)
-    return matchFailure();
+    return failure();
   rewriter.replaceOpWithNewOp<spirv::ConstantOp>(
       op, convertedType, IntegerAttr::get(convertedType, val));
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
@@ -343,11 +343,11 @@ lowerAsEntryFunction(gpu::GPUFuncOp funcOp, SPIRVTypeConverter &typeConverter,
   return newFuncOp;
 }
 
-PatternMatchResult GPUFuncOpConversion::matchAndRewrite(
+LogicalResult GPUFuncOpConversion::matchAndRewrite(
     gpu::GPUFuncOp funcOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   if (!gpu::GPUDialect::isKernel(funcOp))
-    return matchFailure();
+    return failure();
 
   SmallVector<spirv::InterfaceVarABIAttr, 4> argABI;
   for (auto argNum : llvm::seq<unsigned>(0, funcOp.getNumArguments())) {
@@ -358,22 +358,22 @@ PatternMatchResult GPUFuncOpConversion::matchAndRewrite(
   auto entryPointAttr = spirv::lookupEntryPointABI(funcOp);
   if (!entryPointAttr) {
     funcOp.emitRemark("match failure: missing 'spv.entry_point_abi' attribute");
-    return matchFailure();
+    return failure();
   }
   spirv::FuncOp newFuncOp = lowerAsEntryFunction(
       funcOp, typeConverter, rewriter, entryPointAttr, argABI);
   if (!newFuncOp)
-    return matchFailure();
+    return failure();
   newFuncOp.removeAttr(Identifier::get(gpu::GPUDialect::getKernelFuncAttrName(),
                                        rewriter.getContext()));
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // ModuleOp with gpu.module.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult GPUModuleConversion::matchAndRewrite(
+LogicalResult GPUModuleConversion::matchAndRewrite(
     gpu::GPUModuleOp moduleOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   auto spvModule = rewriter.create<spirv::ModuleOp>(
@@ -389,21 +389,21 @@ PatternMatchResult GPUModuleConversion::matchAndRewrite(
   // legalized later.
   spvModuleRegion.back().erase();
   rewriter.eraseOp(moduleOp);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // GPU return inside kernel functions to SPIR-V return.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult GPUReturnOpConversion::matchAndRewrite(
+LogicalResult GPUReturnOpConversion::matchAndRewrite(
     gpu::ReturnOp returnOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   if (!operands.empty())
-    return matchFailure();
+    return failure();
 
   rewriter.replaceOpWithNewOp<spirv::ReturnOp>(returnOp);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp b/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp
index fcfae4563778d..26833fd4daa75 100644
--- a/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp
+++ b/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp
@@ -33,10 +33,10 @@ static constexpr const char *kVulkanLaunch = "vulkanLaunch";
 
 namespace {
 
-// A pass to convert gpu launch op to vulkan launch call op, by creating a
-// SPIR-V binary shader from `spirv::ModuleOp` using `spirv::serialize`
-// function and attaching binary data and entry point name as an attributes to
-// created vulkan launch call op.
+/// A pass to convert gpu launch op to vulkan launch call op, by creating a
+/// SPIR-V binary shader from `spirv::ModuleOp` using `spirv::serialize`
+/// function and attaching binary data and entry point name as an attributes to
+/// created vulkan launch call op.
 class ConvertGpuLaunchFuncToVulkanLaunchFunc
     : public ModulePass<ConvertGpuLaunchFuncToVulkanLaunchFunc> {
 public:
diff --git a/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp b/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
index 92c376e197886..f1dc52e5f8563 100644
--- a/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
+++ b/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
@@ -15,6 +15,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Conversion/GPUToVulkan/ConvertGPUToVulkanPass.h"
+#include "mlir/Dialect/GPU/GPUDialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Builders.h"
@@ -26,7 +27,9 @@
 
 using namespace mlir;
 
-static constexpr const char *kBindResource = "bindResource";
+static constexpr const char *kBindMemRef1DFloat = "bindMemRef1DFloat";
+static constexpr const char *kCInterfaceVulkanLaunch =
+    "_mlir_ciface_vulkanLaunch";
 static constexpr const char *kDeinitVulkan = "deinitVulkan";
 static constexpr const char *kRunOnVulkan = "runOnVulkan";
 static constexpr const char *kInitVulkan = "initVulkan";
@@ -40,11 +43,11 @@ static constexpr const char *kVulkanLaunch = "vulkanLaunch";
 
 namespace {
 
-/// A pass to convert vulkan launch func into a sequence of Vulkan
+/// A pass to convert vulkan launch call op into a sequence of Vulkan
 /// runtime calls in the following order:
 ///
 /// * initVulkan           -- initializes vulkan runtime
-/// * bindResource         -- binds resource
+/// * bindMemRef           -- binds memref
 /// * setBinaryShader      -- sets the binary shader data
 /// * setEntryPoint        -- sets the entry point name
 /// * setNumWorkGroups     -- sets the number of a local workgroups
@@ -67,6 +70,29 @@ class VulkanLaunchFuncToVulkanCallsPass
     llvmPointerType = LLVM::LLVMType::getInt8PtrTy(llvmDialect);
     llvmInt32Type = LLVM::LLVMType::getInt32Ty(llvmDialect);
     llvmInt64Type = LLVM::LLVMType::getInt64Ty(llvmDialect);
+    initializeMemRefTypes();
+  }
+
+  void initializeMemRefTypes() {
+    // According to the MLIR doc memref argument is converted into a
+    // pointer-to-struct argument of type:
+    // template <typename Elem, size_t Rank>
+    // struct {
+    //   Elem *allocated;
+    //   Elem *aligned;
+    //   int64_t offset;
+    //   int64_t sizes[Rank]; // omitted when rank == 0
+    //   int64_t strides[Rank]; // omitted when rank == 0
+    // };
+    auto llvmPtrToFloatType = getFloatType().getPointerTo();
+    auto llvmArrayOneElementSizeType =
+        LLVM::LLVMType::getArrayTy(getInt64Type(), 1);
+
+    // Create a type `!llvm<"{ float*, float*, i64, [1 x i64], [1 x i64]}">`.
+    llvmMemRef1DFloat = LLVM::LLVMType::getStructTy(
+        llvmDialect,
+        {llvmPtrToFloatType, llvmPtrToFloatType, getInt64Type(),
+         llvmArrayOneElementSizeType, llvmArrayOneElementSizeType});
   }
 
   LLVM::LLVMType getFloatType() { return llvmFloatType; }
@@ -74,6 +100,7 @@ class VulkanLaunchFuncToVulkanCallsPass
   LLVM::LLVMType getPointerType() { return llvmPointerType; }
   LLVM::LLVMType getInt32Type() { return llvmInt32Type; }
   LLVM::LLVMType getInt64Type() { return llvmInt64Type; }
+  LLVM::LLVMType getMemRef1DFloat() { return llvmMemRef1DFloat; }
 
   /// Creates a LLVM global for the given `name`.
   Value createEntryPointNameConstant(StringRef name, Location loc,
@@ -85,16 +112,27 @@ class VulkanLaunchFuncToVulkanCallsPass
   /// Checks whether the given LLVM::CallOp is a vulkan launch call op.
   bool isVulkanLaunchCallOp(LLVM::CallOp callOp) {
     return (callOp.callee() && callOp.callee().getValue() == kVulkanLaunch &&
-            callOp.getNumOperands() >= 6);
+            callOp.getNumOperands() >= gpu::LaunchOp::kNumConfigOperands);
+  }
+
+  /// Checks whether the given LLVM::CallOp is a "ci_face" vulkan launch call
+  /// op.
+  bool isCInterfaceVulkanLaunchCallOp(LLVM::CallOp callOp) {
+    return (callOp.callee() &&
+            callOp.callee().getValue() == kCInterfaceVulkanLaunch &&
+            callOp.getNumOperands() >= gpu::LaunchOp::kNumConfigOperands);
   }
 
   /// Translates the given `vulkanLaunchCallOp` to the sequence of Vulkan
   /// runtime calls.
   void translateVulkanLaunchCall(LLVM::CallOp vulkanLaunchCallOp);
 
-  /// Creates call to `bindResource` for each resource operand.
-  void createBindResourceCalls(LLVM::CallOp vulkanLaunchCallOp,
-                               Value vulkanRuntiem);
+  /// Creates call to `bindMemRef` for each memref operand.
+  void createBindMemRefCalls(LLVM::CallOp vulkanLaunchCallOp,
+                             Value vulkanRuntime);
+
+  /// Collects SPIRV attributes from the given `vulkanLaunchCallOp`.
+  void collectSPIRVAttributes(LLVM::CallOp vulkanLaunchCallOp);
 
 public:
   void runOnModule() override;
@@ -106,89 +144,81 @@ class VulkanLaunchFuncToVulkanCallsPass
   LLVM::LLVMType llvmPointerType;
   LLVM::LLVMType llvmInt32Type;
   LLVM::LLVMType llvmInt64Type;
-};
-
-/// Represents operand adaptor for vulkan launch call operation, to simplify an
-/// access to the lowered memref.
-// TODO: We should use 'emit-c-wrappers' option to lower memref type:
-// https://mlir.llvm.org/docs/ConversionToLLVMDialect/#c-compatible-wrapper-emission.
-struct VulkanLaunchOpOperandAdaptor {
-  VulkanLaunchOpOperandAdaptor(ArrayRef<Value> values) { operands = values; }
-  VulkanLaunchOpOperandAdaptor(const VulkanLaunchOpOperandAdaptor &) = delete;
-  VulkanLaunchOpOperandAdaptor
-  operator=(const VulkanLaunchOpOperandAdaptor &) = delete;
-
-  /// Returns a tuple with a pointer to the memory and the size for the index-th
-  /// resource.
-  std::tuple<Value, Value> getResourceDescriptor1D(uint32_t index) {
-    assert(index < getResourceCount1D());
-    // 1D memref calling convention according to "ConversionToLLVMDialect.md":
-    // 0. Allocated pointer.
-    // 1. Aligned pointer.
-    // 2. Offset.
-    // 3. Size in dim 0.
-    // 4. Stride in dim 0.
-    auto offset = numConfigOps + index * loweredMemRefNumOps1D;
-    return std::make_tuple(operands[offset], operands[offset + 3]);
-  }
+  LLVM::LLVMType llvmMemRef1DFloat;
 
-  /// Returns the number of resources assuming all operands lowered from
-  /// 1D memref.
-  uint32_t getResourceCount1D() {
-    return (operands.size() - numConfigOps) / loweredMemRefNumOps1D;
-  }
-
-private:
-  /// The number of operands of lowered 1D memref.
-  static constexpr const uint32_t loweredMemRefNumOps1D = 5;
-  /// The number of the first config operands.
-  static constexpr const uint32_t numConfigOps = 6;
-  ArrayRef<Value> operands;
+  // TODO: Use an associative array to support multiple vulkan launch calls.
+  std::pair<StringAttr, StringAttr> spirvAttributes;
 };
 
 } // anonymous namespace
 
 void VulkanLaunchFuncToVulkanCallsPass::runOnModule() {
   initializeCachedTypes();
+
+  // Collect SPIR-V attributes such as `spirv_blob` and
+  // `spirv_entry_point_name`.
   getModule().walk([this](LLVM::CallOp op) {
     if (isVulkanLaunchCallOp(op))
+      collectSPIRVAttributes(op);
+  });
+
+  // Convert vulkan launch call op into a sequence of Vulkan runtime calls.
+  getModule().walk([this](LLVM::CallOp op) {
+    if (isCInterfaceVulkanLaunchCallOp(op))
       translateVulkanLaunchCall(op);
   });
 }
 
-void VulkanLaunchFuncToVulkanCallsPass::createBindResourceCalls(
-    LLVM::CallOp vulkanLaunchCallOp, Value vulkanRuntime) {
-  if (vulkanLaunchCallOp.getNumOperands() == 6)
+void VulkanLaunchFuncToVulkanCallsPass::collectSPIRVAttributes(
+    LLVM::CallOp vulkanLaunchCallOp) {
+  // Check that `kSPIRVBinary` and `kSPIRVEntryPoint` are present in attributes
+  // for the given vulkan launch call.
+  auto spirvBlobAttr =
+      vulkanLaunchCallOp.getAttrOfType<StringAttr>(kSPIRVBlobAttrName);
+  if (!spirvBlobAttr) {
+    vulkanLaunchCallOp.emitError()
+        << "missing " << kSPIRVBlobAttrName << " attribute";
+    return signalPassFailure();
+  }
+
+  auto spirvEntryPointNameAttr =
+      vulkanLaunchCallOp.getAttrOfType<StringAttr>(kSPIRVEntryPointAttrName);
+  if (!spirvEntryPointNameAttr) {
+    vulkanLaunchCallOp.emitError()
+        << "missing " << kSPIRVEntryPointAttrName << " attribute";
+    return signalPassFailure();
+  }
+
+  spirvAttributes = std::make_pair(spirvBlobAttr, spirvEntryPointNameAttr);
+}
+
+void VulkanLaunchFuncToVulkanCallsPass::createBindMemRefCalls(
+    LLVM::CallOp cInterfaceVulkanLaunchCallOp, Value vulkanRuntime) {
+  if (cInterfaceVulkanLaunchCallOp.getNumOperands() ==
+      gpu::LaunchOp::kNumConfigOperands)
     return;
-  OpBuilder builder(vulkanLaunchCallOp);
-  Location loc = vulkanLaunchCallOp.getLoc();
+  OpBuilder builder(cInterfaceVulkanLaunchCallOp);
+  Location loc = cInterfaceVulkanLaunchCallOp.getLoc();
 
   // Create LLVM constant for the descriptor set index.
-  // Bind all resources to the `0` descriptor set, the same way as `GPUToSPIRV`
+  // Bind all memrefs to the `0` descriptor set, the same way as `GPUToSPIRV`
   // pass does.
   Value descriptorSet = builder.create<LLVM::ConstantOp>(
       loc, getInt32Type(), builder.getI32IntegerAttr(0));
 
-  auto operands = SmallVector<Value, 32>{vulkanLaunchCallOp.getOperands()};
-  VulkanLaunchOpOperandAdaptor vkLaunchOperandAdaptor(operands);
-
-  for (auto resourceIdx :
-       llvm::seq<uint32_t>(0, vkLaunchOperandAdaptor.getResourceCount1D())) {
+  for (auto en :
+       llvm::enumerate(cInterfaceVulkanLaunchCallOp.getOperands().drop_front(
+           gpu::LaunchOp::kNumConfigOperands))) {
     // Create LLVM constant for the descriptor binding index.
     Value descriptorBinding = builder.create<LLVM::ConstantOp>(
-        loc, getInt32Type(), builder.getI32IntegerAttr(resourceIdx));
-    // Get a pointer to the memory and size of that memory.
-    auto resourceDescriptor =
-        vkLaunchOperandAdaptor.getResourceDescriptor1D(resourceIdx);
-    // Create call to `bindResource`.
+        loc, getInt32Type(), builder.getI32IntegerAttr(en.index()));
+    // Create call to `bindMemRef`.
     builder.create<LLVM::CallOp>(
         loc, ArrayRef<Type>{getVoidType()},
-        builder.getSymbolRefAttr(kBindResource),
+        // TODO: Add support for memref with other ranks.
+        builder.getSymbolRefAttr(kBindMemRef1DFloat),
         ArrayRef<Value>{vulkanRuntime, descriptorSet, descriptorBinding,
-                        // Pointer to the memory.
-                        std::get<0>(resourceDescriptor),
-                        // Size of the memory.
-                        std::get<1>(resourceDescriptor)});
+                        en.value()});
   }
 }
 
@@ -228,14 +258,14 @@ void VulkanLaunchFuncToVulkanCallsPass::declareVulkanFunctions(Location loc) {
                                       /*isVarArg=*/false));
   }
 
-  if (!module.lookupSymbol(kBindResource)) {
+  if (!module.lookupSymbol(kBindMemRef1DFloat)) {
     builder.create<LLVM::LLVMFuncOp>(
-        loc, kBindResource,
-        LLVM::LLVMType::getFunctionTy(
-            getVoidType(),
-            {getPointerType(), getInt32Type(), getInt32Type(),
-             getFloatType().getPointerTo(), getInt64Type()},
-            /*isVarArg=*/false));
+        loc, kBindMemRef1DFloat,
+        LLVM::LLVMType::getFunctionTy(getVoidType(),
+                                      {getPointerType(), getInt32Type(),
+                                       getInt32Type(),
+                                       getMemRef1DFloat().getPointerTo()},
+                                      /*isVarArg=*/false));
   }
 
   if (!module.lookupSymbol(kInitVulkan)) {
@@ -267,28 +297,9 @@ Value VulkanLaunchFuncToVulkanCallsPass::createEntryPointNameConstant(
 }
 
 void VulkanLaunchFuncToVulkanCallsPass::translateVulkanLaunchCall(
-    LLVM::CallOp vulkanLaunchCallOp) {
-  OpBuilder builder(vulkanLaunchCallOp);
-  Location loc = vulkanLaunchCallOp.getLoc();
-
-  // Check that `kSPIRVBinary` and `kSPIRVEntryPoint` are present in attributes
-  // for the given vulkan launch call.
-  auto spirvBlobAttr =
-      vulkanLaunchCallOp.getAttrOfType<StringAttr>(kSPIRVBlobAttrName);
-  if (!spirvBlobAttr) {
-    vulkanLaunchCallOp.emitError()
-        << "missing " << kSPIRVBlobAttrName << " attribute";
-    return signalPassFailure();
-  }
-
-  auto entryPointNameAttr =
-      vulkanLaunchCallOp.getAttrOfType<StringAttr>(kSPIRVEntryPointAttrName);
-  if (!entryPointNameAttr) {
-    vulkanLaunchCallOp.emitError()
-        << "missing " << kSPIRVEntryPointAttrName << " attribute";
-    return signalPassFailure();
-  }
-
+    LLVM::CallOp cInterfaceVulkanLaunchCallOp) {
+  OpBuilder builder(cInterfaceVulkanLaunchCallOp);
+  Location loc = cInterfaceVulkanLaunchCallOp.getLoc();
   // Create call to `initVulkan`.
   auto initVulkanCall = builder.create<LLVM::CallOp>(
       loc, ArrayRef<Type>{getPointerType()},
@@ -300,16 +311,16 @@ void VulkanLaunchFuncToVulkanCallsPass::translateVulkanLaunchCall(
   // Create LLVM global with SPIR-V binary data, so we can pass a pointer with
   // that data to runtime call.
   Value ptrToSPIRVBinary = LLVM::createGlobalString(
-      loc, builder, kSPIRVBinary, spirvBlobAttr.getValue(),
+      loc, builder, kSPIRVBinary, spirvAttributes.first.getValue(),
       LLVM::Linkage::Internal, getLLVMDialect());
 
   // Create LLVM constant for the size of SPIR-V binary shader.
   Value binarySize = builder.create<LLVM::ConstantOp>(
       loc, getInt32Type(),
-      builder.getI32IntegerAttr(spirvBlobAttr.getValue().size()));
+      builder.getI32IntegerAttr(spirvAttributes.first.getValue().size()));
 
-  // Create call to `bindResource` for each resource operand.
-  createBindResourceCalls(vulkanLaunchCallOp, vulkanRuntime);
+  // Create call to `bindMemRef` for each memref operand.
+  createBindMemRefCalls(cInterfaceVulkanLaunchCallOp, vulkanRuntime);
 
   // Create call to `setBinaryShader` runtime function with the given pointer to
   // SPIR-V binary and binary size.
@@ -318,8 +329,8 @@ void VulkanLaunchFuncToVulkanCallsPass::translateVulkanLaunchCall(
       builder.getSymbolRefAttr(kSetBinaryShader),
       ArrayRef<Value>{vulkanRuntime, ptrToSPIRVBinary, binarySize});
   // Create LLVM global with entry point name.
-  Value entryPointName =
-      createEntryPointNameConstant(entryPointNameAttr.getValue(), loc, builder);
+  Value entryPointName = createEntryPointNameConstant(
+      spirvAttributes.second.getValue(), loc, builder);
   // Create call to `setEntryPoint` runtime function with the given pointer to
   // entry point name.
   builder.create<LLVM::CallOp>(loc, ArrayRef<Type>{getVoidType()},
@@ -330,9 +341,9 @@ void VulkanLaunchFuncToVulkanCallsPass::translateVulkanLaunchCall(
   builder.create<LLVM::CallOp>(
       loc, ArrayRef<Type>{getVoidType()},
       builder.getSymbolRefAttr(kSetNumWorkGroups),
-      ArrayRef<Value>{vulkanRuntime, vulkanLaunchCallOp.getOperand(0),
-                      vulkanLaunchCallOp.getOperand(1),
-                      vulkanLaunchCallOp.getOperand(2)});
+      ArrayRef<Value>{vulkanRuntime, cInterfaceVulkanLaunchCallOp.getOperand(0),
+                      cInterfaceVulkanLaunchCallOp.getOperand(1),
+                      cInterfaceVulkanLaunchCallOp.getOperand(2)});
 
   // Create call to `runOnVulkan` runtime function.
   builder.create<LLVM::CallOp>(loc, ArrayRef<Type>{getVoidType()},
@@ -347,7 +358,7 @@ void VulkanLaunchFuncToVulkanCallsPass::translateVulkanLaunchCall(
   // Declare runtime functions.
   declareVulkanFunctions(loc);
 
-  vulkanLaunchCallOp.erase();
+  cInterfaceVulkanLaunchCallOp.erase();
 }
 
 std::unique_ptr<mlir::OpPassBase<mlir::ModuleOp>>
diff --git a/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp b/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
index 497cb448ef423..577b134fa5ed5 100644
--- a/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
+++ b/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
@@ -130,7 +130,7 @@ class RangeOpConversion : public ConvertToLLVMPattern {
   explicit RangeOpConversion(MLIRContext *context, LLVMTypeConverter &lowering_)
       : ConvertToLLVMPattern(RangeOp::getOperationName(), context, lowering_) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto rangeOp = cast<RangeOp>(op);
@@ -146,7 +146,7 @@ class RangeOpConversion : public ConvertToLLVMPattern {
     desc = llvm_insertvalue(desc, adaptor.max(), rewriter.getI64ArrayAttr(1));
     desc = llvm_insertvalue(desc, adaptor.step(), rewriter.getI64ArrayAttr(2));
     rewriter.replaceOp(op, desc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -160,14 +160,14 @@ class ReshapeOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(ReshapeOp::getOperationName(), context,
                              lowering_) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto reshapeOp = cast<ReshapeOp>(op);
     MemRefType dstType = reshapeOp.getResult().getType().cast<MemRefType>();
 
     if (!dstType.hasStaticShape())
-      return matchFailure();
+      return failure();
 
     int64_t offset;
     SmallVector<int64_t, 4> strides;
@@ -175,7 +175,7 @@ class ReshapeOpConversion : public ConvertToLLVMPattern {
     if (failed(res) || llvm::any_of(strides, [](int64_t val) {
           return ShapedType::isDynamicStrideOrOffset(val);
         }))
-      return matchFailure();
+      return failure();
 
     edsc::ScopedContext context(rewriter, op->getLoc());
     ReshapeOpOperandAdaptor adaptor(operands);
@@ -189,7 +189,7 @@ class ReshapeOpConversion : public ConvertToLLVMPattern {
     for (auto en : llvm::enumerate(strides))
       desc.setConstantStride(en.index(), en.value());
     rewriter.replaceOp(op, {desc});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -204,7 +204,7 @@ class SliceOpConversion : public ConvertToLLVMPattern {
   explicit SliceOpConversion(MLIRContext *context, LLVMTypeConverter &lowering_)
       : ConvertToLLVMPattern(SliceOp::getOperationName(), context, lowering_) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     edsc::ScopedContext context(rewriter, op->getLoc());
@@ -247,7 +247,7 @@ class SliceOpConversion : public ConvertToLLVMPattern {
 
     // Corner case, no sizes or strides: early return the descriptor.
     if (sliceOp.getShapedType().getRank() == 0)
-      return rewriter.replaceOp(op, {desc}), matchSuccess();
+      return rewriter.replaceOp(op, {desc}), success();
 
     Value zero = llvm_constant(
         int64Ty, rewriter.getIntegerAttr(rewriter.getIndexType(), 0));
@@ -279,7 +279,7 @@ class SliceOpConversion : public ConvertToLLVMPattern {
     }
 
     rewriter.replaceOp(op, {desc});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -297,7 +297,7 @@ class TransposeOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(TransposeOp::getOperationName(), context,
                              lowering_) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     // Initialize the common boilerplate and alloca at the top of the FuncOp.
@@ -308,7 +308,7 @@ class TransposeOpConversion : public ConvertToLLVMPattern {
     auto transposeOp = cast<TransposeOp>(op);
     // No permutation, early exit.
     if (transposeOp.permutation().isIdentity())
-      return rewriter.replaceOp(op, {baseDesc}), matchSuccess();
+      return rewriter.replaceOp(op, {baseDesc}), success();
 
     BaseViewConversionHelper desc(
         typeConverter.convertType(transposeOp.getShapedType()));
@@ -330,7 +330,7 @@ class TransposeOpConversion : public ConvertToLLVMPattern {
     }
 
     rewriter.replaceOp(op, {desc});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -340,11 +340,11 @@ class YieldOpConversion : public ConvertToLLVMPattern {
   explicit YieldOpConversion(MLIRContext *context, LLVMTypeConverter &lowering_)
       : ConvertToLLVMPattern(YieldOp::getOperationName(), context, lowering_) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(op, operands);
-    return matchSuccess();
+    return success();
   }
 };
 } // namespace
@@ -416,15 +416,15 @@ class LinalgOpConversion : public OpRewritePattern<LinalgOp> {
 public:
   using OpRewritePattern<LinalgOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(LinalgOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(LinalgOp op,
+                                PatternRewriter &rewriter) const override {
     auto libraryCallName = getLibraryCallSymbolRef<LinalgOp>(op, rewriter);
     if (!libraryCallName)
-      return this->matchFailure();
+      return failure();
 
     rewriter.replaceOpWithNewOp<mlir::CallOp>(
         op, libraryCallName.getValue(), ArrayRef<Type>{}, op.getOperands());
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -434,22 +434,22 @@ template <> class LinalgOpConversion<CopyOp> : public OpRewritePattern<CopyOp> {
 public:
   using OpRewritePattern<CopyOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(CopyOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(CopyOp op,
+                                PatternRewriter &rewriter) const override {
     auto inputPerm = op.inputPermutation();
     if (inputPerm.hasValue() && !inputPerm->isIdentity())
-      return matchFailure();
+      return failure();
     auto outputPerm = op.outputPermutation();
     if (outputPerm.hasValue() && !outputPerm->isIdentity())
-      return matchFailure();
+      return failure();
 
     auto libraryCallName = getLibraryCallSymbolRef<CopyOp>(op, rewriter);
     if (!libraryCallName)
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOpWithNewOp<mlir::CallOp>(
         op, libraryCallName.getValue(), ArrayRef<Type>{}, op.getOperands());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -460,12 +460,12 @@ class LinalgOpConversion<IndexedGenericOp>
 public:
   using OpRewritePattern<IndexedGenericOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(IndexedGenericOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(IndexedGenericOp op,
+                                PatternRewriter &rewriter) const override {
     auto libraryCallName =
         getLibraryCallSymbolRef<IndexedGenericOp>(op, rewriter);
     if (!libraryCallName)
-      return this->matchFailure();
+      return failure();
 
     // TODO(pifon, ntv): Use induction variables values instead of zeros, when
     // IndexedGenericOp is tiled.
@@ -483,7 +483,7 @@ class LinalgOpConversion<IndexedGenericOp>
     }
     rewriter.replaceOpWithNewOp<mlir::CallOp>(op, libraryCallName.getValue(),
                                               ArrayRef<Type>{}, operands);
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -495,8 +495,8 @@ class CopyTransposeConversion : public OpRewritePattern<CopyOp> {
 public:
   using OpRewritePattern<CopyOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(CopyOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(CopyOp op,
+                                PatternRewriter &rewriter) const override {
     Value in = op.input(), out = op.output();
 
     // If either inputPerm or outputPerm are non-identities, insert transposes.
@@ -511,10 +511,10 @@ class CopyTransposeConversion : public OpRewritePattern<CopyOp> {
 
     // If nothing was transposed, fail and let the conversion kick in.
     if (in == op.input() && out == op.output())
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOpWithNewOp<CopyOp>(op, in, out);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -562,6 +562,7 @@ void ConvertLinalgToLLVMPass::runOnModule() {
   populateLoopToStdConversionPatterns(patterns, &getContext());
   populateStdToLLVMConversionPatterns(converter, patterns, /*useAlloca=*/false,
                                       /*emitCWrappers=*/true);
+  populateVectorToLLVMMatrixConversionPatterns(converter, patterns);
   populateVectorToLLVMConversionPatterns(converter, patterns);
   populateLinalgToStandardConversionPatterns(patterns, &getContext());
   populateLinalgToLLVMConversionPatterns(converter, patterns, &getContext());
diff --git a/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp b/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
index 7598126331361..90ec624a8cc14 100644
--- a/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
+++ b/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
@@ -54,7 +54,7 @@ class SingleWorkgroupReduction final
   static Optional<linalg::RegionMatcher::BinaryOpKind>
   matchAsPerformingReduction(linalg::GenericOp genericOp);
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(linalg::GenericOp genericOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -109,7 +109,7 @@ SingleWorkgroupReduction::matchAsPerformingReduction(
   return linalg::RegionMatcher::matchAsScalarBinaryOp(genericOp);
 }
 
-PatternMatchResult SingleWorkgroupReduction::matchAndRewrite(
+LogicalResult SingleWorkgroupReduction::matchAndRewrite(
     linalg::GenericOp genericOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   Operation *op = genericOp.getOperation();
@@ -118,19 +118,19 @@ PatternMatchResult SingleWorkgroupReduction::matchAndRewrite(
 
   auto binaryOpKind = matchAsPerformingReduction(genericOp);
   if (!binaryOpKind)
-    return matchFailure();
+    return failure();
 
   // Query the shader interface for local workgroup size to make sure the
   // invocation configuration fits with the input memref's shape.
   DenseIntElementsAttr localSize = spirv::lookupLocalWorkGroupSize(genericOp);
   if (!localSize)
-    return matchFailure();
+    return failure();
 
   if ((*localSize.begin()).getSExtValue() != originalInputType.getDimSize(0))
-    return matchFailure();
+    return failure();
   if (llvm::any_of(llvm::drop_begin(localSize.getIntValues(), 1),
                    [](const APInt &size) { return !size.isOneValue(); }))
-    return matchFailure();
+    return failure();
 
   // TODO(antiagainst): Query the target environment to make sure the current
   // workload fits in a local workgroup.
@@ -195,7 +195,7 @@ PatternMatchResult SingleWorkgroupReduction::matchAndRewrite(
   spirv::SelectionOp::createIfThen(loc, condition, createAtomicOp, &rewriter);
 
   rewriter.eraseOp(genericOp);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp b/mlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp
index a16c4a0c5cfb8..8f7c76c921e19 100644
--- a/mlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp
+++ b/mlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp
@@ -98,8 +98,8 @@ struct LoopToStandardPass : public OperationPass<LoopToStandardPass> {
 struct ForLowering : public OpRewritePattern<ForOp> {
   using OpRewritePattern<ForOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(ForOp forOp,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(ForOp forOp,
+                                PatternRewriter &rewriter) const override;
 };
 
 // Create a CFG subgraph for the loop.if operation (including its "then" and
@@ -147,20 +147,20 @@ struct ForLowering : public OpRewritePattern<ForOp> {
 struct IfLowering : public OpRewritePattern<IfOp> {
   using OpRewritePattern<IfOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(IfOp ifOp,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(IfOp ifOp,
+                                PatternRewriter &rewriter) const override;
 };
 
 struct ParallelLowering : public OpRewritePattern<mlir::loop::ParallelOp> {
   using OpRewritePattern<mlir::loop::ParallelOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(mlir::loop::ParallelOp parallelOp,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(mlir::loop::ParallelOp parallelOp,
+                                PatternRewriter &rewriter) const override;
 };
 } // namespace
 
-PatternMatchResult
-ForLowering::matchAndRewrite(ForOp forOp, PatternRewriter &rewriter) const {
+LogicalResult ForLowering::matchAndRewrite(ForOp forOp,
+                                           PatternRewriter &rewriter) const {
   Location loc = forOp.getLoc();
 
   // Start by splitting the block containing the 'loop.for' into two parts.
@@ -189,7 +189,7 @@ ForLowering::matchAndRewrite(ForOp forOp, PatternRewriter &rewriter) const {
   auto step = forOp.step();
   auto stepped = rewriter.create<AddIOp>(loc, iv, step).getResult();
   if (!stepped)
-    return matchFailure();
+    return failure();
 
   SmallVector<Value, 8> loopCarried;
   loopCarried.push_back(stepped);
@@ -202,7 +202,7 @@ ForLowering::matchAndRewrite(ForOp forOp, PatternRewriter &rewriter) const {
   Value lowerBound = forOp.lowerBound();
   Value upperBound = forOp.upperBound();
   if (!lowerBound || !upperBound)
-    return matchFailure();
+    return failure();
 
   // The initial values of loop-carried values is obtained from the operands
   // of the loop operation.
@@ -222,11 +222,11 @@ ForLowering::matchAndRewrite(ForOp forOp, PatternRewriter &rewriter) const {
   // The result of the loop operation is the values of the condition block
   // arguments except the induction variable on the last iteration.
   rewriter.replaceOp(forOp, conditionBlock->getArguments().drop_front());
-  return matchSuccess();
+  return success();
 }
 
-PatternMatchResult
-IfLowering::matchAndRewrite(IfOp ifOp, PatternRewriter &rewriter) const {
+LogicalResult IfLowering::matchAndRewrite(IfOp ifOp,
+                                          PatternRewriter &rewriter) const {
   auto loc = ifOp.getLoc();
 
   // Start by splitting the block containing the 'loop.if' into two parts.
@@ -265,10 +265,10 @@ IfLowering::matchAndRewrite(IfOp ifOp, PatternRewriter &rewriter) const {
 
   // Ok, we're done!
   rewriter.eraseOp(ifOp);
-  return matchSuccess();
+  return success();
 }
 
-PatternMatchResult
+LogicalResult
 ParallelLowering::matchAndRewrite(ParallelOp parallelOp,
                                   PatternRewriter &rewriter) const {
   Location loc = parallelOp.getLoc();
@@ -344,7 +344,7 @@ ParallelLowering::matchAndRewrite(ParallelOp parallelOp,
 
   rewriter.replaceOp(parallelOp, loopResults);
 
-  return matchSuccess();
+  return success();
 }
 
 void mlir::populateLoopToStdConversionPatterns(
diff --git a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
index 9ba3f40d24e98..8023226bc3008 100644
--- a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
+++ b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
@@ -497,8 +497,8 @@ namespace {
 struct ParallelToGpuLaunchLowering : public OpRewritePattern<ParallelOp> {
   using OpRewritePattern<ParallelOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(ParallelOp parallelOp,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(ParallelOp parallelOp,
+                                PatternRewriter &rewriter) const override;
 };
 
 struct MappingAnnotation {
@@ -742,7 +742,7 @@ static LogicalResult processParallelLoop(ParallelOp parallelOp,
 /// the actual loop bound. This only works if an static upper bound for the
 /// dynamic loop bound can be defived, currently via analyzing `affine.min`
 /// operations.
-PatternMatchResult
+LogicalResult
 ParallelToGpuLaunchLowering::matchAndRewrite(ParallelOp parallelOp,
                                              PatternRewriter &rewriter) const {
   // Create a launch operation. We start with bound one for all grid/block
@@ -761,7 +761,7 @@ ParallelToGpuLaunchLowering::matchAndRewrite(ParallelOp parallelOp,
   SmallVector<Operation *, 16> worklist;
   if (failed(processParallelLoop(parallelOp, launchOp, cloningMap, worklist,
                                  launchBounds, rewriter)))
-    return matchFailure();
+    return failure();
 
   // Whether we have seen any side-effects. Reset when leaving an inner scope.
   bool seenSideeffects = false;
@@ -778,13 +778,13 @@ ParallelToGpuLaunchLowering::matchAndRewrite(ParallelOp parallelOp,
       // Before entering a nested scope, make sure there have been no
       // sideeffects until now.
       if (seenSideeffects)
-        return matchFailure();
+        return failure();
       // A nested loop.parallel needs insertion of code to compute indices.
       // Insert that now. This will also update the worklist with the loops
       // body.
       if (failed(processParallelLoop(nestedParallel, launchOp, cloningMap,
                                      worklist, launchBounds, rewriter)))
-        return matchFailure();
+        return failure();
     } else if (op == launchOp.getOperation()) {
       // Found our sentinel value. We have finished the operations from one
       // nesting level, pop one level back up.
@@ -802,7 +802,7 @@ ParallelToGpuLaunchLowering::matchAndRewrite(ParallelOp parallelOp,
                          clone->getNumRegions() != 0;
       // If we are no longer in the innermost scope, sideeffects are disallowed.
       if (seenSideeffects && leftNestingScope)
-        return matchFailure();
+        return failure();
     }
   }
 
@@ -812,7 +812,7 @@ ParallelToGpuLaunchLowering::matchAndRewrite(ParallelOp parallelOp,
     launchOp.setOperand(std::get<0>(bound), std::get<1>(bound));
 
   rewriter.eraseOp(parallelOp);
-  return matchSuccess();
+  return success();
 }
 
 void mlir::populateParallelLoopToGPUPatterns(OwningRewritePatternList &patterns,
diff --git a/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp b/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
index c7c479bf67794..250ff3682653a 100644
--- a/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
+++ b/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
@@ -946,7 +946,7 @@ struct FuncOpConversion : public FuncOpConversionBase {
                    bool emitCWrappers)
       : FuncOpConversionBase(dialect, converter), emitWrappers(emitCWrappers) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto funcOp = cast<FuncOp>(op);
@@ -962,7 +962,7 @@ struct FuncOpConversion : public FuncOpConversionBase {
     }
 
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 
 private:
@@ -976,7 +976,7 @@ struct FuncOpConversion : public FuncOpConversionBase {
 struct BarePtrFuncOpConversion : public FuncOpConversionBase {
   using FuncOpConversionBase::FuncOpConversionBase;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto funcOp = cast<FuncOp>(op);
@@ -990,7 +990,7 @@ struct BarePtrFuncOpConversion : public FuncOpConversionBase {
     auto newFuncOp = convertFuncOpToLLVMFuncOp(funcOp, rewriter);
     if (newFuncOp.getBody().empty()) {
       rewriter.eraseOp(op);
-      return matchSuccess();
+      return success();
     }
 
     // Promote bare pointers from MemRef arguments to a MemRef descriptor struct
@@ -1017,7 +1017,7 @@ struct BarePtrFuncOpConversion : public FuncOpConversionBase {
     }
 
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1109,7 +1109,7 @@ struct OneToOneLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
 
   // Convert the type of the result to an LLVM type, pass operands as is,
   // preserve attributes.
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     unsigned numResults = op->getNumResults();
@@ -1119,7 +1119,7 @@ struct OneToOneLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
       packedType =
           this->typeConverter.packFunctionResults(op->getResultTypes());
       if (!packedType)
-        return this->matchFailure();
+        return failure();
     }
 
     auto newOp = rewriter.create<TargetOp>(op->getLoc(), packedType, operands,
@@ -1127,10 +1127,10 @@ struct OneToOneLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
 
     // If the operation produced 0 or 1 result, return them immediately.
     if (numResults == 0)
-      return rewriter.eraseOp(op), this->matchSuccess();
+      return rewriter.eraseOp(op), success();
     if (numResults == 1)
       return rewriter.replaceOp(op, newOp.getOperation()->getResult(0)),
-             this->matchSuccess();
+             success();
 
     // Otherwise, it had been converted to an operation producing a structure.
     // Extract individual results from the structure and return them as list.
@@ -1143,7 +1143,7 @@ struct OneToOneLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
           rewriter.getI64ArrayAttr(i)));
     }
     rewriter.replaceOp(op, results);
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -1207,7 +1207,7 @@ struct NaryOpLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
 
   // Convert the type of the result to an LLVM type, pass operands as is,
   // preserve attributes.
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     ValidateOpCount<SourceOp, OpCount>();
@@ -1221,7 +1221,7 @@ struct NaryOpLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
     // Cannot convert ops if their operands are not of LLVM type.
     for (Value operand : operands) {
       if (!operand || !operand.getType().isa<LLVM::LLVMType>())
-        return this->matchFailure();
+        return failure();
     }
 
     auto llvmArrayTy = operands[0].getType().cast<LLVM::LLVMType>();
@@ -1230,7 +1230,7 @@ struct NaryOpLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
       auto newOp = rewriter.create<TargetOp>(
           op->getLoc(), operands[0].getType(), operands, op->getAttrs());
       rewriter.replaceOp(op, newOp.getResult());
-      return this->matchSuccess();
+      return success();
     }
 
     if (succeeded(HandleMultidimensionalVectors(
@@ -1240,8 +1240,8 @@ struct NaryOpLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
                                                operands, op->getAttrs());
             },
             rewriter)))
-      return this->matchSuccess();
-    return this->matchFailure();
+      return success();
+    return failure();
   }
 };
 
@@ -1381,24 +1381,24 @@ struct AllocOpLowering : public LLVMLegalizationPattern<AllocOp> {
       : LLVMLegalizationPattern<AllocOp>(dialect_, converter),
         useAlloca(useAlloca) {}
 
-  PatternMatchResult match(Operation *op) const override {
+  LogicalResult match(Operation *op) const override {
     MemRefType type = cast<AllocOp>(op).getType();
     if (isSupportedMemRefType(type))
-      return matchSuccess();
+      return success();
 
     int64_t offset;
     SmallVector<int64_t, 4> strides;
     auto successStrides = getStridesAndOffset(type, strides, offset);
     if (failed(successStrides))
-      return matchFailure();
+      return failure();
 
     // Dynamic strides are ok if they can be deduced from dynamic sizes (which
     // is guaranteed when succeeded(successStrides)). Dynamic offset however can
     // never be alloc'ed.
     if (offset == MemRefType::getDynamicStrideOrOffset())
-      return matchFailure();
+      return failure();
 
-    return matchSuccess();
+    return success();
   }
 
   void rewrite(Operation *op, ArrayRef<Value> operands,
@@ -1574,7 +1574,7 @@ struct CallOpInterfaceLowering : public LLVMLegalizationPattern<CallOpType> {
   using Super = CallOpInterfaceLowering<CallOpType>;
   using Base = LLVMLegalizationPattern<CallOpType>;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     OperandAdaptor<CallOpType> transformed(operands);
@@ -1595,7 +1595,7 @@ struct CallOpInterfaceLowering : public LLVMLegalizationPattern<CallOpType> {
     if (numResults != 0) {
       if (!(packedResult =
                 this->typeConverter.packFunctionResults(resultTypes)))
-        return this->matchFailure();
+        return failure();
     }
 
     auto promoted = this->typeConverter.promoteMemRefDescriptors(
@@ -1606,7 +1606,7 @@ struct CallOpInterfaceLowering : public LLVMLegalizationPattern<CallOpType> {
     // If < 2 results, packing did not do anything and we can just return.
     if (numResults < 2) {
       rewriter.replaceOp(op, newOp.getResults());
-      return this->matchSuccess();
+      return success();
     }
 
     // Otherwise, it had been converted to an operation producing a structure.
@@ -1624,7 +1624,7 @@ struct CallOpInterfaceLowering : public LLVMLegalizationPattern<CallOpType> {
     }
     rewriter.replaceOp(op, results);
 
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -1647,11 +1647,11 @@ struct DeallocOpLowering : public LLVMLegalizationPattern<DeallocOp> {
       : LLVMLegalizationPattern<DeallocOp>(dialect_, converter),
         useAlloca(useAlloca) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     if (useAlloca)
-      return rewriter.eraseOp(op), matchSuccess();
+      return rewriter.eraseOp(op), success();
 
     assert(operands.size() == 1 && "dealloc takes one operand");
     OperandAdaptor<DeallocOp> transformed(operands);
@@ -1673,7 +1673,7 @@ struct DeallocOpLowering : public LLVMLegalizationPattern<DeallocOp> {
         memref.allocatedPtr(rewriter, op->getLoc()));
     rewriter.replaceOpWithNewOp<LLVM::CallOp>(
         op, ArrayRef<Type>(), rewriter.getSymbolRefAttr(freeFunc), casted);
-    return matchSuccess();
+    return success();
   }
 
   bool useAlloca;
@@ -1683,7 +1683,7 @@ struct DeallocOpLowering : public LLVMLegalizationPattern<DeallocOp> {
 struct RsqrtOpLowering : public LLVMLegalizationPattern<RsqrtOp> {
   using LLVMLegalizationPattern<RsqrtOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     OperandAdaptor<RsqrtOp> transformed(operands);
@@ -1691,7 +1691,7 @@ struct RsqrtOpLowering : public LLVMLegalizationPattern<RsqrtOp> {
         transformed.operand().getType().dyn_cast<LLVM::LLVMType>();
 
     if (!operandType)
-      return matchFailure();
+      return failure();
 
     auto loc = op->getLoc();
     auto resultType = *op->result_type_begin();
@@ -1709,12 +1709,12 @@ struct RsqrtOpLowering : public LLVMLegalizationPattern<RsqrtOp> {
       }
       auto sqrt = rewriter.create<LLVM::SqrtOp>(loc, transformed.operand());
       rewriter.replaceOpWithNewOp<LLVM::FDivOp>(op, operandType, one, sqrt);
-      return this->matchSuccess();
+      return success();
     }
 
     auto vectorType = resultType.dyn_cast<VectorType>();
     if (!vectorType)
-      return this->matchFailure();
+      return failure();
 
     if (succeeded(HandleMultidimensionalVectors(
             op, operands, typeConverter,
@@ -1732,8 +1732,8 @@ struct RsqrtOpLowering : public LLVMLegalizationPattern<RsqrtOp> {
                                                    sqrt);
             },
             rewriter)))
-      return this->matchSuccess();
-    return this->matchFailure();
+      return success();
+    return failure();
   }
 };
 
@@ -1741,7 +1741,7 @@ struct RsqrtOpLowering : public LLVMLegalizationPattern<RsqrtOp> {
 struct TanhOpLowering : public LLVMLegalizationPattern<TanhOp> {
   using LLVMLegalizationPattern<TanhOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
 
@@ -1753,7 +1753,7 @@ struct TanhOpLowering : public LLVMLegalizationPattern<TanhOp> {
         transformed.operand().getType().dyn_cast<LLVM::LLVMType>();
 
     if (!operandType)
-      return matchFailure();
+      return failure();
 
     std::string functionName;
     if (operandType.isFloatTy())
@@ -1761,7 +1761,7 @@ struct TanhOpLowering : public LLVMLegalizationPattern<TanhOp> {
     else if (operandType.isDoubleTy())
       functionName = "tanh";
     else
-      return matchFailure();
+      return failure();
 
     // Get a reference to the tanh function, inserting it if necessary.
     Operation *tanhFunc =
@@ -1783,14 +1783,14 @@ struct TanhOpLowering : public LLVMLegalizationPattern<TanhOp> {
     rewriter.replaceOpWithNewOp<LLVM::CallOp>(
         op, operandType, rewriter.getSymbolRefAttr(tanhLLVMFunc),
         transformed.operand());
-    return matchSuccess();
+    return success();
   }
 };
 
 struct MemRefCastOpLowering : public LLVMLegalizationPattern<MemRefCastOp> {
   using LLVMLegalizationPattern<MemRefCastOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult match(Operation *op) const override {
+  LogicalResult match(Operation *op) const override {
     auto memRefCastOp = cast<MemRefCastOp>(op);
     Type srcType = memRefCastOp.getOperand().getType();
     Type dstType = memRefCastOp.getType();
@@ -1801,8 +1801,8 @@ struct MemRefCastOpLowering : public LLVMLegalizationPattern<MemRefCastOp> {
       MemRefType targetType = memRefCastOp.getType().cast<MemRefType>();
       return (isSupportedMemRefType(targetType) &&
               isSupportedMemRefType(sourceType))
-                 ? matchSuccess()
-                 : matchFailure();
+                 ? success()
+                 : failure();
     }
 
     // At least one of the operands is unranked type
@@ -1812,8 +1812,8 @@ struct MemRefCastOpLowering : public LLVMLegalizationPattern<MemRefCastOp> {
     // Unranked to unranked cast is disallowed
     return !(srcType.isa<UnrankedMemRefType>() &&
              dstType.isa<UnrankedMemRefType>())
-               ? matchSuccess()
-               : matchFailure();
+               ? success()
+               : failure();
   }
 
   void rewrite(Operation *op, ArrayRef<Value> operands,
@@ -1886,17 +1886,17 @@ struct DialectCastOpLowering
     : public LLVMLegalizationPattern<LLVM::DialectCastOp> {
   using LLVMLegalizationPattern<LLVM::DialectCastOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto castOp = cast<LLVM::DialectCastOp>(op);
     OperandAdaptor<LLVM::DialectCastOp> transformed(operands);
     if (transformed.in().getType() !=
         typeConverter.convertType(castOp.getType())) {
-      return matchFailure();
+      return failure();
     }
     rewriter.replaceOp(op, transformed.in());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1905,7 +1905,7 @@ struct DialectCastOpLowering
 struct DimOpLowering : public LLVMLegalizationPattern<DimOp> {
   using LLVMLegalizationPattern<DimOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto dimOp = cast<DimOp>(op);
@@ -1922,7 +1922,7 @@ struct DimOpLowering : public LLVMLegalizationPattern<DimOp> {
       // Use constant for static size.
       rewriter.replaceOp(
           op, createIndexConstant(rewriter, op->getLoc(), shape[index]));
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1934,10 +1934,9 @@ struct LoadStoreOpLowering : public LLVMLegalizationPattern<Derived> {
   using LLVMLegalizationPattern<Derived>::LLVMLegalizationPattern;
   using Base = LoadStoreOpLowering<Derived>;
 
-  PatternMatchResult match(Operation *op) const override {
+  LogicalResult match(Operation *op) const override {
     MemRefType type = cast<Derived>(op).getMemRefType();
-    return isSupportedMemRefType(type) ? this->matchSuccess()
-                                       : this->matchFailure();
+    return isSupportedMemRefType(type) ? success() : failure();
   }
 
   // Given subscript indices and array sizes in row-major order,
@@ -2010,7 +2009,7 @@ struct LoadStoreOpLowering : public LLVMLegalizationPattern<Derived> {
 struct LoadOpLowering : public LoadStoreOpLowering<LoadOp> {
   using Base::Base;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loadOp = cast<LoadOp>(op);
@@ -2020,7 +2019,7 @@ struct LoadOpLowering : public LoadStoreOpLowering<LoadOp> {
     Value dataPtr = getDataPtr(op->getLoc(), type, transformed.memref(),
                                transformed.indices(), rewriter, getModule());
     rewriter.replaceOpWithNewOp<LLVM::LoadOp>(op, dataPtr);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2029,7 +2028,7 @@ struct LoadOpLowering : public LoadStoreOpLowering<LoadOp> {
 struct StoreOpLowering : public LoadStoreOpLowering<StoreOp> {
   using Base::Base;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto type = cast<StoreOp>(op).getMemRefType();
@@ -2039,7 +2038,7 @@ struct StoreOpLowering : public LoadStoreOpLowering<StoreOp> {
                                transformed.indices(), rewriter, getModule());
     rewriter.replaceOpWithNewOp<LLVM::StoreOp>(op, transformed.value(),
                                                dataPtr);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2048,7 +2047,7 @@ struct StoreOpLowering : public LoadStoreOpLowering<StoreOp> {
 struct PrefetchOpLowering : public LoadStoreOpLowering<PrefetchOp> {
   using Base::Base;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto prefetchOp = cast<PrefetchOp>(op);
@@ -2072,7 +2071,7 @@ struct PrefetchOpLowering : public LoadStoreOpLowering<PrefetchOp> {
 
     rewriter.replaceOpWithNewOp<LLVM::Prefetch>(op, dataPtr, isWrite,
                                                 localityHint, isData);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2083,7 +2082,7 @@ struct PrefetchOpLowering : public LoadStoreOpLowering<PrefetchOp> {
 struct IndexCastOpLowering : public LLVMLegalizationPattern<IndexCastOp> {
   using LLVMLegalizationPattern<IndexCastOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     IndexCastOpOperandAdaptor transformed(operands);
@@ -2104,7 +2103,7 @@ struct IndexCastOpLowering : public LLVMLegalizationPattern<IndexCastOp> {
     else
       rewriter.replaceOpWithNewOp<LLVM::SExtOp>(op, targetType,
                                                 transformed.in());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2118,7 +2117,7 @@ static LLVMPredType convertCmpPredicate(StdPredType pred) {
 struct CmpIOpLowering : public LLVMLegalizationPattern<CmpIOp> {
   using LLVMLegalizationPattern<CmpIOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto cmpiOp = cast<CmpIOp>(op);
@@ -2130,14 +2129,14 @@ struct CmpIOpLowering : public LLVMLegalizationPattern<CmpIOp> {
             convertCmpPredicate<LLVM::ICmpPredicate>(cmpiOp.getPredicate()))),
         transformed.lhs(), transformed.rhs());
 
-    return matchSuccess();
+    return success();
   }
 };
 
 struct CmpFOpLowering : public LLVMLegalizationPattern<CmpFOp> {
   using LLVMLegalizationPattern<CmpFOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto cmpfOp = cast<CmpFOp>(op);
@@ -2149,7 +2148,7 @@ struct CmpFOpLowering : public LLVMLegalizationPattern<CmpFOp> {
             convertCmpPredicate<LLVM::FCmpPredicate>(cmpfOp.getPredicate()))),
         transformed.lhs(), transformed.rhs());
 
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2189,12 +2188,12 @@ struct OneToOneLLVMTerminatorLowering
   using LLVMLegalizationPattern<SourceOp>::LLVMLegalizationPattern;
   using Super = OneToOneLLVMTerminatorLowering<SourceOp, TargetOp>;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<TargetOp>(op, operands, op->getSuccessors(),
                                           op->getAttrs());
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -2207,7 +2206,7 @@ struct OneToOneLLVMTerminatorLowering
 struct ReturnOpLowering : public LLVMLegalizationPattern<ReturnOp> {
   using LLVMLegalizationPattern<ReturnOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     unsigned numArguments = op->getNumOperands();
@@ -2216,12 +2215,12 @@ struct ReturnOpLowering : public LLVMLegalizationPattern<ReturnOp> {
     if (numArguments == 0) {
       rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(
           op, ArrayRef<Type>(), ArrayRef<Value>(), op->getAttrs());
-      return matchSuccess();
+      return success();
     }
     if (numArguments == 1) {
       rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(
           op, ArrayRef<Type>(), operands.front(), op->getAttrs());
-      return matchSuccess();
+      return success();
     }
 
     // Otherwise, we need to pack the arguments into an LLVM struct type before
@@ -2237,7 +2236,7 @@ struct ReturnOpLowering : public LLVMLegalizationPattern<ReturnOp> {
     }
     rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(op, ArrayRef<Type>(), packed,
                                                 op->getAttrs());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2256,13 +2255,13 @@ struct CondBranchOpLowering
 struct SplatOpLowering : public LLVMLegalizationPattern<SplatOp> {
   using LLVMLegalizationPattern<SplatOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto splatOp = cast<SplatOp>(op);
     VectorType resultType = splatOp.getType().dyn_cast<VectorType>();
     if (!resultType || resultType.getRank() != 1)
-      return matchFailure();
+      return failure();
 
     // First insert it into an undef vector so we can shuffle it.
     auto vectorType = typeConverter.convertType(splatOp.getType());
@@ -2280,7 +2279,7 @@ struct SplatOpLowering : public LLVMLegalizationPattern<SplatOp> {
     // Shuffle the value across the desired number of elements.
     ArrayAttr zeroAttrs = rewriter.getI32ArrayAttr(zeroValues);
     rewriter.replaceOpWithNewOp<LLVM::ShuffleVectorOp>(op, v, undef, zeroAttrs);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2290,14 +2289,14 @@ struct SplatOpLowering : public LLVMLegalizationPattern<SplatOp> {
 struct SplatNdOpLowering : public LLVMLegalizationPattern<SplatOp> {
   using LLVMLegalizationPattern<SplatOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto splatOp = cast<SplatOp>(op);
     OperandAdaptor<SplatOp> adaptor(operands);
     VectorType resultType = splatOp.getType().dyn_cast<VectorType>();
     if (!resultType || resultType.getRank() == 1)
-      return matchFailure();
+      return failure();
 
     // First insert it into an undef vector so we can shuffle it.
     auto loc = op->getLoc();
@@ -2305,7 +2304,7 @@ struct SplatNdOpLowering : public LLVMLegalizationPattern<SplatOp> {
     auto llvmArrayTy = vectorTypeInfo.llvmArrayTy;
     auto llvmVectorTy = vectorTypeInfo.llvmVectorTy;
     if (!llvmArrayTy || !llvmVectorTy)
-      return matchFailure();
+      return failure();
 
     // Construct returned value.
     Value desc = rewriter.create<LLVM::UndefOp>(loc, llvmArrayTy);
@@ -2332,7 +2331,7 @@ struct SplatNdOpLowering : public LLVMLegalizationPattern<SplatOp> {
                                                   position);
     });
     rewriter.replaceOp(op, desc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2344,7 +2343,7 @@ struct SplatNdOpLowering : public LLVMLegalizationPattern<SplatOp> {
 struct SubViewOpLowering : public LLVMLegalizationPattern<SubViewOp> {
   using LLVMLegalizationPattern<SubViewOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -2376,7 +2375,7 @@ struct SubViewOpLowering : public LLVMLegalizationPattern<SubViewOp> {
     auto targetDescTy = typeConverter.convertType(viewMemRefType)
                             .dyn_cast_or_null<LLVM::LLVMType>();
     if (!sourceElementTy || !targetDescTy)
-      return matchFailure();
+      return failure();
 
     // Currently, only rank > 0 and full or no operands are supported. Fail to
     // convert otherwise.
@@ -2385,22 +2384,22 @@ struct SubViewOpLowering : public LLVMLegalizationPattern<SubViewOp> {
         (!dynamicOffsets.empty() && rank != dynamicOffsets.size()) ||
         (!dynamicSizes.empty() && rank != dynamicSizes.size()) ||
         (!dynamicStrides.empty() && rank != dynamicStrides.size()))
-      return matchFailure();
+      return failure();
 
     int64_t offset;
     SmallVector<int64_t, 4> strides;
     auto successStrides = getStridesAndOffset(viewMemRefType, strides, offset);
     if (failed(successStrides))
-      return matchFailure();
+      return failure();
 
     // Fail to convert if neither a dynamic nor static offset is available.
     if (dynamicOffsets.empty() &&
         offset == MemRefType::getDynamicStrideOrOffset())
-      return matchFailure();
+      return failure();
 
     // Create the descriptor.
     if (!operands.front().getType().isa<LLVM::LLVMType>())
-      return matchFailure();
+      return failure();
     MemRefDescriptor sourceMemRef(operands.front());
     auto targetMemRef = MemRefDescriptor::undef(rewriter, loc, targetDescTy);
 
@@ -2460,7 +2459,7 @@ struct SubViewOpLowering : public LLVMLegalizationPattern<SubViewOp> {
     }
 
     rewriter.replaceOp(op, {targetMemRef});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2505,7 +2504,7 @@ struct ViewOpLowering : public LLVMLegalizationPattern<ViewOp> {
     return createIndexConstant(rewriter, loc, 1);
   }
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -2520,14 +2519,13 @@ struct ViewOpLowering : public LLVMLegalizationPattern<ViewOp> {
         typeConverter.convertType(viewMemRefType).dyn_cast<LLVM::LLVMType>();
     if (!targetDescTy)
       return op->emitWarning("Target descriptor type not converted to LLVM"),
-             matchFailure();
+             failure();
 
     int64_t offset;
     SmallVector<int64_t, 4> strides;
     auto successStrides = getStridesAndOffset(viewMemRefType, strides, offset);
     if (failed(successStrides))
-      return op->emitWarning("cannot cast to non-strided shape"),
-             matchFailure();
+      return op->emitWarning("cannot cast to non-strided shape"), failure();
 
     // Create the descriptor.
     MemRefDescriptor sourceMemRef(adaptor.source());
@@ -2560,12 +2558,11 @@ struct ViewOpLowering : public LLVMLegalizationPattern<ViewOp> {
 
     // Early exit for 0-D corner case.
     if (viewMemRefType.getRank() == 0)
-      return rewriter.replaceOp(op, {targetMemRef}), matchSuccess();
+      return rewriter.replaceOp(op, {targetMemRef}), success();
 
     // Fields 4 and 5: Update sizes and strides.
     if (strides.back() != 1)
-      return op->emitWarning("cannot cast to non-contiguous shape"),
-             matchFailure();
+      return op->emitWarning("cannot cast to non-contiguous shape"), failure();
     Value stride = nullptr, nextSize = nullptr;
     // Drop the dynamic stride from the operand list, if present.
     ArrayRef<Value> sizeOperands(sizeAndOffsetOperands);
@@ -2583,7 +2580,7 @@ struct ViewOpLowering : public LLVMLegalizationPattern<ViewOp> {
     }
 
     rewriter.replaceOp(op, {targetMemRef});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2591,7 +2588,7 @@ struct AssumeAlignmentOpLowering
     : public LLVMLegalizationPattern<AssumeAlignmentOp> {
   using LLVMLegalizationPattern<AssumeAlignmentOp>::LLVMLegalizationPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     OperandAdaptor<AssumeAlignmentOp> transformed(operands);
@@ -2622,7 +2619,7 @@ struct AssumeAlignmentOpLowering
             rewriter.create<LLVM::AndOp>(op->getLoc(), ptrValue, mask), zero));
 
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2657,13 +2654,13 @@ namespace {
 struct AtomicRMWOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
   using Base::Base;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto atomicOp = cast<AtomicRMWOp>(op);
     auto maybeKind = matchSimpleAtomicOp(atomicOp);
     if (!maybeKind)
-      return matchFailure();
+      return failure();
     OperandAdaptor<AtomicRMWOp> adaptor(operands);
     auto resultType = adaptor.value().getType();
     auto memRefType = atomicOp.getMemRefType();
@@ -2672,7 +2669,7 @@ struct AtomicRMWOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
     rewriter.replaceOpWithNewOp<LLVM::AtomicRMWOp>(
         op, resultType, *maybeKind, dataPtr, adaptor.value(),
         LLVM::AtomicOrdering::acq_rel);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2706,13 +2703,13 @@ struct AtomicRMWOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
 struct AtomicCmpXchgOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
   using Base::Base;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto atomicOp = cast<AtomicRMWOp>(op);
     auto maybeKind = matchSimpleAtomicOp(atomicOp);
     if (maybeKind)
-      return matchFailure();
+      return failure();
 
     LLVM::FCmpPredicate predicate;
     switch (atomicOp.kind()) {
@@ -2723,7 +2720,7 @@ struct AtomicCmpXchgOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
       predicate = LLVM::FCmpPredicate::olt;
       break;
     default:
-      return matchFailure();
+      return failure();
     }
 
     OperandAdaptor<AtomicRMWOp> adaptor(operands);
@@ -2779,55 +2776,12 @@ struct AtomicCmpXchgOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
     // The 'result' of the atomic_rmw op is the newly loaded value.
     rewriter.replaceOp(op, {newLoaded});
 
-    return matchSuccess();
+    return success();
   }
 };
 
 } // namespace
 
-static void ensureDistinctSuccessors(Block &bb) {
-  Operation *terminator = bb.getTerminator();
-  if (terminator->getNumSuccessors() < 2)
-    return;
-
-  // Find repeated successors with arguments.
-  llvm::SmallDenseMap<Block *, SmallVector<int, 4>> successorPositions;
-  for (int i = 0, e = terminator->getNumSuccessors(); i < e; ++i) {
-    Block *successor = terminator->getSuccessor(i);
-    // Blocks with no arguments are safe even if they appear multiple times
-    // because they don't need PHI nodes.
-    if (successor->getNumArguments() == 0)
-      continue;
-    successorPositions[successor].push_back(i);
-  }
-
-  // If a successor appears for the second or more time in the terminator,
-  // create a new dummy block that unconditionally branches to the original
-  // destination, and retarget the terminator to branch to this new block.
-  // There is no need to pass arguments to the dummy block because it will be
-  // dominated by the original block and can therefore use any values defined in
-  // the original block.
-  OpBuilder builder(terminator->getContext());
-  for (const auto &successor : successorPositions) {
-    // Start from the second occurrence of a block in the successor list.
-    for (int position : llvm::drop_begin(successor.second, 1)) {
-      Block *dummyBlock = builder.createBlock(bb.getParent());
-      terminator->setSuccessor(dummyBlock, position);
-      dummyBlock->addArguments(successor.first->getArgumentTypes());
-      builder.create<BranchOp>(terminator->getLoc(), successor.first,
-                               dummyBlock->getArguments());
-    }
-  }
-}
-
-void mlir::LLVM::ensureDistinctSuccessors(ModuleOp m) {
-  for (auto f : m.getOps<FuncOp>()) {
-    for (auto &bb : f.getBlocks()) {
-      ::ensureDistinctSuccessors(bb);
-    }
-  }
-}
-
 /// Collect a set of patterns to convert from the Standard dialect to LLVM.
 void mlir::populateStdToLLVMNonMemoryConversionPatterns(
     LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
@@ -3024,7 +2978,6 @@ struct LLVMLoweringPass : public ModulePass<LLVMLoweringPass> {
     }
 
     ModuleOp m = getModule();
-    LLVM::ensureDistinctSuccessors(m);
 
     LLVMTypeConverterCustomization customs;
     customs.funcArgConverter = useBarePtrCallConv ? barePtrFuncArgTypeConverter
diff --git a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp b/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
index a1a599b0ab084..310dcd8a86bdb 100644
--- a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
+++ b/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
@@ -31,7 +31,7 @@ class ConstantCompositeOpConversion final : public SPIRVOpLowering<ConstantOp> {
 public:
   using SPIRVOpLowering<ConstantOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(ConstantOp constCompositeOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -45,7 +45,7 @@ class ConstantIndexOpConversion final : public SPIRVOpLowering<ConstantOp> {
 public:
   using SPIRVOpLowering<ConstantOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(ConstantOp constIndexOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -55,7 +55,7 @@ class CmpFOpConversion final : public SPIRVOpLowering<CmpFOp> {
 public:
   using SPIRVOpLowering<CmpFOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(CmpFOp cmpFOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -65,7 +65,7 @@ class CmpIOpConversion final : public SPIRVOpLowering<CmpIOp> {
 public:
   using SPIRVOpLowering<CmpIOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(CmpIOp cmpIOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -81,14 +81,14 @@ class IntegerOpConversion final : public SPIRVOpLowering<StdOp> {
 public:
   using SPIRVOpLowering<StdOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(StdOp operation, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto resultType =
         this->typeConverter.convertType(operation.getResult().getType());
     rewriter.template replaceOpWithNewOp<SPIRVOp>(
         operation, resultType, operands, ArrayRef<NamedAttribute>());
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -100,7 +100,7 @@ class LoadOpConversion final : public SPIRVOpLowering<LoadOp> {
 public:
   using SPIRVOpLowering<LoadOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(LoadOp loadOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -111,7 +111,7 @@ class ReturnOpConversion final : public SPIRVOpLowering<ReturnOp> {
 public:
   using SPIRVOpLowering<ReturnOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(ReturnOp returnOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -121,7 +121,7 @@ class ReturnOpConversion final : public SPIRVOpLowering<ReturnOp> {
 class SelectOpConversion final : public SPIRVOpLowering<SelectOp> {
 public:
   using SPIRVOpLowering<SelectOp>::SPIRVOpLowering;
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(SelectOp op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -134,7 +134,7 @@ class StoreOpConversion final : public SPIRVOpLowering<StoreOp> {
 public:
   using SPIRVOpLowering<StoreOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(StoreOp storeOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -145,22 +145,22 @@ class StoreOpConversion final : public SPIRVOpLowering<StoreOp> {
 // ConstantOp with composite type.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult ConstantCompositeOpConversion::matchAndRewrite(
+LogicalResult ConstantCompositeOpConversion::matchAndRewrite(
     ConstantOp constCompositeOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   auto compositeType =
       constCompositeOp.getResult().getType().dyn_cast<RankedTensorType>();
   if (!compositeType)
-    return matchFailure();
+    return failure();
 
   auto spirvCompositeType = typeConverter.convertType(compositeType);
   if (!spirvCompositeType)
-    return matchFailure();
+    return failure();
 
   auto linearizedElements =
       constCompositeOp.value().dyn_cast<DenseElementsAttr>();
   if (!linearizedElements)
-    return matchFailure();
+    return failure();
 
   // If composite type has rank greater than one, then perform linearization.
   if (compositeType.getRank() > 1) {
@@ -171,24 +171,24 @@ PatternMatchResult ConstantCompositeOpConversion::matchAndRewrite(
 
   rewriter.replaceOpWithNewOp<spirv::ConstantOp>(
       constCompositeOp, spirvCompositeType, linearizedElements);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // ConstantOp with index type.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult ConstantIndexOpConversion::matchAndRewrite(
+LogicalResult ConstantIndexOpConversion::matchAndRewrite(
     ConstantOp constIndexOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   if (!constIndexOp.getResult().getType().isa<IndexType>()) {
-    return matchFailure();
+    return failure();
   }
   // The attribute has index type which is not directly supported in
   // SPIR-V. Get the integer value and create a new IntegerAttr.
   auto constAttr = constIndexOp.value().dyn_cast<IntegerAttr>();
   if (!constAttr) {
-    return matchFailure();
+    return failure();
   }
 
   // Use the bitwidth set in the value attribute to decide the result type
@@ -197,7 +197,7 @@ PatternMatchResult ConstantIndexOpConversion::matchAndRewrite(
   auto constVal = constAttr.getValue();
   auto constValType = constAttr.getType().dyn_cast<IndexType>();
   if (!constValType) {
-    return matchFailure();
+    return failure();
   }
   auto spirvConstType =
       typeConverter.convertType(constIndexOp.getResult().getType());
@@ -205,14 +205,14 @@ PatternMatchResult ConstantIndexOpConversion::matchAndRewrite(
       rewriter.getIntegerAttr(spirvConstType, constAttr.getInt());
   rewriter.replaceOpWithNewOp<spirv::ConstantOp>(constIndexOp, spirvConstType,
                                                  spirvConstVal);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // CmpFOp
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 CmpFOpConversion::matchAndRewrite(CmpFOp cmpFOp, ArrayRef<Value> operands,
                                   ConversionPatternRewriter &rewriter) const {
   CmpFOpOperandAdaptor cmpFOpOperands(operands);
@@ -223,7 +223,7 @@ CmpFOpConversion::matchAndRewrite(CmpFOp cmpFOp, ArrayRef<Value> operands,
     rewriter.replaceOpWithNewOp<spirvOp>(cmpFOp, cmpFOp.getResult().getType(), \
                                          cmpFOpOperands.lhs(),                 \
                                          cmpFOpOperands.rhs());                \
-    return matchSuccess();
+    return success();
 
     // Ordered.
     DISPATCH(CmpFPredicate::OEQ, spirv::FOrdEqualOp);
@@ -245,14 +245,14 @@ CmpFOpConversion::matchAndRewrite(CmpFOp cmpFOp, ArrayRef<Value> operands,
   default:
     break;
   }
-  return matchFailure();
+  return failure();
 }
 
 //===----------------------------------------------------------------------===//
 // CmpIOp
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 CmpIOpConversion::matchAndRewrite(CmpIOp cmpIOp, ArrayRef<Value> operands,
                                   ConversionPatternRewriter &rewriter) const {
   CmpIOpOperandAdaptor cmpIOpOperands(operands);
@@ -263,7 +263,7 @@ CmpIOpConversion::matchAndRewrite(CmpIOp cmpIOp, ArrayRef<Value> operands,
     rewriter.replaceOpWithNewOp<spirvOp>(cmpIOp, cmpIOp.getResult().getType(), \
                                          cmpIOpOperands.lhs(),                 \
                                          cmpIOpOperands.rhs());                \
-    return matchSuccess();
+    return success();
 
     DISPATCH(CmpIPredicate::eq, spirv::IEqualOp);
     DISPATCH(CmpIPredicate::ne, spirv::INotEqualOp);
@@ -278,14 +278,14 @@ CmpIOpConversion::matchAndRewrite(CmpIOp cmpIOp, ArrayRef<Value> operands,
 
 #undef DISPATCH
   }
-  return matchFailure();
+  return failure();
 }
 
 //===----------------------------------------------------------------------===//
 // LoadOp
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 LoadOpConversion::matchAndRewrite(LoadOp loadOp, ArrayRef<Value> operands,
                                   ConversionPatternRewriter &rewriter) const {
   LoadOpOperandAdaptor loadOperands(operands);
@@ -293,42 +293,42 @@ LoadOpConversion::matchAndRewrite(LoadOp loadOp, ArrayRef<Value> operands,
       typeConverter, loadOp.memref().getType().cast<MemRefType>(),
       loadOperands.memref(), loadOperands.indices(), loadOp.getLoc(), rewriter);
   rewriter.replaceOpWithNewOp<spirv::LoadOp>(loadOp, loadPtr);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // ReturnOp
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 ReturnOpConversion::matchAndRewrite(ReturnOp returnOp, ArrayRef<Value> operands,
                                     ConversionPatternRewriter &rewriter) const {
   if (returnOp.getNumOperands()) {
-    return matchFailure();
+    return failure();
   }
   rewriter.replaceOpWithNewOp<spirv::ReturnOp>(returnOp);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // SelectOp
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 SelectOpConversion::matchAndRewrite(SelectOp op, ArrayRef<Value> operands,
                                     ConversionPatternRewriter &rewriter) const {
   SelectOpOperandAdaptor selectOperands(operands);
   rewriter.replaceOpWithNewOp<spirv::SelectOp>(op, selectOperands.condition(),
                                                selectOperands.true_value(),
                                                selectOperands.false_value());
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // StoreOp
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 StoreOpConversion::matchAndRewrite(StoreOp storeOp, ArrayRef<Value> operands,
                                    ConversionPatternRewriter &rewriter) const {
   StoreOpOperandAdaptor storeOperands(operands);
@@ -338,7 +338,7 @@ StoreOpConversion::matchAndRewrite(StoreOp storeOp, ArrayRef<Value> operands,
       rewriter);
   rewriter.replaceOpWithNewOp<spirv::StoreOp>(storeOp, storePtr,
                                               storeOperands.value());
-  return matchSuccess();
+  return success();
 }
 
 namespace {
diff --git a/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp b/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
index efa7bb0306f8e..3af01e025801d 100644
--- a/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
+++ b/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
@@ -26,8 +26,8 @@ class LoadOpOfSubViewFolder final : public OpRewritePattern<LoadOp> {
 public:
   using OpRewritePattern<LoadOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(LoadOp loadOp,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(LoadOp loadOp,
+                                PatternRewriter &rewriter) const override;
 };
 
 /// Merges subview operation with store operation.
@@ -35,8 +35,8 @@ class StoreOpOfSubViewFolder final : public OpRewritePattern<StoreOp> {
 public:
   using OpRewritePattern<StoreOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(StoreOp storeOp,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(StoreOp storeOp,
+                                PatternRewriter &rewriter) const override;
 };
 } // namespace
 
@@ -107,43 +107,43 @@ resolveSourceIndices(Location loc, PatternRewriter &rewriter,
 // Folding SubViewOp and LoadOp.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 LoadOpOfSubViewFolder::matchAndRewrite(LoadOp loadOp,
                                        PatternRewriter &rewriter) const {
   auto subViewOp = dyn_cast_or_null<SubViewOp>(loadOp.memref().getDefiningOp());
   if (!subViewOp) {
-    return matchFailure();
+    return failure();
   }
   SmallVector<Value, 4> sourceIndices;
   if (failed(resolveSourceIndices(loadOp.getLoc(), rewriter, subViewOp,
                                   loadOp.indices(), sourceIndices)))
-    return matchFailure();
+    return failure();
 
   rewriter.replaceOpWithNewOp<LoadOp>(loadOp, subViewOp.source(),
                                       sourceIndices);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
 // Folding SubViewOp and StoreOp.
 //===----------------------------------------------------------------------===//
 
-PatternMatchResult
+LogicalResult
 StoreOpOfSubViewFolder::matchAndRewrite(StoreOp storeOp,
                                         PatternRewriter &rewriter) const {
   auto subViewOp =
       dyn_cast_or_null<SubViewOp>(storeOp.memref().getDefiningOp());
   if (!subViewOp) {
-    return matchFailure();
+    return failure();
   }
   SmallVector<Value, 4> sourceIndices;
   if (failed(resolveSourceIndices(storeOp.getLoc(), rewriter, subViewOp,
                                   storeOp.indices(), sourceIndices)))
-    return matchFailure();
+    return failure();
 
   rewriter.replaceOpWithNewOp<StoreOp>(storeOp, storeOp.value(),
                                        subViewOp.source(), sourceIndices);
-  return matchSuccess();
+  return success();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt b/mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt
index 0da51e850cc17..734af0b96a39d 100644
--- a/mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt
+++ b/mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt
@@ -7,7 +7,7 @@ add_mlir_conversion_library(MLIRVectorToLLVM
 set(LIBS
   MLIRLLVMIR
   MLIRStandardToLLVM
-  MLIRVectorOps
+  MLIRVector
   MLIRTransforms
   LLVMCore
   LLVMSupport
diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
index d295870d09ab3..2b3020d046a2f 100644
--- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
@@ -12,7 +12,7 @@
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/MLIRContext.h"
@@ -133,13 +133,13 @@ class VectorBroadcastOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::BroadcastOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto broadcastOp = cast<vector::BroadcastOp>(op);
     VectorType dstVectorType = broadcastOp.getVectorType();
     if (typeConverter.convertType(dstVectorType) == nullptr)
-      return matchFailure();
+      return failure();
     // Rewrite when the full vector type can be lowered (which
     // implies all 'reduced' types can be lowered too).
     auto adaptor = vector::BroadcastOpOperandAdaptor(operands);
@@ -149,7 +149,7 @@ class VectorBroadcastOpConversion : public ConvertToLLVMPattern {
         op, expandRanks(adaptor.source(), // source value to be expanded
                         op->getLoc(),     // location of original broadcast
                         srcVectorType, dstVectorType, rewriter));
-    return matchSuccess();
+    return success();
   }
 
 private:
@@ -284,7 +284,7 @@ class VectorMatmulOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::MatmulOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto matmulOp = cast<vector::MatmulOp>(op);
@@ -293,7 +293,7 @@ class VectorMatmulOpConversion : public ConvertToLLVMPattern {
         op, typeConverter.convertType(matmulOp.res().getType()), adaptor.lhs(),
         adaptor.rhs(), matmulOp.lhs_rows(), matmulOp.lhs_columns(),
         matmulOp.rhs_columns());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -304,7 +304,7 @@ class VectorReductionOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::ReductionOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto reductionOp = cast<vector::ReductionOp>(op);
@@ -335,8 +335,8 @@ class VectorReductionOpConversion : public ConvertToLLVMPattern {
         rewriter.replaceOpWithNewOp<LLVM::experimental_vector_reduce_xor>(
             op, llvmType, operands[0]);
       else
-        return matchFailure();
-      return matchSuccess();
+        return failure();
+      return success();
 
     } else if (eltType.isF32() || eltType.isF64()) {
       // Floating-point reductions: add/mul/min/max
@@ -364,10 +364,10 @@ class VectorReductionOpConversion : public ConvertToLLVMPattern {
         rewriter.replaceOpWithNewOp<LLVM::experimental_vector_reduce_fmax>(
             op, llvmType, operands[0]);
       else
-        return matchFailure();
-      return matchSuccess();
+        return failure();
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 };
 
@@ -378,7 +378,7 @@ class VectorShuffleOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::ShuffleOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -392,7 +392,7 @@ class VectorShuffleOpConversion : public ConvertToLLVMPattern {
 
     // Bail if result type cannot be lowered.
     if (!llvmType)
-      return matchFailure();
+      return failure();
 
     // Get rank and dimension sizes.
     int64_t rank = vectorType.getRank();
@@ -406,7 +406,7 @@ class VectorShuffleOpConversion : public ConvertToLLVMPattern {
       Value shuffle = rewriter.create<LLVM::ShuffleVectorOp>(
           loc, adaptor.v1(), adaptor.v2(), maskArrayAttr);
       rewriter.replaceOp(op, shuffle);
-      return matchSuccess();
+      return success();
     }
 
     // For all other cases, insert the individual values individually.
@@ -425,7 +425,7 @@ class VectorShuffleOpConversion : public ConvertToLLVMPattern {
                          llvmType, rank, insPos++);
     }
     rewriter.replaceOp(op, insert);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -436,7 +436,7 @@ class VectorExtractElementOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::ExtractElementOp::getOperationName(),
                              context, typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto adaptor = vector::ExtractElementOpOperandAdaptor(operands);
@@ -446,11 +446,11 @@ class VectorExtractElementOpConversion : public ConvertToLLVMPattern {
 
     // Bail if result type cannot be lowered.
     if (!llvmType)
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOpWithNewOp<LLVM::ExtractElementOp>(
         op, llvmType, adaptor.vector(), adaptor.position());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -461,7 +461,7 @@ class VectorExtractOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::ExtractOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -474,14 +474,14 @@ class VectorExtractOpConversion : public ConvertToLLVMPattern {
 
     // Bail if result type cannot be lowered.
     if (!llvmResultType)
-      return matchFailure();
+      return failure();
 
     // One-shot extraction of vector from array (only requires extractvalue).
     if (resultType.isa<VectorType>()) {
       Value extracted = rewriter.create<LLVM::ExtractValueOp>(
           loc, llvmResultType, adaptor.vector(), positionArrayAttr);
       rewriter.replaceOp(op, extracted);
-      return matchSuccess();
+      return success();
     }
 
     // Potential extraction of 1-D vector from array.
@@ -505,7 +505,7 @@ class VectorExtractOpConversion : public ConvertToLLVMPattern {
         rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant);
     rewriter.replaceOp(op, extracted);
 
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -530,17 +530,17 @@ class VectorFMAOp1DConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::FMAOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto adaptor = vector::FMAOpOperandAdaptor(operands);
     vector::FMAOp fmaOp = cast<vector::FMAOp>(op);
     VectorType vType = fmaOp.getVectorType();
     if (vType.getRank() != 1)
-      return matchFailure();
+      return failure();
     rewriter.replaceOpWithNewOp<LLVM::FMAOp>(op, adaptor.lhs(), adaptor.rhs(),
                                              adaptor.acc());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -551,7 +551,7 @@ class VectorInsertElementOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::InsertElementOp::getOperationName(),
                              context, typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto adaptor = vector::InsertElementOpOperandAdaptor(operands);
@@ -561,11 +561,11 @@ class VectorInsertElementOpConversion : public ConvertToLLVMPattern {
 
     // Bail if result type cannot be lowered.
     if (!llvmType)
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOpWithNewOp<LLVM::InsertElementOp>(
         op, llvmType, adaptor.dest(), adaptor.source(), adaptor.position());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -576,7 +576,7 @@ class VectorInsertOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::InsertOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -589,7 +589,7 @@ class VectorInsertOpConversion : public ConvertToLLVMPattern {
 
     // Bail if result type cannot be lowered.
     if (!llvmResultType)
-      return matchFailure();
+      return failure();
 
     // One-shot insertion of a vector into an array (only requires insertvalue).
     if (sourceType.isa<VectorType>()) {
@@ -597,7 +597,7 @@ class VectorInsertOpConversion : public ConvertToLLVMPattern {
           loc, llvmResultType, adaptor.dest(), adaptor.source(),
           positionArrayAttr);
       rewriter.replaceOp(op, inserted);
-      return matchSuccess();
+      return success();
     }
 
     // Potential extraction of 1-D vector from array.
@@ -632,7 +632,7 @@ class VectorInsertOpConversion : public ConvertToLLVMPattern {
     }
 
     rewriter.replaceOp(op, inserted);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -661,11 +661,11 @@ class VectorFMAOpNDRewritePattern : public OpRewritePattern<FMAOp> {
 public:
   using OpRewritePattern<FMAOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(FMAOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(FMAOp op,
+                                PatternRewriter &rewriter) const override {
     auto vType = op.getVectorType();
     if (vType.getRank() < 2)
-      return matchFailure();
+      return failure();
 
     auto loc = op.getLoc();
     auto elemType = vType.getElementType();
@@ -680,7 +680,7 @@ class VectorFMAOpNDRewritePattern : public OpRewritePattern<FMAOp> {
       desc = rewriter.create<InsertOp>(loc, fma, desc, i);
     }
     rewriter.replaceOp(op, desc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -704,19 +704,19 @@ class VectorInsertStridedSliceOpDifferentRankRewritePattern
 public:
   using OpRewritePattern<InsertStridedSliceOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(InsertStridedSliceOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(InsertStridedSliceOp op,
+                                PatternRewriter &rewriter) const override {
     auto srcType = op.getSourceVectorType();
     auto dstType = op.getDestVectorType();
 
     if (op.offsets().getValue().empty())
-      return matchFailure();
+      return failure();
 
     auto loc = op.getLoc();
     int64_t rankDiff = dstType.getRank() - srcType.getRank();
     assert(rankDiff >= 0);
     if (rankDiff == 0)
-      return matchFailure();
+      return failure();
 
     int64_t rankRest = dstType.getRank() - rankDiff;
     // Extract / insert the subvector of matching rank and InsertStridedSlice
@@ -735,7 +735,7 @@ class VectorInsertStridedSliceOpDifferentRankRewritePattern
         op, stridedSliceInnerOp.getResult(), op.dest(),
         getI64SubArray(op.offsets(), /*dropFront=*/0,
                        /*dropFront=*/rankRest));
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -753,22 +753,22 @@ class VectorInsertStridedSliceOpSameRankRewritePattern
 public:
   using OpRewritePattern<InsertStridedSliceOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(InsertStridedSliceOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(InsertStridedSliceOp op,
+                                PatternRewriter &rewriter) const override {
     auto srcType = op.getSourceVectorType();
     auto dstType = op.getDestVectorType();
 
     if (op.offsets().getValue().empty())
-      return matchFailure();
+      return failure();
 
     int64_t rankDiff = dstType.getRank() - srcType.getRank();
     assert(rankDiff >= 0);
     if (rankDiff != 0)
-      return matchFailure();
+      return failure();
 
     if (srcType == dstType) {
       rewriter.replaceOp(op, op.source());
-      return matchSuccess();
+      return success();
     }
 
     int64_t offset =
@@ -805,7 +805,7 @@ class VectorInsertStridedSliceOpSameRankRewritePattern
         // multiple times.
         auto success = matchAndRewrite(insertStridedSliceOp, rewriter);
         (void)success;
-        assert(success && "Unexpected failure");
+        assert(succeeded(success) && "Unexpected failure");
         extractedSource = insertStridedSliceOp;
       }
       // 4. Insert the extractedSource into the res vector.
@@ -813,7 +813,7 @@ class VectorInsertStridedSliceOpSameRankRewritePattern
     }
 
     rewriter.replaceOp(op, res);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -824,7 +824,7 @@ class VectorTypeCastOpConversion : public ConvertToLLVMPattern {
       : ConvertToLLVMPattern(vector::TypeCastOp::getOperationName(), context,
                              typeConverter) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto loc = op->getLoc();
@@ -837,18 +837,18 @@ class VectorTypeCastOpConversion : public ConvertToLLVMPattern {
     // Only static shape casts supported atm.
     if (!sourceMemRefType.hasStaticShape() ||
         !targetMemRefType.hasStaticShape())
-      return matchFailure();
+      return failure();
 
     auto llvmSourceDescriptorTy =
         operands[0].getType().dyn_cast<LLVM::LLVMType>();
     if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy())
-      return matchFailure();
+      return failure();
     MemRefDescriptor sourceMemRef(operands[0]);
 
     auto llvmTargetDescriptorTy = typeConverter.convertType(targetMemRefType)
                                       .dyn_cast_or_null<LLVM::LLVMType>();
     if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy())
-      return matchFailure();
+      return failure();
 
     int64_t offset;
     SmallVector<int64_t, 4> strides;
@@ -866,7 +866,7 @@ class VectorTypeCastOpConversion : public ConvertToLLVMPattern {
     }
     // Only contiguous source tensors supported atm.
     if (failed(successStrides) || !isContiguous)
-      return matchFailure();
+      return failure();
 
     auto int64Ty = LLVM::LLVMType::getInt64Ty(typeConverter.getDialect());
 
@@ -901,7 +901,7 @@ class VectorTypeCastOpConversion : public ConvertToLLVMPattern {
     }
 
     rewriter.replaceOp(op, {desc});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -924,7 +924,7 @@ class VectorPrintOpConversion : public ConvertToLLVMPattern {
   //
   // TODO(ajcbik): rely solely on libc in future? something else?
   //
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto printOp = cast<vector::PrintOp>(op);
@@ -932,7 +932,7 @@ class VectorPrintOpConversion : public ConvertToLLVMPattern {
     Type printType = printOp.getPrintType();
 
     if (typeConverter.convertType(printType) == nullptr)
-      return matchFailure();
+      return failure();
 
     // Make sure element type has runtime support (currently just Float/Double).
     VectorType vectorType = printType.dyn_cast<VectorType>();
@@ -948,13 +948,13 @@ class VectorPrintOpConversion : public ConvertToLLVMPattern {
     else if (eltType.isF64())
       printer = getPrintDouble(op);
     else
-      return matchFailure();
+      return failure();
 
     // Unroll vector into elementary print calls.
     emitRanks(rewriter, op, adaptor.source(), vectorType, printer, rank);
     emitCall(rewriter, op->getLoc(), getPrintNewline(op));
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 
 private:
@@ -1047,8 +1047,8 @@ class VectorStridedSliceOpConversion : public OpRewritePattern<StridedSliceOp> {
 public:
   using OpRewritePattern<StridedSliceOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(StridedSliceOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(StridedSliceOp op,
+                                PatternRewriter &rewriter) const override {
     auto dstType = op.getResult().getType().cast<VectorType>();
 
     assert(!op.offsets().getValue().empty() && "Unexpected empty offsets");
@@ -1083,13 +1083,13 @@ class VectorStridedSliceOpConversion : public OpRewritePattern<StridedSliceOp> {
         // multiple times.
         auto success = matchAndRewrite(stridedSliceOp, rewriter);
         (void)success;
-        assert(success && "Unexpected failure");
+        assert(succeeded(success) && "Unexpected failure");
         extracted = stridedSliceOp;
       }
       res = insertOne(rewriter, loc, extracted, res, idx);
     }
     rewriter.replaceOp(op, {res});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1150,8 +1150,8 @@ void LowerVectorToLLVMPass::runOnModule() {
   }
 }
 
-OpPassBase<ModuleOp> *mlir::createLowerVectorToLLVMPass() {
-  return new LowerVectorToLLVMPass();
+std::unique_ptr<OpPassBase<ModuleOp>> mlir::createConvertVectorToLLVMPass() {
+  return std::make_unique<LowerVectorToLLVMPass>();
 }
 
 static PassRegistration<LowerVectorToLLVMPass>
diff --git a/mlir/lib/Conversion/VectorToLoops/ConvertVectorToLoops.cpp b/mlir/lib/Conversion/VectorToLoops/ConvertVectorToLoops.cpp
index 9414b275e96d2..b16f02ef6b9c9 100644
--- a/mlir/lib/Conversion/VectorToLoops/ConvertVectorToLoops.cpp
+++ b/mlir/lib/Conversion/VectorToLoops/ConvertVectorToLoops.cpp
@@ -16,7 +16,7 @@
 #include "mlir/Dialect/AffineOps/EDSC/Intrinsics.h"
 #include "mlir/Dialect/LoopOps/EDSC/Builders.h"
 #include "mlir/Dialect/StandardOps/EDSC/Intrinsics.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/IR/AffineExpr.h"
 #include "mlir/IR/AffineMap.h"
 #include "mlir/IR/Attributes.h"
@@ -198,8 +198,8 @@ struct VectorTransferRewriter : public RewritePattern {
   }
 
   /// Performs the rewrite.
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override;
 };
 
 /// Lowers TransferReadOp into a combination of:
@@ -246,7 +246,7 @@ struct VectorTransferRewriter : public RewritePattern {
 
 /// Performs the rewrite.
 template <>
-PatternMatchResult VectorTransferRewriter<TransferReadOp>::matchAndRewrite(
+LogicalResult VectorTransferRewriter<TransferReadOp>::matchAndRewrite(
     Operation *op, PatternRewriter &rewriter) const {
   using namespace mlir::edsc::op;
 
@@ -282,7 +282,7 @@ PatternMatchResult VectorTransferRewriter<TransferReadOp>::matchAndRewrite(
 
   // 3. Propagate.
   rewriter.replaceOp(op, vectorValue.getValue());
-  return matchSuccess();
+  return success();
 }
 
 /// Lowers TransferWriteOp into a combination of:
@@ -304,7 +304,7 @@ PatternMatchResult VectorTransferRewriter<TransferReadOp>::matchAndRewrite(
 /// TODO(ntv): implement alternatives to clipping.
 /// TODO(ntv): support non-data-parallel operations.
 template <>
-PatternMatchResult VectorTransferRewriter<TransferWriteOp>::matchAndRewrite(
+LogicalResult VectorTransferRewriter<TransferWriteOp>::matchAndRewrite(
     Operation *op, PatternRewriter &rewriter) const {
   using namespace edsc::op;
 
@@ -340,7 +340,7 @@ PatternMatchResult VectorTransferRewriter<TransferWriteOp>::matchAndRewrite(
   (std_dealloc(tmp)); // vexing parse...
 
   rewriter.eraseOp(op);
-  return matchSuccess();
+  return success();
 }
 
 } // namespace
diff --git a/mlir/lib/Dialect/AffineOps/AffineOps.cpp b/mlir/lib/Dialect/AffineOps/AffineOps.cpp
index 5b1df2b6d7343..0b8795947e06c 100644
--- a/mlir/lib/Dialect/AffineOps/AffineOps.cpp
+++ b/mlir/lib/Dialect/AffineOps/AffineOps.cpp
@@ -727,8 +727,8 @@ struct SimplifyAffineOp : public OpRewritePattern<AffineOpTy> {
   void replaceAffineOp(PatternRewriter &rewriter, AffineOpTy affineOp,
                        AffineMap map, ArrayRef<Value> mapOperands) const;
 
-  PatternMatchResult matchAndRewrite(AffineOpTy affineOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineOpTy affineOp,
+                                PatternRewriter &rewriter) const override {
     static_assert(std::is_same<AffineOpTy, AffineLoadOp>::value ||
                       std::is_same<AffineOpTy, AffinePrefetchOp>::value ||
                       std::is_same<AffineOpTy, AffineStoreOp>::value ||
@@ -743,10 +743,10 @@ struct SimplifyAffineOp : public OpRewritePattern<AffineOpTy> {
     composeAffineMapAndOperands(&map, &resultOperands);
     if (map == oldMap && std::equal(oldOperands.begin(), oldOperands.end(),
                                     resultOperands.begin()))
-      return this->matchFailure();
+      return failure();
 
     replaceAffineOp(rewriter, affineOp, map, resultOperands);
-    return this->matchSuccess();
+    return success();
   }
 };
 
@@ -1185,14 +1185,14 @@ static ParseResult parseBound(bool isLower, OperationState &result,
     if (map.getNumDims() != numDims)
       return p.emitError(
           p.getNameLoc(),
-          "dim operand count and integer set dim count must match");
+          "dim operand count and affine map dim count must match");
 
     unsigned numDimAndSymbolOperands =
         result.operands.size() - currentNumOperands;
     if (numDims + map.getNumSymbols() != numDimAndSymbolOperands)
       return p.emitError(
           p.getNameLoc(),
-          "symbol operand count and integer set symbol count must match");
+          "symbol operand count and affine map symbol count must match");
 
     // If the map has multiple results, make sure that we parsed the min/max
     // prefix.
@@ -1405,13 +1405,13 @@ namespace {
 struct AffineForEmptyLoopFolder : public OpRewritePattern<AffineForOp> {
   using OpRewritePattern<AffineForOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AffineForOp forOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AffineForOp forOp,
+                                PatternRewriter &rewriter) const override {
     // Check that the body only contains a terminator.
     if (!has_single_element(*forOp.getBody()))
-      return matchFailure();
+      return failure();
     rewriter.eraseOp(forOp);
-    return matchSuccess();
+    return success();
   }
 };
 } // end anonymous namespace
diff --git a/mlir/lib/Dialect/CMakeLists.txt b/mlir/lib/Dialect/CMakeLists.txt
index 192616a1409fa..fe99044a90e65 100644
--- a/mlir/lib/Dialect/CMakeLists.txt
+++ b/mlir/lib/Dialect/CMakeLists.txt
@@ -5,12 +5,12 @@ add_subdirectory(Linalg)
 add_subdirectory(LLVMIR)
 add_subdirectory(LoopOps)
 add_subdirectory(OpenMP)
-add_subdirectory(QuantOps)
+add_subdirectory(Quant)
 add_subdirectory(SDBM)
-#add_subdirectory(Shape)
+add_subdirectory(Shape)
 add_subdirectory(SPIRV)
 add_subdirectory(StandardOps)
-add_subdirectory(VectorOps)
+add_subdirectory(Vector)
 
 set(LLVM_OPTIONAL_SOURCES
   Traits.cpp
diff --git a/mlir/lib/Dialect/FxpMathOps/IR/FxpMathOps.cpp b/mlir/lib/Dialect/FxpMathOps/IR/FxpMathOps.cpp
index 3cc4f7710e107..069f431238bcc 100644
--- a/mlir/lib/Dialect/FxpMathOps/IR/FxpMathOps.cpp
+++ b/mlir/lib/Dialect/FxpMathOps/IR/FxpMathOps.cpp
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Dialect/FxpMathOps/FxpMathOps.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/MLIRContext.h"
 #include "mlir/IR/StandardTypes.h"
 #include "llvm/ADT/StringRef.h"
diff --git a/mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp b/mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
index 4084416a88942..2a876a332ea6c 100644
--- a/mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
+++ b/mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
@@ -111,8 +111,8 @@ namespace {
 struct UniformDequantizePattern : public OpRewritePattern<DequantizeCastOp> {
   using OpRewritePattern<DequantizeCastOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(DequantizeCastOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(DequantizeCastOp op,
+                                PatternRewriter &rewriter) const override {
     Type inputType = op.arg().getType();
     Type outputType = op.getResult().getType();
 
@@ -121,16 +121,16 @@ struct UniformDequantizePattern : public OpRewritePattern<DequantizeCastOp> {
     Type expressedOutputType = inputElementType.castToExpressedType(inputType);
     if (expressedOutputType != outputType) {
       // Not a valid uniform cast.
-      return matchFailure();
+      return failure();
     }
 
     Value dequantizedValue = emitDequantize(op.getLoc(), op.arg(), rewriter);
     if (!dequantizedValue) {
-      return matchFailure();
+      return failure();
     }
 
     rewriter.replaceOp(op, dequantizedValue);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -313,40 +313,40 @@ namespace {
 struct UniformRealAddEwPattern : public OpRewritePattern<RealAddEwOp> {
   using OpRewritePattern<RealAddEwOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(RealAddEwOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(RealAddEwOp op,
+                                PatternRewriter &rewriter) const override {
     const UniformBinaryOpInfo info(op, op.lhs(), op.rhs(), op.clamp_min(),
                                    op.clamp_max());
     if (!info.isValid()) {
-      return matchFailure();
+      return failure();
     }
 
     // Try all of the permutations we support.
     if (succeeded(tryRewriteAffineAddEwIsomorphicSigned(info, rewriter))) {
-      return matchSuccess();
+      return success();
     }
 
-    return matchFailure();
+    return failure();
   }
 };
 
 struct UniformRealMulEwPattern : public OpRewritePattern<RealMulEwOp> {
   using OpRewritePattern<RealMulEwOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(RealMulEwOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(RealMulEwOp op,
+                                PatternRewriter &rewriter) const override {
     const UniformBinaryOpInfo info(op, op.lhs(), op.rhs(), op.clamp_min(),
                                    op.clamp_max());
     if (!info.isValid()) {
-      return matchFailure();
+      return failure();
     }
 
     // Try all of the permutations we support.
     if (succeeded(tryRewriteAffineMulEwSigned(info, rewriter))) {
-      return matchSuccess();
+      return success();
     }
 
-    return matchFailure();
+    return failure();
   }
 };
 
diff --git a/mlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h b/mlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h
index 1f52156533f23..e41eeea5b2f3a 100644
--- a/mlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h
+++ b/mlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h
@@ -9,9 +9,9 @@
 #ifndef MLIR_FXPMATH_UNIFORM_KERNEL_UTILS_H_
 #define MLIR_FXPMATH_UNIFORM_KERNEL_UTILS_H_
 
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
-#include "mlir/Dialect/QuantOps/UniformSupport.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
+#include "mlir/Dialect/Quant/UniformSupport.h"
 #include "mlir/IR/Operation.h"
 
 #include <cmath>
diff --git a/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp b/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
index ae5c981aad7ed..d12611f33b9cb 100644
--- a/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
+++ b/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
@@ -380,8 +380,8 @@ struct GpuAllReduceConversion : public RewritePattern {
   explicit GpuAllReduceConversion(MLIRContext *context)
       : RewritePattern(gpu::GPUFuncOp::getOperationName(), 1, context) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override {
     auto funcOp = cast<gpu::GPUFuncOp>(op);
     auto callback = [&](gpu::AllReduceOp reduceOp) {
       GpuAllReduceRewriter(funcOp, reduceOp, rewriter).rewrite();
@@ -391,7 +391,7 @@ struct GpuAllReduceConversion : public RewritePattern {
     };
     while (funcOp.walk(callback).wasInterrupted()) {
     }
-    return matchSuccess();
+    return success();
   }
 };
 } // namespace
diff --git a/mlir/lib/Dialect/LLVMIR/CMakeLists.txt b/mlir/lib/Dialect/LLVMIR/CMakeLists.txt
index fb94a220835c7..2e53d29f768da 100644
--- a/mlir/lib/Dialect/LLVMIR/CMakeLists.txt
+++ b/mlir/lib/Dialect/LLVMIR/CMakeLists.txt
@@ -1,3 +1,5 @@
+add_subdirectory(Transforms)
+
 add_mlir_dialect_library(MLIRLLVMIR
   IR/LLVMDialect.cpp
 
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index 7a15d579127d5..2a2e6699fee5e 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -1567,6 +1567,47 @@ static LogicalResult verify(AtomicCmpXchgOp op) {
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// Printer, parser and verifier for LLVM::FenceOp.
+//===----------------------------------------------------------------------===//
+
+// <operation> ::= `llvm.fence` (`syncscope(`strAttr`)`)? keyword
+// attribute-dict?
+static ParseResult parseFenceOp(OpAsmParser &parser, OperationState &result) {
+  StringAttr sScope;
+  StringRef syncscopeKeyword = "syncscope";
+  if (!failed(parser.parseOptionalKeyword(syncscopeKeyword))) {
+    if (parser.parseLParen() ||
+        parser.parseAttribute(sScope, syncscopeKeyword, result.attributes) ||
+        parser.parseRParen())
+      return failure();
+  } else {
+    result.addAttribute(syncscopeKeyword,
+                        parser.getBuilder().getStringAttr(""));
+  }
+  if (parseAtomicOrdering(parser, result, "ordering") ||
+      parser.parseOptionalAttrDict(result.attributes))
+    return failure();
+  return success();
+}
+
+static void printFenceOp(OpAsmPrinter &p, FenceOp &op) {
+  StringRef syncscopeKeyword = "syncscope";
+  p << op.getOperationName() << ' ';
+  if (!op.getAttr(syncscopeKeyword).cast<StringAttr>().getValue().empty())
+    p << "syncscope(" << op.getAttr(syncscopeKeyword) << ") ";
+  p << stringifyAtomicOrdering(op.ordering());
+}
+
+static LogicalResult verify(FenceOp &op) {
+  if (op.ordering() == AtomicOrdering::not_atomic ||
+      op.ordering() == AtomicOrdering::unordered ||
+      op.ordering() == AtomicOrdering::monotonic)
+    return op.emitOpError("can be given only acquire, release, acq_rel, "
+                          "and seq_cst orderings");
+  return success();
+}
+
 //===----------------------------------------------------------------------===//
 // LLVMDialect initialization, type parsing, and registration.
 //===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt b/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt
new file mode 100644
index 0000000000000..6b37b060de6c8
--- /dev/null
+++ b/mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_mlir_dialect_library(MLIRLLVMIRTransforms
+  LegalizeForExport.cpp
+  )
+
+target_link_libraries(MLIRLLVMIRTransforms
+  PUBLIC
+  MLIRIR
+  MLIRLLVMIR
+  MLIRPass
+  )
diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp
new file mode 100644
index 0000000000000..fce4045f1aa3e
--- /dev/null
+++ b/mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp
@@ -0,0 +1,73 @@
+//===- LegalizeForExport.cpp - Prepare for translation to LLVM IR ---------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/IR/Block.h"
+#include "mlir/IR/Builders.h"
+#include "mlir/IR/Module.h"
+#include "mlir/Pass/Pass.h"
+
+using namespace mlir;
+
+static void ensureDistinctSuccessors(Block &bb) {
+  auto *terminator = bb.getTerminator();
+
+  // Find repeated successors with arguments.
+  llvm::SmallDenseMap<Block *, SmallVector<int, 4>> successorPositions;
+  for (int i = 0, e = terminator->getNumSuccessors(); i < e; ++i) {
+    Block *successor = terminator->getSuccessor(i);
+    // Blocks with no arguments are safe even if they appear multiple times
+    // because they don't need PHI nodes.
+    if (successor->getNumArguments() == 0)
+      continue;
+    successorPositions[successor].push_back(i);
+  }
+
+  // If a successor appears for the second or more time in the terminator,
+  // create a new dummy block that unconditionally branches to the original
+  // destination, and retarget the terminator to branch to this new block.
+  // There is no need to pass arguments to the dummy block because it will be
+  // dominated by the original block and can therefore use any values defined in
+  // the original block.
+  OpBuilder builder(terminator->getContext());
+  for (const auto &successor : successorPositions) {
+    // Start from the second occurrence of a block in the successor list.
+    for (int position : llvm::drop_begin(successor.second, 1)) {
+      Block *dummyBlock = builder.createBlock(bb.getParent());
+      terminator->setSuccessor(dummyBlock, position);
+      dummyBlock->addArguments(successor.first->getArgumentTypes());
+      builder.create<LLVM::BrOp>(terminator->getLoc(),
+                                 dummyBlock->getArguments(), successor.first);
+    }
+  }
+}
+
+void mlir::LLVM::ensureDistinctSuccessors(Operation *op) {
+  op->walk([](LLVMFuncOp f) {
+    for (auto &bb : f.getBlocks()) {
+      ::ensureDistinctSuccessors(bb);
+    }
+  });
+}
+
+namespace {
+struct LegalizeForExportPass : public OperationPass<LegalizeForExportPass> {
+  void runOnOperation() override {
+    LLVM::ensureDistinctSuccessors(getOperation());
+  }
+};
+} // end namespace
+
+std::unique_ptr<Pass> LLVM::createLegalizeForExportPass() {
+  return std::make_unique<LegalizeForExportPass>();
+}
+
+static PassRegistration<LegalizeForExportPass>
+    pass("llvm-legalize-for-export",
+         "Legalize LLVM dialect to be convertible to LLVM IR");
diff --git a/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt b/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
index 7a864ad2def22..82e36f8a00b14 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
+++ b/mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
@@ -27,5 +27,5 @@ target_link_libraries(MLIRLinalgTransforms
   MLIRStandardOps
   MLIRStandardToLLVM
   MLIRTransformUtils
-  MLIRVectorOps
+  MLIRVector
   )
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp b/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
index cf95212982c96..8da000fa5260d 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
@@ -534,10 +534,10 @@ namespace {
 struct FuseGenericTensorOps : public OpRewritePattern<GenericOp> {
   using OpRewritePattern<GenericOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(GenericOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(GenericOp op,
+                                PatternRewriter &rewriter) const override {
     if (!op.hasTensorSemantics())
-      return matchFailure();
+      return failure();
 
     // Find the first operand that is defined by another generic op on tensors.
     for (auto operand : llvm::enumerate(op.getOperation()->getOperands())) {
@@ -551,9 +551,9 @@ struct FuseGenericTensorOps : public OpRewritePattern<GenericOp> {
       if (!fusedOp)
         continue;
       rewriter.replaceOp(op, fusedOp.getValue().getOperation()->getResults());
-      return matchSuccess();
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 };
 
diff --git a/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp b/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp
index 22f53b2ab8bc8..4dc41e2c87ae0 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp
@@ -531,13 +531,13 @@ class LinalgRewritePattern : public RewritePattern {
   explicit LinalgRewritePattern(MLIRContext *context)
       : RewritePattern(ConcreteOp::getOperationName(), 1, context) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override {
     using Impl = LinalgOpToLoopsImpl<LoopType, IndexedValueType, ConcreteOp>;
     if (failed(Impl::doit(op, rewriter)))
-      return matchFailure();
+      return failure();
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -595,26 +595,26 @@ struct FoldAffineOp : public RewritePattern {
   FoldAffineOp(MLIRContext *context)
       : RewritePattern(AffineApplyOp::getOperationName(), 0, context) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override {
     AffineApplyOp affineApplyOp = cast<AffineApplyOp>(op);
     auto map = affineApplyOp.getAffineMap();
     if (map.getNumResults() != 1 || map.getNumInputs() > 1)
-      return matchFailure();
+      return failure();
 
     AffineExpr expr = map.getResult(0);
     if (map.getNumInputs() == 0) {
       if (auto val = expr.dyn_cast<AffineConstantExpr>()) {
         rewriter.replaceOpWithNewOp<ConstantIndexOp>(op, val.getValue());
-        return matchSuccess();
+        return success();
       }
-      return matchFailure();
+      return failure();
     }
     if (expr.dyn_cast<AffineDimExpr>() || expr.dyn_cast<AffineSymbolExpr>()) {
       rewriter.replaceOp(op, op->getOperand(0));
-      return matchSuccess();
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 };
 } // namespace
diff --git a/mlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp b/mlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp
index 2b0654c219a03..8511c8efffce9 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp
@@ -16,7 +16,7 @@
 #include "mlir/Dialect/Linalg/Utils/Utils.h"
 #include "mlir/Dialect/StandardOps/EDSC/Intrinsics.h"
 #include "mlir/Dialect/Utils/StructuredOpsUtils.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/IR/AffineExpr.h"
 #include "mlir/IR/Matchers.h"
 #include "mlir/IR/PatternMatch.h"
diff --git a/mlir/lib/Dialect/QuantOps/CMakeLists.txt b/mlir/lib/Dialect/Quant/CMakeLists.txt
similarity index 100%
rename from mlir/lib/Dialect/QuantOps/CMakeLists.txt
rename to mlir/lib/Dialect/Quant/CMakeLists.txt
diff --git a/mlir/lib/Dialect/Quant/IR/QuantOps.cpp b/mlir/lib/Dialect/Quant/IR/QuantOps.cpp
new file mode 100644
index 0000000000000..f67a9f7fbc229
--- /dev/null
+++ b/mlir/lib/Dialect/Quant/IR/QuantOps.cpp
@@ -0,0 +1,96 @@
+//===- QuantOps.cpp - Quantization Type and Ops Implementation --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "TypeDetail.h"
+
+#include "mlir/Dialect/Quant/QuantTypes.h"
+#include "mlir/IR/MLIRContext.h"
+#include "mlir/IR/Matchers.h"
+#include "mlir/IR/PatternMatch.h"
+#include "mlir/IR/StandardTypes.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/Support/MathExtras.h"
+#include <numeric>
+
+using namespace mlir;
+using namespace mlir::quant;
+using namespace mlir::quant::detail;
+
+QuantizationDialect::QuantizationDialect(MLIRContext *context)
+    : Dialect(/*name=*/"quant", context) {
+  addTypes<AnyQuantizedType, UniformQuantizedType,
+           UniformQuantizedPerAxisType>();
+  addOperations<
+#define GET_OP_LIST
+#include "mlir/Dialect/Quant/QuantOps.cpp.inc"
+      >();
+}
+
+OpFoldResult StorageCastOp::fold(ArrayRef<Attribute> operands) {
+  // Matches x -> [scast -> scast] -> y, replacing the second scast with the
+  // value of x if the casts invert each other.
+  auto srcScastOp = dyn_cast_or_null<StorageCastOp>(arg().getDefiningOp());
+  if (!srcScastOp || srcScastOp.arg().getType() != getType())
+    return OpFoldResult();
+  return srcScastOp.arg();
+}
+
+/// The quantization specification should match the expressed type.
+static bool isValidQuantizationSpec(Attribute quantSpec, Type expressed) {
+  if (auto typeAttr = quantSpec.dyn_cast<TypeAttr>()) {
+    Type spec = typeAttr.getValue();
+    if (spec.isa<TensorType>() || spec.isa<VectorType>())
+      return false;
+
+    // The spec should be either a quantized type which is compatible to the
+    // expressed type, or a primitive type which is as same as the
+    // (element type of) the expressed type.
+    if (auto quantizedType = spec.dyn_cast<QuantizedType>())
+      return quantizedType.isCompatibleExpressedType(expressed);
+
+    if (auto tensorType = expressed.dyn_cast<TensorType>())
+      return spec == tensorType.getElementType();
+
+    if (auto vectorType = expressed.dyn_cast<VectorType>())
+      return spec == vectorType.getElementType();
+  }
+  return false;
+}
+
+static LogicalResult verifyRegionOp(QuantizeRegionOp op) {
+  // There are specifications for both inputs and outputs.
+  if (op.getNumOperands() != op.input_specs().size() ||
+      op.getNumResults() != op.output_specs().size())
+    return op.emitOpError(
+        "has unmatched operands/results number and spec attributes number");
+
+  // Verify that quantization specifications are valid.
+  for (auto input : llvm::zip(op.getOperandTypes(), op.input_specs())) {
+    Type inputType = std::get<0>(input);
+    Attribute inputSpec = std::get<1>(input);
+    if (!isValidQuantizationSpec(inputSpec, inputType)) {
+      return op.emitOpError() << "has incompatible specification " << inputSpec
+                              << " and input type " << inputType;
+    }
+  }
+
+  for (auto result : llvm::zip(op.getResultTypes(), op.output_specs())) {
+    Type outputType = std::get<0>(result);
+    Attribute outputSpec = std::get<1>(result);
+    if (!isValidQuantizationSpec(outputSpec, outputType)) {
+      return op.emitOpError() << "has incompatible specification " << outputSpec
+                              << " and output type " << outputType;
+    }
+  }
+  return success();
+}
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/Quant/QuantOps.cpp.inc"
diff --git a/mlir/lib/Dialect/QuantOps/IR/QuantTypes.cpp b/mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
similarity index 99%
rename from mlir/lib/Dialect/QuantOps/IR/QuantTypes.cpp
rename to mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
index d8cee1afe2559..7ef5b4a77c549 100644
--- a/mlir/lib/Dialect/QuantOps/IR/QuantTypes.cpp
+++ b/mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "TypeDetail.h"
 
 #include "mlir/IR/MLIRContext.h"
diff --git a/mlir/lib/Dialect/QuantOps/IR/TypeDetail.h b/mlir/lib/Dialect/Quant/IR/TypeDetail.h
similarity index 100%
rename from mlir/lib/Dialect/QuantOps/IR/TypeDetail.h
rename to mlir/lib/Dialect/Quant/IR/TypeDetail.h
diff --git a/mlir/lib/Dialect/QuantOps/IR/TypeParser.cpp b/mlir/lib/Dialect/Quant/IR/TypeParser.cpp
similarity index 99%
rename from mlir/lib/Dialect/QuantOps/IR/TypeParser.cpp
rename to mlir/lib/Dialect/Quant/IR/TypeParser.cpp
index 7252f14aa5095..5f382f2dbc3de 100644
--- a/mlir/lib/Dialect/QuantOps/IR/TypeParser.cpp
+++ b/mlir/lib/Dialect/Quant/IR/TypeParser.cpp
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/DialectImplementation.h"
 #include "mlir/IR/Location.h"
 #include "mlir/IR/StandardTypes.h"
diff --git a/mlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp b/mlir/lib/Dialect/Quant/Transforms/ConvertConst.cpp
similarity index 86%
rename from mlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp
rename to mlir/lib/Dialect/Quant/Transforms/ConvertConst.cpp
index 6716bbcdddb0a..2598e8cf50138 100644
--- a/mlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp
+++ b/mlir/lib/Dialect/Quant/Transforms/ConvertConst.cpp
@@ -6,10 +6,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/Passes.h"
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantizeUtils.h"
-#include "mlir/Dialect/QuantOps/UniformSupport.h"
+#include "mlir/Dialect/Quant/Passes.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantizeUtils.h"
+#include "mlir/Dialect/Quant/UniformSupport.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Matchers.h"
@@ -30,8 +30,8 @@ class ConvertConstPass : public FunctionPass<ConvertConstPass> {
 struct QuantizedConstRewrite : public OpRewritePattern<QuantizeCastOp> {
   using OpRewritePattern<QuantizeCastOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(QuantizeCastOp qbarrier,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(QuantizeCastOp qbarrier,
+                                PatternRewriter &rewriter) const override;
 };
 
 } // end anonymous namespace
@@ -39,14 +39,14 @@ struct QuantizedConstRewrite : public OpRewritePattern<QuantizeCastOp> {
 /// Matches a [constant] -> [qbarrier] where the qbarrier results type is
 /// quantized and the operand type is quantizable.
 
-PatternMatchResult
+LogicalResult
 QuantizedConstRewrite::matchAndRewrite(QuantizeCastOp qbarrier,
                                        PatternRewriter &rewriter) const {
   Attribute value;
 
   // Is the operand a constant?
   if (!matchPattern(qbarrier.arg(), m_Constant(&value))) {
-    return matchFailure();
+    return failure();
   }
 
   // Does the qbarrier convert to a quantized type. This will not be true
@@ -56,10 +56,10 @@ QuantizedConstRewrite::matchAndRewrite(QuantizeCastOp qbarrier,
   QuantizedType quantizedElementType =
       QuantizedType::getQuantizedElementType(qbarrierResultType);
   if (!quantizedElementType) {
-    return matchFailure();
+    return failure();
   }
   if (!QuantizedType::castToStorageType(qbarrierResultType)) {
-    return matchFailure();
+    return failure();
   }
 
   // Is the operand type compatible with the expressed type of the quantized
@@ -67,20 +67,20 @@ QuantizedConstRewrite::matchAndRewrite(QuantizeCastOp qbarrier,
   // from and to a quantized type).
   if (!quantizedElementType.isCompatibleExpressedType(
           qbarrier.arg().getType())) {
-    return matchFailure();
+    return failure();
   }
 
   // Is the constant value a type expressed in a way that we support?
   if (!value.isa<FloatAttr>() && !value.isa<DenseElementsAttr>() &&
       !value.isa<SparseElementsAttr>()) {
-    return matchFailure();
+    return failure();
   }
 
   Type newConstValueType;
   auto newConstValue =
       quantizeAttr(value, quantizedElementType, newConstValueType);
   if (!newConstValue) {
-    return matchFailure();
+    return failure();
   }
 
   // When creating the new const op, use a fused location that combines the
@@ -92,7 +92,7 @@ QuantizedConstRewrite::matchAndRewrite(QuantizeCastOp qbarrier,
       rewriter.create<ConstantOp>(fusedLoc, newConstValueType, newConstValue);
   rewriter.replaceOpWithNewOp<StorageCastOp>(qbarrier, qbarrier.getType(),
                                              newConstOp);
-  return matchSuccess();
+  return success();
 }
 
 void ConvertConstPass::runOnFunction() {
diff --git a/mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp b/mlir/lib/Dialect/Quant/Transforms/ConvertSimQuant.cpp
similarity index 92%
rename from mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp
rename to mlir/lib/Dialect/Quant/Transforms/ConvertSimQuant.cpp
index b9502bd9c0637..c921aeafda904 100644
--- a/mlir/lib/Dialect/QuantOps/Transforms/ConvertSimQuant.cpp
+++ b/mlir/lib/Dialect/Quant/Transforms/ConvertSimQuant.cpp
@@ -6,10 +6,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/FakeQuantSupport.h"
-#include "mlir/Dialect/QuantOps/Passes.h"
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/UniformSupport.h"
+#include "mlir/Dialect/Quant/FakeQuantSupport.h"
+#include "mlir/Dialect/Quant/Passes.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/UniformSupport.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/IR/StandardTypes.h"
@@ -35,16 +35,16 @@ class FakeQuantRewrite : public OpRewritePattern<FakeQuantOp> {
   FakeQuantRewrite(MLIRContext *ctx, bool *hadFailure)
       : OpRewritePattern<FakeQuantOp>(ctx), hadFailure(hadFailure) {}
 
-  PatternMatchResult matchAndRewrite(FakeQuantOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(FakeQuantOp op,
+                                PatternRewriter &rewriter) const override {
     // TODO: If this pattern comes up more frequently, consider adding core
     // support for failable rewrites.
     if (failableRewrite(op, rewriter)) {
       *hadFailure = true;
-      return Pattern::matchFailure();
+      return failure();
     }
 
-    return Pattern::matchSuccess();
+    return success();
   }
 
 private:
diff --git a/mlir/lib/Dialect/QuantOps/Utils/FakeQuantSupport.cpp b/mlir/lib/Dialect/Quant/Utils/FakeQuantSupport.cpp
similarity index 98%
rename from mlir/lib/Dialect/QuantOps/Utils/FakeQuantSupport.cpp
rename to mlir/lib/Dialect/Quant/Utils/FakeQuantSupport.cpp
index 24f05e0426ed9..51ed4414f75c4 100644
--- a/mlir/lib/Dialect/QuantOps/Utils/FakeQuantSupport.cpp
+++ b/mlir/lib/Dialect/Quant/Utils/FakeQuantSupport.cpp
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/FakeQuantSupport.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/FakeQuantSupport.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 
 using namespace mlir;
 using namespace mlir::quant;
diff --git a/mlir/lib/Dialect/QuantOps/Utils/QuantizeUtils.cpp b/mlir/lib/Dialect/Quant/Utils/QuantizeUtils.cpp
similarity index 98%
rename from mlir/lib/Dialect/QuantOps/Utils/QuantizeUtils.cpp
rename to mlir/lib/Dialect/Quant/Utils/QuantizeUtils.cpp
index bcd1b6b267111..1fbc60962fd17 100644
--- a/mlir/lib/Dialect/QuantOps/Utils/QuantizeUtils.cpp
+++ b/mlir/lib/Dialect/Quant/Utils/QuantizeUtils.cpp
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantizeUtils.h"
-#include "mlir/Dialect/QuantOps/UniformSupport.h"
+#include "mlir/Dialect/Quant/QuantizeUtils.h"
+#include "mlir/Dialect/Quant/UniformSupport.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/StandardTypes.h"
 
diff --git a/mlir/lib/Dialect/QuantOps/Utils/UniformSupport.cpp b/mlir/lib/Dialect/Quant/Utils/UniformSupport.cpp
similarity index 98%
rename from mlir/lib/Dialect/QuantOps/Utils/UniformSupport.cpp
rename to mlir/lib/Dialect/Quant/Utils/UniformSupport.cpp
index fcb8c24c1e07d..4d5db81e326de 100644
--- a/mlir/lib/Dialect/QuantOps/Utils/UniformSupport.cpp
+++ b/mlir/lib/Dialect/Quant/Utils/UniformSupport.cpp
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/UniformSupport.h"
+#include "mlir/Dialect/Quant/UniformSupport.h"
 #include "mlir/IR/StandardTypes.h"
 #include <numeric>
 
diff --git a/mlir/lib/Dialect/QuantOps/IR/QuantOps.cpp b/mlir/lib/Dialect/QuantOps/IR/QuantOps.cpp
deleted file mode 100644
index 9a678260415a8..0000000000000
--- a/mlir/lib/Dialect/QuantOps/IR/QuantOps.cpp
+++ /dev/null
@@ -1,46 +0,0 @@
-//===- QuantOps.cpp - Quantization Type and Ops Implementation --*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "TypeDetail.h"
-
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
-#include "mlir/IR/MLIRContext.h"
-#include "mlir/IR/Matchers.h"
-#include "mlir/IR/PatternMatch.h"
-#include "mlir/IR/StandardTypes.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/Support/MathExtras.h"
-#include <numeric>
-
-using namespace mlir;
-using namespace mlir::quant;
-using namespace mlir::quant::detail;
-
-QuantizationDialect::QuantizationDialect(MLIRContext *context)
-    : Dialect(/*name=*/"quant", context) {
-  addTypes<AnyQuantizedType, UniformQuantizedType,
-           UniformQuantizedPerAxisType>();
-  addOperations<
-#define GET_OP_LIST
-#include "mlir/Dialect/QuantOps/QuantOps.cpp.inc"
-      >();
-}
-
-OpFoldResult StorageCastOp::fold(ArrayRef<Attribute> operands) {
-  /// Matches x -> [scast -> scast] -> y, replacing the second scast with the
-  /// value of x if the casts invert each other.
-  auto srcScastOp = dyn_cast_or_null<StorageCastOp>(arg().getDefiningOp());
-  if (!srcScastOp || srcScastOp.arg().getType() != getType())
-    return OpFoldResult();
-  return srcScastOp.arg();
-}
-
-#define GET_OP_CLASSES
-#include "mlir/Dialect/QuantOps/QuantOps.cpp.inc"
diff --git a/mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.cpp b/mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.cpp
index c705dc87bfa8a..f378047f36eac 100644
--- a/mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.cpp
+++ b/mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.cpp
@@ -88,13 +88,13 @@ struct CombineChainedAccessChain
     : public OpRewritePattern<spirv::AccessChainOp> {
   using OpRewritePattern<spirv::AccessChainOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(spirv::AccessChainOp accessChainOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(spirv::AccessChainOp accessChainOp,
+                                PatternRewriter &rewriter) const override {
     auto parentAccessChainOp = dyn_cast_or_null<spirv::AccessChainOp>(
         accessChainOp.base_ptr().getDefiningOp());
 
     if (!parentAccessChainOp) {
-      return matchFailure();
+      return failure();
     }
 
     // Combine indices.
@@ -105,7 +105,7 @@ struct CombineChainedAccessChain
     rewriter.replaceOpWithNewOp<spirv::AccessChainOp>(
         accessChainOp, parentAccessChainOp.base_ptr(), indices);
 
-    return matchSuccess();
+    return success();
   }
 };
 } // end anonymous namespace
@@ -291,24 +291,24 @@ struct ConvertSelectionOpToSelect
     : public OpRewritePattern<spirv::SelectionOp> {
   using OpRewritePattern<spirv::SelectionOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(spirv::SelectionOp selectionOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(spirv::SelectionOp selectionOp,
+                                PatternRewriter &rewriter) const override {
     auto *op = selectionOp.getOperation();
     auto &body = op->getRegion(0);
     // Verifier allows an empty region for `spv.selection`.
     if (body.empty()) {
-      return matchFailure();
+      return failure();
     }
 
     // Check that region consists of 4 blocks:
     // header block, `true` block, `false` block and merge block.
     if (std::distance(body.begin(), body.end()) != 4) {
-      return matchFailure();
+      return failure();
     }
 
     auto *headerBlock = selectionOp.getHeaderBlock();
     if (!onlyContainsBranchConditionalOp(headerBlock)) {
-      return matchFailure();
+      return failure();
     }
 
     auto brConditionalOp =
@@ -318,9 +318,8 @@ struct ConvertSelectionOpToSelect
     auto *falseBlock = brConditionalOp.getSuccessor(1);
     auto *mergeBlock = selectionOp.getMergeBlock();
 
-    if (!canCanonicalizeSelection(trueBlock, falseBlock, mergeBlock)) {
-      return matchFailure();
-    }
+    if (failed(canCanonicalizeSelection(trueBlock, falseBlock, mergeBlock)))
+      return failure();
 
     auto trueValue = getSrcValue(trueBlock);
     auto falseValue = getSrcValue(falseBlock);
@@ -336,7 +335,7 @@ struct ConvertSelectionOpToSelect
 
     // `spv.selection` is not needed anymore.
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 
 private:
@@ -346,9 +345,8 @@ struct ConvertSelectionOpToSelect
   // 2. Each `spv.Store` uses the same pointer and the same memory attributes.
   // 3. A control flow goes into the given merge block from the given
   //    conditional blocks.
-  PatternMatchResult canCanonicalizeSelection(Block *trueBlock,
-                                              Block *falseBlock,
-                                              Block *mergeBlock) const;
+  LogicalResult canCanonicalizeSelection(Block *trueBlock, Block *falseBlock,
+                                         Block *mergeBlock) const;
 
   bool onlyContainsBranchConditionalOp(Block *block) const {
     return std::next(block->begin()) == block->end() &&
@@ -383,12 +381,12 @@ struct ConvertSelectionOpToSelect
   }
 };
 
-PatternMatchResult ConvertSelectionOpToSelect::canCanonicalizeSelection(
+LogicalResult ConvertSelectionOpToSelect::canCanonicalizeSelection(
     Block *trueBlock, Block *falseBlock, Block *mergeBlock) const {
   // Each block must consists of 2 operations.
   if ((std::distance(trueBlock->begin(), trueBlock->end()) != 2) ||
       (std::distance(falseBlock->begin(), falseBlock->end()) != 2)) {
-    return matchFailure();
+    return failure();
   }
 
   auto trueBrStoreOp = dyn_cast<spirv::StoreOp>(trueBlock->front());
@@ -400,7 +398,7 @@ PatternMatchResult ConvertSelectionOpToSelect::canCanonicalizeSelection(
 
   if (!trueBrStoreOp || !trueBrBranchOp || !falseBrStoreOp ||
       !falseBrBranchOp) {
-    return matchFailure();
+    return failure();
   }
 
   // Check that each `spv.Store` uses the same pointer, memory access
@@ -408,15 +406,15 @@ PatternMatchResult ConvertSelectionOpToSelect::canCanonicalizeSelection(
   if ((trueBrStoreOp.ptr() != falseBrStoreOp.ptr()) ||
       !isSameAttrList(trueBrStoreOp, falseBrStoreOp) ||
       !isValidType(trueBrStoreOp.value().getType())) {
-    return matchFailure();
+    return failure();
   }
 
   if ((trueBrBranchOp.getOperation()->getSuccessor(0) != mergeBlock) ||
       (falseBrBranchOp.getOperation()->getSuccessor(0) != mergeBlock)) {
-    return matchFailure();
+    return failure();
   }
 
-  return matchSuccess();
+  return success();
 }
 } // end anonymous namespace
 
diff --git a/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp b/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
index 3cf50466e0729..4adabdaa597ea 100644
--- a/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
+++ b/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
@@ -177,25 +177,25 @@ class FuncOpConversion final : public SPIRVOpLowering<FuncOp> {
 public:
   using SPIRVOpLowering<FuncOp>::SPIRVOpLowering;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(FuncOp funcOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
 } // namespace
 
-PatternMatchResult
+LogicalResult
 FuncOpConversion::matchAndRewrite(FuncOp funcOp, ArrayRef<Value> operands,
                                   ConversionPatternRewriter &rewriter) const {
   auto fnType = funcOp.getType();
   // TODO(antiagainst): support converting functions with one result.
   if (fnType.getNumResults())
-    return matchFailure();
+    return failure();
 
   TypeConverter::SignatureConversion signatureConverter(fnType.getNumInputs());
   for (auto argType : enumerate(funcOp.getType().getInputs())) {
     auto convertedType = typeConverter.convertType(argType.value());
     if (!convertedType)
-      return matchFailure();
+      return failure();
     signatureConverter.addInputs(argType.index(), convertedType);
   }
 
@@ -216,7 +216,7 @@ FuncOpConversion::matchAndRewrite(FuncOp funcOp, ArrayRef<Value> operands,
                               newFuncOp.end());
   rewriter.applySignatureConversion(&newFuncOp.getBody(), signatureConverter);
   rewriter.eraseOp(funcOp);
-  return matchSuccess();
+  return success();
 }
 
 void mlir::populateBuiltinFuncToSPIRVPatterns(
diff --git a/mlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp b/mlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp
index d137f45d8361f..0645408398b6a 100644
--- a/mlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp
+++ b/mlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp
@@ -27,8 +27,8 @@ class SPIRVGlobalVariableOpLayoutInfoDecoration
 public:
   using OpRewritePattern<spirv::GlobalVariableOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(spirv::GlobalVariableOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(spirv::GlobalVariableOp op,
+                                PatternRewriter &rewriter) const override {
     spirv::StructType::LayoutInfo structSize = 0;
     VulkanLayoutUtils::Size structAlignment = 1;
     SmallVector<NamedAttribute, 4> globalVarAttrs;
@@ -50,7 +50,7 @@ class SPIRVGlobalVariableOpLayoutInfoDecoration
 
     rewriter.replaceOpWithNewOp<spirv::GlobalVariableOp>(
         op, TypeAttr::get(decoratedType), globalVarAttrs);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -59,15 +59,15 @@ class SPIRVAddressOfOpLayoutInfoDecoration
 public:
   using OpRewritePattern<spirv::AddressOfOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(spirv::AddressOfOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(spirv::AddressOfOp op,
+                                PatternRewriter &rewriter) const override {
     auto spirvModule = op.getParentOfType<spirv::ModuleOp>();
     auto varName = op.variable();
     auto varOp = spirvModule.lookupSymbol<spirv::GlobalVariableOp>(varName);
 
     rewriter.replaceOpWithNewOp<spirv::AddressOfOp>(
         op, varOp.type(), rewriter.getSymbolRefAttr(varName));
-    return matchSuccess();
+    return success();
   }
 };
 } // namespace
diff --git a/mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp b/mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
index ba8dee7527827..4dbc54ecfca2e 100644
--- a/mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
+++ b/mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
@@ -138,7 +138,7 @@ namespace {
 class ProcessInterfaceVarABI final : public SPIRVOpLowering<spirv::FuncOp> {
 public:
   using SPIRVOpLowering<spirv::FuncOp>::SPIRVOpLowering;
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(spirv::FuncOp funcOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
@@ -151,13 +151,13 @@ class LowerABIAttributesPass final
 };
 } // namespace
 
-PatternMatchResult ProcessInterfaceVarABI::matchAndRewrite(
+LogicalResult ProcessInterfaceVarABI::matchAndRewrite(
     spirv::FuncOp funcOp, ArrayRef<Value> operands,
     ConversionPatternRewriter &rewriter) const {
   if (!funcOp.getAttrOfType<spirv::EntryPointABIAttr>(
           spirv::getEntryPointABIAttrName())) {
     // TODO(ravishankarm) : Non-entry point functions are not handled.
-    return matchFailure();
+    return failure();
   }
   TypeConverter::SignatureConversion signatureConverter(
       funcOp.getType().getNumInputs());
@@ -171,12 +171,12 @@ PatternMatchResult ProcessInterfaceVarABI::matchAndRewrite(
       // to pass around scalar/vector values and return a scalar/vector. For now
       // non-entry point functions are not handled in this ABI lowering and will
       // produce an error.
-      return matchFailure();
+      return failure();
     }
     auto var =
         createGlobalVariableForArg(funcOp, rewriter, argType.index(), abiInfo);
     if (!var) {
-      return matchFailure();
+      return failure();
     }
 
     OpBuilder::InsertionGuard funcInsertionGuard(rewriter);
@@ -207,7 +207,7 @@ PatternMatchResult ProcessInterfaceVarABI::matchAndRewrite(
         signatureConverter.getConvertedTypes(), llvm::None));
     rewriter.applySignatureConversion(&funcOp.getBody(), signatureConverter);
   });
-  return matchSuccess();
+  return success();
 }
 
 void LowerABIAttributesPass::runOnOperation() {
diff --git a/mlir/lib/Dialect/Shape/CMakeLists.txt b/mlir/lib/Dialect/Shape/CMakeLists.txt
index de3ddfce8771a..485a3c710abb5 100644
--- a/mlir/lib/Dialect/Shape/CMakeLists.txt
+++ b/mlir/lib/Dialect/Shape/CMakeLists.txt
@@ -1,12 +1,15 @@
-file(GLOB globbed *.c *.cpp)
 add_mlir_dialect_library(MLIRShape
-  ${globbed}
+  IR/Shape.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/Shape
+
+  DEPENDS
+  MLIRShapeOpsIncGen
   )
-add_dependencies(MLIRShape MLIRShapeOpsIncGen LLVMSupport)
 target_link_libraries(MLIRShape
   PUBLIC
+  MLIRIR
   MLIRSideEffects
-  LLVMSupport)
+  LLVMSupport
+  )
diff --git a/mlir/lib/Dialect/Shape/DialectRegistration.cpp b/mlir/lib/Dialect/Shape/DialectRegistration.cpp
deleted file mode 100644
index 818ac149453cc..0000000000000
--- a/mlir/lib/Dialect/Shape/DialectRegistration.cpp
+++ /dev/null
@@ -1,13 +0,0 @@
-//===- DialectRegistration.cpp - Register shape dialect -------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "mlir/Dialect/Shape/IR/Shape.h"
-using namespace mlir;
-
-// Static initialization for shape dialect registration.
-static DialectRegistration<shape::ShapeDialect> ShapeOps;
diff --git a/mlir/lib/Dialect/Shape/IR/Shape.cpp b/mlir/lib/Dialect/Shape/IR/Shape.cpp
new file mode 100644
index 0000000000000..f7f69a64826b1
--- /dev/null
+++ b/mlir/lib/Dialect/Shape/IR/Shape.cpp
@@ -0,0 +1,116 @@
+//===- Shape.cpp - MLIR Shape Operations ----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/Shape/IR/Shape.h"
+
+#include "mlir/IR/Builders.h"
+#include "mlir/IR/DialectImplementation.h"
+#include "mlir/IR/StandardTypes.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace mlir;
+using namespace mlir::shape;
+
+ShapeDialect::ShapeDialect(MLIRContext *context)
+    : Dialect(getDialectNamespace(), context) {
+  addOperations<
+#define GET_OP_LIST
+#include "mlir/Dialect/Shape/IR/ShapeOps.cpp.inc"
+      >();
+  addTypes<ComponentType, ElementType, ShapeType, SizeType, ValueShapeType>();
+  // Allow unknown operations during prototyping and testing. As the dialect is
+  // still evolving it makes it simple to start with an unregistered ops and
+  // try different variants before actually defining the op.
+  allowUnknownOperations();
+}
+
+/// Parse a type registered to this dialect.
+Type ShapeDialect::parseType(DialectAsmParser &parser) const {
+  StringRef keyword;
+  if (parser.parseKeyword(&keyword))
+    return Type();
+
+  if (keyword == "component")
+    return ComponentType::get(getContext());
+  if (keyword == "element")
+    return ElementType::get(getContext());
+  if (keyword == "shape")
+    return ShapeType::get(getContext());
+  if (keyword == "size")
+    return SizeType::get(getContext());
+  if (keyword == "value_shape")
+    return ValueShapeType::get(getContext());
+
+  parser.emitError(parser.getNameLoc(), "unknown shape type: ") << keyword;
+  return Type();
+}
+
+/// Print a type registered to this dialect.
+void ShapeDialect::printType(Type type, DialectAsmPrinter &os) const {
+  switch (type.getKind()) {
+  case ShapeTypes::Component:
+    os << "component";
+    return;
+  case ShapeTypes::Element:
+    os << "element";
+    return;
+  case ShapeTypes::Size:
+    os << "size";
+    return;
+  case ShapeTypes::Shape:
+    os << "shape";
+    return;
+  case ShapeTypes::ValueShape:
+    os << "value_shape";
+    return;
+  default:
+    llvm_unreachable("unexpected 'shape' type kind");
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// Constant*Op
+//===----------------------------------------------------------------------===//
+
+static void print(OpAsmPrinter &p, ConstantOp &op) {
+  p << "shape.constant ";
+  p.printOptionalAttrDict(op.getAttrs(), /*elidedAttrs=*/{"value"});
+
+  if (op.getAttrs().size() > 1)
+    p << ' ';
+  p.printAttributeWithoutType(op.value());
+  p << " : " << op.getType();
+}
+
+static ParseResult parseConstantOp(OpAsmParser &parser,
+                                   OperationState &result) {
+  Attribute valueAttr;
+  if (parser.parseOptionalAttrDict(result.attributes))
+    return failure();
+  Type i64Type = parser.getBuilder().getIntegerType(64);
+  if (parser.parseAttribute(valueAttr, i64Type, "value", result.attributes))
+    return failure();
+
+  Type type;
+  if (parser.parseColonType(type))
+    return failure();
+
+  // Add the attribute type to the list.
+  return parser.addTypeToList(type, result.types);
+}
+
+static LogicalResult verify(ConstantOp &op) { return success(); }
+
+namespace mlir {
+namespace shape {
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/Shape/IR/ShapeOps.cpp.inc"
+
+} // namespace shape
+} // namespace mlir
diff --git a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp
index 0560a0f19526b..0c6d4647b933e 100644
--- a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp
+++ b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp
@@ -313,14 +313,14 @@ namespace {
 struct SimplifyAllocConst : public OpRewritePattern<AllocOp> {
   using OpRewritePattern<AllocOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AllocOp alloc,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AllocOp alloc,
+                                PatternRewriter &rewriter) const override {
     // Check to see if any dimensions operands are constants.  If so, we can
     // substitute and drop them.
     if (llvm::none_of(alloc.getOperands(), [](Value operand) {
           return matchPattern(operand, m_ConstantIndex());
         }))
-      return matchFailure();
+      return failure();
 
     auto memrefType = alloc.getType();
 
@@ -364,7 +364,7 @@ struct SimplifyAllocConst : public OpRewritePattern<AllocOp> {
                                                     alloc.getType());
 
     rewriter.replaceOp(alloc, {resultCast});
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -373,13 +373,13 @@ struct SimplifyAllocConst : public OpRewritePattern<AllocOp> {
 struct SimplifyDeadAlloc : public OpRewritePattern<AllocOp> {
   using OpRewritePattern<AllocOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(AllocOp alloc,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(AllocOp alloc,
+                                PatternRewriter &rewriter) const override {
     if (alloc.use_empty()) {
       rewriter.eraseOp(alloc);
-      return matchSuccess();
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 };
 } // end anonymous namespace.
@@ -461,18 +461,18 @@ namespace {
 struct SimplifyBrToBlockWithSinglePred : public OpRewritePattern<BranchOp> {
   using OpRewritePattern<BranchOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(BranchOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(BranchOp op,
+                                PatternRewriter &rewriter) const override {
     // Check that the successor block has a single predecessor.
     Block *succ = op.getDest();
     Block *opParent = op.getOperation()->getBlock();
     if (succ == opParent || !has_single_element(succ->getPredecessors()))
-      return matchFailure();
+      return failure();
 
     // Merge the successor into the current block and erase the branch.
     rewriter.mergeBlocks(succ, opParent, op.getOperands());
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 } // end anonymous namespace.
@@ -545,18 +545,18 @@ struct SimplifyIndirectCallWithKnownCallee
     : public OpRewritePattern<CallIndirectOp> {
   using OpRewritePattern<CallIndirectOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(CallIndirectOp indirectCall,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(CallIndirectOp indirectCall,
+                                PatternRewriter &rewriter) const override {
     // Check that the callee is a constant callee.
     SymbolRefAttr calledFn;
     if (!matchPattern(indirectCall.getCallee(), m_Constant(&calledFn)))
-      return matchFailure();
+      return failure();
 
     // Replace with a direct call.
     rewriter.replaceOpWithNewOp<CallOp>(indirectCall, calledFn,
                                         indirectCall.getResultTypes(),
                                         indirectCall.getArgOperands());
-    return matchSuccess();
+    return success();
   }
 };
 } // end anonymous namespace.
@@ -733,20 +733,20 @@ namespace {
 struct SimplifyConstCondBranchPred : public OpRewritePattern<CondBranchOp> {
   using OpRewritePattern<CondBranchOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(CondBranchOp condbr,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(CondBranchOp condbr,
+                                PatternRewriter &rewriter) const override {
     if (matchPattern(condbr.getCondition(), m_NonZero())) {
       // True branch taken.
       rewriter.replaceOpWithNewOp<BranchOp>(condbr, condbr.getTrueDest(),
                                             condbr.getTrueOperands());
-      return matchSuccess();
+      return success();
     } else if (matchPattern(condbr.getCondition(), m_Zero())) {
       // False branch taken.
       rewriter.replaceOpWithNewOp<BranchOp>(condbr, condbr.getFalseDest(),
                                             condbr.getFalseOperands());
-      return matchSuccess();
+      return success();
     }
-    return matchFailure();
+    return failure();
   }
 };
 } // end anonymous namespace.
@@ -958,21 +958,21 @@ namespace {
 struct SimplifyDeadDealloc : public OpRewritePattern<DeallocOp> {
   using OpRewritePattern<DeallocOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(DeallocOp dealloc,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(DeallocOp dealloc,
+                                PatternRewriter &rewriter) const override {
     // Check that the memref operand's defining operation is an AllocOp.
     Value memref = dealloc.memref();
     if (!isa_and_nonnull<AllocOp>(memref.getDefiningOp()))
-      return matchFailure();
+      return failure();
 
     // Check that all of the uses of the AllocOp are other DeallocOps.
     for (auto *user : memref.getUsers())
       if (!isa<DeallocOp>(user))
-        return matchFailure();
+        return failure();
 
     // Erase the dealloc operation.
     rewriter.eraseOp(dealloc);
-    return matchSuccess();
+    return success();
   }
 };
 } // end anonymous namespace.
@@ -2003,8 +2003,8 @@ class SubViewOpShapeFolder final : public OpRewritePattern<SubViewOp> {
 public:
   using OpRewritePattern<SubViewOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(SubViewOp subViewOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(SubViewOp subViewOp,
+                                PatternRewriter &rewriter) const override {
     MemRefType subViewType = subViewOp.getType();
     // Follow all or nothing approach for shapes for now. If all the operands
     // for sizes are constants then fold it into the type of the result memref.
@@ -2012,7 +2012,7 @@ class SubViewOpShapeFolder final : public OpRewritePattern<SubViewOp> {
         llvm::any_of(subViewOp.sizes(), [](Value operand) {
           return !matchPattern(operand, m_ConstantIndex());
         })) {
-      return matchFailure();
+      return failure();
     }
     SmallVector<int64_t, 4> staticShape(subViewOp.getNumSizes());
     for (auto size : llvm::enumerate(subViewOp.sizes())) {
@@ -2028,7 +2028,7 @@ class SubViewOpShapeFolder final : public OpRewritePattern<SubViewOp> {
     // Insert a memref_cast for compatibility of the uses of the op.
     rewriter.replaceOpWithNewOp<MemRefCastOp>(subViewOp, newSubViewOp,
                                               subViewOp.getType());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2037,10 +2037,10 @@ class SubViewOpStrideFolder final : public OpRewritePattern<SubViewOp> {
 public:
   using OpRewritePattern<SubViewOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(SubViewOp subViewOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(SubViewOp subViewOp,
+                                PatternRewriter &rewriter) const override {
     if (subViewOp.getNumStrides() == 0) {
-      return matchFailure();
+      return failure();
     }
     // Follow all or nothing approach for strides for now. If all the operands
     // for strides are constants then fold it into the strides of the result
@@ -2056,7 +2056,7 @@ class SubViewOpStrideFolder final : public OpRewritePattern<SubViewOp> {
         llvm::any_of(subViewOp.strides(), [](Value stride) {
           return !matchPattern(stride, m_ConstantIndex());
         })) {
-      return matchFailure();
+      return failure();
     }
 
     SmallVector<int64_t, 4> staticStrides(subViewOp.getNumStrides());
@@ -2077,7 +2077,7 @@ class SubViewOpStrideFolder final : public OpRewritePattern<SubViewOp> {
     // Insert a memref_cast for compatibility of the uses of the op.
     rewriter.replaceOpWithNewOp<MemRefCastOp>(subViewOp, newSubViewOp,
                                               subViewOp.getType());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2086,10 +2086,10 @@ class SubViewOpOffsetFolder final : public OpRewritePattern<SubViewOp> {
 public:
   using OpRewritePattern<SubViewOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(SubViewOp subViewOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(SubViewOp subViewOp,
+                                PatternRewriter &rewriter) const override {
     if (subViewOp.getNumOffsets() == 0) {
-      return matchFailure();
+      return failure();
     }
     // Follow all or nothing approach for offsets for now. If all the operands
     // for offsets are constants then fold it into the offset of the result
@@ -2106,7 +2106,7 @@ class SubViewOpOffsetFolder final : public OpRewritePattern<SubViewOp> {
         llvm::any_of(subViewOp.offsets(), [](Value stride) {
           return !matchPattern(stride, m_ConstantIndex());
         })) {
-      return matchFailure();
+      return failure();
     }
 
     auto staticOffset = baseOffset;
@@ -2128,7 +2128,7 @@ class SubViewOpOffsetFolder final : public OpRewritePattern<SubViewOp> {
     // Insert a memref_cast for compatibility of the uses of the op.
     rewriter.replaceOpWithNewOp<MemRefCastOp>(subViewOp, newSubViewOp,
                                               subViewOp.getType());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -2347,18 +2347,18 @@ namespace {
 struct ViewOpShapeFolder : public OpRewritePattern<ViewOp> {
   using OpRewritePattern<ViewOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(ViewOp viewOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(ViewOp viewOp,
+                                PatternRewriter &rewriter) const override {
     // Return if none of the operands are constants.
     if (llvm::none_of(viewOp.getOperands(), [](Value operand) {
           return matchPattern(operand, m_ConstantIndex());
         }))
-      return matchFailure();
+      return failure();
 
     // Get result memref type.
     auto memrefType = viewOp.getType();
     if (memrefType.getAffineMaps().size() > 1)
-      return matchFailure();
+      return failure();
     auto map = memrefType.getAffineMaps().empty()
                    ? AffineMap::getMultiDimIdentityMap(memrefType.getRank(),
                                                        rewriter.getContext())
@@ -2368,7 +2368,7 @@ struct ViewOpShapeFolder : public OpRewritePattern<ViewOp> {
     int64_t oldOffset;
     SmallVector<int64_t, 4> oldStrides;
     if (failed(getStridesAndOffset(memrefType, oldStrides, oldOffset)))
-      return matchFailure();
+      return failure();
 
     SmallVector<Value, 4> newOperands;
 
@@ -2444,27 +2444,27 @@ struct ViewOpShapeFolder : public OpRewritePattern<ViewOp> {
     // Insert a cast so we have the same type as the old memref type.
     rewriter.replaceOpWithNewOp<MemRefCastOp>(viewOp, newViewOp,
                                               viewOp.getType());
-    return matchSuccess();
+    return success();
   }
 };
 
 struct ViewOpMemrefCastFolder : public OpRewritePattern<ViewOp> {
   using OpRewritePattern<ViewOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(ViewOp viewOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(ViewOp viewOp,
+                                PatternRewriter &rewriter) const override {
     Value memrefOperand = viewOp.getOperand(0);
     MemRefCastOp memrefCastOp =
         dyn_cast_or_null<MemRefCastOp>(memrefOperand.getDefiningOp());
     if (!memrefCastOp)
-      return matchFailure();
+      return failure();
     Value allocOperand = memrefCastOp.getOperand();
     AllocOp allocOp = dyn_cast_or_null<AllocOp>(allocOperand.getDefiningOp());
     if (!allocOp)
-      return matchFailure();
+      return failure();
     rewriter.replaceOpWithNewOp<ViewOp>(viewOp, viewOp.getType(), allocOperand,
                                         viewOp.operands());
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/lib/Dialect/VectorOps/CMakeLists.txt b/mlir/lib/Dialect/Vector/CMakeLists.txt
similarity index 70%
rename from mlir/lib/Dialect/VectorOps/CMakeLists.txt
rename to mlir/lib/Dialect/Vector/CMakeLists.txt
index ad32f271a90f4..3e1d8de0d3ba4 100644
--- a/mlir/lib/Dialect/VectorOps/CMakeLists.txt
+++ b/mlir/lib/Dialect/Vector/CMakeLists.txt
@@ -1,17 +1,17 @@
-add_mlir_dialect_library(MLIRVectorOps
+add_mlir_dialect_library(MLIRVector
   VectorOps.cpp
   VectorTransforms.cpp
   VectorUtils.cpp
   EDSC/Builders.cpp
 
   ADDITIONAL_HEADER_DIRS
-  ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/VectorOps
+  ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/Vector
 
   DEPENDS
   MLIRVectorOpsIncGen
   MLIRVectorTransformPatternsIncGen
   )
-target_link_libraries(MLIRVectorOps
+target_link_libraries(MLIRVector
   PUBLIC
   MLIREDSC
   MLIRIR
diff --git a/mlir/lib/Dialect/VectorOps/EDSC/Builders.cpp b/mlir/lib/Dialect/Vector/EDSC/Builders.cpp
similarity index 91%
rename from mlir/lib/Dialect/VectorOps/EDSC/Builders.cpp
rename to mlir/lib/Dialect/Vector/EDSC/Builders.cpp
index 163000f1cac14..b1f94655ab28b 100644
--- a/mlir/lib/Dialect/VectorOps/EDSC/Builders.cpp
+++ b/mlir/lib/Dialect/Vector/EDSC/Builders.cpp
@@ -6,9 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/VectorOps/EDSC/Builders.h"
-#include "mlir/Dialect/VectorOps/EDSC/Intrinsics.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/EDSC/Builders.h"
+#include "mlir/Dialect/Vector/EDSC/Intrinsics.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/EDSC/Builders.h"
 #include "mlir/EDSC/Intrinsics.h"
 #include "mlir/IR/AffineExpr.h"
diff --git a/mlir/lib/Dialect/VectorOps/VectorOps.cpp b/mlir/lib/Dialect/Vector/VectorOps.cpp
similarity index 98%
rename from mlir/lib/Dialect/VectorOps/VectorOps.cpp
rename to mlir/lib/Dialect/Vector/VectorOps.cpp
index 5afa944c776b6..342ce37ad5157 100644
--- a/mlir/lib/Dialect/VectorOps/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/VectorOps.cpp
@@ -11,10 +11,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Utils/StructuredOpsUtils.h"
-#include "mlir/Dialect/VectorOps/VectorUtils.h"
+#include "mlir/Dialect/Vector/VectorUtils.h"
 #include "mlir/IR/AffineExpr.h"
 #include "mlir/IR/AffineMap.h"
 #include "mlir/IR/Builders.h"
@@ -32,20 +32,20 @@ using namespace mlir;
 using namespace mlir::vector;
 
 //===----------------------------------------------------------------------===//
-// VectorOpsDialect
+// VectorDialect
 //===----------------------------------------------------------------------===//
 
-VectorOpsDialect::VectorOpsDialect(MLIRContext *context)
+VectorDialect::VectorDialect(MLIRContext *context)
     : Dialect(getDialectNamespace(), context) {
   addOperations<
 #define GET_OP_LIST
-#include "mlir/Dialect/VectorOps/VectorOps.cpp.inc"
+#include "mlir/Dialect/Vector/VectorOps.cpp.inc"
       >();
 }
 
 /// Materialize a single constant operation from a given attribute value with
 /// the desired resultant type.
-Operation *VectorOpsDialect::materializeConstant(OpBuilder &builder,
+Operation *VectorDialect::materializeConstant(OpBuilder &builder,
                                                  Attribute value, Type type,
                                                  Location loc) {
   return builder.create<ConstantOp>(loc, type, value);
@@ -1145,18 +1145,18 @@ class StridedSliceConstantMaskFolder final
 public:
   using OpRewritePattern<StridedSliceOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(StridedSliceOp stridedSliceOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(StridedSliceOp stridedSliceOp,
+                                PatternRewriter &rewriter) const override {
     // Return if 'stridedSliceOp' operand is not defined by a ConstantMaskOp.
     auto defOp = stridedSliceOp.vector().getDefiningOp();
     auto constantMaskOp = dyn_cast_or_null<ConstantMaskOp>(defOp);
     if (!constantMaskOp)
-      return matchFailure();
+      return failure();
     // Return if 'stridedSliceOp' has non-unit strides.
     if (llvm::any_of(stridedSliceOp.strides(), [](Attribute attr) {
           return attr.cast<IntegerAttr>().getInt() != 1;
         }))
-      return matchFailure();
+      return failure();
     // Gather constant mask dimension sizes.
     SmallVector<int64_t, 4> maskDimSizes;
     populateFromInt64AttrArray(constantMaskOp.mask_dim_sizes(), maskDimSizes);
@@ -1187,7 +1187,7 @@ class StridedSliceConstantMaskFolder final
     rewriter.replaceOpWithNewOp<ConstantMaskOp>(
         stridedSliceOp, stridedSliceOp.getResult().getType(),
         vector::getVectorSubscriptAttr(rewriter, sliceMaskDimSizes));
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1249,7 +1249,7 @@ static LogicalResult verifyTransferOp(Operation *op, MemRefType memrefType,
     if (memrefVecEltRank > resultVecRank)
       return op->emitOpError(
           "requires memref vector element and vector result ranks to match.");
-    // TODO(b/146516564) Move this to isSuffix in VectorOps/Utils.h.
+    // TODO(b/146516564) Move this to isSuffix in Vector/Utils.h.
     unsigned rankOffset = resultVecRank - memrefVecEltRank;
     auto memrefVecEltShape = memrefVectorElementType.getShape();
     auto resultVecShape = vectorType.getShape();
@@ -1619,14 +1619,14 @@ class CreateMaskFolder final : public OpRewritePattern<CreateMaskOp> {
 public:
   using OpRewritePattern<CreateMaskOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(CreateMaskOp createMaskOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(CreateMaskOp createMaskOp,
+                                PatternRewriter &rewriter) const override {
     // Return if any of 'createMaskOp' operands are not defined by a constant.
     auto is_not_def_by_constant = [](Value operand) {
       return !isa_and_nonnull<ConstantIndexOp>(operand.getDefiningOp());
     };
     if (llvm::any_of(createMaskOp.operands(), is_not_def_by_constant))
-      return matchFailure();
+      return failure();
     // Gather constant mask dimension sizes.
     SmallVector<int64_t, 4> maskDimSizes;
     for (auto operand : createMaskOp.operands()) {
@@ -1637,7 +1637,7 @@ class CreateMaskFolder final : public OpRewritePattern<CreateMaskOp> {
     rewriter.replaceOpWithNewOp<ConstantMaskOp>(
         createMaskOp, createMaskOp.getResult().getType(),
         vector::getVectorSubscriptAttr(rewriter, maskDimSizes));
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1657,7 +1657,7 @@ namespace mlir {
 namespace vector {
 
 #define GET_OP_CLASSES
-#include "mlir/Dialect/VectorOps/VectorOps.cpp.inc"
+#include "mlir/Dialect/Vector/VectorOps.cpp.inc"
 
 } // namespace vector
 } // namespace mlir
diff --git a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp b/mlir/lib/Dialect/Vector/VectorTransforms.cpp
similarity index 92%
rename from mlir/lib/Dialect/VectorOps/VectorTransforms.cpp
rename to mlir/lib/Dialect/Vector/VectorTransforms.cpp
index 4f6634d2be272..dd47e0c80dc1f 100644
--- a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp
+++ b/mlir/lib/Dialect/Vector/VectorTransforms.cpp
@@ -15,9 +15,9 @@
 #include "mlir/Dialect/AffineOps/AffineOps.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Utils/StructuredOpsUtils.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
-#include "mlir/Dialect/VectorOps/VectorTransforms.h"
-#include "mlir/Dialect/VectorOps/VectorUtils.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorTransforms.h"
+#include "mlir/Dialect/Vector/VectorUtils.h"
 #include "mlir/IR/AffineExpr.h"
 #include "mlir/IR/AffineMap.h"
 #include "mlir/IR/Attributes.h"
@@ -42,13 +42,6 @@ using namespace mlir;
 using llvm::dbgs;
 using mlir::functional::zipMap;
 
-static llvm::cl::OptionCategory clOptionsCategory(DEBUG_TYPE " options");
-
-static llvm::cl::opt<bool> lowerToLLVMMatrixIntrinsics(
-    "vector-lower-matrix-intrinsics",
-    llvm::cl::desc("Lower vector.contract to llvm.intr.matrix.multiply"),
-    llvm::cl::init(false), llvm::cl::cat(clOptionsCategory));
-
 /// Given a shape with sizes greater than 0 along all dimensions,
 /// returns the distance, in number of elements, between a slice in a dimension
 /// and the next slice in the same dimension.
@@ -552,18 +545,18 @@ namespace {
 struct SplitTransferReadOp : public OpRewritePattern<vector::TransferReadOp> {
   using OpRewritePattern<vector::TransferReadOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::TransferReadOp xferReadOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::TransferReadOp xferReadOp,
+                                PatternRewriter &rewriter) const override {
     // TODO(andydavis, ntv) Support splitting TransferReadOp with non-identity
     // permutation maps. Repurpose code from MaterializeVectors transformation.
     if (!isIdentitySuffix(xferReadOp.permutation_map()))
-      return matchFailure();
+      return failure();
     // Return unless the unique 'xferReadOp' user is an ExtractSlicesOp.
     Value xferReadResult = xferReadOp.getResult();
     auto extractSlicesOp =
         dyn_cast<vector::ExtractSlicesOp>(*xferReadResult.getUsers().begin());
     if (!xferReadResult.hasOneUse() || !extractSlicesOp)
-      return matchFailure();
+      return failure();
 
     // Get 'sizes' and 'strides' parameters from ExtractSlicesOp user.
     auto sourceVectorType = extractSlicesOp.getSourceVectorType();
@@ -600,7 +593,7 @@ struct SplitTransferReadOp : public OpRewritePattern<vector::TransferReadOp> {
     rewriter.replaceOpWithNewOp<vector::InsertSlicesOp>(
         xferReadOp, sourceVectorType, tupleOp, extractSlicesOp.sizes(),
         extractSlicesOp.strides());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -608,23 +601,23 @@ struct SplitTransferReadOp : public OpRewritePattern<vector::TransferReadOp> {
 struct SplitTransferWriteOp : public OpRewritePattern<vector::TransferWriteOp> {
   using OpRewritePattern<vector::TransferWriteOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::TransferWriteOp xferWriteOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::TransferWriteOp xferWriteOp,
+                                PatternRewriter &rewriter) const override {
     // TODO(andydavis, ntv) Support splitting TransferWriteOp with non-identity
     // permutation maps. Repurpose code from MaterializeVectors transformation.
     if (!isIdentitySuffix(xferWriteOp.permutation_map()))
-      return matchFailure();
+      return failure();
     // Return unless the 'xferWriteOp' 'vector' operand is an 'InsertSlicesOp'.
     auto *vectorDefOp = xferWriteOp.vector().getDefiningOp();
     auto insertSlicesOp = dyn_cast_or_null<vector::InsertSlicesOp>(vectorDefOp);
     if (!insertSlicesOp)
-      return matchFailure();
+      return failure();
 
     // Get TupleOp operand of 'insertSlicesOp'.
     auto tupleOp = dyn_cast_or_null<vector::TupleOp>(
         insertSlicesOp.vectors().getDefiningOp());
     if (!tupleOp)
-      return matchFailure();
+      return failure();
 
     // Get 'sizes' and 'strides' parameters from InsertSlicesOp user.
     auto sourceTupleType = insertSlicesOp.getSourceTupleType();
@@ -651,7 +644,7 @@ struct SplitTransferWriteOp : public OpRewritePattern<vector::TransferWriteOp> {
 
     // Erase old 'xferWriteOp'.
     rewriter.eraseOp(xferWriteOp);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -660,15 +653,15 @@ struct SplitTransferWriteOp : public OpRewritePattern<vector::TransferWriteOp> {
 struct ShapeCastOpDecomposer : public OpRewritePattern<vector::ShapeCastOp> {
   using OpRewritePattern<vector::ShapeCastOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::ShapeCastOp shapeCastOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::ShapeCastOp shapeCastOp,
+                                PatternRewriter &rewriter) const override {
     // Check if 'shapeCastOp' has tuple source/result type.
     auto sourceTupleType =
         shapeCastOp.source().getType().dyn_cast_or_null<TupleType>();
     auto resultTupleType =
         shapeCastOp.result().getType().dyn_cast_or_null<TupleType>();
     if (!sourceTupleType || !resultTupleType)
-      return matchFailure();
+      return failure();
     assert(sourceTupleType.size() == resultTupleType.size());
 
     // Create single-vector ShapeCastOp for each source tuple element.
@@ -686,7 +679,7 @@ struct ShapeCastOpDecomposer : public OpRewritePattern<vector::ShapeCastOp> {
     // Replace 'shapeCastOp' with tuple of 'resultElements'.
     rewriter.replaceOpWithNewOp<vector::TupleOp>(shapeCastOp, resultTupleType,
                                                  resultElements);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -709,21 +702,21 @@ struct ShapeCastOpDecomposer : public OpRewritePattern<vector::ShapeCastOp> {
 struct ShapeCastOpFolder : public OpRewritePattern<vector::ShapeCastOp> {
   using OpRewritePattern<vector::ShapeCastOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::ShapeCastOp shapeCastOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::ShapeCastOp shapeCastOp,
+                                PatternRewriter &rewriter) const override {
     // Check if 'shapeCastOp' has vector source/result type.
     auto sourceVectorType =
         shapeCastOp.source().getType().dyn_cast_or_null<VectorType>();
     auto resultVectorType =
         shapeCastOp.result().getType().dyn_cast_or_null<VectorType>();
     if (!sourceVectorType || !resultVectorType)
-      return matchFailure();
+      return failure();
 
     // Check if shape cast op source operand is also a shape cast op.
     auto sourceShapeCastOp = dyn_cast_or_null<vector::ShapeCastOp>(
         shapeCastOp.source().getDefiningOp());
     if (!sourceShapeCastOp)
-      return matchFailure();
+      return failure();
     auto operandSourceVectorType =
         sourceShapeCastOp.source().getType().cast<VectorType>();
     auto operandResultVectorType =
@@ -732,10 +725,10 @@ struct ShapeCastOpFolder : public OpRewritePattern<vector::ShapeCastOp> {
     // Check if shape cast operations invert each other.
     if (operandSourceVectorType != resultVectorType ||
         operandResultVectorType != sourceVectorType)
-      return matchFailure();
+      return failure();
 
     rewriter.replaceOp(shapeCastOp, sourceShapeCastOp.source());
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -745,30 +738,30 @@ struct ShapeCastOpFolder : public OpRewritePattern<vector::ShapeCastOp> {
 struct TupleGetFolderOp : public OpRewritePattern<vector::TupleGetOp> {
   using OpRewritePattern<vector::TupleGetOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::TupleGetOp tupleGetOp,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::TupleGetOp tupleGetOp,
+                                PatternRewriter &rewriter) const override {
     // Return if 'tupleGetOp.vectors' arg was not defined by ExtractSlicesOp.
     auto extractSlicesOp = dyn_cast_or_null<vector::ExtractSlicesOp>(
         tupleGetOp.vectors().getDefiningOp());
     if (!extractSlicesOp)
-      return matchFailure();
+      return failure();
 
     // Return if 'extractSlicesOp.vector' arg was not defined by InsertSlicesOp.
     auto insertSlicesOp = dyn_cast_or_null<vector::InsertSlicesOp>(
         extractSlicesOp.vector().getDefiningOp());
     if (!insertSlicesOp)
-      return matchFailure();
+      return failure();
 
     // Return if 'insertSlicesOp.vectors' arg was not defined by TupleOp.
     auto tupleOp = dyn_cast_or_null<vector::TupleOp>(
         insertSlicesOp.vectors().getDefiningOp());
     if (!tupleOp)
-      return matchFailure();
+      return failure();
 
     // Forward Value from 'tupleOp' at 'tupleGetOp.index'.
     Value tupleValue = tupleOp.getOperand(tupleGetOp.getIndex());
     rewriter.replaceOp(tupleGetOp, tupleValue);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -785,8 +778,8 @@ class ExtractSlicesOpLowering
 public:
   using OpRewritePattern<vector::ExtractSlicesOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::ExtractSlicesOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::ExtractSlicesOp op,
+                                PatternRewriter &rewriter) const override {
     auto loc = op.getLoc();
 
     VectorType vectorType = op.getSourceVectorType();
@@ -813,7 +806,7 @@ class ExtractSlicesOpLowering
     }
 
     rewriter.replaceOpWithNewOp<vector::TupleOp>(op, tupleType, tupleValues);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -832,8 +825,8 @@ class InsertSlicesOpLowering : public OpRewritePattern<vector::InsertSlicesOp> {
 public:
   using OpRewritePattern<vector::InsertSlicesOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::InsertSlicesOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::InsertSlicesOp op,
+                                PatternRewriter &rewriter) const override {
     auto loc = op.getLoc();
 
     VectorType vectorType = op.getResultVectorType();
@@ -867,7 +860,7 @@ class InsertSlicesOpLowering : public OpRewritePattern<vector::InsertSlicesOp> {
     }
 
     rewriter.replaceOp(op, result);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -888,8 +881,8 @@ class OuterProductOpLowering : public OpRewritePattern<vector::OuterProductOp> {
 public:
   using OpRewritePattern<vector::OuterProductOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::OuterProductOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::OuterProductOp op,
+                                PatternRewriter &rewriter) const override {
     auto loc = op.getLoc();
 
     VectorType rhsType = op.getOperandVectorTypeRHS();
@@ -914,7 +907,7 @@ class OuterProductOpLowering : public OpRewritePattern<vector::OuterProductOp> {
       result = rewriter.create<vector::InsertOp>(loc, resType, m, result, pos);
     }
     rewriter.replaceOp(op, result);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -936,43 +929,56 @@ class ContractionOpLowering : public OpRewritePattern<vector::ContractionOp> {
 public:
   using OpRewritePattern<vector::ContractionOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::ContractionOp op,
-                                     PatternRewriter &rewriter) const override {
+  ContractionOpLowering(vector::VectorTransformsOptions vectorTransformsOptions,
+                        MLIRContext *context)
+      : OpRewritePattern<vector::ContractionOp>(context),
+        vectorTransformsOptions(vectorTransformsOptions) {}
+
+  LogicalResult matchAndRewrite(vector::ContractionOp op,
+                                PatternRewriter &rewriter) const override {
     // TODO(ajcbik): implement masks
     if (llvm::size(op.masks()) != 0)
-      return matchFailure();
+      return failure();
 
     // TODO(ntv, ajcbik): implement benefits, cost models, separate this out in
     // a new pattern.
     // TODO(ntv, fhahn): once row-major mode is available in LLVM's matrix
     // intrinsics, use that.
-    if (lowerToLLVMMatrixIntrinsics &&
+    if (vectorTransformsOptions.lowerToLLVMMatrixIntrinsics &&
         isColumnMajorMatmul(op.indexing_maps())) {
       VectorType lhsType = op.getLhsType();
       VectorType rhsType = op.getRhsType();
-      Type flattenedLHSType =
-          VectorType::get(lhsType.getNumElements(), lhsType.getElementType());
-      Type flattenedRHSType =
-          VectorType::get(rhsType.getNumElements(), rhsType.getElementType());
-      auto lhs = rewriter.create<vector::ShapeCastOp>(
-          op.getLoc(), flattenedLHSType, op.lhs());
-      auto rhs = rewriter.create<vector::ShapeCastOp>(
-          op.getLoc(), flattenedRHSType, op.rhs());
-
       unsigned lhsRows = op.getLhsType().getShape()[0];
       unsigned lhsColumns = op.getLhsType().getShape()[1];
       unsigned rhsColumns = op.getRhsType().getShape()[1];
-      Value mul = rewriter.create<vector::MatmulOp>(
-          op.getLoc(), lhs, rhs, lhsRows, lhsColumns, rhsColumns);
-      mul = rewriter.create<vector::ShapeCastOp>(op.getLoc(),
-                                                 op.acc().getType(), mul);
-      Type elementType = op.getLhsType().getElementType();
-      assert(elementType.isIntOrFloat());
-      if (elementType.isa<IntegerType>())
-        rewriter.replaceOpWithNewOp<AddIOp>(op, op.acc(), mul);
-      else
-        rewriter.replaceOpWithNewOp<AddFOp>(op, op.acc(), mul);
-      return matchSuccess();
+
+      // In cases where matrices are degenerate, scalarization issues occur in
+      // the backend. Avoid all LLVM scalarization issues for now.
+      // For more details, see: https://bugs.llvm.org/show_bug.cgi?id=45227 and
+      // https://bugs.llvm.org/show_bug.cgi?id=45229
+      // TODO(ntv, fhahn): Relax once above bugs are fixed.
+      if (lhsRows != 1 && lhsColumns != 1 && rhsColumns != 1) {
+        Type flattenedLHSType =
+            VectorType::get(lhsType.getNumElements(), lhsType.getElementType());
+        Type flattenedRHSType =
+            VectorType::get(rhsType.getNumElements(), rhsType.getElementType());
+        auto lhs = rewriter.create<vector::ShapeCastOp>(
+            op.getLoc(), flattenedLHSType, op.lhs());
+        auto rhs = rewriter.create<vector::ShapeCastOp>(
+            op.getLoc(), flattenedRHSType, op.rhs());
+
+        Value mul = rewriter.create<vector::MatmulOp>(
+            op.getLoc(), lhs, rhs, lhsRows, lhsColumns, rhsColumns);
+        mul = rewriter.create<vector::ShapeCastOp>(op.getLoc(),
+                                                   op.acc().getType(), mul);
+        Type elementType = op.getLhsType().getElementType();
+        assert(elementType.isIntOrFloat());
+        if (elementType.isa<IntegerType>())
+          rewriter.replaceOpWithNewOp<AddIOp>(op, op.acc(), mul);
+        else
+          rewriter.replaceOpWithNewOp<AddFOp>(op, op.acc(), mul);
+        return success();
+      }
     }
 
     // Find first batch dimension in LHS/RHS, and lower when found.
@@ -981,7 +987,7 @@ class ContractionOpLowering : public OpRewritePattern<vector::ContractionOp> {
       int64_t lhsIndex = batchDimMap[0].first;
       int64_t rhsIndex = batchDimMap[0].second;
       rewriter.replaceOp(op, lowerParallel(op, lhsIndex, rhsIndex, rewriter));
-      return matchSuccess();
+      return success();
     }
 
     // Collect contracting dimensions.
@@ -1001,7 +1007,7 @@ class ContractionOpLowering : public OpRewritePattern<vector::ContractionOp> {
       if (lhsContractingDimSet.count(lhsIndex) == 0) {
         rewriter.replaceOp(
             op, lowerParallel(op, lhsIndex, /*rhsIndex=*/-1, rewriter));
-        return matchSuccess();
+        return success();
       }
     }
 
@@ -1012,17 +1018,17 @@ class ContractionOpLowering : public OpRewritePattern<vector::ContractionOp> {
       if (rhsContractingDimSet.count(rhsIndex) == 0) {
         rewriter.replaceOp(
             op, lowerParallel(op, /*lhsIndex=*/-1, rhsIndex, rewriter));
-        return matchSuccess();
+        return success();
       }
     }
 
     // Lower the first remaining reduction dimension.
     if (!contractingDimMap.empty()) {
       rewriter.replaceOp(op, lowerReduction(op, rewriter));
-      return matchSuccess();
+      return success();
     }
 
-    return matchFailure();
+    return failure();
   }
 
 private:
@@ -1255,6 +1261,8 @@ class ContractionOpLowering : public OpRewritePattern<vector::ContractionOp> {
     }
     return result;
   }
+
+  vector::VectorTransformsOptions vectorTransformsOptions;
 };
 
 /// ShapeOp 2D -> 1D downcast serves the purpose of flattening 2-D to 1-D
@@ -1267,12 +1275,12 @@ class ShapeCastOp2DDownCastRewritePattern
 public:
   using OpRewritePattern<vector::ShapeCastOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::ShapeCastOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::ShapeCastOp op,
+                                PatternRewriter &rewriter) const override {
     auto sourceVectorType = op.getSourceVectorType();
     auto resultVectorType = op.getResultVectorType();
     if (sourceVectorType.getRank() != 2 || resultVectorType.getRank() != 1)
-      return matchFailure();
+      return failure();
 
     auto loc = op.getLoc();
     auto elemType = sourceVectorType.getElementType();
@@ -1287,7 +1295,7 @@ class ShapeCastOp2DDownCastRewritePattern
           /*offsets=*/i * mostMinorVectorSize, /*strides=*/1);
     }
     rewriter.replaceOp(op, desc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1301,12 +1309,12 @@ class ShapeCastOp2DUpCastRewritePattern
 public:
   using OpRewritePattern<vector::ShapeCastOp>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(vector::ShapeCastOp op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(vector::ShapeCastOp op,
+                                PatternRewriter &rewriter) const override {
     auto sourceVectorType = op.getSourceVectorType();
     auto resultVectorType = op.getResultVectorType();
     if (sourceVectorType.getRank() != 1 || resultVectorType.getRank() != 2)
-      return matchFailure();
+      return failure();
 
     auto loc = op.getLoc();
     auto elemType = sourceVectorType.getElementType();
@@ -1322,7 +1330,7 @@ class ShapeCastOp2DUpCastRewritePattern
       desc = rewriter.create<vector::InsertOp>(loc, vec, desc, i);
     }
     rewriter.replaceOp(op, desc);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -1342,8 +1350,10 @@ void mlir::vector::populateVectorSlicesLoweringPatterns(
 }
 
 void mlir::vector::populateVectorContractLoweringPatterns(
-    OwningRewritePatternList &patterns, MLIRContext *context) {
-  patterns.insert<ContractionOpLowering, ShapeCastOp2DDownCastRewritePattern,
+    OwningRewritePatternList &patterns, MLIRContext *context,
+    VectorTransformsOptions parameters) {
+  patterns.insert<ShapeCastOp2DDownCastRewritePattern,
                   ShapeCastOp2DUpCastRewritePattern, OuterProductOpLowering>(
       context);
+  patterns.insert<ContractionOpLowering>(parameters, context);
 }
diff --git a/mlir/lib/Dialect/VectorOps/VectorUtils.cpp b/mlir/lib/Dialect/Vector/VectorUtils.cpp
similarity index 98%
rename from mlir/lib/Dialect/VectorOps/VectorUtils.cpp
rename to mlir/lib/Dialect/Vector/VectorUtils.cpp
index 0e76e853f2586..1cace25b9835e 100644
--- a/mlir/lib/Dialect/VectorOps/VectorUtils.cpp
+++ b/mlir/lib/Dialect/Vector/VectorUtils.cpp
@@ -6,15 +6,15 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements utility methods for working with the VectorOps dialect.
+// This file implements utility methods for working with the Vector dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/VectorOps/VectorUtils.h"
+#include "mlir/Dialect/Vector/VectorUtils.h"
 #include "mlir/Analysis/LoopAnalysis.h"
 #include "mlir/Dialect/AffineOps/AffineOps.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/IntegerSet.h"
 #include "mlir/IR/Operation.h"
diff --git a/mlir/lib/IR/AffineExpr.cpp b/mlir/lib/IR/AffineExpr.cpp
index 921538b4edc33..295b5155c29b4 100644
--- a/mlir/lib/IR/AffineExpr.cpp
+++ b/mlir/lib/IR/AffineExpr.cpp
@@ -314,6 +314,39 @@ static AffineExpr simplifyAdd(AffineExpr lhs, AffineExpr rhs) {
       return lBin.getLHS() + (lrhs.getValue() + rhsConst.getValue());
   }
 
+  // Detect "c1 * expr + c_2 * expr" as "(c1 + c2) * expr".
+  // c1 is rRhsConst, c2 is rLhsConst; firstExpr, secondExpr are their
+  // respective multiplicands.
+  Optional<int64_t> rLhsConst, rRhsConst;
+  AffineExpr firstExpr, secondExpr;
+  AffineConstantExpr rLhsConstExpr;
+  auto lBinOpExpr = lhs.dyn_cast<AffineBinaryOpExpr>();
+  if (lBinOpExpr && lBinOpExpr.getKind() == AffineExprKind::Mul &&
+      (rLhsConstExpr = lBinOpExpr.getRHS().dyn_cast<AffineConstantExpr>())) {
+    rLhsConst = rLhsConstExpr.getValue();
+    firstExpr = lBinOpExpr.getLHS();
+  } else {
+    rLhsConst = 1;
+    firstExpr = lhs;
+  }
+
+  auto rBinOpExpr = rhs.dyn_cast<AffineBinaryOpExpr>();
+  AffineConstantExpr rRhsConstExpr;
+  if (rBinOpExpr && rBinOpExpr.getKind() == AffineExprKind::Mul &&
+      (rRhsConstExpr = rBinOpExpr.getRHS().dyn_cast<AffineConstantExpr>())) {
+    rRhsConst = rRhsConstExpr.getValue();
+    secondExpr = rBinOpExpr.getLHS();
+  } else {
+    rRhsConst = 1;
+    secondExpr = rhs;
+  }
+
+  if (rLhsConst && rRhsConst && firstExpr == secondExpr)
+    return getAffineBinaryOpExpr(
+        AffineExprKind::Mul, firstExpr,
+        getAffineConstantExpr(rLhsConst.getValue() + rRhsConst.getValue(),
+                              lhs.getContext()));
+
   // When doing successive additions, bring constant to the right: turn (d0 + 2)
   // + d1 into (d0 + d1) + 2.
   if (lBin && lBin.getKind() == AffineExprKind::Add) {
@@ -327,7 +360,6 @@ static AffineExpr simplifyAdd(AffineExpr lhs, AffineExpr rhs) {
   // general a more compact and readable form.
 
   // Process '(expr floordiv c) * (-c)'.
-  AffineBinaryOpExpr rBinOpExpr = rhs.dyn_cast<AffineBinaryOpExpr>();
   if (!rBinOpExpr)
     return nullptr;
 
diff --git a/mlir/lib/IR/PatternMatch.cpp b/mlir/lib/IR/PatternMatch.cpp
index b111137e736aa..7d9fd5dd3c87f 100644
--- a/mlir/lib/IR/PatternMatch.cpp
+++ b/mlir/lib/IR/PatternMatch.cpp
@@ -39,17 +39,12 @@ void Pattern::anchor() {}
 // RewritePattern and PatternRewriter implementation
 //===----------------------------------------------------------------------===//
 
-void RewritePattern::rewrite(Operation *op, std::unique_ptr<PatternState> state,
-                             PatternRewriter &rewriter) const {
-  rewrite(op, rewriter);
-}
-
 void RewritePattern::rewrite(Operation *op, PatternRewriter &rewriter) const {
   llvm_unreachable("need to implement either matchAndRewrite or one of the "
                    "rewrite functions!");
 }
 
-PatternMatchResult RewritePattern::match(Operation *op) const {
+LogicalResult RewritePattern::match(Operation *op) const {
   llvm_unreachable("need to implement either match or matchAndRewrite!");
 }
 
@@ -191,7 +186,7 @@ bool RewritePatternMatcher::matchAndRewrite(Operation *op,
 
     // Try to match and rewrite this pattern. The patterns are sorted by
     // benefit, so if we match we can immediately rewrite and return.
-    if (pattern->matchAndRewrite(op, rewriter))
+    if (succeeded(pattern->matchAndRewrite(op, rewriter)))
       return true;
   }
   return false;
diff --git a/mlir/lib/Quantizer/Configurations/FxpMathConfig.cpp b/mlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
index 1dc9a0596a8be..4131a114d7cd3 100644
--- a/mlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
+++ b/mlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
@@ -15,8 +15,8 @@
 #include "mlir/Quantizer/Configurations/FxpMathConfig.h"
 
 #include "mlir/Dialect/FxpMathOps/FxpMathOps.h"
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/IR/Matchers.h"
 #include "mlir/IR/StandardTypes.h"
@@ -60,7 +60,7 @@ struct FxpMathTargetConfigImpl : public FxpMathTargetConfig {
     // Op handlers.
     addOpHandler<ConstantOp>(
         std::bind(&FxpMathTargetConfigImpl::handleConstant, this, _1, _2));
-    addOpHandler<ReturnOp>(
+    addOpHandler<mlir::ReturnOp>(
         std::bind(&FxpMathTargetConfigImpl::handleTerminal, this, _1, _2));
     addOpHandler<quant::StatisticsOp>(
         std::bind(&FxpMathTargetConfigImpl::handleStats, this, _1, _2));
diff --git a/mlir/lib/Quantizer/Support/UniformConstraints.cpp b/mlir/lib/Quantizer/Support/UniformConstraints.cpp
index fc8f8fc97a549..2372cdb005aa0 100644
--- a/mlir/lib/Quantizer/Support/UniformConstraints.cpp
+++ b/mlir/lib/Quantizer/Support/UniformConstraints.cpp
@@ -8,7 +8,7 @@
 
 #include "mlir/Quantizer/Support/UniformConstraints.h"
 
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/Diagnostics.h"
 #include "mlir/IR/Location.h"
 #include "mlir/IR/MLIRContext.h"
diff --git a/mlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp b/mlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp
index 51c3e185637f5..7a9627dd144e8 100644
--- a/mlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp
+++ b/mlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp
@@ -11,8 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/Quantizer/Configurations/FxpMathConfig.h"
diff --git a/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp b/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp
index 48c2ca2c075e5..1876b33b84214 100644
--- a/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp
+++ b/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp
@@ -12,8 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantTypes.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantTypes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/Quantizer/Configurations/FxpMathConfig.h"
 #include "mlir/Quantizer/Support/Configuration.h"
diff --git a/mlir/lib/Quantizer/Transforms/RemoveInstrumentationPass.cpp b/mlir/lib/Quantizer/Transforms/RemoveInstrumentationPass.cpp
index 4307c776fa153..0112753c49fc7 100644
--- a/mlir/lib/Quantizer/Transforms/RemoveInstrumentationPass.cpp
+++ b/mlir/lib/Quantizer/Transforms/RemoveInstrumentationPass.cpp
@@ -12,7 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
 #include "mlir/IR/MLIRContext.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/Pass/Pass.h"
@@ -35,13 +35,13 @@ class RemoveIdentityOpRewrite : public RewritePattern {
   RemoveIdentityOpRewrite(MLIRContext *context)
       : RewritePattern(OpTy::getOperationName(), 1, context) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override {
     assert(op->getNumOperands() == 1);
     assert(op->getNumResults() == 1);
 
     rewriter.replaceOp(op, op->getOperand(0));
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/lib/TableGen/Dialect.cpp b/mlir/lib/TableGen/Dialect.cpp
index 7e757eaeae4f4..db68ed43593f9 100644
--- a/mlir/lib/TableGen/Dialect.cpp
+++ b/mlir/lib/TableGen/Dialect.cpp
@@ -58,6 +58,18 @@ bool tblgen::Dialect::hasConstantMaterializer() const {
   return def->getValueAsBit("hasConstantMaterializer");
 }
 
+bool tblgen::Dialect::hasOperationAttrVerify() const {
+  return def->getValueAsBit("hasOperationAttrVerify");
+}
+
+bool tblgen::Dialect::hasRegionArgAttrVerify() const {
+  return def->getValueAsBit("hasRegionArgAttrVerify");
+}
+
+bool tblgen::Dialect::hasRegionResultAttrVerify() const {
+  return def->getValueAsBit("hasRegionResultAttrVerify");
+}
+
 bool Dialect::operator==(const Dialect &other) const {
   return def == other.def;
 }
diff --git a/mlir/lib/Target/CMakeLists.txt b/mlir/lib/Target/CMakeLists.txt
index f51b46b4da1ad..b68bfa8d3cf20 100644
--- a/mlir/lib/Target/CMakeLists.txt
+++ b/mlir/lib/Target/CMakeLists.txt
@@ -10,6 +10,7 @@ add_mlir_library(MLIRTargetLLVMIRModuleTranslation
 target_link_libraries(MLIRTargetLLVMIRModuleTranslation
   PUBLIC
   MLIRLLVMIR
+  MLIRLLVMIRTransforms
   LLVMCore
   LLVMIRReader
   LLVMSupport
diff --git a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
index 6a774acdf6bf9..86351bd689ad9 100644
--- a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -485,8 +485,7 @@ static const DenseMap<unsigned, StringRef> opcMap = {
     INST(Or, Or), INST(Xor, XOr), INST(Alloca, Alloca), INST(Load, Load),
     INST(Store, Store),
     // Getelementptr is handled specially.
-    INST(Ret, Return),
-    // FIXME: fence
+    INST(Ret, Return), INST(Fence, Fence),
     // FIXME: atomiccmpxchg
     // FIXME: atomicrmw
     INST(Trunc, Trunc), INST(ZExt, ZExt), INST(SExt, SExt),
@@ -539,6 +538,26 @@ static ICmpPredicate getICmpPredicate(llvm::CmpInst::Predicate p) {
   llvm_unreachable("incorrect comparison predicate");
 }
 
+static AtomicOrdering getLLVMAtomicOrdering(llvm::AtomicOrdering ordering) {
+  switch (ordering) {
+  case llvm::AtomicOrdering::NotAtomic:
+    return LLVM::AtomicOrdering::not_atomic;
+  case llvm::AtomicOrdering::Unordered:
+    return LLVM::AtomicOrdering::unordered;
+  case llvm::AtomicOrdering::Monotonic:
+    return LLVM::AtomicOrdering::monotonic;
+  case llvm::AtomicOrdering::Acquire:
+    return LLVM::AtomicOrdering::acquire;
+  case llvm::AtomicOrdering::Release:
+    return LLVM::AtomicOrdering::release;
+  case llvm::AtomicOrdering::AcquireRelease:
+    return LLVM::AtomicOrdering::acq_rel;
+  case llvm::AtomicOrdering::SequentiallyConsistent:
+    return LLVM::AtomicOrdering::seq_cst;
+  }
+  llvm_unreachable("incorrect atomic ordering");
+}
+
 // `br` branches to `target`. Return the branch arguments to `br`, in the
 // same order of the PHIs in `target`.
 LogicalResult
@@ -743,6 +762,23 @@ LogicalResult Importer::processInstruction(llvm::Instruction *inst) {
       v = op->getResult(0);
     return success();
   }
+  case llvm::Instruction::Fence: {
+    StringRef syncscope;
+    SmallVector<StringRef, 4> ssNs;
+    llvm::LLVMContext &llvmContext = dialect->getLLVMContext();
+    llvm::FenceInst *fence = cast<llvm::FenceInst>(inst);
+    llvmContext.getSyncScopeNames(ssNs);
+    int fenceSyncScopeID = fence->getSyncScopeID();
+    for (unsigned i = 0, e = ssNs.size(); i != e; i++) {
+      if (fenceSyncScopeID == llvmContext.getOrInsertSyncScopeID(ssNs[i])) {
+        syncscope = ssNs[i];
+        break;
+      }
+    }
+    b.create<FenceOp>(loc, getLLVMAtomicOrdering(fence->getOrdering()),
+                      syncscope);
+    return success();
+  }
   case llvm::Instruction::GetElementPtr: {
     // FIXME: Support inbounds GEPs.
     llvm::GetElementPtrInst *gep = cast<llvm::GetElementPtrInst>(inst);
diff --git a/mlir/lib/Transforms/CMakeLists.txt b/mlir/lib/Transforms/CMakeLists.txt
index 1cd89a334eefc..6d1d7b41d568e 100644
--- a/mlir/lib/Transforms/CMakeLists.txt
+++ b/mlir/lib/Transforms/CMakeLists.txt
@@ -39,5 +39,5 @@ target_link_libraries(MLIRTransforms
   MLIRLoopOps
   MLIRPass
   MLIRTransformUtils
-  MLIRVectorOps
+  MLIRVector
   )
diff --git a/mlir/lib/Transforms/DialectConversion.cpp b/mlir/lib/Transforms/DialectConversion.cpp
index a58dd05d08126..19304b3fb73f8 100644
--- a/mlir/lib/Transforms/DialectConversion.cpp
+++ b/mlir/lib/Transforms/DialectConversion.cpp
@@ -989,6 +989,17 @@ void ConversionPatternRewriter::cancelRootUpdate(Operation *op) {
   rootUpdates.erase(rootUpdates.begin() + (rootUpdates.rend() - it));
 }
 
+/// PatternRewriter hook for notifying match failure reasons.
+LogicalResult ConversionPatternRewriter::notifyMatchFailure(
+    Operation *op, function_ref<void(Diagnostic &)> reasonCallback) {
+  LLVM_DEBUG({
+    Diagnostic diag(op->getLoc(), DiagnosticSeverity::Remark);
+    reasonCallback(diag);
+    impl->logger.startLine() << "** Failure : " << diag.str() << "\n";
+  });
+  return failure();
+}
+
 /// Return a reference to the internal implementation.
 detail::ConversionPatternRewriterImpl &ConversionPatternRewriter::getImpl() {
   return *impl;
@@ -999,7 +1010,7 @@ detail::ConversionPatternRewriterImpl &ConversionPatternRewriter::getImpl() {
 //===----------------------------------------------------------------------===//
 
 /// Attempt to match and rewrite the IR root at the specified operation.
-PatternMatchResult
+LogicalResult
 ConversionPattern::matchAndRewrite(Operation *op,
                                    PatternRewriter &rewriter) const {
   SmallVector<Value, 4> operands;
@@ -1097,6 +1108,12 @@ OperationLegalizer::legalize(Operation *op,
     os.startLine() << "Legalizing operation : '" << op->getName() << "'(" << op
                    << ") {\n";
     os.indent();
+
+    // If the operation has no regions, just print it here.
+    if (op->getNumRegions() == 0) {
+      op->print(os.startLine(), OpPrintingFlags().printGenericOpForm());
+      os.getOStream() << "\n\n";
+    }
   });
 
   // Check if this operation is legal on the target.
@@ -1237,12 +1254,12 @@ OperationLegalizer::legalizePattern(Operation *op, RewritePattern *pattern,
 
   // Try to rewrite with the given pattern.
   rewriter.setInsertionPoint(op);
-  auto matchedPattern = pattern->matchAndRewrite(op, rewriter);
+  LogicalResult matchedPattern = pattern->matchAndRewrite(op, rewriter);
 #ifndef NDEBUG
   assert(rewriterImpl.pendingRootUpdates.empty() && "dangling root updates");
 #endif
 
-  if (!matchedPattern) {
+  if (failed(matchedPattern)) {
     LLVM_DEBUG(logFailure(rewriterImpl.logger, "pattern failed to match"));
     return cleanupFailure();
   }
@@ -1694,7 +1711,7 @@ struct FuncOpSignatureConversion : public OpConversionPattern<FuncOp> {
       : OpConversionPattern(ctx), converter(converter) {}
 
   /// Hook for derived classes to implement combined matching and rewriting.
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(FuncOp funcOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     FunctionType type = funcOp.getType();
@@ -1703,12 +1720,12 @@ struct FuncOpSignatureConversion : public OpConversionPattern<FuncOp> {
     TypeConverter::SignatureConversion result(type.getNumInputs());
     for (unsigned i = 0, e = type.getNumInputs(); i != e; ++i)
       if (failed(converter.convertSignatureArg(i, type.getInput(i), result)))
-        return matchFailure();
+        return failure();
 
     // Convert the original function results.
     SmallVector<Type, 1> convertedResults;
     if (failed(converter.convertTypes(type.getResults(), convertedResults)))
-      return matchFailure();
+      return failure();
 
     // Update the function signature in-place.
     rewriter.updateRootInPlace(funcOp, [&] {
@@ -1716,7 +1733,7 @@ struct FuncOpSignatureConversion : public OpConversionPattern<FuncOp> {
                                        convertedResults, funcOp.getContext()));
       rewriter.applySignatureConversion(&funcOp.getBody(), result);
     });
-    return matchSuccess();
+    return success();
   }
 
   /// The type converter to use when rewriting the signature.
diff --git a/mlir/lib/Transforms/Inliner.cpp b/mlir/lib/Transforms/Inliner.cpp
index b6fcf8bc3941c..ea48582dc52a9 100644
--- a/mlir/lib/Transforms/Inliner.cpp
+++ b/mlir/lib/Transforms/Inliner.cpp
@@ -14,8 +14,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "mlir/Analysis/CallGraph.h"
-#include "mlir/IR/Builders.h"
 #include "mlir/IR/PatternMatch.h"
+#include "mlir/Interfaces/SideEffects.h"
 #include "mlir/Pass/Pass.h"
 #include "mlir/Transforms/InliningUtils.h"
 #include "mlir/Transforms/Passes.h"
@@ -37,6 +37,259 @@ static llvm::cl::opt<unsigned> maxInliningIterations(
     llvm::cl::desc("Maximum number of iterations when inlining within an SCC"),
     llvm::cl::ReallyHidden, llvm::cl::init(4));
 
+//===----------------------------------------------------------------------===//
+// Symbol Use Tracking
+//===----------------------------------------------------------------------===//
+
+/// Returns true if this operation can be discarded if it is a symbol and has no
+/// uses. 'allUsesVisible' corresponds to if the parent symbol table is hidden
+/// from above.
+static bool canDiscardSymbolOnUseEmpty(Operation *op, bool allUsesVisible) {
+  if (!SymbolTable::isSymbol(op))
+    return false;
+
+  // TODO: This is essentially the same logic from SymbolDCE. Remove this when
+  // we have a 'Symbol' interface.
+  // Private symbols are always initially considered dead.
+  SymbolTable::Visibility visibility = SymbolTable::getSymbolVisibility(op);
+  if (visibility == mlir::SymbolTable::Visibility::Private)
+    return true;
+  // We only include nested visibility here if all uses are visible.
+  if (allUsesVisible && visibility == SymbolTable::Visibility::Nested)
+    return true;
+  // Otherwise, public symbols are never removable.
+  return false;
+}
+
+/// Walk all of the symbol table operations nested with 'op' along with a
+/// boolean signifying if the symbols within can be treated as if all uses are
+/// visible. The provided callback is invoked with the symbol table operation,
+/// and a boolean signaling if all of the uses within the symbol table are
+/// visible.
+static void walkSymbolTables(Operation *op, bool allSymUsesVisible,
+                             function_ref<void(Operation *, bool)> callback) {
+  if (op->hasTrait<OpTrait::SymbolTable>()) {
+    allSymUsesVisible = allSymUsesVisible || !SymbolTable::isSymbol(op) ||
+                        SymbolTable::getSymbolVisibility(op) ==
+                            SymbolTable::Visibility::Private;
+    callback(op, allSymUsesVisible);
+  } else {
+    // Otherwise if 'op' is not a symbol table, any nested symbols are
+    // guaranteed to be hidden.
+    allSymUsesVisible = true;
+  }
+
+  for (Region &region : op->getRegions())
+    for (Block &block : region)
+      for (Operation &nested : block)
+        walkSymbolTables(&nested, allSymUsesVisible, callback);
+}
+
+/// Walk all of the used symbol callgraph nodes referenced with the given op.
+static void walkReferencedSymbolNodes(
+    Operation *op, CallGraph &cg,
+    DenseMap<Attribute, CallGraphNode *> &resolvedRefs,
+    function_ref<void(CallGraphNode *, Operation *)> callback) {
+  auto symbolUses = SymbolTable::getSymbolUses(op);
+  assert(symbolUses && "expected uses to be valid");
+
+  Operation *symbolTableOp = op->getParentOp();
+  for (const SymbolTable::SymbolUse &use : *symbolUses) {
+    auto refIt = resolvedRefs.insert({use.getSymbolRef(), nullptr});
+    CallGraphNode *&node = refIt.first->second;
+
+    // If this is the first instance of this reference, try to resolve a
+    // callgraph node for it.
+    if (refIt.second) {
+      auto *symbolOp = SymbolTable::lookupNearestSymbolFrom(symbolTableOp,
+                                                            use.getSymbolRef());
+      auto callableOp = dyn_cast_or_null<CallableOpInterface>(symbolOp);
+      if (!callableOp)
+        continue;
+      node = cg.lookupNode(callableOp.getCallableRegion());
+    }
+    if (node)
+      callback(node, use.getUser());
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// CGUseList
+
+namespace {
+/// This struct tracks the uses of callgraph nodes that can be dropped when
+/// use_empty. It directly tracks and manages a use-list for all of the
+/// call-graph nodes. This is necessary because many callgraph nodes are
+/// referenced by SymbolRefAttr, which has no mechanism akin to the SSA `Use`
+/// class.
+struct CGUseList {
+  /// This struct tracks the uses of callgraph nodes within a specific
+  /// operation.
+  struct CGUser {
+    /// Any nodes referenced in the top-level attribute list of this user. We
+    /// use a set here because the number of references does not matter.
+    DenseSet<CallGraphNode *> topLevelUses;
+
+    /// Uses of nodes referenced by nested operations.
+    DenseMap<CallGraphNode *, int> innerUses;
+  };
+
+  CGUseList(Operation *op, CallGraph &cg);
+
+  /// Drop uses of nodes referred to by the given call operation that resides
+  /// within 'userNode'.
+  void dropCallUses(CallGraphNode *userNode, Operation *callOp, CallGraph &cg);
+
+  /// Remove the given node from the use list.
+  void eraseNode(CallGraphNode *node);
+
+  /// Returns true if the given callgraph node has no uses and can be pruned.
+  bool isDead(CallGraphNode *node) const;
+
+  /// Returns true if the given callgraph node has a single use and can be
+  /// discarded.
+  bool hasOneUseAndDiscardable(CallGraphNode *node) const;
+
+  /// Recompute the uses held by the given callgraph node.
+  void recomputeUses(CallGraphNode *node, CallGraph &cg);
+
+  /// Merge the uses of 'lhs' with the uses of the 'rhs' after inlining a copy
+  /// of 'lhs' into 'rhs'.
+  void mergeUsesAfterInlining(CallGraphNode *lhs, CallGraphNode *rhs);
+
+private:
+  /// Decrement the uses of discardable nodes referenced by the given user.
+  void decrementDiscardableUses(CGUser &uses);
+
+  /// A mapping between a discardable callgraph node (that is a symbol) and the
+  /// number of uses for this node.
+  DenseMap<CallGraphNode *, int> discardableSymNodeUses;
+  /// A mapping between a callgraph node and the symbol callgraph nodes that it
+  /// uses.
+  DenseMap<CallGraphNode *, CGUser> nodeUses;
+};
+} // end anonymous namespace
+
+CGUseList::CGUseList(Operation *op, CallGraph &cg) {
+  /// A set of callgraph nodes that are always known to be live during inlining.
+  DenseMap<Attribute, CallGraphNode *> alwaysLiveNodes;
+
+  // Walk each of the symbol tables looking for discardable callgraph nodes.
+  auto walkFn = [&](Operation *symbolTableOp, bool allUsesVisible) {
+    for (Block &block : symbolTableOp->getRegion(0)) {
+      for (Operation &op : block) {
+        // If this is a callgraph operation, check to see if it is discardable.
+        if (auto callable = dyn_cast<CallableOpInterface>(&op)) {
+          if (auto *node = cg.lookupNode(callable.getCallableRegion())) {
+            if (canDiscardSymbolOnUseEmpty(&op, allUsesVisible))
+              discardableSymNodeUses.try_emplace(node, 0);
+            continue;
+          }
+        }
+        // Otherwise, check for any referenced nodes. These will be always-live.
+        walkReferencedSymbolNodes(&op, cg, alwaysLiveNodes,
+                                  [](CallGraphNode *, Operation *) {});
+      }
+    }
+  };
+  walkSymbolTables(op, /*allSymUsesVisible=*/!op->getBlock(), walkFn);
+
+  // Drop the use information for any discardable nodes that are always live.
+  for (auto &it : alwaysLiveNodes)
+    discardableSymNodeUses.erase(it.second);
+
+  // Compute the uses for each of the callable nodes in the graph.
+  for (CallGraphNode *node : cg)
+    recomputeUses(node, cg);
+}
+
+void CGUseList::dropCallUses(CallGraphNode *userNode, Operation *callOp,
+                             CallGraph &cg) {
+  auto &userRefs = nodeUses[userNode].innerUses;
+  auto walkFn = [&](CallGraphNode *node, Operation *user) {
+    auto parentIt = userRefs.find(node);
+    if (parentIt == userRefs.end())
+      return;
+    --parentIt->second;
+    --discardableSymNodeUses[node];
+  };
+  DenseMap<Attribute, CallGraphNode *> resolvedRefs;
+  walkReferencedSymbolNodes(callOp, cg, resolvedRefs, walkFn);
+}
+
+void CGUseList::eraseNode(CallGraphNode *node) {
+  // Drop all child nodes.
+  for (auto &edge : *node)
+    if (edge.isChild())
+      eraseNode(edge.getTarget());
+
+  // Drop the uses held by this node and erase it.
+  auto useIt = nodeUses.find(node);
+  assert(useIt != nodeUses.end() && "expected node to be valid");
+  decrementDiscardableUses(useIt->getSecond());
+  nodeUses.erase(useIt);
+  discardableSymNodeUses.erase(node);
+}
+
+bool CGUseList::isDead(CallGraphNode *node) const {
+  // If the parent operation isn't a symbol, simply check normal SSA deadness.
+  Operation *nodeOp = node->getCallableRegion()->getParentOp();
+  if (!SymbolTable::isSymbol(nodeOp))
+    return MemoryEffectOpInterface::hasNoEffect(nodeOp) && nodeOp->use_empty();
+
+  // Otherwise, check the number of symbol uses.
+  auto symbolIt = discardableSymNodeUses.find(node);
+  return symbolIt != discardableSymNodeUses.end() && symbolIt->second == 0;
+}
+
+bool CGUseList::hasOneUseAndDiscardable(CallGraphNode *node) const {
+  // If this isn't a symbol node, check for side-effects and SSA use count.
+  Operation *nodeOp = node->getCallableRegion()->getParentOp();
+  if (!SymbolTable::isSymbol(nodeOp))
+    return MemoryEffectOpInterface::hasNoEffect(nodeOp) && nodeOp->hasOneUse();
+
+  // Otherwise, check the number of symbol uses.
+  auto symbolIt = discardableSymNodeUses.find(node);
+  return symbolIt != discardableSymNodeUses.end() && symbolIt->second == 1;
+}
+
+void CGUseList::recomputeUses(CallGraphNode *node, CallGraph &cg) {
+  Operation *parentOp = node->getCallableRegion()->getParentOp();
+  CGUser &uses = nodeUses[node];
+  decrementDiscardableUses(uses);
+
+  // Collect the new discardable uses within this node.
+  uses = CGUser();
+  DenseMap<Attribute, CallGraphNode *> resolvedRefs;
+  auto walkFn = [&](CallGraphNode *refNode, Operation *user) {
+    auto discardSymIt = discardableSymNodeUses.find(refNode);
+    if (discardSymIt == discardableSymNodeUses.end())
+      return;
+
+    if (user != parentOp)
+      ++uses.innerUses[refNode];
+    else if (!uses.topLevelUses.insert(refNode).second)
+      return;
+    ++discardSymIt->second;
+  };
+  walkReferencedSymbolNodes(parentOp, cg, resolvedRefs, walkFn);
+}
+
+void CGUseList::mergeUsesAfterInlining(CallGraphNode *lhs, CallGraphNode *rhs) {
+  auto &lhsUses = nodeUses[lhs], &rhsUses = nodeUses[rhs];
+  for (auto &useIt : lhsUses.innerUses) {
+    rhsUses.innerUses[useIt.first] += useIt.second;
+    discardableSymNodeUses[useIt.first] += useIt.second;
+  }
+}
+
+void CGUseList::decrementDiscardableUses(CGUser &uses) {
+  for (CallGraphNode *node : uses.topLevelUses)
+    --discardableSymNodeUses[node];
+  for (auto &it : uses.innerUses)
+    discardableSymNodeUses[it.first] -= it.second;
+}
+
 //===----------------------------------------------------------------------===//
 // CallGraph traversal
 //===----------------------------------------------------------------------===//
@@ -45,7 +298,7 @@ static llvm::cl::opt<unsigned> maxInliningIterations(
 /// traversal.
 static void runTransformOnCGSCCs(
     const CallGraph &cg,
-    function_ref<void(ArrayRef<CallGraphNode *>)> sccTransformer) {
+    function_ref<void(MutableArrayRef<CallGraphNode *>)> sccTransformer) {
   std::vector<CallGraphNode *> currentSCCVec;
   auto cgi = llvm::scc_begin(&cg);
   while (!cgi.isAtEnd()) {
@@ -63,10 +316,11 @@ namespace {
 /// Region(CallGraphNode) that it is dispatching to, we need to resolve them
 /// explicitly.
 struct ResolvedCall {
-  ResolvedCall(CallOpInterface call, CallGraphNode *targetNode)
-      : call(call), targetNode(targetNode) {}
+  ResolvedCall(CallOpInterface call, CallGraphNode *sourceNode,
+               CallGraphNode *targetNode)
+      : call(call), sourceNode(sourceNode), targetNode(targetNode) {}
   CallOpInterface call;
-  CallGraphNode *targetNode;
+  CallGraphNode *sourceNode, *targetNode;
 };
 } // end anonymous namespace
 
@@ -74,17 +328,22 @@ struct ResolvedCall {
 /// `traverseNestedCGNodes` is true, this will also collect call operations
 /// inside of nested callgraph nodes.
 static void collectCallOps(iterator_range<Region::iterator> blocks,
-                           CallGraph &cg, SmallVectorImpl<ResolvedCall> &calls,
+                           CallGraphNode *sourceNode, CallGraph &cg,
+                           SmallVectorImpl<ResolvedCall> &calls,
                            bool traverseNestedCGNodes) {
-  SmallVector<Block *, 8> worklist;
-  auto addToWorklist = [&](iterator_range<Region::iterator> blocks) {
+  SmallVector<std::pair<Block *, CallGraphNode *>, 8> worklist;
+  auto addToWorklist = [&](CallGraphNode *node,
+                           iterator_range<Region::iterator> blocks) {
     for (Block &block : blocks)
-      worklist.push_back(&block);
+      worklist.emplace_back(&block, node);
   };
 
-  addToWorklist(blocks);
+  addToWorklist(sourceNode, blocks);
   while (!worklist.empty()) {
-    for (Operation &op : *worklist.pop_back_val()) {
+    Block *block;
+    std::tie(block, sourceNode) = worklist.pop_back_val();
+
+    for (Operation &op : *block) {
       if (auto call = dyn_cast<CallOpInterface>(op)) {
         // TODO(riverriddle) Support inlining nested call references.
         CallInterfaceCallable callable = call.getCallableForCallee();
@@ -93,18 +352,20 @@ static void collectCallOps(iterator_range<Region::iterator> blocks,
             continue;
         }
 
-        CallGraphNode *node = cg.resolveCallable(call);
-        if (!node->isExternal())
-          calls.emplace_back(call, node);
+        CallGraphNode *targetNode = cg.resolveCallable(call);
+        if (!targetNode->isExternal())
+          calls.emplace_back(call, sourceNode, targetNode);
         continue;
       }
 
       // If this is not a call, traverse the nested regions. If
       // `traverseNestedCGNodes` is false, then don't traverse nested call graph
       // regions.
-      for (auto &nestedRegion : op.getRegions())
-        if (traverseNestedCGNodes || !cg.lookupNode(&nestedRegion))
-          addToWorklist(nestedRegion);
+      for (auto &nestedRegion : op.getRegions()) {
+        CallGraphNode *nestedNode = cg.lookupNode(&nestedRegion);
+        if (traverseNestedCGNodes || !nestedNode)
+          addToWorklist(nestedNode ? nestedNode : sourceNode, nestedRegion);
+      }
     }
   }
 }
@@ -122,7 +383,16 @@ struct Inliner : public InlinerInterface {
   /// *before* inlined terminator operations have been processed.
   void
   processInlinedBlocks(iterator_range<Region::iterator> inlinedBlocks) final {
-    collectCallOps(inlinedBlocks, cg, calls, /*traverseNestedCGNodes=*/true);
+    // Find the closest callgraph node from the first block.
+    CallGraphNode *node;
+    Region *region = inlinedBlocks.begin()->getParent();
+    while (!(node = cg.lookupNode(region))) {
+      region = region->getParentRegion();
+      assert(region && "expected valid parent node");
+    }
+
+    collectCallOps(inlinedBlocks, node, cg, calls,
+                   /*traverseNestedCGNodes=*/true);
   }
 
   /// The current set of call instructions to consider for inlining.
@@ -150,24 +420,47 @@ static bool shouldInline(ResolvedCall &resolvedCall) {
   return true;
 }
 
+/// Delete the given node and remove it from the current scc and the callgraph.
+static void deleteNode(CallGraphNode *node, CGUseList &useList, CallGraph &cg,
+                       MutableArrayRef<CallGraphNode *> currentSCC) {
+  // Erase the parent operation and remove it from the various lists.
+  node->getCallableRegion()->getParentOp()->erase();
+  cg.eraseNode(node);
+
+  // Replace this node in the currentSCC with the external node.
+  auto it = llvm::find(currentSCC, node);
+  if (it != currentSCC.end())
+    *it = cg.getExternalNode();
+}
+
 /// Attempt to inline calls within the given scc. This function returns
 /// success if any calls were inlined, failure otherwise.
-static LogicalResult inlineCallsInSCC(Inliner &inliner,
-                                      ArrayRef<CallGraphNode *> currentSCC) {
+static LogicalResult
+inlineCallsInSCC(Inliner &inliner, CGUseList &useList,
+                 MutableArrayRef<CallGraphNode *> currentSCC) {
   CallGraph &cg = inliner.cg;
   auto &calls = inliner.calls;
 
   // Collect all of the direct calls within the nodes of the current SCC. We
   // don't traverse nested callgraph nodes, because they are handled separately
   // likely within a different SCC.
-  for (auto *node : currentSCC) {
-    if (!node->isExternal())
-      collectCallOps(*node->getCallableRegion(), cg, calls,
+  for (CallGraphNode *node : currentSCC) {
+    if (node->isExternal())
+      continue;
+
+    // If this node is dead, just delete it now.
+    if (useList.isDead(node))
+      deleteNode(node, useList, cg, currentSCC);
+    else
+      collectCallOps(*node->getCallableRegion(), node, cg, calls,
                      /*traverseNestedCGNodes=*/false);
   }
   if (calls.empty())
     return failure();
 
+  // A set of dead nodes to remove after inlining.
+  SmallVector<CallGraphNode *, 1> deadNodes;
+
   // Try to inline each of the call operations. Don't cache the end iterator
   // here as more calls may be added during inlining.
   bool inlinedAnyCalls = false;
@@ -179,26 +472,44 @@ static LogicalResult inlineCallsInSCC(Inliner &inliner,
     });
     if (!shouldInline(it))
       continue;
-
     CallOpInterface call = it.call;
     Region *targetRegion = it.targetNode->getCallableRegion();
+
+    // If this is the last call to the target node and the node is discardable,
+    // then inline it in-place and delete the node if successful.
+    bool inlineInPlace = useList.hasOneUseAndDiscardable(it.targetNode);
+
     LogicalResult inlineResult = inlineCall(
         inliner, call, cast<CallableOpInterface>(targetRegion->getParentOp()),
-        targetRegion);
+        targetRegion, /*shouldCloneInlinedRegion=*/!inlineInPlace);
     if (failed(inlineResult))
       continue;
+    inlinedAnyCalls = true;
+
+    // If the inlining was successful, Merge the new uses into the source node.
+    useList.dropCallUses(it.sourceNode, call.getOperation(), cg);
+    useList.mergeUsesAfterInlining(it.targetNode, it.sourceNode);
 
-    // If the inlining was successful, then erase the call.
+    // then erase the call.
     call.erase();
-    inlinedAnyCalls = true;
+
+    // If we inlined in place, mark the node for deletion.
+    if (inlineInPlace) {
+      useList.eraseNode(it.targetNode);
+      deadNodes.push_back(it.targetNode);
+    }
   }
+
+  for (CallGraphNode *node : deadNodes)
+    deleteNode(node, useList, cg, currentSCC);
   calls.clear();
   return success(inlinedAnyCalls);
 }
 
 /// Canonicalize the nodes within the given SCC with the given set of
 /// canonicalization patterns.
-static void canonicalizeSCC(CallGraph &cg, ArrayRef<CallGraphNode *> currentSCC,
+static void canonicalizeSCC(CallGraph &cg, CGUseList &useList,
+                            MutableArrayRef<CallGraphNode *> currentSCC,
                             MLIRContext *context,
                             const OwningRewritePatternList &canonPatterns) {
   // Collect the sets of nodes to canonicalize.
@@ -246,12 +557,17 @@ static void canonicalizeSCC(CallGraph &cg, ArrayRef<CallGraphNode *> currentSCC,
         // thread may be used in a different context.
         canonicalizationHandler.eraseOrderIDForThread();
       });
+
+  // Recompute the uses held by each of the nodes.
+  for (CallGraphNode *node : nodesToCanonicalize)
+    useList.recomputeUses(node, cg);
 }
 
 /// Attempt to inline calls within the given scc, and run canonicalizations with
 /// the given patterns, until a fixed point is reached. This allows for the
 /// inlining of newly devirtualized calls.
-static void inlineSCC(Inliner &inliner, ArrayRef<CallGraphNode *> currentSCC,
+static void inlineSCC(Inliner &inliner, CGUseList &useList,
+                      MutableArrayRef<CallGraphNode *> currentSCC,
                       MLIRContext *context,
                       const OwningRewritePatternList &canonPatterns) {
   // If we successfully inlined any calls, run some simplifications on the
@@ -259,12 +575,12 @@ static void inlineSCC(Inliner &inliner, ArrayRef<CallGraphNode *> currentSCC,
   // point, or a maximum iteration count. We canonicalize here as it may
   // devirtualize new calls, as well as give us a better cost model.
   unsigned iterationCount = 0;
-  while (succeeded(inlineCallsInSCC(inliner, currentSCC))) {
+  while (succeeded(inlineCallsInSCC(inliner, useList, currentSCC))) {
     // If we aren't allowing simplifications or the max iteration count was
     // reached, then bail out early.
     if (disableCanonicalization || ++iterationCount >= maxInliningIterations)
       break;
-    canonicalizeSCC(inliner.cg, currentSCC, context, canonPatterns);
+    canonicalizeSCC(inliner.cg, useList, currentSCC, context, canonPatterns);
   }
 }
 
@@ -272,8 +588,6 @@ static void inlineSCC(Inliner &inliner, ArrayRef<CallGraphNode *> currentSCC,
 // InlinerPass
 //===----------------------------------------------------------------------===//
 
-// TODO(riverriddle) This pass should currently only be used for basic testing
-// of inlining functionality.
 namespace {
 struct InlinerPass : public OperationPass<InlinerPass> {
   void runOnOperation() override {
@@ -297,8 +611,9 @@ struct InlinerPass : public OperationPass<InlinerPass> {
 
     // Run the inline transform in post-order over the SCCs in the callgraph.
     Inliner inliner(context, cg);
-    runTransformOnCGSCCs(cg, [&](ArrayRef<CallGraphNode *> scc) {
-      inlineSCC(inliner, scc, context, canonPatterns);
+    CGUseList useList(getOperation(), cg);
+    runTransformOnCGSCCs(cg, [&](MutableArrayRef<CallGraphNode *> scc) {
+      inlineSCC(inliner, useList, scc, context, canonPatterns);
     });
   }
 };
diff --git a/mlir/lib/Transforms/PipelineDataTransfer.cpp b/mlir/lib/Transforms/PipelineDataTransfer.cpp
index 7057ecb853835..39874b1bc44a0 100644
--- a/mlir/lib/Transforms/PipelineDataTransfer.cpp
+++ b/mlir/lib/Transforms/PipelineDataTransfer.cpp
@@ -22,6 +22,7 @@
 #include "mlir/Transforms/Utils.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/Support/Debug.h"
+
 #define DEBUG_TYPE "affine-pipeline-data-transfer"
 
 using namespace mlir;
@@ -46,9 +47,9 @@ std::unique_ptr<OpPassBase<FuncOp>> mlir::createPipelineDataTransferPass() {
 // Returns the position of the tag memref operand given a DMA operation.
 // Temporary utility: will be replaced when DmaStart/DmaFinish abstract op's are
 // added.  TODO(b/117228571)
-static unsigned getTagMemRefPos(Operation &dmaInst) {
-  assert(isa<AffineDmaStartOp>(dmaInst) || isa<AffineDmaWaitOp>(dmaInst));
-  if (auto dmaStartOp = dyn_cast<AffineDmaStartOp>(dmaInst)) {
+static unsigned getTagMemRefPos(Operation &dmaOp) {
+  assert(isa<AffineDmaStartOp>(dmaOp) || isa<AffineDmaWaitOp>(dmaOp));
+  if (auto dmaStartOp = dyn_cast<AffineDmaStartOp>(dmaOp)) {
     return dmaStartOp.getTagMemRefOperandIndex();
   }
   // First operand for a dma finish operation.
@@ -79,21 +80,20 @@ static bool doubleBuffer(Value oldMemRef, AffineForOp forOp) {
   auto oldMemRefType = oldMemRef.getType().cast<MemRefType>();
   auto newMemRefType = doubleShape(oldMemRefType);
 
-  // The double buffer is allocated right before 'forInst'.
-  auto *forInst = forOp.getOperation();
-  OpBuilder bOuter(forInst);
+  // The double buffer is allocated right before 'forOp'.
+  OpBuilder bOuter(forOp);
   // Put together alloc operands for any dynamic dimensions of the memref.
   SmallVector<Value, 4> allocOperands;
   unsigned dynamicDimCount = 0;
   for (auto dimSize : oldMemRefType.getShape()) {
     if (dimSize == -1)
-      allocOperands.push_back(bOuter.create<DimOp>(forInst->getLoc(), oldMemRef,
-                                                   dynamicDimCount++));
+      allocOperands.push_back(
+          bOuter.create<DimOp>(forOp.getLoc(), oldMemRef, dynamicDimCount++));
   }
 
   // Create and place the alloc right before the 'affine.for' operation.
   Value newMemRef =
-      bOuter.create<AllocOp>(forInst->getLoc(), newMemRefType, allocOperands);
+      bOuter.create<AllocOp>(forOp.getLoc(), newMemRefType, allocOperands);
 
   // Create 'iv mod 2' value to index the leading dimension.
   auto d0 = bInner.getAffineDimExpr(0);
@@ -118,8 +118,8 @@ static bool doubleBuffer(Value oldMemRef, AffineForOp forOp) {
     return false;
   }
   // Insert the dealloc op right after the for loop.
-  bOuter.setInsertionPointAfter(forInst);
-  bOuter.create<DeallocOp>(forInst->getLoc(), newMemRef);
+  bOuter.setInsertionPointAfter(forOp);
+  bOuter.create<DeallocOp>(forOp.getLoc(), newMemRef);
 
   return true;
 }
@@ -219,11 +219,11 @@ static void findMatchingStartFinishInsts(
   }
 
   // For each start operation, we look for a matching finish operation.
-  for (auto *dmaStartInst : dmaStartInsts) {
-    for (auto *dmaFinishInst : dmaFinishInsts) {
-      if (checkTagMatch(cast<AffineDmaStartOp>(dmaStartInst),
-                        cast<AffineDmaWaitOp>(dmaFinishInst))) {
-        startWaitPairs.push_back({dmaStartInst, dmaFinishInst});
+  for (auto *dmaStartOp : dmaStartInsts) {
+    for (auto *dmaFinishOp : dmaFinishInsts) {
+      if (checkTagMatch(cast<AffineDmaStartOp>(dmaStartOp),
+                        cast<AffineDmaWaitOp>(dmaFinishOp))) {
+        startWaitPairs.push_back({dmaStartOp, dmaFinishOp});
         break;
       }
     }
@@ -236,8 +236,7 @@ static void findMatchingStartFinishInsts(
 void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
   auto mayBeConstTripCount = getConstantTripCount(forOp);
   if (!mayBeConstTripCount.hasValue()) {
-    LLVM_DEBUG(
-        forOp.emitRemark("won't pipeline due to unknown trip count loop"));
+    LLVM_DEBUG(forOp.emitRemark("won't pipeline due to unknown trip count"));
     return;
   }
 
@@ -258,14 +257,14 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
   // the dimension we are adding here for the double buffering is the outermost
   // dimension.
   for (auto &pair : startWaitPairs) {
-    auto *dmaStartInst = pair.first;
-    Value oldMemRef = dmaStartInst->getOperand(
-        cast<AffineDmaStartOp>(dmaStartInst).getFasterMemPos());
+    auto *dmaStartOp = pair.first;
+    Value oldMemRef = dmaStartOp->getOperand(
+        cast<AffineDmaStartOp>(dmaStartOp).getFasterMemPos());
     if (!doubleBuffer(oldMemRef, forOp)) {
       // Normally, double buffering should not fail because we already checked
       // that there are no uses outside.
       LLVM_DEBUG(llvm::dbgs()
-                     << "double buffering failed for" << dmaStartInst << "\n";);
+                     << "double buffering failed for" << dmaStartOp << "\n";);
       // IR still valid and semantically correct.
       return;
     }
@@ -275,13 +274,13 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
     // order to create the double buffer above.)
     // '-canonicalize' does this in a more general way, but we'll anyway do the
     // simple/common case so that the output / test cases looks clear.
-    if (auto *allocInst = oldMemRef.getDefiningOp()) {
+    if (auto *allocOp = oldMemRef.getDefiningOp()) {
       if (oldMemRef.use_empty()) {
-        allocInst->erase();
+        allocOp->erase();
       } else if (oldMemRef.hasOneUse()) {
         if (auto dealloc = dyn_cast<DeallocOp>(*oldMemRef.user_begin())) {
           dealloc.erase();
-          allocInst->erase();
+          allocOp->erase();
         }
       }
     }
@@ -289,22 +288,21 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
 
   // Double the buffers for tag memrefs.
   for (auto &pair : startWaitPairs) {
-    auto *dmaFinishInst = pair.second;
-    Value oldTagMemRef =
-        dmaFinishInst->getOperand(getTagMemRefPos(*dmaFinishInst));
+    auto *dmaFinishOp = pair.second;
+    Value oldTagMemRef = dmaFinishOp->getOperand(getTagMemRefPos(*dmaFinishOp));
     if (!doubleBuffer(oldTagMemRef, forOp)) {
       LLVM_DEBUG(llvm::dbgs() << "tag double buffering failed\n";);
       return;
     }
     // If the old tag has no uses or a single dealloc use, remove it.
     // (canonicalization handles more complex cases).
-    if (auto *tagAllocInst = oldTagMemRef.getDefiningOp()) {
+    if (auto *tagAllocOp = oldTagMemRef.getDefiningOp()) {
       if (oldTagMemRef.use_empty()) {
-        tagAllocInst->erase();
+        tagAllocOp->erase();
       } else if (oldTagMemRef.hasOneUse()) {
         if (auto dealloc = dyn_cast<DeallocOp>(*oldTagMemRef.user_begin())) {
           dealloc.erase();
-          tagAllocInst->erase();
+          tagAllocOp->erase();
         }
       }
     }
@@ -317,12 +315,12 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
   // Store shift for operation for later lookup for AffineApplyOp's.
   DenseMap<Operation *, unsigned> instShiftMap;
   for (auto &pair : startWaitPairs) {
-    auto *dmaStartInst = pair.first;
-    assert(isa<AffineDmaStartOp>(dmaStartInst));
-    instShiftMap[dmaStartInst] = 0;
+    auto *dmaStartOp = pair.first;
+    assert(isa<AffineDmaStartOp>(dmaStartOp));
+    instShiftMap[dmaStartOp] = 0;
     // Set shifts for DMA start op's affine operand computation slices to 0.
     SmallVector<AffineApplyOp, 4> sliceOps;
-    mlir::createAffineComputationSlice(dmaStartInst, &sliceOps);
+    mlir::createAffineComputationSlice(dmaStartOp, &sliceOps);
     if (!sliceOps.empty()) {
       for (auto sliceOp : sliceOps) {
         instShiftMap[sliceOp.getOperation()] = 0;
@@ -331,7 +329,7 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
       // If a slice wasn't created, the reachable affine.apply op's from its
       // operands are the ones that go with it.
       SmallVector<Operation *, 4> affineApplyInsts;
-      SmallVector<Value, 4> operands(dmaStartInst->getOperands());
+      SmallVector<Value, 4> operands(dmaStartOp->getOperands());
       getReachableAffineApplyOps(operands, affineApplyInsts);
       for (auto *op : affineApplyInsts) {
         instShiftMap[op] = 0;
@@ -339,16 +337,14 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
     }
   }
   // Everything else (including compute ops and dma finish) are shifted by one.
-  for (auto &op : *forOp.getBody()) {
-    if (instShiftMap.find(&op) == instShiftMap.end()) {
+  for (auto &op : forOp.getBody()->without_terminator())
+    if (instShiftMap.find(&op) == instShiftMap.end())
       instShiftMap[&op] = 1;
-    }
-  }
 
   // Get shifts stored in map.
   std::vector<uint64_t> shifts(forOp.getBody()->getOperations().size());
   unsigned s = 0;
-  for (auto &op : *forOp.getBody()) {
+  for (auto &op : forOp.getBody()->without_terminator()) {
     assert(instShiftMap.find(&op) != instShiftMap.end());
     shifts[s++] = instShiftMap[&op];
 
@@ -365,7 +361,7 @@ void PipelineDataTransfer::runOnAffineForOp(AffineForOp forOp) {
     return;
   }
 
-  if (failed(instBodySkew(forOp, shifts))) {
+  if (failed(affineForOpBodySkew(forOp, shifts))) {
     LLVM_DEBUG(llvm::dbgs() << "op body skewing failed - unexpected\n";);
     return;
   }
diff --git a/mlir/lib/Transforms/Utils/LoopUtils.cpp b/mlir/lib/Transforms/Utils/LoopUtils.cpp
index 0df8837503d79..96b4e72eff488 100644
--- a/mlir/lib/Transforms/Utils/LoopUtils.cpp
+++ b/mlir/lib/Transforms/Utils/LoopUtils.cpp
@@ -156,65 +156,57 @@ void mlir::promoteSingleIterationLoops(FuncOp f) {
   f.walk([](AffineForOp forOp) { promoteIfSingleIteration(forOp); });
 }
 
-/// Generates a 'affine.for' op with the specified lower and upper bounds
-/// while generating the right IV remappings for the shifted operations. The
-/// operation blocks that go into the loop are specified in instGroupQueue
-/// starting from the specified offset, and in that order; the first element of
-/// the pair specifies the shift applied to that group of operations; note
-/// that the shift is multiplied by the loop step before being applied. Returns
-/// nullptr if the generated loop simplifies to a single iteration one.
-static AffineForOp
-generateLoop(AffineMap lbMap, AffineMap ubMap,
-             const std::vector<std::pair<uint64_t, ArrayRef<Operation *>>>
-                 &instGroupQueue,
-             unsigned offset, AffineForOp srcForInst, OpBuilder b) {
-  auto lbOperands = srcForInst.getLowerBoundOperands();
-  auto ubOperands = srcForInst.getUpperBoundOperands();
+/// Generates an affine.for op with the specified lower and upper bounds
+/// while generating the right IV remappings to realize shifts for operations in
+/// its body. The operations that go into the loop body are specified in
+/// opGroupQueue starting from the specified offset, and in that order. The
+/// first element of the pair specifies the shift applied to that group of
+/// operations; the shift is multiplied by the loop step before being applied.
+/// Returns nullptr if the generated loop simplifies to a single iteration one.
+static AffineForOp generateShiftedLoop(
+    AffineMap lbMap, AffineMap ubMap,
+    const std::vector<std::pair<uint64_t, ArrayRef<Operation *>>> &opGroupQueue,
+    unsigned offset, AffineForOp srcForOp, OpBuilder b) {
+  auto lbOperands = srcForOp.getLowerBoundOperands();
+  auto ubOperands = srcForOp.getUpperBoundOperands();
 
   assert(lbMap.getNumInputs() == lbOperands.size());
   assert(ubMap.getNumInputs() == ubOperands.size());
 
-  auto loopChunk =
-      b.create<AffineForOp>(srcForInst.getLoc(), lbOperands, lbMap, ubOperands,
-                            ubMap, srcForInst.getStep());
+  auto loopChunk = b.create<AffineForOp>(srcForOp.getLoc(), lbOperands, lbMap,
+                                         ubOperands, ubMap, srcForOp.getStep());
   auto loopChunkIV = loopChunk.getInductionVar();
-  auto srcIV = srcForInst.getInductionVar();
+  auto srcIV = srcForOp.getInductionVar();
 
   BlockAndValueMapping operandMap;
 
   OpBuilder bodyBuilder = loopChunk.getBodyBuilder();
-  for (auto it = instGroupQueue.begin() + offset, e = instGroupQueue.end();
-       it != e; ++it) {
+  for (auto it = opGroupQueue.begin() + offset, e = opGroupQueue.end(); it != e;
+       ++it) {
     uint64_t shift = it->first;
-    auto insts = it->second;
+    auto ops = it->second;
     // All 'same shift' operations get added with their operands being
     // remapped to results of cloned operations, and their IV used remapped.
     // Generate the remapping if the shift is not zero: remappedIV = newIV -
     // shift.
     if (!srcIV.use_empty() && shift != 0) {
       auto ivRemap = bodyBuilder.create<AffineApplyOp>(
-          srcForInst.getLoc(),
+          srcForOp.getLoc(),
           bodyBuilder.getSingleDimShiftAffineMap(
-              -static_cast<int64_t>(srcForInst.getStep() * shift)),
+              -static_cast<int64_t>(srcForOp.getStep() * shift)),
           loopChunkIV);
       operandMap.map(srcIV, ivRemap);
     } else {
       operandMap.map(srcIV, loopChunkIV);
     }
-    for (auto *op : insts) {
-      if (!isa<AffineTerminatorOp>(op))
-        bodyBuilder.clone(*op, operandMap);
-    }
+    for (auto *op : ops)
+      bodyBuilder.clone(*op, operandMap);
   };
   if (succeeded(promoteIfSingleIteration(loopChunk)))
     return AffineForOp();
   return loopChunk;
 }
 
-/// Skew the operations in the body of a 'affine.for' operation with the
-/// specified operation-wise shifts. The shifts are with respect to the
-/// original execution order, and are multiplied by the loop 'step' before being
-/// applied. A shift of zero for each operation will lead to no change.
 // The skewing of operations with respect to one another can be used for
 // example to allow overlap of asynchronous operations (such as DMA
 // communication) with computation, or just relative shifting of operations
@@ -226,8 +218,9 @@ generateLoop(AffineMap lbMap, AffineMap ubMap,
 // asserts preservation of SSA dominance. A check for that as well as that for
 // memory-based dependence preservation check rests with the users of this
 // method.
-LogicalResult mlir::instBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts,
-                                 bool unrollPrologueEpilogue) {
+LogicalResult mlir::affineForOpBodySkew(AffineForOp forOp,
+                                        ArrayRef<uint64_t> shifts,
+                                        bool unrollPrologueEpilogue) {
   if (forOp.getBody()->begin() == std::prev(forOp.getBody()->end()))
     return success();
 
@@ -263,11 +256,11 @@ LogicalResult mlir::instBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts,
   // An array of operation groups sorted by shift amount; each group has all
   // operations with the same shift in the order in which they appear in the
   // body of the 'affine.for' op.
-  std::vector<std::vector<Operation *>> sortedInstGroups(maxShift + 1);
+  std::vector<std::vector<Operation *>> sortedOpGroups(maxShift + 1);
   unsigned pos = 0;
-  for (auto &op : *forOp.getBody()) {
+  for (auto &op : forOp.getBody()->without_terminator()) {
     auto shift = shifts[pos++];
-    sortedInstGroups[shift].push_back(&op);
+    sortedOpGroups[shift].push_back(&op);
   }
 
   // Unless the shifts have a specific pattern (which actually would be the
@@ -275,40 +268,39 @@ LogicalResult mlir::instBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts,
   // Nevertheless, if 'unrollPrologueEpilogue' is set, we will treat the first
   // loop generated as the prologue and the last as epilogue and unroll these
   // fully.
-  AffineForOp prologue;
-  AffineForOp epilogue;
+  AffineForOp prologue, epilogue;
 
   // Do a sweep over the sorted shifts while storing open groups in a
   // vector, and generating loop portions as necessary during the sweep. A block
   // of operations is paired with its shift.
-  std::vector<std::pair<uint64_t, ArrayRef<Operation *>>> instGroupQueue;
+  std::vector<std::pair<uint64_t, ArrayRef<Operation *>>> opGroupQueue;
 
   auto origLbMap = forOp.getLowerBoundMap();
   uint64_t lbShift = 0;
   OpBuilder b(forOp.getOperation());
-  for (uint64_t d = 0, e = sortedInstGroups.size(); d < e; ++d) {
+  for (uint64_t d = 0, e = sortedOpGroups.size(); d < e; ++d) {
     // If nothing is shifted by d, continue.
-    if (sortedInstGroups[d].empty())
+    if (sortedOpGroups[d].empty())
       continue;
-    if (!instGroupQueue.empty()) {
+    if (!opGroupQueue.empty()) {
       assert(d >= 1 &&
              "Queue expected to be empty when the first block is found");
       // The interval for which the loop needs to be generated here is:
       // [lbShift, min(lbShift + tripCount, d)) and the body of the
-      // loop needs to have all operations in instQueue in that order.
+      // loop needs to have all operations in opQueue in that order.
       AffineForOp res;
       if (lbShift + tripCount * step < d * step) {
-        res = generateLoop(
+        res = generateShiftedLoop(
             b.getShiftedAffineMap(origLbMap, lbShift),
             b.getShiftedAffineMap(origLbMap, lbShift + tripCount * step),
-            instGroupQueue, 0, forOp, b);
+            opGroupQueue, /*offset=*/0, forOp, b);
         // Entire loop for the queued op groups generated, empty it.
-        instGroupQueue.clear();
+        opGroupQueue.clear();
         lbShift += tripCount * step;
       } else {
-        res = generateLoop(b.getShiftedAffineMap(origLbMap, lbShift),
-                           b.getShiftedAffineMap(origLbMap, d), instGroupQueue,
-                           0, forOp, b);
+        res = generateShiftedLoop(b.getShiftedAffineMap(origLbMap, lbShift),
+                                  b.getShiftedAffineMap(origLbMap, d),
+                                  opGroupQueue, /*offset=*/0, forOp, b);
         lbShift = d * step;
       }
       if (!prologue && res)
@@ -319,16 +311,16 @@ LogicalResult mlir::instBodySkew(AffineForOp forOp, ArrayRef<uint64_t> shifts,
       lbShift = d * step;
     }
     // Augment the list of operations that get into the current open interval.
-    instGroupQueue.push_back({d, sortedInstGroups[d]});
+    opGroupQueue.push_back({d, sortedOpGroups[d]});
   }
 
   // Those operations groups left in the queue now need to be processed (FIFO)
   // and their loops completed.
-  for (unsigned i = 0, e = instGroupQueue.size(); i < e; ++i) {
-    uint64_t ubShift = (instGroupQueue[i].first + tripCount) * step;
-    epilogue = generateLoop(b.getShiftedAffineMap(origLbMap, lbShift),
-                            b.getShiftedAffineMap(origLbMap, ubShift),
-                            instGroupQueue, i, forOp, b);
+  for (unsigned i = 0, e = opGroupQueue.size(); i < e; ++i) {
+    uint64_t ubShift = (opGroupQueue[i].first + tripCount) * step;
+    epilogue = generateShiftedLoop(b.getShiftedAffineMap(origLbMap, lbShift),
+                                   b.getShiftedAffineMap(origLbMap, ubShift),
+                                   opGroupQueue, /*offset=*/i, forOp, b);
     lbShift = ubShift;
     if (!prologue)
       prologue = epilogue;
diff --git a/mlir/lib/Transforms/Vectorize.cpp b/mlir/lib/Transforms/Vectorize.cpp
index c5d0f57daf365..75a7d4d5cf6ba 100644
--- a/mlir/lib/Transforms/Vectorize.cpp
+++ b/mlir/lib/Transforms/Vectorize.cpp
@@ -17,8 +17,8 @@
 #include "mlir/Analysis/Utils.h"
 #include "mlir/Dialect/AffineOps/AffineOps.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
-#include "mlir/Dialect/VectorOps/VectorUtils.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorUtils.h"
 #include "mlir/IR/AffineExpr.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/Location.h"
diff --git a/mlir/test/Conversion/GPUToVulkan/invoke-vulkan.mlir b/mlir/test/Conversion/GPUToVulkan/invoke-vulkan.mlir
index 060e2b3c93db6..4313eb5548535 100644
--- a/mlir/test/Conversion/GPUToVulkan/invoke-vulkan.mlir
+++ b/mlir/test/Conversion/GPUToVulkan/invoke-vulkan.mlir
@@ -6,7 +6,7 @@
 // CHECK: %[[addressof_SPIRV_BIN:.*]] = llvm.mlir.addressof @SPIRV_BIN
 // CHECK: %[[SPIRV_BIN_ptr:.*]] = llvm.getelementptr %[[addressof_SPIRV_BIN]]
 // CHECK: %[[SPIRV_BIN_size:.*]] = llvm.mlir.constant
-// CHECK: llvm.call @bindResource(%[[Vulkan_Runtime_ptr]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) : (!llvm<"i8*">, !llvm.i32, !llvm.i32, !llvm<"float*">, !llvm.i64) -> !llvm.void
+// CHECK: llvm.call @bindMemRef1DFloat(%[[Vulkan_Runtime_ptr]], %{{.*}}, %{{.*}}, %{{.*}}) : (!llvm<"i8*">, !llvm.i32, !llvm.i32, !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }*">) -> !llvm.void
 // CHECK: llvm.call @setBinaryShader(%[[Vulkan_Runtime_ptr]], %[[SPIRV_BIN_ptr]], %[[SPIRV_BIN_size]]) : (!llvm<"i8*">, !llvm<"i8*">, !llvm.i32) -> !llvm.void
 // CHECK: %[[addressof_entry_point:.*]] = llvm.mlir.addressof @kernel_spv_entry_point_name
 // CHECK: %[[entry_point_ptr:.*]] = llvm.getelementptr %[[addressof_entry_point]]
@@ -44,5 +44,18 @@ module attributes {gpu.container_module} {
     : (!llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm<"float*">, !llvm<"float*">, !llvm.i64, !llvm.i64, !llvm.i64) -> ()
     llvm.return
   }
-  llvm.func @vulkanLaunch(!llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm<"float*">, !llvm<"float*">, !llvm.i64, !llvm.i64, !llvm.i64)
+  llvm.func @vulkanLaunch(%arg0: !llvm.i64, %arg1: !llvm.i64, %arg2: !llvm.i64, %arg3: !llvm.i64, %arg4: !llvm.i64, %arg5: !llvm.i64, %arg6: !llvm<"float*">, %arg7: !llvm<"float*">, %arg8: !llvm.i64, %arg9: !llvm.i64, %arg10: !llvm.i64) {
+    %0 = llvm.mlir.undef : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
+    %1 = llvm.insertvalue %arg6, %0[0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
+    %2 = llvm.insertvalue %arg7, %1[1] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
+    %3 = llvm.insertvalue %arg8, %2[2] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
+    %4 = llvm.insertvalue %arg9, %3[3, 0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
+    %5 = llvm.insertvalue %arg10, %4[4, 0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
+    %6 = llvm.mlir.constant(1 : index) : !llvm.i64
+    %7 = llvm.alloca %6 x !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }"> : (!llvm.i64) -> !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }*">
+    llvm.store %5, %7 : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }*">
+    llvm.call @_mlir_ciface_vulkanLaunch(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %7) : (!llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }*">) -> ()
+    llvm.return
+  }
+  llvm.func @_mlir_ciface_vulkanLaunch(!llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }*">)
 }
diff --git a/mlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir b/mlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir
index 6406a547bef56..699ea31836a5c 100644
--- a/mlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir
+++ b/mlir/test/Conversion/StandardToLLVM/convert-to-llvmir.mlir
@@ -554,19 +554,6 @@ func @dfs_block_order(%arg0: i32) -> (i32) {
 // CHECK-NEXT:  llvm.br ^bb1
   br ^bb1
 }
-// CHECK-LABEL: func @cond_br_same_target(%arg0: !llvm.i1, %arg1: !llvm.i32, %arg2: !llvm.i32)
-func @cond_br_same_target(%arg0: i1, %arg1: i32, %arg2 : i32) -> (i32) {
-// CHECK-NEXT:  llvm.cond_br %arg0, ^[[origBlock:bb[0-9]+]](%arg1 : !llvm.i32), ^[[dummyBlock:bb[0-9]+]](%arg2 : !llvm.i32)
-  cond_br %arg0, ^bb1(%arg1 : i32), ^bb1(%arg2 : i32)
-
-// CHECK:      ^[[origBlock]](%[[BLOCKARG1:.*]]: !llvm.i32):
-// CHECK-NEXT:  llvm.return %[[BLOCKARG1]] : !llvm.i32
-^bb1(%0 : i32):
-  return %0 : i32
-
-// CHECK:      ^[[dummyBlock]](%[[BLOCKARG2:.*]]: !llvm.i32):
-// CHECK-NEXT:  llvm.br ^[[origBlock]](%[[BLOCKARG2]] : !llvm.i32)
-}
 
 // CHECK-LABEL: func @fcmp(%arg0: !llvm.float, %arg1: !llvm.float) {
 func @fcmp(f32, f32) -> () {
diff --git a/mlir/test/Dialect/AffineOps/canonicalize.mlir b/mlir/test/Dialect/AffineOps/canonicalize.mlir
index 26220925bfb31..ede438eb0bd4d 100644
--- a/mlir/test/Dialect/AffineOps/canonicalize.mlir
+++ b/mlir/test/Dialect/AffineOps/canonicalize.mlir
@@ -448,7 +448,7 @@ func @canonicalize_affine_if(%M : index, %N : index) {
 // -----
 
 // CHECK-DAG: [[LBMAP:#map[0-9]+]] = affine_map<()[s0] -> (0, s0)>
-// CHECK-DAG: [[UBMAP:#map[0-9]+]] = affine_map<()[s0] -> (1024, s0 + s0)>
+// CHECK-DAG: [[UBMAP:#map[0-9]+]] = affine_map<()[s0] -> (1024, s0 * 2)>
 
 // CHECK-LABEL: func @canonicalize_bounds
 // CHECK-SAME: [[M:%.*]]: index,
diff --git a/mlir/test/Dialect/LLVMIR/invalid.mlir b/mlir/test/Dialect/LLVMIR/invalid.mlir
index eaee62ef83249..03de594083dde 100644
--- a/mlir/test/Dialect/LLVMIR/invalid.mlir
+++ b/mlir/test/Dialect/LLVMIR/invalid.mlir
@@ -561,3 +561,10 @@ llvm.func @caller(%arg0: !llvm.i32) -> !llvm.i32 {
   %2 = llvm.landingpad : !llvm<"{ i8*, i32 }">
   llvm.return %0 : !llvm.i32
 }
+
+// -----
+
+func @invalid_ordering_in_fence() {
+  // expected-error @+1 {{can be given only acquire, release, acq_rel, and seq_cst orderings}}
+  llvm.fence syncscope("agent") monotonic
+}
diff --git a/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir b/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir
new file mode 100644
index 0000000000000..f695f2c362f88
--- /dev/null
+++ b/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir
@@ -0,0 +1,31 @@
+// RUN: mlir-opt -llvm-legalize-for-export %s | FileCheck %s
+
+// Verifies that duplicate successor with different arguments are deduplicated
+// by introducing a new block that forwards its arguments to the original
+// successor through an unconditional branch.
+// CHECK-LABEL: @repeated_successor_different_args
+llvm.func @repeated_successor_different_args(%arg0: !llvm.i1, %arg1: !llvm.i32, %arg2: !llvm.i32) {
+  // CHECK: llvm.cond_br %{{.*}}, ^[[BB1:.*]]({{.*}}), ^[[BB2:.*]]({{.*}})
+  llvm.cond_br %arg0, ^bb1(%arg1: !llvm.i32), ^bb1(%arg2: !llvm.i32)
+
+// CHECK: ^[[BB1]]({{.*}}):
+^bb1(%arg3: !llvm.i32):
+  llvm.return
+
+// CHECK: ^[[BB2]](%[[ARG:.*]]: !llvm.i32):
+// CHECK:  llvm.br ^[[BB1]](%[[ARG]] : !llvm.i32)
+}
+
+// Verifies that duplicate successors without arguments do not lead to the
+// introduction of new blocks during legalization.
+// CHECK-LABEL: @repeated_successor_no_args
+llvm.func @repeated_successor_no_args(%arg0: !llvm.i1) {
+  // CHECK: llvm.cond_br
+  llvm.cond_br %arg0, ^bb1, ^bb1
+
+// CHECK: ^{{.*}}:
+^bb1:
+  llvm.return
+
+// CHECK-NOT: ^{{.*}}:
+}
diff --git a/mlir/test/Dialect/LLVMIR/roundtrip.mlir b/mlir/test/Dialect/LLVMIR/roundtrip.mlir
index 8a8de4cf6f213..32fe4c496523a 100644
--- a/mlir/test/Dialect/LLVMIR/roundtrip.mlir
+++ b/mlir/test/Dialect/LLVMIR/roundtrip.mlir
@@ -292,4 +292,15 @@ func @useFreezeOp(%arg0: !llvm.i32) {
   // CHECK:  = llvm.freeze %[[x]] : !llvm.i8
   %2 = llvm.freeze %1 : !llvm.i8
   return
+}
+
+// CHECK-LABEL: @useFenceInst
+func @useFenceInst() {
+  // CHECK:  syncscope("agent") seq_cst 
+  llvm.fence syncscope("agent") seq_cst
+  // CHECK:  seq_cst 
+  llvm.fence syncscope("") seq_cst
+  // CHECK:  release
+  llvm.fence release
+  return
 }
\ No newline at end of file
diff --git a/mlir/test/Dialect/QuantOps/canonicalize.mlir b/mlir/test/Dialect/Quant/canonicalize.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/canonicalize.mlir
rename to mlir/test/Dialect/Quant/canonicalize.mlir
diff --git a/mlir/test/Dialect/QuantOps/convert-const.mlir b/mlir/test/Dialect/Quant/convert-const.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/convert-const.mlir
rename to mlir/test/Dialect/Quant/convert-const.mlir
diff --git a/mlir/test/Dialect/QuantOps/convert-fakequant-invalid.mlir b/mlir/test/Dialect/Quant/convert-fakequant-invalid.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/convert-fakequant-invalid.mlir
rename to mlir/test/Dialect/Quant/convert-fakequant-invalid.mlir
diff --git a/mlir/test/Dialect/QuantOps/convert-fakequant.mlir b/mlir/test/Dialect/Quant/convert-fakequant.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/convert-fakequant.mlir
rename to mlir/test/Dialect/Quant/convert-fakequant.mlir
diff --git a/mlir/test/Dialect/QuantOps/parse-any-invalid.mlir b/mlir/test/Dialect/Quant/parse-any-invalid.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/parse-any-invalid.mlir
rename to mlir/test/Dialect/Quant/parse-any-invalid.mlir
diff --git a/mlir/test/Dialect/QuantOps/parse-any.mlir b/mlir/test/Dialect/Quant/parse-any.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/parse-any.mlir
rename to mlir/test/Dialect/Quant/parse-any.mlir
diff --git a/mlir/test/Dialect/QuantOps/parse-ops-invalid.mlir b/mlir/test/Dialect/Quant/parse-ops-invalid.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/parse-ops-invalid.mlir
rename to mlir/test/Dialect/Quant/parse-ops-invalid.mlir
diff --git a/mlir/test/Dialect/QuantOps/parse-ops.mlir b/mlir/test/Dialect/Quant/parse-ops.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/parse-ops.mlir
rename to mlir/test/Dialect/Quant/parse-ops.mlir
diff --git a/mlir/test/Dialect/QuantOps/parse-uniform-invalid.mlir b/mlir/test/Dialect/Quant/parse-uniform-invalid.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/parse-uniform-invalid.mlir
rename to mlir/test/Dialect/Quant/parse-uniform-invalid.mlir
diff --git a/mlir/test/Dialect/QuantOps/parse-uniform.mlir b/mlir/test/Dialect/Quant/parse-uniform.mlir
similarity index 100%
rename from mlir/test/Dialect/QuantOps/parse-uniform.mlir
rename to mlir/test/Dialect/Quant/parse-uniform.mlir
diff --git a/mlir/test/Dialect/Quant/quant_region.mlir b/mlir/test/Dialect/Quant/quant_region.mlir
new file mode 100644
index 0000000000000..ee874211a7acb
--- /dev/null
+++ b/mlir/test/Dialect/Quant/quant_region.mlir
@@ -0,0 +1,101 @@
+// RUN: mlir-opt -split-input-file -verify-diagnostics %s | FileCheck %s
+
+// CHECK-LABEL: @source
+func @source(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  %0 = "quant.region"(%arg0, %arg1, %arg2) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>, %12: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      %14 = "bar"(%13, %12) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [f32, f32, f32], output_specs = [f32], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
+// CHECK-LABEL: @annotated
+func @annotated(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  %0 = "quant.region"(%arg0, %arg1, %arg2) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>, %12: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      %14 = "bar"(%13, %12) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [!quant.uniform<i8:f32, 1.0>, !quant.uniform<i8:f32, 2.0>, f32],
+      output_specs = [!quant.uniform<i8:f32, 4.0>], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
+// CHECK-LABEL: @quantized
+func @quantized(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  %0 = "quant.region"(%arg0, %arg1, %arg2) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>, %12: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      %14 = "bar"(%13, %12) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [!quant.uniform<i8:f32, 1.0>, !quant.uniform<i8:f32, 2.0>, !quant.uniform<i32:f32, 2.0>],
+      output_specs = [!quant.uniform<i8:f32, 4.0>], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
+// -----
+
+func @unmatched_quantize(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  // @expected-error @+1 {{'quant.region' op has incompatible specification !quant.uniform<i32:f16, 3.000000e+00> and input type 'tensor<4xf32>'}}
+  %0 = "quant.region"(%arg0, %arg1, %arg2) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>, %12: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      %14 = "bar"(%13, %12) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [!quant.uniform<i8:f32, 1.0>, !quant.uniform<i8:f32, 2.0>, !quant.uniform<i32:f16, 3.0>],
+      output_specs = [!quant.uniform<i8:f32, 4.0>], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
+// -----
+
+func @unmatched_primitive(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  // @expected-error @+1 {{'quant.region' op has incompatible specification i32 and input type 'tensor<4xf32>'}}
+  %0 = "quant.region"(%arg0, %arg1, %arg2) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>, %12: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      %14 = "bar"(%13, %12) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [!quant.uniform<i8:f32, 1.0>, !quant.uniform<i8:f32, 2.0>, i32],
+      output_specs = [!quant.uniform<i8:f32, 4.0>], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
+// -----
+
+func @unmatched_number(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  // @expected-error @+1 {{'quant.region' op has unmatched operands/results number and spec attributes number}}
+  %0 = "quant.region"(%arg0, %arg1, %arg2) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>, %12: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      %14 = "bar"(%13, %12) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [!quant.uniform<i8:f32, 1.0>, !quant.uniform<i8:f32, 2.0>],
+      output_specs = [!quant.uniform<i8:f32, 4.0>], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
+// -----
+
+func @isolated(%arg0: tensor<4xf32>, %arg1: tensor<4xf32>, %arg2: tensor<4xf32>) -> (tensor<4xf32>) {
+  // @expected-note @+1 {{required by region isolation constraints}}
+  %0 = "quant.region"(%arg0, %arg1) ({
+    ^bb0(%10: tensor<4xf32>, %11: tensor<4xf32>):
+      %13 = "foo"(%10, %11) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      // @expected-error @+1 {{'bar' op using value defined outside the region}}
+      %14 = "bar"(%13, %arg2) : (tensor<4xf32>, tensor<4xf32>) -> tensor<4xf32>
+      "quant.return"(%14) : (tensor<4xf32>) -> ()
+  }) {input_specs = [!quant.uniform<i8:f32, 1.0>, !quant.uniform<i8:f32, 2.0>],
+      output_specs = [!quant.uniform<i8:f32, 4.0>], logical_kernel = "xyz"}
+    : (tensor<4xf32>, tensor<4xf32>) -> (tensor<4xf32>)
+  return %0 : tensor<4xf32>
+}
+
diff --git a/mlir/test/Dialect/Shape/ops.mlir b/mlir/test/Dialect/Shape/ops.mlir
new file mode 100644
index 0000000000000..0dc1c32894d2f
--- /dev/null
+++ b/mlir/test/Dialect/Shape/ops.mlir
@@ -0,0 +1,58 @@
+// RUN: mlir-opt -split-input-file %s | FileCheck %s --dump-input-on-failure
+
+// CHECK-LABEL: shape_num_elements
+func @shape_num_elements(%shape : !shape.shape) -> !shape.size {
+  %0 = shape.constant 0 : !shape.size
+  %1 = "shape.reduce"(%shape, %0) ( {
+    ^bb0(%index: i32, %dim: !shape.size, %lci: !shape.size):
+      %acc = "shape.add"(%lci, %dim) : (!shape.size, !shape.size) -> !shape.size
+      "shape.yield"(%acc) : (!shape.size) -> ()
+    }) : (!shape.shape, !shape.size) -> (!shape.size)
+  return %1 : !shape.size
+}
+
+func @test_shape_num_elements_unknown() {
+  %0 = "shape.unknown_shape"() : () -> !shape.shape
+  %1 = call @shape_num_elements(%0) : (!shape.shape) -> (!shape.size)
+  %2 = "shape.print"(%1) : (!shape.size) -> !shape.size
+  return
+}
+
+func @test_shape_num_elements_fixed() {
+  %0 = "shape.constant"() { value = [1, 57, 92] }: () -> !shape.shape
+  %1 = call @shape_num_elements(%0) : (!shape.shape) -> (!shape.size)
+  %3 = "shape.print"(%1) : (!shape.size) -> !shape.size
+  return
+}
+
+func @test_broadcastable_fixed() {
+  %0 = "shape.constant"() { value = [10, 1, 57, 92] }: () -> !shape.shape
+  %1 = "shape.constant"() { value = [4, 57, 92] }: () -> !shape.shape
+  %2 = "shape.broadcastable"(%0, %1) : (!shape.shape, !shape.shape) -> !shape.shape
+  %3 = "shape.print"(%2) : (!shape.shape) -> !shape.shape
+  return
+}
+
+func @test_shape_any_fixed() {
+  %0 = "shape.constant"() { value = [4, 57, 92] }: () -> !shape.shape
+  %1 = "shape.constant"() { value = [4, 57, 92] }: () -> !shape.shape
+  %2 = "shape.join"(%0, %1) : (!shape.shape, !shape.shape) -> !shape.shape
+  %3 = "shape.print"(%2) : (!shape.shape) -> !shape.shape
+  return
+}
+
+func @test_shape_any_unknown() {
+  %0 = "shape.constant"() { value = [4, -1, 92] }: () -> !shape.shape
+  %1 = "shape.constant"() { value = [-1, 57, 92] }: () -> !shape.shape
+  %2 = "shape.join"(%0, %1) : (!shape.shape, !shape.shape) -> !shape.shape
+  %3 = "shape.print"(%2) : (!shape.shape) -> !shape.shape
+  return
+}
+
+func @test_shape_any_fixed_mismatch() {
+  %0 = "shape.constant"() { value = [4, 57, 92] }: () -> !shape.shape
+  %1 = "shape.constant"() { value = [2, 57, 92] }: () -> !shape.shape
+  %2 = "shape.join"(%0, %1) : (!shape.shape, !shape.shape) -> !shape.shape
+  %3 = "shape.print"(%2) : (!shape.shape) -> !shape.shape
+  return
+}
diff --git a/mlir/test/Dialect/VectorOps/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir
similarity index 100%
rename from mlir/test/Dialect/VectorOps/canonicalize.mlir
rename to mlir/test/Dialect/Vector/canonicalize.mlir
diff --git a/mlir/test/Dialect/VectorOps/invalid.mlir b/mlir/test/Dialect/Vector/invalid.mlir
similarity index 100%
rename from mlir/test/Dialect/VectorOps/invalid.mlir
rename to mlir/test/Dialect/Vector/invalid.mlir
diff --git a/mlir/test/Dialect/VectorOps/ops.mlir b/mlir/test/Dialect/Vector/ops.mlir
similarity index 100%
rename from mlir/test/Dialect/VectorOps/ops.mlir
rename to mlir/test/Dialect/Vector/ops.mlir
diff --git a/mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir b/mlir/test/Dialect/Vector/vector-contract-transforms.mlir
similarity index 99%
rename from mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir
rename to mlir/test/Dialect/Vector/vector-contract-transforms.mlir
index 2440c7b4a566b..bed90d6341d94 100644
--- a/mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir
+++ b/mlir/test/Dialect/Vector/vector-contract-transforms.mlir
@@ -1,5 +1,5 @@
 // RUN: mlir-opt %s -test-vector-contraction-conversion | FileCheck %s
-// RUN: mlir-opt %s -test-vector-contraction-conversion -vector-lower-matrix-intrinsics | FileCheck %s --check-prefix=MATRIX
+// RUN: mlir-opt %s -test-vector-contraction-conversion=vector-lower-matrix-intrinsics=1 | FileCheck %s --check-prefix=MATRIX
 
 #dotp_accesses = [
   affine_map<(i) -> (i)>,
diff --git a/mlir/test/Dialect/VectorOps/vector-slices-transforms.mlir b/mlir/test/Dialect/Vector/vector-slices-transforms.mlir
similarity index 100%
rename from mlir/test/Dialect/VectorOps/vector-slices-transforms.mlir
rename to mlir/test/Dialect/Vector/vector-slices-transforms.mlir
diff --git a/mlir/test/Dialect/VectorOps/vector-transforms.mlir b/mlir/test/Dialect/Vector/vector-transforms.mlir
similarity index 100%
rename from mlir/test/Dialect/VectorOps/vector-transforms.mlir
rename to mlir/test/Dialect/Vector/vector-transforms.mlir
diff --git a/mlir/test/EDSC/CMakeLists.txt b/mlir/test/EDSC/CMakeLists.txt
index b922c594dffd7..c3c0cf35497b7 100644
--- a/mlir/test/EDSC/CMakeLists.txt
+++ b/mlir/test/EDSC/CMakeLists.txt
@@ -14,7 +14,7 @@ target_link_libraries(mlir-edsc-builder-api-test
   MLIRLoopOps
   MLIRStandardOps
   MLIRTransforms
-  MLIRVectorOps
+  MLIRVector
   LLVMCore
   LLVMSupport
 )
@@ -26,6 +26,6 @@ whole_archive_link(mlir-edsc-builder-api-test
   MLIRLinalgOps
   MLIRLoopOps
   MLIRStandardOps
-  MLIRVectorOps
+  MLIRVector
   MLIRTransforms
 )
diff --git a/mlir/test/EDSC/builder-api-test.cpp b/mlir/test/EDSC/builder-api-test.cpp
index 69f615e6434c5..b60d5894df030 100644
--- a/mlir/test/EDSC/builder-api-test.cpp
+++ b/mlir/test/EDSC/builder-api-test.cpp
@@ -12,7 +12,7 @@
 #include "mlir/Dialect/Linalg/EDSC/Intrinsics.h"
 #include "mlir/Dialect/LoopOps/EDSC/Builders.h"
 #include "mlir/Dialect/StandardOps/EDSC/Intrinsics.h"
-#include "mlir/Dialect/VectorOps/EDSC/Intrinsics.h"
+#include "mlir/Dialect/Vector/EDSC/Intrinsics.h"
 #include "mlir/EDSC/Builders.h"
 #include "mlir/EDSC/Intrinsics.h"
 #include "mlir/IR/AffineExpr.h"
@@ -42,7 +42,7 @@ static MLIRContext &globalContext() {
     registerDialect<linalg::LinalgDialect>();
     registerDialect<loop::LoopOpsDialect>();
     registerDialect<StandardOpsDialect>();
-    registerDialect<vector::VectorOpsDialect>();
+    registerDialect<vector::VectorDialect>();
     return true;
   }();
   (void)init_once;
diff --git a/mlir/test/IR/affine-map.mlir b/mlir/test/IR/affine-map.mlir
index 9ce4d8c0bfc74..d4c80049b7423 100644
--- a/mlir/test/IR/affine-map.mlir
+++ b/mlir/test/IR/affine-map.mlir
@@ -33,7 +33,7 @@
 // The following reduction should be unique'd out too but such expression
 // simplification is not performed for IR parsing, but only through analyses
 // and transforms.
-// CHECK: #map{{[0-9]+}} = affine_map<(d0, d1) -> (d1 - d0 + (d0 - d1 + 1) * 2 + d1 - 1, d1 + d1 + d1 + d1 + 2)>
+// CHECK: #map{{[0-9]+}} = affine_map<(d0, d1) -> (d1 - d0 + (d0 - d1 + 1) * 2 + d1 - 1, d1 * 4 + 2)>
 #map3l = affine_map<(i, j) -> ((j - i) + 2*(i - j + 1) + j - 1 + 0, j + j + 1 + j + j + 1)>
 
 // CHECK: #map{{[0-9]+}} = affine_map<(d0, d1) -> (d0 + 2, d1)>
@@ -183,6 +183,12 @@
 // CHECK: #map{{[0-9]+}} = affine_map<(d0, d1) -> (d0, d0 * 2 + d1 * 4 + 2, 1, 2, (d0 * 4) mod 8)>
 #map56 = affine_map<(d0, d1) -> ((4*d0 + 2) floordiv 4, (4*d0 + 8*d1 + 5) floordiv 2, (2*d0 + 4*d1 + 3) mod 2, (3*d0 - 4) mod 3, (4*d0 + 8*d1) mod 8)>
 
+// CHECK: #map{{[0-9]+}} = affine_map<(d0, d1) -> (d1, d0, 0)>
+#map57 = affine_map<(d0, d1) -> (d0 - d0 + d1, -d0 + d0 + d0, (1 + d0 + d1 floordiv 4) - (d0 + d1 floordiv 4 + 1))>
+
+// CHECK: #map{{[0-9]+}} = affine_map<(d0, d1) -> (d0 * 3, (d0 + d1) * 2, d0 mod 2)>
+#map58 = affine_map<(d0, d1) -> (4*d0 - 2*d0 + d0, (d0 + d1) + (d0 + d1), 2 * (d0 mod 2) - d0 mod 2)>
+
 // Single identity maps are removed.
 // CHECK: func @f0(memref<2x4xi8, 1>)
 func @f0(memref<2x4xi8, #map0, 1>)
@@ -361,3 +367,9 @@ func @f54(memref<10xi32, #map54>)
 
 // CHECK: func @f56(memref<1x1xi8, #map{{[0-9]+}}>)
 func @f56(memref<1x1xi8, #map56>)
+
+// CHECK: "f57"() {map = #map{{[0-9]+}}} : () -> ()
+"f57"() {map = #map57} : () -> ()
+
+// CHECK: "f58"() {map = #map{{[0-9]+}}} : () -> ()
+"f58"() {map = #map58} : () -> ()
diff --git a/mlir/test/IR/invalid.mlir b/mlir/test/IR/invalid.mlir
index 80b83fe60ec3d..2c008be930fd7 100644
--- a/mlir/test/IR/invalid.mlir
+++ b/mlir/test/IR/invalid.mlir
@@ -535,7 +535,7 @@ func @undefined_function() {
 
 func @bound_symbol_mismatch(%N : index) {
   affine.for %i = #map1(%N) to 100 {
-  // expected-error@-1 {{symbol operand count and integer set symbol count must match}}
+  // expected-error@-1 {{symbol operand count and affine map symbol count must match}}
   }
   return
 }
@@ -546,7 +546,7 @@ func @bound_symbol_mismatch(%N : index) {
 
 func @bound_dim_mismatch(%N : index) {
   affine.for %i = #map1(%N, %N)[%N] to 100 {
-  // expected-error@-1 {{dim operand count and integer set dim count must match}}
+  // expected-error@-1 {{dim operand count and affine map dim count must match}}
   }
   return
 }
diff --git a/mlir/test/Target/import.ll b/mlir/test/Target/import.ll
index 5e38b6b2fe7d6..0394309093f29 100644
--- a/mlir/test/Target/import.ll
+++ b/mlir/test/Target/import.ll
@@ -307,4 +307,15 @@ define i32 @useFreezeOp(i32 %x) {
   %3 = freeze i8 %2
   %poison = add nsw i1 0, undef
   ret i32 0
+}
+
+;CHECK-LABEL: @useFenceInst
+define i32 @useFenceInst() {
+  ;CHECK: llvm.fence syncscope("agent") seq_cst
+  fence syncscope("agent") seq_cst
+  ;CHECK: llvm.fence release
+  fence release
+  ;CHECK: llvm.fence seq_cst
+  fence syncscope("") seq_cst
+  ret i32 0
 }
\ No newline at end of file
diff --git a/mlir/test/Target/llvmir-intrinsics.mlir b/mlir/test/Target/llvmir-intrinsics.mlir
index f0f17966e0c38..7be5e5fd596e5 100644
--- a/mlir/test/Target/llvmir-intrinsics.mlir
+++ b/mlir/test/Target/llvmir-intrinsics.mlir
@@ -152,6 +152,20 @@ llvm.func @matrix_intrinsics(%A: !llvm<"<64 x float>">, %B: !llvm<"<48 x float>"
   llvm.return
 }
 
+// CHECK-LABEL: @masked_intrinsics
+llvm.func @masked_intrinsics(%A: !llvm<"<7 x float>*">, %mask: !llvm<"<7 x i1>">) {
+  // CHECK: call <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>* %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> undef)
+  %a = llvm.intr.masked.load %A, %mask { alignment = 1: i32} :
+    (!llvm<"<7 x float>*">, !llvm<"<7 x i1>">) -> !llvm<"<7 x float>">
+  // CHECK: call <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>* %{{.*}}, i32 1, <7 x i1> %{{.*}}, <7 x float> %{{.*}})
+  %b = llvm.intr.masked.load %A, %mask, %a { alignment = 1: i32} :
+    (!llvm<"<7 x float>*">, !llvm<"<7 x i1>">, !llvm<"<7 x float>">) -> !llvm<"<7 x float>">
+  // CHECK: call void @llvm.masked.store.v7f32.p0v7f32(<7 x float> %{{.*}}, <7 x float>* %0, i32 {{.*}}, <7 x i1> %{{.*}})
+  llvm.intr.masked.store %b, %A, %mask { alignment = 1: i32} :
+    !llvm<"<7 x float>">, !llvm<"<7 x i1>"> into !llvm<"<7 x float>*">
+  llvm.return
+}
+
 // Check that intrinsics are declared with appropriate types.
 // CHECK-DAG: declare float @llvm.fma.f32(float, float, float)
 // CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
@@ -179,3 +193,5 @@ llvm.func @matrix_intrinsics(%A: !llvm<"<64 x float>">, %B: !llvm<"<48 x float>"
 // CHECK-DAG: declare <48 x float> @llvm.matrix.transpose.v48f32(<48 x float>, i32 immarg, i32 immarg)
 // CHECK-DAG: declare <48 x float> @llvm.matrix.columnwise.load.v48f32.p0f32(float*, i32, i32 immarg, i32 immarg)
 // CHECK-DAG: declare void @llvm.matrix.columnwise.store.v48f32.p0f32(<48 x float>, float* writeonly, i32, i32 immarg, i32 immarg)
+// CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>*, i32 immarg, <7 x i1>, <7 x float>)
+// CHECK-DAG: declare void @llvm.masked.store.v7f32.p0v7f32(<7 x float>, <7 x float>*, i32 immarg, <7 x i1>)
diff --git a/mlir/test/Target/llvmir.mlir b/mlir/test/Target/llvmir.mlir
index 7f202b39a471d..43cc7d804daec 100644
--- a/mlir/test/Target/llvmir.mlir
+++ b/mlir/test/Target/llvmir.mlir
@@ -1190,3 +1190,14 @@ llvm.func @boolConstArg() -> !llvm.i1 {
   %2 = llvm.and %0, %1 : !llvm.i1
   llvm.return %2 : !llvm.i1
 }
+
+// CHECK-LABEL: @callFenceInst
+llvm.func @callFenceInst() {
+  // CHECK: fence syncscope("agent") release
+  llvm.fence syncscope("agent") release
+  // CHECK: fence release
+  llvm.fence release
+  // CHECK: fence release
+  llvm.fence syncscope("") release
+  llvm.return
+}
\ No newline at end of file
diff --git a/mlir/test/Transforms/inlining-dce.mlir b/mlir/test/Transforms/inlining-dce.mlir
new file mode 100644
index 0000000000000..d9c8bf983c195
--- /dev/null
+++ b/mlir/test/Transforms/inlining-dce.mlir
@@ -0,0 +1,53 @@
+// RUN: mlir-opt %s -inline | FileCheck %s
+
+// This file tests the callgraph dead code elimination performed by the inliner.
+
+// Function is already dead.
+// CHECK-NOT: func @dead_function
+func @dead_function() attributes {sym_visibility = "private"} {
+  return
+}
+
+// Function becomes dead after inlining.
+// CHECK-NOT: func @dead_function_b
+func @dead_function_b() attributes {sym_visibility = "private"} {
+  return
+}
+
+// CHECK: func @live_function()
+func @live_function() {
+  call @dead_function_b() : () -> ()
+  return
+}
+
+// Same as above, but a transitive example.
+
+// CHECK: func @live_function_b
+func @live_function_b() {
+  return
+}
+// CHECK-NOT: func @dead_function_c
+func @dead_function_c() attributes {sym_visibility = "private"} {
+  call @live_function_b() : () -> ()
+  return
+}
+// CHECK-NOT: func @dead_function_d
+func @dead_function_d() attributes {sym_visibility = "private"} {
+  call @dead_function_c() : () -> ()
+  call @dead_function_c() : () -> ()
+  return
+}
+// CHECK: func @live_function_c
+func @live_function_c() {
+  call @dead_function_c() : () -> ()
+  call @dead_function_d() : () -> ()
+  return
+}
+
+// Function is referenced by non-callable top-level user.
+// CHECK: func @live_function_d
+func @live_function_d() attributes {sym_visibility = "private"} {
+  return
+}
+
+"live.user"() {use = @live_function_d} : () -> ()
diff --git a/mlir/test/Transforms/pipeline-data-transfer.mlir b/mlir/test/Transforms/pipeline-data-transfer.mlir
index 8293120d50e8f..a2ff126255209 100644
--- a/mlir/test/Transforms/pipeline-data-transfer.mlir
+++ b/mlir/test/Transforms/pipeline-data-transfer.mlir
@@ -36,23 +36,23 @@ func @loop_nest_dma() {
 // CHECK-NEXT:  affine.dma_start %{{.*}}[%{{.*}}], %{{.*}}[%{{.*}} mod 2, %{{.*}}], %{{.*}}[%{{.*}} mod 2, 0], %{{.*}} : memref<256xf32>, memref<2x32xf32, 1>, memref<2x1xf32>
 // CHECK-NEXT:  affine.for %{{.*}} = 1 to 8 {
 // CHECK-NEXT:    affine.dma_start %{{.*}}[%{{.*}}], %{{.*}}[%{{.*}} mod 2, %{{.*}}], %{{.*}}[%{{.*}} mod 2, 0], %{{.*}} : memref<256xf32>, memref<2x32xf32, 1>, memref<2x1xf32>
-// CHECK-NEXT:    %{{.*}} = affine.apply [[MAP_MINUS_1]](%{{.*}})
-// CHECK-NEXT:    %{{.*}} = affine.apply [[MOD_2]](%{{.*}})
-// CHECK-NEXT:    %{{.*}} = affine.apply [[MOD_2]](%{{.*}})
+// CHECK-NEXT:    affine.apply [[MAP_MINUS_1]](%{{.*}})
+// CHECK-NEXT:    affine.apply [[MOD_2]](%{{.*}})
+// CHECK-NEXT:    affine.apply [[MOD_2]](%{{.*}})
 // CHECK-NEXT:    affine.dma_wait %{{.*}}[%{{.*}} mod 2, 0], %{{.*}} : memref<2x1xf32>
-// CHECK-NEXT:    %{{.*}} = affine.load %{{.*}}[%{{.*}} mod 2, %{{.*}}] : memref<2x32xf32, 1>
-// CHECK-NEXT:    %{{.*}} = "compute"(%{{.*}}) : (f32) -> f32
+// CHECK-NEXT:    affine.load %{{.*}}[%{{.*}} mod 2, %{{.*}}] : memref<2x32xf32, 1>
+// CHECK-NEXT:    "compute"(%{{.*}}) : (f32) -> f32
 // CHECK-NEXT:    affine.store %{{.*}}, %{{.*}}[%{{.*}} mod 2, %{{.*}}] : memref<2x32xf32, 1>
 // CHECK-NEXT:    affine.for %{{.*}} = 0 to 32 {
 // CHECK-NEXT:      "do_more_compute"(%{{.*}}, %{{.*}}) : (index, index) -> ()
 // CHECK-NEXT:    }
 // CHECK-NEXT:  }
-// CHECK-NEXT:  %{{.*}} = affine.apply [[MAP_MINUS_1]](%{{.*}})
-// CHECK-NEXT:  %{{.*}} = affine.apply [[MOD_2]](%{{.*}})
-// CHECK-NEXT:  %{{.*}} = affine.apply [[MOD_2]](%{{.*}})
+// CHECK-NEXT:  affine.apply [[MAP_MINUS_1]](%{{.*}})
+// CHECK-NEXT:  affine.apply [[MOD_2]](%{{.*}})
+// CHECK-NEXT:  affine.apply [[MOD_2]](%{{.*}})
 // CHECK-NEXT:  affine.dma_wait %{{.*}}[%{{.*}} mod 2, 0], %{{.*}} : memref<2x1xf32>
-// CHECK-NEXT:  %{{.*}} = affine.load %{{.*}}[%{{.*}} mod 2, %{{.*}}] : memref<2x32xf32, 1>
-// CHECK-NEXT:  %{{.*}} = "compute"(%{{.*}}) : (f32) -> f32
+// CHECK-NEXT:  affine.load %{{.*}}[%{{.*}} mod 2, %{{.*}}] : memref<2x32xf32, 1>
+// CHECK-NEXT:  "compute"(%{{.*}}) : (f32) -> f32
 // CHECK-NEXT:  affine.store %{{.*}}, %{{.*}}[%{{.*}} mod 2, %{{.*}}] : memref<2x32xf32, 1>
 // CHECK-NEXT:  affine.for %{{.*}} = 0 to 32 {
 // CHECK-NEXT:    "do_more_compute"(%{{.*}}, %{{.*}}) : (index, index) -> ()
@@ -89,8 +89,8 @@ func @loop_step(%arg0: memref<512xf32>,
 // CHECK-NEXT:   affine.dma_start %{{.*}}[%{{.*}}], %{{.*}}[(%{{.*}} floordiv 4) mod 2, 0], [[TAG]][(%{{.*}} floordiv 4) mod 2, 0], %{{.*}} : memref<512xf32>, memref<2x4xf32, 1>, memref<2x1xi32>
 // CHECK-NEXT:   affine.for %{{.*}} = 4 to 512 step 4 {
 // CHECK-NEXT:     affine.dma_start %{{.*}}[%{{.*}}], %{{.*}}[(%{{.*}} floordiv 4) mod 2, 0], [[TAG]][(%{{.*}} floordiv 4) mod 2, 0], %{{.*}} : memref<512xf32>, memref<2x4xf32, 1>, memref<2x1xi32>
-// CHECK-NEXT:     %{{.*}} = affine.apply [[REMAP_SHIFT_MINUS_4]](%{{.*}})
-// CHECK-NEXT:     %{{.*}} = affine.apply [[FLOOR_MOD_2]](%{{.*}})
+// CHECK-NEXT:     affine.apply [[REMAP_SHIFT_MINUS_4]](%{{.*}})
+// CHECK-NEXT:     affine.apply [[FLOOR_MOD_2]](%{{.*}})
 // CHECK:          affine.dma_wait [[TAG]][(%{{.*}} floordiv 4) mod 2, 0], %{{.*}} : memref<2x1xi32>
 // CHECK-NEXT:     "compute"(%{{.*}}) : (index) -> ()
 // CHECK-NEXT:   }
@@ -313,7 +313,7 @@ func @live_out_use(%arg0: memref<512 x 32 x f32>) -> f32 {
   dealloc %tag : memref<1 x i32>
   dealloc %Av : memref<32 x 32 x f32, 2>
   return %v : f32
-// CHECK:      %{{[0-9]+}} = affine.load %{{[0-9]+}}[%{{.*}}, %{{.*}}] : memref<32x32xf32, 2>
+// CHECK:      affine.load %{{[0-9]+}}[%{{.*}}, %{{.*}}] : memref<32x32xf32, 2>
 // CHECK:      return
 }
 
@@ -329,10 +329,10 @@ func @dynamic_shape_dma_buffer(%arg0: memref<512 x 32 x f32>) {
   %tag = alloc() : memref<1 x i32>
 
 // Double buffering for dynamic shaped buffer.
-// CHECK:       %{{.*}} = alloc(%{{.*}}, %{{.*}}) : memref<?x?xf32, 2>
-// CHECK-NEXT:  %{{.*}} = dim %{{.*}}, 0 : memref<?x?xf32, 2>
-// CHECK-NEXT:  %{{.*}} = dim %{{.*}}, 1 : memref<?x?xf32, 2>
-// CHECK-NEXT:  %{{.*}} = alloc(%{{.*}}, %{{.*}}) : memref<2x?x?xf32, 2>
+// CHECK:       alloc(%{{.*}}, %{{.*}}) : memref<?x?xf32, 2>
+// CHECK-NEXT:  dim %{{.*}}, 0 : memref<?x?xf32, 2>
+// CHECK-NEXT:  dim %{{.*}}, 1 : memref<?x?xf32, 2>
+// CHECK-NEXT:  alloc(%{{.*}}, %{{.*}}) : memref<2x?x?xf32, 2>
 // CHECK:       affine.dma_start %{{.*}}[%{{.*}}, %{{.*}}], %{{.*}}[%{{.*}} mod 2, 0, 0], %{{.*}}[%{{.*}} mod 2, 0], %{{.*}}
   affine.for %kTT = 0 to 16 {
     affine.dma_start %arg0[%zero, %zero], %Av[%zero, %zero], %tag[%zero], %num_elt :
diff --git a/mlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td b/mlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td
index e75a109376fa8..49a3499b0bada 100644
--- a/mlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td
+++ b/mlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td
@@ -15,8 +15,8 @@
 #define TEST_VECTOR_TRANSFORMS_PATTERNS
 
 include "mlir/Dialect/StandardOps/IR/Ops.td"
-include "mlir/Dialect/VectorOps/VectorOps.td"
-include "mlir/Dialect/VectorOps/VectorTransformPatterns.td"
+include "mlir/Dialect/Vector/VectorOps.td"
+include "mlir/Dialect/Vector/VectorTransformPatterns.td"
 
 def : Pat<(AddFOp:$op_results $a, $b),
           (UnrollVectorOp<[2, 2]> $op_results, $a, $b),
diff --git a/mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp b/mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
index 0ebd3d8785fce..a91800d68fc04 100644
--- a/mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
+++ b/mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
@@ -94,32 +94,32 @@ struct ConvertToTargetEnv : public FunctionPass<ConvertToTargetEnv> {
 
 struct ConvertToAtomCmpExchangeWeak : public RewritePattern {
   ConvertToAtomCmpExchangeWeak(MLIRContext *context);
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override;
 };
 
 struct ConvertToBitReverse : public RewritePattern {
   ConvertToBitReverse(MLIRContext *context);
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override;
 };
 
 struct ConvertToGroupNonUniformBallot : public RewritePattern {
   ConvertToGroupNonUniformBallot(MLIRContext *context);
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override;
 };
 
 struct ConvertToModule : public RewritePattern {
   ConvertToModule(MLIRContext *context);
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override;
 };
 
 struct ConvertToSubgroupBallot : public RewritePattern {
   ConvertToSubgroupBallot(MLIRContext *context);
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const override;
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const override;
 };
 } // end anonymous namespace
 
@@ -145,7 +145,7 @@ ConvertToAtomCmpExchangeWeak::ConvertToAtomCmpExchangeWeak(MLIRContext *context)
     : RewritePattern("test.convert_to_atomic_compare_exchange_weak_op",
                      {"spv.AtomicCompareExchangeWeak"}, 1, context) {}
 
-PatternMatchResult
+LogicalResult
 ConvertToAtomCmpExchangeWeak::matchAndRewrite(Operation *op,
                                               PatternRewriter &rewriter) const {
   Value ptr = op->getOperand(0);
@@ -159,21 +159,21 @@ ConvertToAtomCmpExchangeWeak::matchAndRewrite(Operation *op,
       spirv::MemorySemantics::AcquireRelease |
           spirv::MemorySemantics::AtomicCounterMemory,
       spirv::MemorySemantics::Acquire, value, comparator);
-  return matchSuccess();
+  return success();
 }
 
 ConvertToBitReverse::ConvertToBitReverse(MLIRContext *context)
     : RewritePattern("test.convert_to_bit_reverse_op", {"spv.BitReverse"}, 1,
                      context) {}
 
-PatternMatchResult
+LogicalResult
 ConvertToBitReverse::matchAndRewrite(Operation *op,
                                      PatternRewriter &rewriter) const {
   Value predicate = op->getOperand(0);
 
   rewriter.replaceOpWithNewOp<spirv::BitReverseOp>(
       op, op->getResult(0).getType(), predicate);
-  return matchSuccess();
+  return success();
 }
 
 ConvertToGroupNonUniformBallot::ConvertToGroupNonUniformBallot(
@@ -181,39 +181,39 @@ ConvertToGroupNonUniformBallot::ConvertToGroupNonUniformBallot(
     : RewritePattern("test.convert_to_group_non_uniform_ballot_op",
                      {"spv.GroupNonUniformBallot"}, 1, context) {}
 
-PatternMatchResult ConvertToGroupNonUniformBallot::matchAndRewrite(
+LogicalResult ConvertToGroupNonUniformBallot::matchAndRewrite(
     Operation *op, PatternRewriter &rewriter) const {
   Value predicate = op->getOperand(0);
 
   rewriter.replaceOpWithNewOp<spirv::GroupNonUniformBallotOp>(
       op, op->getResult(0).getType(), spirv::Scope::Workgroup, predicate);
-  return matchSuccess();
+  return success();
 }
 
 ConvertToModule::ConvertToModule(MLIRContext *context)
     : RewritePattern("test.convert_to_module_op", {"spv.module"}, 1, context) {}
 
-PatternMatchResult
+LogicalResult
 ConvertToModule::matchAndRewrite(Operation *op,
                                  PatternRewriter &rewriter) const {
   rewriter.replaceOpWithNewOp<spirv::ModuleOp>(
       op, spirv::AddressingModel::PhysicalStorageBuffer64,
       spirv::MemoryModel::Vulkan);
-  return matchSuccess();
+  return success();
 }
 
 ConvertToSubgroupBallot::ConvertToSubgroupBallot(MLIRContext *context)
     : RewritePattern("test.convert_to_subgroup_ballot_op",
                      {"spv.SubgroupBallotKHR"}, 1, context) {}
 
-PatternMatchResult
+LogicalResult
 ConvertToSubgroupBallot::matchAndRewrite(Operation *op,
                                          PatternRewriter &rewriter) const {
   Value predicate = op->getOperand(0);
 
   rewriter.replaceOpWithNewOp<spirv::SubgroupBallotKHROp>(
       op, op->getResult(0).getType(), predicate);
-  return matchSuccess();
+  return success();
 }
 
 namespace mlir {
diff --git a/mlir/test/lib/TestDialect/CMakeLists.txt b/mlir/test/lib/TestDialect/CMakeLists.txt
index 6424d5ab23e1f..d625a58190965 100644
--- a/mlir/test/lib/TestDialect/CMakeLists.txt
+++ b/mlir/test/lib/TestDialect/CMakeLists.txt
@@ -6,6 +6,7 @@ set(LLVM_OPTIONAL_SOURCES
 set(LLVM_TARGET_DEFINITIONS TestOps.td)
 mlir_tablegen(TestOps.h.inc -gen-op-decls)
 mlir_tablegen(TestOps.cpp.inc -gen-op-defs)
+mlir_tablegen(TestOpsDialect.h.inc -gen-dialect-decls)
 mlir_tablegen(TestOpEnums.h.inc -gen-enum-decls)
 mlir_tablegen(TestOpEnums.cpp.inc -gen-enum-defs)
 mlir_tablegen(TestPatterns.inc -gen-rewriters)
diff --git a/mlir/test/lib/TestDialect/TestDialect.cpp b/mlir/test/lib/TestDialect/TestDialect.cpp
index 94b5017978a09..166edf8202061 100644
--- a/mlir/test/lib/TestDialect/TestDialect.cpp
+++ b/mlir/test/lib/TestDialect/TestDialect.cpp
@@ -128,7 +128,7 @@ struct TestInlinerInterface : public DialectInlinerInterface {
 //===----------------------------------------------------------------------===//
 
 TestDialect::TestDialect(MLIRContext *context)
-    : Dialect(getDialectName(), context) {
+    : Dialect(getDialectNamespace(), context) {
   addOperations<
 #define GET_OP_LIST
 #include "TestOps.cpp.inc"
@@ -283,10 +283,10 @@ struct TestRemoveOpWithInnerOps
     : public OpRewritePattern<TestOpWithRegionPattern> {
   using OpRewritePattern<TestOpWithRegionPattern>::OpRewritePattern;
 
-  PatternMatchResult matchAndRewrite(TestOpWithRegionPattern op,
-                                     PatternRewriter &rewriter) const override {
+  LogicalResult matchAndRewrite(TestOpWithRegionPattern op,
+                                PatternRewriter &rewriter) const override {
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 } // end anonymous namespace
diff --git a/mlir/test/lib/TestDialect/TestDialect.h b/mlir/test/lib/TestDialect/TestDialect.h
index f751918bb1b3a..9b4dfee2daaa3 100644
--- a/mlir/test/lib/TestDialect/TestDialect.h
+++ b/mlir/test/lib/TestDialect/TestDialect.h
@@ -29,23 +29,7 @@
 
 namespace mlir {
 
-class TestDialect : public Dialect {
-public:
-  /// Create the dialect in the given `context`.
-  TestDialect(MLIRContext *context);
-
-  /// Get the canonical string name of the dialect.
-  static StringRef getDialectName() { return "test"; }
-
-  LogicalResult verifyOperationAttribute(Operation *op,
-                                         NamedAttribute namedAttr) override;
-  LogicalResult verifyRegionArgAttribute(Operation *op, unsigned regionIndex,
-                                         unsigned argIndex,
-                                         NamedAttribute namedAttr) override;
-  LogicalResult verifyRegionResultAttribute(Operation *op, unsigned regionIndex,
-                                            unsigned resultIndex,
-                                            NamedAttribute namedAttr) override;
-};
+#include "TestOpsDialect.h.inc"
 
 #define GET_OP_CLASSES
 #include "TestOps.h.inc"
diff --git a/mlir/test/lib/TestDialect/TestOps.td b/mlir/test/lib/TestDialect/TestOps.td
index d9710ba03961b..cf0ec63fe6c59 100644
--- a/mlir/test/lib/TestDialect/TestOps.td
+++ b/mlir/test/lib/TestDialect/TestOps.td
@@ -17,13 +17,16 @@ include "mlir/Interfaces/ControlFlowInterfaces.td"
 include "mlir/Interfaces/InferTypeOpInterface.td"
 include "mlir/Interfaces/SideEffects.td"
 
-def TEST_Dialect : Dialect {
+def Test_Dialect : Dialect {
   let name = "test";
   let cppNamespace = "";
+  let hasOperationAttrVerify = 1;
+  let hasRegionArgAttrVerify = 1;
+  let hasRegionResultAttrVerify = 1;
 }
 
 class TEST_Op<string mnemonic, list<OpTrait> traits = []> :
-    Op<TEST_Dialect, mnemonic, traits>;
+    Op<Test_Dialect, mnemonic, traits>;
 
 //===----------------------------------------------------------------------===//
 // Test Types
diff --git a/mlir/test/lib/TestDialect/TestPatterns.cpp b/mlir/test/lib/TestDialect/TestPatterns.cpp
index 3760ed7dae90a..c7235b8cb3a54 100644
--- a/mlir/test/lib/TestDialect/TestPatterns.cpp
+++ b/mlir/test/lib/TestDialect/TestPatterns.cpp
@@ -141,7 +141,7 @@ struct TestRegionRewriteBlockMovement : public ConversionPattern {
   TestRegionRewriteBlockMovement(MLIRContext *ctx)
       : ConversionPattern("test.region", 1, ctx) {}
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     // Inline this region into the parent region.
@@ -155,7 +155,7 @@ struct TestRegionRewriteBlockMovement : public ConversionPattern {
 
     // Drop this operation.
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 /// This pattern is a simple pattern that generates a region containing an
@@ -164,8 +164,8 @@ struct TestRegionRewriteUndo : public RewritePattern {
   TestRegionRewriteUndo(MLIRContext *ctx)
       : RewritePattern("test.region_builder", 1, ctx) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const final {
     // Create the region operation with an entry block containing arguments.
     OperationState newRegion(op->getLoc(), "test.region");
     newRegion.addRegion();
@@ -179,7 +179,7 @@ struct TestRegionRewriteUndo : public RewritePattern {
 
     // Drop this operation.
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -191,7 +191,7 @@ struct TestDropOpSignatureConversion : public ConversionPattern {
   TestDropOpSignatureConversion(MLIRContext *ctx, TypeConverter &converter)
       : ConversionPattern("test.drop_region_op", 1, ctx), converter(converter) {
   }
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     Region &region = op->getRegion(0);
@@ -202,12 +202,12 @@ struct TestDropOpSignatureConversion : public ConversionPattern {
     for (unsigned i = 0, e = entry->getNumArguments(); i != e; ++i)
       if (failed(converter.convertSignatureArg(
               i, entry->getArgument(i).getType(), result)))
-        return matchFailure();
+        return failure();
 
     // Convert the region signature and just drop the operation.
     rewriter.applySignatureConversion(&region, result);
     rewriter.eraseOp(op);
-    return matchSuccess();
+    return success();
   }
 
   /// The type converter to use when rewriting the signature.
@@ -217,35 +217,35 @@ struct TestDropOpSignatureConversion : public ConversionPattern {
 struct TestPassthroughInvalidOp : public ConversionPattern {
   TestPassthroughInvalidOp(MLIRContext *ctx)
       : ConversionPattern("test.invalid", 1, ctx) {}
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     rewriter.replaceOpWithNewOp<TestValidOp>(op, llvm::None, operands,
                                              llvm::None);
-    return matchSuccess();
+    return success();
   }
 };
 /// This pattern handles the case of a split return value.
 struct TestSplitReturnType : public ConversionPattern {
   TestSplitReturnType(MLIRContext *ctx)
       : ConversionPattern("test.return", 1, ctx) {}
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     // Check for a return of F32.
     if (op->getNumOperands() != 1 || !op->getOperand(0).getType().isF32())
-      return matchFailure();
+      return failure();
 
     // Check if the first operation is a cast operation, if it is we use the
     // results directly.
     auto *defOp = operands[0].getDefiningOp();
     if (auto packerOp = llvm::dyn_cast_or_null<TestCastOp>(defOp)) {
       rewriter.replaceOpWithNewOp<TestReturnOp>(op, packerOp.getOperands());
-      return matchSuccess();
+      return success();
     }
 
     // Otherwise, fail to match.
-    return matchFailure();
+    return failure();
   }
 };
 
@@ -254,52 +254,52 @@ struct TestSplitReturnType : public ConversionPattern {
 struct TestChangeProducerTypeI32ToF32 : public ConversionPattern {
   TestChangeProducerTypeI32ToF32(MLIRContext *ctx)
       : ConversionPattern("test.type_producer", 1, ctx) {}
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     // If the type is I32, change the type to F32.
     if (!Type(*op->result_type_begin()).isSignlessInteger(32))
-      return matchFailure();
+      return failure();
     rewriter.replaceOpWithNewOp<TestTypeProducerOp>(op, rewriter.getF32Type());
-    return matchSuccess();
+    return success();
   }
 };
 struct TestChangeProducerTypeF32ToF64 : public ConversionPattern {
   TestChangeProducerTypeF32ToF64(MLIRContext *ctx)
       : ConversionPattern("test.type_producer", 1, ctx) {}
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     // If the type is F32, change the type to F64.
     if (!Type(*op->result_type_begin()).isF32())
-      return matchFailure();
+      return rewriter.notifyMatchFailure(op, "expected single f32 operand");
     rewriter.replaceOpWithNewOp<TestTypeProducerOp>(op, rewriter.getF64Type());
-    return matchSuccess();
+    return success();
   }
 };
 struct TestChangeProducerTypeF32ToInvalid : public ConversionPattern {
   TestChangeProducerTypeF32ToInvalid(MLIRContext *ctx)
       : ConversionPattern("test.type_producer", 10, ctx) {}
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     // Always convert to B16, even though it is not a legal type. This tests
     // that values are unmapped correctly.
     rewriter.replaceOpWithNewOp<TestTypeProducerOp>(op, rewriter.getBF16Type());
-    return matchSuccess();
+    return success();
   }
 };
 struct TestUpdateConsumerType : public ConversionPattern {
   TestUpdateConsumerType(MLIRContext *ctx)
       : ConversionPattern("test.type_consumer", 1, ctx) {}
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const final {
     // Verify that the incoming operand has been successfully remapped to F64.
     if (!operands[0].getType().isF64())
-      return matchFailure();
+      return failure();
     rewriter.replaceOpWithNewOp<TestTypeConsumerOp>(op, operands[0]);
-    return matchSuccess();
+    return success();
   }
 };
 
@@ -312,15 +312,15 @@ struct TestNonRootReplacement : public RewritePattern {
   TestNonRootReplacement(MLIRContext *ctx)
       : RewritePattern("test.replace_non_root", 1, ctx) {}
 
-  PatternMatchResult matchAndRewrite(Operation *op,
-                                     PatternRewriter &rewriter) const final {
+  LogicalResult matchAndRewrite(Operation *op,
+                                PatternRewriter &rewriter) const final {
     auto resultType = *op->result_type_begin();
     auto illegalOp = rewriter.create<ILLegalOpF>(op->getLoc(), resultType);
     auto legalOp = rewriter.create<LegalOpB>(op->getLoc(), resultType);
 
     rewriter.replaceOp(illegalOp, {legalOp});
     rewriter.replaceOp(op, {illegalOp});
-    return matchSuccess();
+    return success();
   }
 };
 } // namespace
@@ -475,7 +475,7 @@ struct OneVResOneVOperandOp1Converter
     : public OpConversionPattern<OneVResOneVOperandOp1> {
   using OpConversionPattern<OneVResOneVOperandOp1>::OpConversionPattern;
 
-  PatternMatchResult
+  LogicalResult
   matchAndRewrite(OneVResOneVOperandOp1 op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     auto origOps = op.getOperands();
@@ -490,7 +490,7 @@ struct OneVResOneVOperandOp1Converter
 
     rewriter.replaceOpWithNewOp<OneVResOneVOperandOp1>(op, op.getResultTypes(),
                                                        remappedOperands);
-    return matchSuccess();
+    return success();
   }
 };
 
diff --git a/mlir/test/lib/Transforms/CMakeLists.txt b/mlir/test/lib/Transforms/CMakeLists.txt
index e98623c7f1ba6..bc737a0a119fb 100644
--- a/mlir/test/lib/Transforms/CMakeLists.txt
+++ b/mlir/test/lib/Transforms/CMakeLists.txt
@@ -48,5 +48,5 @@ target_link_libraries(MLIRTestTransforms
   MLIRTestDialect
   MLIRTransformUtils
   MLIRVectorToLoops
-  MLIRVectorOps
+  MLIRVector
   )
diff --git a/mlir/test/lib/Transforms/TestVectorTransforms.cpp b/mlir/test/lib/Transforms/TestVectorTransforms.cpp
index aa3d960ce0900..8f2f64e5f60a5 100644
--- a/mlir/test/lib/Transforms/TestVectorTransforms.cpp
+++ b/mlir/test/lib/Transforms/TestVectorTransforms.cpp
@@ -9,14 +9,13 @@
 #include <type_traits>
 
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
-#include "mlir/Dialect/VectorOps/VectorOps.h"
-#include "mlir/Dialect/VectorOps/VectorTransforms.h"
+#include "mlir/Dialect/Vector/VectorOps.h"
+#include "mlir/Dialect/Vector/VectorTransforms.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/Pass/Pass.h"
 
 using namespace mlir;
 using namespace mlir::vector;
-
 namespace {
 
 #include "TestVectorTransformPatterns.h.inc"
@@ -44,9 +43,20 @@ struct TestVectorSlicesConversion
 
 struct TestVectorContractionConversion
     : public FunctionPass<TestVectorContractionConversion> {
+  TestVectorContractionConversion() = default;
+  TestVectorContractionConversion(const TestVectorContractionConversion &pass) {
+  }
+
+  Option<bool> lowerToLLVMMatrixIntrinsics{
+      *this, "vector-lower-matrix-intrinsics",
+      llvm::cl::desc("Lower vector.contract to llvm.intr.matrix.multiply"),
+      llvm::cl::init(false)};
+
   void runOnFunction() override {
     OwningRewritePatternList patterns;
-    populateVectorContractLoweringPatterns(patterns, &getContext());
+    VectorTransformsOptions options{
+        /*lowerToLLVMMatrixIntrinsics=*/lowerToLLVMMatrixIntrinsics};
+    populateVectorContractLoweringPatterns(patterns, &getContext(), options);
     applyPatternsGreedily(getFunction(), patterns);
   }
 };
diff --git a/mlir/test/lib/Transforms/TestVectorizationUtils.cpp b/mlir/test/lib/Transforms/TestVectorizationUtils.cpp
index 50086e5c333a7..4ae4509bc56d2 100644
--- a/mlir/test/lib/Transforms/TestVectorizationUtils.cpp
+++ b/mlir/test/lib/Transforms/TestVectorizationUtils.cpp
@@ -14,7 +14,7 @@
 #include "mlir/Analysis/NestedMatcher.h"
 #include "mlir/Analysis/SliceAnalysis.h"
 #include "mlir/Dialect/AffineOps/AffineOps.h"
-#include "mlir/Dialect/VectorOps/VectorUtils.h"
+#include "mlir/Dialect/Vector/VectorUtils.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/Diagnostics.h"
 #include "mlir/IR/StandardTypes.h"
diff --git a/mlir/tools/mlir-tblgen/DialectGen.cpp b/mlir/tools/mlir-tblgen/DialectGen.cpp
index c0009d6e1231b..a662f6273b9dd 100644
--- a/mlir/tools/mlir-tblgen/DialectGen.cpp
+++ b/mlir/tools/mlir-tblgen/DialectGen.cpp
@@ -36,14 +36,23 @@ static llvm::cl::opt<std::string>
     selectedDialect("dialect", llvm::cl::desc("The dialect to gen for"),
                     llvm::cl::cat(dialectGenCat), llvm::cl::CommaSeparated);
 
+/// Utility iterator used for filtering records for a specific dialect.
+namespace {
+using DialectFilterIterator =
+    llvm::filter_iterator<ArrayRef<llvm::Record *>::iterator,
+                          std::function<bool(const llvm::Record *)>>;
+} // end anonymous namespace
+
 /// Given a set of records for a T, filter the ones that correspond to
 /// the given dialect.
 template <typename T>
-static auto filterForDialect(ArrayRef<llvm::Record *> records,
-                             Dialect &dialect) {
-  return llvm::make_filter_range(records, [&](const llvm::Record *record) {
+static iterator_range<DialectFilterIterator>
+filterForDialect(ArrayRef<llvm::Record *> records, Dialect &dialect) {
+  auto filterFn = [&](const llvm::Record *record) {
     return T(record).getDialect() == dialect;
-  });
+  };
+  return {DialectFilterIterator(records.begin(), records.end(), filterFn),
+          DialectFilterIterator(records.end(), records.end(), filterFn)};
 }
 
 //===----------------------------------------------------------------------===//
@@ -92,13 +101,37 @@ static const char *const constantMaterializerDecl = R"(
                                          ::mlir::Location loc) override;
 )";
 
+/// The code block for the operation attribute verifier hook.
+static const char *const opAttrVerifierDecl = R"(
+    /// Provides a hook for verifying dialect attributes attached to the given
+    /// op.
+    ::mlir::LogicalResult verifyOperationAttribute(
+        ::mlir::Operation *op, ::mlir::NamedAttribute attribute) override;
+)";
+
+/// The code block for the region argument attribute verifier hook.
+static const char *const regionArgAttrVerifierDecl = R"(
+    /// Provides a hook for verifying dialect attributes attached to the given
+    /// op's region argument.
+    ::mlir::LogicalResult verifyRegionArgAttribute(
+        ::mlir::Operation *op, unsigned regionIndex, unsigned argIndex,
+        ::mlir::NamedAttribute attribute) override;
+)";
+
+/// The code block for the region result attribute verifier hook.
+static const char *const regionResultAttrVerifierDecl = R"(
+    /// Provides a hook for verifying dialect attributes attached to the given
+    /// op's region result.
+    ::mlir::LogicalResult verifyRegionResultAttribute(
+        ::mlir::Operation *op, unsigned regionIndex, unsigned resultIndex,
+        ::mlir::NamedAttribute attribute) override;
+)";
+
 /// Generate the declaration for the given dialect class.
-static void emitDialectDecl(
-    Dialect &dialect,
-    FunctionTraits<decltype(&filterForDialect<Attribute>)>::result_t
-        dialectAttrs,
-    FunctionTraits<decltype(&filterForDialect<Type>)>::result_t dialectTypes,
-    raw_ostream &os) {
+static void emitDialectDecl(Dialect &dialect,
+                            iterator_range<DialectFilterIterator> dialectAttrs,
+                            iterator_range<DialectFilterIterator> dialectTypes,
+                            raw_ostream &os) {
   // Emit the start of the decl.
   std::string cppName = dialect.getCppClassName();
   os << llvm::formatv(dialectDeclBeginStr, cppName, dialect.getName());
@@ -113,6 +146,12 @@ static void emitDialectDecl(
   // Add the decls for the various features of the dialect.
   if (dialect.hasConstantMaterializer())
     os << constantMaterializerDecl;
+  if (dialect.hasOperationAttrVerify())
+    os << opAttrVerifierDecl;
+  if (dialect.hasRegionArgAttrVerify())
+    os << regionArgAttrVerifierDecl;
+  if (dialect.hasRegionResultAttrVerify())
+    os << regionResultAttrVerifierDecl;
   if (llvm::Optional<StringRef> extraDecl = dialect.getExtraClassDeclaration())
     os << *extraDecl;
 
diff --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp
index fa57219fe005c..a42c7390bb755 100644
--- a/mlir/tools/mlir-tblgen/RewriterGen.cpp
+++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp
@@ -83,6 +83,11 @@ class PatternEmitter {
   // DAG `tree` as an attribute.
   void emitAttributeMatch(DagNode tree, int argIndex, int depth, int indent);
 
+  // Emits C++ for checking a match with a corresponding match failure
+  // diagnostic.
+  void emitMatchCheck(int depth, const FmtObjectBase &matchFmt,
+                      const llvm::formatv_object_base &failureFmt);
+
   //===--------------------------------------------------------------------===//
   // Rewrite utilities
   //===--------------------------------------------------------------------===//
@@ -215,7 +220,7 @@ void PatternEmitter::emitOpMatch(DagNode tree, int depth) {
   // Skip the operand matching at depth 0 as the pattern rewriter already does.
   if (depth != 0) {
     // Skip if there is no defining operation (e.g., arguments to function).
-    os.indent(indent) << formatv("if (!castedOp{0}) return matchFailure();\n",
+    os.indent(indent) << formatv("if (!castedOp{0}) return failure();\n",
                                  depth);
   }
   if (tree.getNumArgs() != op.getNumArgs()) {
@@ -287,7 +292,8 @@ void PatternEmitter::emitOperandMatch(DagNode tree, int argIndex, int depth,
 
     // Only need to verify if the matcher's type is different from the one
     // of op definition.
-    if (operand->constraint != matcher.getAsConstraint()) {
+    Constraint constraint = matcher.getAsConstraint();
+    if (operand->constraint != constraint) {
       if (operand->isVariadic()) {
         auto error = formatv(
             "further constrain op {0}'s variadic operand #{1} unsupported now",
@@ -297,10 +303,13 @@ void PatternEmitter::emitOperandMatch(DagNode tree, int argIndex, int depth,
       auto self =
           formatv("(*castedOp{0}.getODSOperands({1}).begin()).getType()", depth,
                   argIndex);
-      os.indent(indent) << "if (!("
-                        << std::string(tgfmt(matcher.getConditionTemplate(),
-                                             &fmtCtx.withSelf(self)))
-                        << ")) return matchFailure();\n";
+      emitMatchCheck(
+          depth,
+          tgfmt(constraint.getConditionTemplate(), &fmtCtx.withSelf(self)),
+          formatv("\"operand {0} of op '{1}' failed to satisfy constraint: "
+                  "'{2}'\"",
+                  operand - op.operand_begin(), op.getOperationName(),
+                  constraint.getDescription()));
     }
   }
 
@@ -321,7 +330,6 @@ void PatternEmitter::emitOperandMatch(DagNode tree, int argIndex, int depth,
 
 void PatternEmitter::emitAttributeMatch(DagNode tree, int argIndex, int depth,
                                         int indent) {
-
   Operator &op = tree.getDialectOp(opMap);
   auto *namedAttr = op.getArg(argIndex).get<NamedAttribute *>();
   const auto &attr = namedAttr->attr;
@@ -344,7 +352,11 @@ void PatternEmitter::emitAttributeMatch(DagNode tree, int argIndex, int depth,
     // should just capture a mlir::Attribute() to signal the missing state.
     // That is precisely what getAttr() returns on missing attributes.
   } else {
-    os.indent(indent) << "if (!tblgen_attr) return matchFailure();\n";
+    emitMatchCheck(depth, tgfmt("tblgen_attr", &fmtCtx),
+                   formatv("\"expected op '{0}' to have attribute '{1}' "
+                           "of type '{2}'\"",
+                           op.getOperationName(), namedAttr->name,
+                           attr.getStorageType()));
   }
 
   auto matcher = tree.getArgAsLeaf(argIndex);
@@ -357,10 +369,13 @@ void PatternEmitter::emitAttributeMatch(DagNode tree, int argIndex, int depth,
 
     // If a constraint is specified, we need to generate C++ statements to
     // check the constraint.
-    os.indent(indent) << "if (!("
-                      << std::string(tgfmt(matcher.getConditionTemplate(),
-                                           &fmtCtx.withSelf("tblgen_attr")))
-                      << ")) return matchFailure();\n";
+    emitMatchCheck(
+        depth,
+        tgfmt(matcher.getConditionTemplate(), &fmtCtx.withSelf("tblgen_attr")),
+        formatv("\"op '{0}' attribute '{1}' failed to satisfy constraint: "
+                "{2}\"",
+                op.getOperationName(), namedAttr->name,
+                matcher.getAsConstraint().getDescription()));
   }
 
   // Capture the value
@@ -374,22 +389,40 @@ void PatternEmitter::emitAttributeMatch(DagNode tree, int argIndex, int depth,
   os.indent(indent) << "}\n";
 }
 
+void PatternEmitter::emitMatchCheck(
+    int depth, const FmtObjectBase &matchFmt,
+    const llvm::formatv_object_base &failureFmt) {
+  // {0} The match depth (used to get the operation that failed to match).
+  // {1} The format for the match string.
+  // {2} The format for the failure string.
+  const char *matchStr = R"(
+    if (!({1})) {
+      return rewriter.notifyMatchFailure(op{0}, [&](::mlir::Diagnostic &diag) {
+        diag << {2};
+      });
+    })";
+  os << llvm::formatv(matchStr, depth, matchFmt.str(), failureFmt.str())
+     << "\n";
+}
+
 void PatternEmitter::emitMatchLogic(DagNode tree) {
   LLVM_DEBUG(llvm::dbgs() << "--- start emitting match logic ---\n");
-  emitOpMatch(tree, 0);
+  int depth = 0;
+  emitOpMatch(tree, depth);
 
   for (auto &appliedConstraint : pattern.getConstraints()) {
     auto &constraint = appliedConstraint.constraint;
     auto &entities = appliedConstraint.entities;
 
     auto condition = constraint.getConditionTemplate();
-    auto cmd = "if (!({0})) return matchFailure();\n";
-
     if (isa<TypeConstraint>(constraint)) {
       auto self = formatv("({0}.getType())",
                           symbolInfoMap.getValueAndRangeUse(entities.front()));
-      os.indent(4) << formatv(cmd,
-                              tgfmt(condition, &fmtCtx.withSelf(self.str())));
+      emitMatchCheck(
+          depth, tgfmt(condition, &fmtCtx.withSelf(self.str())),
+          formatv("\"value entity '{0}' failed to satisfy constraint: {1}\"",
+                  entities.front(), constraint.getDescription()));
+
     } else if (isa<AttrConstraint>(constraint)) {
       PrintFatalError(
           loc, "cannot use AttrConstraint in Pattern multi-entity constraints");
@@ -408,9 +441,13 @@ void PatternEmitter::emitMatchLogic(DagNode tree) {
         self = symbolInfoMap.getValueAndRangeUse(self);
       for (; i < 4; ++i)
         names.push_back("<unused>");
-      os.indent(4) << formatv(cmd,
-                              tgfmt(condition, &fmtCtx.withSelf(self), names[0],
-                                    names[1], names[2], names[3]));
+      emitMatchCheck(depth,
+                     tgfmt(condition, &fmtCtx.withSelf(self), names[0],
+                           names[1], names[2], names[3]),
+                     formatv("\"entities '{0}' failed to satisfy constraint: "
+                             "{1}\"",
+                             llvm::join(entities, ", "),
+                             constraint.getDescription()));
     }
   }
   LLVM_DEBUG(llvm::dbgs() << "--- done emitting match logic ---\n");
@@ -468,7 +505,7 @@ void PatternEmitter::emit(StringRef rewriteName) {
 
   // Emit matchAndRewrite() function.
   os << R"(
-  PatternMatchResult matchAndRewrite(Operation *op0,
+  LogicalResult matchAndRewrite(Operation *op0,
                                      PatternRewriter &rewriter) const override {
 )";
 
@@ -501,7 +538,7 @@ void PatternEmitter::emit(StringRef rewriteName) {
   os.indent(4) << "// Rewrite\n";
   emitRewriteLogic();
 
-  os.indent(4) << "return matchSuccess();\n";
+  os.indent(4) << "return success();\n";
   os << "  };\n";
   os << "};\n";
 }
diff --git a/mlir/tools/mlir-vulkan-runner/VulkanRuntime.h b/mlir/tools/mlir-vulkan-runner/VulkanRuntime.h
index 91f234007f74b..9c63714306b97 100644
--- a/mlir/tools/mlir-vulkan-runner/VulkanRuntime.h
+++ b/mlir/tools/mlir-vulkan-runner/VulkanRuntime.h
@@ -22,7 +22,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/Support/ToolOutputFile.h"
 
-#include <vulkan/vulkan.h> // NOLINT
+#include <vulkan/vulkan.h>
 
 using namespace mlir;
 
diff --git a/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp b/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
index f91bc71e8713e..10987f6939cab 100644
--- a/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
+++ b/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
@@ -40,7 +40,9 @@ static LogicalResult runMLIRPasses(ModuleOp module) {
   modulePM.addPass(spirv::createLowerABIAttributesPass());
   modulePM.addPass(spirv::createUpdateVersionCapabilityExtensionPass());
   passManager.addPass(createConvertGpuLaunchFuncToVulkanLaunchFuncPass());
-  passManager.addPass(createLowerToLLVMPass());
+  passManager.addPass(createLowerToLLVMPass(/*useAlloca=*/false,
+                                            /*useBarePtrCallConv=*/false,
+                                            /*emitCWrappers=*/true));
   passManager.addPass(createConvertVulkanLaunchFuncToVulkanCallsPass());
   return passManager.run(module);
 }
diff --git a/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp b/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp
index eb9a682da3000..52c11dad8c7e0 100644
--- a/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp
+++ b/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp
@@ -62,34 +62,28 @@ class VulkanRuntimeManager {
 
 } // namespace
 
+template <typename T, int N>
+struct MemRefDescriptor {
+  T *allocated;
+  T *aligned;
+  int64_t offset;
+  int64_t sizes[N];
+  int64_t strides[N];
+};
+
 extern "C" {
-// Initializes `VulkanRuntimeManager` and returns a pointer to it.
+/// Initializes `VulkanRuntimeManager` and returns a pointer to it.
 void *initVulkan() { return new VulkanRuntimeManager(); }
 
-// Deinitializes `VulkanRuntimeManager` by the given pointer.
+/// Deinitializes `VulkanRuntimeManager` by the given pointer.
 void deinitVulkan(void *vkRuntimeManager) {
   delete reinterpret_cast<VulkanRuntimeManager *>(vkRuntimeManager);
 }
 
-/// Binds the given memref to the given descriptor set and descriptor index.
-void bindResource(void *vkRuntimeManager, DescriptorSetIndex setIndex,
-                  BindingIndex bindIndex, float *ptr, int64_t size) {
-  VulkanHostMemoryBuffer memBuffer{ptr,
-                                   static_cast<uint32_t>(size * sizeof(float))};
-  reinterpret_cast<VulkanRuntimeManager *>(vkRuntimeManager)
-      ->setResourceData(setIndex, bindIndex, memBuffer);
-}
-
 void runOnVulkan(void *vkRuntimeManager) {
   reinterpret_cast<VulkanRuntimeManager *>(vkRuntimeManager)->runOnVulkan();
 }
 
-/// Fills the given 1D float memref with the given float value.
-void fillResource1DFloat(float *allocated, float *aligned, int64_t offset,
-                         int64_t size, int64_t stride, float value) {
-  std::fill_n(allocated, size, value);
-}
-
 void setEntryPoint(void *vkRuntimeManager, const char *entryPoint) {
   reinterpret_cast<VulkanRuntimeManager *>(vkRuntimeManager)
       ->setEntryPoint(entryPoint);
@@ -105,4 +99,21 @@ void setBinaryShader(void *vkRuntimeManager, uint8_t *shader, uint32_t size) {
   reinterpret_cast<VulkanRuntimeManager *>(vkRuntimeManager)
       ->setShaderModule(shader, size);
 }
+
+/// Binds the given 1D float memref to the given descriptor set and descriptor
+/// index.
+void bindMemRef1DFloat(void *vkRuntimeManager, DescriptorSetIndex setIndex,
+                       BindingIndex bindIndex,
+                       MemRefDescriptor<float, 1> *ptr) {
+  VulkanHostMemoryBuffer memBuffer{
+      ptr->allocated, static_cast<uint32_t>(ptr->sizes[0] * sizeof(float))};
+  reinterpret_cast<VulkanRuntimeManager *>(vkRuntimeManager)
+      ->setResourceData(setIndex, bindIndex, memBuffer);
+}
+
+/// Fills the given 1D float memref with the given float value.
+void _mlir_ciface_fillResource1DFloat(MemRefDescriptor<float, 1> *ptr, // NOLINT
+                                      float value) {
+  std::fill_n(ptr->allocated, ptr->sizes[0], value);
+}
 }
diff --git a/mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp b/mlir/unittests/Dialect/Quant/QuantizationUtilsTest.cpp
similarity index 97%
rename from mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp
rename to mlir/unittests/Dialect/Quant/QuantizationUtilsTest.cpp
index e6188ea0de7ed..68e43d45ab427 100644
--- a/mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp
+++ b/mlir/unittests/Dialect/Quant/QuantizationUtilsTest.cpp
@@ -6,9 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/QuantOps/QuantOps.h"
-#include "mlir/Dialect/QuantOps/QuantizeUtils.h"
-#include "mlir/Dialect/QuantOps/UniformSupport.h"
+#include "mlir/Dialect/Quant/QuantOps.h"
+#include "mlir/Dialect/Quant/QuantizeUtils.h"
+#include "mlir/Dialect/Quant/UniformSupport.h"
 #include "mlir/IR/Attributes.h"
 #include "mlir/IR/StandardTypes.h"
 #include "gmock/gmock.h"
diff --git a/pstl/include/pstl/internal/glue_numeric_defs.h b/pstl/include/pstl/internal/glue_numeric_defs.h
index f997b542362ec..86cd38b34b137 100644
--- a/pstl/include/pstl/internal/glue_numeric_defs.h
+++ b/pstl/include/pstl/internal/glue_numeric_defs.h
@@ -60,7 +60,7 @@ exclusive_scan(_ExecutionPolicy&& __exec, _ForwardIterator1 __first, _ForwardIte
                _ForwardIterator2 __result, _Tp __init);
 
 template <class _ExecutionPolicy, class _ForwardIterator1, class _ForwardIterator2, class _Tp, class _BinaryOperation>
-_ForwardIterator2
+__pstl::__internal::__enable_if_execution_policy<_ExecutionPolicy, _ForwardIterator2>
 exclusive_scan(_ExecutionPolicy&& __exec, _ForwardIterator1 __first, _ForwardIterator1 __last,
                _ForwardIterator2 __result, _Tp __init, _BinaryOperation __binary_op);
 
diff --git a/pstl/include/pstl/internal/glue_numeric_impl.h b/pstl/include/pstl/internal/glue_numeric_impl.h
index 18b3371335159..241b8a3bebc71 100644
--- a/pstl/include/pstl/internal/glue_numeric_impl.h
+++ b/pstl/include/pstl/internal/glue_numeric_impl.h
@@ -101,17 +101,25 @@ __pstl::__internal::__enable_if_execution_policy<_ExecutionPolicy, _ForwardItera
 exclusive_scan(_ExecutionPolicy&& __exec, _ForwardIterator1 __first, _ForwardIterator1 __last,
                _ForwardIterator2 __result, _Tp __init)
 {
-    return transform_exclusive_scan(std::forward<_ExecutionPolicy>(__exec), __first, __last, __result, __init,
-                                    std::plus<_Tp>(), __pstl::__internal::__no_op());
+    using namespace __pstl;
+    return __internal::__pattern_transform_scan(
+        std::forward<_ExecutionPolicy>(__exec), __first, __last, __result, __pstl::__internal::__no_op(), __init,
+        std::plus<_Tp>(), /*inclusive=*/std::false_type(),
+        __internal::__is_vectorization_preferred<_ExecutionPolicy, _ForwardIterator1, _ForwardIterator2>(__exec),
+        __internal::__is_parallelization_preferred<_ExecutionPolicy, _ForwardIterator1, _ForwardIterator2>(__exec));
 }
 
 template <class _ExecutionPolicy, class _ForwardIterator1, class _ForwardIterator2, class _Tp, class _BinaryOperation>
-_ForwardIterator2
+__pstl::__internal::__enable_if_execution_policy<_ExecutionPolicy, _ForwardIterator2>
 exclusive_scan(_ExecutionPolicy&& __exec, _ForwardIterator1 __first, _ForwardIterator1 __last,
                _ForwardIterator2 __result, _Tp __init, _BinaryOperation __binary_op)
 {
-    return transform_exclusive_scan(std::forward<_ExecutionPolicy>(__exec), __first, __last, __result, __init,
-                                    __binary_op, __pstl::__internal::__no_op());
+    using namespace __pstl;
+    return __internal::__pattern_transform_scan(
+        std::forward<_ExecutionPolicy>(__exec), __first, __last, __result, __pstl::__internal::__no_op(), __init,
+        __binary_op, /*inclusive=*/std::false_type(),
+        __internal::__is_vectorization_preferred<_ExecutionPolicy, _ForwardIterator1, _ForwardIterator2>(__exec),
+        __internal::__is_parallelization_preferred<_ExecutionPolicy, _ForwardIterator1, _ForwardIterator2>(__exec));
 }
 
 // [inclusive.scan]
diff --git a/pstl/test/std/numerics/numeric.ops/scan.fail.cpp b/pstl/test/std/numerics/numeric.ops/scan.fail.cpp
new file mode 100644
index 0000000000000..13b2c9b751fec
--- /dev/null
+++ b/pstl/test/std/numerics/numeric.ops/scan.fail.cpp
@@ -0,0 +1,38 @@
+// -*- C++ -*-
+//===-- scan.fail.cpp -----------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++98, c++03, c++11, c++14
+
+#include <execution>
+#include <numeric>
+
+struct CustomPolicy
+{
+    constexpr std::false_type
+    __allow_vector()
+    {
+        return std::false_type{};
+    }
+    constexpr std::false_type
+    __allow_parallel()
+    {
+        return std::false_type{};
+    }
+} policy;
+
+int32_t
+main()
+{
+    int *first = nullptr, *last = nullptr, *result = nullptr;
+
+    std::exclusive_scan(policy, first, last, result, 0); // expected-error {{no matching function for call to 'exclusive_scan'}}
+    std::exclusive_scan(policy, first, last, result, 0, std::plus<int>()); // expected-error {{no matching function for call to 'exclusive_scan'}}
+
+    return 0;
+}
diff --git a/sycl/test/basic_tests/buffer/subbuffer.cpp b/sycl/test/basic_tests/buffer/subbuffer.cpp
index ef4fb8da98dfb..6014fa716d400 100644
--- a/sycl/test/basic_tests/buffer/subbuffer.cpp
+++ b/sycl/test/basic_tests/buffer/subbuffer.cpp
@@ -3,7 +3,7 @@
 // RUN: %CPU_RUN_PLACEHOLDER %t.out
 // RUN: %GPU_RUN_PLACEHOLDER %t.out
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
-// XFAIL: cuda,windows
+// XFAIL: cuda
 // TODO: cuda fail due to unimplemented param_name 4121 in cuda_piDeviceGetInfo
 
 //==---------- subbuffer.cpp --- sub-buffer basic test ---------------------==//