Implement StreamingInterfaceINTEL execution mode

In an FPGA design, one may want to control the interface that a kernel
exposes to the rest of the design. This extension adds a new Execution
Mode to indicate that the kernel has a streaming interface, in which
invocation and return is synchronized by a handshaking protocol.

The decision whether to add StreamingInterfaceINTEL execution mode with
0/1 literal is based on the kernel metadata, in case of:
!ip_interface !N
!N = !{!"streaming"}
the translator emits StreamingInterfaceINTEL 0

and

!ip_interface !N
!N = !{!"streaming", !"stall_free_return"}
the translator emits StreamingInterfaceINTEL 1

Spec update:
KhronosGroup/SPIRV-Registry#130

Signed-off-by: Dmitry Sidorov <[email protected]>

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@4d66fe7

Author: MrSidims

llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp

@@ -256,6 +256,34 @@ void PreprocessMetadataBase::visit(Module *M) {
           .add(getMDOperandAsInt(SchedulerTargetFmaxMhzINTEL, 0))
           .done();
     }
+
+    // !{void (i32 addrspace(1)*)* @kernel, i32 ip_interface, i32 interface}
+    if (MDNode *Interface =
+            Kernel.getMetadata(kSPIR2MD::IntelFPGAIPInterface)) {
+      std::set<std::string> InterfaceStrSet;
+      // Default mode is 'csr' aka !ip_interface !N
+      //                           !N = !{!”csr”}
+      // don't emit any particular SPIR-V for it
+      // Streaming mode metadata be like:
+      // Not 'stall free' mode (to be mapped on '0' literal)
+      // !ip_interface !N
+      // !N = !{!"streaming"}
+      // 'stall free' mode (to be mapped on '1' literal)
+      // !ip_interface !N
+      // !N = !{!"streaming", !"stall_free_return"}
+      for (size_t I = 0; I != Interface->getNumOperands(); ++I)
+        InterfaceStrSet.insert(getMDOperandAsString(Interface, I));
+      if (InterfaceStrSet.find("streaming") != InterfaceStrSet.end()) {
+        int32_t InterfaceMode = 0;
+        if (InterfaceStrSet.find("stall_free_return") != InterfaceStrSet.end())
+          InterfaceMode = 1;
+        EM.addOp()
+            .add(&Kernel)
+            .add(spv::internal::ExecutionModeStreamingInterfaceINTEL)
+            .add(InterfaceMode)
+            .done();
+      }
+    }
   }
 }
 

llvm-spirv/lib/SPIRV/SPIRVInternal.h

@@ -428,6 +428,7 @@ const static char PropDSPPref[] = "propagate_dsp_preference";
 const static char InitiationInterval[] = "initiation_interval";
 const static char MaxConcurrency[] = "max_concurrency";
 const static char DisableLoopPipelining[] = "disable_loop_pipelining";
+const static char IntelFPGAIPInterface[] = "ip_interface";
 } // namespace kSPIR2MD
 
 enum Spir2SamplerKind {

llvm-spirv/lib/SPIRV/SPIRVReader.cpp

@@ -3786,6 +3786,27 @@ bool SPIRVToLLVM::transMetadata() {
       F->setMetadata(kSPIR2MD::FmaxMhz,
                      getMDNodeStringIntVec(Context, EM->getLiterals()));
     }
+    // Generate metadata for Intel FPGA streaming interface
+    if (auto *EM = BF->getExecutionMode(
+            internal::ExecutionModeStreamingInterfaceINTEL)) {
+      std::vector<uint32_t> InterfaceVec = EM->getLiterals();
+      assert(InterfaceVec.size() == 1 &&
+             "Expected StreamingInterfaceINTEL to have exactly 1 literal");
+      std::vector<Metadata *> InterfaceMDVec =
+          [&]() -> std::vector<Metadata *> {
+        switch (InterfaceVec[0]) {
+        case 0:
+          return {MDString::get(*Context, "streaming")};
+        case 1:
+          return {MDString::get(*Context, "streaming"),
+                  MDString::get(*Context, "stall_free_return")};
+        default:
+          llvm_unreachable("Invalid streaming interface mode");
+        }
+      }();
+      F->setMetadata(kSPIR2MD::IntelFPGAIPInterface,
+                     MDNode::get(*Context, InterfaceMDVec));
+    }
   }
   NamedMDNode *MemoryModelMD =
       M->getOrInsertNamedMetadata(kSPIRVMD::MemoryModel);

llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

@@ -3855,6 +3855,7 @@ bool LLVMToSPIRVBase::transExecutionMode() {
           N.get(X).get(Y).get(Z);
           BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
               BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
+          BM->addExtension(ExtensionID::SPV_INTEL_kernel_attributes);
           BM->addCapability(CapabilityKernelAttributesINTEL);
         }
       } break;
@@ -3863,6 +3864,7 @@ bool LLVMToSPIRVBase::transExecutionMode() {
                 ExtensionID::SPV_INTEL_kernel_attributes)) {
           BF->addExecutionMode(BM->add(
               new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
+          BM->addExtension(ExtensionID::SPV_INTEL_kernel_attributes);
           BM->addCapability(CapabilityKernelAttributesINTEL);
         }
       } break;
@@ -3876,13 +3878,15 @@ bool LLVMToSPIRVBase::transExecutionMode() {
       } break;
       case spv::ExecutionModeNumSIMDWorkitemsINTEL:
       case spv::ExecutionModeSchedulerTargetFmaxMhzINTEL:
-      case spv::ExecutionModeMaxWorkDimINTEL: {
+      case spv::ExecutionModeMaxWorkDimINTEL:
+      case spv::internal::ExecutionModeStreamingInterfaceINTEL: {
         if (BM->isAllowedToUseExtension(
                 ExtensionID::SPV_INTEL_kernel_attributes)) {
           unsigned X;
           N.get(X);
           BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
               BF, static_cast<ExecutionMode>(EMode), X)));
+          BM->addExtension(ExtensionID::SPV_INTEL_kernel_attributes);
           BM->addCapability(CapabilityFPGAKernelAttributesINTEL);
         }
       } break;

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.cpp

@@ -552,7 +552,7 @@ void SPIRVExecutionMode::encode(spv_ostream &O) const {
 
 void SPIRVExecutionMode::decode(std::istream &I) {
   getDecoder(I) >> Target >> ExecMode;
-  switch (ExecMode) {
+  switch (static_cast<uint32_t>(ExecMode)) {
   case ExecutionModeLocalSize:
   case ExecutionModeLocalSizeHint:
   case ExecutionModeMaxWorkgroupSizeINTEL:
@@ -575,6 +575,7 @@ void SPIRVExecutionMode::decode(std::istream &I) {
   case ExecutionModeMaxWorkDimINTEL:
   case ExecutionModeNumSIMDWorkitemsINTEL:
   case ExecutionModeSchedulerTargetFmaxMhzINTEL:
+  case internal::ExecutionModeStreamingInterfaceINTEL:
     WordLiterals.resize(1);
     break;
   default:

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

@@ -261,6 +261,8 @@ template <> inline void SPIRVMap<SPIRVExecutionModeKind, SPIRVCapVec>::init() {
                {CapabilityVectorComputeINTEL});
   ADD_VEC_INIT(internal::ExecutionModeFastCompositeKernelINTEL,
                {internal::CapabilityFastCompositeINTEL});
+  ADD_VEC_INIT(internal::ExecutionModeStreamingInterfaceINTEL,
+               {CapabilityFPGAKernelAttributesINTEL});
 }
 
 template <> inline void SPIRVMap<SPIRVMemoryModelKind, SPIRVCapVec>::init() {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h

@@ -55,7 +55,7 @@ using namespace spv;
 namespace SPIRV {
 
 inline bool isValid(spv::ExecutionModel V) {
-  switch (V) {
+  switch (static_cast<uint32_t>(V)) {
   case ExecutionModelVertex:
   case ExecutionModelTessellationControl:
   case ExecutionModelTessellationEvaluation:
@@ -71,6 +71,7 @@ inline bool isValid(spv::ExecutionModel V) {
   case ExecutionModelClosestHitKHR:
   case ExecutionModelMissKHR:
   case ExecutionModelCallableKHR:
+  case internal::ExecutionModeStreamingInterfaceINTEL:
     return true;
   default:
     return false;

llvm-spirv/lib/SPIRV/libSPIRV/spirv_internal.hpp

@@ -86,7 +86,10 @@ enum InternalMemoryAccessMask {
   IMemAccessNoAliasINTELMask = 0x20000
 };
 
-enum InternalExecutionMode { IExecModeFastCompositeKernelINTEL = 6088 };
+enum InternalExecutionMode {
+  IExecModeFastCompositeKernelINTEL = 6088,
+  IExecModeStreamingInterfaceINTEL = 6154
+};
 
 enum InternalLoopControlMask { ILoopControlLoopCountINTELMask = 0x1000000 };
 
@@ -168,6 +171,8 @@ constexpr MemoryAccessMask MemoryAccessNoAliasINTELMask =
 
 constexpr ExecutionMode ExecutionModeFastCompositeKernelINTEL =
     static_cast<ExecutionMode>(IExecModeFastCompositeKernelINTEL);
+constexpr ExecutionMode ExecutionModeStreamingInterfaceINTEL =
+    static_cast<ExecutionMode>(IExecModeStreamingInterfaceINTEL);
 
 constexpr LoopControlMask LoopControlLoopCountINTELMask =
     static_cast<LoopControlMask>(ILoopControlLoopCountINTELMask);

llvm-spirv/test/transcoding/IntelFPGAFunctionAttributes.ll renamed to llvm-spirv/test/transcoding/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll

@@ -0,0 +1,45 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_kernel_attributes -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: Capability FPGAKernelAttributesINTEL
+; CHECK-SPIRV: Extension "SPV_INTEL_kernel_attributes"
+; CHECK-SPIRV: EntryPoint [[#]] [[#KERNEL1:]] "test_1"
+; CHECK-SPIRV: EntryPoint [[#]] [[#KERNEL2:]] "test_2"
+; CHECK-SPIRV: ExecutionMode [[#KERNEL1]] 6154 0
+; CHECK-SPIRV: ExecutionMode [[#KERNEL2]] 6154 1
+; CHECK-SPIRV: Function [[#]] [[#KERNEL1]]
+; CHECK-SPIRV: Function [[#]] [[#KERNEL2]]
+
+
+; CHECK-LLVM: define spir_kernel void @test_1{{.*}} !ip_interface ![[#NOSTALLFREE:]]
+; CHECK-LLVM: define spir_kernel void @test_2{{.*}} !ip_interface ![[#STALLFREE:]]
+; CHECK-LLVM: ![[#NOSTALLFREE:]] = !{!"streaming"}
+; CHECK-LLVM: ![[#STALLFREE:]] = !{!"streaming", !"stall_free_return"}
+
+; ModuleID = 'test.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024"
+target triple = "spir64-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @test_1() #0 !ip_interface !0
+{
+entry:
+  ret void
+}
+
+; Function Attrs: nounwind
+define spir_kernel void @test_2() #0 !ip_interface !1
+{
+entry:
+  ret void
+}
+
+attributes #0 = { nounwind }
+
+!0 = !{!"streaming"}
+!1 = !{!"streaming", !"stall_free_return"}