@@ -70,12 +70,12 @@ entry:
7070; CHECK-SPIRV: Label
7171 %i = alloca i32 , align 4
7272 %x = alloca i32 , align 4
73- store i32 0 , i32* %i , align 4
73+ store i32 0 , ptr %i , align 4
7474 br label %for.cond
7575
7676for.cond: ; preds = %for.inc, %entry
7777; CHECK-SPIRV: Label [[#HEADER:]]
78- %0 = load i32 , i32* %i , align 4
78+ %0 = load i32 , ptr %i , align 4
7979 %cmp = icmp slt i32 %0 , 1024
8080; Per SPIRV spec p3.23 "DontUnroll" loop control = 0x2
8181; CHECK-SPIRV: LoopMerge [[#MERGEBLOCK:]] [[#CONTINUE:]] 2
@@ -84,7 +84,7 @@ for.cond: ; preds = %for.inc, %entry
8484
8585for.body: ; preds = %for.cond
8686; CHECK-SPIRV: Label
87- %1 = load i32 , i32* %i , align 4
87+ %1 = load i32 , ptr %i , align 4
8888 %rem = srem i32 %1 , 2
8989 %tobool = icmp ne i32 %rem , 0
9090 br i1 %tobool , label %if.then , label %if.end
@@ -95,15 +95,15 @@ if.then: ; preds = %for.body
9595
9696if.end: ; preds = %for.body
9797; CHECK-SPIRV: Label
98- %2 = load i32 , i32* %i , align 4
99- store i32 %2 , i32* %x , align 4
98+ %2 = load i32 , ptr %i , align 4
99+ store i32 %2 , ptr %x , align 4
100100 br label %for.inc
101101
102102for.inc: ; preds = %if.end, %if.then
103103; CHECK-SPIRV: Label [[#CONTINUE]]
104- %3 = load i32 , i32* %i , align 4
104+ %3 = load i32 , ptr %i , align 4
105105 %inc = add nsw i32 %3 , 1
106- store i32 %inc , i32* %i , align 4
106+ store i32 %inc , ptr %i , align 4
107107 br label %for.cond , !llvm.loop !5
108108; CHECK-LLVM: br label %for.cond, !llvm.loop ![[#UNROLLDISABLE:]]
109109; CHECK-SPIRV: Branch [[#HEADER]]
@@ -120,14 +120,14 @@ entry:
120120; CHECK-SPIRV: Label
121121 %i = alloca i32 , align 4
122122 %x = alloca i32 , align 4
123- store i32 1024 , i32* %i , align 4
123+ store i32 1024 , ptr %i , align 4
124124 br label %while.cond
125125
126126while.cond: ; preds = %if.end, %if.then, %entry
127127; CHECK-SPIRV: Label [[#HEADER:]]
128- %0 = load i32 , i32* %i , align 4
128+ %0 = load i32 , ptr %i , align 4
129129 %dec = add nsw i32 %0 , -1
130- store i32 %dec , i32* %i , align 4
130+ store i32 %dec , ptr %i , align 4
131131 %cmp = icmp sgt i32 %0 , 0
132132; Per SPIRV spec p3.23 "Unroll" loop control = 0x1
133133; CHECK-SPIRV: LoopMerge [[#MERGEBLOCK:]] [[#CONTINUE:]] 256 8
@@ -137,7 +137,7 @@ while.cond: ; preds = %if.end, %if.then, %
137137
138138while.body: ; preds = %while.cond
139139; CHECK-SPIRV: Label
140- %1 = load i32 , i32* %i , align 4
140+ %1 = load i32 , ptr %i , align 4
141141 %rem = srem i32 %1 , 2
142142 %tobool = icmp ne i32 %rem , 0
143143 br i1 %tobool , label %if.then , label %if.end
@@ -154,8 +154,8 @@ if.then: ; preds = %while.body
154154
155155if.end: ; preds = %while.body
156156; CHECK-SPIRV: Label
157- %2 = load i32 , i32* %i , align 4
158- store i32 %2 , i32* %x , align 4
157+ %2 = load i32 , ptr %i , align 4
158+ store i32 %2 , ptr %x , align 4
159159 br label %while.cond , !llvm.loop !7
160160
161161while.end: ; preds = %while.cond
@@ -170,12 +170,12 @@ entry:
170170; CHECK-SPIRV: Label
171171 %i = alloca i32 , align 4
172172 %x = alloca i32 , align 4
173- store i32 1024 , i32* %i , align 4
173+ store i32 1024 , ptr %i , align 4
174174 br label %do.body
175175
176176do.body: ; preds = %do.cond, %entry
177177; CHECK-SPIRV: Label [[#HEADER:]]
178- %0 = load i32 , i32* %i , align 4
178+ %0 = load i32 , ptr %i , align 4
179179 %rem = srem i32 %0 , 2
180180 %tobool = icmp ne i32 %rem , 0
181181; Per SPIRV spec p3.23 "Unroll" loop control = 0x1
@@ -189,15 +189,15 @@ if.then: ; preds = %do.body
189189
190190if.end: ; preds = %do.body
191191; CHECK-SPIRV: Label
192- %1 = load i32 , i32* %i , align 4
193- store i32 %1 , i32* %x , align 4
192+ %1 = load i32 , ptr %i , align 4
193+ store i32 %1 , ptr %x , align 4
194194 br label %do.cond
195195
196196do.cond: ; preds = %if.end, %if.then
197197; CHECK-SPIRV: Label [[#CONTINUE]]
198- %2 = load i32 , i32* %i , align 4
198+ %2 = load i32 , ptr %i , align 4
199199 %dec = add nsw i32 %2 , -1
200- store i32 %dec , i32* %i , align 4
200+ store i32 %dec , ptr %i , align 4
201201 %cmp = icmp sgt i32 %2 , 0
202202; CHECK-SPIRV: BranchConditional [[#]] [[#HEADER]] [[#MERGEBLOCK]]
203203; CHECK-LLVM: br i1 %cmp, label %do.body, label %do.end, !llvm.loop ![[#UNROLLENABLE1:]]
@@ -215,12 +215,12 @@ entry:
215215; CHECK-SPIRV: Label
216216 %i = alloca i32 , align 4
217217 %x = alloca i32 , align 4
218- store i32 1024 , i32* %i , align 4
218+ store i32 1024 , ptr %i , align 4
219219 br label %for.body
220220
221221for.body: ; preds = %for.cond, %entry
222222; CHECK-SPIRV: Label [[#HEADER:]]
223- %0 = load i32 , i32* %i , align 4
223+ %0 = load i32 , ptr %i , align 4
224224 %rem = srem i32 %0 , 2
225225 %tobool = icmp ne i32 %rem , 0
226226; Per SPIRV spec p3.23 "Unroll" loop control = 0x1
@@ -234,15 +234,15 @@ if.then: ; preds = %for.body
234234
235235if.end: ; preds = %for.body
236236; CHECK-SPIRV: Label
237- %1 = load i32 , i32* %i , align 4
238- store i32 %1 , i32* %x , align 4
237+ %1 = load i32 , ptr %i , align 4
238+ store i32 %1 , ptr %x , align 4
239239 br label %for.cond
240240
241241for.cond: ; preds = %if.end, %if.then
242242; CHECK-SPIRV: Label [[#CONTINUE]]
243- %2 = load i32 , i32* %i , align 4
243+ %2 = load i32 , ptr %i , align 4
244244 %dec = add nsw i32 %2 , -1
245- store i32 %dec , i32* %i , align 4
245+ store i32 %dec , ptr %i , align 4
246246 %cmp = icmp sgt i32 %2 , 0
247247; CHECK-SPIRV: BranchConditional [[#]] [[#MERGEBLOCK]] [[#HEADER]]
248248; CHECK-LLVM: br i1 %cmp, label %for.end, label %for.body, !llvm.loop ![[#UNROLLENABLE2:]]
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