Fix outdated comment.

pratikashar · igcbot · commit d5bef0c991c4 · 2022-02-15T09:08:29.000+01:00
diff --git a/IGC/Compiler/CISACodeGen/CISABuilder.cpp b/IGC/Compiler/CISACodeGen/CISABuilder.cpp
@@ -7419,7 +7419,10 @@ namespace IGC
 
     LSC_ADDR_TYPE CEncoder::getLSCAddrType(const ResourceDescriptor* resource)
     {
-        return getLSCAddrType(resource->m_surfaceType);
+        if (resource->m_isThreadArg)
+            return LSC_ADDR_TYPE_ARG;
+        else
+            return getLSCAddrType(resource->m_surfaceType);
     }
 
     LSC_ADDR_TYPE CEncoder::getLSCAddrType(e_predefSurface surfaceType)
@@ -7477,6 +7480,11 @@ namespace IGC
             {
                 globalOffsetOpnd = nullptr;
             }
+            else if (addr.type == LSC_ADDR_TYPE_ARG)
+            {
+                globalOffsetOpnd = nullptr;
+                addr.size = LSC_ADDR_SIZE_32b;
+            }
             else
             {
                 globalOffsetOpnd = GetVISALSCSurfaceOpnd(resource->m_surfaceType, resource->m_resource);
diff --git a/IGC/Compiler/CISACodeGen/CISACodeGen.h b/IGC/Compiler/CISACodeGen/CISACodeGen.h
@@ -167,7 +167,12 @@ namespace IGC
     {
         CVariable* m_resource;
         e_predefSurface m_surfaceType;
-        ResourceDescriptor() : m_resource(nullptr), m_surfaceType(ESURFACE_NORMAL) {}
+        // this flag is set whenever addrspace is set to ADDRESS_SPACE_THREAD_ARG
+        // to access thread arguments. we need to lower such messages
+        // using special addressing mode.
+        bool m_isThreadArg = false;
+        ResourceDescriptor() : m_resource(nullptr), m_surfaceType(ESURFACE_NORMAL),
+            m_isThreadArg(false) {}
     };
 
     struct SamplerDescriptor
diff --git a/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp b/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp
@@ -19610,6 +19610,9 @@ ResourceDescriptor EmitPass::GetResourceVariable(Value* resourcePtr)
 
         bufType = DecodeAS4GFXResource(as, directIndexing, bufferIndex);
 
+        if (as == ADDRESS_SPACE_THREAD_ARG)
+            resource.m_isThreadArg = true;
+
         if (IsBindless(bufType) || !directIndexing)
         {
             if (isa<IntToPtrInst>(resourcePtr))
diff --git a/IGC/Compiler/CISACodeGen/helper.cpp b/IGC/Compiler/CISACodeGen/helper.cpp
@@ -79,7 +79,7 @@ namespace IGC
         }
         else if (bufType == STATELESS_A32)
         {
-            return ADDRESS_SPACE_A32;
+            return ADDRESS_SPACE_THREAD_ARG;
         }
         else if (auto *CI = dyn_cast<ConstantInt>(&bufIdx))
         {
@@ -110,7 +110,7 @@ namespace IGC
         {
             return SLM;
         }
-        else if (addrSpace == ADDRESS_SPACE_A32)
+        else if (addrSpace == ADDRESS_SPACE_THREAD_ARG)
         {
             return STATELESS_A32;
         }
@@ -207,7 +207,7 @@ namespace IGC
             return SLM;
         case ADDRESS_SPACE_GLOBAL:
             return STATELESS;
-        case ADDRESS_SPACE_A32:
+        case ADDRESS_SPACE_THREAD_ARG:
             return STATELESS_A32;
         default:
             break;
diff --git a/IGC/Compiler/CodeGenContext.cpp b/IGC/Compiler/CodeGenContext.cpp
@@ -974,7 +974,7 @@ namespace IGC
                 getModule()->getDataLayout().getPointerSizeInBits(AS);
             break;
         case ADDRESS_SPACE_LOCAL:
-        case ADDRESS_SPACE_A32:
+        case ADDRESS_SPACE_THREAD_ARG:
             pointerSizeInRegister = 32;
             break;
         case ADDRESS_SPACE_PRIVATE:
diff --git a/IGC/Compiler/CodeGenPublicEnums.h b/IGC/Compiler/CodeGenPublicEnums.h
@@ -115,7 +115,7 @@ namespace IGC
         ADDRESS_SPACE_CONSTANT = 2,
         ADDRESS_SPACE_LOCAL = 3,
         ADDRESS_SPACE_GENERIC = 4,
-        ADDRESS_SPACE_A32 = 5,
+        ADDRESS_SPACE_THREAD_ARG = 5,
 
         ADDRESS_SPACE_GLOBAL_OR_PRIVATE = 20,
 
diff --git a/IGC/Compiler/Optimizer/OpenCLPasses/WIFuncs/WIFuncResolution.cpp b/IGC/Compiler/Optimizer/OpenCLPasses/WIFuncs/WIFuncResolution.cpp
@@ -333,7 +333,7 @@ llvm::Value* LowerImplicitArgIntrinsics::BuildLoadInst(llvm::CallInst& CI, unsig
     unsigned int AddrSpace = ADDRESS_SPACE_GLOBAL;
     if (m_ctx->platform.isProductChildOf(IGFX_XE_HP_SDV))
     {
-        AddrSpace = ADDRESS_SPACE_A32;
+        AddrSpace = ADDRESS_SPACE_THREAD_ARG;
     }
 
     llvm::Value* LoadedData = nullptr;
diff --git a/visa/BuildIRImpl.cpp b/visa/BuildIRImpl.cpp
@@ -2670,8 +2670,9 @@ G4_SendDescRaw* IR_Builder::createLscMsgDesc(
             // promote the immediate BTI to the descriptor
             exDesc |= surfaceImm << 24;
             surface = nullptr;
-        }
-        else if (
+        } else if (addr.type == LSC_ADDR_TYPE_ARG) {
+            MUST_BE_TRUE(false, "caller should have converted LSC_ADDR_TYPE_ARG to ...BTI");
+        } else if (
             addr.type == LSC_ADDR_TYPE_BSS ||
             addr.type == LSC_ADDR_TYPE_SS)
         {
@@ -2781,7 +2782,7 @@ G4_InstSend *IR_Builder::createLscSendInst(
     if (surface && surface->isSrcRegRegion()) {
         if (emitA0RegDef)
         {
-            // This path is taken when caller hasnt defined a0.2 register for use
+            // This path is taken when caller hasn't defined a0.2 register for use
             // as ext msg descriptor of lsc. Currently, spill module defines a0.2
             // once per BB and reuses it in all spill msgs for that BB. Without this
             // check, each spill/fill msg would get its own computation of a0.2
diff --git a/visa/CISA.l b/visa/CISA.l
@@ -1082,6 +1082,7 @@ flat   {return LSC_AM_FLAT;}
 bti    {return LSC_AM_BTI;}
 ss     {return LSC_AM_SS;}
 bss    {return LSC_AM_BSS;}
+arg    {return LSC_AM_ARG;}
 
 ".none" {
         CISAlval.lsc_fence_op = LSC_FENCE_OP_NONE;
diff --git a/visa/CISA.y b/visa/CISA.y
@@ -593,6 +593,7 @@ std::vector<attr_gen_struct*> AttrOptVar;
 %token                         LSC_AM_BTI
 %token                         LSC_AM_BSS
 %token                         LSC_AM_SS
+%token                         LSC_AM_ARG
 //
 %token <lsc_fence_op>          LSC_FENCE_OP_TYPE
 %token <lsc_scope>             LSC_FENCE_SCOPE
@@ -1132,7 +1133,7 @@ MovInstruction:
     Predicate MOV_OP SatModOpt ExecSize VecDstOperand_A VecSrcOperand_G_I_IMM_A_AO
     {
         pBuilder->CISA_create_mov_instruction(
-            $1, $2, $4.emask, $4.exec_size, $3, 
+            $1, $2, $4.emask, $4.exec_size, $3,
             $5.cisa_gen_opnd, $6.cisa_gen_opnd, CISAlineno);
     }
     |
@@ -2003,6 +2004,7 @@ LscAddrImmScaleOpt:
 LscAddrModelOpt:
     %empty       {$$ = {LSC_ADDR_TYPE_FLAT,nullptr};}
   | LSC_AM_FLAT  {$$ = {LSC_ADDR_TYPE_FLAT,nullptr};}
+  | LSC_AM_ARG   {$$ = {LSC_ADDR_TYPE_ARG,nullptr};}
   | LscRegAddrModel
 
 LscRegAddrModel:
diff --git a/visa/IsaDisassembly.cpp b/visa/IsaDisassembly.cpp
@@ -2683,6 +2683,7 @@ class LscInstFormatter {
         case LSC_ADDR_TYPE_BSS:   ss << "bss"; break;
         case LSC_ADDR_TYPE_SS:    ss << "ss"; break;
         case LSC_ADDR_TYPE_BTI:   ss << "bti"; break;
+        case LSC_ADDR_TYPE_ARG:   ss << "arg"; break;
         default: formatBadEnum(addrType); break;
         }
         switch (addrType) {
diff --git a/visa/IsaVerification.cpp b/visa/IsaVerification.cpp
@@ -3512,6 +3512,7 @@ struct LscInstVerifier {
 
         switch (addrType) {
         case LSC_ADDR_TYPE_FLAT:
+        case LSC_ADDR_TYPE_ARG:
             verify(sfid != LSC_TGM, ".tgm may not use flat address model");
             switch (vo.tag & 0x7) {
             case OPERAND_IMMEDIATE:
diff --git a/visa/Optimizer.cpp b/visa/Optimizer.cpp
@@ -8708,10 +8708,10 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)
         auto getStartAddrInst = [this, &instBuffer, r0, rtail](int subreg)
         {
             // (W) and (1) r127.2<1>:ud r0.0<0;1,0>:ud 0xFFFFFFC0
-            uint32_t GRFMask = 0x3F;
             auto src0 = builder.createSrc(r0->getRegVar(), 0, 0,
                 builder.getRegionScalar(), Type_UD);
-            auto src1 = builder.createImm(~GRFMask, Type_UD);
+            const uint32_t ArgOffsetMask = 0xFFFFFFC0;
+            auto src1 = builder.createImm(ArgOffsetMask, Type_UD);
             auto dst = builder.createDst(rtail->getRegVar(), 0, subreg, 1, Type_UD);
             auto andInst = builder.createBinOp(G4_and, g4::SIMD1,
                 dst, src0, src1, InstOpt_WriteEnable, false);
diff --git a/visa/VISAKernelImpl.cpp b/visa/VISAKernelImpl.cpp
@@ -741,9 +741,10 @@ void VISAKernelImpl::createReservedKeywordSet() {
     // specification
     reservedNames.insert("FILE");
     reservedNames.insert("LOC");
-    reservedNames.insert("flat");
-    reservedNames.insert("bti");
+    reservedNames.insert("arg");
     reservedNames.insert("bss");
+    reservedNames.insert("bti");
+    reservedNames.insert("flat");
     reservedNames.insert("ss");
 }
 
diff --git a/visa/VisaToG4/TranslateSendLdStLsc.cpp b/visa/VisaToG4/TranslateSendLdStLsc.cpp
@@ -43,6 +43,10 @@ static G4_Operand *lscTryPromoteSurfaceImmToExDesc(
                 exDesc |= surfaceImm;
                 surface = nullptr;
             }
+        } else if (addrModel == LSC_ADDR_TYPE_ARG) {
+            MUST_BE_TRUE(false, "caller should have fixed this");
+            exDesc |= 0xFF << 24;
+            surface = nullptr;
         } else {
             // flat address type
             MUST_BE_TRUE(surface->isNullReg() ||
@@ -142,6 +146,34 @@ int IR_Builder::translateLscUntypedInst(
 
     const static uint32_t BYTES_PER_REG = COMMON_ISA_GRF_REG_SIZE;
 
+    if (addrInfo.type == LSC_ADDR_TYPE_ARG) {
+        // Translate argument loads to platform specific logic
+        MUST_BE_TRUE(addrInfo.size == LSC_ADDR_SIZE_32b,
+            "lsc_load... arg[...] must be :a32");
+        //
+        // (W)  and (1) TMP0:ud   r0.0:ud  0xFFFFFFC0:ud
+        // (W)  add (1) TMP1:ud   TMP0:ud  src0Addr:ud
+        // ... load.ugm.a32... bti[255][TMP]
+        G4_Declare *argBase = createTempVar(1, Type_UD, Even_Word);
+        auto andDst = createDst(argBase->getRegVar(), 0, 0, 1, Type_UD);
+        auto andSrc0 = createSrc(getBuiltinR0()->getRegVar(), 0, 0,
+            getRegionScalar(),Type_UD);
+        auto andSrc1 = createImm(0xFFFFFFC0, Type_UD);
+        (void)createBinOp(G4_and, g4::SIMD1,
+            andDst, andSrc0, andSrc1, InstOpt_WriteEnable, true);
+        auto addDst = createDst(src0Addr->getBase(), src0Addr->getRegOff(),
+            src0Addr->getSubRegOff(), 1, Type_UD);
+        auto addSrc0 = createSrc(src0Addr->getBase(), src0Addr->getRegOff(),
+            src0Addr->getSubRegOff(), src0Addr->getRegion(), src0Addr->getType());
+        auto addSrc1 =
+            createSrc(argBase->getRegVar(), 0, 0, getRegionScalar(), Type_UD);
+        (void)createBinOp(G4_add, g4::SIMD1,
+            addDst, addSrc0, addSrc1, InstOpt_WriteEnable, true);
+        //
+        addrInfo.type = LSC_ADDR_TYPE_BTI;
+        surface =  createImm(0xFF, Type_UD);
+    }
+
     // send descriptor
     uint32_t desc = 0;
     uint32_t exDesc = 0;
diff --git a/visa/include/visa_igc_common_header.h b/visa/include/visa_igc_common_header.h
@@ -729,6 +729,9 @@ enum LSC_ADDR_TYPE {
     LSC_ADDR_TYPE_BSS,  // bindless surface state offset
     LSC_ADDR_TYPE_SS,   // surface state offset
     LSC_ADDR_TYPE_BTI,  // binding table interface (legacy)
+    //
+    // Pseudo address types
+    LSC_ADDR_TYPE_ARG,  // built-in surface access to kernel arguments
 };
 
 //

Original file line number	Diff line number	Diff line change
`@@ -7419,7 +7419,10 @@ namespace IGC`
`7419`	`7419`
`7420`	`7420`	`LSC_ADDR_TYPE CEncoder::getLSCAddrType(const ResourceDescriptor* resource)`
`7421`	`7421`	`{`
`7422`		`- return getLSCAddrType(resource->m_surfaceType);`
	`7422`	`+ if (resource->m_isThreadArg)`
	`7423`	`+ return LSC_ADDR_TYPE_ARG;`
	`7424`	`+ else`
	`7425`	`+ return getLSCAddrType(resource->m_surfaceType);`
`7423`	`7426`	`}`
`7424`	`7427`
`7425`	`7428`	`LSC_ADDR_TYPE CEncoder::getLSCAddrType(e_predefSurface surfaceType)`
`@@ -7477,6 +7480,11 @@ namespace IGC`
`7477`	`7480`	`{`
`7478`	`7481`	`globalOffsetOpnd = nullptr;`
`7479`	`7482`	`}`
	`7483`	`+ else if (addr.type == LSC_ADDR_TYPE_ARG)`
	`7484`	`+ {`
	`7485`	`+ globalOffsetOpnd = nullptr;`
	`7486`	`+ addr.size = LSC_ADDR_SIZE_32b;`
	`7487`	`+ }`
`7480`	`7488`	`else`
`7481`	`7489`	`{`
`7482`	`7490`	`globalOffsetOpnd = GetVISALSCSurfaceOpnd(resource->m_surfaceType, resource->m_resource);`
Original file line number	Diff line number	Diff line change
`@@ -19610,6 +19610,9 @@ ResourceDescriptor EmitPass::GetResourceVariable(Value* resourcePtr)`
`19610`	`19610`
`19611`	`19611`	`bufType = DecodeAS4GFXResource(as, directIndexing, bufferIndex);`
`19612`	`19612`
	`19613`	`+ if (as == ADDRESS_SPACE_THREAD_ARG)`
	`19614`	`+ resource.m_isThreadArg = true;`
	`19615`	`+`
`19613`	`19616`	`if (IsBindless(bufType) \|\| !directIndexing)`
`19614`	`19617`	`{`
`19615`	`19618`	`if (isa<IntToPtrInst>(resourcePtr))`
Original file line number	Diff line number	Diff line change
`@@ -79,7 +79,7 @@ namespace IGC`
`79`	`79`	`}`
`80`	`80`	`else if (bufType == STATELESS_A32)`
`81`	`81`	`{`
`82`		`- return ADDRESS_SPACE_A32;`
	`82`	`+ return ADDRESS_SPACE_THREAD_ARG;`
`83`	`83`	`}`
`84`	`84`	`else if (auto *CI = dyn_cast<ConstantInt>(&bufIdx))`
`85`	`85`	`{`
`@@ -110,7 +110,7 @@ namespace IGC`
`110`	`110`	`{`
`111`	`111`	`return SLM;`
`112`	`112`	`}`
`113`		`- else if (addrSpace == ADDRESS_SPACE_A32)`
	`113`	`+ else if (addrSpace == ADDRESS_SPACE_THREAD_ARG)`
`114`	`114`	`{`
`115`	`115`	`return STATELESS_A32;`
`116`	`116`	`}`
`@@ -207,7 +207,7 @@ namespace IGC`
`207`	`207`	`return SLM;`
`208`	`208`	`case ADDRESS_SPACE_GLOBAL:`
`209`	`209`	`return STATELESS;`
`210`		`- case ADDRESS_SPACE_A32:`
	`210`	`+ case ADDRESS_SPACE_THREAD_ARG:`
`211`	`211`	`return STATELESS_A32;`
`212`	`212`	`default:`
`213`	`213`	`break;`
Original file line number	Diff line number	Diff line change
`@@ -333,7 +333,7 @@ llvm::Value* LowerImplicitArgIntrinsics::BuildLoadInst(llvm::CallInst& CI, unsig`
`333`	`333`	`unsigned int AddrSpace = ADDRESS_SPACE_GLOBAL;`
`334`	`334`	`if (m_ctx->platform.isProductChildOf(IGFX_XE_HP_SDV))`
`335`	`335`	`{`
`336`		`- AddrSpace = ADDRESS_SPACE_A32;`
	`336`	`+ AddrSpace = ADDRESS_SPACE_THREAD_ARG;`
`337`	`337`	`}`
`338`	`338`
`339`	`339`	`llvm::Value* LoadedData = nullptr;`