Remove VME register category

VME variables are not longer used in Finalizer and can be removed

Author: skachkov-intel

IGC/VectorCompiler/include/vc/GenXOpts/Utils/KernelInfo.h

@@ -177,15 +177,13 @@ class KernelMetadata {
     return ArgTypeDescs[Idx];
   }
 
-  enum { AK_NORMAL, AK_SAMPLER, AK_SURFACE, AK_VME };
+  enum { AK_NORMAL, AK_SAMPLER, AK_SURFACE };
   unsigned getArgCategory(unsigned Idx) const {
     switch (getArgKind(Idx) & 7) {
     case AK_SAMPLER:
       return RegCategory::SAMPLER;
     case AK_SURFACE:
       return RegCategory::SURFACE;
-    case AK_VME:
-      return RegCategory::VME;
     default:
       return RegCategory::GENERAL;
     }

IGC/VectorCompiler/include/vc/GenXOpts/Utils/RegCategory.h

@@ -23,7 +23,6 @@ struct RegCategory {
     PREDICATE,
     SAMPLER,
     SURFACE,
-    VME,
     NUMREALCATEGORIES,
     EM,
     RM,

IGC/VectorCompiler/lib/GenXCodeGen/GenXCategory.cpp

@@ -782,8 +782,6 @@ static unsigned intrinsicCategoryToRegCategory(unsigned ICat)
       return RegCategory::SAMPLER;
     case GenXIntrinsicInfo::SURFACE:
       return RegCategory::SURFACE;
-    case GenXIntrinsicInfo::VME:
-      return RegCategory::VME;
     default:
       return RegCategory::GENERAL;
   }

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -1722,7 +1722,6 @@ GenXKernelBuilder::createDestination(Value *Dest, genx::Signedness Signed,
                                  DONTCARESIGNED, Mod, true /*isDest*/);
     } else {
       IGC_ASSERT(Reg->Category == RegCategory::SURFACE ||
-             Reg->Category == RegCategory::VME ||
              Reg->Category == RegCategory::SAMPLER);
 
       return createState(Reg, 0 /*Offset*/, true /*IsDst*/);
@@ -1755,8 +1754,7 @@ GenXKernelBuilder::createDestination(Value *Dest, genx::Signedness Signed,
     *SignedRes = RegAlloc->getSigned(Reg);
 
   if (Reg && (Reg->Category == RegCategory::SAMPLER ||
-              Reg->Category == RegCategory::SURFACE ||
-              Reg->Category == RegCategory::VME)) {
+              Reg->Category == RegCategory::SURFACE)) {
     IGC_ASSERT(R.ElementBytes);
     return createState(Reg, R.Offset / R.ElementBytes, true /*IsDest*/);
   } else {
@@ -2086,8 +2084,7 @@ VISA_VectorOpnd *GenXKernelBuilder::createSource(Value *V, Signedness Signed,
     Register *Reg = getRegForValueAndSaveAlias(KernFunc, V, Signed);
     IGC_ASSERT(Reg->Category == RegCategory::GENERAL ||
            Reg->Category == RegCategory::SURFACE ||
-           Reg->Category == RegCategory::SAMPLER ||
-           Reg->Category == RegCategory::VME);
+           Reg->Category == RegCategory::SAMPLER);
     // Write the vISA general operand.
     Region R(V);
     if (Offset)
@@ -2614,8 +2611,7 @@ void GenXKernelBuilder::buildLoneOperand(Instruction *Inst, genx::BaleInfo BI,
       DstReg = getRegForValueAndSaveAlias(KernFunc, Inst, DONTCARESIGNED);
     }
     if (DstReg && (DstReg->Category == RegCategory::SURFACE ||
-                   DstReg->Category == RegCategory::SAMPLER ||
-                   DstReg->Category == RegCategory::VME)) {
+                   DstReg->Category == RegCategory::SAMPLER)) {
       Opcode = ISA_MOVS;
     }
   }
@@ -3215,10 +3211,6 @@ void GenXKernelBuilder::buildVariables() {
       Reg->SetVar(Kernel, Decl);
     } break;
 
-    case RegCategory::VME:
-      report_fatal_error("VME variable is no longer supported");
-      break;
-
     default:
       report_fatal_error("Unknown category for register");
       break;

IGC/VectorCompiler/lib/GenXCodeGen/GenXIntrinsics.cpp

@@ -126,8 +126,9 @@ unsigned GenXIntrinsicInfo::getTrailingNullZoneStart(CallInst *CI) {
  */
 unsigned GenXIntrinsicInfo::getExecSizeAllowedBits() {
   for (const auto *p = Args; *p; p++) {
-    if (!(*p & GENERAL)) {
-      switch (*p & CATMASK) {
+    ArgInfo AI(*p);
+    if (!AI.isGeneral()) {
+      switch (AI.getCategory()) {
       case EXECSIZE:
         return 0x3f;
       case EXECSIZE_GE2:

IGC/VectorCompiler/lib/GenXCodeGen/GenXIntrinsics.h

@@ -116,31 +116,32 @@ class GenXIntrinsicInfo {
     Z_PREDICATE = PREDICATE | PREDICATE_ZEROED,
     SAMPLER =               GENX_ITR_CATVAL(0x25), // sampler operand
     SURFACE =               GENX_ITR_CATVAL(0x26), // surface operand
-    VME =                   GENX_ITR_CATVAL(0x27), // vme operand
     // byte height of media 2D block, inferred from the width operand
     // pointed at and the size of the return type or final operand type
-    MEDIAHEIGHT =           GENX_ITR_CATVAL(0x28),
+    MEDIAHEIGHT =           GENX_ITR_CATVAL(0x27),
     // predication control field from explicit predicate arg
-    PREDICATION =           GENX_ITR_CATVAL(0x29),
+    PREDICATION =           GENX_ITR_CATVAL(0x28),
     // chmask field in load/sample, with exec size bit
-    SAMPLECHMASK =          GENX_ITR_CATVAL(0x2a),
+    SAMPLECHMASK =          GENX_ITR_CATVAL(0x29),
     // does not appear in the vISA output, but needs to be two address
     // coalesced with result
-    TWOADDR =               GENX_ITR_CATVAL(0x2b),
-    CONSTVI1ASI32 =         GENX_ITR_CATVAL(0x2c), // constant vXi1 written as i32 (used in setp)
-    RAW =                   GENX_ITR_CATVAL(0x2d), // raw operand or result,
+    TWOADDR =               GENX_ITR_CATVAL(0x2a),
+    CONSTVI1ASI32 =         GENX_ITR_CATVAL(0x2b), // constant vXi1 written as i32 (used in setp)
+    RAW =                   GENX_ITR_CATVAL(0x2c), // raw operand or result,
       // Raw descriptor flags, 3 bits used
       RAW_UNSIGNED =        GENX_ITR_FLAGVAL(0),   // raw operand/result must be unsigned
       RAW_SIGNED =          GENX_ITR_FLAGVAL(1),   // raw operand/result must be signed
       RAW_NULLALLOWED =     GENX_ITR_FLAGVAL(2),   // raw operand or result can be null (V0)
     URAW =                  RAW | RAW_UNSIGNED,
     SRAW =                  RAW | RAW_SIGNED,
-    EXECSIZE_NOMASK =       GENX_ITR_CATVAL(0x2e), // execution size with NoMask
+    EXECSIZE_NOMASK =       GENX_ITR_CATVAL(0x2d), // execution size with NoMask
 
     // A general operand
-    GENERAL =               GENX_ITR_CATVAL(0x30),
+    GENERAL =               GENX_ITR_CATVAL(0x2e),
     // A general operand with compile-time signedness choosing
     GENERAL_CTSIGN =        GENERAL,
+    // A predefined surface operand
+    PREDEF_SURFACE =        GENX_ITR_CATVAL(0x2f),
     // Modifiers for destination or source, 7 bits used
     UNSIGNED =              GENX_ITR_FLAGVAL(0), // int type forced to unsigned
     SIGNED =                GENX_ITR_FLAGVAL(1), // int type forced to signed
@@ -170,7 +171,6 @@ class GenXIntrinsicInfo {
     MODIFIER_LOGIC =        GENX_ITR_FLAGENUM(8, 2), // src modifier: logic
     MODIFIER_EXTONLY =      GENX_ITR_FLAGENUM(8, 3), // src modifier: extend only
     DIRECTONLY =            GENX_ITR_FLAGVAL(10), // indirect region not allowed
-    PREDEF_SURFACE =        GENX_ITR_CATVAL(0x31), // predefined surface operand
   };
   struct ArgInfo {
     unsigned Info;
@@ -267,7 +267,6 @@ class GenXIntrinsicInfo {
         case PREDICATION:
         case SURFACE:
         case SAMPLER:
-        case VME:
           return true;
         default: break;
       }

IGC/VectorCompiler/lib/GenXCodeGen/GenXLiveness.cpp

@@ -1782,11 +1782,10 @@ void LiveRange::print(raw_ostream &OS) const
     case RegCategory::GENERAL: Cat = "general"; break;
     case RegCategory::ADDRESS: Cat = "address"; break;
     case RegCategory::PREDICATE: Cat = "predicate"; break;
-    case RegCategory::EM: Cat = "em"; break;
-    case RegCategory::RM: Cat = "rm"; break;
     case RegCategory::SAMPLER: Cat = "sampler"; break;
     case RegCategory::SURFACE: Cat = "surface"; break;
-    case RegCategory::VME: Cat = "vme"; break;
+    case RegCategory::EM: Cat = "em"; break;
+    case RegCategory::RM: Cat = "rm"; break;
   }
   OS << "{" << Cat << ",align" << (1U << LogAlignment);
   if (Offset)

IGC/VectorCompiler/lib/GenXCodeGen/GenXVisa.h

@@ -115,8 +115,7 @@ namespace llvm {
            VISA_MAX_ADDRESS_REGS = 4096,
            VISA_MAX_PREDICATE_REGS = 4096,
            VISA_MAX_SAMPLER_REGS = 32 - 1,
-           VISA_MAX_SURFACE_REGS = 256,
-           VISA_MAX_VME_REGS = 16 };
+           VISA_MAX_SURFACE_REGS = 256 };
 
     enum { VISA_WIDTH_GENERAL_REG = 32 };
 

IGC/VectorCompiler/lib/GenXCodeGen/GenXVisaRegAlloc.cpp

@@ -155,8 +155,6 @@ bool GenXVisaRegAlloc::runOnFunctionGroup(FunctionGroup &FGArg)
     report_fatal_error("Too many vISA sampler registers");
   if (CurrentRegId[RegCategory::SURFACE] > VISA_MAX_SURFACE_REGS)
     report_fatal_error("Too many vISA surface registers");
-  if (CurrentRegId[RegCategory::VME] > VISA_MAX_VME_REGS)
-    report_fatal_error("Too many vISA VME registers");
   return false;
 }
 
@@ -951,7 +949,6 @@ void GenXVisaRegAlloc::Reg::print(raw_ostream &OS) const
     case RegCategory::PREDICATE: OS << "p"; break;
     case RegCategory::SAMPLER: OS << "s"; break;
     case RegCategory::SURFACE: OS << "t"; break;
-    case RegCategory::VME: OS << "vme"; break;
     default: OS << "?"; break;
   }
   OS << Num;

IGC/VectorCompiler/lib/GenXCodeGen/GenXVisaRegAlloc.h

@@ -100,7 +100,7 @@ namespace llvm {
           Reg* AliasTo = nullptr)
           : Category(Category), Num(Num), AliasTo(AliasTo), Signed(Signed),
             Ty(Ty), Alignment(LogAlignment) {
-        static const char* Prefix[] = { "ERR", "V", "A", "P", "S", "T", "VME" };
+        static const char* Prefix[] = { "ERR", "V", "A", "P", "S", "T" };
         IGC_ASSERT(Category);
         IGC_ASSERT(Category < genx::RegCategory::NUMREALCATEGORIES);
         NameStr = Prefix[Category] + std::to_string(Num);