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bcheng0127igcbot
bcheng0127
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igcbot
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address register update
address register update
1 parent 011f75e commit 5270b5d

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4 files changed

+82
-18
lines changed

4 files changed

+82
-18
lines changed

‎visa/GraphColor.cpp

Lines changed: 34 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12557,28 +12557,57 @@ unsigned GraphColor::edgeWeightARF(const LiveRange *lr1, const LiveRange *lr2) {
1255712557
unsigned lr1_nreg = lr1->getNumRegNeeded();
1255812558
unsigned lr2_nreg = lr2->getNumRegNeeded();
1255912559

12560+
if (lr1_align < lr2_align) {
12561+
G4_SubReg_Align tmp_align = lr1_align;
12562+
unsigned tmp_nreg = lr1_nreg;
12563+
lr1_align = lr2_align;
12564+
lr2_align = tmp_align;
12565+
lr1_nreg = lr2_nreg;
12566+
lr2_nreg = tmp_nreg;
12567+
}
12568+
1256012569
if (lr1_align == Any) {
12570+
// Any vs
1256112571
return lr1_nreg + lr2_nreg - 1;
1256212572
} else if (lr1_align == Four_Word && lr2_align == Any) {
12573+
// 4 vs Any
1256312574
return lr1_nreg + lr2_nreg + 3 - (lr1_nreg + lr2_nreg) % 4;
1256412575
} else if (lr1_align == Four_Word && lr2_align == Four_Word) {
12576+
// 4 vs 4
1256512577
return lr1_nreg + lr2_nreg - 1 + (4 - lr1_nreg % 4) % 4 +
1256612578
(4 - lr2_nreg % 4) % 4;
12567-
} else if (lr1_align == Four_Word && lr2_align == Eight_Word) {
12568-
if (((8 - lr2_nreg % 8) % 8) >= 4)
12569-
return lr2_nreg + lr1_nreg - 1 + (8 - lr2_nreg % 8) % 8 - 4;
12570-
return lr1_nreg + lr2_nreg - 1 + (8 - lr2_nreg % 8) % 8 +
12571-
(4 - lr1_nreg % 4) % 4;
1257212579
} else if (lr1_align == Eight_Word && lr2_align == Any) {
12580+
// 8 vs Any
1257312581
return lr1_nreg + lr2_nreg + 7 - (lr1_nreg + lr2_nreg) % 8;
1257412582
} else if (lr1_align == Eight_Word && lr2_align == Four_Word) {
12583+
// 8 vs 4
1257512584
if (((8 - lr1_nreg % 8) % 8) >= 4)
1257612585
return lr1_nreg + lr2_nreg - 1 + (8 - lr1_nreg % 8) % 8 - 4;
1257712586
return lr1_nreg + lr2_nreg - 1 + (8 - lr1_nreg % 8) % 8 +
1257812587
(4 - lr2_nreg % 4) % 4;
1257912588
} else if (lr1_align == Eight_Word && lr2_align == Eight_Word) {
12589+
// 8 vs 8
1258012590
return lr1_nreg + lr2_nreg - 1 + (8 - lr1_nreg % 8) % 8 +
1258112591
(8 - lr2_nreg % 8) % 8;
12592+
} else if (lr1_align == Sixteen_Word && lr2_align == Any) {
12593+
// 16 vs Any
12594+
return lr1_nreg + lr2_nreg + 15 - (lr1_nreg + lr2_nreg) % 16;
12595+
} else if (lr1_align == Sixteen_Word && lr2_align == Four_Word) {
12596+
// 16 vs 4
12597+
if (((16 - lr1_nreg % 16) % 16) >= 4)
12598+
return lr1_nreg + lr2_nreg - 1 + (16 - lr1_nreg % 16) % 16 - 4;
12599+
return lr1_nreg + lr2_nreg - 1 + (16 - lr1_nreg % 16) % 16 +
12600+
(4 - lr2_nreg % 4) % 4;
12601+
} else if (lr1_align == Sixteen_Word && lr2_align == Eight_Word) {
12602+
// 16 vs 8
12603+
if (((16 - lr1_nreg % 16) % 16) >= 8)
12604+
return lr1_nreg + lr2_nreg - 1 + (16 - lr1_nreg % 16) % 16 - 8;
12605+
return lr1_nreg + lr2_nreg - 1 + (16 - lr1_nreg % 16) % 16 +
12606+
(8 - lr2_nreg % 8) % 8;
12607+
} else if (lr1_align == Sixteen_Word && lr2_align == Sixteen_Word) {
12608+
// 16 vs 16
12609+
return lr1_nreg + lr2_nreg - 1 + (16 - lr1_nreg % 16) % 16 +
12610+
(16 - lr2_nreg % 16) % 16;
1258212611
} else {
1258312612
vISA_ASSERT_UNREACHABLE(
1258412613
"Found unsupported subRegAlignment in address register allocation!");

‎visa/Optimizer.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5726,6 +5726,9 @@ void Optimizer::preRA_HWWorkaround() {
57265726
cloneSampleInst();
57275727

57285728
insertIEEEExceptionTrap();
5729+
5730+
if (builder.supportNativeSIMD32())
5731+
fixDirectAddrBoundOnDst();
57295732
}
57305733

57315734
//

‎visa/PrologEpilog.cpp

Lines changed: 24 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1105,13 +1105,30 @@ void Optimizer::resetA0() {
11051105
G4_BB *bb = *kernel.fg.begin();
11061106
auto insertIt = std::find_if(
11071107
bb->begin(), bb->end(), [](G4_INST *inst) { return !inst->isLabel(); });
1108-
bb->insertBefore(
1109-
insertIt,
1110-
builder.createMov(G4_ExecSize(builder.getNumAddrRegisters()),
1111-
builder.createDst(builder.phyregpool.getAddrReg(), 0,
1112-
0, 1, Type_UW),
1113-
builder.createImm(0, Type_UW), InstOpt_WriteEnable,
1114-
false));
1108+
if (builder.supportNativeSIMD32()) {
1109+
bb->insertBefore(
1110+
insertIt,
1111+
builder.createMov(G4_ExecSize(16),
1112+
builder.createDst(builder.phyregpool.getAddrReg(),
1113+
0, 0, 1, Type_UW),
1114+
builder.createImm(0, Type_UW), InstOpt_WriteEnable,
1115+
false));
1116+
bb->insertBefore(
1117+
insertIt,
1118+
builder.createMov(G4_ExecSize(16),
1119+
builder.createDst(builder.phyregpool.getAddrReg(),
1120+
0, 16, 1, Type_UW),
1121+
builder.createImm(0, Type_UW), InstOpt_WriteEnable,
1122+
false));
1123+
} else {
1124+
bb->insertBefore(
1125+
insertIt,
1126+
builder.createMov(G4_ExecSize(builder.getNumAddrRegisters()),
1127+
builder.createDst(builder.phyregpool.getAddrReg(),
1128+
0, 0, 1, Type_UW),
1129+
builder.createImm(0, Type_UW), InstOpt_WriteEnable,
1130+
false));
1131+
}
11151132
}
11161133
}
11171134

‎visa/SWWA.cpp

Lines changed: 21 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4001,9 +4001,6 @@ void Optimizer::HWWorkaround() {
40014001
if (builder.hasFPU0ReadSuppressionIssue()) {
40024002
fixReadSuppressioninFPU0();
40034003
}
4004-
4005-
if (builder.supportNativeSIMD32())
4006-
fixDirectAddrBoundOnDst();
40074004
}
40084005

40094006
// When destination is an address register the following apply:
@@ -4016,9 +4013,27 @@ void Optimizer::fixDirectAddrBoundOnDst() {
40164013
for (auto bb : kernel.fg) {
40174014
for (auto it = bb->begin(), ie = bb->end(); it != ie; ++it) {
40184015
G4_INST *inst = *it;
4019-
if (inst->getExecSize() == g4::SIMD32 && inst->getDst() &&
4020-
inst->getDst()->isDirectA0())
4021-
hwConf.evenlySplitInst(it, bb, /*checkOverlap*/ false);
4016+
G4_DstRegRegion *dst = inst->getDst();
4017+
if (dst && !dst->isNullReg() &&
4018+
dst->getRegAccess() == Direct && dst->getTopDcl() &&
4019+
dst->getTopDcl()->getRegVar()->isAddress()) {
4020+
G4_Declare *dcl = dst->getTopDcl();
4021+
if (dcl->getTotalElems() > Eight_Word) {
4022+
if (dcl->getSubRegAlign() < Sixteen_Word)
4023+
dcl->setSubRegAlign(Sixteen_Word);
4024+
} else if (dcl->getTotalElems() > Four_Word) {
4025+
if (dcl->getSubRegAlign() < Eight_Word)
4026+
dcl->setSubRegAlign(Eight_Word);
4027+
} else if (dcl->getTotalElems() > Any) {
4028+
if (dcl->getSubRegAlign() < Four_Word)
4029+
dcl->setSubRegAlign(Four_Word);
4030+
}
4031+
if (((dst->getSubRegOff() + inst->getExecSize() - 1) / 16 !=
4032+
(dst->getSubRegOff() / 16)) ||
4033+
inst->getExecSize() == g4::SIMD32) {
4034+
hwConf.evenlySplitInst(it, bb, /*checkOverlap*/ false);
4035+
}
4036+
}
40224037
}
40234038
}
40244039
}

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