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[RISCV] Use i32 in more RV32 only patterns. NFC
This reduces RISCVGenDAGISel.inc by about 750 bytes.
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+43
-40
lines changed

5 files changed

+43
-40
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1367,9 +1367,8 @@ def : InstAlias<".insn_s $opcode, $funct3, $rs2, (${rs1})",
13671367

13681368
class PatGpr<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
13691369
: Pat<(vt (OpNode (vt GPR:$rs1))), (Inst GPR:$rs1)>;
1370-
class PatGprGpr<SDPatternOperator OpNode, RVInst Inst, ValueType vt1 = XLenVT,
1371-
ValueType vt2 = XLenVT>
1372-
: Pat<(vt1 (OpNode (vt1 GPR:$rs1), (vt2 GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2)>;
1370+
class PatGprGpr<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
1371+
: Pat<(vt (OpNode (vt GPR:$rs1), (vt GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2)>;
13731372

13741373
class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType,
13751374
ValueType vt = XLenVT>
@@ -1973,8 +1972,9 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
19731972

19741973
/// Loads
19751974

1976-
class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
1977-
: Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12_lo:$imm12))),
1975+
class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT,
1976+
ValueType PtrVT = XLenVT>
1977+
: Pat<(vt (LoadOp (AddrRegImm (PtrVT GPRMem:$rs1), simm12_lo:$imm12))),
19781978
(Inst GPRMem:$rs1, simm12_lo:$imm12)>;
19791979

19801980
def : LdPat<sextloadi8, LB>;
@@ -1988,8 +1988,8 @@ def : LdPat<zextloadi16, LHU>;
19881988
/// Stores
19891989

19901990
class StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
1991-
ValueType vt>
1992-
: Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPRMem:$rs1),
1991+
ValueType vt, ValueType PtrVT = XLenVT>
1992+
: Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (PtrVT GPRMem:$rs1),
19931993
simm12_lo:$imm12)),
19941994
(Inst StTy:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
19951995

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -544,8 +544,8 @@ def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12_l
544544
} // Predicates = [HasStdExtZdinx, IsRV32]
545545

546546
let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in {
547-
def : LdPat<load, LD_RV32, f64>;
548-
def : StPat<store, SD_RV32, GPRPair, f64>;
547+
def : LdPat<load, LD_RV32, f64, i32>;
548+
def : StPat<store, SD_RV32, GPRPair, f64, i32>;
549549
}
550550

551551
let Predicates = [HasStdExtD, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -669,19 +669,19 @@ let Predicates = [HasVendorXCValu, IsRV32] in {
669669
// Patterns for load & store operations
670670
//===----------------------------------------------------------------------===//
671671
class CVLdrrPat<PatFrag LoadOp, RVInst Inst>
672-
: Pat<(XLenVT (LoadOp CVrr:$regreg)),
672+
: Pat<(i32 (LoadOp CVrr:$regreg)),
673673
(Inst CVrr:$regreg)>;
674674

675675
class CVStriPat<PatFrag StoreOp, RVInst Inst>
676-
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12_lo:$imm12),
676+
: Pat<(StoreOp (i32 GPR:$rs2), GPR:$rs1, simm12_lo:$imm12),
677677
(Inst GPR:$rs2, GPR:$rs1, simm12_lo:$imm12)>;
678678

679679
class CVStrriPat<PatFrag StoreOp, RVInst Inst>
680-
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, GPR:$rs3),
680+
: Pat<(StoreOp (i32 GPR:$rs2), GPR:$rs1, GPR:$rs3),
681681
(Inst GPR:$rs2, GPR:$rs1, GPR:$rs3)>;
682682

683683
class CVStrrPat<PatFrag StoreOp, RVInst Inst>
684-
: Pat<(StoreOp (XLenVT GPR:$rs2), CVrr:$regreg),
684+
: Pat<(StoreOp (i32 GPR:$rs2), CVrr:$regreg),
685685
(Inst GPR:$rs2, CVrr:$regreg)>;
686686

687687
let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
@@ -725,17 +725,17 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
725725
(CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm),
726726
(CV_LO5 cv_uimm10:$imm))>;
727727

728-
def : PatGpr<cttz, CV_FF1>;
729-
def : PatGpr<ctlz, CV_FL1>;
728+
def : PatGpr<cttz, CV_FF1, i32>;
729+
def : PatGpr<ctlz, CV_FL1, i32>;
730730
def : PatGpr<int_riscv_cv_bitmanip_clb, CV_CLB>;
731-
def : PatGpr<ctpop, CV_CNT>;
731+
def : PatGpr<ctpop, CV_CNT, i32>;
732732

733-
def : PatGprGpr<rotr, CV_ROR>;
733+
def : PatGprGpr<rotr, CV_ROR, i32>;
734734

735735
def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts,
736736
cv_tuimm2:$radix),
737737
(CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
738-
def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
738+
def : Pat<(bitreverse (i32 GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
739739
}
740740

741741
class PatCoreVAluGpr<string intr, string asm> :
@@ -760,18 +760,18 @@ multiclass PatCoreVAluGprGprImm<Intrinsic intr> {
760760
}
761761

762762
let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
763-
def : PatGpr<abs, CV_ABS>;
764-
def : PatGprGpr<setle, CV_SLE>;
765-
def : PatGprGpr<setule, CV_SLEU>;
766-
def : PatGprGpr<smin, CV_MIN>;
767-
def : PatGprGpr<umin, CV_MINU>;
768-
def : PatGprGpr<smax, CV_MAX>;
769-
def : PatGprGpr<umax, CV_MAXU>;
770-
771-
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
772-
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
773-
def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;
774-
def : Pat<(and (XLenVT GPR:$rs1), 0xff), (CV_EXTBZ GPR:$rs1)>;
763+
def : PatGpr<abs, CV_ABS, i32>;
764+
def : PatGprGpr<setle, CV_SLE, i32>;
765+
def : PatGprGpr<setule, CV_SLEU, i32>;
766+
def : PatGprGpr<smin, CV_MIN, i32>;
767+
def : PatGprGpr<umin, CV_MINU, i32>;
768+
def : PatGprGpr<smax, CV_MAX, i32>;
769+
def : PatGprGpr<umax, CV_MAXU, i32>;
770+
771+
def : Pat<(sext_inreg (i32 GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
772+
def : Pat<(sext_inreg (i32 GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
773+
def : Pat<(and (i32 GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;
774+
def : Pat<(and (i32 GPR:$rs1), 0xff), (CV_EXTBZ GPR:$rs1)>;
775775

776776
defm CLIP : PatCoreVAluGprImm<int_riscv_cv_alu_clip>;
777777
defm CLIPU : PatCoreVAluGprImm<int_riscv_cv_alu_clipu>;
@@ -790,9 +790,9 @@ let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
790790
//===----------------------------------------------------------------------===//
791791

792792
let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
793-
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
793+
def : Pat<(riscv_brcc (i32 GPR:$rs1), simm5:$imm5, SETEQ, bb:$imm12),
794794
(CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
795-
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
795+
def : Pat<(riscv_brcc (i32 GPR:$rs1), simm5:$imm5, SETNE, bb:$imm12),
796796
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
797797

798798
defm CC_SImm5_CV : SelectCC_GPR_riirr<GPR, simm5>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1648,10 +1648,10 @@ def : Pat<(qc_setwmi (i32 GPR:$rs3), GPR:$rs1, tuimm5nonzero:$uimm5, tuimm7_lsb0
16481648
} // Predicates = [HasVendorXqcilsm, IsRV32]
16491649

16501650
let Predicates = [HasVendorXqcili, IsRV32] in {
1651-
def: Pat<(qc_e_li tglobaladdr:$A), (QC_E_LI bare_simm32:$A)>;
1652-
def: Pat<(qc_e_li tblockaddress:$A), (QC_E_LI bare_simm32:$A)>;
1653-
def: Pat<(qc_e_li tjumptable:$A), (QC_E_LI bare_simm32:$A)>;
1654-
def: Pat<(qc_e_li tconstpool:$A), (QC_E_LI bare_simm32:$A)>;
1651+
def: Pat<(i32 (qc_e_li tglobaladdr:$A)), (QC_E_LI bare_simm32:$A)>;
1652+
def: Pat<(i32 (qc_e_li tblockaddress:$A)), (QC_E_LI bare_simm32:$A)>;
1653+
def: Pat<(i32 (qc_e_li tjumptable:$A)), (QC_E_LI bare_simm32:$A)>;
1654+
def: Pat<(i32 (qc_e_li tconstpool:$A)), (QC_E_LI bare_simm32:$A)>;
16551655
} // Predicates = [HasVendorXqcili, IsRV32]
16561656

16571657
//===----------------------------------------------------------------------===/i

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -607,13 +607,16 @@ def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs
607607
let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in {
608608
/// Float conversion operations
609609
// f64 -> f16, f16 -> f64
610-
def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_H_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>;
611-
def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_IN32X FPR16INX:$rs1, FRM_RNE)>;
610+
def : Pat<(any_fpround FPR64IN32X:$rs1),
611+
(FCVT_H_D_IN32X FPR64IN32X:$rs1, (i32 FRM_DYN))>;
612+
def : Pat<(any_fpextend FPR16INX:$rs1),
613+
(FCVT_D_H_IN32X FPR16INX:$rs1, (i32 FRM_RNE))>;
612614

613615
/// Float arithmetic operations
614616
def : Pat<(fcopysign FPR16INX:$rs1, FPR64IN32X:$rs2),
615-
(FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, 0b111))>;
616-
def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2), (FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2, FRM_RNE))>;
617+
(FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, (i32 FRM_DYN)))>;
618+
def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2),
619+
(FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2, (i32 FRM_RNE)))>;
617620
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32]
618621

619622
let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] in {

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