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#include "tusb_option.h"
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- #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2 ) || (CFG_TUSB_MCU == OPT_MCU_ESP32S3 )) && TUSB_OPT_DEVICE_ENABLED )
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+ #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2 ) || (CFG_TUSB_MCU == OPT_MCU_ESP32S3 )) && CFG_TUD_ENABLED )
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// Espressif
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- #include "driver/periph_ctrl.h"
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#include "freertos/xtensa_api.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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- #include "driver/gpio.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/usb_periph.h"
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+ #include "soc/periph_defs.h" // for interrupt source
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#include "device/dcd.h"
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@@ -60,6 +59,7 @@ typedef struct {
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uint16_t queued_len ;
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uint16_t max_size ;
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bool short_packet ;
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+ uint8_t interval ;
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} xfer_ctl_t ;
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static const char * TAG = "TUSB:DCD" ;
@@ -284,6 +284,14 @@ void dcd_disconnect(uint8_t rhport)
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USB0 .dctl |= USB_SFTDISCON_M ;
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}
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+ void dcd_sof_enable (uint8_t rhport , bool en )
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+ {
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+ (void ) rhport ;
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+ (void ) en ;
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+
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+ // TODO implement later
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+ }
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+
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/*------------------------------------------------------------------*/
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/* DCD Endpoint port
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*------------------------------------------------------------------*/
@@ -303,6 +311,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
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xfer_ctl_t * xfer = XFER_CTL_BASE (epnum , dir );
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xfer -> max_size = tu_edpt_packet_size (desc_edpt );
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+ xfer -> interval = desc_edpt -> bInterval ;
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if (dir == TUSB_DIR_OUT ) {
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out_ep [epnum ].doepctl &= ~(USB_D_EPTYPE0_M | USB_D_MPS0_M );
@@ -423,6 +432,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
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USB0 .in_ep_reg [epnum ].dieptsiz = (num_packets << USB_D_PKTCNT0_S ) | total_bytes ;
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USB0 .in_ep_reg [epnum ].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M ; // Enable | CNAK
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+ // For ISO endpoint with interval=1 set correct DATA0/DATA1 bit for next frame
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+ if ((USB0 .in_ep_reg [epnum ].diepctl & USB_D_EPTYPE0_M ) == (1 << USB_D_EPTYPE1_S ) && xfer -> interval == 1 ) {
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+ // Take odd/even bit from frame counter.
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+ uint32_t const odd_frame_now = (USB0 .dsts & (1u << USB_SOFFN_S ));
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+ USB0 .in_ep_reg [epnum ].diepctl |= (odd_frame_now ? USB_DI_SETD0PID1 : USB_DI_SETD1PID1 );
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+ }
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+
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// Enable fifo empty interrupt only if there are something to put in the fifo.
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if (total_bytes != 0 ) {
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USB0 .dtknqr4_fifoemptymsk |= (1 << epnum );
@@ -431,6 +447,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
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// Each complete packet for OUT xfers triggers XFRC.
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USB0 .out_ep_reg [epnum ].doeptsiz |= USB_PKTCNT0_M | ((xfer -> max_size & USB_XFERSIZE0_V ) << USB_XFERSIZE0_S );
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USB0 .out_ep_reg [epnum ].doepctl |= USB_EPENA0_M | USB_CNAK0_M ;
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+
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+ // For ISO endpoint with interval=1 set correct DATA0/DATA1 bit for next frame
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+ if ((USB0 .out_ep_reg [epnum ].doepctl & USB_D_EPTYPE0_M ) == (1 << USB_D_EPTYPE1_S ) && xfer -> interval == 1 ) {
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+ // Take odd/even bit from frame counter.
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+ uint32_t const odd_frame_now = (USB0 .dsts & (1u << USB_SOFFN_S ));
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+ USB0 .out_ep_reg [epnum ].doepctl |= (odd_frame_now ? USB_DO_SETD0PID1 : USB_DO_SETD1PID1 );
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+ }
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}
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return true;
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}
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