From 4d7acc42c09e0f340400807113b616334aa1076d Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Aug 2022 16:05:27 -0700 Subject: [PATCH 1/4] Revert "Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant (#70171)" This reverts commit 24f5de4bb10976dfb391e9b6affe5481f55a2d00. --- src/coreclr/jit/codegenarmarch.cpp | 2 +- src/coreclr/jit/lsra.cpp | 7 ------- src/coreclr/jit/lsraxarch.cpp | 1 - 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index 536797eaba9593..f2e7cb212d44f6 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -144,7 +144,7 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode) if (treeNode->IsReuseRegVal()) { // For now, this is only used for constant nodes. - assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL, GT_CNS_VEC)); + assert((treeNode->OperGet() == GT_CNS_INT) || (treeNode->OperGet() == GT_CNS_DBL)); JITDUMP(" TreeNode is marked ReuseReg\n"); return; } diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index 144d5f3ab17753..41e517a5517553 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -2706,7 +2706,6 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo } break; } - case GT_CNS_DBL: { // For floating point constants, the values must be identical, not simply compare @@ -2718,12 +2717,6 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo } break; } - - case GT_CNS_VEC: - { - return GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon()); - } - default: break; } diff --git a/src/coreclr/jit/lsraxarch.cpp b/src/coreclr/jit/lsraxarch.cpp index 9fdfe585c68e8e..1e9b33392e5951 100644 --- a/src/coreclr/jit/lsraxarch.cpp +++ b/src/coreclr/jit/lsraxarch.cpp @@ -147,7 +147,6 @@ int LinearScan::BuildNode(GenTree* tree) case GT_CNS_INT: case GT_CNS_LNG: case GT_CNS_DBL: - case GT_CNS_VEC: { srcCount = 0; assert(dstCount == 1); From 5cd2c38c57540544c772f0a7e4b1d493253aa813 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Aug 2022 23:01:34 -0700 Subject: [PATCH 2/4] Revert "Revert "Ensure that GT_CNS_VEC is handled in LinearScan::isMatchingConstant (#70171)"" This reverts commit 984120f0cde0d26f9768112296e68164cfe76c8e. --- src/coreclr/jit/codegenarmarch.cpp | 2 +- src/coreclr/jit/lsra.cpp | 7 +++++++ src/coreclr/jit/lsraxarch.cpp | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index f2e7cb212d44f6..536797eaba9593 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -144,7 +144,7 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode) if (treeNode->IsReuseRegVal()) { // For now, this is only used for constant nodes. - assert((treeNode->OperGet() == GT_CNS_INT) || (treeNode->OperGet() == GT_CNS_DBL)); + assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL, GT_CNS_VEC)); JITDUMP(" TreeNode is marked ReuseReg\n"); return; } diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index 41e517a5517553..144d5f3ab17753 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -2706,6 +2706,7 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo } break; } + case GT_CNS_DBL: { // For floating point constants, the values must be identical, not simply compare @@ -2717,6 +2718,12 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo } break; } + + case GT_CNS_VEC: + { + return GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon()); + } + default: break; } diff --git a/src/coreclr/jit/lsraxarch.cpp b/src/coreclr/jit/lsraxarch.cpp index 1e9b33392e5951..9fdfe585c68e8e 100644 --- a/src/coreclr/jit/lsraxarch.cpp +++ b/src/coreclr/jit/lsraxarch.cpp @@ -147,6 +147,7 @@ int LinearScan::BuildNode(GenTree* tree) case GT_CNS_INT: case GT_CNS_LNG: case GT_CNS_DBL: + case GT_CNS_VEC: { srcCount = 0; assert(dstCount == 1); From 5cc59cf575b0b968cbb288df12c903102a7d8aa7 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Aug 2022 23:14:32 -0700 Subject: [PATCH 3/4] Add partial save check --- src/coreclr/jit/lsra.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index 144d5f3ab17753..f7b97ecd62487e 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -2721,7 +2721,11 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo case GT_CNS_VEC: { - return GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon()); + return +#if FEATURE_PARTIAL_SIMD_CALLEE_SAVE + !Compiler::varTypeNeedsPartialCalleeSave(physRegRecord->registerType) && +#endif + GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon()); } default: From 6490cd0f996cfe316107a72f38d11b618945947f Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Aug 2022 23:46:26 -0700 Subject: [PATCH 4/4] Use the correct register type --- src/coreclr/jit/lsra.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index f7b97ecd62487e..4417858838d548 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -2723,7 +2723,7 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo { return #if FEATURE_PARTIAL_SIMD_CALLEE_SAVE - !Compiler::varTypeNeedsPartialCalleeSave(physRegRecord->registerType) && + !Compiler::varTypeNeedsPartialCalleeSave(physRegRecord->assignedInterval->registerType) && #endif GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon()); }