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khushal1996khushal1996
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Run formatting
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3 files changed

+44
-18
lines changed

3 files changed

+44
-18
lines changed

‎src/coreclr/jit/emitxarch.cpp‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2909,7 +2909,9 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co
29092909
if (sizePrefix == 0)
29102910
{
29112911
// no simd prefix for EVEX2 - AVX10.2 and above
2912-
assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || emitComp->compIsaSupportedDebugOnly(InstructionSet_AVXVNNIINT8) || emitComp->compIsaSupportedDebugOnly(InstructionSet_AVXVNNIINT16));
2912+
assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) ||
2913+
emitComp->compIsaSupportedDebugOnly(InstructionSet_AVXVNNIINT8) ||
2914+
emitComp->compIsaSupportedDebugOnly(InstructionSet_AVXVNNIINT16));
29132915
}
29142916
else if (isPrefix(sizePrefix))
29152917
{
@@ -10001,7 +10003,8 @@ void emitter::emitIns_SIMD_R_R_R_A(instruction ins,
1000110003
GenTreeIndir* indir,
1000210004
insOpts instOptions)
1000310005
{
10004-
assert(IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) || IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins));
10006+
assert(IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) ||
10007+
IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins));
1000510008
assert(UseSimdEncoding());
1000610009

1000710010
// Ensure we aren't overwriting op2
@@ -10034,7 +10037,8 @@ void emitter::emitIns_SIMD_R_R_R_C(instruction ins,
1003410037
int offs,
1003510038
insOpts instOptions)
1003610039
{
10037-
assert(IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) || IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins));
10040+
assert(IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) ||
10041+
IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins));
1003810042
assert(UseSimdEncoding());
1003910043

1004010044
// Ensure we aren't overwriting op2
@@ -10065,7 +10069,8 @@ void emitter::emitIns_SIMD_R_R_R_R(instruction ins,
1006510069
regNumber op3Reg,
1006610070
insOpts instOptions)
1006710071
{
10068-
if (IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) || IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins))
10072+
if (IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) ||
10073+
IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins))
1006910074
{
1007010075
assert(UseSimdEncoding());
1007110076

@@ -10152,7 +10157,8 @@ void emitter::emitIns_SIMD_R_R_R_S(instruction ins,
1015210157
int offs,
1015310158
insOpts instOptions)
1015410159
{
10155-
assert(IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) || IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins));
10160+
assert(IsFMAInstruction(ins) || IsPermuteVar2xInstruction(ins) || IsAVXVNNIInstruction(ins) ||
10161+
IsAVXVNNIINT8Instruction(ins) || IsAVXVNNIINT16Instruction(ins));
1015610162
assert(UseSimdEncoding());
1015710163

1015810164
// Ensure we aren't overwriting op2

‎src/coreclr/jit/hwintrinsic.cpp‎

Lines changed: 32 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2239,9 +2239,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
22392239
{
22402240
var_types op2Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
22412241
var_types op3Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
2242-
assert((op2Type == TYP_BYTE && (op3Type == TYP_UBYTE || op3Type == TYP_BYTE)) || (op2Type == TYP_UBYTE && op3Type == TYP_UBYTE));
2243-
intrinsic = (op2Type == TYP_UBYTE) ? NI_EVEX_MultiplyWideningAndAddByteByte : ((op3Type == TYP_UBYTE) ? NI_EVEX_MultiplyWideningAndAddSByteByte : NI_EVEX_MultiplyWideningAndAddSByteSByte);
2244-
retNode = gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
2242+
assert((op2Type == TYP_BYTE && (op3Type == TYP_UBYTE || op3Type == TYP_BYTE)) ||
2243+
(op2Type == TYP_UBYTE && op3Type == TYP_UBYTE));
2244+
intrinsic = (op2Type == TYP_UBYTE)
2245+
? NI_EVEX_MultiplyWideningAndAddByteByte
2246+
: ((op3Type == TYP_UBYTE) ? NI_EVEX_MultiplyWideningAndAddSByteByte
2247+
: NI_EVEX_MultiplyWideningAndAddSByteSByte);
2248+
retNode =
2249+
gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
22452250
break;
22462251
}
22472252

@@ -2250,9 +2255,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
22502255
{
22512256
var_types op2Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
22522257
var_types op3Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
2253-
assert((op2Type == TYP_BYTE && (op3Type == TYP_UBYTE || op3Type == TYP_BYTE)) || (op2Type == TYP_UBYTE && op3Type == TYP_UBYTE));
2254-
intrinsic = (op2Type == TYP_UBYTE) ? NI_EVEX_MultiplyWideningAndAddByteByteSaturate : ((op3Type == TYP_UBYTE) ? NI_EVEX_MultiplyWideningAndAddSByteByteSaturate : NI_EVEX_MultiplyWideningAndAddSByteSByteSaturate);
2255-
retNode = gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
2258+
assert((op2Type == TYP_BYTE && (op3Type == TYP_UBYTE || op3Type == TYP_BYTE)) ||
2259+
(op2Type == TYP_UBYTE && op3Type == TYP_UBYTE));
2260+
intrinsic = (op2Type == TYP_UBYTE)
2261+
? NI_EVEX_MultiplyWideningAndAddByteByteSaturate
2262+
: ((op3Type == TYP_UBYTE) ? NI_EVEX_MultiplyWideningAndAddSByteByteSaturate
2263+
: NI_EVEX_MultiplyWideningAndAddSByteSByteSaturate);
2264+
retNode =
2265+
gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
22562266
break;
22572267
}
22582268

@@ -2261,9 +2271,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
22612271
{
22622272
var_types op2Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
22632273
var_types op3Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
2264-
assert((op2Type == TYP_USHORT && (op3Type == TYP_USHORT || op3Type == TYP_SHORT)) || (op2Type == TYP_SHORT && op3Type == TYP_USHORT));
2265-
intrinsic = (op2Type == TYP_SHORT) ? NI_EVEX_MultiplyWideningAndAddInt16UInt16 : ((op3Type == TYP_USHORT) ? NI_EVEX_MultiplyWideningAndAddUInt16UInt16 : NI_EVEX_MultiplyWideningAndAddUInt16Int16);
2266-
retNode = gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
2274+
assert((op2Type == TYP_USHORT && (op3Type == TYP_USHORT || op3Type == TYP_SHORT)) ||
2275+
(op2Type == TYP_SHORT && op3Type == TYP_USHORT));
2276+
intrinsic = (op2Type == TYP_SHORT)
2277+
? NI_EVEX_MultiplyWideningAndAddInt16UInt16
2278+
: ((op3Type == TYP_USHORT) ? NI_EVEX_MultiplyWideningAndAddUInt16UInt16
2279+
: NI_EVEX_MultiplyWideningAndAddUInt16Int16);
2280+
retNode =
2281+
gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
22672282
break;
22682283
}
22692284

@@ -2272,9 +2287,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
22722287
{
22732288
var_types op2Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
22742289
var_types op3Type = JitType2PreciseVarType(getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
2275-
assert((op2Type == TYP_USHORT && (op3Type == TYP_USHORT || op3Type == TYP_SHORT)) || (op2Type == TYP_SHORT && op3Type == TYP_USHORT));
2276-
intrinsic = (op2Type == TYP_SHORT) ? NI_EVEX_MultiplyWideningAndAddInt16UInt16Saturate : ((op3Type == TYP_USHORT) ? NI_EVEX_MultiplyWideningAndAddUInt16UInt16Saturate : NI_EVEX_MultiplyWideningAndAddUInt16Int16Saturate);
2277-
retNode = gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
2290+
assert((op2Type == TYP_USHORT && (op3Type == TYP_USHORT || op3Type == TYP_SHORT)) ||
2291+
(op2Type == TYP_SHORT && op3Type == TYP_USHORT));
2292+
intrinsic = (op2Type == TYP_SHORT)
2293+
? NI_EVEX_MultiplyWideningAndAddInt16UInt16Saturate
2294+
: ((op3Type == TYP_USHORT) ? NI_EVEX_MultiplyWideningAndAddUInt16UInt16Saturate
2295+
: NI_EVEX_MultiplyWideningAndAddUInt16Int16Saturate);
2296+
retNode =
2297+
gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
22782298
break;
22792299
}
22802300

‎src/coreclr/jit/hwintrinsicxarch.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ static CORINFO_InstructionSet X64VersionOfIsa(CORINFO_InstructionSet isa)
5959
case InstructionSet_AVXVNNIINT8:
6060
return InstructionSet_AVXVNNIINT8_X64;
6161
case InstructionSet_AVXVNNIINT16:
62-
return InstructionSet_AVXVNNIINT16_X64;
62+
return InstructionSet_AVXVNNIINT16_X64;
6363
case InstructionSet_AES:
6464
return InstructionSet_AES_X64;
6565
case InstructionSet_BMI1:

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