"Load/StoreWithPush" -> "Load/StoreFullSlot"

The load variant in codegen now has double purpose.

Author: SingleAccretion

src/coreclr/jit/codegenxarch.cpp

@@ -7959,19 +7959,19 @@ void CodeGen::genPutArgStkFieldList(GenTreePutArgStk* putArgStk)
             }
         }
 
-        bool canStoreWithPush = fieldIsSlot;
-        bool canLoadWithPush  = genIsValidIntReg(argReg);
+        bool canStoreFullSlot = fieldIsSlot;
+        bool canLoadFullSlot  = genIsValidIntReg(argReg);
         if (argReg == REG_NA)
         {
             assert((genTypeSize(fieldNode) <= TARGET_POINTER_SIZE));
             assert(genTypeSize(genActualType(fieldNode)) == genTypeSize(genActualType(fieldType)));
 
             // We can widen local loads if the excess only affects padding bits.
-            canLoadWithPush = (genTypeSize(fieldNode) == TARGET_POINTER_SIZE) || fieldNode->isUsedFromSpillTemp() ||
+            canLoadFullSlot = (genTypeSize(fieldNode) == TARGET_POINTER_SIZE) || fieldNode->isUsedFromSpillTemp() ||
                               (fieldNode->OperIsLocalRead() && (genTypeSize(fieldNode) >= genTypeSize(fieldType)));
         }
 
-        if (canStoreWithPush && canLoadWithPush)
+        if (canStoreFullSlot && canLoadFullSlot)
         {
             assert(m_pushStkArg);
             assert(genTypeSize(fieldNode) <= TARGET_POINTER_SIZE);
@@ -7998,8 +7998,8 @@ void CodeGen::genPutArgStkFieldList(GenTreePutArgStk* putArgStk)
                 else
                 {
                     // Use the smaller "mov" instruction in case we do not need a sign/zero-extending load.
-                    instruction loadIns  = canLoadWithPush ? INS_mov : ins_Load(fieldNode->TypeGet());
-                    emitAttr    loadSize = canLoadWithPush ? EA_PTRSIZE : emitTypeSize(fieldNode);
+                    instruction loadIns  = canLoadFullSlot ? INS_mov : ins_Load(fieldNode->TypeGet());
+                    emitAttr    loadSize = canLoadFullSlot ? EA_PTRSIZE : emitTypeSize(fieldNode);
                     inst_RV_TT(loadIns, loadSize, intTmpReg, fieldNode);
                 }
 

src/coreclr/jit/lsraxarch.cpp

@@ -1512,18 +1512,18 @@ int LinearScan::BuildPutArgStk(GenTreePutArgStk* putArgStk)
 
                 // We can treat as a slot any field that is stored at a slot boundary, where the previous
                 // field is not in the same slot. (Note that we store the fields in reverse order.)
-                const bool fieldIsSlot      = ((fieldOffset % 4) == 0) && ((prevOffset - fieldOffset) >= 4);
-                const bool canStoreWithPush = fieldIsSlot;
-                const bool canLoadWithPush  = (genTypeSize(fieldNode) == TARGET_POINTER_SIZE) ||
+                const bool canStoreFullSlot = ((fieldOffset % 4) == 0) && ((prevOffset - fieldOffset) >= 4);
+                const bool canLoadFullSlot =
+                    (genTypeSize(fieldNode) == TARGET_POINTER_SIZE) ||
                     (fieldNode->OperIsLocalRead() && (genTypeSize(fieldNode) >= genTypeSize(fieldType)));
 
-                if ((!canStoreWithPush || !canLoadWithPush) && (intTemp == nullptr))
+                if ((!canStoreFullSlot || !canLoadFullSlot) && (intTemp == nullptr))
                 {
                     intTemp = buildInternalIntRegisterDefForNode(putArgStk);
                 }
 
                 // We can only store bytes using byteable registers.
-                if (!canStoreWithPush && varTypeIsByte(fieldType))
+                if (!canStoreFullSlot && varTypeIsByte(fieldType))
                 {
                     intTemp->registerAssignment &= allByteRegs();
                 }