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Commit cbeadac

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author
Sergey Andreenko
authored
Revert "Delete unused variables in jit. Part 2. (#23481)" (#23488)
This reverts commit 6cb120c.
1 parent 6cb120c commit cbeadac

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12 files changed

+147
-68
lines changed

12 files changed

+147
-68
lines changed

‎src/jit/emitarm64.cpp‎

Lines changed: 31 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2327,9 +2327,9 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
23272327
unsigned R = bmImm.immR;
23282328
unsigned S = bmImm.immS;
23292329

2330-
unsigned elemWidth = 64; // used when N == 1
2330+
unsigned elemWidth = 64; // used when immN == 1
23312331

2332-
if (N == 0) // find the smaller elemWidth when N == 0
2332+
if (bmImm.immN == 0) // find the smaller elemWidth when immN == 0
23332333
{
23342334
// Scan S for the highest bit not set
23352335
elemWidth = 32;
@@ -3393,8 +3393,9 @@ void emitter::emitIns_I(instruction ins, emitAttr attr, ssize_t imm)
33933393

33943394
void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg)
33953395
{
3396-
insFormat fmt = IF_NONE;
3397-
instrDesc* id = nullptr;
3396+
emitAttr size = EA_SIZE(attr);
3397+
insFormat fmt = IF_NONE;
3398+
instrDesc* id = nullptr;
33983399

33993400
/* Figure out the encoding format of the instruction */
34003401
switch (ins)
@@ -3536,6 +3537,7 @@ void emitter::emitIns_R_I(instruction ins, emitAttr attr, regNumber reg, ssize_t
35363537
ssize_t imm8 = 0;
35373538
unsigned pos = 0;
35383539
canEncode = true;
3540+
bool failed = false;
35393541
while (uimm != 0)
35403542
{
35413543
INT64 loByte = uimm & 0xFF;
@@ -6087,7 +6089,8 @@ void emitter::emitIns_R_R_R_R(
60876089

60886090
void emitter::emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insCond cond)
60896091
{
6090-
insFormat fmt = IF_NONE;
6092+
emitAttr size = EA_SIZE(attr);
6093+
insFormat fmt = IF_NONE;
60916094
condFlagsImm cfi;
60926095
cfi.immCFVal = 0;
60936096

@@ -6129,7 +6132,8 @@ void emitter::emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insC
61296132

61306133
void emitter::emitIns_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCond cond)
61316134
{
6132-
insFormat fmt = IF_NONE;
6135+
emitAttr size = EA_SIZE(attr);
6136+
insFormat fmt = IF_NONE;
61336137
condFlagsImm cfi;
61346138
cfi.immCFVal = 0;
61356139

@@ -6174,7 +6178,8 @@ void emitter::emitIns_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, r
61746178
void emitter::emitIns_R_R_R_COND(
61756179
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insCond cond)
61766180
{
6177-
insFormat fmt = IF_NONE;
6181+
emitAttr size = EA_SIZE(attr);
6182+
insFormat fmt = IF_NONE;
61786183
condFlagsImm cfi;
61796184
cfi.immCFVal = 0;
61806185

@@ -6224,7 +6229,8 @@ void emitter::emitIns_R_R_R_COND(
62246229
void emitter::emitIns_R_R_FLAGS_COND(
62256230
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCflags flags, insCond cond)
62266231
{
6227-
insFormat fmt = IF_NONE;
6232+
emitAttr size = EA_SIZE(attr);
6233+
insFormat fmt = IF_NONE;
62286234
condFlagsImm cfi;
62296235
cfi.immCFVal = 0;
62306236

@@ -6268,7 +6274,8 @@ void emitter::emitIns_R_R_FLAGS_COND(
62686274
void emitter::emitIns_R_I_FLAGS_COND(
62696275
instruction ins, emitAttr attr, regNumber reg, int imm, insCflags flags, insCond cond)
62706276
{
6271-
insFormat fmt = IF_NONE;
6277+
emitAttr size = EA_SIZE(attr);
6278+
insFormat fmt = IF_NONE;
62726279
condFlagsImm cfi;
62736280
cfi.immCFVal = 0;
62746281

@@ -6869,6 +6876,7 @@ void emitter::emitIns_R_C(
68696876

68706877
emitAttr size = EA_SIZE(attr);
68716878
insFormat fmt = IF_NONE;
6879+
int disp = 0;
68726880
instrDescJmp* id = emitNewInstrJmp();
68736881

68746882
switch (ins)
@@ -9063,13 +9071,14 @@ unsigned emitter::emitOutputCall(insGroup* ig, BYTE* dst, instrDesc* id, code_t
90639071

90649072
size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
90659073
{
9066-
BYTE* dst = *dp;
9067-
BYTE* odst = dst;
9068-
code_t code = 0;
9069-
size_t sz = emitGetInstrDescSize(id); // TODO-ARM64-Cleanup: on ARM, this is set in each case. why?
9070-
instruction ins = id->idIns();
9071-
insFormat fmt = id->idInsFmt();
9072-
emitAttr size = id->idOpSize();
9074+
BYTE* dst = *dp;
9075+
BYTE* odst = dst;
9076+
code_t code = 0;
9077+
size_t sz = emitGetInstrDescSize(id); // TODO-ARM64-Cleanup: on ARM, this is set in each case. why?
9078+
instruction ins = id->idIns();
9079+
insFormat fmt = id->idInsFmt();
9080+
emitAttr size = id->idOpSize();
9081+
unsigned char callInstrSize = 0;
90739082

90749083
#ifdef DEBUG
90759084
#if DUMP_GC_TABLES
@@ -9081,6 +9090,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
90819090

90829091
assert(REG_NA == (int)REG_NA);
90839092

9093+
VARSET_TP GCvars(VarSetOps::UninitVal());
9094+
90849095
/* What instruction format have we got? */
90859096

90869097
switch (fmt)
@@ -11694,6 +11705,8 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
1169411705

1169511706
regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src)
1169611707
{
11708+
regNumber result = REG_NA;
11709+
1169711710
// dst can only be a reg
1169811711
assert(!dst->isContained());
1169911712

@@ -11724,6 +11737,8 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
1172411737

1172511738
regNumber emitter::emitInsTernary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src1, GenTree* src2)
1172611739
{
11740+
regNumber result = REG_NA;
11741+
1172711742
// dst can only be a reg
1172811743
assert(!dst->isContained());
1172911744

‎src/jit/hwintrinsiccodegenxarch.cpp‎

Lines changed: 41 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -89,10 +89,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
8989

9090
if (genIsTableDrivenHWIntrinsic(intrinsicId, category))
9191
{
92-
GenTree* op1 = node->gtGetOp1();
93-
GenTree* op2 = node->gtGetOp2();
94-
regNumber targetReg = node->gtRegNum;
95-
var_types baseType = node->gtSIMDBaseType;
92+
GenTree* op1 = node->gtGetOp1();
93+
GenTree* op2 = node->gtGetOp2();
94+
regNumber targetReg = node->gtRegNum;
95+
var_types targetType = node->TypeGet();
96+
var_types baseType = node->gtSIMDBaseType;
9697

9798
regNumber op1Reg = REG_NA;
9899
regNumber op2Reg = REG_NA;
@@ -383,10 +384,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
383384
//
384385
void CodeGen::genHWIntrinsic_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr)
385386
{
386-
regNumber targetReg = node->gtRegNum;
387-
GenTree* op1 = node->gtGetOp1();
388-
GenTree* op2 = node->gtGetOp2();
389-
emitter* emit = getEmitter();
387+
var_types targetType = node->TypeGet();
388+
regNumber targetReg = node->gtRegNum;
389+
GenTree* op1 = node->gtGetOp1();
390+
GenTree* op2 = node->gtGetOp2();
391+
emitter* emit = getEmitter();
390392

391393
if (op2 != nullptr)
392394
{
@@ -521,10 +523,11 @@ void CodeGen::genHWIntrinsic_R_RM(GenTreeHWIntrinsic* node, instruction ins, emi
521523
//
522524
void CodeGen::genHWIntrinsic_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, int8_t ival)
523525
{
524-
regNumber targetReg = node->gtRegNum;
525-
GenTree* op1 = node->gtGetOp1();
526-
emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
527-
emitter* emit = getEmitter();
526+
var_types targetType = node->TypeGet();
527+
regNumber targetReg = node->gtRegNum;
528+
GenTree* op1 = node->gtGetOp1();
529+
emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
530+
emitter* emit = getEmitter();
528531

529532
// TODO-XArch-CQ: Commutative operations can have op1 be contained
530533
// TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
@@ -714,11 +717,12 @@ void CodeGen::genHWIntrinsic_R_R_RM(
714717
//
715718
void CodeGen::genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, int8_t ival)
716719
{
717-
regNumber targetReg = node->gtRegNum;
718-
GenTree* op1 = node->gtGetOp1();
719-
GenTree* op2 = node->gtGetOp2();
720-
emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
721-
emitter* emit = getEmitter();
720+
var_types targetType = node->TypeGet();
721+
regNumber targetReg = node->gtRegNum;
722+
GenTree* op1 = node->gtGetOp1();
723+
GenTree* op2 = node->gtGetOp2();
724+
emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
725+
emitter* emit = getEmitter();
722726

723727
// TODO-XArch-CQ: Commutative operations can have op1 be contained
724728
// TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
@@ -869,12 +873,13 @@ void CodeGen::genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins,
869873
//
870874
void CodeGen::genHWIntrinsic_R_R_RM_R(GenTreeHWIntrinsic* node, instruction ins)
871875
{
872-
regNumber targetReg = node->gtRegNum;
873-
GenTree* op1 = node->gtGetOp1();
874-
GenTree* op2 = node->gtGetOp2();
875-
GenTree* op3 = nullptr;
876-
emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
877-
emitter* emit = getEmitter();
876+
var_types targetType = node->TypeGet();
877+
regNumber targetReg = node->gtRegNum;
878+
GenTree* op1 = node->gtGetOp1();
879+
GenTree* op2 = node->gtGetOp2();
880+
GenTree* op3 = nullptr;
881+
emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
882+
emitter* emit = getEmitter();
878883

879884
assert(op1->OperIsList());
880885
assert(op2 == nullptr);
@@ -1151,6 +1156,7 @@ void CodeGen::genHWIntrinsicJumpTableFallback(NamedIntrinsic intrinsi
11511156
BasicBlock* jmpTable[256];
11521157

11531158
unsigned jmpTableBase = emit->emitBBTableDataGenBeg(maxByte, true);
1159+
unsigned jmpTableOffs = 0;
11541160

11551161
// Emit the jump table
11561162
for (unsigned i = 0; i < maxByte; i++)
@@ -1327,10 +1333,16 @@ void CodeGen::genSSEIntrinsic(GenTreeHWIntrinsic* node)
13271333
NamedIntrinsic intrinsicId = node->gtHWIntrinsicId;
13281334
GenTree* op1 = node->gtGetOp1();
13291335
GenTree* op2 = node->gtGetOp2();
1336+
GenTree* op3 = nullptr;
1337+
GenTree* op4 = nullptr;
13301338
regNumber targetReg = node->gtRegNum;
1339+
var_types targetType = node->TypeGet();
13311340
var_types baseType = node->gtSIMDBaseType;
13321341

13331342
regNumber op1Reg = REG_NA;
1343+
regNumber op2Reg = REG_NA;
1344+
regNumber op3Reg = REG_NA;
1345+
regNumber op4Reg = REG_NA;
13341346
emitter* emit = getEmitter();
13351347

13361348
genConsumeHWIntrinsicOperands(node);
@@ -1694,10 +1706,16 @@ void CodeGen::genSSE41Intrinsic(GenTreeHWIntrinsic* node)
16941706
NamedIntrinsic intrinsicId = node->gtHWIntrinsicId;
16951707
GenTree* op1 = node->gtGetOp1();
16961708
GenTree* op2 = node->gtGetOp2();
1709+
GenTree* op3 = nullptr;
1710+
GenTree* op4 = nullptr;
16971711
regNumber targetReg = node->gtRegNum;
1712+
var_types targetType = node->TypeGet();
16981713
var_types baseType = node->gtSIMDBaseType;
16991714

17001715
regNumber op1Reg = REG_NA;
1716+
regNumber op2Reg = REG_NA;
1717+
regNumber op3Reg = REG_NA;
1718+
regNumber op4Reg = REG_NA;
17011719
emitter* emit = getEmitter();
17021720

17031721
genConsumeHWIntrinsicOperands(node);

‎src/jit/lower.cpp‎

Lines changed: 28 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -496,6 +496,8 @@ GenTree* Lowering::LowerSwitch(GenTree* node)
496496
noway_assert(jumpCnt >= 2);
497497

498498
// Spill the argument to the switch node into a local so that it can be used later.
499+
unsigned blockWeight = originalSwitchBB->getBBWeight(comp);
500+
499501
LIR::Use use(switchBBRange, &(node->gtOp.gtOp1), node);
500502
ReplaceWithLclVar(use);
501503

@@ -506,8 +508,9 @@ GenTree* Lowering::LowerSwitch(GenTree* node)
506508
assert(node->gtOper == GT_SWITCH);
507509
GenTree* temp = node->gtOp.gtOp1;
508510
assert(temp->gtOper == GT_LCL_VAR);
509-
unsigned tempLclNum = temp->gtLclVarCommon.gtLclNum;
510-
var_types tempLclType = temp->TypeGet();
511+
unsigned tempLclNum = temp->gtLclVarCommon.gtLclNum;
512+
LclVarDsc* tempVarDsc = comp->lvaTable + tempLclNum;
513+
var_types tempLclType = temp->TypeGet();
511514

512515
BasicBlock* defaultBB = jumpTab[jumpCnt - 1];
513516
BasicBlock* followingBB = originalSwitchBB->bbNext;
@@ -2041,7 +2044,8 @@ void Lowering::LowerFastTailCall(GenTreeCall* call)
20412044
// This should not be a GT_PHI_ARG.
20422045
assert(treeNode->OperGet() != GT_PHI_ARG);
20432046

2044-
GenTreeLclVarCommon* lcl = treeNode->AsLclVarCommon();
2047+
GenTreeLclVarCommon* lcl = treeNode->AsLclVarCommon();
2048+
LclVarDsc* lclVar = &comp->lvaTable[lcl->gtLclNum];
20452049

20462050
// Fast tail calling criteria permits passing of structs of size 1, 2, 4 and 8 as args.
20472051
// It is possible that the callerArgLclNum corresponds to such a struct whose stack slot
@@ -2562,11 +2566,11 @@ GenTree* Lowering::OptimizeConstCompare(GenTree* cmp)
25622566

25632567
#if defined(_TARGET_XARCH_) || defined(_TARGET_ARM64_)
25642568
GenTree* op1 = cmp->gtGetOp1();
2569+
var_types op1Type = op1->TypeGet();
25652570
GenTreeIntCon* op2 = cmp->gtGetOp2()->AsIntCon();
25662571
ssize_t op2Value = op2->IconValue();
25672572

25682573
#ifdef _TARGET_XARCH_
2569-
var_types op1Type = op1->TypeGet();
25702574
if (IsContainableMemoryOp(op1) && varTypeIsSmall(op1Type) && genSmallTypeCanRepresentValue(op1Type, op2Value))
25712575
{
25722576
//
@@ -3837,6 +3841,7 @@ GenTree* Lowering::LowerNonvirtPinvokeCall(GenTreeCall* call)
38373841
// platform. They may be changed in the future such that they preserve all register values.
38383842

38393843
GenTree* result = nullptr;
3844+
void* addr = nullptr;
38403845

38413846
// assert we have seen one of these
38423847
noway_assert(comp->info.compCallUnmanaged != 0);
@@ -4188,6 +4193,8 @@ bool Lowering::AreSourcesPossiblyModifiedLocals(GenTree* addr, GenTree* base, Ge
41884193
{
41894194
assert(addr != nullptr);
41904195

4196+
unsigned markCount = 0;
4197+
41914198
SideEffectSet baseSideEffects;
41924199
if (base != nullptr)
41934200
{
@@ -4335,6 +4342,8 @@ GenTree* Lowering::TryCreateAddrMode(LIR::Use&& use, bool isIndir)
43354342
return addr;
43364343
}
43374344

4345+
GenTree* arrLength = nullptr;
4346+
43384347
JITDUMP("Addressing mode:\n");
43394348
JITDUMP(" Base\n ");
43404349
DISPNODE(base);
@@ -4394,6 +4403,8 @@ GenTree* Lowering::TryCreateAddrMode(LIR::Use&& use, bool isIndir)
43944403
//
43954404
GenTree* Lowering::LowerAdd(GenTree* node)
43964405
{
4406+
GenTree* next = node->gtNext;
4407+
43974408
#ifndef _TARGET_ARMARCH_
43984409
if (varTypeIsIntegralOrI(node))
43994410
{
@@ -4448,6 +4459,7 @@ bool Lowering::LowerUnsignedDivOrMod(GenTreeOp* divMod)
44484459
assert(divMod->OperGet() != GT_UMOD);
44494460
#endif // _TARGET_ARM64_
44504461

4462+
GenTree* next = divMod->gtNext;
44514463
GenTree* dividend = divMod->gtGetOp1();
44524464
GenTree* divisor = divMod->gtGetOp2();
44534465

@@ -4821,6 +4833,9 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
48214833

48224834
// We need to use the dividend node multiple times so its value needs to be
48234835
// computed once and stored in a temp variable.
4836+
4837+
unsigned curBBWeight = comp->compCurBB->getBBWeight(comp);
4838+
48244839
LIR::Use opDividend(BlockRange(), &divMod->gtOp.gtOp1, divMod);
48254840
dividend = ReplaceWithLclVar(opDividend);
48264841

@@ -4897,7 +4912,10 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
48974912
GenTree* Lowering::LowerSignedDivOrMod(GenTree* node)
48984913
{
48994914
assert((node->OperGet() == GT_DIV) || (node->OperGet() == GT_MOD));
4900-
GenTree* next = node->gtNext;
4915+
GenTree* next = node->gtNext;
4916+
GenTree* divMod = node;
4917+
GenTree* dividend = divMod->gtGetOp1();
4918+
GenTree* divisor = divMod->gtGetOp2();
49014919

49024920
if (varTypeIsIntegral(node->TypeGet()))
49034921
{
@@ -5054,8 +5072,9 @@ void Lowering::WidenSIMD12IfNecessary(GenTreeLclVarCommon* node)
50545072
GenTree* Lowering::LowerArrElem(GenTree* node)
50555073
{
50565074
// This will assert if we don't have an ArrElem node
5057-
GenTreeArrElem* arrElem = node->AsArrElem();
5058-
const unsigned char rank = arrElem->gtArrElem.gtArrRank;
5075+
GenTreeArrElem* arrElem = node->AsArrElem();
5076+
const unsigned char rank = arrElem->gtArrElem.gtArrRank;
5077+
const unsigned blockWeight = m_block->getBBWeight(comp);
50595078

50605079
JITDUMP("Lowering ArrElem\n");
50615080
JITDUMP("============\n");
@@ -5074,6 +5093,8 @@ GenTree* Lowering::LowerArrElem(GenTree* node)
50745093
GenTree* arrObjNode = arrElem->gtArrObj;
50755094
assert(arrObjNode->IsLocal());
50765095

5096+
LclVarDsc* const varDsc = &comp->lvaTable[arrElem->gtArrObj->AsLclVarCommon()->gtLclNum];
5097+
50775098
GenTree* insertionPoint = arrElem;
50785099

50795100
// The first ArrOffs node will have 0 for the offset of the previous dimension.

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