Verilog logical (in)equality expression

Author: kroening

src/hw_cbmc_irep_ids.h

@@ -51,6 +51,8 @@ IREP_ID_ONE(ports)
 IREP_ID_ONE(inst)
 IREP_ID_ONE(Verilog)
 IREP_ID_ONE(verilog_assignment_pattern)
+IREP_ID_ONE(verilog_logical_equality)
+IREP_ID_ONE(verilog_logical_inequality)
 IREP_ID_ONE(verilog_explicit_cast)
 IREP_ID_ONE(verilog_size_cast)
 IREP_ID_ONE(verilog_implicit_typecast)

src/verilog/parser.y

@@ -3541,9 +3541,9 @@ expression:
 	| expression TOK_PERCENT expression
 		{ init($$, ID_mod); mto($$, $1); mto($$, $3); }
 	| expression TOK_EQUALEQUAL expression
-		{ init($$, ID_equal); mto($$, $1); mto($$, $3); }
+		{ init($$, ID_verilog_logical_equality); mto($$, $1); mto($$, $3); }
 	| expression TOK_EXCLAMEQUAL expression
-		{ init($$, ID_notequal); mto($$, $1); mto($$, $3); }
+		{ init($$, ID_verilog_logical_inequality); mto($$, $1); mto($$, $3); }
 	| expression TOK_EQUALEQUALEQUAL expression
 		{ init($$, ID_verilog_case_equality); mto($$, $1); mto($$, $3); }
 	| expression TOK_EXCLAMEQUALEQUAL expression