Verilog: extend test for unary minus

This extends the test for unary minus to check that the downwards expression
context passes through this operator.

Author: kroening

regression/verilog/expressions/unary_minus1.sv

@@ -3,4 +3,7 @@ module main;
   // Any arithmetic with x or z returns x.
   initial assert(-32'bz === 32'hxxxx_xxxx);
 
+  // Downwards type propagation passes through unary minus.
+  initial assert(-(1'sb1 + 1'sb1) == 2);
+
 endmodule