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SystemVerilog: event data type
This adds 1800-2017 6.17 event.
1 parent cb19887 commit 20645b2

15 files changed

+130
-14
lines changed
Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
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CORE
2+
event1.sv
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--bound 0
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^EXIT=0$
5+
^SIGNAL=0$
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--
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
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module main;
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// IEEE 1800-2017 6.17
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event done;
5+
event empty = null;
6+
7+
task trigger_done;
8+
-> done;
9+
endtask
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11+
task wait_until_done;
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@ done;
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endtask
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15+
endmodule

src/hw_cbmc_irep_ids.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,8 @@ IREP_ID_ONE(verilog_streaming_concatenation_left_to_right)
106106
IREP_ID_ONE(verilog_streaming_concatenation_right_to_left)
107107
IREP_ID_ONE(verilog_chandle)
108108
IREP_ID_ONE(verilog_null)
109-
IREP_ID_ONE(event)
109+
IREP_ID_ONE(verilog_event)
110+
IREP_ID_ONE(verilog_event_trigger)
110111
IREP_ID_ONE(reg)
111112
IREP_ID_ONE(macromodule)
112113
IREP_ID_ONE(output_register)

src/verilog/expr2verilog.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1208,7 +1208,7 @@ expr2verilogt::resultt expr2verilogt::convert_constant(
12081208
ieee_float.from_expr(tmp);
12091209
return {precedence, ieee_float.to_ansi_c_string()};
12101210
}
1211-
else if(type.id() == ID_verilog_chandle)
1211+
else if(type.id() == ID_verilog_chandle || type.id() == ID_verilog_event)
12121212
{
12131213
if(src.get_value() == ID_NULL)
12141214
{
@@ -1989,6 +1989,8 @@ std::string expr2verilogt::convert(const typet &type)
19891989
}
19901990
else if(type.id() == ID_verilog_chandle)
19911991
return "chandle";
1992+
else if(type.id() == ID_verilog_event)
1993+
return "event";
19921994
else if(type.id() == ID_verilog_genvar)
19931995
return "genvar";
19941996
else if(type.id()==ID_integer)

src/verilog/parser.y

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1482,7 +1482,7 @@ data_type:
14821482
$$ = $2; }
14831483
// | class_type
14841484
| TOK_EVENT
1485-
{ init($$, ID_event); }
1485+
{ init($$, ID_verilog_event); }
14861486
/*
14871487
| ps_covergroup_identifier
14881488
*/
@@ -3382,7 +3382,7 @@ event_control:
33823382

33833383
ored_event_expression:
33843384
event_expression
3385-
{ init($$, ID_event); mto($$, $1); }
3385+
{ init($$, ID_verilog_event); mto($$, $1); }
33863386
| ored_event_expression TOK_OR event_expression
33873387
{ $$=$1; mto($$, $3); }
33883388
| ored_event_expression ',' event_expression
@@ -3857,6 +3857,7 @@ function_subroutine_call: subroutine_call
38573857
;
38583858

38593859
event_trigger: TOK_MINUSGREATER hierarchical_event_identifier ';'
3860+
{ init($$, ID_verilog_event_trigger); mto($$, $2); }
38603861
;
38613862

38623863
// System Verilog standard 1800-2017

src/verilog/verilog_elaborate.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,9 @@ void verilog_typecheckt::collect_symbols(const verilog_statementt &statement)
751751
else if(statement.id() == ID_wait)
752752
{
753753
}
754+
else if(statement.id() == ID_verilog_event_trigger)
755+
{
756+
}
754757
else
755758
DATA_INVARIANT(false, "unexpected statement: " + statement.id_string());
756759
}

src/verilog/verilog_elaborate_type.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -256,6 +256,10 @@ typet verilog_typecheck_exprt::elaborate_type(const typet &src)
256256
result.set(ID_C_identifier, enum_type.identifier());
257257
return result.with_source_location(source_location);
258258
}
259+
else if(src.id() == ID_verilog_event)
260+
{
261+
return src;
262+
}
259263
else if(src.id() == ID_verilog_packed_array)
260264
{
261265
return convert_packed_array_type(to_type_with_subtype(src));

src/verilog/verilog_lowering.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,11 @@ exprt verilog_lowering(exprt expr)
189189
// this is 'null'
190190
return to_verilog_chandle_type(expr.type()).null_expr();
191191
}
192+
else if(expr.type().id() == ID_verilog_event)
193+
{
194+
// this is 'null'
195+
return to_verilog_event_type(expr.type()).null_expr();
196+
}
192197

193198
return expr;
194199
}
@@ -201,6 +206,11 @@ exprt verilog_lowering(exprt expr)
201206
return symbol_exprt{
202207
symbol_expr.get_identifier(), chandle_type.encoding()};
203208
}
209+
else if(expr.type().id() == ID_verilog_event)
210+
{
211+
auto &event_type = to_verilog_event_type(expr.type());
212+
return symbol_exprt{symbol_expr.get_identifier(), event_type.encoding()};
213+
}
204214
else
205215
return expr;
206216
}
@@ -441,6 +451,8 @@ typet verilog_lowering(typet type)
441451
return lower_to_aval_bval(type);
442452
else if(type.id() == ID_verilog_chandle)
443453
return to_verilog_chandle_type(type).encoding();
454+
else if(type.id() == ID_verilog_event)
455+
return to_verilog_event_type(type).encoding();
444456
else
445457
return type;
446458
}

src/verilog/verilog_synthesis.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3185,6 +3185,10 @@ void verilog_synthesist::synth_statement(
31853185
}
31863186
else if(statement.id() == ID_verilog_label_statement)
31873187
synth_statement(to_verilog_label_statement(statement).statement());
3188+
else if(statement.id() == ID_verilog_event_trigger)
3189+
{
3190+
// not synthesized
3191+
}
31883192
else
31893193
{
31903194
throw errort().with_location(statement.source_location())
@@ -3348,8 +3352,6 @@ void verilog_synthesist::synth_assignments(
33483352

33493353
auto lhs = symbol_expr(symbol, curr_or_next);
33503354

3351-
if(lhs.type() != new_value.type())
3352-
throw errort() << lhs.pretty() << "\nVS\n" << new_value.pretty();
33533355
DATA_INVARIANT(
33543356
lhs.type() == new_value.type(), "synth_assignments type consistency");
33553357

src/verilog/verilog_typecheck.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1613,6 +1613,10 @@ void verilog_typecheckt::convert_statement(
16131613
else if(statement.id() == ID_wait)
16141614
{
16151615
}
1616+
else if(statement.id() == ID_verilog_event_trigger)
1617+
{
1618+
convert_expr(to_unary_expr(statement).op());
1619+
}
16161620
else
16171621
{
16181622
throw errort().with_location(statement.source_location())

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