Verilog: KNOWNBUG test for module port with value

Author: kroening

regression/verilog/modules/port_with_value1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+port_with_value1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This yields a syntax error.

regression/verilog/modules/port_with_value1.sv

@@ -0,0 +1,14 @@
+module M1(input [31:0] in1 = 1234, in2 = 4567);
+
+  assert final (in1 == in2);
+
+endmodule
+
+module main;
+  // inputs not connected
+  M1 m1();
+  
+  // in2 connected
+  M1 m2(.in2(1234));
+  
+endmodule