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Thomas RichterVasily Gorbik
Thomas Richter
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Vasily Gorbik
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s390/cpum_cf: Add new extended counters for IBM z15
Add CPU measurement counter facility event description for IBM z15. Signed-off-by: Thomas Richter <[email protected]> Reviewed-by: Sumanth Korikkar <[email protected]> Signed-off-by: Vasily Gorbik <[email protected]>
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‎arch/s390/kernel/perf_cpum_cf_events.c‎

Lines changed: 122 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,6 +238,64 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238238
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239239
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240240

241+
CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
242+
CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
243+
CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
244+
CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
245+
CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
246+
CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
247+
CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
248+
CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
249+
CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
250+
CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
251+
CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
252+
CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
253+
CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
254+
CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
255+
CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
256+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
257+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
258+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
259+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
260+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
261+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
262+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
263+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
264+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
265+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
266+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
267+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
268+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
269+
CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
270+
CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
271+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
272+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
273+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
274+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
275+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
276+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
277+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
278+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
279+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
280+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
281+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
282+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
283+
CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
284+
CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
285+
CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
286+
CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
287+
CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
288+
CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
289+
CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
290+
CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
291+
CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
292+
CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
293+
CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
294+
CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
295+
CPUMF_EVENT_ATTR(cf_z15, DFLT_CCERROR, 0x00109);
296+
CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
297+
CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
298+
241299
static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
242300
CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
243301
CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
@@ -516,6 +574,67 @@ static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
516574
NULL,
517575
};
518576

577+
static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
578+
CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
579+
CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
580+
CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
581+
CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
582+
CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
583+
CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
584+
CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
585+
CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
586+
CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
587+
CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
588+
CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
589+
CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
590+
CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
591+
CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
592+
CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
593+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
594+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
595+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
596+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
597+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
598+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
599+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
600+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
601+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
602+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
603+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
604+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
605+
CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
606+
CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
607+
CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
608+
CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
609+
CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
610+
CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
611+
CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
612+
CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
613+
CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
614+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
615+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
616+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
617+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
618+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
619+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
620+
CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
621+
CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
622+
CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
623+
CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
624+
CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
625+
CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
626+
CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
627+
CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
628+
CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
629+
CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
630+
CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
631+
CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
632+
CPUMF_EVENT_PTR(cf_z15, DFLT_CCERROR),
633+
CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
634+
CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
635+
NULL,
636+
};
637+
519638
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
520639

521640
static struct attribute_group cpumcf_pmu_events_group = {
@@ -624,9 +743,11 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
624743
break;
625744
case 0x3906:
626745
case 0x3907:
746+
model = cpumcf_z14_pmu_event_attr;
747+
break;
627748
case 0x8561:
628749
case 0x8562:
629-
model = cpumcf_z14_pmu_event_attr;
750+
model = cpumcf_z15_pmu_event_attr;
630751
break;
631752
default:
632753
model = none;

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